sys/dev/drm/radeon/radeon_fence.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Dave Airlie
  30  *
  31  * $FreeBSD: head/sys/dev/drm2/radeon/radeon_fence.c 254885 2013-08-25 19:37:15Z dumbbell $
  32  */
  33
  34 #include <drm/drmP.h>
  35 #include "radeon_reg.h"
  36 #include "radeon.h"
  37 #ifdef DUMBBELL_WIP
  38 #include "radeon_trace.h"
  39 #endif /* DUMBBELL_WIP */
  40
  41 /*
  42  * Fences
  43  * Fences mark an event in the GPUs pipeline and are used
  44  * for GPU/CPU synchronization.  When the fence is written,
  45  * it is expected that all buffers associated with that fence
  46  * are no longer in use by the associated ring on the GPU and
  47  * that the the relevant GPU caches have been flushed.  Whether
  48  * we use a scratch register or memory location depends on the asic
  49  * and whether writeback is enabled.
  50  */
  51
  52 /**
  53  * radeon_fence_write - write a fence value
  54  *
  55  * @rdev: radeon_device pointer
  56  * @seq: sequence number to write
  57  * @ring: ring index the fence is associated with
  58  *
  59  * Writes a fence value to memory or a scratch register (all asics).
  60  */
  61 static void radeon_fence_write(struct radeon_device *rdev, u32 seq, int ring)
  62 {
  63         struct radeon_fence_driver *drv = &rdev->fence_drv[ring];
  64         if (likely(rdev->wb.enabled || !drv->scratch_reg)) {
  65                 *drv->cpu_addr = cpu_to_le32(seq);
  66         } else {
  67                 WREG32(drv->scratch_reg, seq);
  68         }
  69 }
  70
  71 /**
  72  * radeon_fence_read - read a fence value
  73  *
  74  * @rdev: radeon_device pointer
  75  * @ring: ring index the fence is associated with
  76  *
  77  * Reads a fence value from memory or a scratch register (all asics).
  78  * Returns the value of the fence read from memory or register.
  79  */
  80 static u32 radeon_fence_read(struct radeon_device *rdev, int ring)
  81 {
  82         struct radeon_fence_driver *drv = &rdev->fence_drv[ring];
  83         u32 seq = 0;
  84
  85         if (likely(rdev->wb.enabled || !drv->scratch_reg)) {
  86                 seq = le32_to_cpu(*drv->cpu_addr);
  87         } else {
  88                 seq = RREG32(drv->scratch_reg);
  89         }
  90         return seq;
  91 }
  92
  93 /**
  94  * radeon_fence_emit - emit a fence on the requested ring
  95  *
  96  * @rdev: radeon_device pointer
  97  * @fence: radeon fence object
  98  * @ring: ring index the fence is associated with
  99  *
 100  * Emits a fence command on the requested ring (all asics).
 101  * Returns 0 on success, -ENOMEM on failure.
 102  */
 103 int radeon_fence_emit(struct radeon_device *rdev,
 104                       struct radeon_fence **fence,
 105                       int ring)
 106 {
 107         /* we are protected by the ring emission mutex */
 108         *fence = kmalloc(sizeof(struct radeon_fence), M_DRM,
 109                          M_WAITOK);
 110         if ((*fence) == NULL) {
 111                 return -ENOMEM;
 112         }
 113         refcount_init(&((*fence)->kref), 1);
 114         (*fence)->rdev = rdev;
 115         (*fence)->seq = ++rdev->fence_drv[ring].sync_seq[ring];
 116         (*fence)->ring = ring;
 117         radeon_fence_ring_emit(rdev, ring, *fence);
 118         return 0;
 119 }
 120
 121 /**
 122  * radeon_fence_process - process a fence
 123  *
 124  * @rdev: radeon_device pointer
 125  * @ring: ring index the fence is associated with
 126  *
 127  * Checks the current fence value and wakes the fence queue
 128  * if the sequence number has increased (all asics).
 129  */
 130 void radeon_fence_process(struct radeon_device *rdev, int ring)
 131 {
 132         uint64_t seq, last_seq, last_emitted;
 133         unsigned count_loop = 0;
 134         bool wake = false;
 135
 136         /* Note there is a scenario here for an infinite loop but it's
 137          * very unlikely to happen. For it to happen, the current polling
 138          * process need to be interrupted by another process and another
 139          * process needs to update the last_seq btw the atomic read and
 140          * xchg of the current process.
 141          *
 142          * More over for this to go in infinite loop there need to be
 143          * continuously new fence signaled ie radeon_fence_read needs
 144          * to return a different value each time for both the currently
 145          * polling process and the other process that xchg the last_seq
 146          * btw atomic read and xchg of the current process. And the
 147          * value the other process set as last seq must be higher than
 148          * the seq value we just read. Which means that current process
 149          * need to be interrupted after radeon_fence_read and before
 150          * atomic xchg.
 151          *
 152          * To be even more safe we count the number of time we loop and
 153          * we bail after 10 loop just accepting the fact that we might
 154          * have temporarly set the last_seq not to the true real last
 155          * seq but to an older one.
 156          */
 157         last_seq = atomic64_read(&rdev->fence_drv[ring].last_seq);
 158         do {
 159                 last_emitted = rdev->fence_drv[ring].sync_seq[ring];
 160                 seq = radeon_fence_read(rdev, ring);
 161                 seq |= last_seq & 0xffffffff00000000LL;
 162                 if (seq < last_seq) {
 163                         seq &= 0xffffffff;
 164                         seq |= last_emitted & 0xffffffff00000000LL;
 165                 }
 166
 167                 if (seq <= last_seq || seq > last_emitted) {
 168                         break;
 169                 }
 170                 /* If we loop over we don't want to return without
 171                  * checking if a fence is signaled as it means that the
 172                  * seq we just read is different from the previous on.
 173                  */
 174                 wake = true;
 175                 last_seq = seq;
 176                 if ((count_loop++) > 10) {
 177                         /* We looped over too many time leave with the
 178                          * fact that we might have set an older fence
 179                          * seq then the current real last seq as signaled
 180                          * by the hw.
 181                          */
 182                         break;
 183                 }
 184         } while (atomic64_xchg(&rdev->fence_drv[ring].last_seq, seq) > seq);
 185
 186         if (wake) {
 187                 rdev->fence_drv[ring].last_activity = jiffies;
 188                 cv_broadcast(&rdev->fence_queue);
 189         }
 190 }
 191
 192 /**
 193  * radeon_fence_destroy - destroy a fence
 194  *
 195  * @kref: fence kref
 196  *
 197  * Frees the fence object (all asics).
 198  */
 199 static void radeon_fence_destroy(struct radeon_fence *fence)
 200 {
 201
 202         drm_free(fence, M_DRM);
 203 }
 204
 205 /**
 206  * radeon_fence_seq_signaled - check if a fence sequeuce number has signaled
 207  *
 208  * @rdev: radeon device pointer
 209  * @seq: sequence number
 210  * @ring: ring index the fence is associated with
 211  *
 212  * Check if the last singled fence sequnce number is >= the requested
 213  * sequence number (all asics).
 214  * Returns true if the fence has signaled (current fence value
 215  * is >= requested value) or false if it has not (current fence
 216  * value is < the requested value.  Helper function for
 217  * radeon_fence_signaled().
 218  */
 219 static bool radeon_fence_seq_signaled(struct radeon_device *rdev,
 220                                       u64 seq, unsigned ring)
 221 {
 222         if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
 223                 return true;
 224         }
 225         /* poll new last sequence at least once */
 226         radeon_fence_process(rdev, ring);
 227         if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
 228                 return true;
 229         }
 230         return false;
 231 }
 232
 233 /**
 234  * radeon_fence_signaled - check if a fence has signaled
 235  *
 236  * @fence: radeon fence object
 237  *
 238  * Check if the requested fence has signaled (all asics).
 239  * Returns true if the fence has signaled or false if it has not.
 240  */
 241 bool radeon_fence_signaled(struct radeon_fence *fence)
 242 {
 243         if (!fence) {
 244                 return true;
 245         }
 246         if (fence->seq == RADEON_FENCE_SIGNALED_SEQ) {
 247                 return true;
 248         }
 249         if (radeon_fence_seq_signaled(fence->rdev, fence->seq, fence->ring)) {
 250                 fence->seq = RADEON_FENCE_SIGNALED_SEQ;
 251                 return true;
 252         }
 253         return false;
 254 }
 255
 256 /**
 257  * radeon_fence_wait_seq - wait for a specific sequence number
 258  *
 259  * @rdev: radeon device pointer
 260  * @target_seq: sequence number we want to wait for
 261  * @ring: ring index the fence is associated with
 262  * @intr: use interruptable sleep
 263  * @lock_ring: whether the ring should be locked or not
 264  *
 265  * Wait for the requested sequence number to be written (all asics).
 266  * @intr selects whether to use interruptable (true) or non-interruptable
 267  * (false) sleep when waiting for the sequence number.  Helper function
 268  * for radeon_fence_wait(), et al.
 269  * Returns 0 if the sequence number has passed, error for all other cases.
 270  * -EDEADLK is returned when a GPU lockup has been detected and the ring is
 271  * marked as not ready so no further jobs get scheduled until a successful
 272  * reset.
 273  */
 274 static int radeon_fence_wait_seq(struct radeon_device *rdev, u64 target_seq,
 275                                  unsigned ring, bool intr, bool lock_ring)
 276 {
 277         unsigned long timeout, last_activity;
 278         uint64_t seq;
 279         unsigned i;
 280         bool signaled, fence_queue_locked;
 281         int r;
 282
 283         while (target_seq > atomic64_read(&rdev->fence_drv[ring].last_seq)) {
 284                 if (!rdev->ring[ring].ready) {
 285                         return -EBUSY;
 286                 }
 287
 288                 timeout = jiffies - RADEON_FENCE_JIFFIES_TIMEOUT;
 289                 if (time_after(rdev->fence_drv[ring].last_activity, timeout)) {
 290                         /* the normal case, timeout is somewhere before last_activity */
 291                         timeout = rdev->fence_drv[ring].last_activity - timeout;
 292                 } else {
 293                         /* either jiffies wrapped around, or no fence was signaled in the last 500ms
 294                          * anyway we will just wait for the minimum amount and then check for a lockup
 295                          */
 296                         timeout = 1;
 297                 }
 298                 seq = atomic64_read(&rdev->fence_drv[ring].last_seq);
 299                 /* Save current last activity valuee, used to check for GPU lockups */
 300                 last_activity = rdev->fence_drv[ring].last_activity;
 301
 302                 radeon_irq_kms_sw_irq_get(rdev, ring);
 303                 fence_queue_locked = false;
 304                 r = 0;
 305                 while (!(signaled = radeon_fence_seq_signaled(rdev,
 306                     target_seq, ring))) {
 307                         if (!fence_queue_locked) {
 308                                 lockmgr(&rdev->fence_queue_mtx, LK_EXCLUSIVE);
 309                                 fence_queue_locked = true;
 310                         }
 311                         if (intr) {
 312                                 r = cv_timedwait_sig(&rdev->fence_queue,
 313                                     &rdev->fence_queue_mtx,
 314                                     timeout);
 315                         } else {
 316                                 r = cv_timedwait(&rdev->fence_queue,
 317                                     &rdev->fence_queue_mtx,
 318                                     timeout);
 319                         }
 320                         if (r != 0) {
 321                                 if (r == EWOULDBLOCK) {
 322                                         signaled =
 323                                             radeon_fence_seq_signaled(
 324                                                 rdev, target_seq, ring);
 325                                 }
 326                                 break;
 327                         }
 328                 }
 329                 if (fence_queue_locked) {
 330                         lockmgr(&rdev->fence_queue_mtx, LK_RELEASE);
 331                 }
 332                 radeon_irq_kms_sw_irq_put(rdev, ring);
 333                 if (unlikely(r == EINTR || r == ERESTART)) {
 334                         return -r;
 335                 }
 336
 337                 if (unlikely(!signaled)) {
 338 #ifndef __FreeBSD__
 339                         /* we were interrupted for some reason and fence
 340                          * isn't signaled yet, resume waiting */
 341                         if (r) {
 342                                 continue;
 343                         }
 344 #endif
 345
 346                         /* check if sequence value has changed since last_activity */
 347                         if (seq != atomic64_read(&rdev->fence_drv[ring].last_seq)) {
 348                                 continue;
 349                         }
 350
 351                         if (lock_ring) {
 352                                 lockmgr(&rdev->ring_lock, LK_EXCLUSIVE);
 353                         }
 354
 355                         /* test if somebody else has already decided that this is a lockup */
 356                         if (last_activity != rdev->fence_drv[ring].last_activity) {
 357                                 if (lock_ring) {
 358                                         lockmgr(&rdev->ring_lock, LK_RELEASE);
 359                                 }
 360                                 continue;
 361                         }
 362
 363                         if (radeon_ring_is_lockup(rdev, ring, &rdev->ring[ring])) {
 364                                 /* good news we believe it's a lockup */
 365                                 dev_warn(rdev->dev, "GPU lockup (waiting for 0x%016jx last fence id 0x%016jx)\n",
 366                                          (uintmax_t)target_seq, (uintmax_t)seq);
 367
 368                                 /* change last activity so nobody else think there is a lockup */
 369                                 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 370                                         rdev->fence_drv[i].last_activity = jiffies;
 371                                 }
 372
 373                                 /* mark the ring as not ready any more */
 374                                 rdev->ring[ring].ready = false;
 375                                 if (lock_ring) {
 376                                         lockmgr(&rdev->ring_lock, LK_RELEASE);
 377                                 }
 378                                 return -EDEADLK;
 379                         }
 380
 381                         if (lock_ring) {
 382                                 lockmgr(&rdev->ring_lock, LK_RELEASE);
 383                         }
 384                 }
 385         }
 386         return 0;
 387 }
 388
 389 /**
 390  * radeon_fence_wait - wait for a fence to signal
 391  *
 392  * @fence: radeon fence object
 393  * @intr: use interruptable sleep
 394  *
 395  * Wait for the requested fence to signal (all asics).
 396  * @intr selects whether to use interruptable (true) or non-interruptable
 397  * (false) sleep when waiting for the fence.
 398  * Returns 0 if the fence has passed, error for all other cases.
 399  */
 400 int radeon_fence_wait(struct radeon_fence *fence, bool intr)
 401 {
 402         int r;
 403
 404         if (fence == NULL) {
 405                 DRM_ERROR("Querying an invalid fence : %p !\n", fence);
 406                 return -EINVAL;
 407         }
 408
 409         r = radeon_fence_wait_seq(fence->rdev, fence->seq,
 410                                   fence->ring, intr, true);
 411         if (r) {
 412                 return r;
 413         }
 414         fence->seq = RADEON_FENCE_SIGNALED_SEQ;
 415         return 0;
 416 }
 417
 418 static bool radeon_fence_any_seq_signaled(struct radeon_device *rdev, u64 *seq)
 419 {
 420         unsigned i;
 421
 422         for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 423                 if (seq[i] && radeon_fence_seq_signaled(rdev, seq[i], i)) {
 424                         return true;
 425                 }
 426         }
 427         return false;
 428 }
 429
 430 /**
 431  * radeon_fence_wait_any_seq - wait for a sequence number on any ring
 432  *
 433  * @rdev: radeon device pointer
 434  * @target_seq: sequence number(s) we want to wait for
 435  * @intr: use interruptable sleep
 436  *
 437  * Wait for the requested sequence number(s) to be written by any ring
 438  * (all asics).  Sequnce number array is indexed by ring id.
 439  * @intr selects whether to use interruptable (true) or non-interruptable
 440  * (false) sleep when waiting for the sequence number.  Helper function
 441  * for radeon_fence_wait_any(), et al.
 442  * Returns 0 if the sequence number has passed, error for all other cases.
 443  */
 444 static int radeon_fence_wait_any_seq(struct radeon_device *rdev,
 445                                      u64 *target_seq, bool intr)
 446 {
 447         unsigned long timeout, last_activity, tmp;
 448         unsigned i, ring = RADEON_NUM_RINGS;
 449         bool signaled, fence_queue_locked;
 450         int r;
 451
 452         for (i = 0, last_activity = 0; i < RADEON_NUM_RINGS; ++i) {
 453                 if (!target_seq[i]) {
 454                         continue;
 455                 }
 456
 457                 /* use the most recent one as indicator */
 458                 if (time_after(rdev->fence_drv[i].last_activity, last_activity)) {
 459                         last_activity = rdev->fence_drv[i].last_activity;
 460                 }
 461
 462                 /* For lockup detection just pick the lowest ring we are
 463                  * actively waiting for
 464                  */
 465                 if (i < ring) {
 466                         ring = i;
 467                 }
 468         }
 469
 470         /* nothing to wait for ? */
 471         if (ring == RADEON_NUM_RINGS) {
 472                 return -ENOENT;
 473         }
 474
 475         while (!radeon_fence_any_seq_signaled(rdev, target_seq)) {
 476                 timeout = jiffies - RADEON_FENCE_JIFFIES_TIMEOUT;
 477                 if (time_after(last_activity, timeout)) {
 478                         /* the normal case, timeout is somewhere before last_activity */
 479                         timeout = last_activity - timeout;
 480                 } else {
 481                         /* either jiffies wrapped around, or no fence was signaled in the last 500ms
 482                          * anyway we will just wait for the minimum amount and then check for a lockup
 483                          */
 484                         timeout = 1;
 485                 }
 486
 487                 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 488                         if (target_seq[i]) {
 489                                 radeon_irq_kms_sw_irq_get(rdev, i);
 490                         }
 491                 }
 492                 fence_queue_locked = false;
 493                 r = 0;
 494                 while (!(signaled = radeon_fence_any_seq_signaled(rdev,
 495                     target_seq))) {
 496                         if (!fence_queue_locked) {
 497                                 lockmgr(&rdev->fence_queue_mtx, LK_EXCLUSIVE);
 498                                 fence_queue_locked = true;
 499                         }
 500                         if (intr) {
 501                                 r = cv_timedwait_sig(&rdev->fence_queue,
 502                                     &rdev->fence_queue_mtx,
 503                                     timeout);
 504                         } else {
 505                                 r = cv_timedwait(&rdev->fence_queue,
 506                                     &rdev->fence_queue_mtx,
 507                                     timeout);
 508                         }
 509                         if (r != 0) {
 510                                 if (r == EWOULDBLOCK) {
 511                                         signaled =
 512                                             radeon_fence_any_seq_signaled(
 513                                                 rdev, target_seq);
 514                                 }
 515                                 break;
 516                         }
 517                 }
 518                 if (fence_queue_locked) {
 519                         lockmgr(&rdev->fence_queue_mtx, LK_RELEASE);
 520                 }
 521                 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 522                         if (target_seq[i]) {
 523                                 radeon_irq_kms_sw_irq_put(rdev, i);
 524                         }
 525                 }
 526                 if (unlikely(r == EINTR || r == ERESTART)) {
 527                         return -r;
 528                 }
 529
 530                 if (unlikely(!signaled)) {
 531 #ifndef __FreeBSD__
 532                         /* we were interrupted for some reason and fence
 533                          * isn't signaled yet, resume waiting */
 534                         if (r) {
 535                                 continue;
 536                         }
 537 #endif
 538
 539                         lockmgr(&rdev->ring_lock, LK_EXCLUSIVE);
 540                         for (i = 0, tmp = 0; i < RADEON_NUM_RINGS; ++i) {
 541                                 if (time_after(rdev->fence_drv[i].last_activity, tmp)) {
 542                                         tmp = rdev->fence_drv[i].last_activity;
 543                                 }
 544                         }
 545                         /* test if somebody else has already decided that this is a lockup */
 546                         if (last_activity != tmp) {
 547                                 last_activity = tmp;
 548                                 lockmgr(&rdev->ring_lock, LK_RELEASE);
 549                                 continue;
 550                         }
 551
 552                         if (radeon_ring_is_lockup(rdev, ring, &rdev->ring[ring])) {
 553                                 /* good news we believe it's a lockup */
 554                                 dev_warn(rdev->dev, "GPU lockup (waiting for 0x%016jx)\n",
 555                                          (uintmax_t)target_seq[ring]);
 556
 557                                 /* change last activity so nobody else think there is a lockup */
 558                                 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 559                                         rdev->fence_drv[i].last_activity = jiffies;
 560                                 }
 561
 562                                 /* mark the ring as not ready any more */
 563                                 rdev->ring[ring].ready = false;
 564                                 lockmgr(&rdev->ring_lock, LK_RELEASE);
 565                                 return -EDEADLK;
 566                         }
 567                         lockmgr(&rdev->ring_lock, LK_RELEASE);
 568                 }
 569         }
 570         return 0;
 571 }
 572
 573 /**
 574  * radeon_fence_wait_any - wait for a fence to signal on any ring
 575  *
 576  * @rdev: radeon device pointer
 577  * @fences: radeon fence object(s)
 578  * @intr: use interruptable sleep
 579  *
 580  * Wait for any requested fence to signal (all asics).  Fence
 581  * array is indexed by ring id.  @intr selects whether to use
 582  * interruptable (true) or non-interruptable (false) sleep when
 583  * waiting for the fences. Used by the suballocator.
 584  * Returns 0 if any fence has passed, error for all other cases.
 585  */
 586 int radeon_fence_wait_any(struct radeon_device *rdev,
 587                           struct radeon_fence **fences,
 588                           bool intr)
 589 {
 590         uint64_t seq[RADEON_NUM_RINGS];
 591         unsigned i;
 592         int r;
 593
 594         for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 595                 seq[i] = 0;
 596
 597                 if (!fences[i]) {
 598                         continue;
 599                 }
 600
 601                 if (fences[i]->seq == RADEON_FENCE_SIGNALED_SEQ) {
 602                         /* something was allready signaled */
 603                         return 0;
 604                 }
 605
 606                 seq[i] = fences[i]->seq;
 607         }
 608
 609         r = radeon_fence_wait_any_seq(rdev, seq, intr);
 610         if (r) {
 611                 return r;
 612         }
 613         return 0;
 614 }
 615
 616 /**
 617  * radeon_fence_wait_next_locked - wait for the next fence to signal
 618  *
 619  * @rdev: radeon device pointer
 620  * @ring: ring index the fence is associated with
 621  *
 622  * Wait for the next fence on the requested ring to signal (all asics).
 623  * Returns 0 if the next fence has passed, error for all other cases.
 624  * Caller must hold ring lock.
 625  */
 626 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring)
 627 {
 628         uint64_t seq;
 629
 630         seq = atomic64_read(&rdev->fence_drv[ring].last_seq) + 1ULL;
 631         if (seq >= rdev->fence_drv[ring].sync_seq[ring]) {
 632                 /* nothing to wait for, last_seq is
 633                    already the last emited fence */
 634                 return -ENOENT;
 635         }
 636         return radeon_fence_wait_seq(rdev, seq, ring, false, false);
 637 }
 638
 639 /**
 640  * radeon_fence_wait_empty_locked - wait for all fences to signal
 641  *
 642  * @rdev: radeon device pointer
 643  * @ring: ring index the fence is associated with
 644  *
 645  * Wait for all fences on the requested ring to signal (all asics).
 646  * Returns 0 if the fences have passed, error for all other cases.
 647  * Caller must hold ring lock.
 648  */
 649 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring)
 650 {
 651         uint64_t seq = rdev->fence_drv[ring].sync_seq[ring];
 652         int r;
 653
 654         r = radeon_fence_wait_seq(rdev, seq, ring, false, false);
 655         if (r) {
 656                 if (r == -EDEADLK) {
 657                         return -EDEADLK;
 658                 }
 659                 dev_err(rdev->dev, "error waiting for ring[%d] to become idle (%d)\n",
 660                         ring, r);
 661         }
 662         return 0;
 663 }
 664
 665 /**
 666  * radeon_fence_ref - take a ref on a fence
 667  *
 668  * @fence: radeon fence object
 669  *
 670  * Take a reference on a fence (all asics).
 671  * Returns the fence.
 672  */
 673 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)
 674 {
 675         refcount_acquire(&fence->kref);
 676         return fence;
 677 }
 678
 679 /**
 680  * radeon_fence_unref - remove a ref on a fence
 681  *
 682  * @fence: radeon fence object
 683  *
 684  * Remove a reference on a fence (all asics).
 685  */
 686 void radeon_fence_unref(struct radeon_fence **fence)
 687 {
 688         struct radeon_fence *tmp = *fence;
 689
 690         *fence = NULL;
 691         if (tmp) {
 692                 if (refcount_release(&tmp->kref)) {
 693                         radeon_fence_destroy(tmp);
 694                 }
 695         }
 696 }
 697
 698 /**
 699  * radeon_fence_count_emitted - get the count of emitted fences
 700  *
 701  * @rdev: radeon device pointer
 702  * @ring: ring index the fence is associated with
 703  *
 704  * Get the number of fences emitted on the requested ring (all asics).
 705  * Returns the number of emitted fences on the ring.  Used by the
 706  * dynpm code to ring track activity.
 707  */
 708 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring)
 709 {
 710         uint64_t emitted;
 711
 712         /* We are not protected by ring lock when reading the last sequence
 713          * but it's ok to report slightly wrong fence count here.
 714          */
 715         radeon_fence_process(rdev, ring);
 716         emitted = rdev->fence_drv[ring].sync_seq[ring]
 717                 - atomic64_read(&rdev->fence_drv[ring].last_seq);
 718         /* to avoid 32bits warp around */
 719         if (emitted > 0x10000000) {
 720                 emitted = 0x10000000;
 721         }
 722         return (unsigned)emitted;
 723 }
 724
 725 /**
 726  * radeon_fence_need_sync - do we need a semaphore
 727  *
 728  * @fence: radeon fence object
 729  * @dst_ring: which ring to check against
 730  *
 731  * Check if the fence needs to be synced against another ring
 732  * (all asics).  If so, we need to emit a semaphore.
 733  * Returns true if we need to sync with another ring, false if
 734  * not.
 735  */
 736 bool radeon_fence_need_sync(struct radeon_fence *fence, int dst_ring)
 737 {
 738         struct radeon_fence_driver *fdrv;
 739
 740         if (!fence) {
 741                 return false;
 742         }
 743
 744         if (fence->ring == dst_ring) {
 745                 return false;
 746         }
 747
 748         /* we are protected by the ring mutex */
 749         fdrv = &fence->rdev->fence_drv[dst_ring];
 750         if (fence->seq <= fdrv->sync_seq[fence->ring]) {
 751                 return false;
 752         }
 753
 754         return true;
 755 }
 756
 757 /**
 758  * radeon_fence_note_sync - record the sync point
 759  *
 760  * @fence: radeon fence object
 761  * @dst_ring: which ring to check against
 762  *
 763  * Note the sequence number at which point the fence will
 764  * be synced with the requested ring (all asics).
 765  */
 766 void radeon_fence_note_sync(struct radeon_fence *fence, int dst_ring)
 767 {
 768         struct radeon_fence_driver *dst, *src;
 769         unsigned i;
 770
 771         if (!fence) {
 772                 return;
 773         }
 774
 775         if (fence->ring == dst_ring) {
 776                 return;
 777         }
 778
 779         /* we are protected by the ring mutex */
 780         src = &fence->rdev->fence_drv[fence->ring];
 781         dst = &fence->rdev->fence_drv[dst_ring];
 782         for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 783                 if (i == dst_ring) {
 784                         continue;
 785                 }
 786                 dst->sync_seq[i] = max(dst->sync_seq[i], src->sync_seq[i]);
 787         }
 788 }
 789
 790 /**
 791  * radeon_fence_driver_start_ring - make the fence driver
 792  * ready for use on the requested ring.
 793  *
 794  * @rdev: radeon device pointer
 795  * @ring: ring index to start the fence driver on
 796  *
 797  * Make the fence driver ready for processing (all asics).
 798  * Not all asics have all rings, so each asic will only
 799  * start the fence driver on the rings it has.
 800  * Returns 0 for success, errors for failure.
 801  */
 802 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring)
 803 {
 804         uint64_t index;
 805         int r;
 806
 807         radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
 808         if (rdev->wb.use_event || !radeon_ring_supports_scratch_reg(rdev, &rdev->ring[ring])) {
 809                 rdev->fence_drv[ring].scratch_reg = 0;
 810                 index = R600_WB_EVENT_OFFSET + ring * 4;
 811         } else {
 812                 r = radeon_scratch_get(rdev, &rdev->fence_drv[ring].scratch_reg);
 813                 if (r) {
 814                         dev_err(rdev->dev, "fence failed to get scratch register\n");
 815                         return r;
 816                 }
 817                 index = RADEON_WB_SCRATCH_OFFSET +
 818                         rdev->fence_drv[ring].scratch_reg -
 819                         rdev->scratch.reg_base;
 820         }
 821         rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
 822         rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index;
 823         radeon_fence_write(rdev, atomic64_read(&rdev->fence_drv[ring].last_seq), ring);
 824         rdev->fence_drv[ring].initialized = true;
 825         dev_info(rdev->dev, "fence driver on ring %d use gpu addr 0x%016jx and cpu addr 0x%p\n",
 826                  ring, (uintmax_t)rdev->fence_drv[ring].gpu_addr, rdev->fence_drv[ring].cpu_addr);
 827         return 0;
 828 }
 829
 830 /**
 831  * radeon_fence_driver_init_ring - init the fence driver
 832  * for the requested ring.
 833  *
 834  * @rdev: radeon device pointer
 835  * @ring: ring index to start the fence driver on
 836  *
 837  * Init the fence driver for the requested ring (all asics).
 838  * Helper function for radeon_fence_driver_init().
 839  */
 840 static void radeon_fence_driver_init_ring(struct radeon_device *rdev, int ring)
 841 {
 842         int i;
 843
 844         rdev->fence_drv[ring].scratch_reg = -1;
 845         rdev->fence_drv[ring].cpu_addr = NULL;
 846         rdev->fence_drv[ring].gpu_addr = 0;
 847         for (i = 0; i < RADEON_NUM_RINGS; ++i)
 848                 rdev->fence_drv[ring].sync_seq[i] = 0;
 849         atomic64_set(&rdev->fence_drv[ring].last_seq, 0);
 850         rdev->fence_drv[ring].last_activity = jiffies;
 851         rdev->fence_drv[ring].initialized = false;
 852 }
 853
 854 /**
 855  * radeon_fence_driver_init - init the fence driver
 856  * for all possible rings.
 857  *
 858  * @rdev: radeon device pointer
 859  *
 860  * Init the fence driver for all possible rings (all asics).
 861  * Not all asics have all rings, so each asic will only
 862  * start the fence driver on the rings it has using
 863  * radeon_fence_driver_start_ring().
 864  * Returns 0 for success.
 865  */
 866 int radeon_fence_driver_init(struct radeon_device *rdev)
 867 {
 868         int ring;
 869
 870         lockinit(&rdev->fence_queue_mtx,
 871             "drm__radeon_device__fence_queue_mtx", 0, LK_CANRECURSE);
 872         cv_init(&rdev->fence_queue, "drm__radeon_device__fence_queue");
 873         for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
 874                 radeon_fence_driver_init_ring(rdev, ring);
 875         }
 876         if (radeon_debugfs_fence_init(rdev)) {
 877                 dev_err(rdev->dev, "fence debugfs file creation failed\n");
 878         }
 879         return 0;
 880 }
 881
 882 /**
 883  * radeon_fence_driver_fini - tear down the fence driver
 884  * for all possible rings.
 885  *
 886  * @rdev: radeon device pointer
 887  *
 888  * Tear down the fence driver for all possible rings (all asics).
 889  */
 890 void radeon_fence_driver_fini(struct radeon_device *rdev)
 891 {
 892         int ring, r;
 893
 894         lockmgr(&rdev->ring_lock, LK_EXCLUSIVE);
 895         for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
 896                 if (!rdev->fence_drv[ring].initialized)
 897                         continue;
 898                 r = radeon_fence_wait_empty_locked(rdev, ring);
 899                 if (r) {
 900                         /* no need to trigger GPU reset as we are unloading */
 901                         radeon_fence_driver_force_completion(rdev);
 902                 }
 903                 cv_broadcast(&rdev->fence_queue);
 904                 radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
 905                 rdev->fence_drv[ring].initialized = false;
 906                 cv_destroy(&rdev->fence_queue);
 907         }
 908         lockmgr(&rdev->ring_lock, LK_RELEASE);
 909 }
 910
 911 /**
 912  * radeon_fence_driver_force_completion - force all fence waiter to complete
 913  *
 914  * @rdev: radeon device pointer
 915  *
 916  * In case of GPU reset failure make sure no process keep waiting on fence
 917  * that will never complete.
 918  */
 919 void radeon_fence_driver_force_completion(struct radeon_device *rdev)
 920 {
 921         int ring;
 922
 923         for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
 924                 if (!rdev->fence_drv[ring].initialized)
 925                         continue;
 926                 radeon_fence_write(rdev, rdev->fence_drv[ring].sync_seq[ring], ring);
 927         }
 928 }
 929
 930
 931 /*
 932  * Fence debugfs
 933  */
 934 #if defined(CONFIG_DEBUG_FS)
 935 static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
 936 {
 937         struct drm_info_node *node = (struct drm_info_node *)m->private;
 938         struct drm_device *dev = node->minor->dev;
 939         struct radeon_device *rdev = dev->dev_private;
 940         int i, j;
 941
 942         for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 943                 if (!rdev->fence_drv[i].initialized)
 944                         continue;
 945
 946                 seq_printf(m, "--- ring %d ---\n", i);
 947                 seq_printf(m, "Last signaled fence 0x%016llx\n",
 948                            (unsigned long long)atomic_load_acq_64(&rdev->fence_drv[i].last_seq));
 949                 seq_printf(m, "Last emitted        0x%016llx\n",
 950                            rdev->fence_drv[i].sync_seq[i]);
 951
 952                 for (j = 0; j < RADEON_NUM_RINGS; ++j) {
 953                         if (i != j && rdev->fence_drv[j].initialized)
 954                                 seq_printf(m, "Last sync to ring %d 0x%016llx\n",
 955                                            j, rdev->fence_drv[i].sync_seq[j]);
 956                 }
 957         }
 958         return 0;
 959 }
 960
 961 static struct drm_info_list radeon_debugfs_fence_list[] = {
 962         {"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL},
 963 };
 964 #endif
 965
 966 int radeon_debugfs_fence_init(struct radeon_device *rdev)
 967 {
 968 #if defined(CONFIG_DEBUG_FS)
 969         return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1);
 970 #else
 971         return 0;
 972 #endif
 973 }