sys/dev/netif/ig_hal/e1000_nvm.c

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2012, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD:$*/
  34
  35 #include "e1000_api.h"
  36
  37 static void e1000_reload_nvm_generic(struct e1000_hw *hw);
  38
  39 /**
  40  *  e1000_init_nvm_ops_generic - Initialize NVM function pointers
  41  *  @hw: pointer to the HW structure
  42  *
  43  *  Setups up the function pointers to no-op functions
  44  **/
  45 void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
  46 {
  47         struct e1000_nvm_info *nvm = &hw->nvm;
  48         DEBUGFUNC("e1000_init_nvm_ops_generic");
  49
  50         /* Initialize function pointers */
  51         nvm->ops.init_params = e1000_null_ops_generic;
  52         nvm->ops.acquire = e1000_null_ops_generic;
  53         nvm->ops.read = e1000_null_read_nvm;
  54         nvm->ops.release = e1000_null_nvm_generic;
  55         nvm->ops.reload = e1000_reload_nvm_generic;
  56         nvm->ops.update = e1000_null_ops_generic;
  57         nvm->ops.valid_led_default = e1000_null_led_default;
  58         nvm->ops.validate = e1000_null_ops_generic;
  59         nvm->ops.write = e1000_null_write_nvm;
  60 }
  61
  62 /**
  63  *  e1000_null_nvm_read - No-op function, return 0
  64  *  @hw: pointer to the HW structure
  65  **/
  66 s32 e1000_null_read_nvm(struct e1000_hw E1000_UNUSEDARG *hw,
  67                         u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,
  68                         u16 E1000_UNUSEDARG *c)
  69 {
  70         DEBUGFUNC("e1000_null_read_nvm");
  71         return E1000_SUCCESS;
  72 }
  73
  74 /**
  75  *  e1000_null_nvm_generic - No-op function, return void
  76  *  @hw: pointer to the HW structure
  77  **/
  78 void e1000_null_nvm_generic(struct e1000_hw E1000_UNUSEDARG *hw)
  79 {
  80         DEBUGFUNC("e1000_null_nvm_generic");
  81         return;
  82 }
  83
  84 /**
  85  *  e1000_null_led_default - No-op function, return 0
  86  *  @hw: pointer to the HW structure
  87  **/
  88 s32 e1000_null_led_default(struct e1000_hw E1000_UNUSEDARG *hw,
  89                            u16 E1000_UNUSEDARG *data)
  90 {
  91         DEBUGFUNC("e1000_null_led_default");
  92         return E1000_SUCCESS;
  93 }
  94
  95 /**
  96  *  e1000_null_write_nvm - No-op function, return 0
  97  *  @hw: pointer to the HW structure
  98  **/
  99 s32 e1000_null_write_nvm(struct e1000_hw E1000_UNUSEDARG *hw,
 100                          u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,
 101                          u16 E1000_UNUSEDARG *c)
 102 {
 103         DEBUGFUNC("e1000_null_write_nvm");
 104         return E1000_SUCCESS;
 105 }
 106
 107 /**
 108  *  e1000_raise_eec_clk - Raise EEPROM clock
 109  *  @hw: pointer to the HW structure
 110  *  @eecd: pointer to the EEPROM
 111  *
 112  *  Enable/Raise the EEPROM clock bit.
 113  **/
 114 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
 115 {
 116         *eecd = *eecd | E1000_EECD_SK;
 117         E1000_WRITE_REG(hw, E1000_EECD, *eecd);
 118         E1000_WRITE_FLUSH(hw);
 119         usec_delay(hw->nvm.delay_usec);
 120 }
 121
 122 /**
 123  *  e1000_lower_eec_clk - Lower EEPROM clock
 124  *  @hw: pointer to the HW structure
 125  *  @eecd: pointer to the EEPROM
 126  *
 127  *  Clear/Lower the EEPROM clock bit.
 128  **/
 129 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
 130 {
 131         *eecd = *eecd & ~E1000_EECD_SK;
 132         E1000_WRITE_REG(hw, E1000_EECD, *eecd);
 133         E1000_WRITE_FLUSH(hw);
 134         usec_delay(hw->nvm.delay_usec);
 135 }
 136
 137 /**
 138  *  e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
 139  *  @hw: pointer to the HW structure
 140  *  @data: data to send to the EEPROM
 141  *  @count: number of bits to shift out
 142  *
 143  *  We need to shift 'count' bits out to the EEPROM.  So, the value in the
 144  *  "data" parameter will be shifted out to the EEPROM one bit at a time.
 145  *  In order to do this, "data" must be broken down into bits.
 146  **/
 147 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
 148 {
 149         struct e1000_nvm_info *nvm = &hw->nvm;
 150         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 151         u32 mask;
 152
 153         DEBUGFUNC("e1000_shift_out_eec_bits");
 154
 155         mask = 0x01 << (count - 1);
 156         if (nvm->type == e1000_nvm_eeprom_microwire)
 157                 eecd &= ~E1000_EECD_DO;
 158         else
 159         if (nvm->type == e1000_nvm_eeprom_spi)
 160                 eecd |= E1000_EECD_DO;
 161
 162         do {
 163                 eecd &= ~E1000_EECD_DI;
 164
 165                 if (data & mask)
 166                         eecd |= E1000_EECD_DI;
 167
 168                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 169                 E1000_WRITE_FLUSH(hw);
 170
 171                 usec_delay(nvm->delay_usec);
 172
 173                 e1000_raise_eec_clk(hw, &eecd);
 174                 e1000_lower_eec_clk(hw, &eecd);
 175
 176                 mask >>= 1;
 177         } while (mask);
 178
 179         eecd &= ~E1000_EECD_DI;
 180         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 181 }
 182
 183 /**
 184  *  e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
 185  *  @hw: pointer to the HW structure
 186  *  @count: number of bits to shift in
 187  *
 188  *  In order to read a register from the EEPROM, we need to shift 'count' bits
 189  *  in from the EEPROM.  Bits are "shifted in" by raising the clock input to
 190  *  the EEPROM (setting the SK bit), and then reading the value of the data out
 191  *  "DO" bit.  During this "shifting in" process the data in "DI" bit should
 192  *  always be clear.
 193  **/
 194 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
 195 {
 196         u32 eecd;
 197         u32 i;
 198         u16 data;
 199
 200         DEBUGFUNC("e1000_shift_in_eec_bits");
 201
 202         eecd = E1000_READ_REG(hw, E1000_EECD);
 203
 204         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 205         data = 0;
 206
 207         for (i = 0; i < count; i++) {
 208                 data <<= 1;
 209                 e1000_raise_eec_clk(hw, &eecd);
 210
 211                 eecd = E1000_READ_REG(hw, E1000_EECD);
 212
 213                 eecd &= ~E1000_EECD_DI;
 214                 if (eecd & E1000_EECD_DO)
 215                         data |= 1;
 216
 217                 e1000_lower_eec_clk(hw, &eecd);
 218         }
 219
 220         return data;
 221 }
 222
 223 /**
 224  *  e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
 225  *  @hw: pointer to the HW structure
 226  *  @ee_reg: EEPROM flag for polling
 227  *
 228  *  Polls the EEPROM status bit for either read or write completion based
 229  *  upon the value of 'ee_reg'.
 230  **/
 231 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
 232 {
 233         u32 attempts = 100000;
 234         u32 i, reg = 0;
 235
 236         DEBUGFUNC("e1000_poll_eerd_eewr_done");
 237
 238         for (i = 0; i < attempts; i++) {
 239                 if (ee_reg == E1000_NVM_POLL_READ)
 240                         reg = E1000_READ_REG(hw, E1000_EERD);
 241                 else
 242                         reg = E1000_READ_REG(hw, E1000_EEWR);
 243
 244                 if (reg & E1000_NVM_RW_REG_DONE)
 245                         return E1000_SUCCESS;
 246
 247                 usec_delay(5);
 248         }
 249
 250         return -E1000_ERR_NVM;
 251 }
 252
 253 /**
 254  *  e1000_acquire_nvm_generic - Generic request for access to EEPROM
 255  *  @hw: pointer to the HW structure
 256  *
 257  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
 258  *  Return successful if access grant bit set, else clear the request for
 259  *  EEPROM access and return -E1000_ERR_NVM (-1).
 260  **/
 261 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
 262 {
 263         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 264         s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
 265
 266         DEBUGFUNC("e1000_acquire_nvm_generic");
 267
 268         E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
 269         eecd = E1000_READ_REG(hw, E1000_EECD);
 270
 271         while (timeout) {
 272                 if (eecd & E1000_EECD_GNT)
 273                         break;
 274                 usec_delay(5);
 275                 eecd = E1000_READ_REG(hw, E1000_EECD);
 276                 timeout--;
 277         }
 278
 279         if (!timeout) {
 280                 eecd &= ~E1000_EECD_REQ;
 281                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 282                 DEBUGOUT("Could not acquire NVM grant\n");
 283                 return -E1000_ERR_NVM;
 284         }
 285
 286         return E1000_SUCCESS;
 287 }
 288
 289 /**
 290  *  e1000_standby_nvm - Return EEPROM to standby state
 291  *  @hw: pointer to the HW structure
 292  *
 293  *  Return the EEPROM to a standby state.
 294  **/
 295 static void e1000_standby_nvm(struct e1000_hw *hw)
 296 {
 297         struct e1000_nvm_info *nvm = &hw->nvm;
 298         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 299
 300         DEBUGFUNC("e1000_standby_nvm");
 301
 302         if (nvm->type == e1000_nvm_eeprom_microwire) {
 303                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 304                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 305                 E1000_WRITE_FLUSH(hw);
 306                 usec_delay(nvm->delay_usec);
 307
 308                 e1000_raise_eec_clk(hw, &eecd);
 309
 310                 /* Select EEPROM */
 311                 eecd |= E1000_EECD_CS;
 312                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 313                 E1000_WRITE_FLUSH(hw);
 314                 usec_delay(nvm->delay_usec);
 315
 316                 e1000_lower_eec_clk(hw, &eecd);
 317         } else if (nvm->type == e1000_nvm_eeprom_spi) {
 318                 /* Toggle CS to flush commands */
 319                 eecd |= E1000_EECD_CS;
 320                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 321                 E1000_WRITE_FLUSH(hw);
 322                 usec_delay(nvm->delay_usec);
 323                 eecd &= ~E1000_EECD_CS;
 324                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 325                 E1000_WRITE_FLUSH(hw);
 326                 usec_delay(nvm->delay_usec);
 327         }
 328 }
 329
 330 /**
 331  *  e1000_stop_nvm - Terminate EEPROM command
 332  *  @hw: pointer to the HW structure
 333  *
 334  *  Terminates the current command by inverting the EEPROM's chip select pin.
 335  **/
 336 #ifdef NO_82542_SUPPORT
 337 static void e1000_stop_nvm(struct e1000_hw *hw)
 338 #else
 339 void e1000_stop_nvm(struct e1000_hw *hw)
 340 #endif
 341 {
 342         u32 eecd;
 343
 344         DEBUGFUNC("e1000_stop_nvm");
 345
 346         eecd = E1000_READ_REG(hw, E1000_EECD);
 347         if (hw->nvm.type == e1000_nvm_eeprom_spi) {
 348                 /* Pull CS high */
 349                 eecd |= E1000_EECD_CS;
 350                 e1000_lower_eec_clk(hw, &eecd);
 351         } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
 352                 /* CS on Microwire is active-high */
 353                 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
 354                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 355                 e1000_raise_eec_clk(hw, &eecd);
 356                 e1000_lower_eec_clk(hw, &eecd);
 357         }
 358 }
 359
 360 /**
 361  *  e1000_release_nvm_generic - Release exclusive access to EEPROM
 362  *  @hw: pointer to the HW structure
 363  *
 364  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 365  **/
 366 void e1000_release_nvm_generic(struct e1000_hw *hw)
 367 {
 368         u32 eecd;
 369
 370         DEBUGFUNC("e1000_release_nvm_generic");
 371
 372         e1000_stop_nvm(hw);
 373
 374         eecd = E1000_READ_REG(hw, E1000_EECD);
 375         eecd &= ~E1000_EECD_REQ;
 376         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 377 }
 378
 379 /**
 380  *  e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
 381  *  @hw: pointer to the HW structure
 382  *
 383  *  Setups the EEPROM for reading and writing.
 384  **/
 385 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
 386 {
 387         struct e1000_nvm_info *nvm = &hw->nvm;
 388         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 389         u8 spi_stat_reg;
 390
 391         DEBUGFUNC("e1000_ready_nvm_eeprom");
 392
 393         if (nvm->type == e1000_nvm_eeprom_microwire) {
 394                 /* Clear SK and DI */
 395                 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
 396                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 397                 /* Set CS */
 398                 eecd |= E1000_EECD_CS;
 399                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 400         } else if (nvm->type == e1000_nvm_eeprom_spi) {
 401                 u16 timeout = NVM_MAX_RETRY_SPI;
 402
 403                 /* Clear SK and CS */
 404                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 405                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 406                 E1000_WRITE_FLUSH(hw);
 407                 usec_delay(1);
 408
 409                 /* Read "Status Register" repeatedly until the LSB is cleared.
 410                  * The EEPROM will signal that the command has been completed
 411                  * by clearing bit 0 of the internal status register.  If it's
 412                  * not cleared within 'timeout', then error out.
 413                  */
 414                 while (timeout) {
 415                         e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
 416                                                  hw->nvm.opcode_bits);
 417                         spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
 418                         if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
 419                                 break;
 420
 421                         usec_delay(5);
 422                         e1000_standby_nvm(hw);
 423                         timeout--;
 424                 }
 425
 426                 if (!timeout) {
 427                         DEBUGOUT("SPI NVM Status error\n");
 428                         return -E1000_ERR_NVM;
 429                 }
 430         }
 431
 432         return E1000_SUCCESS;
 433 }
 434
 435 /**
 436  *  e1000_read_nvm_spi - Read EEPROM's using SPI
 437  *  @hw: pointer to the HW structure
 438  *  @offset: offset of word in the EEPROM to read
 439  *  @words: number of words to read
 440  *  @data: word read from the EEPROM
 441  *
 442  *  Reads a 16 bit word from the EEPROM.
 443  **/
 444 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 445 {
 446         struct e1000_nvm_info *nvm = &hw->nvm;
 447         u32 i = 0;
 448         s32 ret_val;
 449         u16 word_in;
 450         u8 read_opcode = NVM_READ_OPCODE_SPI;
 451
 452         DEBUGFUNC("e1000_read_nvm_spi");
 453
 454         /* A check for invalid values:  offset too large, too many words,
 455          * and not enough words.
 456          */
 457         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 458             (words == 0)) {
 459                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 460                 return -E1000_ERR_NVM;
 461         }
 462
 463         ret_val = nvm->ops.acquire(hw);
 464         if (ret_val)
 465                 return ret_val;
 466
 467         ret_val = e1000_ready_nvm_eeprom(hw);
 468         if (ret_val)
 469                 goto release;
 470
 471         e1000_standby_nvm(hw);
 472
 473         if ((nvm->address_bits == 8) && (offset >= 128))
 474                 read_opcode |= NVM_A8_OPCODE_SPI;
 475
 476         /* Send the READ command (opcode + addr) */
 477         e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
 478         e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
 479
 480         /* Read the data.  SPI NVMs increment the address with each byte
 481          * read and will roll over if reading beyond the end.  This allows
 482          * us to read the whole NVM from any offset
 483          */
 484         for (i = 0; i < words; i++) {
 485                 word_in = e1000_shift_in_eec_bits(hw, 16);
 486                 data[i] = (word_in >> 8) | (word_in << 8);
 487         }
 488
 489 release:
 490         nvm->ops.release(hw);
 491
 492         return ret_val;
 493 }
 494
 495 /**
 496  *  e1000_read_nvm_microwire - Reads EEPROM's using microwire
 497  *  @hw: pointer to the HW structure
 498  *  @offset: offset of word in the EEPROM to read
 499  *  @words: number of words to read
 500  *  @data: word read from the EEPROM
 501  *
 502  *  Reads a 16 bit word from the EEPROM.
 503  **/
 504 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
 505                              u16 *data)
 506 {
 507         struct e1000_nvm_info *nvm = &hw->nvm;
 508         u32 i = 0;
 509         s32 ret_val;
 510         u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
 511
 512         DEBUGFUNC("e1000_read_nvm_microwire");
 513
 514         /* A check for invalid values:  offset too large, too many words,
 515          * and not enough words.
 516          */
 517         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 518             (words == 0)) {
 519                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 520                 return -E1000_ERR_NVM;
 521         }
 522
 523         ret_val = nvm->ops.acquire(hw);
 524         if (ret_val)
 525                 return ret_val;
 526
 527         ret_val = e1000_ready_nvm_eeprom(hw);
 528         if (ret_val)
 529                 goto release;
 530
 531         for (i = 0; i < words; i++) {
 532                 /* Send the READ command (opcode + addr) */
 533                 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
 534                 e1000_shift_out_eec_bits(hw, (u16)(offset + i),
 535                                         nvm->address_bits);
 536
 537                 /* Read the data.  For microwire, each word requires the
 538                  * overhead of setup and tear-down.
 539                  */
 540                 data[i] = e1000_shift_in_eec_bits(hw, 16);
 541                 e1000_standby_nvm(hw);
 542         }
 543
 544 release:
 545         nvm->ops.release(hw);
 546
 547         return ret_val;
 548 }
 549
 550 /**
 551  *  e1000_read_nvm_eerd - Reads EEPROM using EERD register
 552  *  @hw: pointer to the HW structure
 553  *  @offset: offset of word in the EEPROM to read
 554  *  @words: number of words to read
 555  *  @data: word read from the EEPROM
 556  *
 557  *  Reads a 16 bit word from the EEPROM using the EERD register.
 558  **/
 559 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 560 {
 561         struct e1000_nvm_info *nvm = &hw->nvm;
 562         u32 i, eerd = 0;
 563         s32 ret_val = E1000_SUCCESS;
 564
 565         DEBUGFUNC("e1000_read_nvm_eerd");
 566
 567         /* A check for invalid values:  offset too large, too many words,
 568          * too many words for the offset, and not enough words.
 569          */
 570         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 571             (words == 0)) {
 572                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 573                 return -E1000_ERR_NVM;
 574         }
 575
 576         for (i = 0; i < words; i++) {
 577                 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
 578                        E1000_NVM_RW_REG_START;
 579
 580                 E1000_WRITE_REG(hw, E1000_EERD, eerd);
 581                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
 582                 if (ret_val)
 583                         break;
 584
 585                 data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
 586                            E1000_NVM_RW_REG_DATA);
 587         }
 588
 589         return ret_val;
 590 }
 591
 592 /**
 593  *  e1000_write_nvm_spi - Write to EEPROM using SPI
 594  *  @hw: pointer to the HW structure
 595  *  @offset: offset within the EEPROM to be written to
 596  *  @words: number of words to write
 597  *  @data: 16 bit word(s) to be written to the EEPROM
 598  *
 599  *  Writes data to EEPROM at offset using SPI interface.
 600  *
 601  *  If e1000_update_nvm_checksum is not called after this function , the
 602  *  EEPROM will most likely contain an invalid checksum.
 603  **/
 604 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 605 {
 606         struct e1000_nvm_info *nvm = &hw->nvm;
 607         s32 ret_val = -E1000_ERR_NVM;
 608         u16 widx = 0;
 609
 610         DEBUGFUNC("e1000_write_nvm_spi");
 611
 612         /* A check for invalid values:  offset too large, too many words,
 613          * and not enough words.
 614          */
 615         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 616             (words == 0)) {
 617                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 618                 return -E1000_ERR_NVM;
 619         }
 620
 621         while (widx < words) {
 622                 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
 623
 624                 ret_val = nvm->ops.acquire(hw);
 625                 if (ret_val)
 626                         return ret_val;
 627
 628                 ret_val = e1000_ready_nvm_eeprom(hw);
 629                 if (ret_val) {
 630                         nvm->ops.release(hw);
 631                         return ret_val;
 632                 }
 633
 634                 e1000_standby_nvm(hw);
 635
 636                 /* Send the WRITE ENABLE command (8 bit opcode) */
 637                 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
 638                                          nvm->opcode_bits);
 639
 640                 e1000_standby_nvm(hw);
 641
 642                 /* Some SPI eeproms use the 8th address bit embedded in the
 643                  * opcode
 644                  */
 645                 if ((nvm->address_bits == 8) && (offset >= 128))
 646                         write_opcode |= NVM_A8_OPCODE_SPI;
 647
 648                 /* Send the Write command (8-bit opcode + addr) */
 649                 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
 650                 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
 651                                          nvm->address_bits);
 652
 653                 /* Loop to allow for up to whole page write of eeprom */
 654                 while (widx < words) {
 655                         u16 word_out = data[widx];
 656                         word_out = (word_out >> 8) | (word_out << 8);
 657                         e1000_shift_out_eec_bits(hw, word_out, 16);
 658                         widx++;
 659
 660                         if ((((offset + widx) * 2) % nvm->page_size) == 0) {
 661                                 e1000_standby_nvm(hw);
 662                                 break;
 663                         }
 664                 }
 665                 msec_delay(10);
 666                 nvm->ops.release(hw);
 667         }
 668
 669         return ret_val;
 670 }
 671
 672 /**
 673  *  e1000_write_nvm_microwire - Writes EEPROM using microwire
 674  *  @hw: pointer to the HW structure
 675  *  @offset: offset within the EEPROM to be written to
 676  *  @words: number of words to write
 677  *  @data: 16 bit word(s) to be written to the EEPROM
 678  *
 679  *  Writes data to EEPROM at offset using microwire interface.
 680  *
 681  *  If e1000_update_nvm_checksum is not called after this function , the
 682  *  EEPROM will most likely contain an invalid checksum.
 683  **/
 684 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
 685                               u16 *data)
 686 {
 687         struct e1000_nvm_info *nvm = &hw->nvm;
 688         s32  ret_val;
 689         u32 eecd;
 690         u16 words_written = 0;
 691         u16 widx = 0;
 692
 693         DEBUGFUNC("e1000_write_nvm_microwire");
 694
 695         /* A check for invalid values:  offset too large, too many words,
 696          * and not enough words.
 697          */
 698         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 699             (words == 0)) {
 700                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 701                 return -E1000_ERR_NVM;
 702         }
 703
 704         ret_val = nvm->ops.acquire(hw);
 705         if (ret_val)
 706                 return ret_val;
 707
 708         ret_val = e1000_ready_nvm_eeprom(hw);
 709         if (ret_val)
 710                 goto release;
 711
 712         e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
 713                                  (u16)(nvm->opcode_bits + 2));
 714
 715         e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
 716
 717         e1000_standby_nvm(hw);
 718
 719         while (words_written < words) {
 720                 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
 721                                          nvm->opcode_bits);
 722
 723                 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
 724                                          nvm->address_bits);
 725
 726                 e1000_shift_out_eec_bits(hw, data[words_written], 16);
 727
 728                 e1000_standby_nvm(hw);
 729
 730                 for (widx = 0; widx < 200; widx++) {
 731                         eecd = E1000_READ_REG(hw, E1000_EECD);
 732                         if (eecd & E1000_EECD_DO)
 733                                 break;
 734                         usec_delay(50);
 735                 }
 736
 737                 if (widx == 200) {
 738                         DEBUGOUT("NVM Write did not complete\n");
 739                         ret_val = -E1000_ERR_NVM;
 740                         goto release;
 741                 }
 742
 743                 e1000_standby_nvm(hw);
 744
 745                 words_written++;
 746         }
 747
 748         e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
 749                                  (u16)(nvm->opcode_bits + 2));
 750
 751         e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
 752
 753 release:
 754         nvm->ops.release(hw);
 755
 756         return ret_val;
 757 }
 758
 759 /**
 760  *  e1000_read_pba_string_generic - Read device part number
 761  *  @hw: pointer to the HW structure
 762  *  @pba_num: pointer to device part number
 763  *  @pba_num_size: size of part number buffer
 764  *
 765  *  Reads the product board assembly (PBA) number from the EEPROM and stores
 766  *  the value in pba_num.
 767  **/
 768 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
 769                                   u32 pba_num_size)
 770 {
 771         s32 ret_val;
 772         u16 nvm_data;
 773         u16 pba_ptr;
 774         u16 offset;
 775         u16 length;
 776
 777         DEBUGFUNC("e1000_read_pba_string_generic");
 778
 779         if (pba_num == NULL) {
 780                 DEBUGOUT("PBA string buffer was null\n");
 781                 return -E1000_ERR_INVALID_ARGUMENT;
 782         }
 783
 784         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
 785         if (ret_val) {
 786                 DEBUGOUT("NVM Read Error\n");
 787                 return ret_val;
 788         }
 789
 790         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
 791         if (ret_val) {
 792                 DEBUGOUT("NVM Read Error\n");
 793                 return ret_val;
 794         }
 795
 796         /* if nvm_data is not ptr guard the PBA must be in legacy format which
 797          * means pba_ptr is actually our second data word for the PBA number
 798          * and we can decode it into an ascii string
 799          */
 800         if (nvm_data != NVM_PBA_PTR_GUARD) {
 801                 DEBUGOUT("NVM PBA number is not stored as string\n");
 802
 803                 /* make sure callers buffer is big enough to store the PBA */
 804                 if (pba_num_size < E1000_PBANUM_LENGTH) {
 805                         DEBUGOUT("PBA string buffer too small\n");
 806                         return E1000_ERR_NO_SPACE;
 807                 }
 808
 809                 /* extract hex string from data and pba_ptr */
 810                 pba_num[0] = (nvm_data >> 12) & 0xF;
 811                 pba_num[1] = (nvm_data >> 8) & 0xF;
 812                 pba_num[2] = (nvm_data >> 4) & 0xF;
 813                 pba_num[3] = nvm_data & 0xF;
 814                 pba_num[4] = (pba_ptr >> 12) & 0xF;
 815                 pba_num[5] = (pba_ptr >> 8) & 0xF;
 816                 pba_num[6] = '-';
 817                 pba_num[7] = 0;
 818                 pba_num[8] = (pba_ptr >> 4) & 0xF;
 819                 pba_num[9] = pba_ptr & 0xF;
 820
 821                 /* put a null character on the end of our string */
 822                 pba_num[10] = '\0';
 823
 824                 /* switch all the data but the '-' to hex char */
 825                 for (offset = 0; offset < 10; offset++) {
 826                         if (pba_num[offset] < 0xA)
 827                                 pba_num[offset] += '0';
 828                         else if (pba_num[offset] < 0x10)
 829                                 pba_num[offset] += 'A' - 0xA;
 830                 }
 831
 832                 return E1000_SUCCESS;
 833         }
 834
 835         ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
 836         if (ret_val) {
 837                 DEBUGOUT("NVM Read Error\n");
 838                 return ret_val;
 839         }
 840
 841         if (length == 0xFFFF || length == 0) {
 842                 DEBUGOUT("NVM PBA number section invalid length\n");
 843                 return -E1000_ERR_NVM_PBA_SECTION;
 844         }
 845         /* check if pba_num buffer is big enough */
 846         if (pba_num_size < (((u32)length * 2) - 1)) {
 847                 DEBUGOUT("PBA string buffer too small\n");
 848                 return -E1000_ERR_NO_SPACE;
 849         }
 850
 851         /* trim pba length from start of string */
 852         pba_ptr++;
 853         length--;
 854
 855         for (offset = 0; offset < length; offset++) {
 856                 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
 857                 if (ret_val) {
 858                         DEBUGOUT("NVM Read Error\n");
 859                         return ret_val;
 860                 }
 861                 pba_num[offset * 2] = (u8)(nvm_data >> 8);
 862                 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
 863         }
 864         pba_num[offset * 2] = '\0';
 865
 866         return E1000_SUCCESS;
 867 }
 868
 869 /**
 870  *  e1000_read_pba_length_generic - Read device part number length
 871  *  @hw: pointer to the HW structure
 872  *  @pba_num_size: size of part number buffer
 873  *
 874  *  Reads the product board assembly (PBA) number length from the EEPROM and
 875  *  stores the value in pba_num_size.
 876  **/
 877 s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size)
 878 {
 879         s32 ret_val;
 880         u16 nvm_data;
 881         u16 pba_ptr;
 882         u16 length;
 883
 884         DEBUGFUNC("e1000_read_pba_length_generic");
 885
 886         if (pba_num_size == NULL) {
 887                 DEBUGOUT("PBA buffer size was null\n");
 888                 return -E1000_ERR_INVALID_ARGUMENT;
 889         }
 890
 891         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
 892         if (ret_val) {
 893                 DEBUGOUT("NVM Read Error\n");
 894                 return ret_val;
 895         }
 896
 897         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
 898         if (ret_val) {
 899                 DEBUGOUT("NVM Read Error\n");
 900                 return ret_val;
 901         }
 902
 903          /* if data is not ptr guard the PBA must be in legacy format */
 904         if (nvm_data != NVM_PBA_PTR_GUARD) {
 905                 *pba_num_size = E1000_PBANUM_LENGTH;
 906                 return E1000_SUCCESS;
 907         }
 908
 909         ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
 910         if (ret_val) {
 911                 DEBUGOUT("NVM Read Error\n");
 912                 return ret_val;
 913         }
 914
 915         if (length == 0xFFFF || length == 0) {
 916                 DEBUGOUT("NVM PBA number section invalid length\n");
 917                 return -E1000_ERR_NVM_PBA_SECTION;
 918         }
 919
 920         /* Convert from length in u16 values to u8 chars, add 1 for NULL,
 921          * and subtract 2 because length field is included in length.
 922          */
 923         *pba_num_size = ((u32)length * 2) - 1;
 924
 925         return E1000_SUCCESS;
 926 }
 927
 928 /**
 929  *  e1000_read_pba_num_generic - Read device part number
 930  *  @hw: pointer to the HW structure
 931  *  @pba_num: pointer to device part number
 932  *
 933  *  Reads the product board assembly (PBA) number from the EEPROM and stores
 934  *  the value in pba_num.
 935  **/
 936 s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num)
 937 {
 938         s32 ret_val;
 939         u16 nvm_data;
 940
 941         DEBUGFUNC("e1000_read_pba_num_generic");
 942
 943         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
 944         if (ret_val) {
 945                 DEBUGOUT("NVM Read Error\n");
 946                 return ret_val;
 947         } else if (nvm_data == NVM_PBA_PTR_GUARD) {
 948                 DEBUGOUT("NVM Not Supported\n");
 949                 return -E1000_NOT_IMPLEMENTED;
 950         }
 951         *pba_num = (u32)(nvm_data << 16);
 952
 953         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
 954         if (ret_val) {
 955                 DEBUGOUT("NVM Read Error\n");
 956                 return ret_val;
 957         }
 958         *pba_num |= nvm_data;
 959
 960         return E1000_SUCCESS;
 961 }
 962
 963 /**
 964  *  e1000_read_pba_raw
 965  *  @hw: pointer to the HW structure
 966  *  @eeprom_buf: optional pointer to EEPROM image
 967  *  @eeprom_buf_size: size of EEPROM image in words
 968  *  @max_pba_block_size: PBA block size limit
 969  *  @pba: pointer to output PBA structure
 970  *
 971  *  Reads PBA from EEPROM image when eeprom_buf is not NULL.
 972  *  Reads PBA from physical EEPROM device when eeprom_buf is NULL.
 973  *
 974  **/
 975 s32 e1000_read_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
 976                        u32 eeprom_buf_size, u16 max_pba_block_size,
 977                        struct e1000_pba *pba)
 978 {
 979         s32 ret_val;
 980         u16 pba_block_size;
 981
 982         if (pba == NULL)
 983                 return -E1000_ERR_PARAM;
 984
 985         if (eeprom_buf == NULL) {
 986                 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2,
 987                                          &pba->word[0]);
 988                 if (ret_val)
 989                         return ret_val;
 990         } else {
 991                 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
 992                         pba->word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
 993                         pba->word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
 994                 } else {
 995                         return -E1000_ERR_PARAM;
 996                 }
 997         }
 998
 999         if (pba->word[0] == NVM_PBA_PTR_GUARD) {
1000                 if (pba->pba_block == NULL)
1001                         return -E1000_ERR_PARAM;
1002
1003                 ret_val = e1000_get_pba_block_size(hw, eeprom_buf,
1004                                                    eeprom_buf_size,
1005                                                    &pba_block_size);
1006                 if (ret_val)
1007                         return ret_val;
1008
1009                 if (pba_block_size > max_pba_block_size)
1010                         return -E1000_ERR_PARAM;
1011
1012                 if (eeprom_buf == NULL) {
1013                         ret_val = e1000_read_nvm(hw, pba->word[1],
1014                                                  pba_block_size,
1015                                                  pba->pba_block);
1016                         if (ret_val)
1017                                 return ret_val;
1018                 } else {
1019                         if (eeprom_buf_size > (u32)(pba->word[1] +
1020                                               pba->pba_block[0])) {
1021                                 memcpy(pba->pba_block,
1022                                        &eeprom_buf[pba->word[1]],
1023                                        pba_block_size * sizeof(u16));
1024                         } else {
1025                                 return -E1000_ERR_PARAM;
1026                         }
1027                 }
1028         }
1029
1030         return E1000_SUCCESS;
1031 }
1032
1033 /**
1034  *  e1000_write_pba_raw
1035  *  @hw: pointer to the HW structure
1036  *  @eeprom_buf: optional pointer to EEPROM image
1037  *  @eeprom_buf_size: size of EEPROM image in words
1038  *  @pba: pointer to PBA structure
1039  *
1040  *  Writes PBA to EEPROM image when eeprom_buf is not NULL.
1041  *  Writes PBA to physical EEPROM device when eeprom_buf is NULL.
1042  *
1043  **/
1044 s32 e1000_write_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
1045                         u32 eeprom_buf_size, struct e1000_pba *pba)
1046 {
1047         s32 ret_val;
1048
1049         if (pba == NULL)
1050                 return -E1000_ERR_PARAM;
1051
1052         if (eeprom_buf == NULL) {
1053                 ret_val = e1000_write_nvm(hw, NVM_PBA_OFFSET_0, 2,
1054                                           &pba->word[0]);
1055                 if (ret_val)
1056                         return ret_val;
1057         } else {
1058                 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1059                         eeprom_buf[NVM_PBA_OFFSET_0] = pba->word[0];
1060                         eeprom_buf[NVM_PBA_OFFSET_1] = pba->word[1];
1061                 } else {
1062                         return -E1000_ERR_PARAM;
1063                 }
1064         }
1065
1066         if (pba->word[0] == NVM_PBA_PTR_GUARD) {
1067                 if (pba->pba_block == NULL)
1068                         return -E1000_ERR_PARAM;
1069
1070                 if (eeprom_buf == NULL) {
1071                         ret_val = e1000_write_nvm(hw, pba->word[1],
1072                                                   pba->pba_block[0],
1073                                                   pba->pba_block);
1074                         if (ret_val)
1075                                 return ret_val;
1076                 } else {
1077                         if (eeprom_buf_size > (u32)(pba->word[1] +
1078                                               pba->pba_block[0])) {
1079                                 memcpy(&eeprom_buf[pba->word[1]],
1080                                        pba->pba_block,
1081                                        pba->pba_block[0] * sizeof(u16));
1082                         } else {
1083                                 return -E1000_ERR_PARAM;
1084                         }
1085                 }
1086         }
1087
1088         return E1000_SUCCESS;
1089 }
1090
1091 /**
1092  *  e1000_get_pba_block_size
1093  *  @hw: pointer to the HW structure
1094  *  @eeprom_buf: optional pointer to EEPROM image
1095  *  @eeprom_buf_size: size of EEPROM image in words
1096  *  @pba_data_size: pointer to output variable
1097  *
1098  *  Returns the size of the PBA block in words. Function operates on EEPROM
1099  *  image if the eeprom_buf pointer is not NULL otherwise it accesses physical
1100  *  EEPROM device.
1101  *
1102  **/
1103 s32 e1000_get_pba_block_size(struct e1000_hw *hw, u16 *eeprom_buf,
1104                              u32 eeprom_buf_size, u16 *pba_block_size)
1105 {
1106         s32 ret_val;
1107         u16 pba_word[2];
1108         u16 length;
1109
1110         DEBUGFUNC("e1000_get_pba_block_size");
1111
1112         if (eeprom_buf == NULL) {
1113                 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, &pba_word[0]);
1114                 if (ret_val)
1115                         return ret_val;
1116         } else {
1117                 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1118                         pba_word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
1119                         pba_word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
1120                 } else {
1121                         return -E1000_ERR_PARAM;
1122                 }
1123         }
1124
1125         if (pba_word[0] == NVM_PBA_PTR_GUARD) {
1126                 if (eeprom_buf == NULL) {
1127                         ret_val = e1000_read_nvm(hw, pba_word[1] + 0, 1,
1128                                                  &length);
1129                         if (ret_val)
1130                                 return ret_val;
1131                 } else {
1132                         if (eeprom_buf_size > pba_word[1])
1133                                 length = eeprom_buf[pba_word[1] + 0];
1134                         else
1135                                 return -E1000_ERR_PARAM;
1136                 }
1137
1138                 if (length == 0xFFFF || length == 0)
1139                         return -E1000_ERR_NVM_PBA_SECTION;
1140         } else {
1141                 /* PBA number in legacy format, there is no PBA Block. */
1142                 length = 0;
1143         }
1144
1145         if (pba_block_size != NULL)
1146                 *pba_block_size = length;
1147
1148         return E1000_SUCCESS;
1149 }
1150
1151 /**
1152  *  e1000_read_mac_addr_generic - Read device MAC address
1153  *  @hw: pointer to the HW structure
1154  *
1155  *  Reads the device MAC address from the EEPROM and stores the value.
1156  *  Since devices with two ports use the same EEPROM, we increment the
1157  *  last bit in the MAC address for the second port.
1158  **/
1159 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
1160 {
1161         u32 rar_high;
1162         u32 rar_low;
1163         u16 i;
1164
1165         rar_high = E1000_READ_REG(hw, E1000_RAH(0));
1166         rar_low = E1000_READ_REG(hw, E1000_RAL(0));
1167
1168         for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
1169                 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
1170
1171         for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
1172                 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
1173
1174         for (i = 0; i < ETH_ADDR_LEN; i++)
1175                 hw->mac.addr[i] = hw->mac.perm_addr[i];
1176
1177         return E1000_SUCCESS;
1178 }
1179
1180 /**
1181  *  e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
1182  *  @hw: pointer to the HW structure
1183  *
1184  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
1185  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
1186  **/
1187 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
1188 {
1189         s32 ret_val;
1190         u16 checksum = 0;
1191         u16 i, nvm_data;
1192
1193         DEBUGFUNC("e1000_validate_nvm_checksum_generic");
1194
1195         for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1196                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1197                 if (ret_val) {
1198                         DEBUGOUT("NVM Read Error\n");
1199                         return ret_val;
1200                 }
1201                 checksum += nvm_data;
1202         }
1203
1204         if (checksum != (u16) NVM_SUM) {
1205                 DEBUGOUT("NVM Checksum Invalid\n");
1206                 return -E1000_ERR_NVM;
1207         }
1208
1209         return E1000_SUCCESS;
1210 }
1211
1212 /**
1213  *  e1000_update_nvm_checksum_generic - Update EEPROM checksum
1214  *  @hw: pointer to the HW structure
1215  *
1216  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
1217  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
1218  *  value to the EEPROM.
1219  **/
1220 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
1221 {
1222         s32 ret_val;
1223         u16 checksum = 0;
1224         u16 i, nvm_data;
1225
1226         DEBUGFUNC("e1000_update_nvm_checksum");
1227
1228         for (i = 0; i < NVM_CHECKSUM_REG; i++) {
1229                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1230                 if (ret_val) {
1231                         DEBUGOUT("NVM Read Error while updating checksum.\n");
1232                         return ret_val;
1233                 }
1234                 checksum += nvm_data;
1235         }
1236         checksum = (u16) NVM_SUM - checksum;
1237         ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
1238         if (ret_val)
1239                 DEBUGOUT("NVM Write Error while updating checksum.\n");
1240
1241         return ret_val;
1242 }
1243
1244 /**
1245  *  e1000_reload_nvm_generic - Reloads EEPROM
1246  *  @hw: pointer to the HW structure
1247  *
1248  *  Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
1249  *  extended control register.
1250  **/
1251 static void e1000_reload_nvm_generic(struct e1000_hw *hw)
1252 {
1253         u32 ctrl_ext;
1254
1255         DEBUGFUNC("e1000_reload_nvm_generic");
1256
1257         usec_delay(10);
1258         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1259         ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1260         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1261         E1000_WRITE_FLUSH(hw);
1262 }
1263
1264 /**
1265  *  e1000_get_fw_version - Get firmware version information
1266  *  @hw: pointer to the HW structure
1267  *  @fw_vers: pointer to output version structure
1268  *
1269  *  unsupported/not present features return 0 in version structure
1270  **/
1271 void e1000_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers)
1272 {
1273         u16 eeprom_verh, eeprom_verl, etrack_test, fw_version;
1274         u8 q, hval, rem, result;
1275         u16 comb_verh, comb_verl, comb_offset;
1276
1277         memset(fw_vers, 0, sizeof(struct e1000_fw_version));
1278
1279         /* basic eeprom version numbers, bits used vary by part and by tool
1280          * used to create the nvm images */
1281         /* Check which data format we have */
1282         hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
1283         switch (hw->mac.type) {
1284         case e1000_i211:
1285                 e1000_read_invm_version(hw, fw_vers);
1286                 return;
1287         case e1000_82575:
1288         case e1000_82576:
1289         case e1000_82580:
1290                 /* Use this format, unless EETRACK ID exists,
1291                  * then use alternate format
1292                  */
1293                 if ((etrack_test &  NVM_MAJOR_MASK) != NVM_ETRACK_VALID) {
1294                         hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
1295                         fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
1296                                               >> NVM_MAJOR_SHIFT;
1297                         fw_vers->eep_minor = (fw_version & NVM_MINOR_MASK)
1298                                               >> NVM_MINOR_SHIFT;
1299                         fw_vers->eep_build = (fw_version & NVM_IMAGE_ID_MASK);
1300                         goto etrack_id;
1301                 }
1302                 break;
1303         case e1000_i210:
1304         case e1000_i350:
1305                 /* find combo image version */
1306                 hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset);
1307                 if ((comb_offset != 0x0) &&
1308                     (comb_offset != NVM_VER_INVALID)) {
1309
1310                         hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset
1311                                          + 1), 1, &comb_verh);
1312                         hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset),
1313                                          1, &comb_verl);
1314
1315                         /* get Option Rom version if it exists and is valid */
1316                         if ((comb_verh && comb_verl) &&
1317                             ((comb_verh != NVM_VER_INVALID) &&
1318                              (comb_verl != NVM_VER_INVALID))) {
1319
1320                                 fw_vers->or_valid = TRUE;
1321                                 fw_vers->or_major =
1322                                         comb_verl >> NVM_COMB_VER_SHFT;
1323                                 fw_vers->or_build =
1324                                         (comb_verl << NVM_COMB_VER_SHFT)
1325                                         | (comb_verh >> NVM_COMB_VER_SHFT);
1326                                 fw_vers->or_patch =
1327                                         comb_verh & NVM_COMB_VER_MASK;
1328                         }
1329                 }
1330                 break;
1331         default:
1332                 return;
1333         }
1334         hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
1335         fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
1336                               >> NVM_MAJOR_SHIFT;
1337
1338         /* check for old style version format in newer images*/
1339         if ((fw_version & NVM_NEW_DEC_MASK) == 0x0) {
1340                 eeprom_verl = (fw_version & NVM_COMB_VER_MASK);
1341         } else {
1342                 eeprom_verl = (fw_version & NVM_MINOR_MASK)
1343                                 >> NVM_MINOR_SHIFT;
1344         }
1345         /* Convert minor value to hex before assigning to output struct
1346          * Val to be converted will not be higher than 99, per tool output
1347          */
1348         q = eeprom_verl / NVM_HEX_CONV;
1349         hval = q * NVM_HEX_TENS;
1350         rem = eeprom_verl % NVM_HEX_CONV;
1351         result = hval + rem;
1352         fw_vers->eep_minor = result;
1353
1354 etrack_id:
1355         if ((etrack_test &  NVM_MAJOR_MASK) == NVM_ETRACK_VALID) {
1356                 hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl);
1357                 hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh);
1358                 fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT)
1359                         | eeprom_verl;
1360         }
1361         return;
1362 }
1363
1364