2 * Copyright (c) 1997, Stefan Esser <se@kfreebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@kfreebsd.org>
4 * Copyright (c) 2000, BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/pci/pci.c,v 1.355.2.9.2.1 2009/04/15 03:14:26 kensmith Exp $
33 #include "opt_compat_oldpci.h"
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/malloc.h>
38 #include <sys/module.h>
39 #include <sys/linker.h>
40 #include <sys/fcntl.h>
42 #include <sys/kernel.h>
43 #include <sys/queue.h>
44 #include <sys/sysctl.h>
45 #include <sys/endian.h>
46 #include <sys/machintr.h>
48 #include <machine/msi_machdep.h>
52 #include <vm/vm_extern.h>
56 #include <sys/device.h>
58 #include <sys/pciio.h>
59 #include <bus/pci/pcireg.h>
60 #include <bus/pci/pcivar.h>
61 #include <bus/pci/pci_private.h>
67 #include <contrib/dev/acpica/acpi.h>
70 #define ACPI_PWR_FOR_SLEEP(x, y, z)
73 extern struct dev_ops pcic_ops; /* XXX */
75 typedef void (*pci_read_cap_t)(device_t, int, int, pcicfgregs *);
77 static uint32_t pci_mapbase(unsigned mapreg);
78 static const char *pci_maptype(unsigned mapreg);
79 static int pci_mapsize(unsigned testval);
80 static int pci_maprange(unsigned mapreg);
81 static void pci_fixancient(pcicfgregs *cfg);
83 static int pci_porten(device_t pcib, int b, int s, int f);
84 static int pci_memen(device_t pcib, int b, int s, int f);
85 static void pci_assign_interrupt(device_t bus, device_t dev,
87 static int pci_add_map(device_t pcib, device_t bus, device_t dev,
88 int b, int s, int f, int reg,
89 struct resource_list *rl, int force, int prefetch);
90 static int pci_probe(device_t dev);
91 static int pci_attach(device_t dev);
92 static void pci_child_detached(device_t, device_t);
93 static void pci_load_vendor_data(void);
94 static int pci_describe_parse_line(char **ptr, int *vendor,
95 int *device, char **desc);
96 static char *pci_describe_device(device_t dev);
97 static int pci_modevent(module_t mod, int what, void *arg);
98 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
100 static void pci_read_capabilities(device_t pcib, pcicfgregs *cfg);
101 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
102 int reg, uint32_t *data);
104 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
105 int reg, uint32_t data);
107 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
108 static void pci_disable_msi(device_t dev);
109 static void pci_enable_msi(device_t dev, uint64_t address,
111 static void pci_setup_msix_vector(device_t dev, u_int index,
112 uint64_t address, uint32_t data);
113 static void pci_mask_msix_vector(device_t dev, u_int index);
114 static void pci_unmask_msix_vector(device_t dev, u_int index);
115 static void pci_mask_msix_allvectors(device_t dev);
116 static int pci_msi_blacklisted(void);
117 static void pci_resume_msi(device_t dev);
118 static void pci_resume_msix(device_t dev);
119 static int pcie_slotimpl(const pcicfgregs *);
120 static void pci_print_verbose_expr(const pcicfgregs *);
122 static void pci_read_cap_pmgt(device_t, int, int, pcicfgregs *);
123 static void pci_read_cap_ht(device_t, int, int, pcicfgregs *);
124 static void pci_read_cap_msi(device_t, int, int, pcicfgregs *);
125 static void pci_read_cap_msix(device_t, int, int, pcicfgregs *);
126 static void pci_read_cap_vpd(device_t, int, int, pcicfgregs *);
127 static void pci_read_cap_subvendor(device_t, int, int,
129 static void pci_read_cap_pcix(device_t, int, int, pcicfgregs *);
130 static void pci_read_cap_express(device_t, int, int, pcicfgregs *);
132 static device_method_t pci_methods[] = {
133 /* Device interface */
134 DEVMETHOD(device_probe, pci_probe),
135 DEVMETHOD(device_attach, pci_attach),
136 DEVMETHOD(device_detach, bus_generic_detach),
137 DEVMETHOD(device_shutdown, bus_generic_shutdown),
138 DEVMETHOD(device_suspend, pci_suspend),
139 DEVMETHOD(device_resume, pci_resume),
142 DEVMETHOD(bus_print_child, pci_print_child),
143 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
144 DEVMETHOD(bus_read_ivar, pci_read_ivar),
145 DEVMETHOD(bus_write_ivar, pci_write_ivar),
146 DEVMETHOD(bus_driver_added, pci_driver_added),
147 DEVMETHOD(bus_child_detached, pci_child_detached),
148 DEVMETHOD(bus_setup_intr, pci_setup_intr),
149 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
151 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
152 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
153 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
154 DEVMETHOD(bus_delete_resource, pci_delete_resource),
155 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
156 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
157 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
158 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
159 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
160 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
163 DEVMETHOD(pci_read_config, pci_read_config_method),
164 DEVMETHOD(pci_write_config, pci_write_config_method),
165 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
166 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
167 DEVMETHOD(pci_enable_io, pci_enable_io_method),
168 DEVMETHOD(pci_disable_io, pci_disable_io_method),
169 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
170 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
171 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
172 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
173 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
174 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
175 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
176 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method),
177 DEVMETHOD(pci_release_msi, pci_release_msi_method),
178 DEVMETHOD(pci_msi_count, pci_msi_count_method),
179 DEVMETHOD(pci_msix_count, pci_msix_count_method),
184 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0);
186 static devclass_t pci_devclass;
187 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, NULL);
188 MODULE_VERSION(pci, 1);
190 static char *pci_vendordata;
191 static size_t pci_vendordata_size;
194 static const struct pci_read_cap {
196 pci_read_cap_t read_cap;
197 } pci_read_caps[] = {
198 { PCIY_PMG, pci_read_cap_pmgt },
199 { PCIY_HT, pci_read_cap_ht },
200 { PCIY_MSI, pci_read_cap_msi },
201 { PCIY_MSIX, pci_read_cap_msix },
202 { PCIY_VPD, pci_read_cap_vpd },
203 { PCIY_SUBVENDOR, pci_read_cap_subvendor },
204 { PCIY_PCIX, pci_read_cap_pcix },
205 { PCIY_EXPRESS, pci_read_cap_express },
206 { 0, NULL } /* required last entry */
210 uint32_t devid; /* Vendor/device of the card */
212 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
213 #define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */
218 struct pci_quirk pci_quirks[] = {
219 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
220 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
221 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
222 /* As does the Serverworks OSB4 (the SMBus mapping register) */
223 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
226 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
227 * or the CMIC-SL (AKA ServerWorks GC_LE).
229 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
230 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
233 * MSI doesn't work on earlier Intel chipsets including
234 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
236 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
237 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
238 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
239 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
240 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
241 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
242 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
245 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
248 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
253 /* map register information */
254 #define PCI_MAPMEM 0x01 /* memory map */
255 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
256 #define PCI_MAPPORT 0x04 /* port map */
258 struct devlist pci_devq;
259 uint32_t pci_generation;
260 uint32_t pci_numdevs = 0;
261 static int pcie_chipset, pcix_chipset;
264 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
266 static int pci_enable_io_modes = 1;
267 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
268 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
269 &pci_enable_io_modes, 1,
270 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
271 enable these bits correctly. We'd like to do this all the time, but there\n\
272 are some peripherals that this causes problems with.");
274 static int pci_do_power_nodriver = 0;
275 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
276 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
277 &pci_do_power_nodriver, 0,
278 "Place a function into D3 state when no driver attaches to it. 0 means\n\
279 disable. 1 means conservatively place devices into D3 state. 2 means\n\
280 aggressively place devices into D3 state. 3 means put absolutely everything\n\
283 static int pci_do_power_resume = 1;
284 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
285 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
286 &pci_do_power_resume, 1,
287 "Transition from D3 -> D0 on resume.");
289 static int pci_do_msi = 1;
290 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
291 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
292 "Enable support for MSI interrupts");
294 static int pci_do_msix = 0;
296 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
297 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
298 "Enable support for MSI-X interrupts");
301 static int pci_honor_msi_blacklist = 1;
302 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
303 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
304 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI");
306 static int pci_msi_cpuid;
308 /* Find a device_t by bus/slot/function in domain 0 */
311 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
314 return (pci_find_dbsf(0, bus, slot, func));
317 /* Find a device_t by domain/bus/slot/function */
320 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
322 struct pci_devinfo *dinfo;
324 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
325 if ((dinfo->cfg.domain == domain) &&
326 (dinfo->cfg.bus == bus) &&
327 (dinfo->cfg.slot == slot) &&
328 (dinfo->cfg.func == func)) {
329 return (dinfo->cfg.dev);
336 /* Find a device_t by vendor/device ID */
339 pci_find_device(uint16_t vendor, uint16_t device)
341 struct pci_devinfo *dinfo;
343 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
344 if ((dinfo->cfg.vendor == vendor) &&
345 (dinfo->cfg.device == device)) {
346 return (dinfo->cfg.dev);
353 /* return base address of memory or port map */
356 pci_mapbase(uint32_t mapreg)
359 if (PCI_BAR_MEM(mapreg))
360 return (mapreg & PCIM_BAR_MEM_BASE);
362 return (mapreg & PCIM_BAR_IO_BASE);
365 /* return map type of memory or port map */
368 pci_maptype(unsigned mapreg)
371 if (PCI_BAR_IO(mapreg))
373 if (mapreg & PCIM_BAR_MEM_PREFETCH)
374 return ("Prefetchable Memory");
378 /* return log2 of map size decoded for memory or port map */
381 pci_mapsize(uint32_t testval)
385 testval = pci_mapbase(testval);
388 while ((testval & 1) == 0)
397 /* return log2 of address range supported by map register */
400 pci_maprange(unsigned mapreg)
404 if (PCI_BAR_IO(mapreg))
407 switch (mapreg & PCIM_BAR_MEM_TYPE) {
408 case PCIM_BAR_MEM_32:
411 case PCIM_BAR_MEM_1MB:
414 case PCIM_BAR_MEM_64:
421 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
424 pci_fixancient(pcicfgregs *cfg)
426 if (cfg->hdrtype != 0)
429 /* PCI to PCI bridges use header type 1 */
430 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
434 /* extract header type specific config data */
437 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
439 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
440 switch (cfg->hdrtype) {
442 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
443 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
444 cfg->nummaps = PCI_MAXMAPS_0;
447 cfg->nummaps = PCI_MAXMAPS_1;
449 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
453 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
454 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
455 cfg->nummaps = PCI_MAXMAPS_2;
457 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
464 /* read configuration header into pcicfgregs structure */
466 pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
468 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
469 pcicfgregs *cfg = NULL;
470 struct pci_devinfo *devlist_entry;
471 struct devlist *devlist_head;
473 devlist_head = &pci_devq;
475 devlist_entry = NULL;
477 if (REG(PCIR_DEVVENDOR, 4) != -1) {
478 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
480 cfg = &devlist_entry->cfg;
486 cfg->vendor = REG(PCIR_VENDOR, 2);
487 cfg->device = REG(PCIR_DEVICE, 2);
488 cfg->cmdreg = REG(PCIR_COMMAND, 2);
489 cfg->statreg = REG(PCIR_STATUS, 2);
490 cfg->baseclass = REG(PCIR_CLASS, 1);
491 cfg->subclass = REG(PCIR_SUBCLASS, 1);
492 cfg->progif = REG(PCIR_PROGIF, 1);
493 cfg->revid = REG(PCIR_REVID, 1);
494 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
495 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
496 cfg->lattimer = REG(PCIR_LATTIMER, 1);
497 cfg->intpin = REG(PCIR_INTPIN, 1);
498 cfg->intline = REG(PCIR_INTLINE, 1);
500 cfg->mingnt = REG(PCIR_MINGNT, 1);
501 cfg->maxlat = REG(PCIR_MAXLAT, 1);
503 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
504 cfg->hdrtype &= ~PCIM_MFDEV;
507 pci_hdrtypedata(pcib, b, s, f, cfg);
509 pci_read_capabilities(pcib, cfg);
511 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
513 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
514 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
515 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
516 devlist_entry->conf.pc_sel.pc_func = cfg->func;
517 devlist_entry->conf.pc_hdr = cfg->hdrtype;
519 devlist_entry->conf.pc_subvendor = cfg->subvendor;
520 devlist_entry->conf.pc_subdevice = cfg->subdevice;
521 devlist_entry->conf.pc_vendor = cfg->vendor;
522 devlist_entry->conf.pc_device = cfg->device;
524 devlist_entry->conf.pc_class = cfg->baseclass;
525 devlist_entry->conf.pc_subclass = cfg->subclass;
526 devlist_entry->conf.pc_progif = cfg->progif;
527 devlist_entry->conf.pc_revid = cfg->revid;
532 return (devlist_entry);
537 pci_fixup_nextptr(int *nextptr0)
539 int nextptr = *nextptr0;
541 /* "Next pointer" is only one byte */
542 KASSERT(nextptr <= 0xff, ("Illegal next pointer %d\n", nextptr));
546 * PCI local bus spec 3.0:
548 * "... The bottom two bits of all pointers are reserved
549 * and must be implemented as 00b although software must
550 * mask them to allow for future uses of these bits ..."
553 kprintf("Illegal PCI extended capability "
554 "offset, fixup 0x%02x -> 0x%02x\n",
555 nextptr, nextptr & ~0x3);
561 if (nextptr < 0x40) {
563 kprintf("Illegal PCI extended capability "
564 "offset 0x%02x", nextptr);
572 pci_read_cap_pmgt(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
575 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
577 struct pcicfg_pp *pp = &cfg->pp;
582 pp->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
583 pp->pp_status = ptr + PCIR_POWER_STATUS;
584 pp->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
586 if ((nextptr - ptr) > PCIR_POWER_DATA) {
589 * We should write to data_select and read back from
590 * data_scale to determine whether data register is
594 pp->pp_data = ptr + PCIR_POWER_DATA;
604 pci_read_cap_ht(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
606 #if defined(__i386__) || defined(__x86_64__)
609 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
611 struct pcicfg_ht *ht = &cfg->ht;
615 /* Determine HT-specific capability type. */
616 val = REG(ptr + PCIR_HT_COMMAND, 2);
618 if ((val & 0xe000) == PCIM_HTCAP_SLAVE)
619 cfg->ht.ht_slave = ptr;
621 if ((val & PCIM_HTCMD_CAP_MASK) != PCIM_HTCAP_MSI_MAPPING)
624 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
625 /* Sanity check the mapping window. */
626 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 4);
628 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 4);
629 if (addr != MSI_X86_ADDR_BASE) {
630 device_printf(pcib, "HT Bridge at pci%d:%d:%d:%d "
631 "has non-default MSI window 0x%llx\n",
632 cfg->domain, cfg->bus, cfg->slot, cfg->func,
636 addr = MSI_X86_ADDR_BASE;
640 ht->ht_msictrl = val;
641 ht->ht_msiaddr = addr;
645 #endif /* __i386__ || __x86_64__ */
649 pci_read_cap_msi(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
652 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
654 struct pcicfg_msi *msi = &cfg->msi;
656 msi->msi_location = ptr;
657 msi->msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
658 msi->msi_msgnum = 1 << ((msi->msi_ctrl & PCIM_MSICTRL_MMC_MASK) >> 1);
664 pci_read_cap_msix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
667 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
669 struct pcicfg_msix *msix = &cfg->msix;
672 msix->msix_location = ptr;
673 msix->msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
674 msix->msix_msgnum = (msix->msix_ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
676 val = REG(ptr + PCIR_MSIX_TABLE, 4);
677 msix->msix_table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
678 msix->msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
680 val = REG(ptr + PCIR_MSIX_PBA, 4);
681 msix->msix_pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
682 msix->msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
688 pci_read_cap_vpd(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
690 cfg->vpd.vpd_reg = ptr;
694 pci_read_cap_subvendor(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
697 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
699 /* Should always be true. */
700 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) {
703 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
704 cfg->subvendor = val & 0xffff;
705 cfg->subdevice = val >> 16;
712 pci_read_cap_pcix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
715 * Assume we have a PCI-X chipset if we have
716 * at least one PCI-PCI bridge with a PCI-X
717 * capability. Note that some systems with
718 * PCI-express or HT chipsets might match on
719 * this check as well.
721 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1)
724 cfg->pcix.pcix_ptr = ptr;
728 pcie_slotimpl(const pcicfgregs *cfg)
730 const struct pcicfg_expr *expr = &cfg->expr;
734 * Only version 1 can be parsed currently
736 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
740 * - Slot implemented bit is meaningful iff current port is
741 * root port or down stream port.
742 * - Testing for root port or down stream port is meanningful
743 * iff PCI configure has type 1 header.
746 if (cfg->hdrtype != 1)
749 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
750 if (port_type != PCIE_ROOT_PORT && port_type != PCIE_DOWN_STREAM_PORT)
753 if (!(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
760 pci_read_cap_express(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
763 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
765 struct pcicfg_expr *expr = &cfg->expr;
768 * Assume we have a PCI-express chipset if we have
769 * at least one PCI-express device.
773 expr->expr_ptr = ptr;
774 expr->expr_cap = REG(ptr + PCIER_CAPABILITY, 2);
777 * Only version 1 can be parsed currently
779 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
783 * Read slot capabilities. Slot capabilities exists iff
784 * current port's slot is implemented
786 if (pcie_slotimpl(cfg))
787 expr->expr_slotcap = REG(ptr + PCIER_SLOTCAP, 4);
793 pci_read_capabilities(device_t pcib, pcicfgregs *cfg)
795 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
796 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
801 if ((REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) == 0) {
802 /* No capabilities */
806 switch (cfg->hdrtype & PCIM_HDRTYPE) {
809 ptrptr = PCIR_CAP_PTR;
812 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
815 return; /* no capabilities support */
817 nextptr = REG(ptrptr, 1); /* sanity check? */
820 * Read capability entries.
822 while (pci_fixup_nextptr(&nextptr)) {
823 const struct pci_read_cap *rc;
826 /* Find the next entry */
827 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
829 /* Process this entry */
830 val = REG(ptr + PCICAP_ID, 1);
831 for (rc = pci_read_caps; rc->read_cap != NULL; ++rc) {
832 if (rc->cap == val) {
833 rc->read_cap(pcib, ptr, nextptr, cfg);
839 #if defined(__i386__) || defined(__x86_64__)
841 * Enable the MSI mapping window for all HyperTransport
842 * slaves. PCI-PCI bridges have their windows enabled via
845 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 &&
846 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) {
848 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n",
849 cfg->domain, cfg->bus, cfg->slot, cfg->func);
850 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
851 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl,
856 /* REG and WREG use carry through to next functions */
860 * PCI Vital Product Data
863 #define PCI_VPD_TIMEOUT 1000000
866 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
868 int count = PCI_VPD_TIMEOUT;
870 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
872 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
874 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
877 DELAY(1); /* limit looping */
879 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
886 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
888 int count = PCI_VPD_TIMEOUT;
890 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
892 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
893 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
894 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
897 DELAY(1); /* limit looping */
904 #undef PCI_VPD_TIMEOUT
906 struct vpd_readstate {
916 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
921 if (vrs->bytesinval == 0) {
922 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
924 vrs->val = le32toh(reg);
926 byte = vrs->val & 0xff;
929 vrs->val = vrs->val >> 8;
930 byte = vrs->val & 0xff;
940 pcie_slot_implemented(device_t dev)
942 struct pci_devinfo *dinfo = device_get_ivars(dev);
944 return pcie_slotimpl(&dinfo->cfg);
948 pcie_set_max_readrq(device_t dev, uint16_t rqsize)
953 rqsize &= PCIEM_DEVCTL_MAX_READRQ_MASK;
954 if (rqsize > PCIEM_DEVCTL_MAX_READRQ_4096) {
955 panic("%s: invalid max read request size 0x%02x\n",
956 device_get_nameunit(dev), rqsize);
959 expr_ptr = pci_get_pciecap_ptr(dev);
961 panic("%s: not PCIe device\n", device_get_nameunit(dev));
963 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
964 if ((val & PCIEM_DEVCTL_MAX_READRQ_MASK) != rqsize) {
966 device_printf(dev, "adjust device control 0x%04x", val);
968 val &= ~PCIEM_DEVCTL_MAX_READRQ_MASK;
970 pci_write_config(dev, expr_ptr + PCIER_DEVCTRL, val, 2);
973 kprintf(" -> 0x%04x\n", val);
978 pcie_get_max_readrq(device_t dev)
983 expr_ptr = pci_get_pciecap_ptr(dev);
985 panic("%s: not PCIe device\n", device_get_nameunit(dev));
987 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
988 return (val & PCIEM_DEVCTL_MAX_READRQ_MASK);
992 pci_read_vpd(device_t pcib, pcicfgregs *cfg)
994 struct vpd_readstate vrs;
999 int alloc, off; /* alloc/off for RO/W arrays */
1005 /* init vpd reader */
1013 name = remain = i = 0; /* shut up stupid gcc */
1014 alloc = off = 0; /* shut up stupid gcc */
1015 dflen = 0; /* shut up stupid gcc */
1017 while (state >= 0) {
1018 if (vpd_nextbyte(&vrs, &byte)) {
1023 kprintf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
1024 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
1025 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
1028 case 0: /* item name */
1030 if (vpd_nextbyte(&vrs, &byte2)) {
1035 if (vpd_nextbyte(&vrs, &byte2)) {
1039 remain |= byte2 << 8;
1040 if (remain > (0x7f*4 - vrs.off)) {
1043 "pci%d:%d:%d:%d: invalid VPD data, remain %#x\n",
1044 cfg->domain, cfg->bus, cfg->slot,
1049 remain = byte & 0x7;
1050 name = (byte >> 3) & 0xf;
1053 case 0x2: /* String */
1054 cfg->vpd.vpd_ident = kmalloc(remain + 1,
1055 M_DEVBUF, M_WAITOK);
1062 case 0x10: /* VPD-R */
1065 cfg->vpd.vpd_ros = kmalloc(alloc *
1066 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
1070 case 0x11: /* VPD-W */
1073 cfg->vpd.vpd_w = kmalloc(alloc *
1074 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
1078 default: /* Invalid data, abort */
1084 case 1: /* Identifier String */
1085 cfg->vpd.vpd_ident[i++] = byte;
1088 cfg->vpd.vpd_ident[i] = '\0';
1093 case 2: /* VPD-R Keyword Header */
1095 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
1096 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
1097 M_DEVBUF, M_WAITOK | M_ZERO);
1099 cfg->vpd.vpd_ros[off].keyword[0] = byte;
1100 if (vpd_nextbyte(&vrs, &byte2)) {
1104 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
1105 if (vpd_nextbyte(&vrs, &byte2)) {
1111 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
1114 * if this happens, we can't trust the rest
1118 "pci%d:%d:%d:%d: bad keyword length: %d\n",
1119 cfg->domain, cfg->bus, cfg->slot,
1124 } else if (dflen == 0) {
1125 cfg->vpd.vpd_ros[off].value = kmalloc(1 *
1126 sizeof(*cfg->vpd.vpd_ros[off].value),
1127 M_DEVBUF, M_WAITOK);
1128 cfg->vpd.vpd_ros[off].value[0] = '\x00';
1130 cfg->vpd.vpd_ros[off].value = kmalloc(
1132 sizeof(*cfg->vpd.vpd_ros[off].value),
1133 M_DEVBUF, M_WAITOK);
1136 /* keep in sync w/ state 3's transistions */
1137 if (dflen == 0 && remain == 0)
1139 else if (dflen == 0)
1145 case 3: /* VPD-R Keyword Value */
1146 cfg->vpd.vpd_ros[off].value[i++] = byte;
1147 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
1148 "RV", 2) == 0 && cksumvalid == -1) {
1154 "pci%d:%d:%d:%d: bad VPD cksum, remain %hhu\n",
1155 cfg->domain, cfg->bus,
1156 cfg->slot, cfg->func,
1165 /* keep in sync w/ state 2's transistions */
1167 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
1168 if (dflen == 0 && remain == 0) {
1169 cfg->vpd.vpd_rocnt = off;
1170 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
1171 off * sizeof(*cfg->vpd.vpd_ros),
1172 M_DEVBUF, M_WAITOK | M_ZERO);
1174 } else if (dflen == 0)
1184 case 5: /* VPD-W Keyword Header */
1186 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
1187 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
1188 M_DEVBUF, M_WAITOK | M_ZERO);
1190 cfg->vpd.vpd_w[off].keyword[0] = byte;
1191 if (vpd_nextbyte(&vrs, &byte2)) {
1195 cfg->vpd.vpd_w[off].keyword[1] = byte2;
1196 if (vpd_nextbyte(&vrs, &byte2)) {
1200 cfg->vpd.vpd_w[off].len = dflen = byte2;
1201 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
1202 cfg->vpd.vpd_w[off].value = kmalloc((dflen + 1) *
1203 sizeof(*cfg->vpd.vpd_w[off].value),
1204 M_DEVBUF, M_WAITOK);
1207 /* keep in sync w/ state 6's transistions */
1208 if (dflen == 0 && remain == 0)
1210 else if (dflen == 0)
1216 case 6: /* VPD-W Keyword Value */
1217 cfg->vpd.vpd_w[off].value[i++] = byte;
1220 /* keep in sync w/ state 5's transistions */
1222 cfg->vpd.vpd_w[off++].value[i++] = '\0';
1223 if (dflen == 0 && remain == 0) {
1224 cfg->vpd.vpd_wcnt = off;
1225 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
1226 off * sizeof(*cfg->vpd.vpd_w),
1227 M_DEVBUF, M_WAITOK | M_ZERO);
1229 } else if (dflen == 0)
1234 kprintf("pci%d:%d:%d:%d: invalid state: %d\n",
1235 cfg->domain, cfg->bus, cfg->slot, cfg->func,
1242 if (cksumvalid == 0 || state < -1) {
1243 /* read-only data bad, clean up */
1244 if (cfg->vpd.vpd_ros != NULL) {
1245 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
1246 kfree(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
1247 kfree(cfg->vpd.vpd_ros, M_DEVBUF);
1248 cfg->vpd.vpd_ros = NULL;
1252 /* I/O error, clean up */
1253 kprintf("pci%d:%d:%d:%d: failed to read VPD data.\n",
1254 cfg->domain, cfg->bus, cfg->slot, cfg->func);
1255 if (cfg->vpd.vpd_ident != NULL) {
1256 kfree(cfg->vpd.vpd_ident, M_DEVBUF);
1257 cfg->vpd.vpd_ident = NULL;
1259 if (cfg->vpd.vpd_w != NULL) {
1260 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1261 kfree(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1262 kfree(cfg->vpd.vpd_w, M_DEVBUF);
1263 cfg->vpd.vpd_w = NULL;
1266 cfg->vpd.vpd_cached = 1;
1272 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1274 struct pci_devinfo *dinfo = device_get_ivars(child);
1275 pcicfgregs *cfg = &dinfo->cfg;
1277 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1278 pci_read_vpd(device_get_parent(dev), cfg);
1280 *identptr = cfg->vpd.vpd_ident;
1282 if (*identptr == NULL)
1289 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1292 struct pci_devinfo *dinfo = device_get_ivars(child);
1293 pcicfgregs *cfg = &dinfo->cfg;
1296 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1297 pci_read_vpd(device_get_parent(dev), cfg);
1299 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1300 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1301 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1302 *vptr = cfg->vpd.vpd_ros[i].value;
1305 if (i != cfg->vpd.vpd_rocnt)
1313 * Return the offset in configuration space of the requested extended
1314 * capability entry or 0 if the specified capability was not found.
1317 pci_find_extcap_method(device_t dev, device_t child, int capability,
1320 struct pci_devinfo *dinfo = device_get_ivars(child);
1321 pcicfgregs *cfg = &dinfo->cfg;
1326 * Check the CAP_LIST bit of the PCI status register first.
1328 status = pci_read_config(child, PCIR_STATUS, 2);
1329 if (!(status & PCIM_STATUS_CAPPRESENT))
1333 * Determine the start pointer of the capabilities list.
1335 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1341 ptr = PCIR_CAP_PTR_2;
1345 return (ENXIO); /* no extended capabilities support */
1347 ptr = pci_read_config(child, ptr, 1);
1350 * Traverse the capabilities list.
1353 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1358 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1365 * Support for MSI-X message interrupts.
1368 pci_setup_msix_vector(device_t dev, u_int index, uint64_t address,
1371 struct pci_devinfo *dinfo = device_get_ivars(dev);
1372 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1375 KASSERT(msix->msix_table_len > index, ("bogus index"));
1376 offset = msix->msix_table_offset + index * 16;
1377 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1378 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1379 bus_write_4(msix->msix_table_res, offset + 8, data);
1381 /* Enable MSI -> HT mapping. */
1382 pci_ht_map_msi(dev, address);
1386 pci_mask_msix_vector(device_t dev, u_int index)
1388 struct pci_devinfo *dinfo = device_get_ivars(dev);
1389 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1390 uint32_t offset, val;
1392 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1393 offset = msix->msix_table_offset + index * 16 + 12;
1394 val = bus_read_4(msix->msix_table_res, offset);
1395 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1396 val |= PCIM_MSIX_VCTRL_MASK;
1397 bus_write_4(msix->msix_table_res, offset, val);
1402 pci_unmask_msix_vector(device_t dev, u_int index)
1404 struct pci_devinfo *dinfo = device_get_ivars(dev);
1405 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1406 uint32_t offset, val;
1408 KASSERT(msix->msix_table_len > index, ("bogus index"));
1409 offset = msix->msix_table_offset + index * 16 + 12;
1410 val = bus_read_4(msix->msix_table_res, offset);
1411 if (val & PCIM_MSIX_VCTRL_MASK) {
1412 val &= ~PCIM_MSIX_VCTRL_MASK;
1413 bus_write_4(msix->msix_table_res, offset, val);
1418 pci_pending_msix_vector(device_t dev, u_int index)
1420 struct pci_devinfo *dinfo = device_get_ivars(dev);
1421 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1422 uint32_t offset, bit;
1424 KASSERT(msix->msix_table_res != NULL && msix->msix_pba_res != NULL,
1425 ("MSI-X is not setup yet\n"));
1427 KASSERT(msix->msix_table_len > index, ("bogus index"));
1428 offset = msix->msix_pba_offset + (index / 32) * 4;
1429 bit = 1 << index % 32;
1430 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1434 * Restore MSI-X registers and table during resume. If MSI-X is
1435 * enabled then walk the virtual table to restore the actual MSI-X
1439 pci_resume_msix(device_t dev)
1441 struct pci_devinfo *dinfo = device_get_ivars(dev);
1442 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1443 struct msix_table_entry *mte;
1444 struct msix_vector *mv;
1447 if (msix->msix_alloc > 0) {
1448 pci_mask_msix_allvectors(dev);
1450 /* Program any messages with at least one handler. */
1451 for (i = 0; i < msix->msix_table_len; i++) {
1452 mte = &msix->msix_table[i];
1453 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1455 mv = &msix->msix_vectors[mte->mte_vector - 1];
1456 pci_setup_msix_vector(dev, i, mv->mv_address,
1458 pci_unmask_msix_vector(dev, i);
1461 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1462 msix->msix_ctrl, 2);
1466 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1467 * returned in *count. After this function returns, each message will be
1468 * available to the driver as SYS_RES_IRQ resources starting at rid 1.
1471 pci_alloc_msix_method(device_t dev, device_t child, int *count)
1473 struct pci_devinfo *dinfo = device_get_ivars(child);
1474 pcicfgregs *cfg = &dinfo->cfg;
1475 struct resource_list_entry *rle;
1476 int actual, error, i, irq, max;
1478 /* Don't let count == 0 get us into trouble. */
1482 /* If rid 0 is allocated, then fail. */
1483 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1484 if (rle != NULL && rle->res != NULL)
1487 /* Already have allocated messages? */
1488 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1491 /* If MSI is blacklisted for this system, fail. */
1492 if (pci_msi_blacklisted())
1495 /* MSI-X capability present? */
1496 if (cfg->msix.msix_location == 0 || !pci_do_msix)
1499 /* Make sure the appropriate BARs are mapped. */
1500 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1501 cfg->msix.msix_table_bar);
1502 if (rle == NULL || rle->res == NULL ||
1503 !(rman_get_flags(rle->res) & RF_ACTIVE))
1505 cfg->msix.msix_table_res = rle->res;
1506 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1507 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1508 cfg->msix.msix_pba_bar);
1509 if (rle == NULL || rle->res == NULL ||
1510 !(rman_get_flags(rle->res) & RF_ACTIVE))
1513 cfg->msix.msix_pba_res = rle->res;
1516 device_printf(child,
1517 "attempting to allocate %d MSI-X vectors (%d supported)\n",
1518 *count, cfg->msix.msix_msgnum);
1519 max = min(*count, cfg->msix.msix_msgnum);
1520 for (i = 0; i < max; i++) {
1521 /* Allocate a message. */
1522 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq,
1526 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1533 device_printf(child,
1534 "could not allocate any MSI-X vectors\n");
1540 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
1542 device_printf(child, "using IRQ %lu for MSI-X\n",
1548 * Be fancy and try to print contiguous runs of
1549 * IRQ values as ranges. 'irq' is the previous IRQ.
1550 * 'run' is true if we are in a range.
1552 device_printf(child, "using IRQs %lu", rle->start);
1555 for (i = 1; i < actual; i++) {
1556 rle = resource_list_find(&dinfo->resources,
1557 SYS_RES_IRQ, i + 1);
1559 /* Still in a run? */
1560 if (rle->start == irq + 1) {
1566 /* Finish previous range. */
1568 kprintf("-%d", irq);
1572 /* Start new range. */
1573 kprintf(",%lu", rle->start);
1577 /* Unfinished range? */
1579 kprintf("-%d", irq);
1580 kprintf(" for MSI-X\n");
1584 /* Mask all vectors. */
1585 for (i = 0; i < cfg->msix.msix_msgnum; i++)
1586 pci_mask_msix_vector(child, i);
1588 /* Allocate and initialize vector data and virtual table. */
1589 cfg->msix.msix_vectors = kmalloc(sizeof(struct msix_vector) * actual,
1590 M_DEVBUF, M_WAITOK | M_ZERO);
1591 cfg->msix.msix_table = kmalloc(sizeof(struct msix_table_entry) * actual,
1592 M_DEVBUF, M_WAITOK | M_ZERO);
1593 for (i = 0; i < actual; i++) {
1594 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1595 cfg->msix.msix_vectors[i].mv_irq = rle->start;
1596 cfg->msix.msix_table[i].mte_vector = i + 1;
1599 /* Update control register to enable MSI-X. */
1600 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1601 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
1602 cfg->msix.msix_ctrl, 2);
1604 /* Update counts of alloc'd messages. */
1605 cfg->msix.msix_alloc = actual;
1606 cfg->msix.msix_table_len = actual;
1613 pci_release_msix(device_t dev, device_t child)
1615 struct pci_devinfo *dinfo = device_get_ivars(child);
1616 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1617 struct resource_list_entry *rle;
1620 /* Do we have any messages to release? */
1621 if (msix->msix_alloc == 0)
1624 /* Make sure none of the resources are allocated. */
1625 for (i = 0; i < msix->msix_table_len; i++) {
1626 if (msix->msix_table[i].mte_vector == 0)
1628 if (msix->msix_table[i].mte_handlers > 0)
1630 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1631 KASSERT(rle != NULL, ("missing resource"));
1632 if (rle->res != NULL)
1636 /* Update control register to disable MSI-X. */
1637 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1638 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
1639 msix->msix_ctrl, 2);
1641 /* Free the resource list entries. */
1642 for (i = 0; i < msix->msix_table_len; i++) {
1643 if (msix->msix_table[i].mte_vector == 0)
1645 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1647 kfree(msix->msix_table, M_DEVBUF);
1648 msix->msix_table_len = 0;
1650 /* Release the IRQs. */
1651 for (i = 0; i < msix->msix_alloc; i++)
1652 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1653 msix->msix_vectors[i].mv_irq, -1 /* XXX */);
1654 kfree(msix->msix_vectors, M_DEVBUF);
1655 msix->msix_alloc = 0;
1661 * Return the max supported MSI-X messages this device supports.
1662 * Basically, assuming the MD code can alloc messages, this function
1663 * should return the maximum value that pci_alloc_msix() can return.
1664 * Thus, it is subject to the tunables, etc.
1667 pci_msix_count_method(device_t dev, device_t child)
1669 struct pci_devinfo *dinfo = device_get_ivars(child);
1670 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1672 if (pci_do_msix && msix->msix_location != 0)
1673 return (msix->msix_msgnum);
1678 pci_setup_msix(device_t dev)
1680 struct pci_devinfo *dinfo = device_get_ivars(dev);
1681 pcicfgregs *cfg = &dinfo->cfg;
1682 struct resource_list_entry *rle;
1683 struct resource *table_res, *pba_res;
1685 KASSERT(cfg->msix.msix_table_res == NULL &&
1686 cfg->msix.msix_pba_res == NULL, ("MSI-X has been setup yet\n"));
1688 /* If rid 0 is allocated, then fail. */
1689 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1690 if (rle != NULL && rle->res != NULL)
1693 /* Already have allocated MSIs? */
1694 if (cfg->msi.msi_alloc != 0)
1697 /* If MSI is blacklisted for this system, fail. */
1698 if (pci_msi_blacklisted())
1701 /* MSI-X capability present? */
1702 if (cfg->msix.msix_location == 0 || !pci_do_msix)
1705 /* Make sure the appropriate BARs are mapped. */
1706 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1707 cfg->msix.msix_table_bar);
1708 if (rle == NULL || rle->res == NULL ||
1709 !(rman_get_flags(rle->res) & RF_ACTIVE))
1711 table_res = rle->res;
1712 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1713 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1714 cfg->msix.msix_pba_bar);
1715 if (rle == NULL || rle->res == NULL ||
1716 !(rman_get_flags(rle->res) & RF_ACTIVE))
1721 cfg->msix.msix_table_res = table_res;
1722 cfg->msix.msix_pba_res = pba_res;
1724 pci_mask_msix_allvectors(dev);
1730 pci_teardown_msix(device_t dev)
1732 struct pci_devinfo *dinfo = device_get_ivars(dev);
1733 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1735 KASSERT(msix->msix_table_res != NULL &&
1736 msix->msix_pba_res != NULL, ("MSI-X is not setup yet\n"));
1738 pci_mask_msix_allvectors(dev);
1740 msix->msix_table_res = NULL;
1741 msix->msix_pba_res = NULL;
1745 pci_enable_msix(device_t dev)
1747 struct pci_devinfo *dinfo = device_get_ivars(dev);
1748 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1750 KASSERT(msix->msix_table_res != NULL &&
1751 msix->msix_pba_res != NULL, ("MSI-X is not setup yet\n"));
1753 /* Update control register to enable MSI-X. */
1754 msix->msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1755 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1756 msix->msix_ctrl, 2);
1760 pci_disable_msix(device_t dev)
1762 struct pci_devinfo *dinfo = device_get_ivars(dev);
1763 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1765 KASSERT(msix->msix_table_res != NULL &&
1766 msix->msix_pba_res != NULL, ("MSI-X is not setup yet\n"));
1768 /* Disable MSI -> HT mapping. */
1769 pci_ht_map_msi(dev, 0);
1771 /* Update control register to disable MSI-X. */
1772 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1773 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1774 msix->msix_ctrl, 2);
1778 pci_mask_msix_allvectors(device_t dev)
1780 struct pci_devinfo *dinfo = device_get_ivars(dev);
1783 for (i = 0; i < dinfo->cfg.msix.msix_msgnum; ++i)
1784 pci_mask_msix_vector(dev, i);
1788 * HyperTransport MSI mapping control
1791 pci_ht_map_msi(device_t dev, uint64_t addr)
1793 struct pci_devinfo *dinfo = device_get_ivars(dev);
1794 struct pcicfg_ht *ht = &dinfo->cfg.ht;
1799 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
1800 ht->ht_msiaddr >> 20 == addr >> 20) {
1801 /* Enable MSI -> HT mapping. */
1802 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1803 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1807 if (!addr && (ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) {
1808 /* Disable MSI -> HT mapping. */
1809 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
1810 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1816 * Support for MSI message signalled interrupts.
1819 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
1821 struct pci_devinfo *dinfo = device_get_ivars(dev);
1822 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1824 /* Write data and address values. */
1825 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1826 address & 0xffffffff, 4);
1827 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1828 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
1830 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
1833 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
1836 /* Enable MSI in the control register. */
1837 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
1838 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1841 /* Enable MSI -> HT mapping. */
1842 pci_ht_map_msi(dev, address);
1846 pci_disable_msi(device_t dev)
1848 struct pci_devinfo *dinfo = device_get_ivars(dev);
1849 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1851 /* Disable MSI -> HT mapping. */
1852 pci_ht_map_msi(dev, 0);
1854 /* Disable MSI in the control register. */
1855 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
1856 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1861 * Restore MSI registers during resume. If MSI is enabled then
1862 * restore the data and address registers in addition to the control
1866 pci_resume_msi(device_t dev)
1868 struct pci_devinfo *dinfo = device_get_ivars(dev);
1869 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1873 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
1874 address = msi->msi_addr;
1875 data = msi->msi_data;
1876 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1877 address & 0xffffffff, 4);
1878 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1879 pci_write_config(dev, msi->msi_location +
1880 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
1881 pci_write_config(dev, msi->msi_location +
1882 PCIR_MSI_DATA_64BIT, data, 2);
1884 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
1887 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1892 * Returns true if the specified device is blacklisted because MSI
1896 pci_msi_device_blacklisted(device_t dev)
1898 struct pci_quirk *q;
1900 if (!pci_honor_msi_blacklist)
1903 for (q = &pci_quirks[0]; q->devid; q++) {
1904 if (q->devid == pci_get_devid(dev) &&
1905 q->type == PCI_QUIRK_DISABLE_MSI)
1912 * Determine if MSI is blacklisted globally on this sytem. Currently,
1913 * we just check for blacklisted chipsets as represented by the
1914 * host-PCI bridge at device 0:0:0. In the future, it may become
1915 * necessary to check other system attributes, such as the kenv values
1916 * that give the motherboard manufacturer and model number.
1919 pci_msi_blacklisted(void)
1923 if (!pci_honor_msi_blacklist)
1926 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
1927 if (!(pcie_chipset || pcix_chipset))
1930 dev = pci_find_bsf(0, 0, 0);
1932 return (pci_msi_device_blacklisted(dev));
1937 * Attempt to allocate count MSI messages on start_cpuid.
1939 * If start_cpuid < 0, then the MSI messages' target CPU will be
1940 * selected automaticly.
1942 * If the caller explicitly specified the MSI messages' target CPU,
1943 * i.e. start_cpuid >= 0, then we will try to allocate the count MSI
1944 * messages on the specified CPU, if the allocation fails due to MD
1945 * does not have enough vectors (EMSGSIZE), then we will try next
1946 * available CPU, until the allocation fails on all CPUs.
1948 * EMSGSIZE will be returned, if all available CPUs does not have
1949 * enough vectors for the requested amount of MSI messages. Caller
1950 * should either reduce the amount of MSI messages to be requested,
1951 * or simply giving up using MSI.
1953 * The available SYS_RES_IRQ resources' rids, which are >= 1, are
1954 * returned in 'rid' array, if the allocation succeeds.
1957 pci_alloc_msi_method(device_t dev, device_t child, int *rid, int count,
1960 struct pci_devinfo *dinfo = device_get_ivars(child);
1961 pcicfgregs *cfg = &dinfo->cfg;
1962 struct resource_list_entry *rle;
1963 int error, i, irqs[32], cpuid = 0;
1966 KASSERT(count != 0 && count <= 32 && powerof2(count),
1967 ("invalid MSI count %d\n", count));
1968 KASSERT(start_cpuid < ncpus, ("invalid cpuid %d\n", start_cpuid));
1970 /* If rid 0 is allocated, then fail. */
1971 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1972 if (rle != NULL && rle->res != NULL)
1975 /* Already have allocated messages? */
1976 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1979 /* If MSI is blacklisted for this system, fail. */
1980 if (pci_msi_blacklisted())
1983 /* MSI capability present? */
1984 if (cfg->msi.msi_location == 0 || !pci_do_msi)
1987 KASSERT(count <= cfg->msi.msi_msgnum, ("large MSI count %d, max %d\n",
1988 count, cfg->msi.msi_msgnum));
1991 device_printf(child,
1992 "attempting to allocate %d MSI vectors (%d supported)\n",
1993 count, cfg->msi.msi_msgnum);
1996 if (start_cpuid < 0)
1997 start_cpuid = atomic_fetchadd_int(&pci_msi_cpuid, 1) % ncpus;
2000 for (i = 0; i < ncpus; ++i) {
2001 cpuid = (start_cpuid + i) % ncpus;
2003 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, count,
2004 cfg->msi.msi_msgnum, irqs, cpuid);
2007 else if (error != EMSGSIZE)
2014 * We now have N messages mapped onto SYS_RES_IRQ resources in
2015 * the irqs[] array, so add new resources starting at rid 1.
2017 for (i = 0; i < count; i++) {
2019 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
2020 irqs[i], irqs[i], 1, cpuid);
2025 device_printf(child, "using IRQ %d on cpu%d for MSI\n",
2031 * Be fancy and try to print contiguous runs
2032 * of IRQ values as ranges. 'run' is true if
2033 * we are in a range.
2035 device_printf(child, "using IRQs %d", irqs[0]);
2037 for (i = 1; i < count; i++) {
2039 /* Still in a run? */
2040 if (irqs[i] == irqs[i - 1] + 1) {
2045 /* Finish previous range. */
2047 kprintf("-%d", irqs[i - 1]);
2051 /* Start new range. */
2052 kprintf(",%d", irqs[i]);
2055 /* Unfinished range? */
2057 kprintf("-%d", irqs[count - 1]);
2058 kprintf(" for MSI on cpu%d\n", cpuid);
2062 /* Update control register with count. */
2063 ctrl = cfg->msi.msi_ctrl;
2064 ctrl &= ~PCIM_MSICTRL_MME_MASK;
2065 ctrl |= (ffs(count) - 1) << 4;
2066 cfg->msi.msi_ctrl = ctrl;
2067 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
2069 /* Update counts of alloc'd messages. */
2070 cfg->msi.msi_alloc = count;
2071 cfg->msi.msi_handlers = 0;
2075 /* Release the MSI messages associated with this device. */
2077 pci_release_msi_method(device_t dev, device_t child)
2079 struct pci_devinfo *dinfo = device_get_ivars(child);
2080 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2081 struct resource_list_entry *rle;
2082 int i, irqs[32], cpuid = -1;
2084 /* Do we have any messages to release? */
2085 if (msi->msi_alloc == 0)
2087 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
2089 /* Make sure none of the resources are allocated. */
2090 if (msi->msi_handlers > 0)
2092 for (i = 0; i < msi->msi_alloc; i++) {
2093 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2094 KASSERT(rle != NULL, ("missing MSI resource"));
2095 if (rle->res != NULL)
2099 KASSERT(cpuid >= 0 && cpuid < ncpus,
2100 ("invalid MSI target cpuid %d\n", cpuid));
2102 KASSERT(rle->cpuid == cpuid,
2103 ("MSI targets different cpus, "
2104 "was cpu%d, now cpu%d", cpuid, rle->cpuid));
2106 irqs[i] = rle->start;
2109 /* Update control register with 0 count. */
2110 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
2111 ("%s: MSI still enabled", __func__));
2112 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
2113 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2116 /* Release the messages. */
2117 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs,
2119 for (i = 0; i < msi->msi_alloc; i++)
2120 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2122 /* Update alloc count. */
2130 * Return the max supported MSI messages this device supports.
2131 * Basically, assuming the MD code can alloc messages, this function
2132 * should return the maximum value that pci_alloc_msi() can return.
2133 * Thus, it is subject to the tunables, etc.
2136 pci_msi_count_method(device_t dev, device_t child)
2138 struct pci_devinfo *dinfo = device_get_ivars(child);
2139 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2141 if (pci_do_msi && msi->msi_location != 0)
2142 return (msi->msi_msgnum);
2146 /* kfree pcicfgregs structure and all depending data structures */
2149 pci_freecfg(struct pci_devinfo *dinfo)
2151 struct devlist *devlist_head;
2154 devlist_head = &pci_devq;
2156 if (dinfo->cfg.vpd.vpd_reg) {
2157 kfree(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2158 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2159 kfree(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2160 kfree(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2161 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2162 kfree(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2163 kfree(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2165 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2166 kfree(dinfo, M_DEVBUF);
2168 /* increment the generation count */
2171 /* we're losing one device */
2177 * PCI power manangement
2180 pci_set_powerstate_method(device_t dev, device_t child, int state)
2182 struct pci_devinfo *dinfo = device_get_ivars(child);
2183 pcicfgregs *cfg = &dinfo->cfg;
2185 int result, oldstate, highest, delay;
2187 if (cfg->pp.pp_cap == 0)
2188 return (EOPNOTSUPP);
2191 * Optimize a no state change request away. While it would be OK to
2192 * write to the hardware in theory, some devices have shown odd
2193 * behavior when going from D3 -> D3.
2195 oldstate = pci_get_powerstate(child);
2196 if (oldstate == state)
2200 * The PCI power management specification states that after a state
2201 * transition between PCI power states, system software must
2202 * guarantee a minimal delay before the function accesses the device.
2203 * Compute the worst case delay that we need to guarantee before we
2204 * access the device. Many devices will be responsive much more
2205 * quickly than this delay, but there are some that don't respond
2206 * instantly to state changes. Transitions to/from D3 state require
2207 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2208 * is done below with DELAY rather than a sleeper function because
2209 * this function can be called from contexts where we cannot sleep.
2211 highest = (oldstate > state) ? oldstate : state;
2212 if (highest == PCI_POWERSTATE_D3)
2214 else if (highest == PCI_POWERSTATE_D2)
2218 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2219 & ~PCIM_PSTAT_DMASK;
2222 case PCI_POWERSTATE_D0:
2223 status |= PCIM_PSTAT_D0;
2225 case PCI_POWERSTATE_D1:
2226 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2227 return (EOPNOTSUPP);
2228 status |= PCIM_PSTAT_D1;
2230 case PCI_POWERSTATE_D2:
2231 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2232 return (EOPNOTSUPP);
2233 status |= PCIM_PSTAT_D2;
2235 case PCI_POWERSTATE_D3:
2236 status |= PCIM_PSTAT_D3;
2244 "pci%d:%d:%d:%d: Transition from D%d to D%d\n",
2245 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2246 dinfo->cfg.func, oldstate, state);
2248 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2255 pci_get_powerstate_method(device_t dev, device_t child)
2257 struct pci_devinfo *dinfo = device_get_ivars(child);
2258 pcicfgregs *cfg = &dinfo->cfg;
2262 if (cfg->pp.pp_cap != 0) {
2263 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2264 switch (status & PCIM_PSTAT_DMASK) {
2266 result = PCI_POWERSTATE_D0;
2269 result = PCI_POWERSTATE_D1;
2272 result = PCI_POWERSTATE_D2;
2275 result = PCI_POWERSTATE_D3;
2278 result = PCI_POWERSTATE_UNKNOWN;
2282 /* No support, device is always at D0 */
2283 result = PCI_POWERSTATE_D0;
2289 * Some convenience functions for PCI device drivers.
2292 static __inline void
2293 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2297 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2299 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2302 static __inline void
2303 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2307 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2309 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2313 pci_enable_busmaster_method(device_t dev, device_t child)
2315 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2320 pci_disable_busmaster_method(device_t dev, device_t child)
2322 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2327 pci_enable_io_method(device_t dev, device_t child, int space)
2337 case SYS_RES_IOPORT:
2338 bit = PCIM_CMD_PORTEN;
2341 case SYS_RES_MEMORY:
2342 bit = PCIM_CMD_MEMEN;
2348 pci_set_command_bit(dev, child, bit);
2349 /* Some devices seem to need a brief stall here, what do to? */
2350 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2353 device_printf(child, "failed to enable %s mapping!\n", error);
2358 pci_disable_io_method(device_t dev, device_t child, int space)
2368 case SYS_RES_IOPORT:
2369 bit = PCIM_CMD_PORTEN;
2372 case SYS_RES_MEMORY:
2373 bit = PCIM_CMD_MEMEN;
2379 pci_clear_command_bit(dev, child, bit);
2380 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2381 if (command & bit) {
2382 device_printf(child, "failed to disable %s mapping!\n", error);
2389 * New style pci driver. Parent device is either a pci-host-bridge or a
2390 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2394 pci_print_verbose(struct pci_devinfo *dinfo)
2398 pcicfgregs *cfg = &dinfo->cfg;
2400 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2401 cfg->vendor, cfg->device, cfg->revid);
2402 kprintf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2403 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2404 kprintf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2405 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2407 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2408 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2409 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
2410 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2411 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
2412 if (cfg->intpin > 0)
2413 kprintf("\tintpin=%c, irq=%d\n",
2414 cfg->intpin +'a' -1, cfg->intline);
2415 if (cfg->pp.pp_cap) {
2418 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2419 kprintf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2420 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2421 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2422 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2423 status & PCIM_PSTAT_DMASK);
2425 if (cfg->msi.msi_location) {
2428 ctrl = cfg->msi.msi_ctrl;
2429 kprintf("\tMSI supports %d message%s%s%s\n",
2430 cfg->msi.msi_msgnum,
2431 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2432 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2433 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2435 if (cfg->msix.msix_location) {
2436 kprintf("\tMSI-X supports %d message%s ",
2437 cfg->msix.msix_msgnum,
2438 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2439 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2440 kprintf("in map 0x%x\n",
2441 cfg->msix.msix_table_bar);
2443 kprintf("in maps 0x%x and 0x%x\n",
2444 cfg->msix.msix_table_bar,
2445 cfg->msix.msix_pba_bar);
2447 pci_print_verbose_expr(cfg);
2452 pci_print_verbose_expr(const pcicfgregs *cfg)
2454 const struct pcicfg_expr *expr = &cfg->expr;
2455 const char *port_name;
2461 if (expr->expr_ptr == 0) /* No PCI Express capability */
2464 kprintf("\tPCI Express ver.%d cap=0x%04x",
2465 expr->expr_cap & PCIEM_CAP_VER_MASK, expr->expr_cap);
2466 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
2469 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
2471 switch (port_type) {
2472 case PCIE_END_POINT:
2473 port_name = "DEVICE";
2475 case PCIE_LEG_END_POINT:
2476 port_name = "LEGDEV";
2478 case PCIE_ROOT_PORT:
2481 case PCIE_UP_STREAM_PORT:
2482 port_name = "UPSTREAM";
2484 case PCIE_DOWN_STREAM_PORT:
2485 port_name = "DOWNSTRM";
2487 case PCIE_PCIE2PCI_BRIDGE:
2488 port_name = "PCIE2PCI";
2490 case PCIE_PCI2PCIE_BRIDGE:
2491 port_name = "PCI2PCIE";
2497 if ((port_type == PCIE_ROOT_PORT ||
2498 port_type == PCIE_DOWN_STREAM_PORT) &&
2499 !(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
2501 if (port_name != NULL)
2502 kprintf("[%s]", port_name);
2504 if (pcie_slotimpl(cfg)) {
2505 kprintf(", slotcap=0x%08x", expr->expr_slotcap);
2506 if (expr->expr_slotcap & PCIEM_SLTCAP_HP_CAP)
2507 kprintf("[HOTPLUG]");
2514 pci_porten(device_t pcib, int b, int s, int f)
2516 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2517 & PCIM_CMD_PORTEN) != 0;
2521 pci_memen(device_t pcib, int b, int s, int f)
2523 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2524 & PCIM_CMD_MEMEN) != 0;
2528 * Add a resource based on a pci map register. Return 1 if the map
2529 * register is a 32bit map register or 2 if it is a 64bit register.
2532 pci_add_map(device_t pcib, device_t bus, device_t dev,
2533 int b, int s, int f, int reg, struct resource_list *rl, int force,
2538 pci_addr_t start, end, count;
2545 struct resource *res;
2547 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2548 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
2549 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2550 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
2552 if (PCI_BAR_MEM(map)) {
2553 type = SYS_RES_MEMORY;
2554 if (map & PCIM_BAR_MEM_PREFETCH)
2557 type = SYS_RES_IOPORT;
2558 ln2size = pci_mapsize(testval);
2559 ln2range = pci_maprange(testval);
2560 base = pci_mapbase(map);
2561 barlen = ln2range == 64 ? 2 : 1;
2564 * For I/O registers, if bottom bit is set, and the next bit up
2565 * isn't clear, we know we have a BAR that doesn't conform to the
2566 * spec, so ignore it. Also, sanity check the size of the data
2567 * areas to the type of memory involved. Memory must be at least
2568 * 16 bytes in size, while I/O ranges must be at least 4.
2570 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2572 if ((type == SYS_RES_MEMORY && ln2size < 4) ||
2573 (type == SYS_RES_IOPORT && ln2size < 2))
2577 /* Read the other half of a 64bit map register */
2578 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
2580 kprintf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2581 reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size);
2582 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2583 kprintf(", port disabled\n");
2584 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2585 kprintf(", memory disabled\n");
2587 kprintf(", enabled\n");
2591 * If base is 0, then we have problems. It is best to ignore
2592 * such entries for the moment. These will be allocated later if
2593 * the driver specifically requests them. However, some
2594 * removable busses look better when all resources are allocated,
2595 * so allow '0' to be overriden.
2597 * Similarly treat maps whose values is the same as the test value
2598 * read back. These maps have had all f's written to them by the
2599 * BIOS in an attempt to disable the resources.
2601 if (!force && (base == 0 || map == testval))
2603 if ((u_long)base != base) {
2605 "pci%d:%d:%d:%d bar %#x too many address bits",
2606 pci_get_domain(dev), b, s, f, reg);
2611 * This code theoretically does the right thing, but has
2612 * undesirable side effects in some cases where peripherals
2613 * respond oddly to having these bits enabled. Let the user
2614 * be able to turn them off (since pci_enable_io_modes is 1 by
2617 if (pci_enable_io_modes) {
2618 /* Turn on resources that have been left off by a lazy BIOS */
2619 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
2620 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2621 cmd |= PCIM_CMD_PORTEN;
2622 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2624 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
2625 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2626 cmd |= PCIM_CMD_MEMEN;
2627 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2630 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2632 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2636 count = 1 << ln2size;
2637 if (base == 0 || base == pci_mapbase(testval)) {
2638 start = 0; /* Let the parent decide. */
2642 end = base + (1 << ln2size) - 1;
2644 resource_list_add(rl, type, reg, start, end, count, -1);
2647 * Try to allocate the resource for this BAR from our parent
2648 * so that this resource range is already reserved. The
2649 * driver for this device will later inherit this resource in
2650 * pci_alloc_resource().
2652 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count,
2653 prefetch ? RF_PREFETCHABLE : 0, -1);
2656 * If the allocation fails, delete the resource list
2657 * entry to force pci_alloc_resource() to allocate
2658 * resources from the parent.
2660 resource_list_delete(rl, type, reg);
2661 #ifdef PCI_BAR_CLEAR
2664 #else /* !PCI_BAR_CLEAR */
2666 * Don't clear BAR here. Some BIOS lists HPET as a
2667 * PCI function, clearing the BAR causes HPET timer
2671 kprintf("pci:%d:%d:%d: resource reservation failed "
2672 "%#jx - %#jx\n", b, s, f,
2673 (intmax_t)start, (intmax_t)end);
2676 #endif /* PCI_BAR_CLEAR */
2678 start = rman_get_start(res);
2680 pci_write_config(dev, reg, start, 4);
2682 pci_write_config(dev, reg + 4, start >> 32, 4);
2687 * For ATA devices we need to decide early what addressing mode to use.
2688 * Legacy demands that the primary and secondary ATA ports sits on the
2689 * same addresses that old ISA hardware did. This dictates that we use
2690 * those addresses and ignore the BAR's if we cannot set PCI native
2694 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b,
2695 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask)
2697 int rid, type, progif;
2699 /* if this device supports PCI native addressing use it */
2700 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2701 if ((progif & 0x8a) == 0x8a) {
2702 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2703 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
2704 kprintf("Trying ATA native PCI addressing mode\n");
2705 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2709 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2710 type = SYS_RES_IOPORT;
2711 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
2712 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force,
2713 prefetchmask & (1 << 0));
2714 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force,
2715 prefetchmask & (1 << 1));
2718 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8, -1);
2719 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
2722 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1, -1);
2723 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
2726 if (progif & PCIP_STORAGE_IDE_MODESEC) {
2727 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force,
2728 prefetchmask & (1 << 2));
2729 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force,
2730 prefetchmask & (1 << 3));
2733 resource_list_add(rl, type, rid, 0x170, 0x177, 8, -1);
2734 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
2737 resource_list_add(rl, type, rid, 0x376, 0x376, 1, -1);
2738 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
2741 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force,
2742 prefetchmask & (1 << 4));
2743 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force,
2744 prefetchmask & (1 << 5));
2748 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
2750 struct pci_devinfo *dinfo = device_get_ivars(dev);
2751 pcicfgregs *cfg = &dinfo->cfg;
2752 char tunable_name[64];
2755 /* Has to have an intpin to have an interrupt. */
2756 if (cfg->intpin == 0)
2759 /* Let the user override the IRQ with a tunable. */
2760 irq = PCI_INVALID_IRQ;
2761 ksnprintf(tunable_name, sizeof(tunable_name),
2762 "hw.pci%d.%d.%d.INT%c.irq",
2763 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
2764 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
2765 irq = PCI_INVALID_IRQ;
2768 * If we didn't get an IRQ via the tunable, then we either use the
2769 * IRQ value in the intline register or we ask the bus to route an
2770 * interrupt for us. If force_route is true, then we only use the
2771 * value in the intline register if the bus was unable to assign an
2774 if (!PCI_INTERRUPT_VALID(irq)) {
2775 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
2776 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
2777 if (!PCI_INTERRUPT_VALID(irq))
2781 /* If after all that we don't have an IRQ, just bail. */
2782 if (!PCI_INTERRUPT_VALID(irq))
2785 /* Update the config register if it changed. */
2786 if (irq != cfg->intline) {
2788 pci_write_config(dev, PCIR_INTLINE, irq, 1);
2791 /* Add this IRQ as rid 0 interrupt resource. */
2792 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1,
2793 machintr_legacy_intr_cpuid(irq));
2797 pci_add_resources(device_t pcib, device_t bus, device_t dev, int force, uint32_t prefetchmask)
2799 struct pci_devinfo *dinfo = device_get_ivars(dev);
2800 pcicfgregs *cfg = &dinfo->cfg;
2801 struct resource_list *rl = &dinfo->resources;
2802 struct pci_quirk *q;
2809 /* ATA devices needs special map treatment */
2810 if ((pci_get_class(dev) == PCIC_STORAGE) &&
2811 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
2812 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
2813 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
2814 !pci_read_config(dev, PCIR_BAR(2), 4))) )
2815 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask);
2817 for (i = 0; i < cfg->nummaps;)
2818 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i),
2819 rl, force, prefetchmask & (1 << i));
2822 * Add additional, quirked resources.
2824 for (q = &pci_quirks[0]; q->devid; q++) {
2825 if (q->devid == ((cfg->device << 16) | cfg->vendor)
2826 && q->type == PCI_QUIRK_MAP_REG)
2827 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl,
2831 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2833 * Try to re-route interrupts. Sometimes the BIOS or
2834 * firmware may leave bogus values in these registers.
2835 * If the re-route fails, then just stick with what we
2838 pci_assign_interrupt(bus, dev, 1);
2843 pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
2845 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
2846 device_t pcib = device_get_parent(dev);
2847 struct pci_devinfo *dinfo;
2849 int s, f, pcifunchigh;
2852 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
2853 ("dinfo_size too small"));
2854 maxslots = PCIB_MAXSLOTS(pcib);
2855 for (s = 0; s <= maxslots; s++) {
2859 hdrtype = REG(PCIR_HDRTYPE, 1);
2860 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
2862 if (hdrtype & PCIM_MFDEV)
2863 pcifunchigh = PCI_FUNCMAX;
2864 for (f = 0; f <= pcifunchigh; f++) {
2865 dinfo = pci_read_device(pcib, domain, busno, s, f,
2867 if (dinfo != NULL) {
2868 pci_add_child(dev, dinfo);
2876 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
2880 pcib = device_get_parent(bus);
2881 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
2882 device_set_ivars(dinfo->cfg.dev, dinfo);
2883 resource_list_init(&dinfo->resources);
2884 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
2885 pci_cfg_restore(dinfo->cfg.dev, dinfo);
2886 pci_print_verbose(dinfo);
2887 pci_add_resources(pcib, bus, dinfo->cfg.dev, 0, 0);
2891 pci_probe(device_t dev)
2893 device_set_desc(dev, "PCI bus");
2895 /* Allow other subclasses to override this driver. */
2900 pci_attach(device_t dev)
2905 * Since there can be multiple independantly numbered PCI
2906 * busses on systems with multiple PCI domains, we can't use
2907 * the unit number to decide which bus we are probing. We ask
2908 * the parent pcib what our domain and bus numbers are.
2910 domain = pcib_get_domain(dev);
2911 busno = pcib_get_bus(dev);
2913 device_printf(dev, "domain=%d, physical bus=%d\n",
2916 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
2918 return (bus_generic_attach(dev));
2922 pci_suspend(device_t dev)
2924 int dstate, error, i, numdevs;
2925 device_t acpi_dev, child, *devlist;
2926 struct pci_devinfo *dinfo;
2929 * Save the PCI configuration space for each child and set the
2930 * device in the appropriate power state for this sleep state.
2933 if (pci_do_power_resume)
2934 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2935 device_get_children(dev, &devlist, &numdevs);
2936 for (i = 0; i < numdevs; i++) {
2938 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2939 pci_cfg_save(child, dinfo, 0);
2942 /* Suspend devices before potentially powering them down. */
2943 error = bus_generic_suspend(dev);
2945 kfree(devlist, M_TEMP);
2950 * Always set the device to D3. If ACPI suggests a different
2951 * power state, use it instead. If ACPI is not present, the
2952 * firmware is responsible for managing device power. Skip
2953 * children who aren't attached since they are powered down
2954 * separately. Only manage type 0 devices for now.
2956 for (i = 0; acpi_dev && i < numdevs; i++) {
2958 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2959 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) {
2960 dstate = PCI_POWERSTATE_D3;
2961 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate);
2962 pci_set_powerstate(child, dstate);
2965 kfree(devlist, M_TEMP);
2970 pci_resume(device_t dev)
2973 device_t acpi_dev, child, *devlist;
2974 struct pci_devinfo *dinfo;
2977 * Set each child to D0 and restore its PCI configuration space.
2980 if (pci_do_power_resume)
2981 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2982 device_get_children(dev, &devlist, &numdevs);
2983 for (i = 0; i < numdevs; i++) {
2985 * Notify ACPI we're going to D0 but ignore the result. If
2986 * ACPI is not present, the firmware is responsible for
2987 * managing device power. Only manage type 0 devices for now.
2990 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2991 if (acpi_dev && device_is_attached(child) &&
2992 dinfo->cfg.hdrtype == 0) {
2993 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL);
2994 pci_set_powerstate(child, PCI_POWERSTATE_D0);
2997 /* Now the device is powered up, restore its config space. */
2998 pci_cfg_restore(child, dinfo);
3000 kfree(devlist, M_TEMP);
3001 return (bus_generic_resume(dev));
3005 pci_load_vendor_data(void)
3007 caddr_t vendordata, info;
3009 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
3010 info = preload_search_info(vendordata, MODINFO_ADDR);
3011 pci_vendordata = *(char **)info;
3012 info = preload_search_info(vendordata, MODINFO_SIZE);
3013 pci_vendordata_size = *(size_t *)info;
3014 /* terminate the database */
3015 pci_vendordata[pci_vendordata_size] = '\n';
3020 pci_driver_added(device_t dev, driver_t *driver)
3025 struct pci_devinfo *dinfo;
3029 device_printf(dev, "driver added\n");
3030 DEVICE_IDENTIFY(driver, dev);
3031 device_get_children(dev, &devlist, &numdevs);
3032 for (i = 0; i < numdevs; i++) {
3034 if (device_get_state(child) != DS_NOTPRESENT)
3036 dinfo = device_get_ivars(child);
3037 pci_print_verbose(dinfo);
3039 kprintf("pci%d:%d:%d:%d: reprobing on driver added\n",
3040 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
3042 pci_cfg_restore(child, dinfo);
3043 if (device_probe_and_attach(child) != 0)
3044 pci_cfg_save(child, dinfo, 1);
3046 kfree(devlist, M_TEMP);
3050 pci_child_detached(device_t parent __unused, device_t child)
3052 /* Turn child's power off */
3053 pci_cfg_save(child, device_get_ivars(child), 1);
3057 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
3058 driver_intr_t *intr, void *arg, void **cookiep, lwkt_serialize_t serializer)
3060 struct pci_devinfo *dinfo;
3061 struct msix_table_entry *mte;
3062 struct msix_vector *mv;
3068 error = bus_generic_setup_intr(dev, child, irq, flags, intr,
3069 arg, &cookie, serializer);
3073 /* If this is not a direct child, just bail out. */
3074 if (device_get_parent(child) != dev) {
3079 rid = rman_get_rid(irq);
3081 /* Make sure that INTx is enabled */
3082 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3085 * Check to see if the interrupt is MSI or MSI-X.
3086 * Ask our parent to map the MSI and give
3087 * us the address and data register values.
3088 * If we fail for some reason, teardown the
3089 * interrupt handler.
3091 dinfo = device_get_ivars(child);
3092 if (dinfo->cfg.msi.msi_alloc > 0) {
3093 if (dinfo->cfg.msi.msi_addr == 0) {
3094 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
3095 ("MSI has handlers, but vectors not mapped"));
3096 error = PCIB_MAP_MSI(device_get_parent(dev),
3097 child, rman_get_start(irq), &addr, &data,
3098 rman_get_cpuid(irq));
3101 dinfo->cfg.msi.msi_addr = addr;
3102 dinfo->cfg.msi.msi_data = data;
3103 pci_enable_msi(child, addr, data);
3105 dinfo->cfg.msi.msi_handlers++;
3107 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3108 ("No MSI or MSI-X interrupts allocated"));
3109 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3110 ("MSI-X index too high"));
3111 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3112 KASSERT(mte->mte_vector != 0, ("no message vector"));
3113 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
3114 KASSERT(mv->mv_irq == rman_get_start(irq),
3116 if (mv->mv_address == 0) {
3117 KASSERT(mte->mte_handlers == 0,
3118 ("MSI-X table entry has handlers, but vector not mapped"));
3119 error = PCIB_MAP_MSI(device_get_parent(dev),
3120 child, rman_get_start(irq), &addr, &data,
3121 rman_get_cpuid(irq));
3124 mv->mv_address = addr;
3127 if (mte->mte_handlers == 0) {
3128 pci_setup_msix_vector(child, rid - 1,
3129 mv->mv_address, mv->mv_data);
3130 pci_unmask_msix_vector(child, rid - 1);
3132 mte->mte_handlers++;
3135 /* Make sure that INTx is disabled if we are using MSI/MSIX */
3136 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3139 (void)bus_generic_teardown_intr(dev, child, irq,
3149 pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
3152 struct msix_table_entry *mte;
3153 struct resource_list_entry *rle;
3154 struct pci_devinfo *dinfo;
3157 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
3160 /* If this isn't a direct child, just bail out */
3161 if (device_get_parent(child) != dev)
3162 return(bus_generic_teardown_intr(dev, child, irq, cookie));
3164 rid = rman_get_rid(irq);
3167 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3170 * Check to see if the interrupt is MSI or MSI-X. If so,
3171 * decrement the appropriate handlers count and mask the
3172 * MSI-X message, or disable MSI messages if the count
3175 dinfo = device_get_ivars(child);
3176 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
3177 if (rle->res != irq)
3179 if (dinfo->cfg.msi.msi_alloc > 0) {
3180 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
3181 ("MSI-X index too high"));
3182 if (dinfo->cfg.msi.msi_handlers == 0)
3184 dinfo->cfg.msi.msi_handlers--;
3185 if (dinfo->cfg.msi.msi_handlers == 0)
3186 pci_disable_msi(child);
3188 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3189 ("No MSI or MSI-X interrupts allocated"));
3190 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3191 ("MSI-X index too high"));
3192 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3193 if (mte->mte_handlers == 0)
3195 mte->mte_handlers--;
3196 if (mte->mte_handlers == 0)
3197 pci_mask_msix_vector(child, rid - 1);
3200 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3203 ("%s: generic teardown failed for MSI/MSI-X", __func__));
3208 pci_print_child(device_t dev, device_t child)
3210 struct pci_devinfo *dinfo;
3211 struct resource_list *rl;
3214 dinfo = device_get_ivars(child);
3215 rl = &dinfo->resources;
3217 retval += bus_print_child_header(dev, child);
3219 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
3220 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
3221 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
3222 if (device_get_flags(dev))
3223 retval += kprintf(" flags %#x", device_get_flags(dev));
3225 retval += kprintf(" at device %d.%d", pci_get_slot(child),
3226 pci_get_function(child));
3228 retval += bus_print_child_footer(dev, child);
3238 } pci_nomatch_tab[] = {
3239 {PCIC_OLD, -1, "old"},
3240 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
3241 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
3242 {PCIC_STORAGE, -1, "mass storage"},
3243 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
3244 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
3245 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
3246 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
3247 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
3248 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"},
3249 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"},
3250 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"},
3251 {PCIC_NETWORK, -1, "network"},
3252 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
3253 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
3254 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
3255 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
3256 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
3257 {PCIC_DISPLAY, -1, "display"},
3258 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
3259 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
3260 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
3261 {PCIC_MULTIMEDIA, -1, "multimedia"},
3262 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
3263 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
3264 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
3265 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"},
3266 {PCIC_MEMORY, -1, "memory"},
3267 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
3268 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
3269 {PCIC_BRIDGE, -1, "bridge"},
3270 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
3271 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
3272 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
3273 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
3274 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
3275 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
3276 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
3277 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
3278 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
3279 {PCIC_SIMPLECOMM, -1, "simple comms"},
3280 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
3281 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
3282 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
3283 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
3284 {PCIC_BASEPERIPH, -1, "base peripheral"},
3285 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
3286 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
3287 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
3288 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
3289 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
3290 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"},
3291 {PCIC_INPUTDEV, -1, "input device"},
3292 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
3293 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
3294 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
3295 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
3296 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
3297 {PCIC_DOCKING, -1, "docking station"},
3298 {PCIC_PROCESSOR, -1, "processor"},
3299 {PCIC_SERIALBUS, -1, "serial bus"},
3300 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
3301 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
3302 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
3303 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
3304 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
3305 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
3306 {PCIC_WIRELESS, -1, "wireless controller"},
3307 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
3308 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
3309 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
3310 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
3311 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
3312 {PCIC_SATCOM, -1, "satellite communication"},
3313 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
3314 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
3315 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
3316 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
3317 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
3318 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
3319 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
3320 {PCIC_DASP, -1, "dasp"},
3321 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
3326 pci_probe_nomatch(device_t dev, device_t child)
3329 char *cp, *scp, *device;
3332 * Look for a listing for this device in a loaded device database.
3334 if ((device = pci_describe_device(child)) != NULL) {
3335 device_printf(dev, "<%s>", device);
3336 kfree(device, M_DEVBUF);
3339 * Scan the class/subclass descriptions for a general
3344 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
3345 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
3346 if (pci_nomatch_tab[i].subclass == -1) {
3347 cp = pci_nomatch_tab[i].desc;
3348 } else if (pci_nomatch_tab[i].subclass ==
3349 pci_get_subclass(child)) {
3350 scp = pci_nomatch_tab[i].desc;
3354 device_printf(dev, "<%s%s%s>",
3356 ((cp != NULL) && (scp != NULL)) ? ", " : "",
3359 kprintf(" (vendor 0x%04x, dev 0x%04x) at device %d.%d",
3360 pci_get_vendor(child), pci_get_device(child),
3361 pci_get_slot(child), pci_get_function(child));
3362 if (pci_get_intpin(child) > 0) {
3365 irq = pci_get_irq(child);
3366 if (PCI_INTERRUPT_VALID(irq))
3367 kprintf(" irq %d", irq);
3371 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1);
3375 * Parse the PCI device database, if loaded, and return a pointer to a
3376 * description of the device.
3378 * The database is flat text formatted as follows:
3380 * Any line not in a valid format is ignored.
3381 * Lines are terminated with newline '\n' characters.
3383 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
3386 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
3387 * - devices cannot be listed without a corresponding VENDOR line.
3388 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
3389 * another TAB, then the device name.
3393 * Assuming (ptr) points to the beginning of a line in the database,
3394 * return the vendor or device and description of the next entry.
3395 * The value of (vendor) or (device) inappropriate for the entry type
3396 * is set to -1. Returns nonzero at the end of the database.
3398 * Note that this is slightly unrobust in the face of corrupt data;
3399 * we attempt to safeguard against this by spamming the end of the
3400 * database with a newline when we initialise.
3403 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
3412 left = pci_vendordata_size - (cp - pci_vendordata);
3420 ksscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
3424 ksscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
3427 /* skip to next line */
3428 while (*cp != '\n' && left > 0) {
3437 /* skip to next line */
3438 while (*cp != '\n' && left > 0) {
3442 if (*cp == '\n' && left > 0)
3449 pci_describe_device(device_t dev)
3452 char *desc, *vp, *dp, *line;
3454 desc = vp = dp = NULL;
3457 * If we have no vendor data, we can't do anything.
3459 if (pci_vendordata == NULL)
3463 * Scan the vendor data looking for this device
3465 line = pci_vendordata;
3466 if ((vp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3469 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
3471 if (vendor == pci_get_vendor(dev))
3474 if ((dp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3477 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
3485 if (device == pci_get_device(dev))
3489 ksnprintf(dp, 80, "0x%x", pci_get_device(dev));
3490 if ((desc = kmalloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
3492 ksprintf(desc, "%s, %s", vp, dp);
3495 kfree(vp, M_DEVBUF);
3497 kfree(dp, M_DEVBUF);
3502 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
3504 struct pci_devinfo *dinfo;
3507 dinfo = device_get_ivars(child);
3511 case PCI_IVAR_ETHADDR:
3513 * The generic accessor doesn't deal with failure, so
3514 * we set the return value, then return an error.
3516 *((uint8_t **) result) = NULL;
3518 case PCI_IVAR_SUBVENDOR:
3519 *result = cfg->subvendor;
3521 case PCI_IVAR_SUBDEVICE:
3522 *result = cfg->subdevice;
3524 case PCI_IVAR_VENDOR:
3525 *result = cfg->vendor;
3527 case PCI_IVAR_DEVICE:
3528 *result = cfg->device;
3530 case PCI_IVAR_DEVID:
3531 *result = (cfg->device << 16) | cfg->vendor;
3533 case PCI_IVAR_CLASS:
3534 *result = cfg->baseclass;
3536 case PCI_IVAR_SUBCLASS:
3537 *result = cfg->subclass;
3539 case PCI_IVAR_PROGIF:
3540 *result = cfg->progif;
3542 case PCI_IVAR_REVID:
3543 *result = cfg->revid;
3545 case PCI_IVAR_INTPIN:
3546 *result = cfg->intpin;
3549 *result = cfg->intline;
3551 case PCI_IVAR_DOMAIN:
3552 *result = cfg->domain;
3558 *result = cfg->slot;
3560 case PCI_IVAR_FUNCTION:
3561 *result = cfg->func;
3563 case PCI_IVAR_CMDREG:
3564 *result = cfg->cmdreg;
3566 case PCI_IVAR_CACHELNSZ:
3567 *result = cfg->cachelnsz;
3569 case PCI_IVAR_MINGNT:
3570 *result = cfg->mingnt;
3572 case PCI_IVAR_MAXLAT:
3573 *result = cfg->maxlat;
3575 case PCI_IVAR_LATTIMER:
3576 *result = cfg->lattimer;
3578 case PCI_IVAR_PCIXCAP_PTR:
3579 *result = cfg->pcix.pcix_ptr;
3581 case PCI_IVAR_PCIECAP_PTR:
3582 *result = cfg->expr.expr_ptr;
3584 case PCI_IVAR_VPDCAP_PTR:
3585 *result = cfg->vpd.vpd_reg;
3594 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
3596 struct pci_devinfo *dinfo;
3598 dinfo = device_get_ivars(child);
3601 case PCI_IVAR_INTPIN:
3602 dinfo->cfg.intpin = value;
3604 case PCI_IVAR_ETHADDR:
3605 case PCI_IVAR_SUBVENDOR:
3606 case PCI_IVAR_SUBDEVICE:
3607 case PCI_IVAR_VENDOR:
3608 case PCI_IVAR_DEVICE:
3609 case PCI_IVAR_DEVID:
3610 case PCI_IVAR_CLASS:
3611 case PCI_IVAR_SUBCLASS:
3612 case PCI_IVAR_PROGIF:
3613 case PCI_IVAR_REVID:
3615 case PCI_IVAR_DOMAIN:
3618 case PCI_IVAR_FUNCTION:
3619 return (EINVAL); /* disallow for now */
3626 #include "opt_ddb.h"
3628 #include <ddb/ddb.h>
3629 #include <sys/cons.h>
3632 * List resources based on pci map registers, used for within ddb
3635 DB_SHOW_COMMAND(pciregs, db_pci_dump)
3637 struct pci_devinfo *dinfo;
3638 struct devlist *devlist_head;
3641 int i, error, none_count;
3644 /* get the head of the device queue */
3645 devlist_head = &pci_devq;
3648 * Go through the list of devices and print out devices
3650 for (error = 0, i = 0,
3651 dinfo = STAILQ_FIRST(devlist_head);
3652 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
3653 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
3655 /* Populate pd_name and pd_unit */
3658 name = device_get_name(dinfo->cfg.dev);
3661 db_kprintf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
3662 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
3663 (name && *name) ? name : "none",
3664 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
3666 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
3667 p->pc_sel.pc_func, (p->pc_class << 16) |
3668 (p->pc_subclass << 8) | p->pc_progif,
3669 (p->pc_subdevice << 16) | p->pc_subvendor,
3670 (p->pc_device << 16) | p->pc_vendor,
3671 p->pc_revid, p->pc_hdr);
3677 static struct resource *
3678 pci_alloc_map(device_t dev, device_t child, int type, int *rid,
3679 u_long start, u_long end, u_long count, u_int flags)
3681 struct pci_devinfo *dinfo = device_get_ivars(child);
3682 struct resource_list *rl = &dinfo->resources;
3683 struct resource_list_entry *rle;
3684 struct resource *res;
3685 pci_addr_t map, testval;
3689 * Weed out the bogons, and figure out how large the BAR/map
3690 * is. Bars that read back 0 here are bogus and unimplemented.
3691 * Note: atapci in legacy mode are special and handled elsewhere
3692 * in the code. If you have a atapci device in legacy mode and
3693 * it fails here, that other code is broken.
3696 map = pci_read_config(child, *rid, 4);
3697 pci_write_config(child, *rid, 0xffffffff, 4);
3698 testval = pci_read_config(child, *rid, 4);
3699 if (pci_maprange(testval) == 64)
3700 map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32;
3701 if (pci_mapbase(testval) == 0)
3705 * Restore the original value of the BAR. We may have reprogrammed
3706 * the BAR of the low-level console device and when booting verbose,
3707 * we need the console device addressable.
3709 pci_write_config(child, *rid, map, 4);
3711 if (PCI_BAR_MEM(testval)) {
3712 if (type != SYS_RES_MEMORY) {
3715 "child %s requested type %d for rid %#x,"
3716 " but the BAR says it is an memio\n",
3717 device_get_nameunit(child), type, *rid);
3721 if (type != SYS_RES_IOPORT) {
3724 "child %s requested type %d for rid %#x,"
3725 " but the BAR says it is an ioport\n",
3726 device_get_nameunit(child), type, *rid);
3731 * For real BARs, we need to override the size that
3732 * the driver requests, because that's what the BAR
3733 * actually uses and we would otherwise have a
3734 * situation where we might allocate the excess to
3735 * another driver, which won't work.
3737 mapsize = pci_mapsize(testval);
3738 count = 1UL << mapsize;
3739 if (RF_ALIGNMENT(flags) < mapsize)
3740 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
3741 if (PCI_BAR_MEM(testval) && (testval & PCIM_BAR_MEM_PREFETCH))
3742 flags |= RF_PREFETCHABLE;
3745 * Allocate enough resource, and then write back the
3746 * appropriate bar for that resource.
3748 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
3749 start, end, count, flags, -1);
3751 device_printf(child,
3752 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
3753 count, *rid, type, start, end);
3756 resource_list_add(rl, type, *rid, start, end, count, -1);
3757 rle = resource_list_find(rl, type, *rid);
3759 panic("pci_alloc_map: unexpectedly can't find resource.");
3761 rle->start = rman_get_start(res);
3762 rle->end = rman_get_end(res);
3765 device_printf(child,
3766 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
3767 count, *rid, type, rman_get_start(res));
3768 map = rman_get_start(res);
3770 pci_write_config(child, *rid, map, 4);
3771 if (pci_maprange(testval) == 64)
3772 pci_write_config(child, *rid + 4, map >> 32, 4);
3778 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
3779 u_long start, u_long end, u_long count, u_int flags, int cpuid)
3781 struct pci_devinfo *dinfo = device_get_ivars(child);
3782 struct resource_list *rl = &dinfo->resources;
3783 struct resource_list_entry *rle;
3784 pcicfgregs *cfg = &dinfo->cfg;
3787 * Perform lazy resource allocation
3789 if (device_get_parent(child) == dev) {
3793 * Can't alloc legacy interrupt once MSI messages
3794 * have been allocated.
3796 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
3797 cfg->msix.msix_alloc > 0))
3800 * If the child device doesn't have an
3801 * interrupt routed and is deserving of an
3802 * interrupt, try to assign it one.
3804 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
3806 pci_assign_interrupt(dev, child, 0);
3808 case SYS_RES_IOPORT:
3809 case SYS_RES_MEMORY:
3810 if (*rid < PCIR_BAR(cfg->nummaps)) {
3812 * Enable the I/O mode. We should
3813 * also be assigning resources too
3814 * when none are present. The
3815 * resource_list_alloc kind of sorta does
3818 if (PCI_ENABLE_IO(dev, child, type))
3821 rle = resource_list_find(rl, type, *rid);
3823 return (pci_alloc_map(dev, child, type, rid,
3824 start, end, count, flags));
3828 * If we've already allocated the resource, then
3829 * return it now. But first we may need to activate
3830 * it, since we don't allocate the resource as active
3831 * above. Normally this would be done down in the
3832 * nexus, but since we short-circuit that path we have
3833 * to do its job here. Not sure if we should kfree the
3834 * resource if it fails to activate.
3836 rle = resource_list_find(rl, type, *rid);
3837 if (rle != NULL && rle->res != NULL) {
3839 device_printf(child,
3840 "Reserved %#lx bytes for rid %#x type %d at %#lx\n",
3841 rman_get_size(rle->res), *rid, type,
3842 rman_get_start(rle->res));
3843 if ((flags & RF_ACTIVE) &&
3844 bus_generic_activate_resource(dev, child, type,
3845 *rid, rle->res) != 0)
3850 return (resource_list_alloc(rl, dev, child, type, rid,
3851 start, end, count, flags, cpuid));
3855 pci_delete_resource(device_t dev, device_t child, int type, int rid)
3857 struct pci_devinfo *dinfo;
3858 struct resource_list *rl;
3859 struct resource_list_entry *rle;
3861 if (device_get_parent(child) != dev)
3864 dinfo = device_get_ivars(child);
3865 rl = &dinfo->resources;
3866 rle = resource_list_find(rl, type, rid);
3869 if (rman_get_device(rle->res) != dev ||
3870 rman_get_flags(rle->res) & RF_ACTIVE) {
3871 device_printf(dev, "delete_resource: "
3872 "Resource still owned by child, oops. "
3873 "(type=%d, rid=%d, addr=%lx)\n",
3874 rle->type, rle->rid,
3875 rman_get_start(rle->res));
3878 bus_release_resource(dev, type, rid, rle->res);
3880 resource_list_delete(rl, type, rid);
3883 * Why do we turn off the PCI configuration BAR when we delete a
3886 pci_write_config(child, rid, 0, 4);
3887 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid);
3890 struct resource_list *
3891 pci_get_resource_list (device_t dev, device_t child)
3893 struct pci_devinfo *dinfo = device_get_ivars(child);
3898 return (&dinfo->resources);
3902 pci_read_config_method(device_t dev, device_t child, int reg, int width)
3904 struct pci_devinfo *dinfo = device_get_ivars(child);
3905 pcicfgregs *cfg = &dinfo->cfg;
3907 return (PCIB_READ_CONFIG(device_get_parent(dev),
3908 cfg->bus, cfg->slot, cfg->func, reg, width));
3912 pci_write_config_method(device_t dev, device_t child, int reg,
3913 uint32_t val, int width)
3915 struct pci_devinfo *dinfo = device_get_ivars(child);
3916 pcicfgregs *cfg = &dinfo->cfg;
3918 PCIB_WRITE_CONFIG(device_get_parent(dev),
3919 cfg->bus, cfg->slot, cfg->func, reg, val, width);
3923 pci_child_location_str_method(device_t dev, device_t child, char *buf,
3927 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
3928 pci_get_function(child));
3933 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
3936 struct pci_devinfo *dinfo;
3939 dinfo = device_get_ivars(child);
3941 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
3942 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
3943 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
3949 pci_assign_interrupt_method(device_t dev, device_t child)
3951 struct pci_devinfo *dinfo = device_get_ivars(child);
3952 pcicfgregs *cfg = &dinfo->cfg;
3954 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
3959 pci_modevent(module_t mod, int what, void *arg)
3961 static struct cdev *pci_cdev;
3965 STAILQ_INIT(&pci_devq);
3967 pci_cdev = make_dev(&pcic_ops, 0, UID_ROOT, GID_WHEEL, 0644,
3969 pci_load_vendor_data();
3973 destroy_dev(pci_cdev);
3981 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
3986 * Only do header type 0 devices. Type 1 devices are bridges,
3987 * which we know need special treatment. Type 2 devices are
3988 * cardbus bridges which also require special treatment.
3989 * Other types are unknown, and we err on the side of safety
3992 if (dinfo->cfg.hdrtype != 0)
3996 * Restore the device to full power mode. We must do this
3997 * before we restore the registers because moving from D3 to
3998 * D0 will cause the chip's BARs and some other registers to
3999 * be reset to some unknown power on reset values. Cut down
4000 * the noise on boot by doing nothing if we are already in
4003 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
4004 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4006 for (i = 0; i < dinfo->cfg.nummaps; i++)
4007 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4);
4008 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
4009 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
4010 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
4011 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
4012 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
4013 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
4014 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
4015 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
4016 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
4017 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
4019 /* Restore MSI and MSI-X configurations if they are present. */
4020 if (dinfo->cfg.msi.msi_location != 0)
4021 pci_resume_msi(dev);
4022 if (dinfo->cfg.msix.msix_location != 0)
4023 pci_resume_msix(dev);
4027 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
4034 * Only do header type 0 devices. Type 1 devices are bridges, which
4035 * we know need special treatment. Type 2 devices are cardbus bridges
4036 * which also require special treatment. Other types are unknown, and
4037 * we err on the side of safety by ignoring them. Powering down
4038 * bridges should not be undertaken lightly.
4040 if (dinfo->cfg.hdrtype != 0)
4042 for (i = 0; i < dinfo->cfg.nummaps; i++)
4043 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4);
4044 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
4047 * Some drivers apparently write to these registers w/o updating our
4048 * cached copy. No harm happens if we update the copy, so do so here
4049 * so we can restore them. The COMMAND register is modified by the
4050 * bus w/o updating the cache. This should represent the normally
4051 * writable portion of the 'defined' part of type 0 headers. In
4052 * theory we also need to save/restore the PCI capability structures
4053 * we know about, but apart from power we don't know any that are
4056 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
4057 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4058 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
4059 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
4060 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
4061 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
4062 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
4063 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
4064 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
4065 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
4066 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
4067 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
4068 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
4069 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
4070 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
4073 * don't set the state for display devices, base peripherals and
4074 * memory devices since bad things happen when they are powered down.
4075 * We should (a) have drivers that can easily detach and (b) use
4076 * generic drivers for these devices so that some device actually
4077 * attaches. We need to make sure that when we implement (a) we don't
4078 * power the device down on a reattach.
4080 cls = pci_get_class(dev);
4083 switch (pci_do_power_nodriver)
4085 case 0: /* NO powerdown at all */
4087 case 1: /* Conservative about what to power down */
4088 if (cls == PCIC_STORAGE)
4091 case 2: /* Agressive about what to power down */
4092 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
4093 cls == PCIC_BASEPERIPH)
4096 case 3: /* Power down everything */
4100 * PCI spec says we can only go into D3 state from D0 state.
4101 * Transition from D[12] into D0 before going to D3 state.
4103 ps = pci_get_powerstate(dev);
4104 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
4105 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4106 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
4107 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
4110 #ifdef COMPAT_OLDPCI
4113 * Locate the parent of a PCI device by scanning the PCI devlist
4114 * and return the entry for the parent.
4115 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
4116 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
4119 pci_devlist_get_parent(pcicfgregs *cfg)
4121 struct devlist *devlist_head;
4122 struct pci_devinfo *dinfo;
4123 pcicfgregs *bridge_cfg;
4126 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
4128 /* If the device is on PCI bus 0, look for the host */
4129 if (cfg->bus == 0) {
4130 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
4131 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
4132 bridge_cfg = &dinfo->cfg;
4133 if (bridge_cfg->baseclass == PCIC_BRIDGE
4134 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
4135 && bridge_cfg->bus == cfg->bus) {
4141 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
4143 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
4144 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
4145 bridge_cfg = &dinfo->cfg;
4146 if (bridge_cfg->baseclass == PCIC_BRIDGE
4147 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
4148 && bridge_cfg->secondarybus == cfg->bus) {
4157 #endif /* COMPAT_OLDPCI */
4160 pci_alloc_1intr(device_t dev, int msi_enable, int *rid0, u_int *flags0)
4167 type = PCI_INTR_TYPE_LEGACY;
4168 flags = RF_SHAREABLE | RF_ACTIVE;
4170 ksnprintf(env, sizeof(env), "hw.%s.msi.enable",
4171 device_get_nameunit(dev));
4172 kgetenv_int(env, &msi_enable);
4177 ksnprintf(env, sizeof(env), "hw.%s.msi.cpu",
4178 device_get_nameunit(dev));
4179 kgetenv_int(env, &cpu);
4183 if (pci_alloc_msi(dev, &rid, 1, cpu) == 0) {
4184 flags &= ~RF_SHAREABLE;
4185 type = PCI_INTR_TYPE_MSI;