1 /******************************************************************************
3 Copyright (c) 2001-2011, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
35 #include "e1000_api.h"
37 static void e1000_reload_nvm_generic(struct e1000_hw *hw);
40 * e1000_init_nvm_ops_generic - Initialize NVM function pointers
41 * @hw: pointer to the HW structure
43 * Setups up the function pointers to no-op functions
45 void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
47 struct e1000_nvm_info *nvm = &hw->nvm;
48 DEBUGFUNC("e1000_init_nvm_ops_generic");
50 /* Initialize function pointers */
51 nvm->ops.init_params = e1000_null_ops_generic;
52 nvm->ops.acquire = e1000_null_ops_generic;
53 nvm->ops.read = e1000_null_read_nvm;
54 nvm->ops.release = e1000_null_nvm_generic;
55 nvm->ops.reload = e1000_reload_nvm_generic;
56 nvm->ops.update = e1000_null_ops_generic;
57 nvm->ops.valid_led_default = e1000_null_led_default;
58 nvm->ops.validate = e1000_null_ops_generic;
59 nvm->ops.write = e1000_null_write_nvm;
63 * e1000_null_nvm_read - No-op function, return 0
64 * @hw: pointer to the HW structure
66 s32 e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
68 DEBUGFUNC("e1000_null_read_nvm");
73 * e1000_null_nvm_generic - No-op function, return void
74 * @hw: pointer to the HW structure
76 void e1000_null_nvm_generic(struct e1000_hw *hw)
78 DEBUGFUNC("e1000_null_nvm_generic");
83 * e1000_null_led_default - No-op function, return 0
84 * @hw: pointer to the HW structure
86 s32 e1000_null_led_default(struct e1000_hw *hw, u16 *data)
88 DEBUGFUNC("e1000_null_led_default");
93 * e1000_null_write_nvm - No-op function, return 0
94 * @hw: pointer to the HW structure
96 s32 e1000_null_write_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
98 DEBUGFUNC("e1000_null_write_nvm");
103 * e1000_raise_eec_clk - Raise EEPROM clock
104 * @hw: pointer to the HW structure
105 * @eecd: pointer to the EEPROM
107 * Enable/Raise the EEPROM clock bit.
109 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
111 *eecd = *eecd | E1000_EECD_SK;
112 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
113 E1000_WRITE_FLUSH(hw);
114 usec_delay(hw->nvm.delay_usec);
118 * e1000_lower_eec_clk - Lower EEPROM clock
119 * @hw: pointer to the HW structure
120 * @eecd: pointer to the EEPROM
122 * Clear/Lower the EEPROM clock bit.
124 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
126 *eecd = *eecd & ~E1000_EECD_SK;
127 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
128 E1000_WRITE_FLUSH(hw);
129 usec_delay(hw->nvm.delay_usec);
133 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
134 * @hw: pointer to the HW structure
135 * @data: data to send to the EEPROM
136 * @count: number of bits to shift out
138 * We need to shift 'count' bits out to the EEPROM. So, the value in the
139 * "data" parameter will be shifted out to the EEPROM one bit at a time.
140 * In order to do this, "data" must be broken down into bits.
142 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
144 struct e1000_nvm_info *nvm = &hw->nvm;
145 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
148 DEBUGFUNC("e1000_shift_out_eec_bits");
150 mask = 0x01 << (count - 1);
151 if (nvm->type == e1000_nvm_eeprom_microwire)
152 eecd &= ~E1000_EECD_DO;
154 if (nvm->type == e1000_nvm_eeprom_spi)
155 eecd |= E1000_EECD_DO;
158 eecd &= ~E1000_EECD_DI;
161 eecd |= E1000_EECD_DI;
163 E1000_WRITE_REG(hw, E1000_EECD, eecd);
164 E1000_WRITE_FLUSH(hw);
166 usec_delay(nvm->delay_usec);
168 e1000_raise_eec_clk(hw, &eecd);
169 e1000_lower_eec_clk(hw, &eecd);
174 eecd &= ~E1000_EECD_DI;
175 E1000_WRITE_REG(hw, E1000_EECD, eecd);
179 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
180 * @hw: pointer to the HW structure
181 * @count: number of bits to shift in
183 * In order to read a register from the EEPROM, we need to shift 'count' bits
184 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
185 * the EEPROM (setting the SK bit), and then reading the value of the data out
186 * "DO" bit. During this "shifting in" process the data in "DI" bit should
189 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
195 DEBUGFUNC("e1000_shift_in_eec_bits");
197 eecd = E1000_READ_REG(hw, E1000_EECD);
199 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
202 for (i = 0; i < count; i++) {
204 e1000_raise_eec_clk(hw, &eecd);
206 eecd = E1000_READ_REG(hw, E1000_EECD);
208 eecd &= ~E1000_EECD_DI;
209 if (eecd & E1000_EECD_DO)
212 e1000_lower_eec_clk(hw, &eecd);
219 * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
220 * @hw: pointer to the HW structure
221 * @ee_reg: EEPROM flag for polling
223 * Polls the EEPROM status bit for either read or write completion based
224 * upon the value of 'ee_reg'.
226 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
228 u32 attempts = 100000;
231 DEBUGFUNC("e1000_poll_eerd_eewr_done");
233 for (i = 0; i < attempts; i++) {
234 if (ee_reg == E1000_NVM_POLL_READ)
235 reg = E1000_READ_REG(hw, E1000_EERD);
237 reg = E1000_READ_REG(hw, E1000_EEWR);
239 if (reg & E1000_NVM_RW_REG_DONE)
240 return E1000_SUCCESS;
245 return -E1000_ERR_NVM;
249 * e1000_acquire_nvm_generic - Generic request for access to EEPROM
250 * @hw: pointer to the HW structure
252 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
253 * Return successful if access grant bit set, else clear the request for
254 * EEPROM access and return -E1000_ERR_NVM (-1).
256 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
258 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
259 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
261 DEBUGFUNC("e1000_acquire_nvm_generic");
263 E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
264 eecd = E1000_READ_REG(hw, E1000_EECD);
267 if (eecd & E1000_EECD_GNT)
270 eecd = E1000_READ_REG(hw, E1000_EECD);
275 eecd &= ~E1000_EECD_REQ;
276 E1000_WRITE_REG(hw, E1000_EECD, eecd);
277 DEBUGOUT("Could not acquire NVM grant\n");
278 return -E1000_ERR_NVM;
281 return E1000_SUCCESS;
285 * e1000_standby_nvm - Return EEPROM to standby state
286 * @hw: pointer to the HW structure
288 * Return the EEPROM to a standby state.
290 static void e1000_standby_nvm(struct e1000_hw *hw)
292 struct e1000_nvm_info *nvm = &hw->nvm;
293 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
295 DEBUGFUNC("e1000_standby_nvm");
297 if (nvm->type == e1000_nvm_eeprom_microwire) {
298 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
299 E1000_WRITE_REG(hw, E1000_EECD, eecd);
300 E1000_WRITE_FLUSH(hw);
301 usec_delay(nvm->delay_usec);
303 e1000_raise_eec_clk(hw, &eecd);
306 eecd |= E1000_EECD_CS;
307 E1000_WRITE_REG(hw, E1000_EECD, eecd);
308 E1000_WRITE_FLUSH(hw);
309 usec_delay(nvm->delay_usec);
311 e1000_lower_eec_clk(hw, &eecd);
312 } else if (nvm->type == e1000_nvm_eeprom_spi) {
313 /* Toggle CS to flush commands */
314 eecd |= E1000_EECD_CS;
315 E1000_WRITE_REG(hw, E1000_EECD, eecd);
316 E1000_WRITE_FLUSH(hw);
317 usec_delay(nvm->delay_usec);
318 eecd &= ~E1000_EECD_CS;
319 E1000_WRITE_REG(hw, E1000_EECD, eecd);
320 E1000_WRITE_FLUSH(hw);
321 usec_delay(nvm->delay_usec);
326 * e1000_stop_nvm - Terminate EEPROM command
327 * @hw: pointer to the HW structure
329 * Terminates the current command by inverting the EEPROM's chip select pin.
331 #ifdef NO_82542_SUPPORT
332 static void e1000_stop_nvm(struct e1000_hw *hw)
334 void e1000_stop_nvm(struct e1000_hw *hw)
339 DEBUGFUNC("e1000_stop_nvm");
341 eecd = E1000_READ_REG(hw, E1000_EECD);
342 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
344 eecd |= E1000_EECD_CS;
345 e1000_lower_eec_clk(hw, &eecd);
346 } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
347 /* CS on Microwire is active-high */
348 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
349 E1000_WRITE_REG(hw, E1000_EECD, eecd);
350 e1000_raise_eec_clk(hw, &eecd);
351 e1000_lower_eec_clk(hw, &eecd);
356 * e1000_release_nvm_generic - Release exclusive access to EEPROM
357 * @hw: pointer to the HW structure
359 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
361 void e1000_release_nvm_generic(struct e1000_hw *hw)
365 DEBUGFUNC("e1000_release_nvm_generic");
369 eecd = E1000_READ_REG(hw, E1000_EECD);
370 eecd &= ~E1000_EECD_REQ;
371 E1000_WRITE_REG(hw, E1000_EECD, eecd);
375 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
376 * @hw: pointer to the HW structure
378 * Setups the EEPROM for reading and writing.
380 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
382 struct e1000_nvm_info *nvm = &hw->nvm;
383 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
386 DEBUGFUNC("e1000_ready_nvm_eeprom");
388 if (nvm->type == e1000_nvm_eeprom_microwire) {
389 /* Clear SK and DI */
390 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
391 E1000_WRITE_REG(hw, E1000_EECD, eecd);
393 eecd |= E1000_EECD_CS;
394 E1000_WRITE_REG(hw, E1000_EECD, eecd);
395 } else if (nvm->type == e1000_nvm_eeprom_spi) {
396 u16 timeout = NVM_MAX_RETRY_SPI;
398 /* Clear SK and CS */
399 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
400 E1000_WRITE_REG(hw, E1000_EECD, eecd);
401 E1000_WRITE_FLUSH(hw);
405 * Read "Status Register" repeatedly until the LSB is cleared.
406 * The EEPROM will signal that the command has been completed
407 * by clearing bit 0 of the internal status register. If it's
408 * not cleared within 'timeout', then error out.
411 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
412 hw->nvm.opcode_bits);
413 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
414 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
418 e1000_standby_nvm(hw);
423 DEBUGOUT("SPI NVM Status error\n");
424 return -E1000_ERR_NVM;
428 return E1000_SUCCESS;
432 * e1000_read_nvm_spi - Read EEPROM's using SPI
433 * @hw: pointer to the HW structure
434 * @offset: offset of word in the EEPROM to read
435 * @words: number of words to read
436 * @data: word read from the EEPROM
438 * Reads a 16 bit word from the EEPROM.
440 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
442 struct e1000_nvm_info *nvm = &hw->nvm;
446 u8 read_opcode = NVM_READ_OPCODE_SPI;
448 DEBUGFUNC("e1000_read_nvm_spi");
451 * A check for invalid values: offset too large, too many words,
452 * and not enough words.
454 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
456 DEBUGOUT("nvm parameter(s) out of bounds\n");
457 return -E1000_ERR_NVM;
460 ret_val = nvm->ops.acquire(hw);
464 ret_val = e1000_ready_nvm_eeprom(hw);
468 e1000_standby_nvm(hw);
470 if ((nvm->address_bits == 8) && (offset >= 128))
471 read_opcode |= NVM_A8_OPCODE_SPI;
473 /* Send the READ command (opcode + addr) */
474 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
475 e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
478 * Read the data. SPI NVMs increment the address with each byte
479 * read and will roll over if reading beyond the end. This allows
480 * us to read the whole NVM from any offset
482 for (i = 0; i < words; i++) {
483 word_in = e1000_shift_in_eec_bits(hw, 16);
484 data[i] = (word_in >> 8) | (word_in << 8);
488 nvm->ops.release(hw);
494 * e1000_read_nvm_microwire - Reads EEPROM's using microwire
495 * @hw: pointer to the HW structure
496 * @offset: offset of word in the EEPROM to read
497 * @words: number of words to read
498 * @data: word read from the EEPROM
500 * Reads a 16 bit word from the EEPROM.
502 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
505 struct e1000_nvm_info *nvm = &hw->nvm;
508 u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
510 DEBUGFUNC("e1000_read_nvm_microwire");
513 * A check for invalid values: offset too large, too many words,
514 * and not enough words.
516 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
518 DEBUGOUT("nvm parameter(s) out of bounds\n");
519 return -E1000_ERR_NVM;
522 ret_val = nvm->ops.acquire(hw);
526 ret_val = e1000_ready_nvm_eeprom(hw);
530 for (i = 0; i < words; i++) {
531 /* Send the READ command (opcode + addr) */
532 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
533 e1000_shift_out_eec_bits(hw, (u16)(offset + i),
537 * Read the data. For microwire, each word requires the
538 * overhead of setup and tear-down.
540 data[i] = e1000_shift_in_eec_bits(hw, 16);
541 e1000_standby_nvm(hw);
545 nvm->ops.release(hw);
551 * e1000_read_nvm_eerd - Reads EEPROM using EERD register
552 * @hw: pointer to the HW structure
553 * @offset: offset of word in the EEPROM to read
554 * @words: number of words to read
555 * @data: word read from the EEPROM
557 * Reads a 16 bit word from the EEPROM using the EERD register.
559 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
561 struct e1000_nvm_info *nvm = &hw->nvm;
563 s32 ret_val = E1000_SUCCESS;
565 DEBUGFUNC("e1000_read_nvm_eerd");
568 * A check for invalid values: offset too large, too many words,
569 * too many words for the offset, and not enough words.
571 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
573 DEBUGOUT("nvm parameter(s) out of bounds\n");
574 return -E1000_ERR_NVM;
577 for (i = 0; i < words; i++) {
578 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
579 E1000_NVM_RW_REG_START;
581 E1000_WRITE_REG(hw, E1000_EERD, eerd);
582 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
586 data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
587 E1000_NVM_RW_REG_DATA);
594 * e1000_write_nvm_spi - Write to EEPROM using SPI
595 * @hw: pointer to the HW structure
596 * @offset: offset within the EEPROM to be written to
597 * @words: number of words to write
598 * @data: 16 bit word(s) to be written to the EEPROM
600 * Writes data to EEPROM at offset using SPI interface.
602 * If e1000_update_nvm_checksum is not called after this function , the
603 * EEPROM will most likely contain an invalid checksum.
605 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
607 struct e1000_nvm_info *nvm = &hw->nvm;
611 DEBUGFUNC("e1000_write_nvm_spi");
614 * A check for invalid values: offset too large, too many words,
615 * and not enough words.
617 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
619 DEBUGOUT("nvm parameter(s) out of bounds\n");
620 return -E1000_ERR_NVM;
623 ret_val = nvm->ops.acquire(hw);
627 while (widx < words) {
628 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
630 ret_val = e1000_ready_nvm_eeprom(hw);
634 e1000_standby_nvm(hw);
636 /* Send the WRITE ENABLE command (8 bit opcode) */
637 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
640 e1000_standby_nvm(hw);
643 * Some SPI eeproms use the 8th address bit embedded in the
646 if ((nvm->address_bits == 8) && (offset >= 128))
647 write_opcode |= NVM_A8_OPCODE_SPI;
649 /* Send the Write command (8-bit opcode + addr) */
650 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
651 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
654 /* Loop to allow for up to whole page write of eeprom */
655 while (widx < words) {
656 u16 word_out = data[widx];
657 word_out = (word_out >> 8) | (word_out << 8);
658 e1000_shift_out_eec_bits(hw, word_out, 16);
661 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
662 e1000_standby_nvm(hw);
670 nvm->ops.release(hw);
676 * e1000_write_nvm_microwire - Writes EEPROM using microwire
677 * @hw: pointer to the HW structure
678 * @offset: offset within the EEPROM to be written to
679 * @words: number of words to write
680 * @data: 16 bit word(s) to be written to the EEPROM
682 * Writes data to EEPROM at offset using microwire interface.
684 * If e1000_update_nvm_checksum is not called after this function , the
685 * EEPROM will most likely contain an invalid checksum.
687 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
690 struct e1000_nvm_info *nvm = &hw->nvm;
693 u16 words_written = 0;
696 DEBUGFUNC("e1000_write_nvm_microwire");
699 * A check for invalid values: offset too large, too many words,
700 * and not enough words.
702 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
704 DEBUGOUT("nvm parameter(s) out of bounds\n");
705 return -E1000_ERR_NVM;
708 ret_val = nvm->ops.acquire(hw);
712 ret_val = e1000_ready_nvm_eeprom(hw);
716 e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
717 (u16)(nvm->opcode_bits + 2));
719 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
721 e1000_standby_nvm(hw);
723 while (words_written < words) {
724 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
727 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
730 e1000_shift_out_eec_bits(hw, data[words_written], 16);
732 e1000_standby_nvm(hw);
734 for (widx = 0; widx < 200; widx++) {
735 eecd = E1000_READ_REG(hw, E1000_EECD);
736 if (eecd & E1000_EECD_DO)
742 DEBUGOUT("NVM Write did not complete\n");
743 ret_val = -E1000_ERR_NVM;
747 e1000_standby_nvm(hw);
752 e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
753 (u16)(nvm->opcode_bits + 2));
755 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
758 nvm->ops.release(hw);
764 * e1000_read_pba_string_generic - Read device part number
765 * @hw: pointer to the HW structure
766 * @pba_num: pointer to device part number
767 * @pba_num_size: size of part number buffer
769 * Reads the product board assembly (PBA) number from the EEPROM and stores
770 * the value in pba_num.
772 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
781 DEBUGFUNC("e1000_read_pba_string_generic");
783 if (pba_num == NULL) {
784 DEBUGOUT("PBA string buffer was null\n");
785 return -E1000_ERR_INVALID_ARGUMENT;
788 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
790 DEBUGOUT("NVM Read Error\n");
794 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
796 DEBUGOUT("NVM Read Error\n");
801 * if nvm_data is not ptr guard the PBA must be in legacy format which
802 * means pba_ptr is actually our second data word for the PBA number
803 * and we can decode it into an ascii string
805 if (nvm_data != NVM_PBA_PTR_GUARD) {
806 DEBUGOUT("NVM PBA number is not stored as string\n");
808 /* make sure callers buffer is big enough to store the PBA */
809 if (pba_num_size < E1000_PBANUM_LENGTH) {
810 DEBUGOUT("PBA string buffer too small\n");
811 return E1000_ERR_NO_SPACE;
814 /* extract hex string from data and pba_ptr */
815 pba_num[0] = (nvm_data >> 12) & 0xF;
816 pba_num[1] = (nvm_data >> 8) & 0xF;
817 pba_num[2] = (nvm_data >> 4) & 0xF;
818 pba_num[3] = nvm_data & 0xF;
819 pba_num[4] = (pba_ptr >> 12) & 0xF;
820 pba_num[5] = (pba_ptr >> 8) & 0xF;
823 pba_num[8] = (pba_ptr >> 4) & 0xF;
824 pba_num[9] = pba_ptr & 0xF;
826 /* put a null character on the end of our string */
829 /* switch all the data but the '-' to hex char */
830 for (offset = 0; offset < 10; offset++) {
831 if (pba_num[offset] < 0xA)
832 pba_num[offset] += '0';
833 else if (pba_num[offset] < 0x10)
834 pba_num[offset] += 'A' - 0xA;
837 return E1000_SUCCESS;
840 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
842 DEBUGOUT("NVM Read Error\n");
846 if (length == 0xFFFF || length == 0) {
847 DEBUGOUT("NVM PBA number section invalid length\n");
848 return -E1000_ERR_NVM_PBA_SECTION;
850 /* check if pba_num buffer is big enough */
851 if (pba_num_size < (((u32)length * 2) - 1)) {
852 DEBUGOUT("PBA string buffer too small\n");
853 return -E1000_ERR_NO_SPACE;
856 /* trim pba length from start of string */
860 for (offset = 0; offset < length; offset++) {
861 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
863 DEBUGOUT("NVM Read Error\n");
866 pba_num[offset * 2] = (u8)(nvm_data >> 8);
867 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
869 pba_num[offset * 2] = '\0';
871 return E1000_SUCCESS;
875 * e1000_read_pba_length_generic - Read device part number length
876 * @hw: pointer to the HW structure
877 * @pba_num_size: size of part number buffer
879 * Reads the product board assembly (PBA) number length from the EEPROM and
880 * stores the value in pba_num_size.
882 s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size)
889 DEBUGFUNC("e1000_read_pba_length_generic");
891 if (pba_num_size == NULL) {
892 DEBUGOUT("PBA buffer size was null\n");
893 return -E1000_ERR_INVALID_ARGUMENT;
896 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
898 DEBUGOUT("NVM Read Error\n");
902 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
904 DEBUGOUT("NVM Read Error\n");
908 /* if data is not ptr guard the PBA must be in legacy format */
909 if (nvm_data != NVM_PBA_PTR_GUARD) {
910 *pba_num_size = E1000_PBANUM_LENGTH;
911 return E1000_SUCCESS;
914 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
916 DEBUGOUT("NVM Read Error\n");
920 if (length == 0xFFFF || length == 0) {
921 DEBUGOUT("NVM PBA number section invalid length\n");
922 return -E1000_ERR_NVM_PBA_SECTION;
926 * Convert from length in u16 values to u8 chars, add 1 for NULL,
927 * and subtract 2 because length field is included in length.
929 *pba_num_size = ((u32)length * 2) - 1;
931 return E1000_SUCCESS;
935 * e1000_read_pba_num_generic - Read device part number
936 * @hw: pointer to the HW structure
937 * @pba_num: pointer to device part number
939 * Reads the product board assembly (PBA) number from the EEPROM and stores
940 * the value in pba_num.
942 s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num)
947 DEBUGFUNC("e1000_read_pba_num_generic");
949 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
951 DEBUGOUT("NVM Read Error\n");
953 } else if (nvm_data == NVM_PBA_PTR_GUARD) {
954 DEBUGOUT("NVM Not Supported\n");
955 return -E1000_NOT_IMPLEMENTED;
957 *pba_num = (u32)(nvm_data << 16);
959 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
961 DEBUGOUT("NVM Read Error\n");
964 *pba_num |= nvm_data;
966 return E1000_SUCCESS;
971 * @hw: pointer to the HW structure
972 * @eeprom_buf: optional pointer to EEPROM image
973 * @eeprom_buf_size: size of EEPROM image in words
974 * @max_pba_block_size: PBA block size limit
975 * @pba: pointer to output PBA structure
977 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
978 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
981 s32 e1000_read_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
982 u32 eeprom_buf_size, u16 max_pba_block_size,
983 struct e1000_pba *pba)
989 return -E1000_ERR_PARAM;
991 if (eeprom_buf == NULL) {
992 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2,
997 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
998 pba->word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
999 pba->word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
1001 return -E1000_ERR_PARAM;
1005 if (pba->word[0] == NVM_PBA_PTR_GUARD) {
1006 if (pba->pba_block == NULL)
1007 return -E1000_ERR_PARAM;
1009 ret_val = e1000_get_pba_block_size(hw, eeprom_buf,
1015 if (pba_block_size > max_pba_block_size)
1016 return -E1000_ERR_PARAM;
1018 if (eeprom_buf == NULL) {
1019 ret_val = e1000_read_nvm(hw, pba->word[1],
1025 if (eeprom_buf_size > (u32)(pba->word[1] +
1026 pba->pba_block[0])) {
1027 memcpy(pba->pba_block,
1028 &eeprom_buf[pba->word[1]],
1029 pba_block_size * sizeof(u16));
1031 return -E1000_ERR_PARAM;
1036 return E1000_SUCCESS;
1040 * e1000_write_pba_raw
1041 * @hw: pointer to the HW structure
1042 * @eeprom_buf: optional pointer to EEPROM image
1043 * @eeprom_buf_size: size of EEPROM image in words
1044 * @pba: pointer to PBA structure
1046 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
1047 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
1050 s32 e1000_write_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
1051 u32 eeprom_buf_size, struct e1000_pba *pba)
1056 return -E1000_ERR_PARAM;
1058 if (eeprom_buf == NULL) {
1059 ret_val = e1000_write_nvm(hw, NVM_PBA_OFFSET_0, 2,
1064 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1065 eeprom_buf[NVM_PBA_OFFSET_0] = pba->word[0];
1066 eeprom_buf[NVM_PBA_OFFSET_1] = pba->word[1];
1068 return -E1000_ERR_PARAM;
1072 if (pba->word[0] == NVM_PBA_PTR_GUARD) {
1073 if (pba->pba_block == NULL)
1074 return -E1000_ERR_PARAM;
1076 if (eeprom_buf == NULL) {
1077 ret_val = e1000_write_nvm(hw, pba->word[1],
1083 if (eeprom_buf_size > (u32)(pba->word[1] +
1084 pba->pba_block[0])) {
1085 memcpy(&eeprom_buf[pba->word[1]],
1087 pba->pba_block[0] * sizeof(u16));
1089 return -E1000_ERR_PARAM;
1094 return E1000_SUCCESS;
1098 * e1000_get_pba_block_size
1099 * @hw: pointer to the HW structure
1100 * @eeprom_buf: optional pointer to EEPROM image
1101 * @eeprom_buf_size: size of EEPROM image in words
1102 * @pba_data_size: pointer to output variable
1104 * Returns the size of the PBA block in words. Function operates on EEPROM
1105 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
1109 s32 e1000_get_pba_block_size(struct e1000_hw *hw, u16 *eeprom_buf,
1110 u32 eeprom_buf_size, u16 *pba_block_size)
1116 DEBUGFUNC("e1000_get_pba_block_size");
1118 if (eeprom_buf == NULL) {
1119 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, &pba_word[0]);
1123 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1124 pba_word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
1125 pba_word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
1127 return -E1000_ERR_PARAM;
1131 if (pba_word[0] == NVM_PBA_PTR_GUARD) {
1132 if (eeprom_buf == NULL) {
1133 ret_val = e1000_read_nvm(hw, pba_word[1] + 0, 1,
1138 if (eeprom_buf_size > pba_word[1])
1139 length = eeprom_buf[pba_word[1] + 0];
1141 return -E1000_ERR_PARAM;
1144 if (length == 0xFFFF || length == 0)
1145 return -E1000_ERR_NVM_PBA_SECTION;
1147 /* PBA number in legacy format, there is no PBA Block. */
1151 if (pba_block_size != NULL)
1152 *pba_block_size = length;
1154 return E1000_SUCCESS;
1158 * e1000_read_mac_addr_generic - Read device MAC address
1159 * @hw: pointer to the HW structure
1161 * Reads the device MAC address from the EEPROM and stores the value.
1162 * Since devices with two ports use the same EEPROM, we increment the
1163 * last bit in the MAC address for the second port.
1165 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
1171 rar_high = E1000_READ_REG(hw, E1000_RAH(0));
1172 rar_low = E1000_READ_REG(hw, E1000_RAL(0));
1174 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
1175 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
1177 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
1178 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
1180 for (i = 0; i < ETH_ADDR_LEN; i++)
1181 hw->mac.addr[i] = hw->mac.perm_addr[i];
1183 return E1000_SUCCESS;
1187 * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
1188 * @hw: pointer to the HW structure
1190 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
1191 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
1193 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
1199 DEBUGFUNC("e1000_validate_nvm_checksum_generic");
1201 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1202 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1204 DEBUGOUT("NVM Read Error\n");
1207 checksum += nvm_data;
1210 if (checksum != (u16) NVM_SUM) {
1211 DEBUGOUT("NVM Checksum Invalid\n");
1212 return -E1000_ERR_NVM;
1215 return E1000_SUCCESS;
1219 * e1000_update_nvm_checksum_generic - Update EEPROM checksum
1220 * @hw: pointer to the HW structure
1222 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
1223 * up to the checksum. Then calculates the EEPROM checksum and writes the
1224 * value to the EEPROM.
1226 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
1232 DEBUGFUNC("e1000_update_nvm_checksum");
1234 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
1235 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1237 DEBUGOUT("NVM Read Error while updating checksum.\n");
1240 checksum += nvm_data;
1242 checksum = (u16) NVM_SUM - checksum;
1243 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
1245 DEBUGOUT("NVM Write Error while updating checksum.\n");
1251 * e1000_reload_nvm_generic - Reloads EEPROM
1252 * @hw: pointer to the HW structure
1254 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
1255 * extended control register.
1257 static void e1000_reload_nvm_generic(struct e1000_hw *hw)
1261 DEBUGFUNC("e1000_reload_nvm_generic");
1264 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1265 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1266 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1267 E1000_WRITE_FLUSH(hw);
1271 * e1000_get_fw_version - Get firmware version information
1272 * @hw: pointer to the HW structure
1273 * @fw_vers: pointer to output version structure
1275 * unsupported/not present features return 0 in version structure
1277 void e1000_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers)
1279 u16 eeprom_verh, eeprom_verl, fw_version;
1280 u16 comb_verh, comb_verl, comb_offset;
1282 memset(fw_vers, 0, sizeof(struct e1000_fw_version));
1284 /* this code only applies to certain mac types */
1285 switch (hw->mac.type) {
1287 e1000_read_invm_version(hw, fw_vers);
1299 /* basic eeprom version numbers */
1300 hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
1301 fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT;
1302 fw_vers->eep_minor = (fw_version & NVM_MINOR_MASK);
1305 hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl);
1306 hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh);
1307 fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT) | eeprom_verl;
1309 switch (hw->mac.type) {
1312 /* find combo image version */
1313 hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset);
1314 if ((comb_offset != 0x0) &&
1315 (comb_offset != NVM_VER_INVALID)) {
1317 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset
1318 + 1), 1, &comb_verh);
1319 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset),
1322 /* get Option Rom version if it exists and is valid */
1323 if ((comb_verh && comb_verl) &&
1324 ((comb_verh != NVM_VER_INVALID) &&
1325 (comb_verl != NVM_VER_INVALID))) {
1327 fw_vers->or_valid = TRUE;
1329 comb_verl >> NVM_COMB_VER_SHFT;
1331 (comb_verl << NVM_COMB_VER_SHFT)
1332 | (comb_verh >> NVM_COMB_VER_SHFT);
1334 comb_verh & NVM_COMB_VER_MASK;