2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
135 #include <drm/drmP.h>
136 #include <drm/i915_drm.h>
137 #include "i915_drv.h"
138 #include "intel_drv.h"
139 #include "intel_mocs.h"
141 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
143 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
145 #define RING_EXECLIST_QFULL (1 << 0x2)
146 #define RING_EXECLIST1_VALID (1 << 0x3)
147 #define RING_EXECLIST0_VALID (1 << 0x4)
148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
149 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
150 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
159 #define CTX_LRI_HEADER_0 0x01
160 #define CTX_CONTEXT_CONTROL 0x02
161 #define CTX_RING_HEAD 0x04
162 #define CTX_RING_TAIL 0x06
163 #define CTX_RING_BUFFER_START 0x08
164 #define CTX_RING_BUFFER_CONTROL 0x0a
165 #define CTX_BB_HEAD_U 0x0c
166 #define CTX_BB_HEAD_L 0x0e
167 #define CTX_BB_STATE 0x10
168 #define CTX_SECOND_BB_HEAD_U 0x12
169 #define CTX_SECOND_BB_HEAD_L 0x14
170 #define CTX_SECOND_BB_STATE 0x16
171 #define CTX_BB_PER_CTX_PTR 0x18
172 #define CTX_RCS_INDIRECT_CTX 0x1a
173 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
174 #define CTX_LRI_HEADER_1 0x21
175 #define CTX_CTX_TIMESTAMP 0x22
176 #define CTX_PDP3_UDW 0x24
177 #define CTX_PDP3_LDW 0x26
178 #define CTX_PDP2_UDW 0x28
179 #define CTX_PDP2_LDW 0x2a
180 #define CTX_PDP1_UDW 0x2c
181 #define CTX_PDP1_LDW 0x2e
182 #define CTX_PDP0_UDW 0x30
183 #define CTX_PDP0_LDW 0x32
184 #define CTX_LRI_HEADER_2 0x41
185 #define CTX_R_PWR_CLK_STATE 0x42
186 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
188 #define GEN8_CTX_VALID (1<<0)
189 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
190 #define GEN8_CTX_FORCE_RESTORE (1<<2)
191 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
192 #define GEN8_CTX_PRIVILEGE (1<<8)
194 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \
195 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
196 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
197 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
201 ADVANCED_CONTEXT = 0,
206 #define GEN8_CTX_MODE_SHIFT 3
209 FAULT_AND_HALT, /* Debug only */
211 FAULT_AND_CONTINUE /* Unsupported */
213 #define GEN8_CTX_ID_SHIFT 32
214 #define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
216 static int intel_lr_context_pin(struct drm_i915_gem_request *rq);
219 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
221 * @enable_execlists: value of i915.enable_execlists module parameter.
223 * Only certain platforms support Execlists (the prerequisites being
224 * support for Logical Ring Contexts and Aliasing PPGTT or better).
226 * Return: 1 if Execlists is supported and has to be enabled.
228 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
230 WARN_ON(i915.enable_ppgtt == -1);
232 if (INTEL_INFO(dev)->gen >= 9)
235 if (enable_execlists == 0)
238 if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
239 i915.use_mmio_flip >= 0)
246 * intel_execlists_ctx_id() - get the Execlists Context ID
247 * @ctx_obj: Logical Ring Context backing object.
249 * Do not confuse with ctx->id! Unfortunately we have a name overload
250 * here: the old context ID we pass to userspace as a handler so that
251 * they can refer to a context, and the new context ID we pass to the
252 * ELSP so that the GPU can inform us of the context status via
255 * Return: 20-bits globally unique context ID.
257 u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
259 u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj);
261 /* LRCA is required to be 4K aligned so the more significant 20 bits
262 * are globally unique */
266 static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_request *rq)
268 struct intel_engine_cs *ring = rq->ring;
269 struct drm_device *dev = ring->dev;
270 struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
272 uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj);
274 WARN_ON(lrca & 0xFFFFFFFF00000FFFULL);
276 desc = GEN8_CTX_VALID;
277 desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT;
278 if (IS_GEN8(ctx_obj->base.dev))
279 desc |= GEN8_CTX_L3LLC_COHERENT;
280 desc |= GEN8_CTX_PRIVILEGE;
282 desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT;
284 /* TODO: WaDisableLiteRestore when we start using semaphore
285 * signalling between Command Streamers */
286 /* desc |= GEN8_CTX_FORCE_RESTORE; */
288 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
290 INTEL_REVID(dev) <= SKL_REVID_B0 &&
291 (ring->id == BCS || ring->id == VCS ||
292 ring->id == VECS || ring->id == VCS2))
293 desc |= GEN8_CTX_FORCE_RESTORE;
298 static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
299 struct drm_i915_gem_request *rq1)
302 struct intel_engine_cs *ring = rq0->ring;
303 struct drm_device *dev = ring->dev;
304 struct drm_i915_private *dev_priv = dev->dev_private;
308 desc[1] = execlists_ctx_descriptor(rq1);
309 rq1->elsp_submitted++;
314 desc[0] = execlists_ctx_descriptor(rq0);
315 rq0->elsp_submitted++;
317 /* You must always write both descriptors in the order below. */
318 lockmgr(&dev_priv->uncore.lock, LK_EXCLUSIVE);
319 intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);
320 I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[1]));
321 I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[1]));
323 I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[0]));
324 /* The context is automatically loaded after the following */
325 I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[0]));
327 /* ELSP is a wo register, use another nearby reg for posting */
328 POSTING_READ_FW(RING_EXECLIST_STATUS(ring));
329 intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
330 lockmgr(&dev_priv->uncore.lock, LK_RELEASE);
333 static int execlists_update_context(struct drm_i915_gem_request *rq)
335 struct intel_engine_cs *ring = rq->ring;
336 struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
337 struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
338 struct drm_i915_gem_object *rb_obj = rq->ringbuf->obj;
339 struct vm_page *page;
343 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj));
344 WARN_ON(!i915_gem_obj_is_pinned(rb_obj));
346 page = i915_gem_object_get_page(ctx_obj, 1);
347 reg_state = kmap_atomic(page);
349 reg_state[CTX_RING_TAIL+1] = rq->tail;
350 reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(rb_obj);
352 /* True PPGTT with dynamic page allocation: update PDP registers and
353 * point the unallocated PDPs to the scratch page
356 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
357 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
358 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
359 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
362 kunmap_atomic(reg_state);
367 static void execlists_submit_requests(struct drm_i915_gem_request *rq0,
368 struct drm_i915_gem_request *rq1)
370 execlists_update_context(rq0);
373 execlists_update_context(rq1);
375 execlists_elsp_write(rq0, rq1);
378 static void execlists_context_unqueue(struct intel_engine_cs *ring)
380 struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
381 struct drm_i915_gem_request *cursor = NULL, *tmp = NULL;
383 assert_spin_locked(&ring->execlist_lock);
386 * If irqs are not active generate a warning as batches that finish
387 * without the irqs may get lost and a GPU Hang may occur.
389 WARN_ON(!intel_irqs_enabled(ring->dev->dev_private));
391 if (list_empty(&ring->execlist_queue))
394 /* Try to read in pairs */
395 list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue,
399 } else if (req0->ctx == cursor->ctx) {
400 /* Same ctx: ignore first request, as second request
401 * will update tail past first request's workload */
402 cursor->elsp_submitted = req0->elsp_submitted;
403 list_del(&req0->execlist_link);
404 list_add_tail(&req0->execlist_link,
405 &ring->execlist_retired_req_list);
413 if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) {
415 * WaIdleLiteRestore: make sure we never cause a lite
416 * restore with HEAD==TAIL
418 if (req0->elsp_submitted) {
420 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL
421 * as we resubmit the request. See gen8_emit_request()
422 * for where we prepare the padding after the end of the
425 struct intel_ringbuffer *ringbuf;
427 ringbuf = req0->ctx->engine[ring->id].ringbuf;
429 req0->tail &= ringbuf->size - 1;
433 WARN_ON(req1 && req1->elsp_submitted);
435 execlists_submit_requests(req0, req1);
438 static bool execlists_check_remove_request(struct intel_engine_cs *ring,
441 struct drm_i915_gem_request *head_req;
443 assert_spin_locked(&ring->execlist_lock);
445 head_req = list_first_entry_or_null(&ring->execlist_queue,
446 struct drm_i915_gem_request,
449 if (head_req != NULL) {
450 struct drm_i915_gem_object *ctx_obj =
451 head_req->ctx->engine[ring->id].state;
452 if (intel_execlists_ctx_id(ctx_obj) == request_id) {
453 WARN(head_req->elsp_submitted == 0,
454 "Never submitted head request\n");
456 if (--head_req->elsp_submitted <= 0) {
457 list_del(&head_req->execlist_link);
458 list_add_tail(&head_req->execlist_link,
459 &ring->execlist_retired_req_list);
469 * intel_lrc_irq_handler() - handle Context Switch interrupts
470 * @ring: Engine Command Streamer to handle.
472 * Check the unread Context Status Buffers and manage the submission of new
473 * contexts to the ELSP accordingly.
475 void intel_lrc_irq_handler(struct intel_engine_cs *ring)
477 struct drm_i915_private *dev_priv = ring->dev->dev_private;
483 u32 submit_contexts = 0;
485 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
487 read_pointer = ring->next_context_status_buffer;
488 write_pointer = status_pointer & GEN8_CSB_PTR_MASK;
489 if (read_pointer > write_pointer)
490 write_pointer += GEN8_CSB_ENTRIES;
492 lockmgr(&ring->execlist_lock, LK_EXCLUSIVE);
494 while (read_pointer < write_pointer) {
496 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
497 (read_pointer % GEN8_CSB_ENTRIES) * 8);
498 status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
499 (read_pointer % GEN8_CSB_ENTRIES) * 8 + 4);
501 if (status & GEN8_CTX_STATUS_IDLE_ACTIVE)
504 if (status & GEN8_CTX_STATUS_PREEMPTED) {
505 if (status & GEN8_CTX_STATUS_LITE_RESTORE) {
506 if (execlists_check_remove_request(ring, status_id))
507 WARN(1, "Lite Restored request removed from queue\n");
509 WARN(1, "Preemption without Lite Restore\n");
512 if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) ||
513 (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) {
514 if (execlists_check_remove_request(ring, status_id))
519 if (submit_contexts != 0)
520 execlists_context_unqueue(ring);
522 lockmgr(&ring->execlist_lock, LK_RELEASE);
524 WARN(submit_contexts > 2, "More than two context complete events?\n");
525 ring->next_context_status_buffer = write_pointer % GEN8_CSB_ENTRIES;
527 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring),
528 _MASKED_FIELD(GEN8_CSB_PTR_MASK << 8,
529 ((u32)ring->next_context_status_buffer &
530 GEN8_CSB_PTR_MASK) << 8));
533 static int execlists_context_queue(struct drm_i915_gem_request *request)
535 struct intel_engine_cs *ring = request->ring;
536 struct drm_i915_gem_request *cursor;
537 int num_elements = 0;
539 if (request->ctx != ring->default_context)
540 intel_lr_context_pin(request);
542 i915_gem_request_reference(request);
544 request->tail = request->ringbuf->tail;
546 lockmgr(&ring->execlist_lock, LK_EXCLUSIVE);
548 list_for_each_entry(cursor, &ring->execlist_queue, execlist_link)
549 if (++num_elements > 2)
552 if (num_elements > 2) {
553 struct drm_i915_gem_request *tail_req;
555 tail_req = list_last_entry(&ring->execlist_queue,
556 struct drm_i915_gem_request,
559 if (request->ctx == tail_req->ctx) {
560 WARN(tail_req->elsp_submitted != 0,
561 "More than 2 already-submitted reqs queued\n");
562 list_del(&tail_req->execlist_link);
563 list_add_tail(&tail_req->execlist_link,
564 &ring->execlist_retired_req_list);
568 list_add_tail(&request->execlist_link, &ring->execlist_queue);
569 if (num_elements == 0)
570 execlists_context_unqueue(ring);
572 lockmgr(&ring->execlist_lock, LK_RELEASE);
577 static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
579 struct intel_engine_cs *ring = req->ring;
580 uint32_t flush_domains;
584 if (ring->gpu_caches_dirty)
585 flush_domains = I915_GEM_GPU_DOMAINS;
587 ret = ring->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
591 ring->gpu_caches_dirty = false;
595 static int execlists_move_to_gpu(struct drm_i915_gem_request *req,
596 struct list_head *vmas)
598 const unsigned other_rings = ~intel_ring_flag(req->ring);
599 struct i915_vma *vma;
600 uint32_t flush_domains = 0;
601 bool flush_chipset = false;
604 list_for_each_entry(vma, vmas, exec_list) {
605 struct drm_i915_gem_object *obj = vma->obj;
607 if (obj->active & other_rings) {
608 ret = i915_gem_object_sync(obj, req->ring, &req);
613 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
614 flush_chipset |= i915_gem_clflush_object(obj, false);
616 flush_domains |= obj->base.write_domain;
619 if (flush_domains & I915_GEM_DOMAIN_GTT)
622 /* Unconditionally invalidate gpu caches and ensure that we do flush
623 * any residual writes from the previous batch.
625 return logical_ring_invalidate_all_caches(req);
628 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request)
632 request->ringbuf = request->ctx->engine[request->ring->id].ringbuf;
634 if (request->ctx != request->ring->default_context) {
635 ret = intel_lr_context_pin(request);
643 static int logical_ring_wait_for_space(struct drm_i915_gem_request *req,
646 struct intel_ringbuffer *ringbuf = req->ringbuf;
647 struct intel_engine_cs *ring = req->ring;
648 struct drm_i915_gem_request *target;
652 if (intel_ring_space(ringbuf) >= bytes)
655 /* The whole point of reserving space is to not wait! */
656 WARN_ON(ringbuf->reserved_in_use);
658 list_for_each_entry(target, &ring->request_list, list) {
660 * The request queue is per-engine, so can contain requests
661 * from multiple ringbuffers. Here, we must ignore any that
662 * aren't from the ringbuffer we're considering.
664 if (target->ringbuf != ringbuf)
667 /* Would completion of this request free enough space? */
668 space = __intel_ring_space(target->postfix, ringbuf->tail,
674 if (WARN_ON(&target->list == &ring->request_list))
677 ret = i915_wait_request(target);
681 ringbuf->space = space;
686 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
687 * @request: Request to advance the logical ringbuffer of.
689 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
690 * really happens during submission is that the context and current tail will be placed
691 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
692 * point, the tail *inside* the context is updated and the ELSP written to.
695 intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
697 struct intel_engine_cs *ring = request->ring;
699 intel_logical_ring_advance(request->ringbuf);
701 if (intel_ring_stopped(ring))
704 execlists_context_queue(request);
707 static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
709 uint32_t __iomem *virt;
710 int rem = ringbuf->size - ringbuf->tail;
712 virt = (uint32_t *)(ringbuf->virtual_start + ringbuf->tail);
715 iowrite32(MI_NOOP, virt++);
718 intel_ring_update_space(ringbuf);
721 static int logical_ring_prepare(struct drm_i915_gem_request *req, int bytes)
723 struct intel_ringbuffer *ringbuf = req->ringbuf;
724 int remain_usable = ringbuf->effective_size - ringbuf->tail;
725 int remain_actual = ringbuf->size - ringbuf->tail;
726 int ret, total_bytes, wait_bytes = 0;
727 bool need_wrap = false;
729 if (ringbuf->reserved_in_use)
732 total_bytes = bytes + ringbuf->reserved_size;
734 if (unlikely(bytes > remain_usable)) {
736 * Not enough space for the basic request. So need to flush
737 * out the remainder and then wait for base + reserved.
739 wait_bytes = remain_actual + total_bytes;
742 if (unlikely(total_bytes > remain_usable)) {
744 * The base request will fit but the reserved space
745 * falls off the end. So only need to to wait for the
746 * reserved size after flushing out the remainder.
748 wait_bytes = remain_actual + ringbuf->reserved_size;
750 } else if (total_bytes > ringbuf->space) {
751 /* No wrapping required, just waiting. */
752 wait_bytes = total_bytes;
757 ret = logical_ring_wait_for_space(req, wait_bytes);
762 __wrap_ring_buffer(ringbuf);
769 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
771 * @request: The request to start some new work for
772 * @ctx: Logical ring context whose ringbuffer is being prepared.
773 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
775 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
776 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
777 * and also preallocates a request (every workload submission is still mediated through
778 * requests, same as it did with legacy ringbuffer submission).
780 * Return: non-zero if the ringbuffer is not ready to be written to.
782 int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
784 struct drm_i915_private *dev_priv;
787 WARN_ON(req == NULL);
788 dev_priv = req->ring->dev->dev_private;
790 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
791 dev_priv->mm.interruptible);
795 ret = logical_ring_prepare(req, num_dwords * sizeof(uint32_t));
799 req->ringbuf->space -= num_dwords * sizeof(uint32_t);
803 int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request)
806 * The first call merely notes the reserve request and is common for
807 * all back ends. The subsequent localised _begin() call actually
808 * ensures that the reservation is available. Without the begin, if
809 * the request creator immediately submitted the request without
810 * adding any commands to it then there might not actually be
811 * sufficient room for the submission commands.
813 intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
815 return intel_logical_ring_begin(request, 0);
819 * execlists_submission() - submit a batchbuffer for execution, Execlists style
822 * @ring: Engine Command Streamer to submit to.
823 * @ctx: Context to employ for this submission.
824 * @args: execbuffer call arguments.
825 * @vmas: list of vmas.
826 * @batch_obj: the batchbuffer to submit.
827 * @exec_start: batchbuffer start virtual address pointer.
828 * @dispatch_flags: translated execbuffer call flags.
830 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
831 * away the submission details of the execbuffer ioctl call.
833 * Return: non-zero if the submission fails.
835 int intel_execlists_submission(struct i915_execbuffer_params *params,
836 struct drm_i915_gem_execbuffer2 *args,
837 struct list_head *vmas)
839 struct drm_device *dev = params->dev;
840 struct intel_engine_cs *ring = params->ring;
841 struct drm_i915_private *dev_priv = dev->dev_private;
842 struct intel_ringbuffer *ringbuf = params->ctx->engine[ring->id].ringbuf;
848 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
849 instp_mask = I915_EXEC_CONSTANTS_MASK;
850 switch (instp_mode) {
851 case I915_EXEC_CONSTANTS_REL_GENERAL:
852 case I915_EXEC_CONSTANTS_ABSOLUTE:
853 case I915_EXEC_CONSTANTS_REL_SURFACE:
854 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
855 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
859 if (instp_mode != dev_priv->relative_constants_mode) {
860 if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
861 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
865 /* The HW changed the meaning on this bit on gen6 */
866 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
870 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
874 if (args->num_cliprects != 0) {
875 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
878 if (args->DR4 == 0xffffffff) {
879 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
883 if (args->DR1 || args->DR4 || args->cliprects_ptr) {
884 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
889 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
890 DRM_DEBUG("sol reset is gen7 only\n");
894 ret = execlists_move_to_gpu(params->request, vmas);
898 if (ring == &dev_priv->ring[RCS] &&
899 instp_mode != dev_priv->relative_constants_mode) {
900 ret = intel_logical_ring_begin(params->request, 4);
904 intel_logical_ring_emit(ringbuf, MI_NOOP);
905 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
906 intel_logical_ring_emit(ringbuf, INSTPM);
907 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
908 intel_logical_ring_advance(ringbuf);
910 dev_priv->relative_constants_mode = instp_mode;
913 exec_start = params->batch_obj_vm_offset +
914 args->batch_start_offset;
916 ret = ring->emit_bb_start(params->request, exec_start, params->dispatch_flags);
920 trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
922 i915_gem_execbuffer_move_to_active(vmas, params->request);
923 i915_gem_execbuffer_retire_commands(params);
928 void intel_execlists_retire_requests(struct intel_engine_cs *ring)
930 struct drm_i915_gem_request *req, *tmp;
931 struct list_head retired_list;
933 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
934 if (list_empty(&ring->execlist_retired_req_list))
937 INIT_LIST_HEAD(&retired_list);
938 lockmgr(&ring->execlist_lock, LK_EXCLUSIVE);
939 list_replace_init(&ring->execlist_retired_req_list, &retired_list);
940 lockmgr(&ring->execlist_lock, LK_RELEASE);
942 list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
943 struct intel_context *ctx = req->ctx;
944 struct drm_i915_gem_object *ctx_obj =
945 ctx->engine[ring->id].state;
947 if (ctx_obj && (ctx != ring->default_context))
948 intel_lr_context_unpin(req);
949 list_del(&req->execlist_link);
950 i915_gem_request_unreference(req);
954 void intel_logical_ring_stop(struct intel_engine_cs *ring)
956 struct drm_i915_private *dev_priv = ring->dev->dev_private;
959 if (!intel_ring_initialized(ring))
962 ret = intel_ring_idle(ring);
963 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
964 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
967 /* TODO: Is this correct with Execlists enabled? */
968 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
969 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
970 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
973 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
976 int logical_ring_flush_all_caches(struct drm_i915_gem_request *req)
978 struct intel_engine_cs *ring = req->ring;
981 if (!ring->gpu_caches_dirty)
984 ret = ring->emit_flush(req, 0, I915_GEM_GPU_DOMAINS);
988 ring->gpu_caches_dirty = false;
992 static int intel_lr_context_pin(struct drm_i915_gem_request *rq)
994 struct intel_engine_cs *ring = rq->ring;
995 struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
996 struct intel_ringbuffer *ringbuf = rq->ringbuf;
999 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1000 if (rq->ctx->engine[ring->id].pin_count++ == 0) {
1001 ret = i915_gem_obj_ggtt_pin(ctx_obj,
1002 GEN8_LR_CONTEXT_ALIGN, 0);
1004 goto reset_pin_count;
1006 ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf);
1010 ctx_obj->dirty = true;
1016 i915_gem_object_ggtt_unpin(ctx_obj);
1018 rq->ctx->engine[ring->id].pin_count = 0;
1023 void intel_lr_context_unpin(struct drm_i915_gem_request *rq)
1025 struct intel_engine_cs *ring = rq->ring;
1026 struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
1027 struct intel_ringbuffer *ringbuf = rq->ringbuf;
1030 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1031 if (--rq->ctx->engine[ring->id].pin_count == 0) {
1032 intel_unpin_ringbuffer_obj(ringbuf);
1033 i915_gem_object_ggtt_unpin(ctx_obj);
1038 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
1041 struct intel_engine_cs *ring = req->ring;
1042 struct intel_ringbuffer *ringbuf = req->ringbuf;
1043 struct drm_device *dev = ring->dev;
1044 struct drm_i915_private *dev_priv = dev->dev_private;
1045 struct i915_workarounds *w = &dev_priv->workarounds;
1047 if (WARN_ON_ONCE(w->count == 0))
1050 ring->gpu_caches_dirty = true;
1051 ret = logical_ring_flush_all_caches(req);
1055 ret = intel_logical_ring_begin(req, w->count * 2 + 2);
1059 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
1060 for (i = 0; i < w->count; i++) {
1061 intel_logical_ring_emit(ringbuf, w->reg[i].addr);
1062 intel_logical_ring_emit(ringbuf, w->reg[i].value);
1064 intel_logical_ring_emit(ringbuf, MI_NOOP);
1066 intel_logical_ring_advance(ringbuf);
1068 ring->gpu_caches_dirty = true;
1069 ret = logical_ring_flush_all_caches(req);
1076 #define wa_ctx_emit(batch, index, cmd) \
1078 int __index = (index)++; \
1079 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1082 batch[__index] = (cmd); \
1087 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1088 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1089 * but there is a slight complication as this is applied in WA batch where the
1090 * values are only initialized once so we cannot take register value at the
1091 * beginning and reuse it further; hence we save its value to memory, upload a
1092 * constant value with bit21 set and then we restore it back with the saved value.
1093 * To simplify the WA, a constant value is formed by using the default value
1094 * of this register. This shouldn't be a problem because we are only modifying
1095 * it for a short period and this batch in non-premptible. We can ofcourse
1096 * use additional instructions that read the actual value of the register
1097 * at that time and set our bit of interest but it makes the WA complicated.
1099 * This WA is also required for Gen9 so extracting as a function avoids
1102 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *ring,
1103 uint32_t *const batch,
1106 uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);
1109 * WaDisableLSQCROPERFforOCL:skl
1110 * This WA is implemented in skl_init_clock_gating() but since
1111 * this batch updates GEN8_L3SQCREG4 with default value we need to
1112 * set this bit here to retain the WA during flush.
1114 if (IS_SKYLAKE(ring->dev) && INTEL_REVID(ring->dev) <= SKL_REVID_E0)
1115 l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;
1117 wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8(1) |
1118 MI_SRM_LRM_GLOBAL_GTT));
1119 wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
1120 wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);
1121 wa_ctx_emit(batch, index, 0);
1123 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1124 wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
1125 wa_ctx_emit(batch, index, l3sqc4_flush);
1127 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1128 wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL |
1129 PIPE_CONTROL_DC_FLUSH_ENABLE));
1130 wa_ctx_emit(batch, index, 0);
1131 wa_ctx_emit(batch, index, 0);
1132 wa_ctx_emit(batch, index, 0);
1133 wa_ctx_emit(batch, index, 0);
1135 wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8(1) |
1136 MI_SRM_LRM_GLOBAL_GTT));
1137 wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
1138 wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);
1139 wa_ctx_emit(batch, index, 0);
1144 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx,
1146 uint32_t start_alignment)
1148 return wa_ctx->offset = ALIGN(offset, start_alignment);
1151 static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx,
1153 uint32_t size_alignment)
1155 wa_ctx->size = offset - wa_ctx->offset;
1157 WARN(wa_ctx->size % size_alignment,
1158 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1159 wa_ctx->size, size_alignment);
1164 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
1166 * @ring: only applicable for RCS
1167 * @wa_ctx: structure representing wa_ctx
1168 * offset: specifies start of the batch, should be cache-aligned. This is updated
1169 * with the offset value received as input.
1170 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1171 * @batch: page in which WA are loaded
1172 * @offset: This field specifies the start of the batch, it should be
1173 * cache-aligned otherwise it is adjusted accordingly.
1174 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1175 * initialized at the beginning and shared across all contexts but this field
1176 * helps us to have multiple batches at different offsets and select them based
1177 * on a criteria. At the moment this batch always start at the beginning of the page
1178 * and at this point we don't have multiple wa_ctx batch buffers.
1180 * The number of WA applied are not known at the beginning; we use this field
1181 * to return the no of DWORDS written.
1183 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1184 * so it adds NOOPs as padding to make it cacheline aligned.
1185 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1186 * makes a complete batch buffer.
1188 * Return: non-zero if we exceed the PAGE_SIZE limit.
1191 static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring,
1192 struct i915_wa_ctx_bb *wa_ctx,
1193 uint32_t *const batch,
1196 uint32_t scratch_addr;
1197 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1199 /* WaDisableCtxRestoreArbitration:bdw,chv */
1200 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1202 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1203 if (IS_BROADWELL(ring->dev)) {
1204 index = gen8_emit_flush_coherentl3_wa(ring, batch, index);
1209 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1210 /* Actual scratch location is at 128 bytes offset */
1211 scratch_addr = ring->scratch.gtt_offset + 2*CACHELINE_BYTES;
1213 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1214 wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
1215 PIPE_CONTROL_GLOBAL_GTT_IVB |
1216 PIPE_CONTROL_CS_STALL |
1217 PIPE_CONTROL_QW_WRITE));
1218 wa_ctx_emit(batch, index, scratch_addr);
1219 wa_ctx_emit(batch, index, 0);
1220 wa_ctx_emit(batch, index, 0);
1221 wa_ctx_emit(batch, index, 0);
1223 /* Pad to end of cacheline */
1224 while (index % CACHELINE_DWORDS)
1225 wa_ctx_emit(batch, index, MI_NOOP);
1228 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1229 * execution depends on the length specified in terms of cache lines
1230 * in the register CTX_RCS_INDIRECT_CTX
1233 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1237 * gen8_init_perctx_bb() - initialize per ctx batch with WA
1239 * @ring: only applicable for RCS
1240 * @wa_ctx: structure representing wa_ctx
1241 * offset: specifies start of the batch, should be cache-aligned.
1242 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1243 * @batch: page in which WA are loaded
1244 * @offset: This field specifies the start of this batch.
1245 * This batch is started immediately after indirect_ctx batch. Since we ensure
1246 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1248 * The number of DWORDS written are returned using this field.
1250 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1251 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1253 static int gen8_init_perctx_bb(struct intel_engine_cs *ring,
1254 struct i915_wa_ctx_bb *wa_ctx,
1255 uint32_t *const batch,
1258 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1260 /* WaDisableCtxRestoreArbitration:bdw,chv */
1261 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1263 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1265 return wa_ctx_end(wa_ctx, *offset = index, 1);
1268 static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring,
1269 struct i915_wa_ctx_bb *wa_ctx,
1270 uint32_t *const batch,
1274 struct drm_device *dev = ring->dev;
1275 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1277 /* WaDisableCtxRestoreArbitration:skl,bxt */
1278 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) ||
1279 (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0)))
1280 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1282 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1283 ret = gen8_emit_flush_coherentl3_wa(ring, batch, index);
1288 /* Pad to end of cacheline */
1289 while (index % CACHELINE_DWORDS)
1290 wa_ctx_emit(batch, index, MI_NOOP);
1292 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1295 static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
1296 struct i915_wa_ctx_bb *wa_ctx,
1297 uint32_t *const batch,
1300 struct drm_device *dev = ring->dev;
1301 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1303 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1304 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) ||
1305 (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) {
1306 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1307 wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
1308 wa_ctx_emit(batch, index,
1309 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING));
1310 wa_ctx_emit(batch, index, MI_NOOP);
1313 /* WaDisableCtxRestoreArbitration:skl,bxt */
1314 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) ||
1315 (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0)))
1316 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1318 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1320 return wa_ctx_end(wa_ctx, *offset = index, 1);
1323 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *ring, u32 size)
1327 ring->wa_ctx.obj = i915_gem_alloc_object(ring->dev, PAGE_ALIGN(size));
1328 if (!ring->wa_ctx.obj) {
1329 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1333 ret = i915_gem_obj_ggtt_pin(ring->wa_ctx.obj, PAGE_SIZE, 0);
1335 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1337 drm_gem_object_unreference(&ring->wa_ctx.obj->base);
1344 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *ring)
1346 if (ring->wa_ctx.obj) {
1347 i915_gem_object_ggtt_unpin(ring->wa_ctx.obj);
1348 drm_gem_object_unreference(&ring->wa_ctx.obj->base);
1349 ring->wa_ctx.obj = NULL;
1353 static int intel_init_workaround_bb(struct intel_engine_cs *ring)
1358 struct vm_page *page;
1359 struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx;
1361 WARN_ON(ring->id != RCS);
1363 /* update this when WA for higher Gen are added */
1364 if (INTEL_INFO(ring->dev)->gen > 9) {
1365 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1366 INTEL_INFO(ring->dev)->gen);
1370 /* some WA perform writes to scratch page, ensure it is valid */
1371 if (ring->scratch.obj == NULL) {
1372 DRM_ERROR("scratch page not allocated for %s\n", ring->name);
1376 ret = lrc_setup_wa_ctx_obj(ring, PAGE_SIZE);
1378 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
1382 page = i915_gem_object_get_page(wa_ctx->obj, 0);
1383 batch = kmap_atomic(page);
1386 if (INTEL_INFO(ring->dev)->gen == 8) {
1387 ret = gen8_init_indirectctx_bb(ring,
1388 &wa_ctx->indirect_ctx,
1394 ret = gen8_init_perctx_bb(ring,
1400 } else if (INTEL_INFO(ring->dev)->gen == 9) {
1401 ret = gen9_init_indirectctx_bb(ring,
1402 &wa_ctx->indirect_ctx,
1408 ret = gen9_init_perctx_bb(ring,
1417 kunmap_atomic(batch);
1419 lrc_destroy_wa_ctx_obj(ring);
1424 static int gen8_init_common_ring(struct intel_engine_cs *ring)
1426 struct drm_device *dev = ring->dev;
1427 struct drm_i915_private *dev_priv = dev->dev_private;
1428 u8 next_context_status_buffer_hw;
1430 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1431 I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);
1433 if (ring->status_page.obj) {
1434 I915_WRITE(RING_HWS_PGA(ring->mmio_base),
1435 (u32)ring->status_page.gfx_addr);
1436 POSTING_READ(RING_HWS_PGA(ring->mmio_base));
1439 I915_WRITE(RING_MODE_GEN7(ring),
1440 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1441 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1442 POSTING_READ(RING_MODE_GEN7(ring));
1445 * Instead of resetting the Context Status Buffer (CSB) read pointer to
1446 * zero, we need to read the write pointer from hardware and use its
1447 * value because "this register is power context save restored".
1448 * Effectively, these states have been observed:
1450 * | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) |
1451 * BDW | CSB regs not reset | CSB regs reset |
1452 * CHT | CSB regs not reset | CSB regs not reset |
1454 next_context_status_buffer_hw = (I915_READ(RING_CONTEXT_STATUS_PTR(ring))
1455 & GEN8_CSB_PTR_MASK);
1458 * When the CSB registers are reset (also after power-up / gpu reset),
1459 * CSB write pointer is set to all 1's, which is not valid, use '5' in
1460 * this special case, so the first element read is CSB[0].
1462 if (next_context_status_buffer_hw == GEN8_CSB_PTR_MASK)
1463 next_context_status_buffer_hw = (GEN8_CSB_ENTRIES - 1);
1465 ring->next_context_status_buffer = next_context_status_buffer_hw;
1466 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name);
1468 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
1473 static int gen8_init_render_ring(struct intel_engine_cs *ring)
1475 struct drm_device *dev = ring->dev;
1476 struct drm_i915_private *dev_priv = dev->dev_private;
1479 ret = gen8_init_common_ring(ring);
1483 /* We need to disable the AsyncFlip performance optimisations in order
1484 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1485 * programmed to '1' on all products.
1487 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1489 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1491 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1493 return init_workarounds_ring(ring);
1496 static int gen9_init_render_ring(struct intel_engine_cs *ring)
1500 ret = gen8_init_common_ring(ring);
1504 return init_workarounds_ring(ring);
1507 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
1509 struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
1510 struct intel_engine_cs *ring = req->ring;
1511 struct intel_ringbuffer *ringbuf = req->ringbuf;
1512 const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
1515 ret = intel_logical_ring_begin(req, num_lri_cmds * 2 + 2);
1519 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds));
1520 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
1521 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1523 intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_UDW(ring, i));
1524 intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr));
1525 intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_LDW(ring, i));
1526 intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr));
1529 intel_logical_ring_emit(ringbuf, MI_NOOP);
1530 intel_logical_ring_advance(ringbuf);
1535 static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
1536 u64 offset, unsigned dispatch_flags)
1538 struct intel_ringbuffer *ringbuf = req->ringbuf;
1539 bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
1542 /* Don't rely in hw updating PDPs, specially in lite-restore.
1543 * Ideally, we should set Force PD Restore in ctx descriptor,
1544 * but we can't. Force Restore would be a second option, but
1545 * it is unsafe in case of lite-restore (because the ctx is
1547 if (req->ctx->ppgtt &&
1548 (intel_ring_flag(req->ring) & req->ctx->ppgtt->pd_dirty_rings)) {
1549 ret = intel_logical_ring_emit_pdps(req);
1553 req->ctx->ppgtt->pd_dirty_rings &= ~intel_ring_flag(req->ring);
1556 ret = intel_logical_ring_begin(req, 4);
1560 /* FIXME(BDW): Address space and security selectors. */
1561 intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 |
1563 (dispatch_flags & I915_DISPATCH_RS ?
1564 MI_BATCH_RESOURCE_STREAMER : 0));
1565 intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
1566 intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
1567 intel_logical_ring_emit(ringbuf, MI_NOOP);
1568 intel_logical_ring_advance(ringbuf);
1573 static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring)
1575 struct drm_device *dev = ring->dev;
1576 struct drm_i915_private *dev_priv = dev->dev_private;
1578 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1581 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1582 if (ring->irq_refcount++ == 0) {
1583 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1584 POSTING_READ(RING_IMR(ring->mmio_base));
1586 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1591 static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring)
1593 struct drm_device *dev = ring->dev;
1594 struct drm_i915_private *dev_priv = dev->dev_private;
1596 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1597 if (--ring->irq_refcount == 0) {
1598 I915_WRITE_IMR(ring, ~ring->irq_keep_mask);
1599 POSTING_READ(RING_IMR(ring->mmio_base));
1601 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1604 static int gen8_emit_flush(struct drm_i915_gem_request *request,
1605 u32 invalidate_domains,
1608 struct intel_ringbuffer *ringbuf = request->ringbuf;
1609 struct intel_engine_cs *ring = ringbuf->ring;
1610 struct drm_device *dev = ring->dev;
1611 struct drm_i915_private *dev_priv = dev->dev_private;
1615 ret = intel_logical_ring_begin(request, 4);
1619 cmd = MI_FLUSH_DW + 1;
1621 /* We always require a command barrier so that subsequent
1622 * commands, such as breadcrumb interrupts, are strictly ordered
1623 * wrt the contents of the write cache being flushed to memory
1624 * (and thus being coherent from the CPU).
1626 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1628 if (invalidate_domains & I915_GEM_GPU_DOMAINS) {
1629 cmd |= MI_INVALIDATE_TLB;
1630 if (ring == &dev_priv->ring[VCS])
1631 cmd |= MI_INVALIDATE_BSD;
1634 intel_logical_ring_emit(ringbuf, cmd);
1635 intel_logical_ring_emit(ringbuf,
1636 I915_GEM_HWS_SCRATCH_ADDR |
1637 MI_FLUSH_DW_USE_GTT);
1638 intel_logical_ring_emit(ringbuf, 0); /* upper addr */
1639 intel_logical_ring_emit(ringbuf, 0); /* value */
1640 intel_logical_ring_advance(ringbuf);
1645 static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
1646 u32 invalidate_domains,
1649 struct intel_ringbuffer *ringbuf = request->ringbuf;
1650 struct intel_engine_cs *ring = ringbuf->ring;
1651 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1656 flags |= PIPE_CONTROL_CS_STALL;
1658 if (flush_domains) {
1659 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1660 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1661 flags |= PIPE_CONTROL_FLUSH_ENABLE;
1664 if (invalidate_domains) {
1665 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1666 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1667 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1668 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1669 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1670 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1671 flags |= PIPE_CONTROL_QW_WRITE;
1672 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1676 * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe
1679 vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 &&
1680 flags & PIPE_CONTROL_VF_CACHE_INVALIDATE;
1682 ret = intel_logical_ring_begin(request, vf_flush_wa ? 12 : 6);
1687 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1688 intel_logical_ring_emit(ringbuf, 0);
1689 intel_logical_ring_emit(ringbuf, 0);
1690 intel_logical_ring_emit(ringbuf, 0);
1691 intel_logical_ring_emit(ringbuf, 0);
1692 intel_logical_ring_emit(ringbuf, 0);
1695 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1696 intel_logical_ring_emit(ringbuf, flags);
1697 intel_logical_ring_emit(ringbuf, scratch_addr);
1698 intel_logical_ring_emit(ringbuf, 0);
1699 intel_logical_ring_emit(ringbuf, 0);
1700 intel_logical_ring_emit(ringbuf, 0);
1701 intel_logical_ring_advance(ringbuf);
1706 static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1708 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1711 static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1713 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1716 static int gen8_emit_request(struct drm_i915_gem_request *request)
1718 struct intel_ringbuffer *ringbuf = request->ringbuf;
1719 struct intel_engine_cs *ring = ringbuf->ring;
1724 * Reserve space for 2 NOOPs at the end of each request to be
1725 * used as a workaround for not being allowed to do lite
1726 * restore with HEAD==TAIL (WaIdleLiteRestore).
1728 ret = intel_logical_ring_begin(request, 8);
1732 cmd = MI_STORE_DWORD_IMM_GEN4;
1733 cmd |= MI_GLOBAL_GTT;
1735 intel_logical_ring_emit(ringbuf, cmd);
1736 intel_logical_ring_emit(ringbuf,
1737 (ring->status_page.gfx_addr +
1738 (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
1739 intel_logical_ring_emit(ringbuf, 0);
1740 intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
1741 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1742 intel_logical_ring_emit(ringbuf, MI_NOOP);
1743 intel_logical_ring_advance_and_submit(request);
1746 * Here we add two extra NOOPs as padding to avoid
1747 * lite restore of a context with HEAD==TAIL.
1749 intel_logical_ring_emit(ringbuf, MI_NOOP);
1750 intel_logical_ring_emit(ringbuf, MI_NOOP);
1751 intel_logical_ring_advance(ringbuf);
1756 static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req)
1758 struct render_state so;
1761 ret = i915_gem_render_state_prepare(req->ring, &so);
1765 if (so.rodata == NULL)
1768 ret = req->ring->emit_bb_start(req, so.ggtt_offset,
1769 I915_DISPATCH_SECURE);
1773 ret = req->ring->emit_bb_start(req,
1774 (so.ggtt_offset + so.aux_batch_offset),
1775 I915_DISPATCH_SECURE);
1779 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req);
1782 i915_gem_render_state_fini(&so);
1786 static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
1790 ret = intel_logical_ring_workarounds_emit(req);
1794 ret = intel_rcs_context_init_mocs(req);
1796 * Failing to program the MOCS is non-fatal.The system will not
1797 * run at peak performance. So generate an error and carry on.
1800 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1802 return intel_lr_context_render_state_init(req);
1806 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1808 * @ring: Engine Command Streamer.
1811 void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
1813 struct drm_i915_private *dev_priv;
1815 if (!intel_ring_initialized(ring))
1818 dev_priv = ring->dev->dev_private;
1820 intel_logical_ring_stop(ring);
1821 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1824 ring->cleanup(ring);
1826 i915_cmd_parser_fini_ring(ring);
1827 i915_gem_batch_pool_fini(&ring->batch_pool);
1829 if (ring->status_page.obj) {
1830 kunmap(sg_page(ring->status_page.obj->pages->sgl));
1831 ring->status_page.obj = NULL;
1834 lrc_destroy_wa_ctx_obj(ring);
1837 static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring)
1841 /* Intentionally left blank. */
1842 ring->buffer = NULL;
1845 INIT_LIST_HEAD(&ring->active_list);
1846 INIT_LIST_HEAD(&ring->request_list);
1847 i915_gem_batch_pool_init(dev, &ring->batch_pool);
1848 init_waitqueue_head(&ring->irq_queue);
1850 INIT_LIST_HEAD(&ring->execlist_queue);
1851 INIT_LIST_HEAD(&ring->execlist_retired_req_list);
1852 lockinit(&ring->execlist_lock, "i915el", 0, LK_CANRECURSE);
1854 ret = i915_cmd_parser_init_ring(ring);
1858 ret = intel_lr_context_deferred_create(ring->default_context, ring);
1863 static int logical_render_ring_init(struct drm_device *dev)
1865 struct drm_i915_private *dev_priv = dev->dev_private;
1866 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
1869 ring->name = "render ring";
1871 ring->mmio_base = RENDER_RING_BASE;
1872 ring->irq_enable_mask =
1873 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1874 ring->irq_keep_mask =
1875 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1876 if (HAS_L3_DPF(dev))
1877 ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1879 if (INTEL_INFO(dev)->gen >= 9)
1880 ring->init_hw = gen9_init_render_ring;
1882 ring->init_hw = gen8_init_render_ring;
1883 ring->init_context = gen8_init_rcs_context;
1884 ring->cleanup = intel_fini_pipe_control;
1885 ring->get_seqno = gen8_get_seqno;
1886 ring->set_seqno = gen8_set_seqno;
1887 ring->emit_request = gen8_emit_request;
1888 ring->emit_flush = gen8_emit_flush_render;
1889 ring->irq_get = gen8_logical_ring_get_irq;
1890 ring->irq_put = gen8_logical_ring_put_irq;
1891 ring->emit_bb_start = gen8_emit_bb_start;
1895 ret = intel_init_pipe_control(ring);
1899 ret = intel_init_workaround_bb(ring);
1902 * We continue even if we fail to initialize WA batch
1903 * because we only expect rare glitches but nothing
1904 * critical to prevent us from using GPU
1906 DRM_ERROR("WA batch buffer initialization failed: %d\n",
1910 ret = logical_ring_init(dev, ring);
1912 lrc_destroy_wa_ctx_obj(ring);
1918 static int logical_bsd_ring_init(struct drm_device *dev)
1920 struct drm_i915_private *dev_priv = dev->dev_private;
1921 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
1923 ring->name = "bsd ring";
1925 ring->mmio_base = GEN6_BSD_RING_BASE;
1926 ring->irq_enable_mask =
1927 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1928 ring->irq_keep_mask =
1929 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1931 ring->init_hw = gen8_init_common_ring;
1932 ring->get_seqno = gen8_get_seqno;
1933 ring->set_seqno = gen8_set_seqno;
1934 ring->emit_request = gen8_emit_request;
1935 ring->emit_flush = gen8_emit_flush;
1936 ring->irq_get = gen8_logical_ring_get_irq;
1937 ring->irq_put = gen8_logical_ring_put_irq;
1938 ring->emit_bb_start = gen8_emit_bb_start;
1940 return logical_ring_init(dev, ring);
1943 static int logical_bsd2_ring_init(struct drm_device *dev)
1945 struct drm_i915_private *dev_priv = dev->dev_private;
1946 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
1948 ring->name = "bds2 ring";
1950 ring->mmio_base = GEN8_BSD2_RING_BASE;
1951 ring->irq_enable_mask =
1952 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1953 ring->irq_keep_mask =
1954 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1956 ring->init_hw = gen8_init_common_ring;
1957 ring->get_seqno = gen8_get_seqno;
1958 ring->set_seqno = gen8_set_seqno;
1959 ring->emit_request = gen8_emit_request;
1960 ring->emit_flush = gen8_emit_flush;
1961 ring->irq_get = gen8_logical_ring_get_irq;
1962 ring->irq_put = gen8_logical_ring_put_irq;
1963 ring->emit_bb_start = gen8_emit_bb_start;
1965 return logical_ring_init(dev, ring);
1968 static int logical_blt_ring_init(struct drm_device *dev)
1970 struct drm_i915_private *dev_priv = dev->dev_private;
1971 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
1973 ring->name = "blitter ring";
1975 ring->mmio_base = BLT_RING_BASE;
1976 ring->irq_enable_mask =
1977 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1978 ring->irq_keep_mask =
1979 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1981 ring->init_hw = gen8_init_common_ring;
1982 ring->get_seqno = gen8_get_seqno;
1983 ring->set_seqno = gen8_set_seqno;
1984 ring->emit_request = gen8_emit_request;
1985 ring->emit_flush = gen8_emit_flush;
1986 ring->irq_get = gen8_logical_ring_get_irq;
1987 ring->irq_put = gen8_logical_ring_put_irq;
1988 ring->emit_bb_start = gen8_emit_bb_start;
1990 return logical_ring_init(dev, ring);
1993 static int logical_vebox_ring_init(struct drm_device *dev)
1995 struct drm_i915_private *dev_priv = dev->dev_private;
1996 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
1998 ring->name = "video enhancement ring";
2000 ring->mmio_base = VEBOX_RING_BASE;
2001 ring->irq_enable_mask =
2002 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2003 ring->irq_keep_mask =
2004 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2006 ring->init_hw = gen8_init_common_ring;
2007 ring->get_seqno = gen8_get_seqno;
2008 ring->set_seqno = gen8_set_seqno;
2009 ring->emit_request = gen8_emit_request;
2010 ring->emit_flush = gen8_emit_flush;
2011 ring->irq_get = gen8_logical_ring_get_irq;
2012 ring->irq_put = gen8_logical_ring_put_irq;
2013 ring->emit_bb_start = gen8_emit_bb_start;
2015 return logical_ring_init(dev, ring);
2019 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
2022 * This function inits the engines for an Execlists submission style (the equivalent in the
2023 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
2024 * those engines that are present in the hardware.
2026 * Return: non-zero if the initialization failed.
2028 int intel_logical_rings_init(struct drm_device *dev)
2030 struct drm_i915_private *dev_priv = dev->dev_private;
2033 ret = logical_render_ring_init(dev);
2038 ret = logical_bsd_ring_init(dev);
2040 goto cleanup_render_ring;
2044 ret = logical_blt_ring_init(dev);
2046 goto cleanup_bsd_ring;
2049 if (HAS_VEBOX(dev)) {
2050 ret = logical_vebox_ring_init(dev);
2052 goto cleanup_blt_ring;
2055 if (HAS_BSD2(dev)) {
2056 ret = logical_bsd2_ring_init(dev);
2058 goto cleanup_vebox_ring;
2061 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
2063 goto cleanup_bsd2_ring;
2068 intel_logical_ring_cleanup(&dev_priv->ring[VCS2]);
2070 intel_logical_ring_cleanup(&dev_priv->ring[VECS]);
2072 intel_logical_ring_cleanup(&dev_priv->ring[BCS]);
2074 intel_logical_ring_cleanup(&dev_priv->ring[VCS]);
2075 cleanup_render_ring:
2076 intel_logical_ring_cleanup(&dev_priv->ring[RCS]);
2082 make_rpcs(struct drm_device *dev)
2087 * No explicit RPCS request is needed to ensure full
2088 * slice/subslice/EU enablement prior to Gen9.
2090 if (INTEL_INFO(dev)->gen < 9)
2094 * Starting in Gen9, render power gating can leave
2095 * slice/subslice/EU in a partially enabled state. We
2096 * must make an explicit request through RPCS for full
2099 if (INTEL_INFO(dev)->has_slice_pg) {
2100 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
2101 rpcs |= INTEL_INFO(dev)->slice_total <<
2102 GEN8_RPCS_S_CNT_SHIFT;
2103 rpcs |= GEN8_RPCS_ENABLE;
2106 if (INTEL_INFO(dev)->has_subslice_pg) {
2107 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
2108 rpcs |= INTEL_INFO(dev)->subslice_per_slice <<
2109 GEN8_RPCS_SS_CNT_SHIFT;
2110 rpcs |= GEN8_RPCS_ENABLE;
2113 if (INTEL_INFO(dev)->has_eu_pg) {
2114 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
2115 GEN8_RPCS_EU_MIN_SHIFT;
2116 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
2117 GEN8_RPCS_EU_MAX_SHIFT;
2118 rpcs |= GEN8_RPCS_ENABLE;
2125 populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
2126 struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
2128 struct drm_device *dev = ring->dev;
2129 struct drm_i915_private *dev_priv = dev->dev_private;
2130 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2131 struct vm_page *page;
2132 uint32_t *reg_state;
2136 ppgtt = dev_priv->mm.aliasing_ppgtt;
2138 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
2140 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2144 ret = i915_gem_object_get_pages(ctx_obj);
2146 DRM_DEBUG_DRIVER("Could not get object pages\n");
2150 i915_gem_object_pin_pages(ctx_obj);
2152 /* The second page of the context object contains some fields which must
2153 * be set up prior to the first execution. */
2154 page = i915_gem_object_get_page(ctx_obj, 1);
2155 reg_state = kmap_atomic(page);
2157 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2158 * commands followed by (reg, value) pairs. The values we are setting here are
2159 * only for the first context restore: on a subsequent save, the GPU will
2160 * recreate this batchbuffer with new values (including all the missing
2161 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2162 if (ring->id == RCS)
2163 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14);
2165 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);
2166 reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
2167 reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
2168 reg_state[CTX_CONTEXT_CONTROL+1] =
2169 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
2170 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
2171 CTX_CTRL_RS_CTX_ENABLE);
2172 reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
2173 reg_state[CTX_RING_HEAD+1] = 0;
2174 reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
2175 reg_state[CTX_RING_TAIL+1] = 0;
2176 reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base);
2177 /* Ring buffer start address is not known until the buffer is pinned.
2178 * It is written to the context image in execlists_update_context()
2180 reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);
2181 reg_state[CTX_RING_BUFFER_CONTROL+1] =
2182 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID;
2183 reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168;
2184 reg_state[CTX_BB_HEAD_U+1] = 0;
2185 reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140;
2186 reg_state[CTX_BB_HEAD_L+1] = 0;
2187 reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110;
2188 reg_state[CTX_BB_STATE+1] = (1<<5);
2189 reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c;
2190 reg_state[CTX_SECOND_BB_HEAD_U+1] = 0;
2191 reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114;
2192 reg_state[CTX_SECOND_BB_HEAD_L+1] = 0;
2193 reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118;
2194 reg_state[CTX_SECOND_BB_STATE+1] = 0;
2195 if (ring->id == RCS) {
2196 reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0;
2197 reg_state[CTX_BB_PER_CTX_PTR+1] = 0;
2198 reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4;
2199 reg_state[CTX_RCS_INDIRECT_CTX+1] = 0;
2200 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8;
2201 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0;
2202 if (ring->wa_ctx.obj) {
2203 struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx;
2204 uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj);
2206 reg_state[CTX_RCS_INDIRECT_CTX+1] =
2207 (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) |
2208 (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS);
2210 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =
2211 CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT << 6;
2213 reg_state[CTX_BB_PER_CTX_PTR+1] =
2214 (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
2218 reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9);
2219 reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED;
2220 reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8;
2221 reg_state[CTX_CTX_TIMESTAMP+1] = 0;
2222 reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3);
2223 reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3);
2224 reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2);
2225 reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2);
2226 reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1);
2227 reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);
2228 reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);
2229 reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);
2231 /* With dynamic page allocation, PDPs may not be allocated at this point,
2232 * Point the unallocated PDPs to the scratch page
2234 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
2235 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
2236 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
2237 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
2238 if (ring->id == RCS) {
2239 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2240 reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE;
2241 reg_state[CTX_R_PWR_CLK_STATE+1] = make_rpcs(dev);
2244 kunmap_atomic(reg_state);
2247 set_page_dirty(page);
2248 i915_gem_object_unpin_pages(ctx_obj);
2254 * intel_lr_context_free() - free the LRC specific bits of a context
2255 * @ctx: the LR context to free.
2257 * The real context freeing is done in i915_gem_context_free: this only
2258 * takes care of the bits that are LRC related: the per-engine backing
2259 * objects and the logical ringbuffer.
2261 void intel_lr_context_free(struct intel_context *ctx)
2265 for (i = 0; i < I915_NUM_RINGS; i++) {
2266 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
2269 struct intel_ringbuffer *ringbuf =
2270 ctx->engine[i].ringbuf;
2271 struct intel_engine_cs *ring = ringbuf->ring;
2273 if (ctx == ring->default_context) {
2274 intel_unpin_ringbuffer_obj(ringbuf);
2275 i915_gem_object_ggtt_unpin(ctx_obj);
2277 WARN_ON(ctx->engine[ring->id].pin_count);
2278 intel_destroy_ringbuffer_obj(ringbuf);
2280 drm_gem_object_unreference(&ctx_obj->base);
2285 static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
2289 WARN_ON(INTEL_INFO(ring->dev)->gen < 8);
2293 if (INTEL_INFO(ring->dev)->gen >= 9)
2294 ret = GEN9_LR_CONTEXT_RENDER_SIZE;
2296 ret = GEN8_LR_CONTEXT_RENDER_SIZE;
2302 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
2309 static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
2310 struct drm_i915_gem_object *default_ctx_obj)
2312 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2314 /* The status page is offset 0 from the default context object
2316 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj);
2317 ring->status_page.page_addr =
2318 kmap(sg_page(default_ctx_obj->pages->sgl));
2319 ring->status_page.obj = default_ctx_obj;
2321 I915_WRITE(RING_HWS_PGA(ring->mmio_base),
2322 (u32)ring->status_page.gfx_addr);
2323 POSTING_READ(RING_HWS_PGA(ring->mmio_base));
2327 * intel_lr_context_deferred_create() - create the LRC specific bits of a context
2328 * @ctx: LR context to create.
2329 * @ring: engine to be used with the context.
2331 * This function can be called more than once, with different engines, if we plan
2332 * to use the context with them. The context backing objects and the ringbuffers
2333 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
2334 * the creation is a deferred call: it's better to make sure first that we need to use
2335 * a given ring with the context.
2337 * Return: non-zero on error.
2339 int intel_lr_context_deferred_create(struct intel_context *ctx,
2340 struct intel_engine_cs *ring)
2342 const bool is_global_default_ctx = (ctx == ring->default_context);
2343 struct drm_device *dev = ring->dev;
2344 struct drm_i915_gem_object *ctx_obj;
2345 uint32_t context_size;
2346 struct intel_ringbuffer *ringbuf;
2349 WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
2350 WARN_ON(ctx->engine[ring->id].state);
2352 context_size = round_up(get_lr_context_size(ring), 4096);
2354 ctx_obj = i915_gem_alloc_object(dev, context_size);
2356 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2360 if (is_global_default_ctx) {
2361 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0);
2363 DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n",
2365 drm_gem_object_unreference(&ctx_obj->base);
2370 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
2372 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2375 goto error_unpin_ctx;
2378 ringbuf->ring = ring;
2380 ringbuf->size = 32 * PAGE_SIZE;
2381 ringbuf->effective_size = ringbuf->size;
2384 ringbuf->last_retired_head = -1;
2385 intel_ring_update_space(ringbuf);
2387 if (ringbuf->obj == NULL) {
2388 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
2391 "Failed to allocate ringbuffer obj %s: %d\n",
2393 goto error_free_rbuf;
2396 if (is_global_default_ctx) {
2397 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2400 "Failed to pin and map ringbuffer %s: %d\n",
2402 goto error_destroy_rbuf;
2408 ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
2410 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2414 ctx->engine[ring->id].ringbuf = ringbuf;
2415 ctx->engine[ring->id].state = ctx_obj;
2417 if (ctx == ring->default_context)
2418 lrc_setup_hardware_status_page(ring, ctx_obj);
2419 else if (ring->id == RCS && !ctx->rcs_initialized) {
2420 if (ring->init_context) {
2421 struct drm_i915_gem_request *req;
2423 ret = i915_gem_request_alloc(ring, ctx, &req);
2427 ret = ring->init_context(req);
2429 DRM_ERROR("ring init context: %d\n", ret);
2430 i915_gem_request_cancel(req);
2431 ctx->engine[ring->id].ringbuf = NULL;
2432 ctx->engine[ring->id].state = NULL;
2436 i915_add_request_no_flush(req);
2439 ctx->rcs_initialized = true;
2445 if (is_global_default_ctx)
2446 intel_unpin_ringbuffer_obj(ringbuf);
2448 intel_destroy_ringbuffer_obj(ringbuf);
2452 if (is_global_default_ctx)
2453 i915_gem_object_ggtt_unpin(ctx_obj);
2454 drm_gem_object_unreference(&ctx_obj->base);
2458 void intel_lr_context_reset(struct drm_device *dev,
2459 struct intel_context *ctx)
2461 struct drm_i915_private *dev_priv = dev->dev_private;
2462 struct intel_engine_cs *ring;
2465 for_each_ring(ring, dev_priv, i) {
2466 struct drm_i915_gem_object *ctx_obj =
2467 ctx->engine[ring->id].state;
2468 struct intel_ringbuffer *ringbuf =
2469 ctx->engine[ring->id].ringbuf;
2470 uint32_t *reg_state;
2471 struct vm_page *page;
2476 if (i915_gem_object_get_pages(ctx_obj)) {
2477 WARN(1, "Failed get_pages for context obj\n");
2480 page = i915_gem_object_get_page(ctx_obj, 1);
2481 reg_state = kmap_atomic(page);
2483 reg_state[CTX_RING_HEAD+1] = 0;
2484 reg_state[CTX_RING_TAIL+1] = 0;
2486 kunmap_atomic(reg_state);