sys/dev/netif/ig_hal/e1000_82575.c

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2013, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 /*
  36  * 82575EB Gigabit Network Connection
  37  * 82575EB Gigabit Backplane Connection
  38  * 82575GB Gigabit Network Connection
  39  * 82576 Gigabit Network Connection
  40  * 82576 Quad Port Gigabit Mezzanine Adapter
  41  * 82580 Gigabit Network Connection
  42  * I350 Gigabit Network Connection
  43  */
  44
  45 #include "e1000_api.h"
  46 #include "e1000_i210.h"
  47
  48 static s32  e1000_init_phy_params_82575(struct e1000_hw *hw);
  49 static s32  e1000_init_mac_params_82575(struct e1000_hw *hw);
  50 static s32  e1000_acquire_phy_82575(struct e1000_hw *hw);
  51 static void e1000_release_phy_82575(struct e1000_hw *hw);
  52 static s32  e1000_acquire_nvm_82575(struct e1000_hw *hw);
  53 static void e1000_release_nvm_82575(struct e1000_hw *hw);
  54 static s32  e1000_check_for_link_82575(struct e1000_hw *hw);
  55 static s32  e1000_check_for_link_media_swap(struct e1000_hw *hw);
  56 static s32  e1000_get_cfg_done_82575(struct e1000_hw *hw);
  57 static s32  e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
  58                                          u16 *duplex);
  59 static s32  e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
  60 static s32  e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
  61                                            u16 *data);
  62 static s32  e1000_reset_hw_82575(struct e1000_hw *hw);
  63 static s32  e1000_reset_hw_82580(struct e1000_hw *hw);
  64 static s32  e1000_read_phy_reg_82580(struct e1000_hw *hw,
  65                                      u32 offset, u16 *data);
  66 static s32  e1000_write_phy_reg_82580(struct e1000_hw *hw,
  67                                       u32 offset, u16 data);
  68 static s32  e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
  69                                           bool active);
  70 static s32  e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
  71                                           bool active);
  72 static s32  e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
  73                                           bool active);
  74 static s32  e1000_setup_copper_link_82575(struct e1000_hw *hw);
  75 static s32  e1000_setup_serdes_link_82575(struct e1000_hw *hw);
  76 static s32  e1000_get_media_type_82575(struct e1000_hw *hw);
  77 static s32  e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
  78 static s32  e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
  79 static s32  e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
  80                                             u32 offset, u16 data);
  81 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
  82 static s32  e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  83 static s32  e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
  84                                                  u16 *speed, u16 *duplex);
  85 static s32  e1000_get_phy_id_82575(struct e1000_hw *hw);
  86 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  87 static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
  88 static s32  e1000_reset_init_script_82575(struct e1000_hw *hw);
  89 static s32  e1000_read_mac_addr_82575(struct e1000_hw *hw);
  90 static void e1000_config_collision_dist_82575(struct e1000_hw *hw);
  91 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
  92 static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
  93 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
  94 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
  95 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
  96 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
  97 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
  98 static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
  99                                                  u16 offset);
 100 static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
 101                                                    u16 offset);
 102 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
 103 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
 104 static void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);
 105 static void e1000_clear_vfta_i350(struct e1000_hw *hw);
 106
 107 static void e1000_i2c_start(struct e1000_hw *hw);
 108 static void e1000_i2c_stop(struct e1000_hw *hw);
 109 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
 110 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
 111 static s32 e1000_get_i2c_ack(struct e1000_hw *hw);
 112 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
 113 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
 114 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
 115 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
 116 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
 117 static bool e1000_get_i2c_data(u32 *i2cctl);
 118
 119 static const u16 e1000_82580_rxpbs_table[] = {
 120         36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
 121 #define E1000_82580_RXPBS_TABLE_SIZE \
 122         (sizeof(e1000_82580_rxpbs_table) / \
 123          sizeof(e1000_82580_rxpbs_table[0]))
 124
 125
 126 /**
 127  *  e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
 128  *  @hw: pointer to the HW structure
 129  *
 130  *  Called to determine if the I2C pins are being used for I2C or as an
 131  *  external MDIO interface since the two options are mutually exclusive.
 132  **/
 133 static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
 134 {
 135         u32 reg = 0;
 136         bool ext_mdio = FALSE;
 137
 138         DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
 139
 140         switch (hw->mac.type) {
 141         case e1000_82575:
 142         case e1000_82576:
 143                 reg = E1000_READ_REG(hw, E1000_MDIC);
 144                 ext_mdio = !!(reg & E1000_MDIC_DEST);
 145                 break;
 146         case e1000_82580:
 147         case e1000_i350:
 148         case e1000_i354:
 149         case e1000_i210:
 150         case e1000_i211:
 151                 reg = E1000_READ_REG(hw, E1000_MDICNFG);
 152                 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
 153                 break;
 154         default:
 155                 break;
 156         }
 157         return ext_mdio;
 158 }
 159
 160 /**
 161  *  e1000_init_phy_params_82575 - Init PHY func ptrs.
 162  *  @hw: pointer to the HW structure
 163  **/
 164 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
 165 {
 166         struct e1000_phy_info *phy = &hw->phy;
 167         s32 ret_val = E1000_SUCCESS;
 168         u32 ctrl_ext;
 169
 170         DEBUGFUNC("e1000_init_phy_params_82575");
 171
 172         phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
 173         phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
 174
 175         if (hw->phy.media_type != e1000_media_type_copper) {
 176                 phy->type = e1000_phy_none;
 177                 goto out;
 178         }
 179
 180         phy->ops.power_up   = e1000_power_up_phy_copper;
 181         phy->ops.power_down = e1000_power_down_phy_copper_82575;
 182
 183         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 184         phy->reset_delay_us     = 100;
 185
 186         phy->ops.acquire        = e1000_acquire_phy_82575;
 187         phy->ops.check_reset_block = e1000_check_reset_block_generic;
 188         phy->ops.commit         = e1000_phy_sw_reset_generic;
 189         phy->ops.get_cfg_done   = e1000_get_cfg_done_82575;
 190         phy->ops.release        = e1000_release_phy_82575;
 191
 192         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 193
 194         if (e1000_sgmii_active_82575(hw)) {
 195                 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
 196                 ctrl_ext |= E1000_CTRL_I2C_ENA;
 197         } else {
 198                 phy->ops.reset = e1000_phy_hw_reset_generic;
 199                 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
 200         }
 201
 202         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 203         e1000_reset_mdicnfg_82580(hw);
 204
 205         if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
 206                 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
 207                 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
 208         } else {
 209                 switch (hw->mac.type) {
 210                 case e1000_82580:
 211                 case e1000_i350:
 212                 case e1000_i354:
 213                         phy->ops.read_reg = e1000_read_phy_reg_82580;
 214                         phy->ops.write_reg = e1000_write_phy_reg_82580;
 215                         break;
 216                 case e1000_i210:
 217                 case e1000_i211:
 218                         phy->ops.read_reg = e1000_read_phy_reg_gs40g;
 219                         phy->ops.write_reg = e1000_write_phy_reg_gs40g;
 220                         break;
 221                 default:
 222                         phy->ops.read_reg = e1000_read_phy_reg_igp;
 223                         phy->ops.write_reg = e1000_write_phy_reg_igp;
 224                 }
 225         }
 226
 227         /* Set phy->phy_addr and phy->id. */
 228         ret_val = e1000_get_phy_id_82575(hw);
 229
 230         /* Verify phy id and set remaining function pointers */
 231         switch (phy->id) {
 232         case M88E1543_E_PHY_ID:
 233         case M88E1512_E_PHY_ID:
 234         case I347AT4_E_PHY_ID:
 235         case M88E1112_E_PHY_ID:
 236         case M88E1340M_E_PHY_ID:
 237         case M88E1111_I_PHY_ID:
 238                 phy->type               = e1000_phy_m88;
 239                 phy->ops.check_polarity = e1000_check_polarity_m88;
 240                 phy->ops.get_info       = e1000_get_phy_info_m88;
 241                 if (phy->id == I347AT4_E_PHY_ID ||
 242                     phy->id == M88E1112_E_PHY_ID ||
 243                     phy->id == M88E1340M_E_PHY_ID)
 244                         phy->ops.get_cable_length =
 245                                          e1000_get_cable_length_m88_gen2;
 246                 else if (phy->id == M88E1543_E_PHY_ID ||
 247                          phy->id == M88E1512_E_PHY_ID)
 248                         phy->ops.get_cable_length =
 249                                          e1000_get_cable_length_m88_gen2;
 250                 else
 251                         phy->ops.get_cable_length = e1000_get_cable_length_m88;
 252                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 253                 /* Check if this PHY is confgured for media swap. */
 254                 if (phy->id == M88E1112_E_PHY_ID) {
 255                         u16 data;
 256
 257                         ret_val = phy->ops.write_reg(hw,
 258                                                      E1000_M88E1112_PAGE_ADDR,
 259                                                      2);
 260                         if (ret_val)
 261                                 goto out;
 262
 263                         ret_val = phy->ops.read_reg(hw,
 264                                                     E1000_M88E1112_MAC_CTRL_1,
 265                                                     &data);
 266                         if (ret_val)
 267                                 goto out;
 268
 269                         data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
 270                                E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
 271                         if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
 272                             data == E1000_M88E1112_AUTO_COPPER_BASEX)
 273                                 hw->mac.ops.check_for_link =
 274                                                 e1000_check_for_link_media_swap;
 275                 }
 276                 if (phy->id == M88E1512_E_PHY_ID) {
 277                         ret_val = e1000_initialize_M88E1512_phy(hw);
 278                         if (ret_val)
 279                                 goto out;
 280                 }
 281                 break;
 282         case IGP03E1000_E_PHY_ID:
 283         case IGP04E1000_E_PHY_ID:
 284                 phy->type = e1000_phy_igp_3;
 285                 phy->ops.check_polarity = e1000_check_polarity_igp;
 286                 phy->ops.get_info = e1000_get_phy_info_igp;
 287                 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 288                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 289                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
 290                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
 291                 break;
 292         case I82580_I_PHY_ID:
 293         case I350_I_PHY_ID:
 294                 phy->type = e1000_phy_82580;
 295                 phy->ops.check_polarity = e1000_check_polarity_82577;
 296                 phy->ops.force_speed_duplex =
 297                                          e1000_phy_force_speed_duplex_82577;
 298                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 299                 phy->ops.get_info = e1000_get_phy_info_82577;
 300                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
 301                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 302                 break;
 303         case I210_I_PHY_ID:
 304                 phy->type               = e1000_phy_i210;
 305                 phy->ops.check_polarity = e1000_check_polarity_m88;
 306                 phy->ops.get_info       = e1000_get_phy_info_m88;
 307                 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
 308                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
 309                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 310                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 311                 break;
 312         default:
 313                 ret_val = -E1000_ERR_PHY;
 314                 goto out;
 315         }
 316
 317 out:
 318         return ret_val;
 319 }
 320
 321 /**
 322  *  e1000_init_nvm_params_82575 - Init NVM func ptrs.
 323  *  @hw: pointer to the HW structure
 324  **/
 325 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
 326 {
 327         struct e1000_nvm_info *nvm = &hw->nvm;
 328         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 329         u16 size;
 330
 331         DEBUGFUNC("e1000_init_nvm_params_82575");
 332
 333         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 334                      E1000_EECD_SIZE_EX_SHIFT);
 335         /*
 336          * Added to a constant, "size" becomes the left-shift value
 337          * for setting word_size.
 338          */
 339         size += NVM_WORD_SIZE_BASE_SHIFT;
 340
 341         /* Just in case size is out of range, cap it to the largest
 342          * EEPROM size supported
 343          */
 344         if (size > 15)
 345                 size = 15;
 346
 347         nvm->word_size = 1 << size;
 348         if (hw->mac.type < e1000_i210) {
 349                 nvm->opcode_bits = 8;
 350                 nvm->delay_usec = 1;
 351
 352                 switch (nvm->override) {
 353                 case e1000_nvm_override_spi_large:
 354                         nvm->page_size = 32;
 355                         nvm->address_bits = 16;
 356                         break;
 357                 case e1000_nvm_override_spi_small:
 358                         nvm->page_size = 8;
 359                         nvm->address_bits = 8;
 360                         break;
 361                 default:
 362                         nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 363                         nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
 364                                             16 : 8;
 365                         break;
 366                 }
 367                 if (nvm->word_size == (1 << 15))
 368                         nvm->page_size = 128;
 369
 370                 nvm->type = e1000_nvm_eeprom_spi;
 371         } else {
 372                 nvm->type = e1000_nvm_flash_hw;
 373         }
 374
 375         /* Function Pointers */
 376         nvm->ops.acquire = e1000_acquire_nvm_82575;
 377         nvm->ops.release = e1000_release_nvm_82575;
 378         if (nvm->word_size < (1 << 15))
 379                 nvm->ops.read = e1000_read_nvm_eerd;
 380         else
 381                 nvm->ops.read = e1000_read_nvm_spi;
 382
 383         nvm->ops.write = e1000_write_nvm_spi;
 384         nvm->ops.validate = e1000_validate_nvm_checksum_generic;
 385         nvm->ops.update = e1000_update_nvm_checksum_generic;
 386         nvm->ops.valid_led_default = e1000_valid_led_default_82575;
 387
 388         /* override generic family function pointers for specific descendants */
 389         switch (hw->mac.type) {
 390         case e1000_82580:
 391                 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
 392                 nvm->ops.update = e1000_update_nvm_checksum_82580;
 393                 break;
 394         case e1000_i350:
 395         case e1000_i354:
 396                 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
 397                 nvm->ops.update = e1000_update_nvm_checksum_i350;
 398                 break;
 399         default:
 400                 break;
 401         }
 402
 403         return E1000_SUCCESS;
 404 }
 405
 406 /**
 407  *  e1000_init_mac_params_82575 - Init MAC func ptrs.
 408  *  @hw: pointer to the HW structure
 409  **/
 410 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
 411 {
 412         struct e1000_mac_info *mac = &hw->mac;
 413         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 414
 415         DEBUGFUNC("e1000_init_mac_params_82575");
 416
 417         /* Derives media type */
 418         e1000_get_media_type_82575(hw);
 419         /* Set mta register count */
 420         mac->mta_reg_count = 128;
 421         /* Set uta register count */
 422         mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
 423         /* Set rar entry count */
 424         mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
 425         if (mac->type == e1000_82576)
 426                 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
 427         if (mac->type == e1000_82580)
 428                 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
 429         if (mac->type == e1000_i350 || mac->type == e1000_i354)
 430                 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
 431
 432         /* Enable EEE default settings for EEE supported devices */
 433         if (mac->type >= e1000_i350)
 434                 dev_spec->eee_disable = FALSE;
 435
 436         /* Allow a single clear of the SW semaphore on I210 and newer */
 437         if (mac->type >= e1000_i210)
 438                 dev_spec->clear_semaphore_once = TRUE;
 439
 440         /* Set if part includes ASF firmware */
 441         mac->asf_firmware_present = TRUE;
 442         /* FWSM register */
 443         mac->has_fwsm = TRUE;
 444         /* ARC supported; valid only if manageability features are enabled. */
 445         mac->arc_subsystem_valid =
 446                 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
 447
 448         /* Function pointers */
 449
 450         /* bus type/speed/width */
 451         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 452         /* reset */
 453         if (mac->type >= e1000_82580)
 454                 mac->ops.reset_hw = e1000_reset_hw_82580;
 455         else
 456         mac->ops.reset_hw = e1000_reset_hw_82575;
 457         /* hw initialization */
 458         if ((mac->type == e1000_i210) || (mac->type == e1000_i211))
 459                 mac->ops.init_hw = e1000_init_hw_i210;
 460         else
 461         mac->ops.init_hw = e1000_init_hw_82575;
 462         /* link setup */
 463         mac->ops.setup_link = e1000_setup_link_generic;
 464         /* physical interface link setup */
 465         mac->ops.setup_physical_interface =
 466                 (hw->phy.media_type == e1000_media_type_copper)
 467                 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
 468         /* physical interface shutdown */
 469         mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
 470         /* physical interface power up */
 471         mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
 472         /* check for link */
 473         mac->ops.check_for_link = e1000_check_for_link_82575;
 474         /* read mac address */
 475         mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
 476         /* configure collision distance */
 477         mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
 478         /* multicast address update */
 479         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 480         if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
 481                 /* writing VFTA */
 482                 mac->ops.write_vfta = e1000_write_vfta_i350;
 483                 /* clearing VFTA */
 484                 mac->ops.clear_vfta = e1000_clear_vfta_i350;
 485         } else {
 486                 /* writing VFTA */
 487                 mac->ops.write_vfta = e1000_write_vfta_generic;
 488                 /* clearing VFTA */
 489                 mac->ops.clear_vfta = e1000_clear_vfta_generic;
 490         }
 491         if (hw->mac.type >= e1000_82580)
 492                 mac->ops.validate_mdi_setting =
 493                                 e1000_validate_mdi_setting_crossover_generic;
 494         /* ID LED init */
 495         mac->ops.id_led_init = e1000_id_led_init_generic;
 496         /* blink LED */
 497         mac->ops.blink_led = e1000_blink_led_generic;
 498         /* setup LED */
 499         mac->ops.setup_led = e1000_setup_led_generic;
 500         /* cleanup LED */
 501         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 502         /* turn on/off LED */
 503         mac->ops.led_on = e1000_led_on_generic;
 504         mac->ops.led_off = e1000_led_off_generic;
 505         /* clear hardware counters */
 506         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
 507         /* link info */
 508         mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
 509         /* acquire SW_FW sync */
 510         mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
 511         mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
 512         if (mac->type >= e1000_i210) {
 513                 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
 514                 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
 515         }
 516
 517         /* set lan id for port to determine which phy lock to use */
 518         hw->mac.ops.set_lan_id(hw);
 519
 520         return E1000_SUCCESS;
 521 }
 522
 523 /**
 524  *  e1000_init_function_pointers_82575 - Init func ptrs.
 525  *  @hw: pointer to the HW structure
 526  *
 527  *  Called to initialize all function pointers and parameters.
 528  **/
 529 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
 530 {
 531         DEBUGFUNC("e1000_init_function_pointers_82575");
 532
 533         hw->mac.ops.init_params = e1000_init_mac_params_82575;
 534         hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
 535         hw->phy.ops.init_params = e1000_init_phy_params_82575;
 536         hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
 537 }
 538
 539 /**
 540  *  e1000_acquire_phy_82575 - Acquire rights to access PHY
 541  *  @hw: pointer to the HW structure
 542  *
 543  *  Acquire access rights to the correct PHY.
 544  **/
 545 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
 546 {
 547         u16 mask = E1000_SWFW_PHY0_SM;
 548
 549         DEBUGFUNC("e1000_acquire_phy_82575");
 550
 551         if (hw->bus.func == E1000_FUNC_1)
 552                 mask = E1000_SWFW_PHY1_SM;
 553         else if (hw->bus.func == E1000_FUNC_2)
 554                 mask = E1000_SWFW_PHY2_SM;
 555         else if (hw->bus.func == E1000_FUNC_3)
 556                 mask = E1000_SWFW_PHY3_SM;
 557
 558         return hw->mac.ops.acquire_swfw_sync(hw, mask);
 559 }
 560
 561 /**
 562  *  e1000_release_phy_82575 - Release rights to access PHY
 563  *  @hw: pointer to the HW structure
 564  *
 565  *  A wrapper to release access rights to the correct PHY.
 566  **/
 567 static void e1000_release_phy_82575(struct e1000_hw *hw)
 568 {
 569         u16 mask = E1000_SWFW_PHY0_SM;
 570
 571         DEBUGFUNC("e1000_release_phy_82575");
 572
 573         if (hw->bus.func == E1000_FUNC_1)
 574                 mask = E1000_SWFW_PHY1_SM;
 575         else if (hw->bus.func == E1000_FUNC_2)
 576                 mask = E1000_SWFW_PHY2_SM;
 577         else if (hw->bus.func == E1000_FUNC_3)
 578                 mask = E1000_SWFW_PHY3_SM;
 579
 580         hw->mac.ops.release_swfw_sync(hw, mask);
 581 }
 582
 583 /**
 584  *  e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
 585  *  @hw: pointer to the HW structure
 586  *  @offset: register offset to be read
 587  *  @data: pointer to the read data
 588  *
 589  *  Reads the PHY register at offset using the serial gigabit media independent
 590  *  interface and stores the retrieved information in data.
 591  **/
 592 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 593                                           u16 *data)
 594 {
 595         s32 ret_val = -E1000_ERR_PARAM;
 596
 597         DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
 598
 599         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 600                 DEBUGOUT1("PHY Address %u is out of range\n", offset);
 601                 goto out;
 602         }
 603
 604         ret_val = hw->phy.ops.acquire(hw);
 605         if (ret_val)
 606                 goto out;
 607
 608         ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
 609
 610         hw->phy.ops.release(hw);
 611
 612 out:
 613         return ret_val;
 614 }
 615
 616 /**
 617  *  e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
 618  *  @hw: pointer to the HW structure
 619  *  @offset: register offset to write to
 620  *  @data: data to write at register offset
 621  *
 622  *  Writes the data to PHY register at the offset using the serial gigabit
 623  *  media independent interface.
 624  **/
 625 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 626                                            u16 data)
 627 {
 628         s32 ret_val = -E1000_ERR_PARAM;
 629
 630         DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
 631
 632         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 633                 DEBUGOUT1("PHY Address %d is out of range\n", offset);
 634                 goto out;
 635         }
 636
 637         ret_val = hw->phy.ops.acquire(hw);
 638         if (ret_val)
 639                 goto out;
 640
 641         ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
 642
 643         hw->phy.ops.release(hw);
 644
 645 out:
 646         return ret_val;
 647 }
 648
 649 /**
 650  *  e1000_get_phy_id_82575 - Retrieve PHY addr and id
 651  *  @hw: pointer to the HW structure
 652  *
 653  *  Retrieves the PHY address and ID for both PHY's which do and do not use
 654  *  sgmi interface.
 655  **/
 656 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
 657 {
 658         struct e1000_phy_info *phy = &hw->phy;
 659         s32  ret_val = E1000_SUCCESS;
 660         u16 phy_id;
 661         u32 ctrl_ext;
 662         u32 mdic;
 663
 664         DEBUGFUNC("e1000_get_phy_id_82575");
 665
 666         /* some i354 devices need an extra read for phy id */
 667         if (hw->mac.type == e1000_i354)
 668                 e1000_get_phy_id(hw);
 669
 670         /*
 671          * For SGMII PHYs, we try the list of possible addresses until
 672          * we find one that works.  For non-SGMII PHYs
 673          * (e.g. integrated copper PHYs), an address of 1 should
 674          * work.  The result of this function should mean phy->phy_addr
 675          * and phy->id are set correctly.
 676          */
 677         if (!e1000_sgmii_active_82575(hw)) {
 678                 phy->addr = 1;
 679                 ret_val = e1000_get_phy_id(hw);
 680                 goto out;
 681         }
 682
 683         if (e1000_sgmii_uses_mdio_82575(hw)) {
 684                 switch (hw->mac.type) {
 685                 case e1000_82575:
 686                 case e1000_82576:
 687                         mdic = E1000_READ_REG(hw, E1000_MDIC);
 688                         mdic &= E1000_MDIC_PHY_MASK;
 689                         phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
 690                         break;
 691                 case e1000_82580:
 692                 case e1000_i350:
 693                 case e1000_i354:
 694                 case e1000_i210:
 695                 case e1000_i211:
 696                         mdic = E1000_READ_REG(hw, E1000_MDICNFG);
 697                         mdic &= E1000_MDICNFG_PHY_MASK;
 698                         phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
 699                         break;
 700                 default:
 701                         ret_val = -E1000_ERR_PHY;
 702                         goto out;
 703                         break;
 704                 }
 705                 ret_val = e1000_get_phy_id(hw);
 706                 goto out;
 707         }
 708
 709         /* Power on sgmii phy if it is disabled */
 710         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 711         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 712                         ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
 713         E1000_WRITE_FLUSH(hw);
 714         msec_delay(300);
 715
 716         /*
 717          * The address field in the I2CCMD register is 3 bits and 0 is invalid.
 718          * Therefore, we need to test 1-7
 719          */
 720         for (phy->addr = 1; phy->addr < 8; phy->addr++) {
 721                 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
 722                 if (ret_val == E1000_SUCCESS) {
 723                         DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
 724                                   phy_id, phy->addr);
 725                         /*
 726                          * At the time of this writing, The M88 part is
 727                          * the only supported SGMII PHY product.
 728                          */
 729                         if (phy_id == M88_VENDOR)
 730                                 break;
 731                 } else {
 732                         DEBUGOUT1("PHY address %u was unreadable\n",
 733                                   phy->addr);
 734                 }
 735         }
 736
 737         /* A valid PHY type couldn't be found. */
 738         if (phy->addr == 8) {
 739                 phy->addr = 0;
 740                 ret_val = -E1000_ERR_PHY;
 741         } else {
 742                 ret_val = e1000_get_phy_id(hw);
 743         }
 744
 745         /* restore previous sfp cage power state */
 746         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 747
 748 out:
 749         return ret_val;
 750 }
 751
 752 /**
 753  *  e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
 754  *  @hw: pointer to the HW structure
 755  *
 756  *  Resets the PHY using the serial gigabit media independent interface.
 757  **/
 758 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
 759 {
 760         s32 ret_val = E1000_SUCCESS;
 761         struct e1000_phy_info *phy = &hw->phy;
 762
 763         DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
 764
 765         /*
 766          * This isn't a TRUE "hard" reset, but is the only reset
 767          * available to us at this time.
 768          */
 769
 770         DEBUGOUT("Soft resetting SGMII attached PHY...\n");
 771
 772         if (!(hw->phy.ops.write_reg))
 773                 goto out;
 774
 775         /*
 776          * SFP documentation requires the following to configure the SPF module
 777          * to work on SGMII.  No further documentation is given.
 778          */
 779         ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
 780         if (ret_val)
 781                 goto out;
 782
 783         ret_val = hw->phy.ops.commit(hw);
 784         if (ret_val)
 785                 goto out;
 786
 787         if (phy->id == M88E1512_E_PHY_ID)
 788                 ret_val = e1000_initialize_M88E1512_phy(hw);
 789 out:
 790         return ret_val;
 791 }
 792
 793 /**
 794  *  e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
 795  *  @hw: pointer to the HW structure
 796  *  @active: TRUE to enable LPLU, FALSE to disable
 797  *
 798  *  Sets the LPLU D0 state according to the active flag.  When
 799  *  activating LPLU this function also disables smart speed
 800  *  and vice versa.  LPLU will not be activated unless the
 801  *  device autonegotiation advertisement meets standards of
 802  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 803  *  This is a function pointer entry point only called by
 804  *  PHY setup routines.
 805  **/
 806 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
 807 {
 808         struct e1000_phy_info *phy = &hw->phy;
 809         s32 ret_val = E1000_SUCCESS;
 810         u16 data;
 811
 812         DEBUGFUNC("e1000_set_d0_lplu_state_82575");
 813
 814         if (!(hw->phy.ops.read_reg))
 815                 goto out;
 816
 817         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 818         if (ret_val)
 819                 goto out;
 820
 821         if (active) {
 822                 data |= IGP02E1000_PM_D0_LPLU;
 823                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 824                                              data);
 825                 if (ret_val)
 826                         goto out;
 827
 828                 /* When LPLU is enabled, we should disable SmartSpeed */
 829                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 830                                             &data);
 831                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 832                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 833                                              data);
 834                 if (ret_val)
 835                         goto out;
 836         } else {
 837                 data &= ~IGP02E1000_PM_D0_LPLU;
 838                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 839                                              data);
 840                 /*
 841                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 842                  * during Dx states where the power conservation is most
 843                  * important.  During driver activity we should enable
 844                  * SmartSpeed, so performance is maintained.
 845                  */
 846                 if (phy->smart_speed == e1000_smart_speed_on) {
 847                         ret_val = phy->ops.read_reg(hw,
 848                                                     IGP01E1000_PHY_PORT_CONFIG,
 849                                                     &data);
 850                         if (ret_val)
 851                                 goto out;
 852
 853                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 854                         ret_val = phy->ops.write_reg(hw,
 855                                                      IGP01E1000_PHY_PORT_CONFIG,
 856                                                      data);
 857                         if (ret_val)
 858                                 goto out;
 859                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 860                         ret_val = phy->ops.read_reg(hw,
 861                                                     IGP01E1000_PHY_PORT_CONFIG,
 862                                                     &data);
 863                         if (ret_val)
 864                                 goto out;
 865
 866                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 867                         ret_val = phy->ops.write_reg(hw,
 868                                                      IGP01E1000_PHY_PORT_CONFIG,
 869                                                      data);
 870                         if (ret_val)
 871                                 goto out;
 872                 }
 873         }
 874
 875 out:
 876         return ret_val;
 877 }
 878
 879 /**
 880  *  e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
 881  *  @hw: pointer to the HW structure
 882  *  @active: TRUE to enable LPLU, FALSE to disable
 883  *
 884  *  Sets the LPLU D0 state according to the active flag.  When
 885  *  activating LPLU this function also disables smart speed
 886  *  and vice versa.  LPLU will not be activated unless the
 887  *  device autonegotiation advertisement meets standards of
 888  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 889  *  This is a function pointer entry point only called by
 890  *  PHY setup routines.
 891  **/
 892 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
 893 {
 894         struct e1000_phy_info *phy = &hw->phy;
 895         u32 data;
 896
 897         DEBUGFUNC("e1000_set_d0_lplu_state_82580");
 898
 899         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 900
 901         if (active) {
 902                 data |= E1000_82580_PM_D0_LPLU;
 903
 904                 /* When LPLU is enabled, we should disable SmartSpeed */
 905                 data &= ~E1000_82580_PM_SPD;
 906         } else {
 907                 data &= ~E1000_82580_PM_D0_LPLU;
 908
 909                 /*
 910                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 911                  * during Dx states where the power conservation is most
 912                  * important.  During driver activity we should enable
 913                  * SmartSpeed, so performance is maintained.
 914                  */
 915                 if (phy->smart_speed == e1000_smart_speed_on)
 916                         data |= E1000_82580_PM_SPD;
 917                 else if (phy->smart_speed == e1000_smart_speed_off)
 918                         data &= ~E1000_82580_PM_SPD;
 919         }
 920
 921         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 922         return E1000_SUCCESS;
 923 }
 924
 925 /**
 926  *  e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
 927  *  @hw: pointer to the HW structure
 928  *  @active: boolean used to enable/disable lplu
 929  *
 930  *  Success returns 0, Failure returns 1
 931  *
 932  *  The low power link up (lplu) state is set to the power management level D3
 933  *  and SmartSpeed is disabled when active is TRUE, else clear lplu for D3
 934  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
 935  *  is used during Dx states where the power conservation is most important.
 936  *  During driver activity, SmartSpeed should be enabled so performance is
 937  *  maintained.
 938  **/
 939 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
 940 {
 941         struct e1000_phy_info *phy = &hw->phy;
 942         u32 data;
 943
 944         DEBUGFUNC("e1000_set_d3_lplu_state_82580");
 945
 946         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 947
 948         if (!active) {
 949                 data &= ~E1000_82580_PM_D3_LPLU;
 950                 /*
 951                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 952                  * during Dx states where the power conservation is most
 953                  * important.  During driver activity we should enable
 954                  * SmartSpeed, so performance is maintained.
 955                  */
 956                 if (phy->smart_speed == e1000_smart_speed_on)
 957                         data |= E1000_82580_PM_SPD;
 958                 else if (phy->smart_speed == e1000_smart_speed_off)
 959                         data &= ~E1000_82580_PM_SPD;
 960         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 961                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
 962                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 963                 data |= E1000_82580_PM_D3_LPLU;
 964                 /* When LPLU is enabled, we should disable SmartSpeed */
 965                 data &= ~E1000_82580_PM_SPD;
 966         }
 967
 968         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 969         return E1000_SUCCESS;
 970 }
 971
 972 /**
 973  *  e1000_acquire_nvm_82575 - Request for access to EEPROM
 974  *  @hw: pointer to the HW structure
 975  *
 976  *  Acquire the necessary semaphores for exclusive access to the EEPROM.
 977  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
 978  *  Return successful if access grant bit set, else clear the request for
 979  *  EEPROM access and return -E1000_ERR_NVM (-1).
 980  **/
 981 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
 982 {
 983         s32 ret_val = E1000_SUCCESS;
 984
 985         DEBUGFUNC("e1000_acquire_nvm_82575");
 986
 987         ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 988         if (ret_val)
 989                 goto out;
 990
 991         /*
 992          * Check if there is some access
 993          * error this access may hook on
 994          */
 995         if (hw->mac.type == e1000_i350) {
 996                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 997                 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
 998                     E1000_EECD_TIMEOUT)) {
 999                         /* Clear all access error flags */
1000                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
1001                                         E1000_EECD_ERROR_CLR);
1002                         DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1003                 }
1004         }
1005
1006         if (hw->mac.type == e1000_82580) {
1007                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
1008                 if (eecd & E1000_EECD_BLOCKED) {
1009                         /* Clear access error flag */
1010                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
1011                                         E1000_EECD_BLOCKED);
1012                         DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1013                 }
1014         }
1015
1016         ret_val = e1000_acquire_nvm_generic(hw);
1017         if (ret_val)
1018                 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1019
1020 out:
1021         return ret_val;
1022 }
1023
1024 /**
1025  *  e1000_release_nvm_82575 - Release exclusive access to EEPROM
1026  *  @hw: pointer to the HW structure
1027  *
1028  *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
1029  *  then release the semaphores acquired.
1030  **/
1031 static void e1000_release_nvm_82575(struct e1000_hw *hw)
1032 {
1033         DEBUGFUNC("e1000_release_nvm_82575");
1034
1035         e1000_release_nvm_generic(hw);
1036
1037         e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1038 }
1039
1040 /**
1041  *  e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1042  *  @hw: pointer to the HW structure
1043  *  @mask: specifies which semaphore to acquire
1044  *
1045  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
1046  *  will also specify which port we're acquiring the lock for.
1047  **/
1048 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1049 {
1050         u32 swfw_sync;
1051         u32 swmask = mask;
1052         u32 fwmask = mask << 16;
1053         s32 ret_val = E1000_SUCCESS;
1054         s32 i = 0, timeout = 200;
1055
1056         DEBUGFUNC("e1000_acquire_swfw_sync_82575");
1057
1058         while (i < timeout) {
1059                 if (e1000_get_hw_semaphore_generic(hw)) {
1060                         ret_val = -E1000_ERR_SWFW_SYNC;
1061                         goto out;
1062                 }
1063
1064                 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1065                 if (!(swfw_sync & (fwmask | swmask)))
1066                         break;
1067
1068                 /*
1069                  * Firmware currently using resource (fwmask)
1070                  * or other software thread using resource (swmask)
1071                  */
1072                 e1000_put_hw_semaphore_generic(hw);
1073                 msec_delay_irq(5);
1074                 i++;
1075         }
1076
1077         if (i == timeout) {
1078                 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1079                 ret_val = -E1000_ERR_SWFW_SYNC;
1080                 goto out;
1081         }
1082
1083         swfw_sync |= swmask;
1084         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1085
1086         e1000_put_hw_semaphore_generic(hw);
1087
1088 out:
1089         return ret_val;
1090 }
1091
1092 /**
1093  *  e1000_release_swfw_sync_82575 - Release SW/FW semaphore
1094  *  @hw: pointer to the HW structure
1095  *  @mask: specifies which semaphore to acquire
1096  *
1097  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
1098  *  will also specify which port we're releasing the lock for.
1099  **/
1100 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1101 {
1102         u32 swfw_sync;
1103
1104         DEBUGFUNC("e1000_release_swfw_sync_82575");
1105
1106         while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1107                 ; /* Empty */
1108
1109         swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1110         swfw_sync &= ~mask;
1111         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1112
1113         e1000_put_hw_semaphore_generic(hw);
1114 }
1115
1116 /**
1117  *  e1000_get_cfg_done_82575 - Read config done bit
1118  *  @hw: pointer to the HW structure
1119  *
1120  *  Read the management control register for the config done bit for
1121  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
1122  *  to read the config done bit, so an error is *ONLY* logged and returns
1123  *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
1124  *  would not be able to be reset or change link.
1125  **/
1126 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1127 {
1128         s32 timeout = PHY_CFG_TIMEOUT;
1129         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1130
1131         DEBUGFUNC("e1000_get_cfg_done_82575");
1132
1133         if (hw->bus.func == E1000_FUNC_1)
1134                 mask = E1000_NVM_CFG_DONE_PORT_1;
1135         else if (hw->bus.func == E1000_FUNC_2)
1136                 mask = E1000_NVM_CFG_DONE_PORT_2;
1137         else if (hw->bus.func == E1000_FUNC_3)
1138                 mask = E1000_NVM_CFG_DONE_PORT_3;
1139         while (timeout) {
1140                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1141                         break;
1142                 msec_delay(1);
1143                 timeout--;
1144         }
1145         if (!timeout)
1146                 DEBUGOUT("MNG configuration cycle has not completed.\n");
1147
1148         /* If EEPROM is not marked present, init the PHY manually */
1149         if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1150             (hw->phy.type == e1000_phy_igp_3))
1151                 e1000_phy_init_script_igp3(hw);
1152
1153         return E1000_SUCCESS;
1154 }
1155
1156 /**
1157  *  e1000_get_link_up_info_82575 - Get link speed/duplex info
1158  *  @hw: pointer to the HW structure
1159  *  @speed: stores the current speed
1160  *  @duplex: stores the current duplex
1161  *
1162  *  This is a wrapper function, if using the serial gigabit media independent
1163  *  interface, use PCS to retrieve the link speed and duplex information.
1164  *  Otherwise, use the generic function to get the link speed and duplex info.
1165  **/
1166 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1167                                         u16 *duplex)
1168 {
1169         s32 ret_val;
1170
1171         DEBUGFUNC("e1000_get_link_up_info_82575");
1172
1173         if (hw->phy.media_type != e1000_media_type_copper)
1174                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1175                                                                duplex);
1176         else
1177                 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1178                                                                     duplex);
1179
1180         return ret_val;
1181 }
1182
1183 /**
1184  *  e1000_check_for_link_82575 - Check for link
1185  *  @hw: pointer to the HW structure
1186  *
1187  *  If sgmii is enabled, then use the pcs register to determine link, otherwise
1188  *  use the generic interface for determining link.
1189  **/
1190 static s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1191 {
1192         s32 ret_val;
1193         u16 speed, duplex;
1194
1195         DEBUGFUNC("e1000_check_for_link_82575");
1196
1197         if (hw->phy.media_type != e1000_media_type_copper) {
1198                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1199                                                                &duplex);
1200                 /*
1201                  * Use this flag to determine if link needs to be checked or
1202                  * not.  If we have link clear the flag so that we do not
1203                  * continue to check for link.
1204                  */
1205                 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1206
1207                 /*
1208                  * Configure Flow Control now that Auto-Neg has completed.
1209                  * First, we need to restore the desired flow control
1210                  * settings because we may have had to re-autoneg with a
1211                  * different link partner.
1212                  */
1213                 ret_val = e1000_config_fc_after_link_up_generic(hw);
1214                 if (ret_val)
1215                         DEBUGOUT("Error configuring flow control\n");
1216         } else {
1217                 ret_val = e1000_check_for_copper_link_generic(hw);
1218         }
1219
1220         return ret_val;
1221 }
1222
1223 /**
1224  *  e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1225  *  @hw: pointer to the HW structure
1226  *
1227  *  Poll the M88E1112 interfaces to see which interface achieved link.
1228  */
1229 static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1230 {
1231         struct e1000_phy_info *phy = &hw->phy;
1232         s32 ret_val;
1233         u16 data;
1234         u8 port = 0;
1235
1236         DEBUGFUNC("e1000_check_for_link_media_swap");
1237
1238         /* Check for copper. */
1239         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1240         if (ret_val)
1241                 return ret_val;
1242
1243         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1244         if (ret_val)
1245                 return ret_val;
1246
1247         if (data & E1000_M88E1112_STATUS_LINK)
1248                 port = E1000_MEDIA_PORT_COPPER;
1249
1250         /* Check for other. */
1251         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1252         if (ret_val)
1253                 return ret_val;
1254
1255         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1256         if (ret_val)
1257                 return ret_val;
1258
1259         if (data & E1000_M88E1112_STATUS_LINK)
1260                 port = E1000_MEDIA_PORT_OTHER;
1261
1262         /* Determine if a swap needs to happen. */
1263         if (port && (hw->dev_spec._82575.media_port != port)) {
1264                 hw->dev_spec._82575.media_port = port;
1265                 hw->dev_spec._82575.media_changed = TRUE;
1266         }
1267
1268         if (port == E1000_MEDIA_PORT_COPPER) {
1269                 /* reset page to 0 */
1270                 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1271                 if (ret_val)
1272                         return ret_val;
1273                 e1000_check_for_link_82575(hw);
1274         } else {
1275                 e1000_check_for_link_82575(hw);
1276                 /* reset page to 0 */
1277                 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1278                 if (ret_val)
1279                         return ret_val;
1280         }
1281
1282         return E1000_SUCCESS;
1283 }
1284
1285 /**
1286  *  e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1287  *  @hw: pointer to the HW structure
1288  **/
1289 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1290 {
1291         u32 reg;
1292
1293         DEBUGFUNC("e1000_power_up_serdes_link_82575");
1294
1295         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1296             !e1000_sgmii_active_82575(hw))
1297                 return;
1298
1299         /* Enable PCS to turn on link */
1300         reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1301         reg |= E1000_PCS_CFG_PCS_EN;
1302         E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1303
1304         /* Power up the laser */
1305         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1306         reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1307         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1308
1309         /* flush the write to verify completion */
1310         E1000_WRITE_FLUSH(hw);
1311         msec_delay(1);
1312 }
1313
1314 /**
1315  *  e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1316  *  @hw: pointer to the HW structure
1317  *  @speed: stores the current speed
1318  *  @duplex: stores the current duplex
1319  *
1320  *  Using the physical coding sub-layer (PCS), retrieve the current speed and
1321  *  duplex, then store the values in the pointers provided.
1322  **/
1323 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1324                                                 u16 *speed, u16 *duplex)
1325 {
1326         struct e1000_mac_info *mac = &hw->mac;
1327         u32 pcs;
1328         u32 status;
1329
1330         DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1331
1332         /*
1333          * Read the PCS Status register for link state. For non-copper mode,
1334          * the status register is not accurate. The PCS status register is
1335          * used instead.
1336          */
1337         pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1338
1339         /*
1340          * The link up bit determines when link is up on autoneg.
1341          */
1342         if (pcs & E1000_PCS_LSTS_LINK_OK) {
1343                 mac->serdes_has_link = TRUE;
1344
1345                 /* Detect and store PCS speed */
1346                 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1347                         *speed = SPEED_1000;
1348                 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1349                         *speed = SPEED_100;
1350                 else
1351                         *speed = SPEED_10;
1352
1353                 /* Detect and store PCS duplex */
1354                 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1355                         *duplex = FULL_DUPLEX;
1356                 else
1357                         *duplex = HALF_DUPLEX;
1358
1359                 /* Check if it is an I354 2.5Gb backplane connection. */
1360                 if (mac->type == e1000_i354) {
1361                         status = E1000_READ_REG(hw, E1000_STATUS);
1362                         if ((status & E1000_STATUS_2P5_SKU) &&
1363                             !(status & E1000_STATUS_2P5_SKU_OVER)) {
1364                                 *speed = SPEED_2500;
1365                                 *duplex = FULL_DUPLEX;
1366                                 DEBUGOUT("2500 Mbs, ");
1367                                 DEBUGOUT("Full Duplex\n");
1368                         }
1369                 }
1370
1371         } else {
1372                 mac->serdes_has_link = FALSE;
1373                 *speed = 0;
1374                 *duplex = 0;
1375         }
1376
1377         return E1000_SUCCESS;
1378 }
1379
1380 /**
1381  *  e1000_shutdown_serdes_link_82575 - Remove link during power down
1382  *  @hw: pointer to the HW structure
1383  *
1384  *  In the case of serdes shut down sfp and PCS on driver unload
1385  *  when management pass thru is not enabled.
1386  **/
1387 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1388 {
1389         u32 reg;
1390
1391         DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1392
1393         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1394             !e1000_sgmii_active_82575(hw))
1395                 return;
1396
1397         if (!e1000_enable_mng_pass_thru(hw)) {
1398                 /* Disable PCS to turn off link */
1399                 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1400                 reg &= ~E1000_PCS_CFG_PCS_EN;
1401                 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1402
1403                 /* shutdown the laser */
1404                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1405                 reg |= E1000_CTRL_EXT_SDP3_DATA;
1406                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1407
1408                 /* flush the write to verify completion */
1409                 E1000_WRITE_FLUSH(hw);
1410                 msec_delay(1);
1411         }
1412
1413         return;
1414 }
1415
1416 /**
1417  *  e1000_reset_hw_82575 - Reset hardware
1418  *  @hw: pointer to the HW structure
1419  *
1420  *  This resets the hardware into a known state.
1421  **/
1422 static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1423 {
1424         u32 ctrl;
1425         s32 ret_val;
1426
1427         DEBUGFUNC("e1000_reset_hw_82575");
1428
1429         /*
1430          * Prevent the PCI-E bus from sticking if there is no TLP connection
1431          * on the last TLP read/write transaction when MAC is reset.
1432          */
1433         ret_val = e1000_disable_pcie_master_generic(hw);
1434         if (ret_val)
1435                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1436
1437         /* set the completion timeout for interface */
1438         ret_val = e1000_set_pcie_completion_timeout(hw);
1439         if (ret_val)
1440                 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1441
1442         DEBUGOUT("Masking off all interrupts\n");
1443         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1444
1445         E1000_WRITE_REG(hw, E1000_RCTL, 0);
1446         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1447         E1000_WRITE_FLUSH(hw);
1448
1449         msec_delay(10);
1450
1451         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1452
1453         DEBUGOUT("Issuing a global reset to MAC\n");
1454         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1455
1456         ret_val = e1000_get_auto_rd_done_generic(hw);
1457         if (ret_val) {
1458                 /*
1459                  * When auto config read does not complete, do not
1460                  * return with an error. This can happen in situations
1461                  * where there is no eeprom and prevents getting link.
1462                  */
1463                 DEBUGOUT("Auto Read Done did not complete\n");
1464         }
1465
1466         /* If EEPROM is not present, run manual init scripts */
1467         if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1468                 e1000_reset_init_script_82575(hw);
1469
1470         /* Clear any pending interrupt events. */
1471         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1472         E1000_READ_REG(hw, E1000_ICR);
1473
1474         /* Install any alternate MAC address into RAR0 */
1475         ret_val = e1000_check_alt_mac_addr_generic(hw);
1476
1477         return ret_val;
1478 }
1479
1480 /**
1481  *  e1000_init_hw_82575 - Initialize hardware
1482  *  @hw: pointer to the HW structure
1483  *
1484  *  This inits the hardware readying it for operation.
1485  **/
1486 s32 e1000_init_hw_82575(struct e1000_hw *hw)
1487 {
1488         struct e1000_mac_info *mac = &hw->mac;
1489         s32 ret_val;
1490         u16 i, rar_count = mac->rar_entry_count;
1491
1492         DEBUGFUNC("e1000_init_hw_82575");
1493
1494         /* Initialize identification LED */
1495         ret_val = mac->ops.id_led_init(hw);
1496         if (ret_val) {
1497                 DEBUGOUT("Error initializing identification LED\n");
1498                 /* This is not fatal and we should not stop init due to this */
1499         }
1500
1501         /* Disabling VLAN filtering */
1502         DEBUGOUT("Initializing the IEEE VLAN\n");
1503         mac->ops.clear_vfta(hw);
1504
1505         /* Setup the receive address */
1506         e1000_init_rx_addrs_generic(hw, rar_count);
1507
1508         /* Zero out the Multicast HASH table */
1509         DEBUGOUT("Zeroing the MTA\n");
1510         for (i = 0; i < mac->mta_reg_count; i++)
1511                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1512
1513         /* Zero out the Unicast HASH table */
1514         DEBUGOUT("Zeroing the UTA\n");
1515         for (i = 0; i < mac->uta_reg_count; i++)
1516                 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1517
1518         /* Setup link and flow control */
1519         ret_val = mac->ops.setup_link(hw);
1520
1521         /* Set the default MTU size */
1522         hw->dev_spec._82575.mtu = 1500;
1523
1524         /*
1525          * Clear all of the statistics registers (clear on read).  It is
1526          * important that we do this after we have tried to establish link
1527          * because the symbol error count will increment wildly if there
1528          * is no link.
1529          */
1530         e1000_clear_hw_cntrs_82575(hw);
1531
1532         return ret_val;
1533 }
1534
1535 /**
1536  *  e1000_setup_copper_link_82575 - Configure copper link settings
1537  *  @hw: pointer to the HW structure
1538  *
1539  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1540  *  for link, once link is established calls to configure collision distance
1541  *  and flow control are called.
1542  **/
1543 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1544 {
1545         u32 ctrl;
1546         s32 ret_val;
1547         u32 phpm_reg;
1548
1549         DEBUGFUNC("e1000_setup_copper_link_82575");
1550
1551         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1552         ctrl |= E1000_CTRL_SLU;
1553         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1554         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1555
1556         /* Clear Go Link Disconnect bit on supported devices */
1557         switch (hw->mac.type) {
1558         case e1000_82580:
1559         case e1000_i350:
1560         case e1000_i210:
1561         case e1000_i211:
1562                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1563                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1564                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1565                 break;
1566         default:
1567                 break;
1568         }
1569
1570         ret_val = e1000_setup_serdes_link_82575(hw);
1571         if (ret_val)
1572                 goto out;
1573
1574         if (e1000_sgmii_active_82575(hw)) {
1575                 /* allow time for SFP cage time to power up phy */
1576                 msec_delay(300);
1577
1578                 ret_val = hw->phy.ops.reset(hw);
1579                 if (ret_val) {
1580                         DEBUGOUT("Error resetting the PHY.\n");
1581                         goto out;
1582                 }
1583         }
1584         switch (hw->phy.type) {
1585         case e1000_phy_i210:
1586         case e1000_phy_m88:
1587                 switch (hw->phy.id) {
1588                 case I347AT4_E_PHY_ID:
1589                 case M88E1112_E_PHY_ID:
1590                 case M88E1340M_E_PHY_ID:
1591                 case M88E1543_E_PHY_ID:
1592                 case M88E1512_E_PHY_ID:
1593                 case I210_I_PHY_ID:
1594                         ret_val = e1000_copper_link_setup_m88_gen2(hw);
1595                         break;
1596                 default:
1597                         ret_val = e1000_copper_link_setup_m88(hw);
1598                         break;
1599                 }
1600                 break;
1601         case e1000_phy_igp_3:
1602                 ret_val = e1000_copper_link_setup_igp(hw);
1603                 break;
1604         case e1000_phy_82580:
1605                 ret_val = e1000_copper_link_setup_82577(hw);
1606                 break;
1607         default:
1608                 ret_val = -E1000_ERR_PHY;
1609                 break;
1610         }
1611
1612         if (ret_val)
1613                 goto out;
1614
1615         ret_val = e1000_setup_copper_link_generic(hw);
1616 out:
1617         return ret_val;
1618 }
1619
1620 /**
1621  *  e1000_setup_serdes_link_82575 - Setup link for serdes
1622  *  @hw: pointer to the HW structure
1623  *
1624  *  Configure the physical coding sub-layer (PCS) link.  The PCS link is
1625  *  used on copper connections where the serialized gigabit media independent
1626  *  interface (sgmii), or serdes fiber is being used.  Configures the link
1627  *  for auto-negotiation or forces speed/duplex.
1628  **/
1629 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1630 {
1631         u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1632         bool pcs_autoneg;
1633         s32 ret_val = E1000_SUCCESS;
1634         u16 data;
1635
1636         DEBUGFUNC("e1000_setup_serdes_link_82575");
1637
1638         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1639             !e1000_sgmii_active_82575(hw))
1640                 return ret_val;
1641
1642         /*
1643          * On the 82575, SerDes loopback mode persists until it is
1644          * explicitly turned off or a power cycle is performed.  A read to
1645          * the register does not indicate its status.  Therefore, we ensure
1646          * loopback mode is disabled during initialization.
1647          */
1648         E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1649
1650         /* power on the sfp cage if present */
1651         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1652         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1653         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1654
1655         ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1656         ctrl_reg |= E1000_CTRL_SLU;
1657
1658         /* set both sw defined pins on 82575/82576*/
1659         if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1660                 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1661
1662         reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1663
1664         /* default pcs_autoneg to the same setting as mac autoneg */
1665         pcs_autoneg = hw->mac.autoneg;
1666
1667         switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1668         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1669                 /* sgmii mode lets the phy handle forcing speed/duplex */
1670                 pcs_autoneg = TRUE;
1671                 /* autoneg time out should be disabled for SGMII mode */
1672                 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1673                 break;
1674         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1675                 /* disable PCS autoneg and support parallel detect only */
1676                 pcs_autoneg = FALSE;
1677                 /* fall through to default case */
1678         default:
1679                 if (hw->mac.type == e1000_82575 ||
1680                     hw->mac.type == e1000_82576) {
1681                         ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1682                         if (ret_val) {
1683                                 DEBUGOUT("NVM Read Error\n");
1684                                 return ret_val;
1685                         }
1686
1687                         if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1688                                 pcs_autoneg = FALSE;
1689                 }
1690
1691                 /*
1692                  * non-SGMII modes only supports a speed of 1000/Full for the
1693                  * link so it is best to just force the MAC and let the pcs
1694                  * link either autoneg or be forced to 1000/Full
1695                  */
1696                 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1697                             E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1698
1699                 /* set speed of 1000/Full if speed/duplex is forced */
1700                 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1701                 break;
1702         }
1703
1704         E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1705
1706         /*
1707          * New SerDes mode allows for forcing speed or autonegotiating speed
1708          * at 1gb. Autoneg should be default set by most drivers. This is the
1709          * mode that will be compatible with older link partners and switches.
1710          * However, both are supported by the hardware and some drivers/tools.
1711          */
1712         reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1713                  E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1714
1715         if (pcs_autoneg) {
1716                 /* Set PCS register for autoneg */
1717                 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1718                        E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1719
1720                 /* Disable force flow control for autoneg */
1721                 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1722
1723                 /* Configure flow control advertisement for autoneg */
1724                 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1725                 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1726
1727                 switch (hw->fc.requested_mode) {
1728                 case e1000_fc_full:
1729                 case e1000_fc_rx_pause:
1730                         anadv_reg |= E1000_TXCW_ASM_DIR;
1731                         anadv_reg |= E1000_TXCW_PAUSE;
1732                         break;
1733                 case e1000_fc_tx_pause:
1734                         anadv_reg |= E1000_TXCW_ASM_DIR;
1735                         break;
1736                 default:
1737                         break;
1738                 }
1739
1740                 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1741
1742                 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1743         } else {
1744                 /* Set PCS register for forced link */
1745                 reg |= E1000_PCS_LCTL_FSD;      /* Force Speed */
1746
1747                 /* Force flow control for forced link */
1748                 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1749
1750                 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1751         }
1752
1753         E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1754
1755         if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1756                 e1000_force_mac_fc_generic(hw);
1757
1758         return ret_val;
1759 }
1760
1761 /**
1762  *  e1000_get_media_type_82575 - derives current media type.
1763  *  @hw: pointer to the HW structure
1764  *
1765  *  The media type is chosen reflecting few settings.
1766  *  The following are taken into account:
1767  *  - link mode set in the current port Init Control Word #3
1768  *  - current link mode settings in CSR register
1769  *  - MDIO vs. I2C PHY control interface chosen
1770  *  - SFP module media type
1771  **/
1772 static s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1773 {
1774         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1775         s32 ret_val = E1000_SUCCESS;
1776         u32 ctrl_ext = 0;
1777         u32 link_mode = 0;
1778
1779         /* Set internal phy as default */
1780         dev_spec->sgmii_active = FALSE;
1781         dev_spec->module_plugged = FALSE;
1782
1783         /* Get CSR setting */
1784         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1785
1786         /* extract link mode setting */
1787         link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1788
1789         switch (link_mode) {
1790         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1791                 hw->phy.media_type = e1000_media_type_internal_serdes;
1792                 break;
1793         case E1000_CTRL_EXT_LINK_MODE_GMII:
1794                 hw->phy.media_type = e1000_media_type_copper;
1795                 break;
1796         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1797                 /* Get phy control interface type set (MDIO vs. I2C)*/
1798                 if (e1000_sgmii_uses_mdio_82575(hw)) {
1799                         hw->phy.media_type = e1000_media_type_copper;
1800                         dev_spec->sgmii_active = TRUE;
1801                         break;
1802                 }
1803                 /* fall through for I2C based SGMII */
1804         case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1805                 /* read media type from SFP EEPROM */
1806                 ret_val = e1000_set_sfp_media_type_82575(hw);
1807                 if ((ret_val != E1000_SUCCESS) ||
1808                     (hw->phy.media_type == e1000_media_type_unknown)) {
1809                         /*
1810                          * If media type was not identified then return media
1811                          * type defined by the CTRL_EXT settings.
1812                          */
1813                         hw->phy.media_type = e1000_media_type_internal_serdes;
1814
1815                         if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1816                                 hw->phy.media_type = e1000_media_type_copper;
1817                                 dev_spec->sgmii_active = TRUE;
1818                         }
1819
1820                         break;
1821                 }
1822
1823                 /* do not change link mode for 100BaseFX */
1824                 if (dev_spec->eth_flags.e100_base_fx)
1825                         break;
1826
1827                 /* change current link mode setting */
1828                 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1829
1830                 if (hw->phy.media_type == e1000_media_type_copper)
1831                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1832                 else
1833                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1834
1835                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1836
1837                 break;
1838         }
1839
1840         return ret_val;
1841 }
1842
1843 /**
1844  *  e1000_set_sfp_media_type_82575 - derives SFP module media type.
1845  *  @hw: pointer to the HW structure
1846  *
1847  *  The media type is chosen based on SFP module.
1848  *  compatibility flags retrieved from SFP ID EEPROM.
1849  **/
1850 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1851 {
1852         s32 ret_val = E1000_ERR_CONFIG;
1853         u32 ctrl_ext = 0;
1854         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1855         struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1856         u8 tranceiver_type = 0;
1857         s32 timeout = 3;
1858
1859         /* Turn I2C interface ON and power on sfp cage */
1860         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1861         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1862         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1863
1864         E1000_WRITE_FLUSH(hw);
1865
1866         /* Read SFP module data */
1867         while (timeout) {
1868                 ret_val = e1000_read_sfp_data_byte(hw,
1869                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1870                         &tranceiver_type);
1871                 if (ret_val == E1000_SUCCESS)
1872                         break;
1873                 msec_delay(100);
1874                 timeout--;
1875         }
1876         if (ret_val != E1000_SUCCESS)
1877                 goto out;
1878
1879         ret_val = e1000_read_sfp_data_byte(hw,
1880                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1881                         (u8 *)eth_flags);
1882         if (ret_val != E1000_SUCCESS)
1883                 goto out;
1884
1885         /* Check if there is some SFP module plugged and powered */
1886         if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1887             (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1888                 dev_spec->module_plugged = TRUE;
1889                 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1890                         hw->phy.media_type = e1000_media_type_internal_serdes;
1891                 } else if (eth_flags->e100_base_fx) {
1892                         dev_spec->sgmii_active = TRUE;
1893                         hw->phy.media_type = e1000_media_type_internal_serdes;
1894                 } else if (eth_flags->e1000_base_t) {
1895                         dev_spec->sgmii_active = TRUE;
1896                         hw->phy.media_type = e1000_media_type_copper;
1897                 } else {
1898                         hw->phy.media_type = e1000_media_type_unknown;
1899                         DEBUGOUT("PHY module has not been recognized\n");
1900                         goto out;
1901                 }
1902         } else {
1903                 hw->phy.media_type = e1000_media_type_unknown;
1904         }
1905         ret_val = E1000_SUCCESS;
1906 out:
1907         /* Restore I2C interface setting */
1908         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1909         return ret_val;
1910 }
1911
1912 /**
1913  *  e1000_valid_led_default_82575 - Verify a valid default LED config
1914  *  @hw: pointer to the HW structure
1915  *  @data: pointer to the NVM (EEPROM)
1916  *
1917  *  Read the EEPROM for the current default LED configuration.  If the
1918  *  LED configuration is not valid, set to a valid LED configuration.
1919  **/
1920 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1921 {
1922         s32 ret_val;
1923
1924         DEBUGFUNC("e1000_valid_led_default_82575");
1925
1926         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1927         if (ret_val) {
1928                 DEBUGOUT("NVM Read Error\n");
1929                 goto out;
1930         }
1931
1932         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1933                 switch (hw->phy.media_type) {
1934                 case e1000_media_type_internal_serdes:
1935                         *data = ID_LED_DEFAULT_82575_SERDES;
1936                         break;
1937                 case e1000_media_type_copper:
1938                 default:
1939                         *data = ID_LED_DEFAULT;
1940                         break;
1941                 }
1942         }
1943 out:
1944         return ret_val;
1945 }
1946
1947 /**
1948  *  e1000_sgmii_active_82575 - Return sgmii state
1949  *  @hw: pointer to the HW structure
1950  *
1951  *  82575 silicon has a serialized gigabit media independent interface (sgmii)
1952  *  which can be enabled for use in the embedded applications.  Simply
1953  *  return the current state of the sgmii interface.
1954  **/
1955 static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1956 {
1957         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1958         return dev_spec->sgmii_active;
1959 }
1960
1961 /**
1962  *  e1000_reset_init_script_82575 - Inits HW defaults after reset
1963  *  @hw: pointer to the HW structure
1964  *
1965  *  Inits recommended HW defaults after a reset when there is no EEPROM
1966  *  detected. This is only for the 82575.
1967  **/
1968 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1969 {
1970         DEBUGFUNC("e1000_reset_init_script_82575");
1971
1972         if (hw->mac.type == e1000_82575) {
1973                 DEBUGOUT("Running reset init script for 82575\n");
1974                 /* SerDes configuration via SERDESCTRL */
1975                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1976                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1977                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1978                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1979
1980                 /* CCM configuration via CCMCTL register */
1981                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1982                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1983
1984                 /* PCIe lanes configuration */
1985                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1986                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1987                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1988                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1989
1990                 /* PCIe PLL Configuration */
1991                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1992                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1993                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1994         }
1995
1996         return E1000_SUCCESS;
1997 }
1998
1999 /**
2000  *  e1000_read_mac_addr_82575 - Read device MAC address
2001  *  @hw: pointer to the HW structure
2002  **/
2003 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
2004 {
2005         s32 ret_val;
2006
2007         DEBUGFUNC("e1000_read_mac_addr_82575");
2008
2009         /*
2010          * If there's an alternate MAC address place it in RAR0
2011          * so that it will override the Si installed default perm
2012          * address.
2013          */
2014         ret_val = e1000_check_alt_mac_addr_generic(hw);
2015         if (ret_val)
2016                 goto out;
2017
2018         ret_val = e1000_read_mac_addr_generic(hw);
2019
2020 out:
2021         return ret_val;
2022 }
2023
2024 /**
2025  *  e1000_config_collision_dist_82575 - Configure collision distance
2026  *  @hw: pointer to the HW structure
2027  *
2028  *  Configures the collision distance to the default value and is used
2029  *  during link setup.
2030  **/
2031 static void e1000_config_collision_dist_82575(struct e1000_hw *hw)
2032 {
2033         u32 tctl_ext;
2034
2035         DEBUGFUNC("e1000_config_collision_dist_82575");
2036
2037         tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
2038
2039         tctl_ext &= ~E1000_TCTL_EXT_COLD;
2040         tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
2041
2042         E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
2043         E1000_WRITE_FLUSH(hw);
2044 }
2045
2046 /**
2047  * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
2048  * @hw: pointer to the HW structure
2049  *
2050  * In the case of a PHY power down to save power, or to turn off link during a
2051  * driver unload, or wake on lan is not enabled, remove the link.
2052  **/
2053 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
2054 {
2055         struct e1000_phy_info *phy = &hw->phy;
2056
2057         if (!(phy->ops.check_reset_block))
2058                 return;
2059
2060         /* If the management interface is not enabled, then power down */
2061         if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
2062                 e1000_power_down_phy_copper(hw);
2063
2064         return;
2065 }
2066
2067 /**
2068  *  e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
2069  *  @hw: pointer to the HW structure
2070  *
2071  *  Clears the hardware counters by reading the counter registers.
2072  **/
2073 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
2074 {
2075         DEBUGFUNC("e1000_clear_hw_cntrs_82575");
2076
2077         e1000_clear_hw_cntrs_base_generic(hw);
2078
2079         E1000_READ_REG(hw, E1000_PRC64);
2080         E1000_READ_REG(hw, E1000_PRC127);
2081         E1000_READ_REG(hw, E1000_PRC255);
2082         E1000_READ_REG(hw, E1000_PRC511);
2083         E1000_READ_REG(hw, E1000_PRC1023);
2084         E1000_READ_REG(hw, E1000_PRC1522);
2085         E1000_READ_REG(hw, E1000_PTC64);
2086         E1000_READ_REG(hw, E1000_PTC127);
2087         E1000_READ_REG(hw, E1000_PTC255);
2088         E1000_READ_REG(hw, E1000_PTC511);
2089         E1000_READ_REG(hw, E1000_PTC1023);
2090         E1000_READ_REG(hw, E1000_PTC1522);
2091
2092         E1000_READ_REG(hw, E1000_ALGNERRC);
2093         E1000_READ_REG(hw, E1000_RXERRC);
2094         E1000_READ_REG(hw, E1000_TNCRS);
2095         E1000_READ_REG(hw, E1000_CEXTERR);
2096         E1000_READ_REG(hw, E1000_TSCTC);
2097         E1000_READ_REG(hw, E1000_TSCTFC);
2098
2099         E1000_READ_REG(hw, E1000_MGTPRC);
2100         E1000_READ_REG(hw, E1000_MGTPDC);
2101         E1000_READ_REG(hw, E1000_MGTPTC);
2102
2103         E1000_READ_REG(hw, E1000_IAC);
2104         E1000_READ_REG(hw, E1000_ICRXOC);
2105
2106         E1000_READ_REG(hw, E1000_ICRXPTC);
2107         E1000_READ_REG(hw, E1000_ICRXATC);
2108         E1000_READ_REG(hw, E1000_ICTXPTC);
2109         E1000_READ_REG(hw, E1000_ICTXATC);
2110         E1000_READ_REG(hw, E1000_ICTXQEC);
2111         E1000_READ_REG(hw, E1000_ICTXQMTC);
2112         E1000_READ_REG(hw, E1000_ICRXDMTC);
2113
2114         E1000_READ_REG(hw, E1000_CBTMPC);
2115         E1000_READ_REG(hw, E1000_HTDPMC);
2116         E1000_READ_REG(hw, E1000_CBRMPC);
2117         E1000_READ_REG(hw, E1000_RPTHC);
2118         E1000_READ_REG(hw, E1000_HGPTC);
2119         E1000_READ_REG(hw, E1000_HTCBDPC);
2120         E1000_READ_REG(hw, E1000_HGORCL);
2121         E1000_READ_REG(hw, E1000_HGORCH);
2122         E1000_READ_REG(hw, E1000_HGOTCL);
2123         E1000_READ_REG(hw, E1000_HGOTCH);
2124         E1000_READ_REG(hw, E1000_LENERRS);
2125
2126         /* This register should not be read in copper configurations */
2127         if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
2128             e1000_sgmii_active_82575(hw))
2129                 E1000_READ_REG(hw, E1000_SCVPC);
2130 }
2131
2132 /**
2133  *  e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
2134  *  @hw: pointer to the HW structure
2135  *
2136  *  After Rx enable, if manageability is enabled then there is likely some
2137  *  bad data at the start of the fifo and possibly in the DMA fifo.  This
2138  *  function clears the fifos and flushes any packets that came in as rx was
2139  *  being enabled.
2140  **/
2141 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
2142 {
2143         u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
2144         int i, ms_wait;
2145
2146         DEBUGFUNC("e1000_rx_fifo_flush_82575");
2147
2148         /* disable IPv6 options as per hardware errata */
2149         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2150         rfctl |= E1000_RFCTL_IPV6_EX_DIS;
2151         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2152
2153         if (hw->mac.type != e1000_82575 ||
2154             !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
2155                 return;
2156
2157         /* Disable all Rx queues */
2158         for (i = 0; i < 4; i++) {
2159                 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
2160                 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
2161                                 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
2162         }
2163         /* Poll all queues to verify they have shut down */
2164         for (ms_wait = 0; ms_wait < 10; ms_wait++) {
2165                 msec_delay(1);
2166                 rx_enabled = 0;
2167                 for (i = 0; i < 4; i++)
2168                         rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2169                 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
2170                         break;
2171         }
2172
2173         if (ms_wait == 10)
2174                 DEBUGOUT("Queue disable timed out after 10ms\n");
2175
2176         /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
2177          * incoming packets are rejected.  Set enable and wait 2ms so that
2178          * any packet that was coming in as RCTL.EN was set is flushed
2179          */
2180         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2181
2182         rlpml = E1000_READ_REG(hw, E1000_RLPML);
2183         E1000_WRITE_REG(hw, E1000_RLPML, 0);
2184
2185         rctl = E1000_READ_REG(hw, E1000_RCTL);
2186         temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2187         temp_rctl |= E1000_RCTL_LPE;
2188
2189         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
2190         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2191         E1000_WRITE_FLUSH(hw);
2192         msec_delay(2);
2193
2194         /* Enable Rx queues that were previously enabled and restore our
2195          * previous state
2196          */
2197         for (i = 0; i < 4; i++)
2198                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
2199         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2200         E1000_WRITE_FLUSH(hw);
2201
2202         E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
2203         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2204
2205         /* Flush receive errors generated by workaround */
2206         E1000_READ_REG(hw, E1000_ROC);
2207         E1000_READ_REG(hw, E1000_RNBC);
2208         E1000_READ_REG(hw, E1000_MPC);
2209 }
2210
2211 /**
2212  *  e1000_set_pcie_completion_timeout - set pci-e completion timeout
2213  *  @hw: pointer to the HW structure
2214  *
2215  *  The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2216  *  however the hardware default for these parts is 500us to 1ms which is less
2217  *  than the 10ms recommended by the pci-e spec.  To address this we need to
2218  *  increase the value to either 10ms to 200ms for capability version 1 config,
2219  *  or 16ms to 55ms for version 2.
2220  **/
2221 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2222 {
2223         u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2224         s32 ret_val = E1000_SUCCESS;
2225         u16 pcie_devctl2;
2226
2227         /* only take action if timeout value is defaulted to 0 */
2228         if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2229                 goto out;
2230
2231         /*
2232          * if capababilities version is type 1 we can write the
2233          * timeout of 10ms to 200ms through the GCR register
2234          */
2235         if (!(gcr & E1000_GCR_CAP_VER2)) {
2236                 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2237                 goto out;
2238         }
2239
2240         /*
2241          * for version 2 capabilities we need to write the config space
2242          * directly in order to set the completion timeout value for
2243          * 16ms to 55ms
2244          */
2245         ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2246                                           &pcie_devctl2);
2247         if (ret_val)
2248                 goto out;
2249
2250         pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2251
2252         ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2253                                            &pcie_devctl2);
2254 out:
2255         /* disable completion timeout resend */
2256         gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2257
2258         E1000_WRITE_REG(hw, E1000_GCR, gcr);
2259         return ret_val;
2260 }
2261
2262 /**
2263  *  e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2264  *  @hw: pointer to the hardware struct
2265  *  @enable: state to enter, either enabled or disabled
2266  *  @pf: Physical Function pool - do not set anti-spoofing for the PF
2267  *
2268  *  enables/disables L2 switch anti-spoofing functionality.
2269  **/
2270 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2271 {
2272         u32 reg_val, reg_offset;
2273
2274         switch (hw->mac.type) {
2275         case e1000_82576:
2276                 reg_offset = E1000_DTXSWC;
2277                 break;
2278         case e1000_i350:
2279         case e1000_i354:
2280                 reg_offset = E1000_TXSWC;
2281                 break;
2282         default:
2283                 return;
2284         }
2285
2286         reg_val = E1000_READ_REG(hw, reg_offset);
2287         if (enable) {
2288                 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2289                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2290                 /* The PF can spoof - it has to in order to
2291                  * support emulation mode NICs
2292                  */
2293                 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2294         } else {
2295                 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2296                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2297         }
2298         E1000_WRITE_REG(hw, reg_offset, reg_val);
2299 }
2300
2301 /**
2302  *  e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2303  *  @hw: pointer to the hardware struct
2304  *  @enable: state to enter, either enabled or disabled
2305  *
2306  *  enables/disables L2 switch loopback functionality.
2307  **/
2308 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2309 {
2310         u32 dtxswc;
2311
2312         switch (hw->mac.type) {
2313         case e1000_82576:
2314                 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2315                 if (enable)
2316                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2317                 else
2318                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2319                 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2320                 break;
2321         case e1000_i350:
2322         case e1000_i354:
2323                 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2324                 if (enable)
2325                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2326                 else
2327                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2328                 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2329                 break;
2330         default:
2331                 /* Currently no other hardware supports loopback */
2332                 break;
2333         }
2334
2335
2336 }
2337
2338 /**
2339  *  e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2340  *  @hw: pointer to the hardware struct
2341  *  @enable: state to enter, either enabled or disabled
2342  *
2343  *  enables/disables replication of packets across multiple pools.
2344  **/
2345 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2346 {
2347         u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2348
2349         if (enable)
2350                 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2351         else
2352                 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2353
2354         E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2355 }
2356
2357 /**
2358  *  e1000_read_phy_reg_82580 - Read 82580 MDI control register
2359  *  @hw: pointer to the HW structure
2360  *  @offset: register offset to be read
2361  *  @data: pointer to the read data
2362  *
2363  *  Reads the MDI control register in the PHY at offset and stores the
2364  *  information read to data.
2365  **/
2366 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2367 {
2368         s32 ret_val;
2369
2370         DEBUGFUNC("e1000_read_phy_reg_82580");
2371
2372         ret_val = hw->phy.ops.acquire(hw);
2373         if (ret_val)
2374                 goto out;
2375
2376         ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2377
2378         hw->phy.ops.release(hw);
2379
2380 out:
2381         return ret_val;
2382 }
2383
2384 /**
2385  *  e1000_write_phy_reg_82580 - Write 82580 MDI control register
2386  *  @hw: pointer to the HW structure
2387  *  @offset: register offset to write to
2388  *  @data: data to write to register at offset
2389  *
2390  *  Writes data to MDI control register in the PHY at offset.
2391  **/
2392 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2393 {
2394         s32 ret_val;
2395
2396         DEBUGFUNC("e1000_write_phy_reg_82580");
2397
2398         ret_val = hw->phy.ops.acquire(hw);
2399         if (ret_val)
2400                 goto out;
2401
2402         ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2403
2404         hw->phy.ops.release(hw);
2405
2406 out:
2407         return ret_val;
2408 }
2409
2410 /**
2411  *  e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2412  *  @hw: pointer to the HW structure
2413  *
2414  *  This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2415  *  the values found in the EEPROM.  This addresses an issue in which these
2416  *  bits are not restored from EEPROM after reset.
2417  **/
2418 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2419 {
2420         s32 ret_val = E1000_SUCCESS;
2421         u32 mdicnfg;
2422         u16 nvm_data = 0;
2423
2424         DEBUGFUNC("e1000_reset_mdicnfg_82580");
2425
2426         if (hw->mac.type != e1000_82580)
2427                 goto out;
2428         if (!e1000_sgmii_active_82575(hw))
2429                 goto out;
2430
2431         ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2432                                    NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2433                                    &nvm_data);
2434         if (ret_val) {
2435                 DEBUGOUT("NVM Read Error\n");
2436                 goto out;
2437         }
2438
2439         mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2440         if (nvm_data & NVM_WORD24_EXT_MDIO)
2441                 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2442         if (nvm_data & NVM_WORD24_COM_MDIO)
2443                 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2444         E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2445 out:
2446         return ret_val;
2447 }
2448
2449 /**
2450  *  e1000_reset_hw_82580 - Reset hardware
2451  *  @hw: pointer to the HW structure
2452  *
2453  *  This resets function or entire device (all ports, etc.)
2454  *  to a known state.
2455  **/
2456 static s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2457 {
2458         s32 ret_val = E1000_SUCCESS;
2459         /* BH SW mailbox bit in SW_FW_SYNC */
2460         u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2461         u32 ctrl;
2462         bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2463
2464         DEBUGFUNC("e1000_reset_hw_82580");
2465
2466         hw->dev_spec._82575.global_device_reset = FALSE;
2467
2468         /* 82580 does not reliably do global_device_reset due to hw errata */
2469         if (hw->mac.type == e1000_82580)
2470                 global_device_reset = FALSE;
2471
2472         /* Get current control state. */
2473         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2474
2475         /*
2476          * Prevent the PCI-E bus from sticking if there is no TLP connection
2477          * on the last TLP read/write transaction when MAC is reset.
2478          */
2479         ret_val = e1000_disable_pcie_master_generic(hw);
2480         if (ret_val)
2481                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2482
2483         DEBUGOUT("Masking off all interrupts\n");
2484         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2485         E1000_WRITE_REG(hw, E1000_RCTL, 0);
2486         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2487         E1000_WRITE_FLUSH(hw);
2488
2489         msec_delay(10);
2490
2491         /* Determine whether or not a global dev reset is requested */
2492         if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2493             swmbsw_mask))
2494                         global_device_reset = FALSE;
2495
2496         if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2497             E1000_STAT_DEV_RST_SET))
2498                 ctrl |= E1000_CTRL_DEV_RST;
2499         else
2500                 ctrl |= E1000_CTRL_RST;
2501
2502         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2503
2504         switch (hw->device_id) {
2505         case E1000_DEV_ID_DH89XXCC_SGMII:
2506                 break;
2507         default:
2508                 E1000_WRITE_FLUSH(hw);
2509                 break;
2510         }
2511
2512         /* Add delay to insure DEV_RST or RST has time to complete */
2513         msec_delay(5);
2514
2515         ret_val = e1000_get_auto_rd_done_generic(hw);
2516         if (ret_val) {
2517                 /*
2518                  * When auto config read does not complete, do not
2519                  * return with an error. This can happen in situations
2520                  * where there is no eeprom and prevents getting link.
2521                  */
2522                 DEBUGOUT("Auto Read Done did not complete\n");
2523         }
2524
2525         /* clear global device reset status bit */
2526         E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2527
2528         /* Clear any pending interrupt events. */
2529         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2530         E1000_READ_REG(hw, E1000_ICR);
2531
2532         ret_val = e1000_reset_mdicnfg_82580(hw);
2533         if (ret_val)
2534                 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2535
2536         /* Install any alternate MAC address into RAR0 */
2537         ret_val = e1000_check_alt_mac_addr_generic(hw);
2538
2539         /* Release semaphore */
2540         if (global_device_reset)
2541                 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2542
2543         return ret_val;
2544 }
2545
2546 /**
2547  *  e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2548  *  @data: data received by reading RXPBS register
2549  *
2550  *  The 82580 uses a table based approach for packet buffer allocation sizes.
2551  *  This function converts the retrieved value into the correct table value
2552  *     0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2553  *  0x0 36  72 144   1   2   4   8  16
2554  *  0x8 35  70 140 rsv rsv rsv rsv rsv
2555  */
2556 u16 e1000_rxpbs_adjust_82580(u32 data)
2557 {
2558         u16 ret_val = 0;
2559
2560         if (data < E1000_82580_RXPBS_TABLE_SIZE)
2561                 ret_val = e1000_82580_rxpbs_table[data];
2562
2563         return ret_val;
2564 }
2565
2566 /**
2567  *  e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2568  *  checksum
2569  *  @hw: pointer to the HW structure
2570  *  @offset: offset in words of the checksum protected region
2571  *
2572  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2573  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
2574  **/
2575 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2576 {
2577         s32 ret_val = E1000_SUCCESS;
2578         u16 checksum = 0;
2579         u16 i, nvm_data;
2580
2581         DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2582
2583         for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2584                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2585                 if (ret_val) {
2586                         DEBUGOUT("NVM Read Error\n");
2587                         goto out;
2588                 }
2589                 checksum += nvm_data;
2590         }
2591
2592         if (checksum != (u16) NVM_SUM) {
2593                 DEBUGOUT("NVM Checksum Invalid\n");
2594                 ret_val = -E1000_ERR_NVM;
2595                 goto out;
2596         }
2597
2598 out:
2599         return ret_val;
2600 }
2601
2602 /**
2603  *  e1000_update_nvm_checksum_with_offset - Update EEPROM
2604  *  checksum
2605  *  @hw: pointer to the HW structure
2606  *  @offset: offset in words of the checksum protected region
2607  *
2608  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
2609  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
2610  *  value to the EEPROM.
2611  **/
2612 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2613 {
2614         s32 ret_val;
2615         u16 checksum = 0;
2616         u16 i, nvm_data;
2617
2618         DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2619
2620         for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2621                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2622                 if (ret_val) {
2623                         DEBUGOUT("NVM Read Error while updating checksum.\n");
2624                         goto out;
2625                 }
2626                 checksum += nvm_data;
2627         }
2628         checksum = (u16) NVM_SUM - checksum;
2629         ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2630                                     &checksum);
2631         if (ret_val)
2632                 DEBUGOUT("NVM Write Error while updating checksum.\n");
2633
2634 out:
2635         return ret_val;
2636 }
2637
2638 /**
2639  *  e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2640  *  @hw: pointer to the HW structure
2641  *
2642  *  Calculates the EEPROM section checksum by reading/adding each word of
2643  *  the EEPROM and then verifies that the sum of the EEPROM is
2644  *  equal to 0xBABA.
2645  **/
2646 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2647 {
2648         s32 ret_val;
2649         u16 eeprom_regions_count = 1;
2650         u16 j, nvm_data;
2651         u16 nvm_offset;
2652
2653         DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2654
2655         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2656         if (ret_val) {
2657                 DEBUGOUT("NVM Read Error\n");
2658                 goto out;
2659         }
2660
2661         if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2662                 /* if chekcsums compatibility bit is set validate checksums
2663                  * for all 4 ports. */
2664                 eeprom_regions_count = 4;
2665         }
2666
2667         for (j = 0; j < eeprom_regions_count; j++) {
2668                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2669                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2670                                                                   nvm_offset);
2671                 if (ret_val != E1000_SUCCESS)
2672                         goto out;
2673         }
2674
2675 out:
2676         return ret_val;
2677 }
2678
2679 /**
2680  *  e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2681  *  @hw: pointer to the HW structure
2682  *
2683  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2684  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2685  *  checksum and writes the value to the EEPROM.
2686  **/
2687 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2688 {
2689         s32 ret_val;
2690         u16 j, nvm_data;
2691         u16 nvm_offset;
2692
2693         DEBUGFUNC("e1000_update_nvm_checksum_82580");
2694
2695         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2696         if (ret_val) {
2697                 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2698                 goto out;
2699         }
2700
2701         if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2702                 /* set compatibility bit to validate checksums appropriately */
2703                 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2704                 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2705                                             &nvm_data);
2706                 if (ret_val) {
2707                         DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2708                         goto out;
2709                 }
2710         }
2711
2712         for (j = 0; j < 4; j++) {
2713                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2714                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2715                 if (ret_val)
2716                         goto out;
2717         }
2718
2719 out:
2720         return ret_val;
2721 }
2722
2723 /**
2724  *  e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2725  *  @hw: pointer to the HW structure
2726  *
2727  *  Calculates the EEPROM section checksum by reading/adding each word of
2728  *  the EEPROM and then verifies that the sum of the EEPROM is
2729  *  equal to 0xBABA.
2730  **/
2731 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2732 {
2733         s32 ret_val = E1000_SUCCESS;
2734         u16 j;
2735         u16 nvm_offset;
2736
2737         DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2738
2739         for (j = 0; j < 4; j++) {
2740                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2741                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2742                                                                   nvm_offset);
2743                 if (ret_val != E1000_SUCCESS)
2744                         goto out;
2745         }
2746
2747 out:
2748         return ret_val;
2749 }
2750
2751 /**
2752  *  e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2753  *  @hw: pointer to the HW structure
2754  *
2755  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2756  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2757  *  checksum and writes the value to the EEPROM.
2758  **/
2759 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2760 {
2761         s32 ret_val = E1000_SUCCESS;
2762         u16 j;
2763         u16 nvm_offset;
2764
2765         DEBUGFUNC("e1000_update_nvm_checksum_i350");
2766
2767         for (j = 0; j < 4; j++) {
2768                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2769                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2770                 if (ret_val != E1000_SUCCESS)
2771                         goto out;
2772         }
2773
2774 out:
2775         return ret_val;
2776 }
2777
2778 /**
2779  *  __e1000_access_emi_reg - Read/write EMI register
2780  *  @hw: pointer to the HW structure
2781  *  @addr: EMI address to program
2782  *  @data: pointer to value to read/write from/to the EMI address
2783  *  @read: boolean flag to indicate read or write
2784  **/
2785 static s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
2786                                   u16 *data, bool read)
2787 {
2788         s32 ret_val;
2789
2790         DEBUGFUNC("__e1000_access_emi_reg");
2791
2792         ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2793         if (ret_val)
2794                 return ret_val;
2795
2796         if (read)
2797                 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2798         else
2799                 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2800
2801         return ret_val;
2802 }
2803
2804 /**
2805  *  e1000_read_emi_reg - Read Extended Management Interface register
2806  *  @hw: pointer to the HW structure
2807  *  @addr: EMI address to program
2808  *  @data: value to be read from the EMI address
2809  **/
2810 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2811 {
2812         DEBUGFUNC("e1000_read_emi_reg");
2813
2814         return __e1000_access_emi_reg(hw, addr, data, TRUE);
2815 }
2816
2817 /**
2818  *  e1000_initialize_M88E1512_phy - Initialize M88E1512 PHY
2819  *  @hw: pointer to the HW structure
2820  *
2821  *  Initialize Marverl 1512 to work correctly with Avoton.
2822  **/
2823 s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw)
2824 {
2825         struct e1000_phy_info *phy = &hw->phy;
2826         s32 ret_val = E1000_SUCCESS;
2827
2828         DEBUGFUNC("e1000_initialize_M88E1512_phy");
2829
2830         /* Check if this is correct PHY. */
2831         if (phy->id != M88E1512_E_PHY_ID)
2832                 goto out;
2833
2834         /* Switch to PHY page 0xFF. */
2835         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2836         if (ret_val)
2837                 goto out;
2838
2839         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2840         if (ret_val)
2841                 goto out;
2842
2843         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2844         if (ret_val)
2845                 goto out;
2846
2847         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2848         if (ret_val)
2849                 goto out;
2850
2851         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2852         if (ret_val)
2853                 goto out;
2854
2855         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2856         if (ret_val)
2857                 goto out;
2858
2859         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2860         if (ret_val)
2861                 goto out;
2862
2863         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2864         if (ret_val)
2865                 goto out;
2866
2867         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2868         if (ret_val)
2869                 goto out;
2870
2871         /* Switch to PHY page 0xFB. */
2872         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2873         if (ret_val)
2874                 goto out;
2875
2876         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2877         if (ret_val)
2878                 goto out;
2879
2880         /* Switch to PHY page 0x12. */
2881         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2882         if (ret_val)
2883                 goto out;
2884
2885         /* Change mode to SGMII-to-Copper */
2886         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2887         if (ret_val)
2888                 goto out;
2889
2890         /* Return the PHY to page 0. */
2891         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2892         if (ret_val)
2893                 goto out;
2894
2895         ret_val = phy->ops.commit(hw);
2896         if (ret_val) {
2897                 DEBUGOUT("Error committing the PHY changes\n");
2898                 return ret_val;
2899         }
2900
2901         msec_delay(1000);
2902 out:
2903         return ret_val;
2904 }
2905
2906 /**
2907  *  e1000_set_eee_i350 - Enable/disable EEE support
2908  *  @hw: pointer to the HW structure
2909  *  @adv1g: boolean flag enabling 1G EEE advertisement
2910  *  @adv100m: boolean flag enabling 100M EEE advertisement
2911  *
2912  *  Enable/disable EEE based on setting in dev_spec structure.
2913  *
2914  **/
2915 s32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
2916 {
2917         u32 ipcnfg, eeer;
2918
2919         DEBUGFUNC("e1000_set_eee_i350");
2920
2921         if ((hw->mac.type < e1000_i350) ||
2922             (hw->phy.media_type != e1000_media_type_copper))
2923                 goto out;
2924         ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2925         eeer = E1000_READ_REG(hw, E1000_EEER);
2926
2927         /* enable or disable per user setting */
2928         if (!(hw->dev_spec._82575.eee_disable)) {
2929                 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
2930
2931                 if (adv100M)
2932                         ipcnfg |= E1000_IPCNFG_EEE_100M_AN;
2933                 else
2934                         ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN;
2935
2936                 if (adv1G)
2937                         ipcnfg |= E1000_IPCNFG_EEE_1G_AN;
2938                 else
2939                         ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN;
2940
2941                 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2942                          E1000_EEER_LPI_FC);
2943
2944                 /* This bit should not be set in normal operation. */
2945                 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2946                         DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
2947         } else {
2948                 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2949                 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2950                           E1000_EEER_LPI_FC);
2951         }
2952         E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2953         E1000_WRITE_REG(hw, E1000_EEER, eeer);
2954         E1000_READ_REG(hw, E1000_IPCNFG);
2955         E1000_READ_REG(hw, E1000_EEER);
2956 out:
2957
2958         return E1000_SUCCESS;
2959 }
2960
2961 /**
2962  *  e1000_set_eee_i354 - Enable/disable EEE support
2963  *  @hw: pointer to the HW structure
2964  *  @adv1g: boolean flag enabling 1G EEE advertisement
2965  *  @adv100m: boolean flag enabling 100M EEE advertisement
2966  *
2967  *  Enable/disable EEE legacy mode based on setting in dev_spec structure.
2968  *
2969  **/
2970 s32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
2971 {
2972         struct e1000_phy_info *phy = &hw->phy;
2973         s32 ret_val = E1000_SUCCESS;
2974         u16 phy_data;
2975
2976         DEBUGFUNC("e1000_set_eee_i354");
2977
2978         if ((hw->phy.media_type != e1000_media_type_copper) ||
2979             ((phy->id != M88E1543_E_PHY_ID) &&
2980             (phy->id != M88E1512_E_PHY_ID)))
2981                 goto out;
2982
2983         if (!hw->dev_spec._82575.eee_disable) {
2984                 /* Switch to PHY page 18. */
2985                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2986                 if (ret_val)
2987                         goto out;
2988
2989                 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2990                                             &phy_data);
2991                 if (ret_val)
2992                         goto out;
2993
2994                 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2995                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2996                                              phy_data);
2997                 if (ret_val)
2998                         goto out;
2999
3000                 /* Return the PHY to page 0. */
3001                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
3002                 if (ret_val)
3003                         goto out;
3004
3005                 /* Turn on EEE advertisement. */
3006                 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3007                                                E1000_EEE_ADV_DEV_I354,
3008                                                &phy_data);
3009                 if (ret_val)
3010                         goto out;
3011
3012                 if (adv100M)
3013                         phy_data |= E1000_EEE_ADV_100_SUPPORTED;
3014                 else
3015                         phy_data &= ~E1000_EEE_ADV_100_SUPPORTED;
3016
3017                 if (adv1G)
3018                         phy_data |= E1000_EEE_ADV_1000_SUPPORTED;
3019                 else
3020                         phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED;
3021
3022                 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3023                                                 E1000_EEE_ADV_DEV_I354,
3024                                                 phy_data);
3025         } else {
3026                 /* Turn off EEE advertisement. */
3027                 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3028                                                E1000_EEE_ADV_DEV_I354,
3029                                                &phy_data);
3030                 if (ret_val)
3031                         goto out;
3032
3033                 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
3034                               E1000_EEE_ADV_1000_SUPPORTED);
3035                 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3036                                                 E1000_EEE_ADV_DEV_I354,
3037                                                 phy_data);
3038         }
3039
3040 out:
3041         return ret_val;
3042 }
3043
3044 /**
3045  *  e1000_get_eee_status_i354 - Get EEE status
3046  *  @hw: pointer to the HW structure
3047  *  @status: EEE status
3048  *
3049  *  Get EEE status by guessing based on whether Tx or Rx LPI indications have
3050  *  been received.
3051  **/
3052 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
3053 {
3054         struct e1000_phy_info *phy = &hw->phy;
3055         s32 ret_val = E1000_SUCCESS;
3056         u16 phy_data;
3057
3058         DEBUGFUNC("e1000_get_eee_status_i354");
3059
3060         /* Check if EEE is supported on this device. */
3061         if ((hw->phy.media_type != e1000_media_type_copper) ||
3062             ((phy->id != M88E1543_E_PHY_ID) &&
3063             (phy->id != M88E1512_E_PHY_ID)))
3064                 goto out;
3065
3066         ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
3067                                        E1000_PCS_STATUS_DEV_I354,
3068                                        &phy_data);
3069         if (ret_val)
3070                 goto out;
3071
3072         *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
3073                               E1000_PCS_STATUS_RX_LPI_RCVD) ? TRUE : FALSE;
3074
3075 out:
3076         return ret_val;
3077 }
3078
3079 /* Due to a hw errata, if the host tries to  configure the VFTA register
3080  * while performing queries from the BMC or DMA, then the VFTA in some
3081  * cases won't be written.
3082  */
3083
3084 /**
3085  *  e1000_clear_vfta_i350 - Clear VLAN filter table
3086  *  @hw: pointer to the HW structure
3087  *
3088  *  Clears the register array which contains the VLAN filter table by
3089  *  setting all the values to 0.
3090  **/
3091 void e1000_clear_vfta_i350(struct e1000_hw *hw)
3092 {
3093         u32 offset;
3094         int i;
3095
3096         DEBUGFUNC("e1000_clear_vfta_350");
3097
3098         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
3099                 for (i = 0; i < 10; i++)
3100                         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
3101
3102                 E1000_WRITE_FLUSH(hw);
3103         }
3104 }
3105
3106 /**
3107  *  e1000_write_vfta_i350 - Write value to VLAN filter table
3108  *  @hw: pointer to the HW structure
3109  *  @offset: register offset in VLAN filter table
3110  *  @value: register value written to VLAN filter table
3111  *
3112  *  Writes value at the given offset in the register array which stores
3113  *  the VLAN filter table.
3114  **/
3115 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
3116 {
3117         int i;
3118
3119         DEBUGFUNC("e1000_write_vfta_350");
3120
3121         for (i = 0; i < 10; i++)
3122                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
3123
3124         E1000_WRITE_FLUSH(hw);
3125 }
3126
3127
3128 /**
3129  *  e1000_set_i2c_bb - Enable I2C bit-bang
3130  *  @hw: pointer to the HW structure
3131  *
3132  *  Enable I2C bit-bang interface
3133  *
3134  **/
3135 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
3136 {
3137         s32 ret_val = E1000_SUCCESS;
3138         u32 ctrl_ext, i2cparams;
3139
3140         DEBUGFUNC("e1000_set_i2c_bb");
3141
3142         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3143         ctrl_ext |= E1000_CTRL_I2C_ENA;
3144         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3145         E1000_WRITE_FLUSH(hw);
3146
3147         i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
3148         i2cparams |= E1000_I2CBB_EN;
3149         i2cparams |= E1000_I2C_DATA_OE_N;
3150         i2cparams |= E1000_I2C_CLK_OE_N;
3151         E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
3152         E1000_WRITE_FLUSH(hw);
3153
3154         return ret_val;
3155 }
3156
3157 /**
3158  *  e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
3159  *  @hw: pointer to hardware structure
3160  *  @byte_offset: byte offset to read
3161  *  @dev_addr: device address
3162  *  @data: value read
3163  *
3164  *  Performs byte read operation over I2C interface at
3165  *  a specified device address.
3166  **/
3167 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3168                                 u8 dev_addr, u8 *data)
3169 {
3170         s32 status = E1000_SUCCESS;
3171         u32 max_retry = 10;
3172         u32 retry = 1;
3173         u16 swfw_mask = 0;
3174
3175         bool nack = TRUE;
3176
3177         DEBUGFUNC("e1000_read_i2c_byte_generic");
3178
3179         swfw_mask = E1000_SWFW_PHY0_SM;
3180
3181         do {
3182                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
3183                     != E1000_SUCCESS) {
3184                         status = E1000_ERR_SWFW_SYNC;
3185                         goto read_byte_out;
3186                 }
3187
3188                 e1000_i2c_start(hw);
3189
3190                 /* Device Address and write indication */
3191                 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3192                 if (status != E1000_SUCCESS)
3193                         goto fail;
3194
3195                 status = e1000_get_i2c_ack(hw);
3196                 if (status != E1000_SUCCESS)
3197                         goto fail;
3198
3199                 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3200                 if (status != E1000_SUCCESS)
3201                         goto fail;
3202
3203                 status = e1000_get_i2c_ack(hw);
3204                 if (status != E1000_SUCCESS)
3205                         goto fail;
3206
3207                 e1000_i2c_start(hw);
3208
3209                 /* Device Address and read indication */
3210                 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
3211                 if (status != E1000_SUCCESS)
3212                         goto fail;
3213
3214                 status = e1000_get_i2c_ack(hw);
3215                 if (status != E1000_SUCCESS)
3216                         goto fail;
3217
3218                 status = e1000_clock_in_i2c_byte(hw, data);
3219                 if (status != E1000_SUCCESS)
3220                         goto fail;
3221
3222                 status = e1000_clock_out_i2c_bit(hw, nack);
3223                 if (status != E1000_SUCCESS)
3224                         goto fail;
3225
3226                 e1000_i2c_stop(hw);
3227                 break;
3228
3229 fail:
3230                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3231                 msec_delay(100);
3232                 e1000_i2c_bus_clear(hw);
3233                 retry++;
3234                 if (retry < max_retry)
3235                         DEBUGOUT("I2C byte read error - Retrying.\n");
3236                 else
3237                         DEBUGOUT("I2C byte read error.\n");
3238
3239         } while (retry < max_retry);
3240
3241         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3242
3243 read_byte_out:
3244
3245         return status;
3246 }
3247
3248 /**
3249  *  e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
3250  *  @hw: pointer to hardware structure
3251  *  @byte_offset: byte offset to write
3252  *  @dev_addr: device address
3253  *  @data: value to write
3254  *
3255  *  Performs byte write operation over I2C interface at
3256  *  a specified device address.
3257  **/
3258 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3259                                  u8 dev_addr, u8 data)
3260 {
3261         s32 status = E1000_SUCCESS;
3262         u32 max_retry = 1;
3263         u32 retry = 0;
3264         u16 swfw_mask = 0;
3265
3266         DEBUGFUNC("e1000_write_i2c_byte_generic");
3267
3268         swfw_mask = E1000_SWFW_PHY0_SM;
3269
3270         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
3271                 status = E1000_ERR_SWFW_SYNC;
3272                 goto write_byte_out;
3273         }
3274
3275         do {
3276                 e1000_i2c_start(hw);
3277
3278                 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3279                 if (status != E1000_SUCCESS)
3280                         goto fail;
3281
3282                 status = e1000_get_i2c_ack(hw);
3283                 if (status != E1000_SUCCESS)
3284                         goto fail;
3285
3286                 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3287                 if (status != E1000_SUCCESS)
3288                         goto fail;
3289
3290                 status = e1000_get_i2c_ack(hw);
3291                 if (status != E1000_SUCCESS)
3292                         goto fail;
3293
3294                 status = e1000_clock_out_i2c_byte(hw, data);
3295                 if (status != E1000_SUCCESS)
3296                         goto fail;
3297
3298                 status = e1000_get_i2c_ack(hw);
3299                 if (status != E1000_SUCCESS)
3300                         goto fail;
3301
3302                 e1000_i2c_stop(hw);
3303                 break;
3304
3305 fail:
3306                 e1000_i2c_bus_clear(hw);
3307                 retry++;
3308                 if (retry < max_retry)
3309                         DEBUGOUT("I2C byte write error - Retrying.\n");
3310                 else
3311                         DEBUGOUT("I2C byte write error.\n");
3312         } while (retry < max_retry);
3313
3314         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3315
3316 write_byte_out:
3317
3318         return status;
3319 }
3320
3321 /**
3322  *  e1000_i2c_start - Sets I2C start condition
3323  *  @hw: pointer to hardware structure
3324  *
3325  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
3326  **/
3327 static void e1000_i2c_start(struct e1000_hw *hw)
3328 {
3329         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3330
3331         DEBUGFUNC("e1000_i2c_start");
3332
3333         /* Start condition must begin with data and clock high */
3334         e1000_set_i2c_data(hw, &i2cctl, 1);
3335         e1000_raise_i2c_clk(hw, &i2cctl);
3336
3337         /* Setup time for start condition (4.7us) */
3338         usec_delay(E1000_I2C_T_SU_STA);
3339
3340         e1000_set_i2c_data(hw, &i2cctl, 0);
3341
3342         /* Hold time for start condition (4us) */
3343         usec_delay(E1000_I2C_T_HD_STA);
3344
3345         e1000_lower_i2c_clk(hw, &i2cctl);
3346
3347         /* Minimum low period of clock is 4.7 us */
3348         usec_delay(E1000_I2C_T_LOW);
3349
3350 }
3351
3352 /**
3353  *  e1000_i2c_stop - Sets I2C stop condition
3354  *  @hw: pointer to hardware structure
3355  *
3356  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
3357  **/
3358 static void e1000_i2c_stop(struct e1000_hw *hw)
3359 {
3360         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3361
3362         DEBUGFUNC("e1000_i2c_stop");
3363
3364         /* Stop condition must begin with data low and clock high */
3365         e1000_set_i2c_data(hw, &i2cctl, 0);
3366         e1000_raise_i2c_clk(hw, &i2cctl);
3367
3368         /* Setup time for stop condition (4us) */
3369         usec_delay(E1000_I2C_T_SU_STO);
3370
3371         e1000_set_i2c_data(hw, &i2cctl, 1);
3372
3373         /* bus free time between stop and start (4.7us)*/
3374         usec_delay(E1000_I2C_T_BUF);
3375 }
3376
3377 /**
3378  *  e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3379  *  @hw: pointer to hardware structure
3380  *  @data: data byte to clock in
3381  *
3382  *  Clocks in one byte data via I2C data/clock
3383  **/
3384 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3385 {
3386         s32 i;
3387         bool bit = 0;
3388
3389         DEBUGFUNC("e1000_clock_in_i2c_byte");
3390
3391         *data = 0;
3392         for (i = 7; i >= 0; i--) {
3393                 e1000_clock_in_i2c_bit(hw, &bit);
3394                 *data |= bit << i;
3395         }
3396
3397         return E1000_SUCCESS;
3398 }
3399
3400 /**
3401  *  e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3402  *  @hw: pointer to hardware structure
3403  *  @data: data byte clocked out
3404  *
3405  *  Clocks out one byte data via I2C data/clock
3406  **/
3407 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3408 {
3409         s32 status = E1000_SUCCESS;
3410         s32 i;
3411         u32 i2cctl;
3412         bool bit = 0;
3413
3414         DEBUGFUNC("e1000_clock_out_i2c_byte");
3415
3416         for (i = 7; i >= 0; i--) {
3417                 bit = (data >> i) & 0x1;
3418                 status = e1000_clock_out_i2c_bit(hw, bit);
3419
3420                 if (status != E1000_SUCCESS)
3421                         break;
3422         }
3423
3424         /* Release SDA line (set high) */
3425         i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3426
3427         i2cctl |= E1000_I2C_DATA_OE_N;
3428         E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3429         E1000_WRITE_FLUSH(hw);
3430
3431         return status;
3432 }
3433
3434 /**
3435  *  e1000_get_i2c_ack - Polls for I2C ACK
3436  *  @hw: pointer to hardware structure
3437  *
3438  *  Clocks in/out one bit via I2C data/clock
3439  **/
3440 static s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3441 {
3442         s32 status = E1000_SUCCESS;
3443         u32 i = 0;
3444         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3445         u32 timeout = 10;
3446         bool ack = TRUE;
3447
3448         DEBUGFUNC("e1000_get_i2c_ack");
3449
3450         e1000_raise_i2c_clk(hw, &i2cctl);
3451
3452         /* Minimum high period of clock is 4us */
3453         usec_delay(E1000_I2C_T_HIGH);
3454
3455         /* Wait until SCL returns high */
3456         for (i = 0; i < timeout; i++) {
3457                 usec_delay(1);
3458                 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3459                 if (i2cctl & E1000_I2C_CLK_IN)
3460                         break;
3461         }
3462         if (!(i2cctl & E1000_I2C_CLK_IN))
3463                 return E1000_ERR_I2C;
3464
3465         ack = e1000_get_i2c_data(&i2cctl);
3466         if (ack) {
3467                 DEBUGOUT("I2C ack was not received.\n");
3468                 status = E1000_ERR_I2C;
3469         }
3470
3471         e1000_lower_i2c_clk(hw, &i2cctl);
3472
3473         /* Minimum low period of clock is 4.7 us */
3474         usec_delay(E1000_I2C_T_LOW);
3475
3476         return status;
3477 }
3478
3479 /**
3480  *  e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3481  *  @hw: pointer to hardware structure
3482  *  @data: read data value
3483  *
3484  *  Clocks in one bit via I2C data/clock
3485  **/
3486 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3487 {
3488         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3489
3490         DEBUGFUNC("e1000_clock_in_i2c_bit");
3491
3492         e1000_raise_i2c_clk(hw, &i2cctl);
3493
3494         /* Minimum high period of clock is 4us */
3495         usec_delay(E1000_I2C_T_HIGH);
3496
3497         i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3498         *data = e1000_get_i2c_data(&i2cctl);
3499
3500         e1000_lower_i2c_clk(hw, &i2cctl);
3501
3502         /* Minimum low period of clock is 4.7 us */
3503         usec_delay(E1000_I2C_T_LOW);
3504
3505         return E1000_SUCCESS;
3506 }
3507
3508 /**
3509  *  e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3510  *  @hw: pointer to hardware structure
3511  *  @data: data value to write
3512  *
3513  *  Clocks out one bit via I2C data/clock
3514  **/
3515 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3516 {
3517         s32 status;
3518         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3519
3520         DEBUGFUNC("e1000_clock_out_i2c_bit");
3521
3522         status = e1000_set_i2c_data(hw, &i2cctl, data);
3523         if (status == E1000_SUCCESS) {
3524                 e1000_raise_i2c_clk(hw, &i2cctl);
3525
3526                 /* Minimum high period of clock is 4us */
3527                 usec_delay(E1000_I2C_T_HIGH);
3528
3529                 e1000_lower_i2c_clk(hw, &i2cctl);
3530
3531                 /* Minimum low period of clock is 4.7 us.
3532                  * This also takes care of the data hold time.
3533                  */
3534                 usec_delay(E1000_I2C_T_LOW);
3535         } else {
3536                 status = E1000_ERR_I2C;
3537                 DEBUGOUT1("I2C data was not set to %X\n", data);
3538         }
3539
3540         return status;
3541 }
3542 /**
3543  *  e1000_raise_i2c_clk - Raises the I2C SCL clock
3544  *  @hw: pointer to hardware structure
3545  *  @i2cctl: Current value of I2CCTL register
3546  *
3547  *  Raises the I2C clock line '0'->'1'
3548  **/
3549 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3550 {
3551         DEBUGFUNC("e1000_raise_i2c_clk");
3552
3553         *i2cctl |= E1000_I2C_CLK_OUT;
3554         *i2cctl &= ~E1000_I2C_CLK_OE_N;
3555         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3556         E1000_WRITE_FLUSH(hw);
3557
3558         /* SCL rise time (1000ns) */
3559         usec_delay(E1000_I2C_T_RISE);
3560 }
3561
3562 /**
3563  *  e1000_lower_i2c_clk - Lowers the I2C SCL clock
3564  *  @hw: pointer to hardware structure
3565  *  @i2cctl: Current value of I2CCTL register
3566  *
3567  *  Lowers the I2C clock line '1'->'0'
3568  **/
3569 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3570 {
3571
3572         DEBUGFUNC("e1000_lower_i2c_clk");
3573
3574         *i2cctl &= ~E1000_I2C_CLK_OUT;
3575         *i2cctl &= ~E1000_I2C_CLK_OE_N;
3576         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3577         E1000_WRITE_FLUSH(hw);
3578
3579         /* SCL fall time (300ns) */
3580         usec_delay(E1000_I2C_T_FALL);
3581 }
3582
3583 /**
3584  *  e1000_set_i2c_data - Sets the I2C data bit
3585  *  @hw: pointer to hardware structure
3586  *  @i2cctl: Current value of I2CCTL register
3587  *  @data: I2C data value (0 or 1) to set
3588  *
3589  *  Sets the I2C data bit
3590  **/
3591 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3592 {
3593         s32 status = E1000_SUCCESS;
3594
3595         DEBUGFUNC("e1000_set_i2c_data");
3596
3597         if (data)
3598                 *i2cctl |= E1000_I2C_DATA_OUT;
3599         else
3600                 *i2cctl &= ~E1000_I2C_DATA_OUT;
3601
3602         *i2cctl &= ~E1000_I2C_DATA_OE_N;
3603         *i2cctl |= E1000_I2C_CLK_OE_N;
3604         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3605         E1000_WRITE_FLUSH(hw);
3606
3607         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3608         usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3609
3610         *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3611         if (data != e1000_get_i2c_data(i2cctl)) {
3612                 status = E1000_ERR_I2C;
3613                 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3614         }
3615
3616         return status;
3617 }
3618
3619 /**
3620  *  e1000_get_i2c_data - Reads the I2C SDA data bit
3621  *  @hw: pointer to hardware structure
3622  *  @i2cctl: Current value of I2CCTL register
3623  *
3624  *  Returns the I2C data bit value
3625  **/
3626 static bool e1000_get_i2c_data(u32 *i2cctl)
3627 {
3628         bool data;
3629
3630         DEBUGFUNC("e1000_get_i2c_data");
3631
3632         if (*i2cctl & E1000_I2C_DATA_IN)
3633                 data = 1;
3634         else
3635                 data = 0;
3636
3637         return data;
3638 }
3639
3640 /**
3641  *  e1000_i2c_bus_clear - Clears the I2C bus
3642  *  @hw: pointer to hardware structure
3643  *
3644  *  Clears the I2C bus by sending nine clock pulses.
3645  *  Used when data line is stuck low.
3646  **/
3647 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3648 {
3649         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3650         u32 i;
3651
3652         DEBUGFUNC("e1000_i2c_bus_clear");
3653
3654         e1000_i2c_start(hw);
3655
3656         e1000_set_i2c_data(hw, &i2cctl, 1);
3657
3658         for (i = 0; i < 9; i++) {
3659                 e1000_raise_i2c_clk(hw, &i2cctl);
3660
3661                 /* Min high period of clock is 4us */
3662                 usec_delay(E1000_I2C_T_HIGH);
3663
3664                 e1000_lower_i2c_clk(hw, &i2cctl);
3665
3666                 /* Min low period of clock is 4.7us*/
3667                 usec_delay(E1000_I2C_T_LOW);
3668         }
3669
3670         e1000_i2c_start(hw);
3671
3672         /* Put the i2c bus back to default state */
3673         e1000_i2c_stop(hw);
3674 }
3675