sys/dev/netif/bce/if_bce.c

   1 /*-
   2  * Copyright (c) 2006-2007 Broadcom Corporation
   3  *      David Christensen <davidch@broadcom.com>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the name of Broadcom Corporation nor the name of its contributors
  15  *    may be used to endorse or promote products derived from this software
  16  *    without specific prior written consent.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
  19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
  22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  28  * THE POSSIBILITY OF SUCH DAMAGE.
  29  *
  30  * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
  31  */
  32
  33 /*
  34  * The following controllers are supported by this driver:
  35  *   BCM5706C A2, A3
  36  *   BCM5706S A2, A3
  37  *   BCM5708C B1, B2
  38  *   BCM5708S B1, B2
  39  *   BCM5709C A1, C0
  40  *   BCM5716  C0
  41  *
  42  * The following controllers are not supported by this driver:
  43  *   BCM5706C A0, A1
  44  *   BCM5706S A0, A1
  45  *   BCM5708C A0, B0
  46  *   BCM5708S A0, B0
  47  *   BCM5709C A0, B0, B1
  48  *   BCM5709S A0, A1, B0, B1, B2, C0
  49  */
  50
  51 #include "opt_bce.h"
  52 #include "opt_polling.h"
  53
  54 #include <sys/param.h>
  55 #include <sys/bus.h>
  56 #include <sys/endian.h>
  57 #include <sys/kernel.h>
  58 #include <sys/interrupt.h>
  59 #include <sys/mbuf.h>
  60 #include <sys/malloc.h>
  61 #include <sys/queue.h>
  62 #ifdef BCE_DEBUG
  63 #include <sys/random.h>
  64 #endif
  65 #include <sys/rman.h>
  66 #include <sys/serialize.h>
  67 #include <sys/socket.h>
  68 #include <sys/sockio.h>
  69 #include <sys/sysctl.h>
  70
  71 #include <net/bpf.h>
  72 #include <net/ethernet.h>
  73 #include <net/if.h>
  74 #include <net/if_arp.h>
  75 #include <net/if_dl.h>
  76 #include <net/if_media.h>
  77 #include <net/if_types.h>
  78 #include <net/ifq_var.h>
  79 #include <net/vlan/if_vlan_var.h>
  80 #include <net/vlan/if_vlan_ether.h>
  81
  82 #include <dev/netif/mii_layer/mii.h>
  83 #include <dev/netif/mii_layer/miivar.h>
  84
  85 #include <bus/pci/pcireg.h>
  86 #include <bus/pci/pcivar.h>
  87
  88 #include "miibus_if.h"
  89
  90 #include <dev/netif/bce/if_bcereg.h>
  91 #include <dev/netif/bce/if_bcefw.h>
  92
  93 /****************************************************************************/
  94 /* BCE Debug Options                                                        */
  95 /****************************************************************************/
  96 #ifdef BCE_DEBUG
  97
  98 static uint32_t bce_debug = BCE_WARN;
  99
 100 /*
 101  *          0 = Never
 102  *          1 = 1 in 2,147,483,648
 103  *        256 = 1 in     8,388,608
 104  *       2048 = 1 in     1,048,576
 105  *      65536 = 1 in        32,768
 106  *    1048576 = 1 in         2,048
 107  *  268435456 = 1 in             8
 108  *  536870912 = 1 in             4
 109  * 1073741824 = 1 in             2
 110  *
 111  * bce_debug_l2fhdr_status_check:
 112  *     How often the l2_fhdr frame error check will fail.
 113  *
 114  * bce_debug_unexpected_attention:
 115  *     How often the unexpected attention check will fail.
 116  *
 117  * bce_debug_mbuf_allocation_failure:
 118  *     How often to simulate an mbuf allocation failure.
 119  *
 120  * bce_debug_dma_map_addr_failure:
 121  *     How often to simulate a DMA mapping failure.
 122  *
 123  * bce_debug_bootcode_running_failure:
 124  *     How often to simulate a bootcode failure.
 125  */
 126 static int      bce_debug_l2fhdr_status_check = 0;
 127 static int      bce_debug_unexpected_attention = 0;
 128 static int      bce_debug_mbuf_allocation_failure = 0;
 129 static int      bce_debug_dma_map_addr_failure = 0;
 130 static int      bce_debug_bootcode_running_failure = 0;
 131
 132 #endif  /* BCE_DEBUG */
 133
 134
 135 /****************************************************************************/
 136 /* PCI Device ID Table                                                      */
 137 /*                                                                          */
 138 /* Used by bce_probe() to identify the devices supported by this driver.    */
 139 /****************************************************************************/
 140 #define BCE_DEVDESC_MAX         64
 141
 142 static struct bce_type bce_devs[] = {
 143         /* BCM5706C Controllers and OEM boards. */
 144         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3101,
 145                 "HP NC370T Multifunction Gigabit Server Adapter" },
 146         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3106,
 147                 "HP NC370i Multifunction Gigabit Server Adapter" },
 148         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3070,
 149                 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
 150         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x1709,
 151                 "HP NC371i Multifunction Gigabit Server Adapter" },
 152         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  PCI_ANY_ID,  PCI_ANY_ID,
 153                 "Broadcom NetXtreme II BCM5706 1000Base-T" },
 154
 155         /* BCM5706S controllers and OEM boards. */
 156         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
 157                 "HP NC370F Multifunction Gigabit Server Adapter" },
 158         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID,  PCI_ANY_ID,
 159                 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
 160
 161         /* BCM5708C controllers and OEM boards. */
 162         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7037,
 163                 "HP NC373T PCIe Multifunction Gig Server Adapter" },
 164         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7038,
 165                 "HP NC373i Multifunction Gigabit Server Adapter" },
 166         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7045,
 167                 "HP NC374m PCIe Multifunction Adapter" },
 168         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  PCI_ANY_ID,  PCI_ANY_ID,
 169                 "Broadcom NetXtreme II BCM5708 1000Base-T" },
 170
 171         /* BCM5708S controllers and OEM boards. */
 172         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x1706,
 173                 "HP NC373m Multifunction Gigabit Server Adapter" },
 174         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703b,
 175                 "HP NC373i Multifunction Gigabit Server Adapter" },
 176         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703d,
 177                 "HP NC373F PCIe Multifunc Giga Server Adapter" },
 178         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  PCI_ANY_ID,  PCI_ANY_ID,
 179                 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
 180
 181         /* BCM5709C controllers and OEM boards. */
 182         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7055,
 183                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 184         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7059,
 185                 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
 186         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  PCI_ANY_ID,  PCI_ANY_ID,
 187                 "Broadcom NetXtreme II BCM5709 1000Base-T" },
 188
 189         /* BCM5709S controllers and OEM boards. */
 190         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x171d,
 191                 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
 192         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x7056,
 193                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 194         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  PCI_ANY_ID,  PCI_ANY_ID,
 195                 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
 196
 197         /* BCM5716 controllers and OEM boards. */
 198         { BRCM_VENDORID, BRCM_DEVICEID_BCM5716,   PCI_ANY_ID,  PCI_ANY_ID,
 199                 "Broadcom NetXtreme II BCM5716 1000Base-T" },
 200
 201         { 0, 0, 0, 0, NULL }
 202 };
 203
 204
 205 /****************************************************************************/
 206 /* Supported Flash NVRAM device data.                                       */
 207 /****************************************************************************/
 208 static const struct flash_spec flash_table[] =
 209 {
 210 #define BUFFERED_FLAGS          (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
 211 #define NONBUFFERED_FLAGS       (BCE_NV_WREN)
 212
 213         /* Slow EEPROM */
 214         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 215          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 216          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 217          "EEPROM - slow"},
 218         /* Expansion entry 0001 */
 219         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 220          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 221          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 222          "Entry 0001"},
 223         /* Saifun SA25F010 (non-buffered flash) */
 224         /* strap, cfg1, & write1 need updates */
 225         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 226          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 227          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 228          "Non-buffered flash (128kB)"},
 229         /* Saifun SA25F020 (non-buffered flash) */
 230         /* strap, cfg1, & write1 need updates */
 231         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 232          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 233          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 234          "Non-buffered flash (256kB)"},
 235         /* Expansion entry 0100 */
 236         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 237          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 238          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 239          "Entry 0100"},
 240         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 241         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 242          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 243          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 244          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 245         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 246         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 247          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 248          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 249          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 250         /* Saifun SA25F005 (non-buffered flash) */
 251         /* strap, cfg1, & write1 need updates */
 252         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 253          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 254          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 255          "Non-buffered flash (64kB)"},
 256         /* Fast EEPROM */
 257         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 258          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 259          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 260          "EEPROM - fast"},
 261         /* Expansion entry 1001 */
 262         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 263          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 264          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 265          "Entry 1001"},
 266         /* Expansion entry 1010 */
 267         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 268          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 269          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 270          "Entry 1010"},
 271         /* ATMEL AT45DB011B (buffered flash) */
 272         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 273          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 274          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 275          "Buffered flash (128kB)"},
 276         /* Expansion entry 1100 */
 277         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 278          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 279          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 280          "Entry 1100"},
 281         /* Expansion entry 1101 */
 282         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 283          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 284          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 285          "Entry 1101"},
 286         /* Ateml Expansion entry 1110 */
 287         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 288          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 289          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 290          "Entry 1110 (Atmel)"},
 291         /* ATMEL AT45DB021B (buffered flash) */
 292         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 293          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 294          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 295          "Buffered flash (256kB)"},
 296 };
 297
 298 /*
 299  * The BCM5709 controllers transparently handle the
 300  * differences between Atmel 264 byte pages and all
 301  * flash devices which use 256 byte pages, so no
 302  * logical-to-physical mapping is required in the
 303  * driver.
 304  */
 305 static struct flash_spec flash_5709 = {
 306         .flags          = BCE_NV_BUFFERED,
 307         .page_bits      = BCM5709_FLASH_PAGE_BITS,
 308         .page_size      = BCM5709_FLASH_PAGE_SIZE,
 309         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
 310         .total_size     = BUFFERED_FLASH_TOTAL_SIZE * 2,
 311         .name           = "5709/5716 buffered flash (256kB)",
 312 };
 313
 314
 315 /****************************************************************************/
 316 /* DragonFly device entry points.                                           */
 317 /****************************************************************************/
 318 static int      bce_probe(device_t);
 319 static int      bce_attach(device_t);
 320 static int      bce_detach(device_t);
 321 static void     bce_shutdown(device_t);
 322
 323 /****************************************************************************/
 324 /* BCE Debug Data Structure Dump Routines                                   */
 325 /****************************************************************************/
 326 #ifdef BCE_DEBUG
 327 static void     bce_dump_mbuf(struct bce_softc *, struct mbuf *);
 328 static void     bce_dump_tx_mbuf_chain(struct bce_softc *, int, int);
 329 static void     bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
 330 static void     bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
 331 static void     bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
 332 static void     bce_dump_l2fhdr(struct bce_softc *, int,
 333                                 struct l2_fhdr *) __unused;
 334 static void     bce_dump_tx_chain(struct bce_softc *, int, int);
 335 static void     bce_dump_rx_chain(struct bce_softc *, int, int);
 336 static void     bce_dump_status_block(struct bce_softc *);
 337 static void     bce_dump_driver_state(struct bce_softc *);
 338 static void     bce_dump_stats_block(struct bce_softc *) __unused;
 339 static void     bce_dump_hw_state(struct bce_softc *);
 340 static void     bce_dump_txp_state(struct bce_softc *);
 341 static void     bce_dump_rxp_state(struct bce_softc *) __unused;
 342 static void     bce_dump_tpat_state(struct bce_softc *) __unused;
 343 static void     bce_freeze_controller(struct bce_softc *) __unused;
 344 static void     bce_unfreeze_controller(struct bce_softc *) __unused;
 345 static void     bce_breakpoint(struct bce_softc *);
 346 #endif  /* BCE_DEBUG */
 347
 348
 349 /****************************************************************************/
 350 /* BCE Register/Memory Access Routines                                      */
 351 /****************************************************************************/
 352 static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
 353 static void     bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
 354 static void     bce_shmem_wr(struct bce_softc *, uint32_t, uint32_t);
 355 static uint32_t bce_shmem_rd(struct bce_softc *, u32);
 356 static void     bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
 357 static int      bce_miibus_read_reg(device_t, int, int);
 358 static int      bce_miibus_write_reg(device_t, int, int, int);
 359 static void     bce_miibus_statchg(device_t);
 360
 361
 362 /****************************************************************************/
 363 /* BCE NVRAM Access Routines                                                */
 364 /****************************************************************************/
 365 static int      bce_acquire_nvram_lock(struct bce_softc *);
 366 static int      bce_release_nvram_lock(struct bce_softc *);
 367 static void     bce_enable_nvram_access(struct bce_softc *);
 368 static void     bce_disable_nvram_access(struct bce_softc *);
 369 static int      bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
 370                                      uint32_t);
 371 static int      bce_init_nvram(struct bce_softc *);
 372 static int      bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
 373 static int      bce_nvram_test(struct bce_softc *);
 374
 375 /****************************************************************************/
 376 /* BCE DMA Allocate/Free Routines                                           */
 377 /****************************************************************************/
 378 static int      bce_dma_alloc(struct bce_softc *);
 379 static void     bce_dma_free(struct bce_softc *);
 380 static void     bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 381
 382 /****************************************************************************/
 383 /* BCE Firmware Synchronization and Load                                    */
 384 /****************************************************************************/
 385 static int      bce_fw_sync(struct bce_softc *, uint32_t);
 386 static void     bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
 387                                  uint32_t, uint32_t);
 388 static void     bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
 389                                 struct fw_info *);
 390 static void     bce_init_rxp_cpu(struct bce_softc *);
 391 static void     bce_init_txp_cpu(struct bce_softc *);
 392 static void     bce_init_tpat_cpu(struct bce_softc *);
 393 static void     bce_init_cp_cpu(struct bce_softc *);
 394 static void     bce_init_com_cpu(struct bce_softc *);
 395 static void     bce_init_cpus(struct bce_softc *);
 396
 397 static void     bce_stop(struct bce_softc *);
 398 static int      bce_reset(struct bce_softc *, uint32_t);
 399 static int      bce_chipinit(struct bce_softc *);
 400 static int      bce_blockinit(struct bce_softc *);
 401 static int      bce_newbuf_std(struct bce_softc *, uint16_t *, uint16_t *,
 402                                uint32_t *, int);
 403 static void     bce_setup_rxdesc_std(struct bce_softc *, uint16_t, uint32_t *);
 404 static void     bce_probe_pci_caps(struct bce_softc *);
 405 static void     bce_print_adapter_info(struct bce_softc *);
 406 static void     bce_get_media(struct bce_softc *);
 407
 408 static void     bce_init_tx_context(struct bce_softc *);
 409 static int      bce_init_tx_chain(struct bce_softc *);
 410 static void     bce_init_rx_context(struct bce_softc *);
 411 static int      bce_init_rx_chain(struct bce_softc *);
 412 static void     bce_free_rx_chain(struct bce_softc *);
 413 static void     bce_free_tx_chain(struct bce_softc *);
 414
 415 static int      bce_encap(struct bce_softc *, struct mbuf **);
 416 static void     bce_start(struct ifnet *);
 417 static int      bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 418 static void     bce_watchdog(struct ifnet *);
 419 static int      bce_ifmedia_upd(struct ifnet *);
 420 static void     bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 421 static void     bce_init(void *);
 422 static void     bce_mgmt_init(struct bce_softc *);
 423
 424 static void     bce_init_ctx(struct bce_softc *);
 425 static void     bce_get_mac_addr(struct bce_softc *);
 426 static void     bce_set_mac_addr(struct bce_softc *);
 427 static void     bce_phy_intr(struct bce_softc *);
 428 static void     bce_rx_intr(struct bce_softc *, int);
 429 static void     bce_tx_intr(struct bce_softc *);
 430 static void     bce_disable_intr(struct bce_softc *);
 431 static void     bce_enable_intr(struct bce_softc *, int);
 432
 433 #ifdef DEVICE_POLLING
 434 static void     bce_poll(struct ifnet *, enum poll_cmd, int);
 435 #endif
 436 static void     bce_intr(void *);
 437 static void     bce_set_rx_mode(struct bce_softc *);
 438 static void     bce_stats_update(struct bce_softc *);
 439 static void     bce_tick(void *);
 440 static void     bce_tick_serialized(struct bce_softc *);
 441 static void     bce_pulse(void *);
 442 static void     bce_add_sysctls(struct bce_softc *);
 443
 444 static void     bce_coal_change(struct bce_softc *);
 445 static int      bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
 446 static int      bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
 447 static int      bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
 448 static int      bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
 449 static int      bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
 450 static int      bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
 451 static int      bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
 452 static int      bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
 453 static int      bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
 454                                        uint32_t *, uint32_t);
 455
 456 /*
 457  * NOTE:
 458  * Don't set bce_tx_ticks_int/bce_tx_ticks to 1023.  Linux's bnx2
 459  * takes 1023 as the TX ticks limit.  However, using 1023 will
 460  * cause 5708(B2) to generate extra interrupts (~2000/s) even when
 461  * there is _no_ network activity on the NIC.
 462  */
 463 static uint32_t bce_tx_bds_int = 255;           /* bcm: 20 */
 464 static uint32_t bce_tx_bds = 255;               /* bcm: 20 */
 465 static uint32_t bce_tx_ticks_int = 1022;        /* bcm: 80 */
 466 static uint32_t bce_tx_ticks = 1022;            /* bcm: 80 */
 467 static uint32_t bce_rx_bds_int = 128;           /* bcm: 6 */
 468 static uint32_t bce_rx_bds = 128;               /* bcm: 6 */
 469 static uint32_t bce_rx_ticks_int = 125;         /* bcm: 18 */
 470 static uint32_t bce_rx_ticks = 125;             /* bcm: 18 */
 471
 472 TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
 473 TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
 474 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
 475 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
 476 TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
 477 TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
 478 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
 479 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
 480
 481 /****************************************************************************/
 482 /* DragonFly device dispatch table.                                         */
 483 /****************************************************************************/
 484 static device_method_t bce_methods[] = {
 485         /* Device interface */
 486         DEVMETHOD(device_probe,         bce_probe),
 487         DEVMETHOD(device_attach,        bce_attach),
 488         DEVMETHOD(device_detach,        bce_detach),
 489         DEVMETHOD(device_shutdown,      bce_shutdown),
 490
 491         /* bus interface */
 492         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 493         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 494
 495         /* MII interface */
 496         DEVMETHOD(miibus_readreg,       bce_miibus_read_reg),
 497         DEVMETHOD(miibus_writereg,      bce_miibus_write_reg),
 498         DEVMETHOD(miibus_statchg,       bce_miibus_statchg),
 499
 500         { 0, 0 }
 501 };
 502
 503 static driver_t bce_driver = {
 504         "bce",
 505         bce_methods,
 506         sizeof(struct bce_softc)
 507 };
 508
 509 static devclass_t bce_devclass;
 510
 511
 512 DECLARE_DUMMY_MODULE(if_bce);
 513 MODULE_DEPEND(bce, miibus, 1, 1, 1);
 514 DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, NULL, NULL);
 515 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
 516
 517
 518 /****************************************************************************/
 519 /* Device probe function.                                                   */
 520 /*                                                                          */
 521 /* Compares the device to the driver's list of supported devices and        */
 522 /* reports back to the OS whether this is the right driver for the device.  */
 523 /*                                                                          */
 524 /* Returns:                                                                 */
 525 /*   BUS_PROBE_DEFAULT on success, positive value on failure.               */
 526 /****************************************************************************/
 527 static int
 528 bce_probe(device_t dev)
 529 {
 530         struct bce_type *t;
 531         uint16_t vid, did, svid, sdid;
 532
 533         /* Get the data for the device to be probed. */
 534         vid  = pci_get_vendor(dev);
 535         did  = pci_get_device(dev);
 536         svid = pci_get_subvendor(dev);
 537         sdid = pci_get_subdevice(dev);
 538
 539         /* Look through the list of known devices for a match. */
 540         for (t = bce_devs; t->bce_name != NULL; ++t) {
 541                 if (vid == t->bce_vid && did == t->bce_did &&
 542                     (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
 543                     (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
 544                         uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
 545                         char *descbuf;
 546
 547                         descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
 548
 549                         /* Print out the device identity. */
 550                         ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
 551                                   t->bce_name,
 552                                   ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
 553
 554                         device_set_desc_copy(dev, descbuf);
 555                         kfree(descbuf, M_TEMP);
 556                         return 0;
 557                 }
 558         }
 559         return ENXIO;
 560 }
 561
 562
 563 /****************************************************************************/
 564 /* PCI Capabilities Probe Function.                                         */
 565 /*                                                                          */
 566 /* Walks the PCI capabiites list for the device to find what features are   */
 567 /* supported.                                                               */
 568 /*                                                                          */
 569 /* Returns:                                                                 */
 570 /*   None.                                                                  */
 571 /****************************************************************************/
 572 static void
 573 bce_print_adapter_info(struct bce_softc *sc)
 574 {
 575         device_printf(sc->bce_dev, "ASIC (0x%08X); ", sc->bce_chipid);
 576
 577         kprintf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
 578                 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
 579
 580         /* Bus info. */
 581         if (sc->bce_flags & BCE_PCIE_FLAG) {
 582                 kprintf("Bus (PCIe x%d, ", sc->link_width);
 583                 switch (sc->link_speed) {
 584                 case 1:
 585                         kprintf("2.5Gbps); ");
 586                         break;
 587                 case 2:
 588                         kprintf("5Gbps); ");
 589                         break;
 590                 default:
 591                         kprintf("Unknown link speed); ");
 592                         break;
 593                 }
 594         } else {
 595                 kprintf("Bus (PCI%s, %s, %dMHz); ",
 596                     ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
 597                     ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
 598                     sc->bus_speed_mhz);
 599         }
 600
 601         /* Firmware version and device features. */
 602         kprintf("B/C (%s)", sc->bce_bc_ver);
 603
 604         if ((sc->bce_flags & BCE_MFW_ENABLE_FLAG) ||
 605             (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
 606                 kprintf("; Flags(");
 607                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
 608                         kprintf("MFW[%s]", sc->bce_mfw_ver);
 609                 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
 610                         kprintf(" 2.5G");
 611                 kprintf(")");
 612         }
 613         kprintf("\n");
 614 }
 615
 616
 617 /****************************************************************************/
 618 /* PCI Capabilities Probe Function.                                         */
 619 /*                                                                          */
 620 /* Walks the PCI capabiites list for the device to find what features are   */
 621 /* supported.                                                               */
 622 /*                                                                          */
 623 /* Returns:                                                                 */
 624 /*   None.                                                                  */
 625 /****************************************************************************/
 626 static void
 627 bce_probe_pci_caps(struct bce_softc *sc)
 628 {
 629         device_t dev = sc->bce_dev;
 630         uint8_t ptr;
 631
 632         if (pci_is_pcix(dev))
 633                 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
 634
 635         ptr = pci_get_pciecap_ptr(dev);
 636         if (ptr) {
 637                 uint16_t link_status = pci_read_config(dev, ptr + 0x12, 2);
 638
 639                 sc->link_speed = link_status & 0xf;
 640                 sc->link_width = (link_status >> 4) & 0x3f;
 641                 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
 642                 sc->bce_flags |= BCE_PCIE_FLAG;
 643         }
 644 }
 645
 646
 647 /****************************************************************************/
 648 /* Device attach function.                                                  */
 649 /*                                                                          */
 650 /* Allocates device resources, performs secondary chip identification,      */
 651 /* resets and initializes the hardware, and initializes driver instance     */
 652 /* variables.                                                               */
 653 /*                                                                          */
 654 /* Returns:                                                                 */
 655 /*   0 on success, positive value on failure.                               */
 656 /****************************************************************************/
 657 static int
 658 bce_attach(device_t dev)
 659 {
 660         struct bce_softc *sc = device_get_softc(dev);
 661         struct ifnet *ifp = &sc->arpcom.ac_if;
 662         uint32_t val;
 663         int rid, rc = 0;
 664         int i, j;
 665 #ifdef notyet
 666         int count;
 667 #endif
 668
 669         sc->bce_dev = dev;
 670         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 671
 672         pci_enable_busmaster(dev);
 673
 674         bce_probe_pci_caps(sc);
 675
 676         /* Allocate PCI memory resources. */
 677         rid = PCIR_BAR(0);
 678         sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 679                                                  RF_ACTIVE | PCI_RF_DENSE);
 680         if (sc->bce_res_mem == NULL) {
 681                 device_printf(dev, "PCI memory allocation failed\n");
 682                 return ENXIO;
 683         }
 684         sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
 685         sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
 686
 687         /* Allocate PCI IRQ resources. */
 688 #ifdef notyet
 689         count = pci_msi_count(dev);
 690         if (count == 1 && pci_alloc_msi(dev, &count) == 0) {
 691                 rid = 1;
 692                 sc->bce_flags |= BCE_USING_MSI_FLAG;
 693         } else
 694 #endif
 695         rid = 0;
 696         sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 697                                                  RF_SHAREABLE | RF_ACTIVE);
 698         if (sc->bce_res_irq == NULL) {
 699                 device_printf(dev, "PCI map interrupt failed\n");
 700                 rc = ENXIO;
 701                 goto fail;
 702         }
 703
 704         /*
 705          * Configure byte swap and enable indirect register access.
 706          * Rely on CPU to do target byte swapping on big endian systems.
 707          * Access to registers outside of PCI configurtion space are not
 708          * valid until this is done.
 709          */
 710         pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
 711                          BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
 712                          BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
 713
 714         /* Save ASIC revsion info. */
 715         sc->bce_chipid =  REG_RD(sc, BCE_MISC_ID);
 716
 717         /* Weed out any non-production controller revisions. */
 718         switch (BCE_CHIP_ID(sc)) {
 719         case BCE_CHIP_ID_5706_A0:
 720         case BCE_CHIP_ID_5706_A1:
 721         case BCE_CHIP_ID_5708_A0:
 722         case BCE_CHIP_ID_5708_B0:
 723         case BCE_CHIP_ID_5709_A0:
 724         case BCE_CHIP_ID_5709_B0:
 725         case BCE_CHIP_ID_5709_B1:
 726 #ifdef foo
 727         /* 5709C B2 seems to work fine */
 728         case BCE_CHIP_ID_5709_B2:
 729 #endif
 730                 device_printf(dev, "Unsupported chip id 0x%08x!\n",
 731                               BCE_CHIP_ID(sc));
 732                 rc = ENODEV;
 733                 goto fail;
 734         }
 735
 736         /*
 737          * Find the base address for shared memory access.
 738          * Newer versions of bootcode use a signature and offset
 739          * while older versions use a fixed address.
 740          */
 741         val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
 742         if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) ==
 743             BCE_SHM_HDR_SIGNATURE_SIG) {
 744                 /* Multi-port devices use different offsets in shared memory. */
 745                 sc->bce_shmem_base = REG_RD_IND(sc,
 746                     BCE_SHM_HDR_ADDR_0 + (pci_get_function(sc->bce_dev) << 2));
 747         } else {
 748                 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
 749         }
 750         DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
 751
 752         /* Fetch the bootcode revision. */
 753         val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
 754         for (i = 0, j = 0; i < 3; i++) {
 755                 uint8_t num;
 756                 int k, skip0;
 757
 758                 num = (uint8_t)(val >> (24 - (i * 8)));
 759                 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
 760                         if (num >= k || !skip0 || k == 1) {
 761                                 sc->bce_bc_ver[j++] = (num / k) + '0';
 762                                 skip0 = 0;
 763                         }
 764                 }
 765                 if (i != 2)
 766                         sc->bce_bc_ver[j++] = '.';
 767         }
 768
 769         /* Check if any management firwmare is running. */
 770         val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
 771         if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
 772                 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
 773
 774                 /* Allow time for firmware to enter the running state. */
 775                 for (i = 0; i < 30; i++) {
 776                         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
 777                         if (val & BCE_CONDITION_MFW_RUN_MASK)
 778                                 break;
 779                         DELAY(10000);
 780                 }
 781         }
 782
 783         /* Check the current bootcode state. */
 784         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION) &
 785             BCE_CONDITION_MFW_RUN_MASK;
 786         if (val != BCE_CONDITION_MFW_RUN_UNKNOWN &&
 787             val != BCE_CONDITION_MFW_RUN_NONE) {
 788                 uint32_t addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
 789
 790                 for (i = 0, j = 0; j < 3; j++) {
 791                         val = bce_reg_rd_ind(sc, addr + j * 4);
 792                         val = bswap32(val);
 793                         memcpy(&sc->bce_mfw_ver[i], &val, 4);
 794                         i += 4;
 795                 }
 796         }
 797
 798         /* Get PCI bus information (speed and type). */
 799         val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
 800         if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
 801                 uint32_t clkreg;
 802
 803                 sc->bce_flags |= BCE_PCIX_FLAG;
 804
 805                 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
 806                          BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
 807                 switch (clkreg) {
 808                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
 809                         sc->bus_speed_mhz = 133;
 810                         break;
 811
 812                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
 813                         sc->bus_speed_mhz = 100;
 814                         break;
 815
 816                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
 817                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
 818                         sc->bus_speed_mhz = 66;
 819                         break;
 820
 821                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
 822                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
 823                         sc->bus_speed_mhz = 50;
 824                         break;
 825
 826                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
 827                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
 828                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
 829                         sc->bus_speed_mhz = 33;
 830                         break;
 831                 }
 832         } else {
 833                 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
 834                         sc->bus_speed_mhz = 66;
 835                 else
 836                         sc->bus_speed_mhz = 33;
 837         }
 838
 839         if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
 840                 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
 841
 842         /* Reset the controller. */
 843         rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
 844         if (rc != 0)
 845                 goto fail;
 846
 847         /* Initialize the controller. */
 848         rc = bce_chipinit(sc);
 849         if (rc != 0) {
 850                 device_printf(dev, "Controller initialization failed!\n");
 851                 goto fail;
 852         }
 853
 854         /* Perform NVRAM test. */
 855         rc = bce_nvram_test(sc);
 856         if (rc != 0) {
 857                 device_printf(dev, "NVRAM test failed!\n");
 858                 goto fail;
 859         }
 860
 861         /* Fetch the permanent Ethernet MAC address. */
 862         bce_get_mac_addr(sc);
 863
 864         /*
 865          * Trip points control how many BDs
 866          * should be ready before generating an
 867          * interrupt while ticks control how long
 868          * a BD can sit in the chain before
 869          * generating an interrupt.  Set the default
 870          * values for the RX and TX rings.
 871          */
 872
 873 #ifdef BCE_DRBUG
 874         /* Force more frequent interrupts. */
 875         sc->bce_tx_quick_cons_trip_int = 1;
 876         sc->bce_tx_quick_cons_trip     = 1;
 877         sc->bce_tx_ticks_int           = 0;
 878         sc->bce_tx_ticks               = 0;
 879
 880         sc->bce_rx_quick_cons_trip_int = 1;
 881         sc->bce_rx_quick_cons_trip     = 1;
 882         sc->bce_rx_ticks_int           = 0;
 883         sc->bce_rx_ticks               = 0;
 884 #else
 885         sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
 886         sc->bce_tx_quick_cons_trip     = bce_tx_bds;
 887         sc->bce_tx_ticks_int           = bce_tx_ticks_int;
 888         sc->bce_tx_ticks               = bce_tx_ticks;
 889
 890         sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
 891         sc->bce_rx_quick_cons_trip     = bce_rx_bds;
 892         sc->bce_rx_ticks_int           = bce_rx_ticks_int;
 893         sc->bce_rx_ticks               = bce_rx_ticks;
 894 #endif
 895
 896         /* Update statistics once every second. */
 897         sc->bce_stats_ticks = 1000000 & 0xffff00;
 898
 899         /* Find the media type for the adapter. */
 900         bce_get_media(sc);
 901
 902         /* Allocate DMA memory resources. */
 903         rc = bce_dma_alloc(sc);
 904         if (rc != 0) {
 905                 device_printf(dev, "DMA resource allocation failed!\n");
 906                 goto fail;
 907         }
 908
 909         /* Initialize the ifnet interface. */
 910         ifp->if_softc = sc;
 911         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 912         ifp->if_ioctl = bce_ioctl;
 913         ifp->if_start = bce_start;
 914         ifp->if_init = bce_init;
 915         ifp->if_watchdog = bce_watchdog;
 916 #ifdef DEVICE_POLLING
 917         ifp->if_poll = bce_poll;
 918 #endif
 919         ifp->if_mtu = ETHERMTU;
 920         ifp->if_hwassist = BCE_IF_HWASSIST;
 921         ifp->if_capabilities = BCE_IF_CAPABILITIES;
 922         ifp->if_capenable = ifp->if_capabilities;
 923         ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD);
 924         ifq_set_ready(&ifp->if_snd);
 925
 926         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
 927                 ifp->if_baudrate = IF_Gbps(2.5);
 928         else
 929                 ifp->if_baudrate = IF_Gbps(1);
 930
 931         /* Assume a standard 1500 byte MTU size for mbuf allocations. */
 932         sc->mbuf_alloc_size  = MCLBYTES;
 933
 934         /* Look for our PHY. */
 935         rc = mii_phy_probe(dev, &sc->bce_miibus,
 936                            bce_ifmedia_upd, bce_ifmedia_sts);
 937         if (rc != 0) {
 938                 device_printf(dev, "PHY probe failed!\n");
 939                 goto fail;
 940         }
 941
 942         /* Attach to the Ethernet interface list. */
 943         ether_ifattach(ifp, sc->eaddr, NULL);
 944
 945         callout_init(&sc->bce_tick_callout);
 946         callout_init(&sc->bce_pulse_callout);
 947
 948         /* Hookup IRQ last. */
 949         rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_MPSAFE, bce_intr, sc,
 950                             &sc->bce_intrhand, ifp->if_serializer);
 951         if (rc != 0) {
 952                 device_printf(dev, "Failed to setup IRQ!\n");
 953                 ether_ifdetach(ifp);
 954                 goto fail;
 955         }
 956
 957         ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bce_res_irq));
 958         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
 959
 960         /* Print some important debugging info. */
 961         DBRUN(BCE_INFO, bce_dump_driver_state(sc));
 962
 963         /* Add the supported sysctls to the kernel. */
 964         bce_add_sysctls(sc);
 965
 966         /*
 967          * The chip reset earlier notified the bootcode that
 968          * a driver is present.  We now need to start our pulse
 969          * routine so that the bootcode is reminded that we're
 970          * still running.
 971          */
 972         bce_pulse(sc);
 973
 974         /* Get the firmware running so IPMI still works */
 975         bce_mgmt_init(sc);
 976
 977         bce_print_adapter_info(sc);
 978
 979         return 0;
 980 fail:
 981         bce_detach(dev);
 982         return(rc);
 983 }
 984
 985
 986 /****************************************************************************/
 987 /* Device detach function.                                                  */
 988 /*                                                                          */
 989 /* Stops the controller, resets the controller, and releases resources.     */
 990 /*                                                                          */
 991 /* Returns:                                                                 */
 992 /*   0 on success, positive value on failure.                               */
 993 /****************************************************************************/
 994 static int
 995 bce_detach(device_t dev)
 996 {
 997         struct bce_softc *sc = device_get_softc(dev);
 998
 999         if (device_is_attached(dev)) {
1000                 struct ifnet *ifp = &sc->arpcom.ac_if;
1001                 uint32_t msg;
1002
1003                 /* Stop and reset the controller. */
1004                 lwkt_serialize_enter(ifp->if_serializer);
1005                 callout_stop(&sc->bce_pulse_callout);
1006                 bce_stop(sc);
1007                 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1008                         msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1009                 else
1010                         msg = BCE_DRV_MSG_CODE_UNLOAD;
1011                 bce_reset(sc, msg);
1012                 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
1013                 lwkt_serialize_exit(ifp->if_serializer);
1014
1015                 ether_ifdetach(ifp);
1016         }
1017
1018         /* If we have a child device on the MII bus remove it too. */
1019         if (sc->bce_miibus)
1020                 device_delete_child(dev, sc->bce_miibus);
1021         bus_generic_detach(dev);
1022
1023         if (sc->bce_res_irq != NULL) {
1024                 bus_release_resource(dev, SYS_RES_IRQ,
1025                         sc->bce_flags & BCE_USING_MSI_FLAG ? 1 : 0,
1026                         sc->bce_res_irq);
1027         }
1028
1029 #ifdef notyet
1030         if (sc->bce_flags & BCE_USING_MSI_FLAG)
1031                 pci_release_msi(dev);
1032 #endif
1033
1034         if (sc->bce_res_mem != NULL) {
1035                 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
1036                                      sc->bce_res_mem);
1037         }
1038
1039         bce_dma_free(sc);
1040
1041         if (sc->bce_sysctl_tree != NULL)
1042                 sysctl_ctx_free(&sc->bce_sysctl_ctx);
1043
1044         return 0;
1045 }
1046
1047
1048 /****************************************************************************/
1049 /* Device shutdown function.                                                */
1050 /*                                                                          */
1051 /* Stops and resets the controller.                                         */
1052 /*                                                                          */
1053 /* Returns:                                                                 */
1054 /*   Nothing                                                                */
1055 /****************************************************************************/
1056 static void
1057 bce_shutdown(device_t dev)
1058 {
1059         struct bce_softc *sc = device_get_softc(dev);
1060         struct ifnet *ifp = &sc->arpcom.ac_if;
1061         uint32_t msg;
1062
1063         lwkt_serialize_enter(ifp->if_serializer);
1064         bce_stop(sc);
1065         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1066                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1067         else
1068                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1069         bce_reset(sc, msg);
1070         lwkt_serialize_exit(ifp->if_serializer);
1071 }
1072
1073
1074 /****************************************************************************/
1075 /* Indirect register read.                                                  */
1076 /*                                                                          */
1077 /* Reads NetXtreme II registers using an index/data register pair in PCI    */
1078 /* configuration space.  Using this mechanism avoids issues with posted     */
1079 /* reads but is much slower than memory-mapped I/O.                         */
1080 /*                                                                          */
1081 /* Returns:                                                                 */
1082 /*   The value of the register.                                             */
1083 /****************************************************************************/
1084 static uint32_t
1085 bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
1086 {
1087         device_t dev = sc->bce_dev;
1088
1089         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1090 #ifdef BCE_DEBUG
1091         {
1092                 uint32_t val;
1093                 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1094                 DBPRINT(sc, BCE_EXCESSIVE,
1095                         "%s(); offset = 0x%08X, val = 0x%08X\n",
1096                         __func__, offset, val);
1097                 return val;
1098         }
1099 #else
1100         return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1101 #endif
1102 }
1103
1104
1105 /****************************************************************************/
1106 /* Indirect register write.                                                 */
1107 /*                                                                          */
1108 /* Writes NetXtreme II registers using an index/data register pair in PCI   */
1109 /* configuration space.  Using this mechanism avoids issues with posted     */
1110 /* writes but is muchh slower than memory-mapped I/O.                       */
1111 /*                                                                          */
1112 /* Returns:                                                                 */
1113 /*   Nothing.                                                               */
1114 /****************************************************************************/
1115 static void
1116 bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
1117 {
1118         device_t dev = sc->bce_dev;
1119
1120         DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
1121                 __func__, offset, val);
1122
1123         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1124         pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1125 }
1126
1127
1128 /****************************************************************************/
1129 /* Shared memory write.                                                     */
1130 /*                                                                          */
1131 /* Writes NetXtreme II shared memory region.                                */
1132 /*                                                                          */
1133 /* Returns:                                                                 */
1134 /*   Nothing.                                                               */
1135 /****************************************************************************/
1136 static void
1137 bce_shmem_wr(struct bce_softc *sc, uint32_t offset, uint32_t val)
1138 {
1139         bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1140 }
1141
1142
1143 /****************************************************************************/
1144 /* Shared memory read.                                                      */
1145 /*                                                                          */
1146 /* Reads NetXtreme II shared memory region.                                 */
1147 /*                                                                          */
1148 /* Returns:                                                                 */
1149 /*   The 32 bit value read.                                                 */
1150 /****************************************************************************/
1151 static u32
1152 bce_shmem_rd(struct bce_softc *sc, uint32_t offset)
1153 {
1154         return bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1155 }
1156
1157
1158 /****************************************************************************/
1159 /* Context memory write.                                                    */
1160 /*                                                                          */
1161 /* The NetXtreme II controller uses context memory to track connection      */
1162 /* information for L2 and higher network protocols.                         */
1163 /*                                                                          */
1164 /* Returns:                                                                 */
1165 /*   Nothing.                                                               */
1166 /****************************************************************************/
1167 static void
1168 bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t ctx_offset,
1169     uint32_t ctx_val)
1170 {
1171         uint32_t idx, offset = ctx_offset + cid_addr;
1172         uint32_t val, retry_cnt = 5;
1173
1174         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1175             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1176                 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1177                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1178
1179                 for (idx = 0; idx < retry_cnt; idx++) {
1180                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1181                         if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1182                                 break;
1183                         DELAY(5);
1184                 }
1185
1186                 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) {
1187                         device_printf(sc->bce_dev,
1188                             "Unable to write CTX memory: "
1189                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1190                             cid_addr, ctx_offset);
1191                 }
1192         } else {
1193                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1194                 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1195         }
1196 }
1197
1198
1199 /****************************************************************************/
1200 /* PHY register read.                                                       */
1201 /*                                                                          */
1202 /* Implements register reads on the MII bus.                                */
1203 /*                                                                          */
1204 /* Returns:                                                                 */
1205 /*   The value of the register.                                             */
1206 /****************************************************************************/
1207 static int
1208 bce_miibus_read_reg(device_t dev, int phy, int reg)
1209 {
1210         struct bce_softc *sc = device_get_softc(dev);
1211         uint32_t val;
1212         int i;
1213
1214         /* Make sure we are accessing the correct PHY address. */
1215         if (phy != sc->bce_phy_addr) {
1216                 DBPRINT(sc, BCE_VERBOSE,
1217                         "Invalid PHY address %d for PHY read!\n", phy);
1218                 return 0;
1219         }
1220
1221         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1222                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1223                 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1224
1225                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1226                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1227
1228                 DELAY(40);
1229         }
1230
1231         val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1232               BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1233               BCE_EMAC_MDIO_COMM_START_BUSY;
1234         REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1235
1236         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1237                 DELAY(10);
1238
1239                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1240                 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1241                         DELAY(5);
1242
1243                         val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1244                         val &= BCE_EMAC_MDIO_COMM_DATA;
1245                         break;
1246                 }
1247         }
1248
1249         if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1250                 if_printf(&sc->arpcom.ac_if,
1251                           "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1252                           phy, reg);
1253                 val = 0x0;
1254         } else {
1255                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1256         }
1257
1258         DBPRINT(sc, BCE_EXCESSIVE,
1259                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1260                 __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff);
1261
1262         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1263                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1264                 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1265
1266                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1267                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1268
1269                 DELAY(40);
1270         }
1271         return (val & 0xffff);
1272 }
1273
1274
1275 /****************************************************************************/
1276 /* PHY register write.                                                      */
1277 /*                                                                          */
1278 /* Implements register writes on the MII bus.                               */
1279 /*                                                                          */
1280 /* Returns:                                                                 */
1281 /*   The value of the register.                                             */
1282 /****************************************************************************/
1283 static int
1284 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1285 {
1286         struct bce_softc *sc = device_get_softc(dev);
1287         uint32_t val1;
1288         int i;
1289
1290         /* Make sure we are accessing the correct PHY address. */
1291         if (phy != sc->bce_phy_addr) {
1292                 DBPRINT(sc, BCE_WARN,
1293                         "Invalid PHY address %d for PHY write!\n", phy);
1294                 return(0);
1295         }
1296
1297         DBPRINT(sc, BCE_EXCESSIVE,
1298                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1299                 __func__, phy, (uint16_t)(reg & 0xffff),
1300                 (uint16_t)(val & 0xffff));
1301
1302         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1303                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1304                 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1305
1306                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1307                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1308
1309                 DELAY(40);
1310         }
1311
1312         val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1313                 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1314                 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1315         REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1316
1317         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1318                 DELAY(10);
1319
1320                 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1321                 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1322                         DELAY(5);
1323                         break;
1324                 }
1325         }
1326
1327         if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1328                 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1329
1330         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1331                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1332                 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1333
1334                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1335                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1336
1337                 DELAY(40);
1338         }
1339         return 0;
1340 }
1341
1342
1343 /****************************************************************************/
1344 /* MII bus status change.                                                   */
1345 /*                                                                          */
1346 /* Called by the MII bus driver when the PHY establishes link to set the    */
1347 /* MAC interface registers.                                                 */
1348 /*                                                                          */
1349 /* Returns:                                                                 */
1350 /*   Nothing.                                                               */
1351 /****************************************************************************/
1352 static void
1353 bce_miibus_statchg(device_t dev)
1354 {
1355         struct bce_softc *sc = device_get_softc(dev);
1356         struct mii_data *mii = device_get_softc(sc->bce_miibus);
1357
1358         DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n",
1359                 mii->mii_media_active);
1360
1361 #ifdef BCE_DEBUG
1362         /* Decode the interface media flags. */
1363         if_printf(&sc->arpcom.ac_if, "Media: ( ");
1364         switch(IFM_TYPE(mii->mii_media_active)) {
1365         case IFM_ETHER:
1366                 kprintf("Ethernet )");
1367                 break;
1368         default:
1369                 kprintf("Unknown )");
1370                 break;
1371         }
1372
1373         kprintf(" Media Options: ( ");
1374         switch(IFM_SUBTYPE(mii->mii_media_active)) {
1375         case IFM_AUTO:
1376                 kprintf("Autoselect )");
1377                 break;
1378         case IFM_MANUAL:
1379                 kprintf("Manual )");
1380                 break;
1381         case IFM_NONE:
1382                 kprintf("None )");
1383                 break;
1384         case IFM_10_T:
1385                 kprintf("10Base-T )");
1386                 break;
1387         case IFM_100_TX:
1388                 kprintf("100Base-TX )");
1389                 break;
1390         case IFM_1000_SX:
1391                 kprintf("1000Base-SX )");
1392                 break;
1393         case IFM_1000_T:
1394                 kprintf("1000Base-T )");
1395                 break;
1396         default:
1397                 kprintf("Other )");
1398                 break;
1399         }
1400
1401         kprintf(" Global Options: (");
1402         if (mii->mii_media_active & IFM_FDX)
1403                 kprintf(" FullDuplex");
1404         if (mii->mii_media_active & IFM_HDX)
1405                 kprintf(" HalfDuplex");
1406         if (mii->mii_media_active & IFM_LOOP)
1407                 kprintf(" Loopback");
1408         if (mii->mii_media_active & IFM_FLAG0)
1409                 kprintf(" Flag0");
1410         if (mii->mii_media_active & IFM_FLAG1)
1411                 kprintf(" Flag1");
1412         if (mii->mii_media_active & IFM_FLAG2)
1413                 kprintf(" Flag2");
1414         kprintf(" )\n");
1415 #endif
1416
1417         BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1418
1419         /*
1420          * Set MII or GMII interface based on the speed negotiated
1421          * by the PHY.
1422          */
1423         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1424             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1425                 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n");
1426                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1427         } else {
1428                 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n");
1429                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1430         }
1431
1432         /*
1433          * Set half or full duplex based on the duplicity negotiated
1434          * by the PHY.
1435          */
1436         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1437                 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1438                 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1439         } else {
1440                 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1441                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1442         }
1443 }
1444
1445
1446 /****************************************************************************/
1447 /* Acquire NVRAM lock.                                                      */
1448 /*                                                                          */
1449 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock.  */
1450 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1451 /* for use by the driver.                                                   */
1452 /*                                                                          */
1453 /* Returns:                                                                 */
1454 /*   0 on success, positive value on failure.                               */
1455 /****************************************************************************/
1456 static int
1457 bce_acquire_nvram_lock(struct bce_softc *sc)
1458 {
1459         uint32_t val;
1460         int j;
1461
1462         DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n");
1463
1464         /* Request access to the flash interface. */
1465         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1466         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1467                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1468                 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1469                         break;
1470
1471                 DELAY(5);
1472         }
1473
1474         if (j >= NVRAM_TIMEOUT_COUNT) {
1475                 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1476                 return EBUSY;
1477         }
1478         return 0;
1479 }
1480
1481
1482 /****************************************************************************/
1483 /* Release NVRAM lock.                                                      */
1484 /*                                                                          */
1485 /* When the caller is finished accessing NVRAM the lock must be released.   */
1486 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1487 /* for use by the driver.                                                   */
1488 /*                                                                          */
1489 /* Returns:                                                                 */
1490 /*   0 on success, positive value on failure.                               */
1491 /****************************************************************************/
1492 static int
1493 bce_release_nvram_lock(struct bce_softc *sc)
1494 {
1495         int j;
1496         uint32_t val;
1497
1498         DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n");
1499
1500         /*
1501          * Relinquish nvram interface.
1502          */
1503         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1504
1505         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1506                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1507                 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1508                         break;
1509
1510                 DELAY(5);
1511         }
1512
1513         if (j >= NVRAM_TIMEOUT_COUNT) {
1514                 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1515                 return EBUSY;
1516         }
1517         return 0;
1518 }
1519
1520
1521 /****************************************************************************/
1522 /* Enable NVRAM access.                                                     */
1523 /*                                                                          */
1524 /* Before accessing NVRAM for read or write operations the caller must      */
1525 /* enabled NVRAM access.                                                    */
1526 /*                                                                          */
1527 /* Returns:                                                                 */
1528 /*   Nothing.                                                               */
1529 /****************************************************************************/
1530 static void
1531 bce_enable_nvram_access(struct bce_softc *sc)
1532 {
1533         uint32_t val;
1534
1535         DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n");
1536
1537         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1538         /* Enable both bits, even on read. */
1539         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1540                val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1541 }
1542
1543
1544 /****************************************************************************/
1545 /* Disable NVRAM access.                                                    */
1546 /*                                                                          */
1547 /* When the caller is finished accessing NVRAM access must be disabled.     */
1548 /*                                                                          */
1549 /* Returns:                                                                 */
1550 /*   Nothing.                                                               */
1551 /****************************************************************************/
1552 static void
1553 bce_disable_nvram_access(struct bce_softc *sc)
1554 {
1555         uint32_t val;
1556
1557         DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n");
1558
1559         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1560
1561         /* Disable both bits, even after read. */
1562         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1563                val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1564 }
1565
1566
1567 /****************************************************************************/
1568 /* Read a dword (32 bits) from NVRAM.                                       */
1569 /*                                                                          */
1570 /* Read a 32 bit word from NVRAM.  The caller is assumed to have already    */
1571 /* obtained the NVRAM lock and enabled the controller for NVRAM access.     */
1572 /*                                                                          */
1573 /* Returns:                                                                 */
1574 /*   0 on success and the 32 bit value read, positive value on failure.     */
1575 /****************************************************************************/
1576 static int
1577 bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1578                      uint32_t cmd_flags)
1579 {
1580         uint32_t cmd;
1581         int i, rc = 0;
1582
1583         /* Build the command word. */
1584         cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1585
1586         /* Calculate the offset for buffered flash. */
1587         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
1588                 offset = ((offset / sc->bce_flash_info->page_size) <<
1589                           sc->bce_flash_info->page_bits) +
1590                          (offset % sc->bce_flash_info->page_size);
1591         }
1592
1593         /*
1594          * Clear the DONE bit separately, set the address to read,
1595          * and issue the read.
1596          */
1597         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1598         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1599         REG_WR(sc, BCE_NVM_COMMAND, cmd);
1600
1601         /* Wait for completion. */
1602         for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1603                 uint32_t val;
1604
1605                 DELAY(5);
1606
1607                 val = REG_RD(sc, BCE_NVM_COMMAND);
1608                 if (val & BCE_NVM_COMMAND_DONE) {
1609                         val = REG_RD(sc, BCE_NVM_READ);
1610
1611                         val = be32toh(val);
1612                         memcpy(ret_val, &val, 4);
1613                         break;
1614                 }
1615         }
1616
1617         /* Check for errors. */
1618         if (i >= NVRAM_TIMEOUT_COUNT) {
1619                 if_printf(&sc->arpcom.ac_if,
1620                           "Timeout error reading NVRAM at offset 0x%08X!\n",
1621                           offset);
1622                 rc = EBUSY;
1623         }
1624         return rc;
1625 }
1626
1627
1628 /****************************************************************************/
1629 /* Initialize NVRAM access.                                                 */
1630 /*                                                                          */
1631 /* Identify the NVRAM device in use and prepare the NVRAM interface to      */
1632 /* access that device.                                                      */
1633 /*                                                                          */
1634 /* Returns:                                                                 */
1635 /*   0 on success, positive value on failure.                               */
1636 /****************************************************************************/
1637 static int
1638 bce_init_nvram(struct bce_softc *sc)
1639 {
1640         uint32_t val;
1641         int j, entry_count, rc = 0;
1642         const struct flash_spec *flash;
1643
1644         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
1645
1646         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1647             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1648                 sc->bce_flash_info = &flash_5709;
1649                 goto bce_init_nvram_get_flash_size;
1650         }
1651
1652         /* Determine the selected interface. */
1653         val = REG_RD(sc, BCE_NVM_CFG1);
1654
1655         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1656
1657         /*
1658          * Flash reconfiguration is required to support additional
1659          * NVRAM devices not directly supported in hardware.
1660          * Check if the flash interface was reconfigured
1661          * by the bootcode.
1662          */
1663
1664         if (val & 0x40000000) {
1665                 /* Flash interface reconfigured by bootcode. */
1666
1667                 DBPRINT(sc, BCE_INFO_LOAD,
1668                         "%s(): Flash WAS reconfigured.\n", __func__);
1669
1670                 for (j = 0, flash = flash_table; j < entry_count;
1671                      j++, flash++) {
1672                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
1673                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1674                                 sc->bce_flash_info = flash;
1675                                 break;
1676                         }
1677                 }
1678         } else {
1679                 /* Flash interface not yet reconfigured. */
1680                 uint32_t mask;
1681
1682                 DBPRINT(sc, BCE_INFO_LOAD,
1683                         "%s(): Flash was NOT reconfigured.\n", __func__);
1684
1685                 if (val & (1 << 23))
1686                         mask = FLASH_BACKUP_STRAP_MASK;
1687                 else
1688                         mask = FLASH_STRAP_MASK;
1689
1690                 /* Look for the matching NVRAM device configuration data. */
1691                 for (j = 0, flash = flash_table; j < entry_count;
1692                      j++, flash++) {
1693                         /* Check if the device matches any of the known devices. */
1694                         if ((val & mask) == (flash->strapping & mask)) {
1695                                 /* Found a device match. */
1696                                 sc->bce_flash_info = flash;
1697
1698                                 /* Request access to the flash interface. */
1699                                 rc = bce_acquire_nvram_lock(sc);
1700                                 if (rc != 0)
1701                                         return rc;
1702
1703                                 /* Reconfigure the flash interface. */
1704                                 bce_enable_nvram_access(sc);
1705                                 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1706                                 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1707                                 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1708                                 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1709                                 bce_disable_nvram_access(sc);
1710                                 bce_release_nvram_lock(sc);
1711                                 break;
1712                         }
1713                 }
1714         }
1715
1716         /* Check if a matching device was found. */
1717         if (j == entry_count) {
1718                 sc->bce_flash_info = NULL;
1719                 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
1720                 rc = ENODEV;
1721         }
1722
1723 bce_init_nvram_get_flash_size:
1724         /* Write the flash config data to the shared memory interface. */
1725         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2) &
1726             BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
1727         if (val)
1728                 sc->bce_flash_size = val;
1729         else
1730                 sc->bce_flash_size = sc->bce_flash_info->total_size;
1731
1732         DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n",
1733                 __func__, sc->bce_flash_info->total_size);
1734
1735         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
1736
1737         return rc;
1738 }
1739
1740
1741 /****************************************************************************/
1742 /* Read an arbitrary range of data from NVRAM.                              */
1743 /*                                                                          */
1744 /* Prepares the NVRAM interface for access and reads the requested data     */
1745 /* into the supplied buffer.                                                */
1746 /*                                                                          */
1747 /* Returns:                                                                 */
1748 /*   0 on success and the data read, positive value on failure.             */
1749 /****************************************************************************/
1750 static int
1751 bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1752                int buf_size)
1753 {
1754         uint32_t cmd_flags, offset32, len32, extra;
1755         int rc = 0;
1756
1757         if (buf_size == 0)
1758                 return 0;
1759
1760         /* Request access to the flash interface. */
1761         rc = bce_acquire_nvram_lock(sc);
1762         if (rc != 0)
1763                 return rc;
1764
1765         /* Enable access to flash interface */
1766         bce_enable_nvram_access(sc);
1767
1768         len32 = buf_size;
1769         offset32 = offset;
1770         extra = 0;
1771
1772         cmd_flags = 0;
1773
1774         /* XXX should we release nvram lock if read_dword() fails? */
1775         if (offset32 & 3) {
1776                 uint8_t buf[4];
1777                 uint32_t pre_len;
1778
1779                 offset32 &= ~3;
1780                 pre_len = 4 - (offset & 3);
1781
1782                 if (pre_len >= len32) {
1783                         pre_len = len32;
1784                         cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1785                 } else {
1786                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1787                 }
1788
1789                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1790                 if (rc)
1791                         return rc;
1792
1793                 memcpy(ret_buf, buf + (offset & 3), pre_len);
1794
1795                 offset32 += 4;
1796                 ret_buf += pre_len;
1797                 len32 -= pre_len;
1798         }
1799
1800         if (len32 & 3) {
1801                 extra = 4 - (len32 & 3);
1802                 len32 = (len32 + 4) & ~3;
1803         }
1804
1805         if (len32 == 4) {
1806                 uint8_t buf[4];
1807
1808                 if (cmd_flags)
1809                         cmd_flags = BCE_NVM_COMMAND_LAST;
1810                 else
1811                         cmd_flags = BCE_NVM_COMMAND_FIRST |
1812                                     BCE_NVM_COMMAND_LAST;
1813
1814                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1815
1816                 memcpy(ret_buf, buf, 4 - extra);
1817         } else if (len32 > 0) {
1818                 uint8_t buf[4];
1819
1820                 /* Read the first word. */
1821                 if (cmd_flags)
1822                         cmd_flags = 0;
1823                 else
1824                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1825
1826                 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1827
1828                 /* Advance to the next dword. */
1829                 offset32 += 4;
1830                 ret_buf += 4;
1831                 len32 -= 4;
1832
1833                 while (len32 > 4 && rc == 0) {
1834                         rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1835
1836                         /* Advance to the next dword. */
1837                         offset32 += 4;
1838                         ret_buf += 4;
1839                         len32 -= 4;
1840                 }
1841
1842                 if (rc)
1843                         goto bce_nvram_read_locked_exit;
1844
1845                 cmd_flags = BCE_NVM_COMMAND_LAST;
1846                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1847
1848                 memcpy(ret_buf, buf, 4 - extra);
1849         }
1850
1851 bce_nvram_read_locked_exit:
1852         /* Disable access to flash interface and release the lock. */
1853         bce_disable_nvram_access(sc);
1854         bce_release_nvram_lock(sc);
1855
1856         return rc;
1857 }
1858
1859
1860 /****************************************************************************/
1861 /* Verifies that NVRAM is accessible and contains valid data.               */
1862 /*                                                                          */
1863 /* Reads the configuration data from NVRAM and verifies that the CRC is     */
1864 /* correct.                                                                 */
1865 /*                                                                          */
1866 /* Returns:                                                                 */
1867 /*   0 on success, positive value on failure.                               */
1868 /****************************************************************************/
1869 static int
1870 bce_nvram_test(struct bce_softc *sc)
1871 {
1872         uint32_t buf[BCE_NVRAM_SIZE / 4];
1873         uint32_t magic, csum;
1874         uint8_t *data = (uint8_t *)buf;
1875         int rc = 0;
1876
1877         /*
1878          * Check that the device NVRAM is valid by reading
1879          * the magic value at offset 0.
1880          */
1881         rc = bce_nvram_read(sc, 0, data, 4);
1882         if (rc != 0)
1883                 return rc;
1884
1885         magic = be32toh(buf[0]);
1886         if (magic != BCE_NVRAM_MAGIC) {
1887                 if_printf(&sc->arpcom.ac_if,
1888                           "Invalid NVRAM magic value! Expected: 0x%08X, "
1889                           "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1890                 return ENODEV;
1891         }
1892
1893         /*
1894          * Verify that the device NVRAM includes valid
1895          * configuration data.
1896          */
1897         rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
1898         if (rc != 0)
1899                 return rc;
1900
1901         csum = ether_crc32_le(data, 0x100);
1902         if (csum != BCE_CRC32_RESIDUAL) {
1903                 if_printf(&sc->arpcom.ac_if,
1904                           "Invalid Manufacturing Information NVRAM CRC! "
1905                           "Expected: 0x%08X, Found: 0x%08X\n",
1906                           BCE_CRC32_RESIDUAL, csum);
1907                 return ENODEV;
1908         }
1909
1910         csum = ether_crc32_le(data + 0x100, 0x100);
1911         if (csum != BCE_CRC32_RESIDUAL) {
1912                 if_printf(&sc->arpcom.ac_if,
1913                           "Invalid Feature Configuration Information "
1914                           "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
1915                           BCE_CRC32_RESIDUAL, csum);
1916                 rc = ENODEV;
1917         }
1918         return rc;
1919 }
1920
1921
1922 /****************************************************************************/
1923 /* Identifies the current media type of the controller and sets the PHY     */
1924 /* address.                                                                 */
1925 /*                                                                          */
1926 /* Returns:                                                                 */
1927 /*   Nothing.                                                               */
1928 /****************************************************************************/
1929 static void
1930 bce_get_media(struct bce_softc *sc)
1931 {
1932         uint32_t val;
1933
1934         sc->bce_phy_addr = 1;
1935
1936         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1937             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1938                 uint32_t val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
1939                 uint32_t bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
1940                 uint32_t strap;
1941
1942                 /*
1943                  * The BCM5709S is software configurable
1944                  * for Copper or SerDes operation.
1945                  */
1946                 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
1947                         return;
1948                 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
1949                         sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1950                         return;
1951                 }
1952
1953                 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) {
1954                         strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
1955                 } else {
1956                         strap =
1957                         (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
1958                 }
1959
1960                 if (pci_get_function(sc->bce_dev) == 0) {
1961                         switch (strap) {
1962                         case 0x4:
1963                         case 0x5:
1964                         case 0x6:
1965                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1966                                 break;
1967                         }
1968                 } else {
1969                         switch (strap) {
1970                         case 0x1:
1971                         case 0x2:
1972                         case 0x4:
1973                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1974                                 break;
1975                         }
1976                 }
1977         } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
1978                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1979         }
1980
1981         if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
1982                 sc->bce_flags |= BCE_NO_WOL_FLAG;
1983                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
1984                         sc->bce_phy_addr = 2;
1985                         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
1986                         if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
1987                                 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
1988                 }
1989         } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
1990             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) {
1991                 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
1992         }
1993 }
1994
1995
1996 /****************************************************************************/
1997 /* Free any DMA memory owned by the driver.                                 */
1998 /*                                                                          */
1999 /* Scans through each data structre that requires DMA memory and frees      */
2000 /* the memory if allocated.                                                 */
2001 /*                                                                          */
2002 /* Returns:                                                                 */
2003 /*   Nothing.                                                               */
2004 /****************************************************************************/
2005 static void
2006 bce_dma_free(struct bce_softc *sc)
2007 {
2008         int i;
2009
2010         /* Destroy the status block. */
2011         if (sc->status_tag != NULL) {
2012                 if (sc->status_block != NULL) {
2013                         bus_dmamap_unload(sc->status_tag, sc->status_map);
2014                         bus_dmamem_free(sc->status_tag, sc->status_block,
2015                                         sc->status_map);
2016                 }
2017                 bus_dma_tag_destroy(sc->status_tag);
2018         }
2019
2020
2021         /* Destroy the statistics block. */
2022         if (sc->stats_tag != NULL) {
2023                 if (sc->stats_block != NULL) {
2024                         bus_dmamap_unload(sc->stats_tag, sc->stats_map);
2025                         bus_dmamem_free(sc->stats_tag, sc->stats_block,
2026                                         sc->stats_map);
2027                 }
2028                 bus_dma_tag_destroy(sc->stats_tag);
2029         }
2030
2031         /* Destroy the CTX DMA stuffs. */
2032         if (sc->ctx_tag != NULL) {
2033                 for (i = 0; i < sc->ctx_pages; i++) {
2034                         if (sc->ctx_block[i] != NULL) {
2035                                 bus_dmamap_unload(sc->ctx_tag, sc->ctx_map[i]);
2036                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2037                                                 sc->ctx_map[i]);
2038                         }
2039                 }
2040                 bus_dma_tag_destroy(sc->ctx_tag);
2041         }
2042
2043         /* Destroy the TX buffer descriptor DMA stuffs. */
2044         if (sc->tx_bd_chain_tag != NULL) {
2045                 for (i = 0; i < TX_PAGES; i++) {
2046                         if (sc->tx_bd_chain[i] != NULL) {
2047                                 bus_dmamap_unload(sc->tx_bd_chain_tag,
2048                                                   sc->tx_bd_chain_map[i]);
2049                                 bus_dmamem_free(sc->tx_bd_chain_tag,
2050                                                 sc->tx_bd_chain[i],
2051                                                 sc->tx_bd_chain_map[i]);
2052                         }
2053                 }
2054                 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
2055         }
2056
2057         /* Destroy the RX buffer descriptor DMA stuffs. */
2058         if (sc->rx_bd_chain_tag != NULL) {
2059                 for (i = 0; i < RX_PAGES; i++) {
2060                         if (sc->rx_bd_chain[i] != NULL) {
2061                                 bus_dmamap_unload(sc->rx_bd_chain_tag,
2062                                                   sc->rx_bd_chain_map[i]);
2063                                 bus_dmamem_free(sc->rx_bd_chain_tag,
2064                                                 sc->rx_bd_chain[i],
2065                                                 sc->rx_bd_chain_map[i]);
2066                         }
2067                 }
2068                 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
2069         }
2070
2071         /* Destroy the TX mbuf DMA stuffs. */
2072         if (sc->tx_mbuf_tag != NULL) {
2073                 for (i = 0; i < TOTAL_TX_BD; i++) {
2074                         /* Must have been unloaded in bce_stop() */
2075                         KKASSERT(sc->tx_mbuf_ptr[i] == NULL);
2076                         bus_dmamap_destroy(sc->tx_mbuf_tag,
2077                                            sc->tx_mbuf_map[i]);
2078                 }
2079                 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2080         }
2081
2082         /* Destroy the RX mbuf DMA stuffs. */
2083         if (sc->rx_mbuf_tag != NULL) {
2084                 for (i = 0; i < TOTAL_RX_BD; i++) {
2085                         /* Must have been unloaded in bce_stop() */
2086                         KKASSERT(sc->rx_mbuf_ptr[i] == NULL);
2087                         bus_dmamap_destroy(sc->rx_mbuf_tag,
2088                                            sc->rx_mbuf_map[i]);
2089                 }
2090                 bus_dmamap_destroy(sc->rx_mbuf_tag, sc->rx_mbuf_tmpmap);
2091                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2092         }
2093
2094         /* Destroy the parent tag */
2095         if (sc->parent_tag != NULL)
2096                 bus_dma_tag_destroy(sc->parent_tag);
2097 }
2098
2099
2100 /****************************************************************************/
2101 /* Get DMA memory from the OS.                                              */
2102 /*                                                                          */
2103 /* Validates that the OS has provided DMA buffers in response to a          */
2104 /* bus_dmamap_load() call and saves the physical address of those buffers.  */
2105 /* When the callback is used the OS will return 0 for the mapping function  */
2106 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any  */
2107 /* failures back to the caller.                                             */
2108 /*                                                                          */
2109 /* Returns:                                                                 */
2110 /*   Nothing.                                                               */
2111 /****************************************************************************/
2112 static void
2113 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2114 {
2115         bus_addr_t *busaddr = arg;
2116
2117         /*
2118          * Simulate a mapping failure.
2119          * XXX not correct.
2120          */
2121         DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2122                 kprintf("bce: %s(%d): Simulating DMA mapping error.\n",
2123                         __FILE__, __LINE__);
2124                 error = ENOMEM);
2125
2126         /* Check for an error and signal the caller that an error occurred. */
2127         if (error)
2128                 return;
2129
2130         KASSERT(nseg == 1, ("only one segment is allowed\n"));
2131         *busaddr = segs->ds_addr;
2132 }
2133
2134
2135 /****************************************************************************/
2136 /* Allocate any DMA memory needed by the driver.                            */
2137 /*                                                                          */
2138 /* Allocates DMA memory needed for the various global structures needed by  */
2139 /* hardware.                                                                */
2140 /*                                                                          */
2141 /* Memory alignment requirements:                                           */
2142 /* -----------------+----------+----------+----------+----------+           */
2143 /*  Data Structure  |   5706   |   5708   |   5709   |   5716   |           */
2144 /* -----------------+----------+----------+----------+----------+           */
2145 /* Status Block     | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2146 /* Statistics Block | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2147 /* RX Buffers       | 16 bytes | 16 bytes | 16 bytes | 16 bytes |           */
2148 /* PG Buffers       |   none   |   none   |   none   |   none   |           */
2149 /* TX Buffers       |   none   |   none   |   none   |   none   |           */
2150 /* Chain Pages(1)   |   4KiB   |   4KiB   |   4KiB   |   4KiB   |           */
2151 /* Context Pages(1) |   N/A    |   N/A    |   4KiB   |   4KiB   |           */
2152 /* -----------------+----------+----------+----------+----------+           */
2153 /*                                                                          */
2154 /* (1) Must align with CPU page size (BCM_PAGE_SZIE).                       */
2155 /*                                                                          */
2156 /* Returns:                                                                 */
2157 /*   0 for success, positive value for failure.                             */
2158 /****************************************************************************/
2159 static int
2160 bce_dma_alloc(struct bce_softc *sc)
2161 {
2162         struct ifnet *ifp = &sc->arpcom.ac_if;
2163         int i, j, rc = 0;
2164         bus_addr_t busaddr, max_busaddr;
2165         bus_size_t status_align, stats_align;
2166
2167         /*
2168          * The embedded PCIe to PCI-X bridge (EPB)
2169          * in the 5708 cannot address memory above
2170          * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
2171          */
2172         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
2173                 max_busaddr = BCE_BUS_SPACE_MAXADDR;
2174         else
2175                 max_busaddr = BUS_SPACE_MAXADDR;
2176
2177         /*
2178          * BCM5709 and BCM5716 uses host memory as cache for context memory.
2179          */
2180         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2181             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2182                 sc->ctx_pages = BCE_CTX_BLK_SZ / BCM_PAGE_SIZE;
2183                 if (sc->ctx_pages == 0)
2184                         sc->ctx_pages = 1;
2185                 if (sc->ctx_pages > BCE_CTX_PAGES) {
2186                         device_printf(sc->bce_dev, "excessive ctx pages %d\n",
2187                             sc->ctx_pages);
2188                         return ENOMEM;
2189                 }
2190                 status_align = 16;
2191                 stats_align = 16;
2192         } else {
2193                 status_align = 8;
2194                 stats_align = 8;
2195         }
2196
2197         /*
2198          * Allocate the parent bus DMA tag appropriate for PCI.
2199          */
2200         rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
2201                                 max_busaddr, BUS_SPACE_MAXADDR,
2202                                 NULL, NULL,
2203                                 BUS_SPACE_MAXSIZE_32BIT, 0,
2204                                 BUS_SPACE_MAXSIZE_32BIT,
2205                                 0, &sc->parent_tag);
2206         if (rc != 0) {
2207                 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2208                 return rc;
2209         }
2210
2211         /*
2212          * Allocate status block.
2213          */
2214         sc->status_block = bus_dmamem_coherent_any(sc->parent_tag,
2215                                 status_align, BCE_STATUS_BLK_SZ,
2216                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2217                                 &sc->status_tag, &sc->status_map,
2218                                 &sc->status_block_paddr);
2219         if (sc->status_block == NULL) {
2220                 if_printf(ifp, "Could not allocate status block!\n");
2221                 return ENOMEM;
2222         }
2223
2224         /*
2225          * Allocate statistics block.
2226          */
2227         sc->stats_block = bus_dmamem_coherent_any(sc->parent_tag,
2228                                 stats_align, BCE_STATS_BLK_SZ,
2229                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2230                                 &sc->stats_tag, &sc->stats_map,
2231                                 &sc->stats_block_paddr);
2232         if (sc->stats_block == NULL) {
2233                 if_printf(ifp, "Could not allocate statistics block!\n");
2234                 return ENOMEM;
2235         }
2236
2237         /*
2238          * Allocate context block, if needed
2239          */
2240         if (sc->ctx_pages != 0) {
2241                 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2242                                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2243                                         NULL, NULL,
2244                                         BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
2245                                         0, &sc->ctx_tag);
2246                 if (rc != 0) {
2247                         if_printf(ifp, "Could not allocate "
2248                                   "context block DMA tag!\n");
2249                         return rc;
2250                 }
2251
2252                 for (i = 0; i < sc->ctx_pages; i++) {
2253                         rc = bus_dmamem_alloc(sc->ctx_tag,
2254                                               (void **)&sc->ctx_block[i],
2255                                               BUS_DMA_WAITOK | BUS_DMA_ZERO |
2256                                               BUS_DMA_COHERENT,
2257                                               &sc->ctx_map[i]);
2258                         if (rc != 0) {
2259                                 if_printf(ifp, "Could not allocate %dth context "
2260                                           "DMA memory!\n", i);
2261                                 return rc;
2262                         }
2263
2264                         rc = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
2265                                              sc->ctx_block[i], BCM_PAGE_SIZE,
2266                                              bce_dma_map_addr, &busaddr,
2267                                              BUS_DMA_WAITOK);
2268                         if (rc != 0) {
2269                                 if (rc == EINPROGRESS) {
2270                                         panic("%s coherent memory loading "
2271                                               "is still in progress!", ifp->if_xname);
2272                                 }
2273                                 if_printf(ifp, "Could not map %dth context "
2274                                           "DMA memory!\n", i);
2275                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2276                                                 sc->ctx_map[i]);
2277                                 sc->ctx_block[i] = NULL;
2278                                 return rc;
2279                         }
2280                         sc->ctx_paddr[i] = busaddr;
2281                 }
2282         }
2283
2284         /*
2285          * Create a DMA tag for the TX buffer descriptor chain,
2286          * allocate and clear the  memory, and fetch the
2287          * physical address of the block.
2288          */
2289         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2290                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2291                                 NULL, NULL,
2292                                 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2293                                 0, &sc->tx_bd_chain_tag);
2294         if (rc != 0) {
2295                 if_printf(ifp, "Could not allocate "
2296                           "TX descriptor chain DMA tag!\n");
2297                 return rc;
2298         }
2299
2300         for (i = 0; i < TX_PAGES; i++) {
2301                 rc = bus_dmamem_alloc(sc->tx_bd_chain_tag,
2302                                       (void **)&sc->tx_bd_chain[i],
2303                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2304                                       BUS_DMA_COHERENT,
2305                                       &sc->tx_bd_chain_map[i]);
2306                 if (rc != 0) {
2307                         if_printf(ifp, "Could not allocate %dth TX descriptor "
2308                                   "chain DMA memory!\n", i);
2309                         return rc;
2310                 }
2311
2312                 rc = bus_dmamap_load(sc->tx_bd_chain_tag,
2313                                      sc->tx_bd_chain_map[i],
2314                                      sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ,
2315                                      bce_dma_map_addr, &busaddr,
2316                                      BUS_DMA_WAITOK);
2317                 if (rc != 0) {
2318                         if (rc == EINPROGRESS) {
2319                                 panic("%s coherent memory loading "
2320                                       "is still in progress!", ifp->if_xname);
2321                         }
2322                         if_printf(ifp, "Could not map %dth TX descriptor "
2323                                   "chain DMA memory!\n", i);
2324                         bus_dmamem_free(sc->tx_bd_chain_tag,
2325                                         sc->tx_bd_chain[i],
2326                                         sc->tx_bd_chain_map[i]);
2327                         sc->tx_bd_chain[i] = NULL;
2328                         return rc;
2329                 }
2330
2331                 sc->tx_bd_chain_paddr[i] = busaddr;
2332                 /* DRC - Fix for 64 bit systems. */
2333                 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n",
2334                         i, (uint32_t)sc->tx_bd_chain_paddr[i]);
2335         }
2336
2337         /* Create a DMA tag for TX mbufs. */
2338         rc = bus_dma_tag_create(sc->parent_tag, 1, 0,
2339                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2340                                 NULL, NULL,
2341                                 /* BCE_MAX_JUMBO_ETHER_MTU_VLAN */MCLBYTES,
2342                                 BCE_MAX_SEGMENTS, MCLBYTES,
2343                                 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2344                                 BUS_DMA_ONEBPAGE,
2345                                 &sc->tx_mbuf_tag);
2346         if (rc != 0) {
2347                 if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n");
2348                 return rc;
2349         }
2350
2351         /* Create DMA maps for the TX mbufs clusters. */
2352         for (i = 0; i < TOTAL_TX_BD; i++) {
2353                 rc = bus_dmamap_create(sc->tx_mbuf_tag,
2354                                        BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2355                                        &sc->tx_mbuf_map[i]);
2356                 if (rc != 0) {
2357                         for (j = 0; j < i; ++j) {
2358                                 bus_dmamap_destroy(sc->tx_mbuf_tag,
2359                                                    sc->tx_mbuf_map[i]);
2360                         }
2361                         bus_dma_tag_destroy(sc->tx_mbuf_tag);
2362                         sc->tx_mbuf_tag = NULL;
2363
2364                         if_printf(ifp, "Unable to create "
2365                                   "%dth TX mbuf DMA map!\n", i);
2366                         return rc;
2367                 }
2368         }
2369
2370         /*
2371          * Create a DMA tag for the RX buffer descriptor chain,
2372          * allocate and clear the  memory, and fetch the physical
2373          * address of the blocks.
2374          */
2375         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2376                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2377                                 NULL, NULL,
2378                                 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2379                                 0, &sc->rx_bd_chain_tag);
2380         if (rc != 0) {
2381                 if_printf(ifp, "Could not allocate "
2382                           "RX descriptor chain DMA tag!\n");
2383                 return rc;
2384         }
2385
2386         for (i = 0; i < RX_PAGES; i++) {
2387                 rc = bus_dmamem_alloc(sc->rx_bd_chain_tag,
2388                                       (void **)&sc->rx_bd_chain[i],
2389                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2390                                       BUS_DMA_COHERENT,
2391                                       &sc->rx_bd_chain_map[i]);
2392                 if (rc != 0) {
2393                         if_printf(ifp, "Could not allocate %dth RX descriptor "
2394                                   "chain DMA memory!\n", i);
2395                         return rc;
2396                 }
2397
2398                 rc = bus_dmamap_load(sc->rx_bd_chain_tag,
2399                                      sc->rx_bd_chain_map[i],
2400                                      sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ,
2401                                      bce_dma_map_addr, &busaddr,
2402                                      BUS_DMA_WAITOK);
2403                 if (rc != 0) {
2404                         if (rc == EINPROGRESS) {
2405                                 panic("%s coherent memory loading "
2406                                       "is still in progress!", ifp->if_xname);
2407                         }
2408                         if_printf(ifp, "Could not map %dth RX descriptor "
2409                                   "chain DMA memory!\n", i);
2410                         bus_dmamem_free(sc->rx_bd_chain_tag,
2411                                         sc->rx_bd_chain[i],
2412                                         sc->rx_bd_chain_map[i]);
2413                         sc->rx_bd_chain[i] = NULL;
2414                         return rc;
2415                 }
2416
2417                 sc->rx_bd_chain_paddr[i] = busaddr;
2418                 /* DRC - Fix for 64 bit systems. */
2419                 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2420                         i, (uint32_t)sc->rx_bd_chain_paddr[i]);
2421         }
2422
2423         /* Create a DMA tag for RX mbufs. */
2424         rc = bus_dma_tag_create(sc->parent_tag, BCE_DMA_RX_ALIGN, 0,
2425                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2426                                 NULL, NULL,
2427                                 MCLBYTES, 1, MCLBYTES,
2428                                 BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED |
2429                                 BUS_DMA_WAITOK,
2430                                 &sc->rx_mbuf_tag);
2431         if (rc != 0) {
2432                 if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n");
2433                 return rc;
2434         }
2435
2436         /* Create tmp DMA map for RX mbuf clusters. */
2437         rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2438                                &sc->rx_mbuf_tmpmap);
2439         if (rc != 0) {
2440                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2441                 sc->rx_mbuf_tag = NULL;
2442
2443                 if_printf(ifp, "Could not create RX mbuf tmp DMA map!\n");
2444                 return rc;
2445         }
2446
2447         /* Create DMA maps for the RX mbuf clusters. */
2448         for (i = 0; i < TOTAL_RX_BD; i++) {
2449                 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2450                                        &sc->rx_mbuf_map[i]);
2451                 if (rc != 0) {
2452                         for (j = 0; j < i; ++j) {
2453                                 bus_dmamap_destroy(sc->rx_mbuf_tag,
2454                                                    sc->rx_mbuf_map[j]);
2455                         }
2456                         bus_dma_tag_destroy(sc->rx_mbuf_tag);
2457                         sc->rx_mbuf_tag = NULL;
2458
2459                         if_printf(ifp, "Unable to create "
2460                                   "%dth RX mbuf DMA map!\n", i);
2461                         return rc;
2462                 }
2463         }
2464         return 0;
2465 }
2466
2467
2468 /****************************************************************************/
2469 /* Firmware synchronization.                                                */
2470 /*                                                                          */
2471 /* Before performing certain events such as a chip reset, synchronize with  */
2472 /* the firmware first.                                                      */
2473 /*                                                                          */
2474 /* Returns:                                                                 */
2475 /*   0 for success, positive value for failure.                             */
2476 /****************************************************************************/
2477 static int
2478 bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2479 {
2480         int i, rc = 0;
2481         uint32_t val;
2482
2483         /* Don't waste any time if we've timed out before. */
2484         if (sc->bce_fw_timed_out)
2485                 return EBUSY;
2486
2487         /* Increment the message sequence number. */
2488         sc->bce_fw_wr_seq++;
2489         msg_data |= sc->bce_fw_wr_seq;
2490
2491         DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
2492
2493         /* Send the message to the bootcode driver mailbox. */
2494         bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2495
2496         /* Wait for the bootcode to acknowledge the message. */
2497         for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2498                 /* Check for a response in the bootcode firmware mailbox. */
2499                 val = bce_shmem_rd(sc, BCE_FW_MB);
2500                 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2501                         break;
2502                 DELAY(1000);
2503         }
2504
2505         /* If we've timed out, tell the bootcode that we've stopped waiting. */
2506         if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2507             (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2508                 if_printf(&sc->arpcom.ac_if,
2509                           "Firmware synchronization timeout! "
2510                           "msg_data = 0x%08X\n", msg_data);
2511
2512                 msg_data &= ~BCE_DRV_MSG_CODE;
2513                 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2514
2515                 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2516
2517                 sc->bce_fw_timed_out = 1;
2518                 rc = EBUSY;
2519         }
2520         return rc;
2521 }
2522
2523
2524 /****************************************************************************/
2525 /* Load Receive Virtual 2 Physical (RV2P) processor firmware.               */
2526 /*                                                                          */
2527 /* Returns:                                                                 */
2528 /*   Nothing.                                                               */
2529 /****************************************************************************/
2530 static void
2531 bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2532                  uint32_t rv2p_code_len, uint32_t rv2p_proc)
2533 {
2534         int i;
2535         uint32_t val;
2536
2537         for (i = 0; i < rv2p_code_len; i += 8) {
2538                 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2539                 rv2p_code++;
2540                 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2541                 rv2p_code++;
2542
2543                 if (rv2p_proc == RV2P_PROC1) {
2544                         val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2545                         REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2546                 } else {
2547                         val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2548                         REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2549                 }
2550         }
2551
2552         /* Reset the processor, un-stall is done later. */
2553         if (rv2p_proc == RV2P_PROC1)
2554                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2555         else
2556                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2557 }
2558
2559
2560 /****************************************************************************/
2561 /* Load RISC processor firmware.                                            */
2562 /*                                                                          */
2563 /* Loads firmware from the file if_bcefw.h into the scratchpad memory       */
2564 /* associated with a particular processor.                                  */
2565 /*                                                                          */
2566 /* Returns:                                                                 */
2567 /*   Nothing.                                                               */
2568 /****************************************************************************/
2569 static void
2570 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2571                 struct fw_info *fw)
2572 {
2573         uint32_t offset, val;
2574         int j;
2575
2576         /* Halt the CPU. */
2577         val = REG_RD_IND(sc, cpu_reg->mode);
2578         val |= cpu_reg->mode_value_halt;
2579         REG_WR_IND(sc, cpu_reg->mode, val);
2580         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2581
2582         /* Load the Text area. */
2583         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2584         if (fw->text) {
2585                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2586                         REG_WR_IND(sc, offset, fw->text[j]);
2587         }
2588
2589         /* Load the Data area. */
2590         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2591         if (fw->data) {
2592                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2593                         REG_WR_IND(sc, offset, fw->data[j]);
2594         }
2595
2596         /* Load the SBSS area. */
2597         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2598         if (fw->sbss) {
2599                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2600                         REG_WR_IND(sc, offset, fw->sbss[j]);
2601         }
2602
2603         /* Load the BSS area. */
2604         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2605         if (fw->bss) {
2606                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2607                         REG_WR_IND(sc, offset, fw->bss[j]);
2608         }
2609
2610         /* Load the Read-Only area. */
2611         offset = cpu_reg->spad_base +
2612                 (fw->rodata_addr - cpu_reg->mips_view_base);
2613         if (fw->rodata) {
2614                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2615                         REG_WR_IND(sc, offset, fw->rodata[j]);
2616         }
2617
2618         /* Clear the pre-fetch instruction. */
2619         REG_WR_IND(sc, cpu_reg->inst, 0);
2620         REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2621
2622         /* Start the CPU. */
2623         val = REG_RD_IND(sc, cpu_reg->mode);
2624         val &= ~cpu_reg->mode_value_halt;
2625         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2626         REG_WR_IND(sc, cpu_reg->mode, val);
2627 }
2628
2629
2630 /****************************************************************************/
2631 /* Initialize the RX CPU.                                                   */
2632 /*                                                                          */
2633 /* Returns:                                                                 */
2634 /*   Nothing.                                                               */
2635 /****************************************************************************/
2636 static void
2637 bce_init_rxp_cpu(struct bce_softc *sc)
2638 {
2639         struct cpu_reg cpu_reg;
2640         struct fw_info fw;
2641
2642         cpu_reg.mode = BCE_RXP_CPU_MODE;
2643         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2644         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2645         cpu_reg.state = BCE_RXP_CPU_STATE;
2646         cpu_reg.state_value_clear = 0xffffff;
2647         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2648         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2649         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2650         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2651         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2652         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2653         cpu_reg.mips_view_base = 0x8000000;
2654
2655         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2656             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2657                 fw.ver_major = bce_RXP_b09FwReleaseMajor;
2658                 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
2659                 fw.ver_fix = bce_RXP_b09FwReleaseFix;
2660                 fw.start_addr = bce_RXP_b09FwStartAddr;
2661
2662                 fw.text_addr = bce_RXP_b09FwTextAddr;
2663                 fw.text_len = bce_RXP_b09FwTextLen;
2664                 fw.text_index = 0;
2665                 fw.text = bce_RXP_b09FwText;
2666
2667                 fw.data_addr = bce_RXP_b09FwDataAddr;
2668                 fw.data_len = bce_RXP_b09FwDataLen;
2669                 fw.data_index = 0;
2670                 fw.data = bce_RXP_b09FwData;
2671
2672                 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
2673                 fw.sbss_len = bce_RXP_b09FwSbssLen;
2674                 fw.sbss_index = 0;
2675                 fw.sbss = bce_RXP_b09FwSbss;
2676
2677                 fw.bss_addr = bce_RXP_b09FwBssAddr;
2678                 fw.bss_len = bce_RXP_b09FwBssLen;
2679                 fw.bss_index = 0;
2680                 fw.bss = bce_RXP_b09FwBss;
2681
2682                 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
2683                 fw.rodata_len = bce_RXP_b09FwRodataLen;
2684                 fw.rodata_index = 0;
2685                 fw.rodata = bce_RXP_b09FwRodata;
2686         } else {
2687                 fw.ver_major = bce_RXP_b06FwReleaseMajor;
2688                 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2689                 fw.ver_fix = bce_RXP_b06FwReleaseFix;
2690                 fw.start_addr = bce_RXP_b06FwStartAddr;
2691
2692                 fw.text_addr = bce_RXP_b06FwTextAddr;
2693                 fw.text_len = bce_RXP_b06FwTextLen;
2694                 fw.text_index = 0;
2695                 fw.text = bce_RXP_b06FwText;
2696
2697                 fw.data_addr = bce_RXP_b06FwDataAddr;
2698                 fw.data_len = bce_RXP_b06FwDataLen;
2699                 fw.data_index = 0;
2700                 fw.data = bce_RXP_b06FwData;
2701
2702                 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2703                 fw.sbss_len = bce_RXP_b06FwSbssLen;
2704                 fw.sbss_index = 0;
2705                 fw.sbss = bce_RXP_b06FwSbss;
2706
2707                 fw.bss_addr = bce_RXP_b06FwBssAddr;
2708                 fw.bss_len = bce_RXP_b06FwBssLen;
2709                 fw.bss_index = 0;
2710                 fw.bss = bce_RXP_b06FwBss;
2711
2712                 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2713                 fw.rodata_len = bce_RXP_b06FwRodataLen;
2714                 fw.rodata_index = 0;
2715                 fw.rodata = bce_RXP_b06FwRodata;
2716         }
2717
2718         DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
2719         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2720 }
2721
2722
2723 /****************************************************************************/
2724 /* Initialize the TX CPU.                                                   */
2725 /*                                                                          */
2726 /* Returns:                                                                 */
2727 /*   Nothing.                                                               */
2728 /****************************************************************************/
2729 static void
2730 bce_init_txp_cpu(struct bce_softc *sc)
2731 {
2732         struct cpu_reg cpu_reg;
2733         struct fw_info fw;
2734
2735         cpu_reg.mode = BCE_TXP_CPU_MODE;
2736         cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2737         cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2738         cpu_reg.state = BCE_TXP_CPU_STATE;
2739         cpu_reg.state_value_clear = 0xffffff;
2740         cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2741         cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2742         cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2743         cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2744         cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2745         cpu_reg.spad_base = BCE_TXP_SCRATCH;
2746         cpu_reg.mips_view_base = 0x8000000;
2747
2748         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2749             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2750                 fw.ver_major = bce_TXP_b09FwReleaseMajor;
2751                 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
2752                 fw.ver_fix = bce_TXP_b09FwReleaseFix;
2753                 fw.start_addr = bce_TXP_b09FwStartAddr;
2754
2755                 fw.text_addr = bce_TXP_b09FwTextAddr;
2756                 fw.text_len = bce_TXP_b09FwTextLen;
2757                 fw.text_index = 0;
2758                 fw.text = bce_TXP_b09FwText;
2759
2760                 fw.data_addr = bce_TXP_b09FwDataAddr;
2761                 fw.data_len = bce_TXP_b09FwDataLen;
2762                 fw.data_index = 0;
2763                 fw.data = bce_TXP_b09FwData;
2764
2765                 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
2766                 fw.sbss_len = bce_TXP_b09FwSbssLen;
2767                 fw.sbss_index = 0;
2768                 fw.sbss = bce_TXP_b09FwSbss;
2769
2770                 fw.bss_addr = bce_TXP_b09FwBssAddr;
2771                 fw.bss_len = bce_TXP_b09FwBssLen;
2772                 fw.bss_index = 0;
2773                 fw.bss = bce_TXP_b09FwBss;
2774
2775                 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
2776                 fw.rodata_len = bce_TXP_b09FwRodataLen;
2777                 fw.rodata_index = 0;
2778                 fw.rodata = bce_TXP_b09FwRodata;
2779         } else {
2780                 fw.ver_major = bce_TXP_b06FwReleaseMajor;
2781                 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2782                 fw.ver_fix = bce_TXP_b06FwReleaseFix;
2783                 fw.start_addr = bce_TXP_b06FwStartAddr;
2784
2785                 fw.text_addr = bce_TXP_b06FwTextAddr;
2786                 fw.text_len = bce_TXP_b06FwTextLen;
2787                 fw.text_index = 0;
2788                 fw.text = bce_TXP_b06FwText;
2789
2790                 fw.data_addr = bce_TXP_b06FwDataAddr;
2791                 fw.data_len = bce_TXP_b06FwDataLen;
2792                 fw.data_index = 0;
2793                 fw.data = bce_TXP_b06FwData;
2794
2795                 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2796                 fw.sbss_len = bce_TXP_b06FwSbssLen;
2797                 fw.sbss_index = 0;
2798                 fw.sbss = bce_TXP_b06FwSbss;
2799
2800                 fw.bss_addr = bce_TXP_b06FwBssAddr;
2801                 fw.bss_len = bce_TXP_b06FwBssLen;
2802                 fw.bss_index = 0;
2803                 fw.bss = bce_TXP_b06FwBss;
2804
2805                 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2806                 fw.rodata_len = bce_TXP_b06FwRodataLen;
2807                 fw.rodata_index = 0;
2808                 fw.rodata = bce_TXP_b06FwRodata;
2809         }
2810
2811         DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
2812         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2813 }
2814
2815
2816 /****************************************************************************/
2817 /* Initialize the TPAT CPU.                                                 */
2818 /*                                                                          */
2819 /* Returns:                                                                 */
2820 /*   Nothing.                                                               */
2821 /****************************************************************************/
2822 static void
2823 bce_init_tpat_cpu(struct bce_softc *sc)
2824 {
2825         struct cpu_reg cpu_reg;
2826         struct fw_info fw;
2827
2828         cpu_reg.mode = BCE_TPAT_CPU_MODE;
2829         cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2830         cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2831         cpu_reg.state = BCE_TPAT_CPU_STATE;
2832         cpu_reg.state_value_clear = 0xffffff;
2833         cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2834         cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2835         cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2836         cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
2837         cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
2838         cpu_reg.spad_base = BCE_TPAT_SCRATCH;
2839         cpu_reg.mips_view_base = 0x8000000;
2840
2841         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2842             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2843                 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
2844                 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
2845                 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
2846                 fw.start_addr = bce_TPAT_b09FwStartAddr;
2847
2848                 fw.text_addr = bce_TPAT_b09FwTextAddr;
2849                 fw.text_len = bce_TPAT_b09FwTextLen;
2850                 fw.text_index = 0;
2851                 fw.text = bce_TPAT_b09FwText;
2852
2853                 fw.data_addr = bce_TPAT_b09FwDataAddr;
2854                 fw.data_len = bce_TPAT_b09FwDataLen;
2855                 fw.data_index = 0;
2856                 fw.data = bce_TPAT_b09FwData;
2857
2858                 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
2859                 fw.sbss_len = bce_TPAT_b09FwSbssLen;
2860                 fw.sbss_index = 0;
2861                 fw.sbss = bce_TPAT_b09FwSbss;
2862
2863                 fw.bss_addr = bce_TPAT_b09FwBssAddr;
2864                 fw.bss_len = bce_TPAT_b09FwBssLen;
2865                 fw.bss_index = 0;
2866                 fw.bss = bce_TPAT_b09FwBss;
2867
2868                 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
2869                 fw.rodata_len = bce_TPAT_b09FwRodataLen;
2870                 fw.rodata_index = 0;
2871                 fw.rodata = bce_TPAT_b09FwRodata;
2872         } else {
2873                 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
2874                 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
2875                 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
2876                 fw.start_addr = bce_TPAT_b06FwStartAddr;
2877
2878                 fw.text_addr = bce_TPAT_b06FwTextAddr;
2879                 fw.text_len = bce_TPAT_b06FwTextLen;
2880                 fw.text_index = 0;
2881                 fw.text = bce_TPAT_b06FwText;
2882
2883                 fw.data_addr = bce_TPAT_b06FwDataAddr;
2884                 fw.data_len = bce_TPAT_b06FwDataLen;
2885                 fw.data_index = 0;
2886                 fw.data = bce_TPAT_b06FwData;
2887
2888                 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
2889                 fw.sbss_len = bce_TPAT_b06FwSbssLen;
2890                 fw.sbss_index = 0;
2891                 fw.sbss = bce_TPAT_b06FwSbss;
2892
2893                 fw.bss_addr = bce_TPAT_b06FwBssAddr;
2894                 fw.bss_len = bce_TPAT_b06FwBssLen;
2895                 fw.bss_index = 0;
2896                 fw.bss = bce_TPAT_b06FwBss;
2897
2898                 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
2899                 fw.rodata_len = bce_TPAT_b06FwRodataLen;
2900                 fw.rodata_index = 0;
2901                 fw.rodata = bce_TPAT_b06FwRodata;
2902         }
2903
2904         DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
2905         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2906 }
2907
2908
2909 /****************************************************************************/
2910 /* Initialize the CP CPU.                                                   */
2911 /*                                                                          */
2912 /* Returns:                                                                 */
2913 /*   Nothing.                                                               */
2914 /****************************************************************************/
2915 static void
2916 bce_init_cp_cpu(struct bce_softc *sc)
2917 {
2918         struct cpu_reg cpu_reg;
2919         struct fw_info fw;
2920
2921         cpu_reg.mode = BCE_CP_CPU_MODE;
2922         cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
2923         cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
2924         cpu_reg.state = BCE_CP_CPU_STATE;
2925         cpu_reg.state_value_clear = 0xffffff;
2926         cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
2927         cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
2928         cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
2929         cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
2930         cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
2931         cpu_reg.spad_base = BCE_CP_SCRATCH;
2932         cpu_reg.mips_view_base = 0x8000000;
2933
2934         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2935             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2936                 fw.ver_major = bce_CP_b09FwReleaseMajor;
2937                 fw.ver_minor = bce_CP_b09FwReleaseMinor;
2938                 fw.ver_fix = bce_CP_b09FwReleaseFix;
2939                 fw.start_addr = bce_CP_b09FwStartAddr;
2940
2941                 fw.text_addr = bce_CP_b09FwTextAddr;
2942                 fw.text_len = bce_CP_b09FwTextLen;
2943                 fw.text_index = 0;
2944                 fw.text = bce_CP_b09FwText;
2945
2946                 fw.data_addr = bce_CP_b09FwDataAddr;
2947                 fw.data_len = bce_CP_b09FwDataLen;
2948                 fw.data_index = 0;
2949                 fw.data = bce_CP_b09FwData;
2950
2951                 fw.sbss_addr = bce_CP_b09FwSbssAddr;
2952                 fw.sbss_len = bce_CP_b09FwSbssLen;
2953                 fw.sbss_index = 0;
2954                 fw.sbss = bce_CP_b09FwSbss;
2955
2956                 fw.bss_addr = bce_CP_b09FwBssAddr;
2957                 fw.bss_len = bce_CP_b09FwBssLen;
2958                 fw.bss_index = 0;
2959                 fw.bss = bce_CP_b09FwBss;
2960
2961                 fw.rodata_addr = bce_CP_b09FwRodataAddr;
2962                 fw.rodata_len = bce_CP_b09FwRodataLen;
2963                 fw.rodata_index = 0;
2964                 fw.rodata = bce_CP_b09FwRodata;
2965         } else {
2966                 fw.ver_major = bce_CP_b06FwReleaseMajor;
2967                 fw.ver_minor = bce_CP_b06FwReleaseMinor;
2968                 fw.ver_fix = bce_CP_b06FwReleaseFix;
2969                 fw.start_addr = bce_CP_b06FwStartAddr;
2970
2971                 fw.text_addr = bce_CP_b06FwTextAddr;
2972                 fw.text_len = bce_CP_b06FwTextLen;
2973                 fw.text_index = 0;
2974                 fw.text = bce_CP_b06FwText;
2975
2976                 fw.data_addr = bce_CP_b06FwDataAddr;
2977                 fw.data_len = bce_CP_b06FwDataLen;
2978                 fw.data_index = 0;
2979                 fw.data = bce_CP_b06FwData;
2980
2981                 fw.sbss_addr = bce_CP_b06FwSbssAddr;
2982                 fw.sbss_len = bce_CP_b06FwSbssLen;
2983                 fw.sbss_index = 0;
2984                 fw.sbss = bce_CP_b06FwSbss;
2985
2986                 fw.bss_addr = bce_CP_b06FwBssAddr;
2987                 fw.bss_len = bce_CP_b06FwBssLen;
2988                 fw.bss_index = 0;
2989                 fw.bss = bce_CP_b06FwBss;
2990
2991                 fw.rodata_addr = bce_CP_b06FwRodataAddr;
2992                 fw.rodata_len = bce_CP_b06FwRodataLen;
2993                 fw.rodata_index = 0;
2994                 fw.rodata = bce_CP_b06FwRodata;
2995         }
2996
2997         DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
2998         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2999 }
3000
3001
3002 /****************************************************************************/
3003 /* Initialize the COM CPU.                                                 */
3004 /*                                                                          */
3005 /* Returns:                                                                 */
3006 /*   Nothing.                                                               */
3007 /****************************************************************************/
3008 static void
3009 bce_init_com_cpu(struct bce_softc *sc)
3010 {
3011         struct cpu_reg cpu_reg;
3012         struct fw_info fw;
3013
3014         cpu_reg.mode = BCE_COM_CPU_MODE;
3015         cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
3016         cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
3017         cpu_reg.state = BCE_COM_CPU_STATE;
3018         cpu_reg.state_value_clear = 0xffffff;
3019         cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
3020         cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
3021         cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
3022         cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
3023         cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
3024         cpu_reg.spad_base = BCE_COM_SCRATCH;
3025         cpu_reg.mips_view_base = 0x8000000;
3026
3027         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3028             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3029                 fw.ver_major = bce_COM_b09FwReleaseMajor;
3030                 fw.ver_minor = bce_COM_b09FwReleaseMinor;
3031                 fw.ver_fix = bce_COM_b09FwReleaseFix;
3032                 fw.start_addr = bce_COM_b09FwStartAddr;
3033
3034                 fw.text_addr = bce_COM_b09FwTextAddr;
3035                 fw.text_len = bce_COM_b09FwTextLen;
3036                 fw.text_index = 0;
3037                 fw.text = bce_COM_b09FwText;
3038
3039                 fw.data_addr = bce_COM_b09FwDataAddr;
3040                 fw.data_len = bce_COM_b09FwDataLen;
3041                 fw.data_index = 0;
3042                 fw.data = bce_COM_b09FwData;
3043
3044                 fw.sbss_addr = bce_COM_b09FwSbssAddr;
3045                 fw.sbss_len = bce_COM_b09FwSbssLen;
3046                 fw.sbss_index = 0;
3047                 fw.sbss = bce_COM_b09FwSbss;
3048
3049                 fw.bss_addr = bce_COM_b09FwBssAddr;
3050                 fw.bss_len = bce_COM_b09FwBssLen;
3051                 fw.bss_index = 0;
3052                 fw.bss = bce_COM_b09FwBss;
3053
3054                 fw.rodata_addr = bce_COM_b09FwRodataAddr;
3055                 fw.rodata_len = bce_COM_b09FwRodataLen;
3056                 fw.rodata_index = 0;
3057                 fw.rodata = bce_COM_b09FwRodata;
3058         } else {
3059                 fw.ver_major = bce_COM_b06FwReleaseMajor;
3060                 fw.ver_minor = bce_COM_b06FwReleaseMinor;
3061                 fw.ver_fix = bce_COM_b06FwReleaseFix;
3062                 fw.start_addr = bce_COM_b06FwStartAddr;
3063
3064                 fw.text_addr = bce_COM_b06FwTextAddr;
3065                 fw.text_len = bce_COM_b06FwTextLen;
3066                 fw.text_index = 0;
3067                 fw.text = bce_COM_b06FwText;
3068
3069                 fw.data_addr = bce_COM_b06FwDataAddr;
3070                 fw.data_len = bce_COM_b06FwDataLen;
3071                 fw.data_index = 0;
3072                 fw.data = bce_COM_b06FwData;
3073
3074                 fw.sbss_addr = bce_COM_b06FwSbssAddr;
3075                 fw.sbss_len = bce_COM_b06FwSbssLen;
3076                 fw.sbss_index = 0;
3077                 fw.sbss = bce_COM_b06FwSbss;
3078
3079                 fw.bss_addr = bce_COM_b06FwBssAddr;
3080                 fw.bss_len = bce_COM_b06FwBssLen;
3081                 fw.bss_index = 0;
3082                 fw.bss = bce_COM_b06FwBss;
3083
3084                 fw.rodata_addr = bce_COM_b06FwRodataAddr;
3085                 fw.rodata_len = bce_COM_b06FwRodataLen;
3086                 fw.rodata_index = 0;
3087                 fw.rodata = bce_COM_b06FwRodata;
3088         }
3089
3090         DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
3091         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3092 }
3093
3094
3095 /****************************************************************************/
3096 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs.                     */
3097 /*                                                                          */
3098 /* Loads the firmware for each CPU and starts the CPU.                      */
3099 /*                                                                          */
3100 /* Returns:                                                                 */
3101 /*   Nothing.                                                               */
3102 /****************************************************************************/
3103 static void
3104 bce_init_cpus(struct bce_softc *sc)
3105 {
3106         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3107             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3108                 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax) {
3109                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
3110                             sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
3111                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
3112                             sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
3113                 } else {
3114                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
3115                             sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
3116                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
3117                             sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
3118                 }
3119         } else {
3120                 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
3121                     sizeof(bce_rv2p_proc1), RV2P_PROC1);
3122                 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
3123                     sizeof(bce_rv2p_proc2), RV2P_PROC2);
3124         }
3125
3126         bce_init_rxp_cpu(sc);
3127         bce_init_txp_cpu(sc);
3128         bce_init_tpat_cpu(sc);
3129         bce_init_com_cpu(sc);
3130         bce_init_cp_cpu(sc);
3131 }
3132
3133
3134 /****************************************************************************/
3135 /* Initialize context memory.                                               */
3136 /*                                                                          */
3137 /* Clears the memory associated with each Context ID (CID).                 */
3138 /*                                                                          */
3139 /* Returns:                                                                 */
3140 /*   Nothing.                                                               */
3141 /****************************************************************************/
3142 static void
3143 bce_init_ctx(struct bce_softc *sc)
3144 {
3145         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3146             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3147                 /* DRC: Replace this constant value with a #define. */
3148                 int i, retry_cnt = 10;
3149                 uint32_t val;
3150
3151                 /*
3152                  * BCM5709 context memory may be cached
3153                  * in host memory so prepare the host memory
3154                  * for access.
3155                  */
3156                 val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT |
3157                     (1 << 12);
3158                 val |= (BCM_PAGE_BITS - 8) << 16;
3159                 REG_WR(sc, BCE_CTX_COMMAND, val);
3160
3161                 /* Wait for mem init command to complete. */
3162                 for (i = 0; i < retry_cnt; i++) {
3163                         val = REG_RD(sc, BCE_CTX_COMMAND);
3164                         if (!(val & BCE_CTX_COMMAND_MEM_INIT))
3165                                 break;
3166                         DELAY(2);
3167                 }
3168
3169                 for (i = 0; i < sc->ctx_pages; i++) {
3170                         int j;
3171
3172                         /*
3173                          * Set the physical address of the context
3174                          * memory cache.
3175                          */
3176                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
3177                             BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
3178                             BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
3179                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
3180                             BCE_ADDR_HI(sc->ctx_paddr[i]));
3181                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL,
3182                             i | BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
3183
3184                         /*
3185                          * Verify that the context memory write was successful.
3186                          */
3187                         for (j = 0; j < retry_cnt; j++) {
3188                                 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
3189                                 if ((val &
3190                                     BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
3191                                         break;
3192                                 DELAY(5);
3193                         }
3194                 }
3195         } else {
3196                 uint32_t vcid_addr, offset;
3197
3198                 /*
3199                  * For the 5706/5708, context memory is local to
3200                  * the controller, so initialize the controller
3201                  * context memory.
3202                  */
3203
3204                 vcid_addr = GET_CID_ADDR(96);
3205                 while (vcid_addr) {
3206                         vcid_addr -= PHY_CTX_SIZE;
3207
3208                         REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
3209                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3210
3211                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
3212                                 CTX_WR(sc, 0x00, offset, 0);
3213
3214                         REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
3215                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3216                 }
3217         }
3218 }
3219
3220
3221 /****************************************************************************/
3222 /* Fetch the permanent MAC address of the controller.                       */
3223 /*                                                                          */
3224 /* Returns:                                                                 */
3225 /*   Nothing.                                                               */
3226 /****************************************************************************/
3227 static void
3228 bce_get_mac_addr(struct bce_softc *sc)
3229 {
3230         uint32_t mac_lo = 0, mac_hi = 0;
3231
3232         /*
3233          * The NetXtreme II bootcode populates various NIC
3234          * power-on and runtime configuration items in a
3235          * shared memory area.  The factory configured MAC
3236          * address is available from both NVRAM and the
3237          * shared memory area so we'll read the value from
3238          * shared memory for speed.
3239          */
3240
3241         mac_hi = bce_shmem_rd(sc,  BCE_PORT_HW_CFG_MAC_UPPER);
3242         mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
3243
3244         if (mac_lo == 0 && mac_hi == 0) {
3245                 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
3246         } else {
3247                 sc->eaddr[0] = (u_char)(mac_hi >> 8);
3248                 sc->eaddr[1] = (u_char)(mac_hi >> 0);
3249                 sc->eaddr[2] = (u_char)(mac_lo >> 24);
3250                 sc->eaddr[3] = (u_char)(mac_lo >> 16);
3251                 sc->eaddr[4] = (u_char)(mac_lo >> 8);
3252                 sc->eaddr[5] = (u_char)(mac_lo >> 0);
3253         }
3254
3255         DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
3256 }
3257
3258
3259 /****************************************************************************/
3260 /* Program the MAC address.                                                 */
3261 /*                                                                          */
3262 /* Returns:                                                                 */
3263 /*   Nothing.                                                               */
3264 /****************************************************************************/
3265 static void
3266 bce_set_mac_addr(struct bce_softc *sc)
3267 {
3268         const uint8_t *mac_addr = sc->eaddr;
3269         uint32_t val;
3270
3271         DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n",
3272                 sc->eaddr, ":");
3273
3274         val = (mac_addr[0] << 8) | mac_addr[1];
3275         REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
3276
3277         val = (mac_addr[2] << 24) |
3278               (mac_addr[3] << 16) |
3279               (mac_addr[4] << 8) |
3280               mac_addr[5];
3281         REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
3282 }
3283
3284
3285 /****************************************************************************/
3286 /* Stop the controller.                                                     */
3287 /*                                                                          */
3288 /* Returns:                                                                 */
3289 /*   Nothing.                                                               */
3290 /****************************************************************************/
3291 static void
3292 bce_stop(struct bce_softc *sc)
3293 {
3294         struct ifnet *ifp = &sc->arpcom.ac_if;
3295         struct mii_data *mii = device_get_softc(sc->bce_miibus);
3296         struct ifmedia_entry *ifm;
3297         int mtmp, itmp;
3298
3299         ASSERT_SERIALIZED(ifp->if_serializer);
3300
3301         callout_stop(&sc->bce_tick_callout);
3302
3303         /* Disable the transmit/receive blocks. */
3304         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
3305         REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3306         DELAY(20);
3307
3308         bce_disable_intr(sc);
3309
3310         /* Free the RX lists. */
3311         bce_free_rx_chain(sc);
3312
3313         /* Free TX buffers. */
3314         bce_free_tx_chain(sc);
3315
3316         /*
3317          * Isolate/power down the PHY, but leave the media selection
3318          * unchanged so that things will be put back to normal when
3319          * we bring the interface back up.
3320          *
3321          * 'mii' may be NULL if bce_stop() is called by bce_detach().
3322          */
3323         if (mii != NULL) {
3324                 itmp = ifp->if_flags;
3325                 ifp->if_flags |= IFF_UP;
3326                 ifm = mii->mii_media.ifm_cur;
3327                 mtmp = ifm->ifm_media;
3328                 ifm->ifm_media = IFM_ETHER | IFM_NONE;
3329                 mii_mediachg(mii);
3330                 ifm->ifm_media = mtmp;
3331                 ifp->if_flags = itmp;
3332         }
3333
3334         sc->bce_link = 0;
3335         sc->bce_coalchg_mask = 0;
3336
3337         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3338         ifp->if_timer = 0;
3339 }
3340
3341
3342 static int
3343 bce_reset(struct bce_softc *sc, uint32_t reset_code)
3344 {
3345         uint32_t val;
3346         int i, rc = 0;
3347
3348         /* Wait for pending PCI transactions to complete. */
3349         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
3350                BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3351                BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3352                BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3353                BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3354         val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3355         DELAY(5);
3356
3357         /* Disable DMA */
3358         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3359             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3360                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3361                 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3362                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3363         }
3364
3365         /* Assume bootcode is running. */
3366         sc->bce_fw_timed_out = 0;
3367
3368         /* Give the firmware a chance to prepare for the reset. */
3369         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
3370         if (rc) {
3371                 if_printf(&sc->arpcom.ac_if,
3372                           "Firmware is not ready for reset\n");
3373                 return rc;
3374         }
3375
3376         /* Set a firmware reminder that this is a soft reset. */
3377         bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE,
3378             BCE_DRV_RESET_SIGNATURE_MAGIC);
3379
3380         /* Dummy read to force the chip to complete all current transactions. */
3381         val = REG_RD(sc, BCE_MISC_ID);
3382
3383         /* Chip reset. */
3384         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3385             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3386                 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
3387                 REG_RD(sc, BCE_MISC_COMMAND);
3388                 DELAY(5);
3389
3390                 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3391                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3392
3393                 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
3394         } else {
3395                 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3396                     BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3397                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3398                 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
3399
3400                 /* Allow up to 30us for reset to complete. */
3401                 for (i = 0; i < 10; i++) {
3402                         val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
3403                         if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3404                             BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3405                                 break;
3406                         DELAY(10);
3407                 }
3408
3409                 /* Check that reset completed successfully. */
3410                 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3411                     BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3412                         if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
3413                         return EBUSY;
3414                 }
3415         }
3416
3417         /* Make sure byte swapping is properly configured. */
3418         val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
3419         if (val != 0x01020304) {
3420                 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
3421                 return ENODEV;
3422         }
3423
3424         /* Just completed a reset, assume that firmware is running again. */
3425         sc->bce_fw_timed_out = 0;
3426
3427         /* Wait for the firmware to finish its initialization. */
3428         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3429         if (rc) {
3430                 if_printf(&sc->arpcom.ac_if,
3431                           "Firmware did not complete initialization!\n");
3432         }
3433         return rc;
3434 }
3435
3436
3437 static int
3438 bce_chipinit(struct bce_softc *sc)
3439 {
3440         uint32_t val;
3441         int rc = 0;
3442
3443         /* Make sure the interrupt is not active. */
3444         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
3445         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
3446
3447         /*
3448          * Initialize DMA byte/word swapping, configure the number of DMA
3449          * channels and PCI clock compensation delay.
3450          */
3451         val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3452               BCE_DMA_CONFIG_DATA_WORD_SWAP |
3453 #if BYTE_ORDER == BIG_ENDIAN
3454               BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3455 #endif
3456               BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3457               DMA_READ_CHANS << 12 |
3458               DMA_WRITE_CHANS << 16;
3459
3460         val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3461
3462         if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3463                 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3464
3465         /*
3466          * This setting resolves a problem observed on certain Intel PCI
3467          * chipsets that cannot handle multiple outstanding DMA operations.
3468          * See errata E9_5706A1_65.
3469          */
3470         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3471             BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3472             !(sc->bce_flags & BCE_PCIX_FLAG))
3473                 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3474
3475         REG_WR(sc, BCE_DMA_CONFIG, val);
3476
3477         /* Enable the RX_V2P and Context state machines before access. */
3478         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3479                BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3480                BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3481                BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3482
3483         /* Initialize context mapping and zero out the quick contexts. */
3484         bce_init_ctx(sc);
3485
3486         /* Initialize the on-boards CPUs */
3487         bce_init_cpus(sc);
3488
3489         /* Prepare NVRAM for access. */
3490         rc = bce_init_nvram(sc);
3491         if (rc != 0)
3492                 return rc;
3493
3494         /* Set the kernel bypass block size */
3495         val = REG_RD(sc, BCE_MQ_CONFIG);
3496         val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3497         val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3498
3499         /* Enable bins used on the 5709/5716. */
3500         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3501             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3502                 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
3503                 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
3504                         val |= BCE_MQ_CONFIG_HALT_DIS;
3505         }
3506
3507         REG_WR(sc, BCE_MQ_CONFIG, val);
3508
3509         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3510         REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3511         REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3512
3513         /* Set the page size and clear the RV2P processor stall bits. */
3514         val = (BCM_PAGE_BITS - 8) << 24;
3515         REG_WR(sc, BCE_RV2P_CONFIG, val);
3516
3517         /* Configure page size. */
3518         val = REG_RD(sc, BCE_TBDR_CONFIG);
3519         val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
3520         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3521         REG_WR(sc, BCE_TBDR_CONFIG, val);
3522
3523         /* Set the perfect match control register to default. */
3524         REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
3525
3526         return 0;
3527 }
3528
3529
3530 /****************************************************************************/
3531 /* Initialize the controller in preparation to send/receive traffic.        */
3532 /*                                                                          */
3533 /* Returns:                                                                 */
3534 /*   0 for success, positive value for failure.                             */
3535 /****************************************************************************/
3536 static int
3537 bce_blockinit(struct bce_softc *sc)
3538 {
3539         uint32_t reg, val;
3540         int rc = 0;
3541
3542         /* Load the hardware default MAC address. */
3543         bce_set_mac_addr(sc);
3544
3545         /* Set the Ethernet backoff seed value */
3546         val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
3547               sc->eaddr[3] + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
3548         REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
3549
3550         sc->last_status_idx = 0;
3551         sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
3552
3553         /* Set up link change interrupt generation. */
3554         REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
3555
3556         /* Program the physical address of the status block. */
3557         REG_WR(sc, BCE_HC_STATUS_ADDR_L, BCE_ADDR_LO(sc->status_block_paddr));
3558         REG_WR(sc, BCE_HC_STATUS_ADDR_H, BCE_ADDR_HI(sc->status_block_paddr));
3559
3560         /* Program the physical address of the statistics block. */
3561         REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
3562                BCE_ADDR_LO(sc->stats_block_paddr));
3563         REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
3564                BCE_ADDR_HI(sc->stats_block_paddr));
3565
3566         /* Program various host coalescing parameters. */
3567         REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
3568                (sc->bce_tx_quick_cons_trip_int << 16) |
3569                sc->bce_tx_quick_cons_trip);
3570         REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
3571                (sc->bce_rx_quick_cons_trip_int << 16) |
3572                sc->bce_rx_quick_cons_trip);
3573         REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
3574                (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
3575         REG_WR(sc, BCE_HC_TX_TICKS,
3576                (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
3577         REG_WR(sc, BCE_HC_RX_TICKS,
3578                (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
3579         REG_WR(sc, BCE_HC_COM_TICKS,
3580                (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
3581         REG_WR(sc, BCE_HC_CMD_TICKS,
3582                (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
3583         REG_WR(sc, BCE_HC_STATS_TICKS, (sc->bce_stats_ticks & 0xffff00));
3584         REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8);   /* 3ms */
3585         REG_WR(sc, BCE_HC_CONFIG,
3586                BCE_HC_CONFIG_TX_TMR_MODE |
3587                BCE_HC_CONFIG_COLLECT_STATS);
3588
3589         /* Clear the internal statistics counters. */
3590         REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
3591
3592         /* Verify that bootcode is running. */
3593         reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);
3594
3595         DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure),
3596                 if_printf(&sc->arpcom.ac_if,
3597                           "%s(%d): Simulating bootcode failure.\n",
3598                           __FILE__, __LINE__);
3599                 reg = 0);
3600
3601         if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
3602             BCE_DEV_INFO_SIGNATURE_MAGIC) {
3603                 if_printf(&sc->arpcom.ac_if,
3604                           "Bootcode not running! Found: 0x%08X, "
3605                           "Expected: 08%08X\n",
3606                           reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK,
3607                           BCE_DEV_INFO_SIGNATURE_MAGIC);
3608                 return ENODEV;
3609         }
3610
3611         /* Enable DMA */
3612         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3613             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3614                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3615                 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3616                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3617         }
3618
3619         /* Allow bootcode to apply any additional fixes before enabling MAC. */
3620         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET);
3621
3622         /* Enable link state change interrupt generation. */
3623         REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3624
3625         /* Enable all remaining blocks in the MAC. */
3626         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3627             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3628                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3629                     BCE_MISC_ENABLE_DEFAULT_XI);
3630         } else {
3631                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
3632         }
3633         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
3634         DELAY(20);
3635
3636         /* Save the current host coalescing block settings. */
3637         sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
3638
3639         return 0;
3640 }
3641
3642
3643 /****************************************************************************/
3644 /* Encapsulate an mbuf cluster into the rx_bd chain.                        */
3645 /*                                                                          */
3646 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's.     */
3647 /* This routine will map an mbuf cluster into 1 or more rx_bd's as          */
3648 /* necessary.                                                               */
3649 /*                                                                          */
3650 /* Returns:                                                                 */
3651 /*   0 for success, positive value for failure.                             */
3652 /****************************************************************************/
3653 static int
3654 bce_newbuf_std(struct bce_softc *sc, uint16_t *prod, uint16_t *chain_prod,
3655                uint32_t *prod_bseq, int init)
3656 {
3657         bus_dmamap_t map;
3658         bus_dma_segment_t seg;
3659         struct mbuf *m_new;
3660         int error, nseg;
3661 #ifdef BCE_DEBUG
3662         uint16_t debug_chain_prod = *chain_prod;
3663 #endif
3664
3665         /* Make sure the inputs are valid. */
3666         DBRUNIF((*chain_prod > MAX_RX_BD),
3667                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3668                           "RX producer out of range: 0x%04X > 0x%04X\n",
3669                           __FILE__, __LINE__,
3670                           *chain_prod, (uint16_t)MAX_RX_BD));
3671
3672         DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, "
3673                 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3674
3675         DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
3676                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3677                           "Simulating mbuf allocation failure.\n",
3678                           __FILE__, __LINE__);
3679                 sc->mbuf_alloc_failed++;
3680                 return ENOBUFS);
3681
3682         /* This is a new mbuf allocation. */
3683         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
3684         if (m_new == NULL)
3685                 return ENOBUFS;
3686         DBRUNIF(1, sc->rx_mbuf_alloc++);
3687
3688         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
3689
3690         /* Map the mbuf cluster into device memory. */
3691         error = bus_dmamap_load_mbuf_segment(sc->rx_mbuf_tag,
3692                         sc->rx_mbuf_tmpmap, m_new, &seg, 1, &nseg,
3693                         BUS_DMA_NOWAIT);
3694         if (error) {
3695                 m_freem(m_new);
3696                 if (init) {
3697                         if_printf(&sc->arpcom.ac_if,
3698                                   "Error mapping mbuf into RX chain!\n");
3699                 }
3700                 DBRUNIF(1, sc->rx_mbuf_alloc--);
3701                 return error;
3702         }
3703
3704         if (sc->rx_mbuf_ptr[*chain_prod] != NULL) {
3705                 bus_dmamap_unload(sc->rx_mbuf_tag,
3706                                   sc->rx_mbuf_map[*chain_prod]);
3707         }
3708
3709         map = sc->rx_mbuf_map[*chain_prod];
3710         sc->rx_mbuf_map[*chain_prod] = sc->rx_mbuf_tmpmap;
3711         sc->rx_mbuf_tmpmap = map;
3712
3713         /* Watch for overflow. */
3714         DBRUNIF((sc->free_rx_bd > USABLE_RX_BD),
3715                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3716                           "Too many free rx_bd (0x%04X > 0x%04X)!\n",
3717                           __FILE__, __LINE__, sc->free_rx_bd,
3718                           (uint16_t)USABLE_RX_BD));
3719
3720         /* Update some debug statistic counters */
3721         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3722                 sc->rx_low_watermark = sc->free_rx_bd);
3723         DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
3724
3725         /* Save the mbuf and update our counter. */
3726         sc->rx_mbuf_ptr[*chain_prod] = m_new;
3727         sc->rx_mbuf_paddr[*chain_prod] = seg.ds_addr;
3728         sc->free_rx_bd--;
3729
3730         bce_setup_rxdesc_std(sc, *chain_prod, prod_bseq);
3731
3732         DBRUN(BCE_VERBOSE_RECV,
3733               bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 1));
3734
3735         DBPRINT(sc, BCE_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, "
3736                 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3737
3738         return 0;
3739 }
3740
3741
3742 static void
3743 bce_setup_rxdesc_std(struct bce_softc *sc, uint16_t chain_prod, uint32_t *prod_bseq)
3744 {
3745         struct rx_bd *rxbd;
3746         bus_addr_t paddr;
3747         int len;
3748
3749         paddr = sc->rx_mbuf_paddr[chain_prod];
3750         len = sc->rx_mbuf_ptr[chain_prod]->m_len;
3751
3752         /* Setup the rx_bd for the first segment. */
3753         rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)];
3754
3755         rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(paddr));
3756         rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(paddr));
3757         rxbd->rx_bd_len = htole32(len);
3758         rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START);
3759         *prod_bseq += len;
3760
3761         rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END);
3762 }
3763
3764
3765 /****************************************************************************/
3766 /* Initialize the TX context memory.                                        */
3767 /*                                                                          */
3768 /* Returns:                                                                 */
3769 /*   Nothing                                                                */
3770 /****************************************************************************/
3771 static void
3772 bce_init_tx_context(struct bce_softc *sc)
3773 {
3774         uint32_t val;
3775
3776         /* Initialize the context ID for an L2 TX chain. */
3777         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3778             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3779                 /* Set the CID type to support an L2 connection. */
3780                 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3781                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val);
3782                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3783                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE_XI, val);
3784
3785                 /* Point the hardware to the first page in the chain. */
3786                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3787                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3788                     BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
3789                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3790                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3791                     BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
3792         } else {
3793                 /* Set the CID type to support an L2 connection. */
3794                 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3795                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val);
3796                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3797                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val);
3798
3799                 /* Point the hardware to the first page in the chain. */
3800                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3801                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3802                     BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
3803                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3804                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3805                     BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
3806         }
3807 }
3808
3809
3810 /****************************************************************************/
3811 /* Allocate memory and initialize the TX data structures.                   */
3812 /*                                                                          */
3813 /* Returns:                                                                 */
3814 /*   0 for success, positive value for failure.                             */
3815 /****************************************************************************/
3816 static int
3817 bce_init_tx_chain(struct bce_softc *sc)
3818 {
3819         struct tx_bd *txbd;
3820         int i, rc = 0;
3821
3822         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3823
3824         /* Set the initial TX producer/consumer indices. */
3825         sc->tx_prod = 0;
3826         sc->tx_cons = 0;
3827         sc->tx_prod_bseq   = 0;
3828         sc->used_tx_bd = 0;
3829         sc->max_tx_bd = USABLE_TX_BD;
3830         DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD);
3831         DBRUNIF(1, sc->tx_full_count = 0);
3832
3833         /*
3834          * The NetXtreme II supports a linked-list structre called
3835          * a Buffer Descriptor Chain (or BD chain).  A BD chain
3836          * consists of a series of 1 or more chain pages, each of which
3837          * consists of a fixed number of BD entries.
3838          * The last BD entry on each page is a pointer to the next page
3839          * in the chain, and the last pointer in the BD chain
3840          * points back to the beginning of the chain.
3841          */
3842
3843         /* Set the TX next pointer chain entries. */
3844         for (i = 0; i < TX_PAGES; i++) {
3845                 int j;
3846
3847                 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
3848
3849                 /* Check if we've reached the last page. */
3850                 if (i == (TX_PAGES - 1))
3851                         j = 0;
3852                 else
3853                         j = i + 1;
3854
3855                 txbd->tx_bd_haddr_hi =
3856                         htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
3857                 txbd->tx_bd_haddr_lo =
3858                         htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
3859         }
3860         bce_init_tx_context(sc);
3861
3862         return(rc);
3863 }
3864
3865
3866 /****************************************************************************/
3867 /* Free memory and clear the TX data structures.                            */
3868 /*                                                                          */
3869 /* Returns:                                                                 */
3870 /*   Nothing.                                                               */
3871 /****************************************************************************/
3872 static void
3873 bce_free_tx_chain(struct bce_softc *sc)
3874 {
3875         int i;
3876
3877         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3878
3879         /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
3880         for (i = 0; i < TOTAL_TX_BD; i++) {
3881                 if (sc->tx_mbuf_ptr[i] != NULL) {
3882                         bus_dmamap_unload(sc->tx_mbuf_tag, sc->tx_mbuf_map[i]);
3883                         m_freem(sc->tx_mbuf_ptr[i]);
3884                         sc->tx_mbuf_ptr[i] = NULL;
3885                         DBRUNIF(1, sc->tx_mbuf_alloc--);
3886                 }
3887         }
3888
3889         /* Clear each TX chain page. */
3890         for (i = 0; i < TX_PAGES; i++)
3891                 bzero(sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
3892         sc->used_tx_bd = 0;
3893
3894         /* Check if we lost any mbufs in the process. */
3895         DBRUNIF((sc->tx_mbuf_alloc),
3896                 if_printf(&sc->arpcom.ac_if,
3897                           "%s(%d): Memory leak! "
3898                           "Lost %d mbufs from tx chain!\n",
3899                           __FILE__, __LINE__, sc->tx_mbuf_alloc));
3900
3901         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3902 }
3903
3904
3905 /****************************************************************************/
3906 /* Initialize the RX context memory.                                        */
3907 /*                                                                          */
3908 /* Returns:                                                                 */
3909 /*   Nothing                                                                */
3910 /****************************************************************************/
3911 static void
3912 bce_init_rx_context(struct bce_softc *sc)
3913 {
3914         uint32_t val;
3915
3916         /* Initialize the context ID for an L2 RX chain. */
3917         val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
3918             BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
3919
3920         /*
3921          * Set the level for generating pause frames
3922          * when the number of available rx_bd's gets
3923          * too low (the low watermark) and the level
3924          * when pause frames can be stopped (the high
3925          * watermark).
3926          */
3927         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3928             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3929                 uint32_t lo_water, hi_water;
3930
3931                 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT;
3932                 hi_water = USABLE_RX_BD / 4;
3933
3934                 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE;
3935                 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE;
3936
3937                 if (hi_water > 0xf)
3938                         hi_water = 0xf;
3939                 else if (hi_water == 0)
3940                         lo_water = 0;
3941                 val |= lo_water |
3942                     (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT);
3943         }
3944
3945         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val);
3946
3947         /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
3948         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3949             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3950                 val = REG_RD(sc, BCE_MQ_MAP_L2_5);
3951                 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
3952         }
3953
3954         /* Point the hardware to the first page in the chain. */
3955         val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
3956         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val);
3957         val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
3958         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val);
3959 }
3960
3961
3962 /****************************************************************************/
3963 /* Allocate memory and initialize the RX data structures.                   */
3964 /*                                                                          */
3965 /* Returns:                                                                 */
3966 /*   0 for success, positive value for failure.                             */
3967 /****************************************************************************/
3968 static int
3969 bce_init_rx_chain(struct bce_softc *sc)
3970 {
3971         struct rx_bd *rxbd;
3972         int i, rc = 0;
3973         uint16_t prod, chain_prod;
3974         uint32_t prod_bseq;
3975
3976         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3977
3978         /* Initialize the RX producer and consumer indices. */
3979         sc->rx_prod = 0;
3980         sc->rx_cons = 0;
3981         sc->rx_prod_bseq = 0;
3982         sc->free_rx_bd = USABLE_RX_BD;
3983         sc->max_rx_bd = USABLE_RX_BD;
3984         DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD);
3985         DBRUNIF(1, sc->rx_empty_count = 0);
3986
3987         /* Initialize the RX next pointer chain entries. */
3988         for (i = 0; i < RX_PAGES; i++) {
3989                 int j;
3990
3991                 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
3992
3993                 /* Check if we've reached the last page. */
3994                 if (i == (RX_PAGES - 1))
3995                         j = 0;
3996                 else
3997                         j = i + 1;
3998
3999                 /* Setup the chain page pointers. */
4000                 rxbd->rx_bd_haddr_hi =
4001                         htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
4002                 rxbd->rx_bd_haddr_lo =
4003                         htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
4004         }
4005
4006         /* Allocate mbuf clusters for the rx_bd chain. */
4007         prod = prod_bseq = 0;
4008         while (prod < TOTAL_RX_BD) {
4009                 chain_prod = RX_CHAIN_IDX(prod);
4010                 if (bce_newbuf_std(sc, &prod, &chain_prod, &prod_bseq, 1)) {
4011                         if_printf(&sc->arpcom.ac_if,
4012                                   "Error filling RX chain: rx_bd[0x%04X]!\n",
4013                                   chain_prod);
4014                         rc = ENOBUFS;
4015                         break;
4016                 }
4017                 prod = NEXT_RX_BD(prod);
4018         }
4019
4020         /* Save the RX chain producer index. */
4021         sc->rx_prod = prod;
4022         sc->rx_prod_bseq = prod_bseq;
4023
4024         /* Tell the chip about the waiting rx_bd's. */
4025         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
4026             sc->rx_prod);
4027         REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
4028             sc->rx_prod_bseq);
4029
4030         bce_init_rx_context(sc);
4031
4032         return(rc);
4033 }
4034
4035
4036 /****************************************************************************/
4037 /* Free memory and clear the RX data structures.                            */
4038 /*                                                                          */
4039 /* Returns:                                                                 */
4040 /*   Nothing.                                                               */
4041 /****************************************************************************/
4042 static void
4043 bce_free_rx_chain(struct bce_softc *sc)
4044 {
4045         int i;
4046
4047         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4048
4049         /* Free any mbufs still in the RX mbuf chain. */
4050         for (i = 0; i < TOTAL_RX_BD; i++) {
4051                 if (sc->rx_mbuf_ptr[i] != NULL) {
4052                         bus_dmamap_unload(sc->rx_mbuf_tag, sc->rx_mbuf_map[i]);
4053                         m_freem(sc->rx_mbuf_ptr[i]);
4054                         sc->rx_mbuf_ptr[i] = NULL;
4055                         DBRUNIF(1, sc->rx_mbuf_alloc--);
4056                 }
4057         }
4058
4059         /* Clear each RX chain page. */
4060         for (i = 0; i < RX_PAGES; i++)
4061                 bzero(sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ);
4062
4063         /* Check if we lost any mbufs in the process. */
4064         DBRUNIF((sc->rx_mbuf_alloc),
4065                 if_printf(&sc->arpcom.ac_if,
4066                           "%s(%d): Memory leak! "
4067                           "Lost %d mbufs from rx chain!\n",
4068                           __FILE__, __LINE__, sc->rx_mbuf_alloc));
4069
4070         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
4071 }
4072
4073
4074 /****************************************************************************/
4075 /* Set media options.                                                       */
4076 /*                                                                          */
4077 /* Returns:                                                                 */
4078 /*   0 for success, positive value for failure.                             */
4079 /****************************************************************************/
4080 static int
4081 bce_ifmedia_upd(struct ifnet *ifp)
4082 {
4083         struct bce_softc *sc = ifp->if_softc;
4084         struct mii_data *mii = device_get_softc(sc->bce_miibus);
4085
4086         /*
4087          * 'mii' will be NULL, when this function is called on following
4088          * code path: bce_attach() -> bce_mgmt_init()
4089          */
4090         if (mii != NULL) {
4091                 /* Make sure the MII bus has been enumerated. */
4092                 sc->bce_link = 0;
4093                 if (mii->mii_instance) {
4094                         struct mii_softc *miisc;
4095
4096                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
4097                                 mii_phy_reset(miisc);
4098                 }
4099                 mii_mediachg(mii);
4100         }
4101         return 0;
4102 }
4103
4104
4105 /****************************************************************************/
4106 /* Reports current media status.                                            */
4107 /*                                                                          */
4108 /* Returns:                                                                 */
4109 /*   Nothing.                                                               */
4110 /****************************************************************************/
4111 static void
4112 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4113 {
4114         struct bce_softc *sc = ifp->if_softc;
4115         struct mii_data *mii = device_get_softc(sc->bce_miibus);
4116
4117         mii_pollstat(mii);
4118         ifmr->ifm_active = mii->mii_media_active;
4119         ifmr->ifm_status = mii->mii_media_status;
4120 }
4121
4122
4123 /****************************************************************************/
4124 /* Handles PHY generated interrupt events.                                  */
4125 /*                                                                          */
4126 /* Returns:                                                                 */
4127 /*   Nothing.                                                               */
4128 /****************************************************************************/
4129 static void
4130 bce_phy_intr(struct bce_softc *sc)
4131 {
4132         uint32_t new_link_state, old_link_state;
4133         struct ifnet *ifp = &sc->arpcom.ac_if;
4134
4135         ASSERT_SERIALIZED(ifp->if_serializer);
4136
4137         new_link_state = sc->status_block->status_attn_bits &
4138                          STATUS_ATTN_BITS_LINK_STATE;
4139         old_link_state = sc->status_block->status_attn_bits_ack &
4140                          STATUS_ATTN_BITS_LINK_STATE;
4141
4142         /* Handle any changes if the link state has changed. */
4143         if (new_link_state != old_link_state) { /* XXX redundant? */
4144                 DBRUN(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
4145
4146                 /* Update the status_attn_bits_ack field in the status block. */
4147                 if (new_link_state) {
4148                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
4149                                STATUS_ATTN_BITS_LINK_STATE);
4150                         if (bootverbose)
4151                                 if_printf(ifp, "Link is now UP.\n");
4152                 } else {
4153                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
4154                                STATUS_ATTN_BITS_LINK_STATE);
4155                         if (bootverbose)
4156                                 if_printf(ifp, "Link is now DOWN.\n");
4157                 }
4158
4159                 /*
4160                  * Assume link is down and allow tick routine to
4161                  * update the state based on the actual media state.
4162                  */
4163                 sc->bce_link = 0;
4164                 callout_stop(&sc->bce_tick_callout);
4165                 bce_tick_serialized(sc);
4166         }
4167
4168         /* Acknowledge the link change interrupt. */
4169         REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
4170 }
4171
4172
4173 /****************************************************************************/
4174 /* Reads the receive consumer value from the status block (skipping over    */
4175 /* chain page pointer if necessary).                                        */
4176 /*                                                                          */
4177 /* Returns:                                                                 */
4178 /*   hw_cons                                                                */
4179 /****************************************************************************/
4180 static __inline uint16_t
4181 bce_get_hw_rx_cons(struct bce_softc *sc)
4182 {
4183         uint16_t hw_cons = sc->status_block->status_rx_quick_consumer_index0;
4184
4185         if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
4186                 hw_cons++;
4187         return hw_cons;
4188 }
4189
4190
4191 /****************************************************************************/
4192 /* Handles received frame interrupt events.                                 */
4193 /*                                                                          */
4194 /* Returns:                                                                 */
4195 /*   Nothing.                                                               */
4196 /****************************************************************************/
4197 static void
4198 bce_rx_intr(struct bce_softc *sc, int count)
4199 {
4200         struct ifnet *ifp = &sc->arpcom.ac_if;
4201         uint16_t hw_cons, sw_cons, sw_chain_cons, sw_prod, sw_chain_prod;
4202         uint32_t sw_prod_bseq;
4203         struct mbuf_chain chain[MAXCPU];
4204
4205         ASSERT_SERIALIZED(ifp->if_serializer);
4206
4207         ether_input_chain_init(chain);
4208
4209         DBRUNIF(1, sc->rx_interrupts++);
4210
4211         /* Get the hardware's view of the RX consumer index. */
4212         hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
4213
4214         /* Get working copies of the driver's view of the RX indices. */
4215         sw_cons = sc->rx_cons;
4216         sw_prod = sc->rx_prod;
4217         sw_prod_bseq = sc->rx_prod_bseq;
4218
4219         DBPRINT(sc, BCE_INFO_RECV, "%s(enter): sw_prod = 0x%04X, "
4220                 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n",
4221                 __func__, sw_prod, sw_cons, sw_prod_bseq);
4222
4223         /* Prevent speculative reads from getting ahead of the status block. */
4224         bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4225                           BUS_SPACE_BARRIER_READ);
4226
4227         /* Update some debug statistics counters */
4228         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
4229                 sc->rx_low_watermark = sc->free_rx_bd);
4230         DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
4231
4232         /* Scan through the receive chain as long as there is work to do. */
4233         while (sw_cons != hw_cons) {
4234                 struct mbuf *m = NULL;
4235                 struct l2_fhdr *l2fhdr = NULL;
4236                 struct rx_bd *rxbd;
4237                 unsigned int len;
4238                 uint32_t status = 0;
4239
4240 #ifdef DEVICE_POLLING
4241                 if (count >= 0 && count-- == 0) {
4242                         sc->hw_rx_cons = sw_cons;
4243                         break;
4244                 }
4245 #endif
4246
4247                 /*
4248                  * Convert the producer/consumer indices
4249                  * to an actual rx_bd index.
4250                  */
4251                 sw_chain_cons = RX_CHAIN_IDX(sw_cons);
4252                 sw_chain_prod = RX_CHAIN_IDX(sw_prod);
4253
4254                 /* Get the used rx_bd. */
4255                 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)]
4256                                        [RX_IDX(sw_chain_cons)];
4257                 sc->free_rx_bd++;
4258
4259                 DBRUN(BCE_VERBOSE_RECV,
4260                       if_printf(ifp, "%s(): ", __func__);
4261                       bce_dump_rxbd(sc, sw_chain_cons, rxbd));
4262
4263                 /* The mbuf is stored with the last rx_bd entry of a packet. */
4264                 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) {
4265                         /* Validate that this is the last rx_bd. */
4266                         DBRUNIF((!(rxbd->rx_bd_flags & RX_BD_FLAGS_END)),
4267                                 if_printf(ifp, "%s(%d): "
4268                                 "Unexpected mbuf found in rx_bd[0x%04X]!\n",
4269                                 __FILE__, __LINE__, sw_chain_cons);
4270                                 bce_breakpoint(sc));
4271
4272                         if (sw_chain_cons != sw_chain_prod) {
4273                                 if_printf(ifp, "RX cons(%d) != prod(%d), "
4274                                           "drop!\n", sw_chain_cons,
4275                                           sw_chain_prod);
4276                                 ifp->if_ierrors++;
4277
4278                                 bce_setup_rxdesc_std(sc, sw_chain_cons,
4279                                                      &sw_prod_bseq);
4280                                 m = NULL;
4281                                 goto bce_rx_int_next_rx;
4282                         }
4283
4284                         /* Unmap the mbuf from DMA space. */
4285                         bus_dmamap_sync(sc->rx_mbuf_tag,
4286                                         sc->rx_mbuf_map[sw_chain_cons],
4287                                         BUS_DMASYNC_POSTREAD);
4288
4289                         /* Save the mbuf from the driver's chain. */
4290                         m = sc->rx_mbuf_ptr[sw_chain_cons];
4291
4292                         /*
4293                          * Frames received on the NetXteme II are prepended
4294                          * with an l2_fhdr structure which provides status
4295                          * information about the received frame (including
4296                          * VLAN tags and checksum info).  The frames are also
4297                          * automatically adjusted to align the IP header
4298                          * (i.e. two null bytes are inserted before the
4299                          * Ethernet header).  As a result the data DMA'd by
4300                          * the controller into the mbuf is as follows:
4301                          *
4302                          * +---------+-----+---------------------+-----+
4303                          * | l2_fhdr | pad | packet data         | FCS |
4304                          * +---------+-----+---------------------+-----+
4305                          *
4306                          * The l2_fhdr needs to be checked and skipped and the
4307                          * FCS needs to be stripped before sending the packet
4308                          * up the stack.
4309                          */
4310                         l2fhdr = mtod(m, struct l2_fhdr *);
4311
4312                         len = l2fhdr->l2_fhdr_pkt_len;
4313                         status = l2fhdr->l2_fhdr_status;
4314
4315                         DBRUNIF(DB_RANDOMTRUE(bce_debug_l2fhdr_status_check),
4316                                 if_printf(ifp,
4317                                 "Simulating l2_fhdr status error.\n");
4318                                 status = status | L2_FHDR_ERRORS_PHY_DECODE);
4319
4320                         /* Watch for unusual sized frames. */
4321                         DBRUNIF((len < BCE_MIN_MTU ||
4322                                  len > BCE_MAX_JUMBO_ETHER_MTU_VLAN),
4323                                 if_printf(ifp,
4324                                 "%s(%d): Unusual frame size found. "
4325                                 "Min(%d), Actual(%d), Max(%d)\n",
4326                                 __FILE__, __LINE__,
4327                                 (int)BCE_MIN_MTU, len,
4328                                 (int)BCE_MAX_JUMBO_ETHER_MTU_VLAN);
4329                                 bce_dump_mbuf(sc, m);
4330                                 bce_breakpoint(sc));
4331
4332                         len -= ETHER_CRC_LEN;
4333
4334                         /* Check the received frame for errors. */
4335                         if (status & (L2_FHDR_ERRORS_BAD_CRC |
4336                                       L2_FHDR_ERRORS_PHY_DECODE |
4337                                       L2_FHDR_ERRORS_ALIGNMENT |
4338                                       L2_FHDR_ERRORS_TOO_SHORT |
4339                                       L2_FHDR_ERRORS_GIANT_FRAME)) {
4340                                 ifp->if_ierrors++;
4341                                 DBRUNIF(1, sc->l2fhdr_status_errors++);
4342
4343                                 /* Reuse the mbuf for a new frame. */
4344                                 bce_setup_rxdesc_std(sc, sw_chain_prod,
4345                                                      &sw_prod_bseq);
4346                                 m = NULL;
4347                                 goto bce_rx_int_next_rx;
4348                         }
4349
4350                         /*
4351                          * Get a new mbuf for the rx_bd.   If no new
4352                          * mbufs are available then reuse the current mbuf,
4353                          * log an ierror on the interface, and generate
4354                          * an error in the system log.
4355                          */
4356                         if (bce_newbuf_std(sc, &sw_prod, &sw_chain_prod,
4357                                            &sw_prod_bseq, 0)) {
4358                                 DBRUN(BCE_WARN,
4359                                       if_printf(ifp,
4360                                       "%s(%d): Failed to allocate new mbuf, "
4361                                       "incoming frame dropped!\n",
4362                                       __FILE__, __LINE__));
4363
4364                                 ifp->if_ierrors++;
4365
4366                                 /* Try and reuse the exisitng mbuf. */
4367                                 bce_setup_rxdesc_std(sc, sw_chain_prod,
4368                                                      &sw_prod_bseq);
4369                                 m = NULL;
4370                                 goto bce_rx_int_next_rx;
4371                         }
4372
4373                         /*
4374                          * Skip over the l2_fhdr when passing
4375                          * the data up the stack.
4376                          */
4377                         m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN);
4378
4379                         m->m_pkthdr.len = m->m_len = len;
4380                         m->m_pkthdr.rcvif = ifp;
4381
4382                         DBRUN(BCE_VERBOSE_RECV,
4383                               struct ether_header *eh;
4384                               eh = mtod(m, struct ether_header *);
4385                               if_printf(ifp, "%s(): to: %6D, from: %6D, "
4386                                         "type: 0x%04X\n", __func__,
4387                                         eh->ether_dhost, ":",
4388                                         eh->ether_shost, ":",
4389                                         htons(eh->ether_type)));
4390
4391                         /* Validate the checksum if offload enabled. */
4392                         if (ifp->if_capenable & IFCAP_RXCSUM) {
4393                                 /* Check for an IP datagram. */
4394                                 if (status & L2_FHDR_STATUS_IP_DATAGRAM) {
4395                                         m->m_pkthdr.csum_flags |=
4396                                                 CSUM_IP_CHECKED;
4397
4398                                         /* Check if the IP checksum is valid. */
4399                                         if ((l2fhdr->l2_fhdr_ip_xsum ^
4400                                              0xffff) == 0) {
4401                                                 m->m_pkthdr.csum_flags |=
4402                                                         CSUM_IP_VALID;
4403                                         } else {
4404                                                 DBPRINT(sc, BCE_WARN_RECV,
4405                                                         "%s(): Invalid IP checksum = 0x%04X!\n",
4406                                                         __func__, l2fhdr->l2_fhdr_ip_xsum);
4407                                         }
4408                                 }
4409
4410                                 /* Check for a valid TCP/UDP frame. */
4411                                 if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
4412                                               L2_FHDR_STATUS_UDP_DATAGRAM)) {
4413
4414                                         /* Check for a good TCP/UDP checksum. */
4415                                         if ((status &
4416                                              (L2_FHDR_ERRORS_TCP_XSUM |
4417                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
4418                                                 m->m_pkthdr.csum_data =
4419                                                 l2fhdr->l2_fhdr_tcp_udp_xsum;
4420                                                 m->m_pkthdr.csum_flags |=
4421                                                         CSUM_DATA_VALID |
4422                                                         CSUM_PSEUDO_HDR;
4423                                         } else {
4424                                                 DBPRINT(sc, BCE_WARN_RECV,
4425                                                         "%s(): Invalid TCP/UDP checksum = 0x%04X!\n",
4426                                                         __func__, l2fhdr->l2_fhdr_tcp_udp_xsum);
4427                                         }
4428                                 }
4429                         }
4430
4431                         ifp->if_ipackets++;
4432 bce_rx_int_next_rx:
4433                         sw_prod = NEXT_RX_BD(sw_prod);
4434                 }
4435
4436                 sw_cons = NEXT_RX_BD(sw_cons);
4437
4438                 /* If we have a packet, pass it up the stack */
4439                 if (m) {
4440                         DBPRINT(sc, BCE_VERBOSE_RECV,
4441                                 "%s(): Passing received frame up.\n", __func__);
4442
4443                         if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
4444                                 m->m_flags |= M_VLANTAG;
4445                                 m->m_pkthdr.ether_vlantag =
4446                                         l2fhdr->l2_fhdr_vlan_tag;
4447                         }
4448                         ether_input_chain(ifp, m, NULL, chain);
4449
4450                         DBRUNIF(1, sc->rx_mbuf_alloc--);
4451                 }
4452
4453                 /*
4454                  * If polling(4) is not enabled, refresh hw_cons to see
4455                  * whether there's new work.
4456                  *
4457                  * If polling(4) is enabled, i.e count >= 0, refreshing
4458                  * should not be performed, so that we would not spend
4459                  * too much time in RX processing.
4460                  */
4461                 if (count < 0 && sw_cons == hw_cons)
4462                         hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
4463
4464                 /*
4465                  * Prevent speculative reads from getting ahead
4466                  * of the status block.
4467                  */
4468                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4469                                   BUS_SPACE_BARRIER_READ);
4470         }
4471
4472         ether_input_dispatch(chain);
4473
4474         sc->rx_cons = sw_cons;
4475         sc->rx_prod = sw_prod;
4476         sc->rx_prod_bseq = sw_prod_bseq;
4477
4478         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
4479             sc->rx_prod);
4480         REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
4481             sc->rx_prod_bseq);
4482
4483         DBPRINT(sc, BCE_INFO_RECV, "%s(exit): rx_prod = 0x%04X, "
4484                 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
4485                 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
4486 }
4487
4488
4489 /****************************************************************************/
4490 /* Reads the transmit consumer value from the status block (skipping over   */
4491 /* chain page pointer if necessary).                                        */
4492 /*                                                                          */
4493 /* Returns:                                                                 */
4494 /*   hw_cons                                                                */
4495 /****************************************************************************/
4496 static __inline uint16_t
4497 bce_get_hw_tx_cons(struct bce_softc *sc)
4498 {
4499         uint16_t hw_cons = sc->status_block->status_tx_quick_consumer_index0;
4500
4501         if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
4502                 hw_cons++;
4503         return hw_cons;
4504 }
4505
4506
4507 /****************************************************************************/
4508 /* Handles transmit completion interrupt events.                            */
4509 /*                                                                          */
4510 /* Returns:                                                                 */
4511 /*   Nothing.                                                               */
4512 /****************************************************************************/
4513 static void
4514 bce_tx_intr(struct bce_softc *sc)
4515 {
4516         struct ifnet *ifp = &sc->arpcom.ac_if;
4517         uint16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
4518
4519         ASSERT_SERIALIZED(ifp->if_serializer);
4520
4521         DBRUNIF(1, sc->tx_interrupts++);
4522
4523         /* Get the hardware's view of the TX consumer index. */
4524         hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4525         sw_tx_cons = sc->tx_cons;
4526
4527         /* Prevent speculative reads from getting ahead of the status block. */
4528         bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4529                           BUS_SPACE_BARRIER_READ);
4530
4531         /* Cycle through any completed TX chain page entries. */
4532         while (sw_tx_cons != hw_tx_cons) {
4533 #ifdef BCE_DEBUG
4534                 struct tx_bd *txbd = NULL;
4535 #endif
4536                 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons);
4537
4538                 DBPRINT(sc, BCE_INFO_SEND,
4539                         "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
4540                         "sw_tx_chain_cons = 0x%04X\n",
4541                         __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
4542
4543                 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD),
4544                         if_printf(ifp, "%s(%d): "
4545                                   "TX chain consumer out of range! "
4546                                   " 0x%04X > 0x%04X\n",
4547                                   __FILE__, __LINE__, sw_tx_chain_cons,
4548                                   (int)MAX_TX_BD);
4549                         bce_breakpoint(sc));
4550
4551                 DBRUNIF(1, txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
4552                                 [TX_IDX(sw_tx_chain_cons)]);
4553
4554                 DBRUNIF((txbd == NULL),
4555                         if_printf(ifp, "%s(%d): "
4556                                   "Unexpected NULL tx_bd[0x%04X]!\n",
4557                                   __FILE__, __LINE__, sw_tx_chain_cons);
4558                         bce_breakpoint(sc));
4559
4560                 DBRUN(BCE_INFO_SEND,
4561                       if_printf(ifp, "%s(): ", __func__);
4562                       bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
4563
4564                 /*
4565                  * Free the associated mbuf. Remember
4566                  * that only the last tx_bd of a packet
4567                  * has an mbuf pointer and DMA map.
4568                  */
4569                 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
4570                         /* Validate that this is the last tx_bd. */
4571                         DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
4572                                 if_printf(ifp, "%s(%d): "
4573                                 "tx_bd END flag not set but "
4574                                 "txmbuf == NULL!\n", __FILE__, __LINE__);
4575                                 bce_breakpoint(sc));
4576
4577                         DBRUN(BCE_INFO_SEND,
4578                               if_printf(ifp, "%s(): Unloading map/freeing mbuf "
4579                                         "from tx_bd[0x%04X]\n", __func__,
4580                                         sw_tx_chain_cons));
4581
4582                         /* Unmap the mbuf. */
4583                         bus_dmamap_unload(sc->tx_mbuf_tag,
4584                                           sc->tx_mbuf_map[sw_tx_chain_cons]);
4585
4586                         /* Free the mbuf. */
4587                         m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
4588                         sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
4589                         DBRUNIF(1, sc->tx_mbuf_alloc--);
4590
4591                         ifp->if_opackets++;
4592                 }
4593
4594                 sc->used_tx_bd--;
4595                 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
4596
4597                 if (sw_tx_cons == hw_tx_cons) {
4598                         /* Refresh hw_cons to see if there's new work. */
4599                         hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4600                 }
4601
4602                 /*
4603                  * Prevent speculative reads from getting
4604                  * ahead of the status block.
4605                  */
4606                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4607                                   BUS_SPACE_BARRIER_READ);
4608         }
4609
4610         if (sc->used_tx_bd == 0) {
4611                 /* Clear the TX timeout timer. */
4612                 ifp->if_timer = 0;
4613         }
4614
4615         /* Clear the tx hardware queue full flag. */
4616         if (sc->max_tx_bd - sc->used_tx_bd >= BCE_TX_SPARE_SPACE) {
4617                 DBRUNIF((ifp->if_flags & IFF_OACTIVE),
4618                         DBPRINT(sc, BCE_WARN_SEND,
4619                                 "%s(): Open TX chain! %d/%d (used/total)\n",
4620                                 __func__, sc->used_tx_bd, sc->max_tx_bd));
4621                 ifp->if_flags &= ~IFF_OACTIVE;
4622         }
4623         sc->tx_cons = sw_tx_cons;
4624 }
4625
4626
4627 /****************************************************************************/
4628 /* Disables interrupt generation.                                           */
4629 /*                                                                          */
4630 /* Returns:                                                                 */
4631 /*   Nothing.                                                               */
4632 /****************************************************************************/
4633 static void
4634 bce_disable_intr(struct bce_softc *sc)
4635 {
4636         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4637         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
4638         lwkt_serialize_handler_disable(sc->arpcom.ac_if.if_serializer);
4639 }
4640
4641
4642 /****************************************************************************/
4643 /* Enables interrupt generation.                                            */
4644 /*                                                                          */
4645 /* Returns:                                                                 */
4646 /*   Nothing.                                                               */
4647 /****************************************************************************/
4648 static void
4649 bce_enable_intr(struct bce_softc *sc, int coal_now)
4650 {
4651         lwkt_serialize_handler_enable(sc->arpcom.ac_if.if_serializer);
4652
4653         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4654                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
4655                BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
4656
4657         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4658                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4659
4660         if (coal_now) {
4661                 REG_WR(sc, BCE_HC_COMMAND,
4662                     sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
4663         }
4664 }
4665
4666
4667 /****************************************************************************/
4668 /* Handles controller initialization.                                       */
4669 /*                                                                          */
4670 /* Returns:                                                                 */
4671 /*   Nothing.                                                               */
4672 /****************************************************************************/
4673 static void
4674 bce_init(void *xsc)
4675 {
4676         struct bce_softc *sc = xsc;
4677         struct ifnet *ifp = &sc->arpcom.ac_if;
4678         uint32_t ether_mtu;
4679         int error;
4680
4681         ASSERT_SERIALIZED(ifp->if_serializer);
4682
4683         /* Check if the driver is still running and bail out if it is. */
4684         if (ifp->if_flags & IFF_RUNNING)
4685                 return;
4686
4687         bce_stop(sc);
4688
4689         error = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
4690         if (error) {
4691                 if_printf(ifp, "Controller reset failed!\n");
4692                 goto back;
4693         }
4694
4695         error = bce_chipinit(sc);
4696         if (error) {
4697                 if_printf(ifp, "Controller initialization failed!\n");
4698                 goto back;
4699         }
4700
4701         error = bce_blockinit(sc);
4702         if (error) {
4703                 if_printf(ifp, "Block initialization failed!\n");
4704                 goto back;
4705         }
4706
4707         /* Load our MAC address. */
4708         bcopy(IF_LLADDR(ifp), sc->eaddr, ETHER_ADDR_LEN);
4709         bce_set_mac_addr(sc);
4710
4711         /* Calculate and program the Ethernet MTU size. */
4712         ether_mtu = ETHER_HDR_LEN + EVL_ENCAPLEN + ifp->if_mtu + ETHER_CRC_LEN;
4713
4714         DBPRINT(sc, BCE_INFO, "%s(): setting mtu = %d\n", __func__, ether_mtu);
4715
4716         /*
4717          * Program the mtu, enabling jumbo frame
4718          * support if necessary.  Also set the mbuf
4719          * allocation count for RX frames.
4720          */
4721         if (ether_mtu > ETHER_MAX_LEN + EVL_ENCAPLEN) {
4722 #ifdef notyet
4723                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
4724                        min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
4725                        BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
4726                 sc->mbuf_alloc_size = MJUM9BYTES;
4727 #else
4728                 panic("jumbo buffer is not supported yet\n");
4729 #endif
4730         } else {
4731                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
4732                 sc->mbuf_alloc_size = MCLBYTES;
4733         }
4734
4735         /* Calculate the RX Ethernet frame size for rx_bd's. */
4736         sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8;
4737
4738         DBPRINT(sc, BCE_INFO,
4739                 "%s(): mclbytes = %d, mbuf_alloc_size = %d, "
4740                 "max_frame_size = %d\n",
4741                 __func__, (int)MCLBYTES, sc->mbuf_alloc_size,
4742                 sc->max_frame_size);
4743
4744         /* Program appropriate promiscuous/multicast filtering. */
4745         bce_set_rx_mode(sc);
4746
4747         /* Init RX buffer descriptor chain. */
4748         bce_init_rx_chain(sc);  /* XXX return value */
4749
4750         /* Init TX buffer descriptor chain. */
4751         bce_init_tx_chain(sc);  /* XXX return value */
4752
4753 #ifdef DEVICE_POLLING
4754         /* Disable interrupts if we are polling. */
4755         if (ifp->if_flags & IFF_POLLING) {
4756                 bce_disable_intr(sc);
4757
4758                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4759                        (1 << 16) | sc->bce_rx_quick_cons_trip);
4760                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4761                        (1 << 16) | sc->bce_tx_quick_cons_trip);
4762         } else
4763 #endif
4764         /* Enable host interrupts. */
4765         bce_enable_intr(sc, 1);
4766
4767         bce_ifmedia_upd(ifp);
4768
4769         ifp->if_flags |= IFF_RUNNING;
4770         ifp->if_flags &= ~IFF_OACTIVE;
4771
4772         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
4773 back:
4774         if (error)
4775                 bce_stop(sc);
4776 }
4777
4778
4779 /****************************************************************************/
4780 /* Initialize the controller just enough so that any management firmware    */
4781 /* running on the device will continue to operate corectly.                 */
4782 /*                                                                          */
4783 /* Returns:                                                                 */
4784 /*   Nothing.                                                               */
4785 /****************************************************************************/
4786 static void
4787 bce_mgmt_init(struct bce_softc *sc)
4788 {
4789         struct ifnet *ifp = &sc->arpcom.ac_if;
4790
4791         /* Bail out if management firmware is not running. */
4792         if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
4793                 return;
4794
4795         /* Enable all critical blocks in the MAC. */
4796         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4797             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4798                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
4799                     BCE_MISC_ENABLE_DEFAULT_XI);
4800         } else {
4801                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
4802         }
4803         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
4804         DELAY(20);
4805
4806         bce_ifmedia_upd(ifp);
4807 }
4808
4809
4810 /****************************************************************************/
4811 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
4812 /* memory visible to the controller.                                        */
4813 /*                                                                          */
4814 /* Returns:                                                                 */
4815 /*   0 for success, positive value for failure.                             */
4816 /****************************************************************************/
4817 static int
4818 bce_encap(struct bce_softc *sc, struct mbuf **m_head)
4819 {
4820         bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
4821         bus_dmamap_t map, tmp_map;
4822         struct mbuf *m0 = *m_head;
4823         struct tx_bd *txbd = NULL;
4824         uint16_t vlan_tag = 0, flags = 0;
4825         uint16_t chain_prod, chain_prod_start, prod;
4826         uint32_t prod_bseq;
4827         int i, error, maxsegs, nsegs;
4828 #ifdef BCE_DEBUG
4829         uint16_t debug_prod;
4830 #endif
4831
4832         /* Transfer any checksum offload flags to the bd. */
4833         if (m0->m_pkthdr.csum_flags) {
4834                 if (m0->m_pkthdr.csum_flags & CSUM_IP)
4835                         flags |= TX_BD_FLAGS_IP_CKSUM;
4836                 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
4837                         flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4838         }
4839
4840         /* Transfer any VLAN tags to the bd. */
4841         if (m0->m_flags & M_VLANTAG) {
4842                 flags |= TX_BD_FLAGS_VLAN_TAG;
4843                 vlan_tag = m0->m_pkthdr.ether_vlantag;
4844         }
4845
4846         prod = sc->tx_prod;
4847         chain_prod_start = chain_prod = TX_CHAIN_IDX(prod);
4848
4849         /* Map the mbuf into DMAable memory. */
4850         map = sc->tx_mbuf_map[chain_prod_start];
4851
4852         maxsegs = sc->max_tx_bd - sc->used_tx_bd;
4853         KASSERT(maxsegs >= BCE_TX_SPARE_SPACE,
4854                 ("not enough segements %d\n", maxsegs));
4855         if (maxsegs > BCE_MAX_SEGMENTS)
4856                 maxsegs = BCE_MAX_SEGMENTS;
4857
4858         /* Map the mbuf into our DMA address space. */
4859         error = bus_dmamap_load_mbuf_defrag(sc->tx_mbuf_tag, map, m_head,
4860                         segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
4861         if (error)
4862                 goto back;
4863         bus_dmamap_sync(sc->tx_mbuf_tag, map, BUS_DMASYNC_PREWRITE);
4864
4865         /* Reset m0 */
4866         m0 = *m_head;
4867
4868         /* prod points to an empty tx_bd at this point. */
4869         prod_bseq  = sc->tx_prod_bseq;
4870
4871 #ifdef BCE_DEBUG
4872         debug_prod = chain_prod;
4873 #endif
4874
4875         DBPRINT(sc, BCE_INFO_SEND,
4876                 "%s(): Start: prod = 0x%04X, chain_prod = %04X, "
4877                 "prod_bseq = 0x%08X\n",
4878                 __func__, prod, chain_prod, prod_bseq);
4879
4880         /*
4881          * Cycle through each mbuf segment that makes up
4882          * the outgoing frame, gathering the mapping info
4883          * for that segment and creating a tx_bd to for
4884          * the mbuf.
4885          */
4886         for (i = 0; i < nsegs; i++) {
4887                 chain_prod = TX_CHAIN_IDX(prod);
4888                 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)];
4889
4890                 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr));
4891                 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr));
4892                 txbd->tx_bd_mss_nbytes = htole16(segs[i].ds_len);
4893                 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
4894                 txbd->tx_bd_flags = htole16(flags);
4895                 prod_bseq += segs[i].ds_len;
4896                 if (i == 0)
4897                         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
4898                 prod = NEXT_TX_BD(prod);
4899         }
4900
4901         /* Set the END flag on the last TX buffer descriptor. */
4902         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
4903
4904         DBRUN(BCE_EXCESSIVE_SEND,
4905               bce_dump_tx_chain(sc, debug_prod, nsegs));
4906
4907         DBPRINT(sc, BCE_INFO_SEND,
4908                 "%s(): End: prod = 0x%04X, chain_prod = %04X, "
4909                 "prod_bseq = 0x%08X\n",
4910                 __func__, prod, chain_prod, prod_bseq);
4911
4912         /*
4913          * Ensure that the mbuf pointer for this transmission
4914          * is placed at the array index of the last
4915          * descriptor in this chain.  This is done
4916          * because a single map is used for all
4917          * segments of the mbuf and we don't want to
4918          * unload the map before all of the segments
4919          * have been freed.
4920          */
4921         sc->tx_mbuf_ptr[chain_prod] = m0;
4922
4923         tmp_map = sc->tx_mbuf_map[chain_prod];
4924         sc->tx_mbuf_map[chain_prod] = map;
4925         sc->tx_mbuf_map[chain_prod_start] = tmp_map;
4926
4927         sc->used_tx_bd += nsegs;
4928
4929         /* Update some debug statistic counters */
4930         DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
4931                 sc->tx_hi_watermark = sc->used_tx_bd);
4932         DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
4933         DBRUNIF(1, sc->tx_mbuf_alloc++);
4934
4935         DBRUN(BCE_VERBOSE_SEND,
4936               bce_dump_tx_mbuf_chain(sc, chain_prod, nsegs));
4937
4938         /* prod points to the next free tx_bd at this point. */
4939         sc->tx_prod = prod;
4940         sc->tx_prod_bseq = prod_bseq;
4941 back:
4942         if (error) {
4943                 m_freem(*m_head);
4944                 *m_head = NULL;
4945         }
4946         return error;
4947 }
4948
4949
4950 /****************************************************************************/
4951 /* Main transmit routine when called from another routine with a lock.      */
4952 /*                                                                          */
4953 /* Returns:                                                                 */
4954 /*   Nothing.                                                               */
4955 /****************************************************************************/
4956 static void
4957 bce_start(struct ifnet *ifp)
4958 {
4959         struct bce_softc *sc = ifp->if_softc;
4960         int count = 0;
4961
4962         ASSERT_SERIALIZED(ifp->if_serializer);
4963
4964         /* If there's no link or the transmit queue is empty then just exit. */
4965         if (!sc->bce_link) {
4966                 ifq_purge(&ifp->if_snd);
4967                 return;
4968         }
4969
4970         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
4971                 return;
4972
4973         DBPRINT(sc, BCE_INFO_SEND,
4974                 "%s(): Start: tx_prod = 0x%04X, tx_chain_prod = %04zX, "
4975                 "tx_prod_bseq = 0x%08X\n",
4976                 __func__,
4977                 sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq);
4978
4979         for (;;) {
4980                 struct mbuf *m_head;
4981
4982                 /*
4983                  * We keep BCE_TX_SPARE_SPACE entries, so bce_encap() is
4984                  * unlikely to fail.
4985                  */
4986                 if (sc->max_tx_bd - sc->used_tx_bd < BCE_TX_SPARE_SPACE) {
4987                         ifp->if_flags |= IFF_OACTIVE;
4988                         break;
4989                 }
4990
4991                 /* Check for any frames to send. */
4992                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
4993                 if (m_head == NULL)
4994                         break;
4995
4996                 /*
4997                  * Pack the data into the transmit ring. If we
4998                  * don't have room, place the mbuf back at the
4999                  * head of the queue and set the OACTIVE flag
5000                  * to wait for the NIC to drain the chain.
5001                  */
5002                 if (bce_encap(sc, &m_head)) {
5003                         ifp->if_oerrors++;
5004                         if (sc->used_tx_bd == 0) {
5005                                 continue;
5006                         } else {
5007                                 ifp->if_flags |= IFF_OACTIVE;
5008                                 break;
5009                         }
5010                 }
5011
5012                 count++;
5013
5014                 /* Send a copy of the frame to any BPF listeners. */
5015                 ETHER_BPF_MTAP(ifp, m_head);
5016         }
5017
5018         if (count == 0) {
5019                 /* no packets were dequeued */
5020                 DBPRINT(sc, BCE_VERBOSE_SEND,
5021                         "%s(): No packets were dequeued\n", __func__);
5022                 return;
5023         }
5024
5025         DBPRINT(sc, BCE_INFO_SEND,
5026                 "%s(): End: tx_prod = 0x%04X, tx_chain_prod = 0x%04zX, "
5027                 "tx_prod_bseq = 0x%08X\n",
5028                 __func__,
5029                 sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq);
5030
5031         REG_WR(sc, BCE_MQ_COMMAND,
5032             REG_RD(sc, BCE_MQ_COMMAND) | BCE_MQ_COMMAND_NO_MAP_ERROR);
5033
5034         /* Start the transmit. */
5035         REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod);
5036         REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq);
5037
5038         /* Set the tx timeout. */
5039         ifp->if_timer = BCE_TX_TIMEOUT;
5040 }
5041
5042
5043 /****************************************************************************/
5044 /* Handles any IOCTL calls from the operating system.                       */
5045 /*                                                                          */
5046 /* Returns:                                                                 */
5047 /*   0 for success, positive value for failure.                             */
5048 /****************************************************************************/
5049 static int
5050 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
5051 {
5052         struct bce_softc *sc = ifp->if_softc;
5053         struct ifreq *ifr = (struct ifreq *)data;
5054         struct mii_data *mii;
5055         int mask, error = 0;
5056
5057         ASSERT_SERIALIZED(ifp->if_serializer);
5058
5059         switch(command) {
5060         case SIOCSIFMTU:
5061                 /* Check that the MTU setting is supported. */
5062                 if (ifr->ifr_mtu < BCE_MIN_MTU ||
5063 #ifdef notyet
5064                     ifr->ifr_mtu > BCE_MAX_JUMBO_MTU
5065 #else
5066                     ifr->ifr_mtu > ETHERMTU
5067 #endif
5068                    ) {
5069                         error = EINVAL;
5070                         break;
5071                 }
5072
5073                 DBPRINT(sc, BCE_INFO, "Setting new MTU of %d\n", ifr->ifr_mtu);
5074
5075                 ifp->if_mtu = ifr->ifr_mtu;
5076                 ifp->if_flags &= ~IFF_RUNNING;  /* Force reinitialize */
5077                 bce_init(sc);
5078                 break;
5079
5080         case SIOCSIFFLAGS:
5081                 if (ifp->if_flags & IFF_UP) {
5082                         if (ifp->if_flags & IFF_RUNNING) {
5083                                 mask = ifp->if_flags ^ sc->bce_if_flags;
5084
5085                                 if (mask & (IFF_PROMISC | IFF_ALLMULTI))
5086                                         bce_set_rx_mode(sc);
5087                         } else {
5088                                 bce_init(sc);
5089                         }
5090                 } else if (ifp->if_flags & IFF_RUNNING) {
5091                         bce_stop(sc);
5092
5093                         /* If MFW is running, restart the controller a bit. */
5094                         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5095                                 bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
5096                                 bce_chipinit(sc);
5097                                 bce_mgmt_init(sc);
5098                         }
5099                 }
5100                 sc->bce_if_flags = ifp->if_flags;
5101                 break;
5102
5103         case SIOCADDMULTI:
5104         case SIOCDELMULTI:
5105                 if (ifp->if_flags & IFF_RUNNING)
5106                         bce_set_rx_mode(sc);
5107                 break;
5108
5109         case SIOCSIFMEDIA:
5110         case SIOCGIFMEDIA:
5111                 DBPRINT(sc, BCE_VERBOSE, "bce_phy_flags = 0x%08X\n",
5112                         sc->bce_phy_flags);
5113                 DBPRINT(sc, BCE_VERBOSE, "Copper media set/get\n");
5114
5115                 mii = device_get_softc(sc->bce_miibus);
5116                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
5117                 break;
5118
5119         case SIOCSIFCAP:
5120                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
5121                 DBPRINT(sc, BCE_INFO, "Received SIOCSIFCAP = 0x%08X\n",
5122                         (uint32_t) mask);
5123
5124                 if (mask & IFCAP_HWCSUM) {
5125                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
5126                         if (IFCAP_HWCSUM & ifp->if_capenable)
5127                                 ifp->if_hwassist = BCE_IF_HWASSIST;
5128                         else
5129                                 ifp->if_hwassist = 0;
5130                 }
5131                 break;
5132
5133         default:
5134                 error = ether_ioctl(ifp, command, data);
5135                 break;
5136         }
5137         return error;
5138 }
5139
5140
5141 /****************************************************************************/
5142 /* Transmit timeout handler.                                                */
5143 /*                                                                          */
5144 /* Returns:                                                                 */
5145 /*   Nothing.                                                               */
5146 /****************************************************************************/
5147 static void
5148 bce_watchdog(struct ifnet *ifp)
5149 {
5150         struct bce_softc *sc = ifp->if_softc;
5151
5152         ASSERT_SERIALIZED(ifp->if_serializer);
5153
5154         DBRUN(BCE_VERBOSE_SEND,
5155               bce_dump_driver_state(sc);
5156               bce_dump_status_block(sc));
5157
5158         /*
5159          * If we are in this routine because of pause frames, then
5160          * don't reset the hardware.
5161          */
5162         if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED)
5163                 return;
5164
5165         if_printf(ifp, "Watchdog timeout occurred, resetting!\n");
5166
5167         /* DBRUN(BCE_FATAL, bce_breakpoint(sc)); */
5168
5169         ifp->if_flags &= ~IFF_RUNNING;  /* Force reinitialize */
5170         bce_init(sc);
5171
5172         ifp->if_oerrors++;
5173
5174         if (!ifq_is_empty(&ifp->if_snd))
5175                 if_devstart(ifp);
5176 }
5177
5178
5179 #ifdef DEVICE_POLLING
5180
5181 static void
5182 bce_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
5183 {
5184         struct bce_softc *sc = ifp->if_softc;
5185         struct status_block *sblk = sc->status_block;
5186         uint16_t hw_tx_cons, hw_rx_cons;
5187
5188         ASSERT_SERIALIZED(ifp->if_serializer);
5189
5190         switch (cmd) {
5191         case POLL_REGISTER:
5192                 bce_disable_intr(sc);
5193
5194                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5195                        (1 << 16) | sc->bce_rx_quick_cons_trip);
5196                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5197                        (1 << 16) | sc->bce_tx_quick_cons_trip);
5198                 return;
5199         case POLL_DEREGISTER:
5200                 bce_enable_intr(sc, 1);
5201
5202                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5203                        (sc->bce_tx_quick_cons_trip_int << 16) |
5204                        sc->bce_tx_quick_cons_trip);
5205                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5206                        (sc->bce_rx_quick_cons_trip_int << 16) |
5207                        sc->bce_rx_quick_cons_trip);
5208                 return;
5209         default:
5210                 break;
5211         }
5212
5213         if (cmd == POLL_AND_CHECK_STATUS) {
5214                 uint32_t status_attn_bits;
5215
5216                 status_attn_bits = sblk->status_attn_bits;
5217
5218                 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
5219                         if_printf(ifp,
5220                         "Simulating unexpected status attention bit set.");
5221                         status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
5222
5223                 /* Was it a link change interrupt? */
5224                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5225                     (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
5226                         bce_phy_intr(sc);
5227
5228                 /* Clear any transient status updates during link state change. */
5229                 REG_WR(sc, BCE_HC_COMMAND,
5230                     sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5231                 REG_RD(sc, BCE_HC_COMMAND);
5232
5233                 /*
5234                  * If any other attention is asserted then
5235                  * the chip is toast.
5236                  */
5237                 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5238                      (sblk->status_attn_bits_ack &
5239                       ~STATUS_ATTN_BITS_LINK_STATE)) {
5240                         DBRUN(1, sc->unexpected_attentions++);
5241
5242                         if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5243                                   sblk->status_attn_bits);
5244
5245                         DBRUN(BCE_FATAL,
5246                         if (bce_debug_unexpected_attention == 0)
5247                                 bce_breakpoint(sc));
5248
5249                         bce_init(sc);
5250                         return;
5251                 }
5252         }
5253
5254         hw_rx_cons = bce_get_hw_rx_cons(sc);
5255         hw_tx_cons = bce_get_hw_tx_cons(sc);
5256
5257         /* Check for any completed RX frames. */
5258         if (hw_rx_cons != sc->hw_rx_cons)
5259                 bce_rx_intr(sc, count);
5260
5261         /* Check for any completed TX frames. */
5262         if (hw_tx_cons != sc->hw_tx_cons)
5263                 bce_tx_intr(sc);
5264
5265         /* Check for new frames to transmit. */
5266         if (!ifq_is_empty(&ifp->if_snd))
5267                 if_devstart(ifp);
5268 }
5269
5270 #endif  /* DEVICE_POLLING */
5271
5272
5273 /*
5274  * Interrupt handler.
5275  */
5276 /****************************************************************************/
5277 /* Main interrupt entry point.  Verifies that the controller generated the  */
5278 /* interrupt and then calls a separate routine for handle the various       */
5279 /* interrupt causes (PHY, TX, RX).                                          */
5280 /*                                                                          */
5281 /* Returns:                                                                 */
5282 /*   0 for success, positive value for failure.                             */
5283 /****************************************************************************/
5284 static void
5285 bce_intr(void *xsc)
5286 {
5287         struct bce_softc *sc = xsc;
5288         struct ifnet *ifp = &sc->arpcom.ac_if;
5289         struct status_block *sblk;
5290         uint16_t hw_rx_cons, hw_tx_cons;
5291
5292         ASSERT_SERIALIZED(ifp->if_serializer);
5293
5294         DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5295         DBRUNIF(1, sc->interrupts_generated++);
5296
5297         sblk = sc->status_block;
5298
5299         /*
5300          * If the hardware status block index matches the last value
5301          * read by the driver and we haven't asserted our interrupt
5302          * then there's nothing to do.
5303          */
5304         if (sblk->status_idx == sc->last_status_idx &&
5305             (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
5306              BCE_PCICFG_MISC_STATUS_INTA_VALUE))
5307                 return;
5308
5309         /* Ack the interrupt and stop others from occuring. */
5310         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5311                BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
5312                BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5313
5314         /* Check if the hardware has finished any work. */
5315         hw_rx_cons = bce_get_hw_rx_cons(sc);
5316         hw_tx_cons = bce_get_hw_tx_cons(sc);
5317
5318         /* Keep processing data as long as there is work to do. */
5319         for (;;) {
5320                 uint32_t status_attn_bits;
5321
5322                 status_attn_bits = sblk->status_attn_bits;
5323
5324                 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
5325                         if_printf(ifp,
5326                         "Simulating unexpected status attention bit set.");
5327                         status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
5328
5329                 /* Was it a link change interrupt? */
5330                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5331                     (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) {
5332                         bce_phy_intr(sc);
5333
5334                         /*
5335                          * Clear any transient status updates during link state
5336                          * change.
5337                          */
5338                         REG_WR(sc, BCE_HC_COMMAND,
5339                             sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5340                         REG_RD(sc, BCE_HC_COMMAND);
5341                 }
5342
5343                 /*
5344                  * If any other attention is asserted then
5345                  * the chip is toast.
5346                  */
5347                 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5348                      (sblk->status_attn_bits_ack &
5349                       ~STATUS_ATTN_BITS_LINK_STATE)) {
5350                         DBRUN(1, sc->unexpected_attentions++);
5351
5352                         if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5353                                   sblk->status_attn_bits);
5354
5355                         DBRUN(BCE_FATAL,
5356                         if (bce_debug_unexpected_attention == 0)
5357                                 bce_breakpoint(sc));
5358
5359                         bce_init(sc);
5360                         return;
5361                 }
5362
5363                 /* Check for any completed RX frames. */
5364                 if (hw_rx_cons != sc->hw_rx_cons)
5365                         bce_rx_intr(sc, -1);
5366
5367                 /* Check for any completed TX frames. */
5368                 if (hw_tx_cons != sc->hw_tx_cons)
5369                         bce_tx_intr(sc);
5370
5371                 /*
5372                  * Save the status block index value
5373                  * for use during the next interrupt.
5374                  */
5375                 sc->last_status_idx = sblk->status_idx;
5376
5377                 /*
5378                  * Prevent speculative reads from getting
5379                  * ahead of the status block.
5380                  */
5381                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
5382                                   BUS_SPACE_BARRIER_READ);
5383
5384                 /*
5385                  * If there's no work left then exit the
5386                  * interrupt service routine.
5387                  */
5388                 hw_rx_cons = bce_get_hw_rx_cons(sc);
5389                 hw_tx_cons = bce_get_hw_tx_cons(sc);
5390                 if ((hw_rx_cons == sc->hw_rx_cons) && (hw_tx_cons == sc->hw_tx_cons))
5391                         break;
5392         }
5393
5394         /* Re-enable interrupts. */
5395         bce_enable_intr(sc, 0);
5396
5397         if (sc->bce_coalchg_mask)
5398                 bce_coal_change(sc);
5399
5400         /* Handle any frames that arrived while handling the interrupt. */
5401         if (!ifq_is_empty(&ifp->if_snd))
5402                 if_devstart(ifp);
5403 }
5404
5405
5406 /****************************************************************************/
5407 /* Programs the various packet receive modes (broadcast and multicast).     */
5408 /*                                                                          */
5409 /* Returns:                                                                 */
5410 /*   Nothing.                                                               */
5411 /****************************************************************************/
5412 static void
5413 bce_set_rx_mode(struct bce_softc *sc)
5414 {
5415         struct ifnet *ifp = &sc->arpcom.ac_if;
5416         struct ifmultiaddr *ifma;
5417         uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
5418         uint32_t rx_mode, sort_mode;
5419         int h, i;
5420
5421         ASSERT_SERIALIZED(ifp->if_serializer);
5422
5423         /* Initialize receive mode default settings. */
5424         rx_mode = sc->rx_mode &
5425                   ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
5426                     BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
5427         sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
5428
5429         /*
5430          * ASF/IPMI/UMP firmware requires that VLAN tag stripping
5431          * be enbled.
5432          */
5433         if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
5434             !(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
5435                 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
5436
5437         /*
5438          * Check for promiscuous, all multicast, or selected
5439          * multicast address filtering.
5440          */
5441         if (ifp->if_flags & IFF_PROMISC) {
5442                 DBPRINT(sc, BCE_INFO, "Enabling promiscuous mode.\n");
5443
5444                 /* Enable promiscuous mode. */
5445                 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
5446                 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
5447         } else if (ifp->if_flags & IFF_ALLMULTI) {
5448                 DBPRINT(sc, BCE_INFO, "Enabling all multicast mode.\n");
5449
5450                 /* Enable all multicast addresses. */
5451                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5452                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5453                                0xffffffff);
5454                 }
5455                 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
5456         } else {
5457                 /* Accept one or more multicast(s). */
5458                 DBPRINT(sc, BCE_INFO, "Enabling selective multicast mode.\n");
5459
5460                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
5461                         if (ifma->ifma_addr->sa_family != AF_LINK)
5462                                 continue;
5463                         h = ether_crc32_le(
5464                             LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
5465                             ETHER_ADDR_LEN) & 0xFF;
5466                         hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
5467                 }
5468
5469                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5470                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5471                                hashes[i]);
5472                 }
5473                 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
5474         }
5475
5476         /* Only make changes if the recive mode has actually changed. */
5477         if (rx_mode != sc->rx_mode) {
5478                 DBPRINT(sc, BCE_VERBOSE, "Enabling new receive mode: 0x%08X\n",
5479                         rx_mode);
5480
5481                 sc->rx_mode = rx_mode;
5482                 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
5483         }
5484
5485         /* Disable and clear the exisitng sort before enabling a new sort. */
5486         REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
5487         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
5488         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
5489 }
5490
5491
5492 /****************************************************************************/
5493 /* Called periodically to updates statistics from the controllers           */
5494 /* statistics block.                                                        */
5495 /*                                                                          */
5496 /* Returns:                                                                 */
5497 /*   Nothing.                                                               */
5498 /****************************************************************************/
5499 static void
5500 bce_stats_update(struct bce_softc *sc)
5501 {
5502         struct ifnet *ifp = &sc->arpcom.ac_if;
5503         struct statistics_block *stats = sc->stats_block;
5504
5505         DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5506
5507         ASSERT_SERIALIZED(ifp->if_serializer);
5508
5509         /*
5510          * Certain controllers don't report carrier sense errors correctly.
5511          * See errata E11_5708CA0_1165.
5512          */
5513         if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
5514             !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) {
5515                 ifp->if_oerrors +=
5516                         (u_long)stats->stat_Dot3StatsCarrierSenseErrors;
5517         }
5518
5519         /*
5520          * Update the sysctl statistics from the hardware statistics.
5521          */
5522         sc->stat_IfHCInOctets =
5523                 ((uint64_t)stats->stat_IfHCInOctets_hi << 32) +
5524                  (uint64_t)stats->stat_IfHCInOctets_lo;
5525
5526         sc->stat_IfHCInBadOctets =
5527                 ((uint64_t)stats->stat_IfHCInBadOctets_hi << 32) +
5528                  (uint64_t)stats->stat_IfHCInBadOctets_lo;
5529
5530         sc->stat_IfHCOutOctets =
5531                 ((uint64_t)stats->stat_IfHCOutOctets_hi << 32) +
5532                  (uint64_t)stats->stat_IfHCOutOctets_lo;
5533
5534         sc->stat_IfHCOutBadOctets =
5535                 ((uint64_t)stats->stat_IfHCOutBadOctets_hi << 32) +
5536                  (uint64_t)stats->stat_IfHCOutBadOctets_lo;
5537
5538         sc->stat_IfHCInUcastPkts =
5539                 ((uint64_t)stats->stat_IfHCInUcastPkts_hi << 32) +
5540                  (uint64_t)stats->stat_IfHCInUcastPkts_lo;
5541
5542         sc->stat_IfHCInMulticastPkts =
5543                 ((uint64_t)stats->stat_IfHCInMulticastPkts_hi << 32) +
5544                  (uint64_t)stats->stat_IfHCInMulticastPkts_lo;
5545
5546         sc->stat_IfHCInBroadcastPkts =
5547                 ((uint64_t)stats->stat_IfHCInBroadcastPkts_hi << 32) +
5548                  (uint64_t)stats->stat_IfHCInBroadcastPkts_lo;
5549
5550         sc->stat_IfHCOutUcastPkts =
5551                 ((uint64_t)stats->stat_IfHCOutUcastPkts_hi << 32) +
5552                  (uint64_t)stats->stat_IfHCOutUcastPkts_lo;
5553
5554         sc->stat_IfHCOutMulticastPkts =
5555                 ((uint64_t)stats->stat_IfHCOutMulticastPkts_hi << 32) +
5556                  (uint64_t)stats->stat_IfHCOutMulticastPkts_lo;
5557
5558         sc->stat_IfHCOutBroadcastPkts =
5559                 ((uint64_t)stats->stat_IfHCOutBroadcastPkts_hi << 32) +
5560                  (uint64_t)stats->stat_IfHCOutBroadcastPkts_lo;
5561
5562         sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
5563                 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
5564
5565         sc->stat_Dot3StatsCarrierSenseErrors =
5566                 stats->stat_Dot3StatsCarrierSenseErrors;
5567
5568         sc->stat_Dot3StatsFCSErrors =
5569                 stats->stat_Dot3StatsFCSErrors;
5570
5571         sc->stat_Dot3StatsAlignmentErrors =
5572                 stats->stat_Dot3StatsAlignmentErrors;
5573
5574         sc->stat_Dot3StatsSingleCollisionFrames =
5575                 stats->stat_Dot3StatsSingleCollisionFrames;
5576
5577         sc->stat_Dot3StatsMultipleCollisionFrames =
5578                 stats->stat_Dot3StatsMultipleCollisionFrames;
5579
5580         sc->stat_Dot3StatsDeferredTransmissions =
5581                 stats->stat_Dot3StatsDeferredTransmissions;
5582
5583         sc->stat_Dot3StatsExcessiveCollisions =
5584                 stats->stat_Dot3StatsExcessiveCollisions;
5585
5586         sc->stat_Dot3StatsLateCollisions =
5587                 stats->stat_Dot3StatsLateCollisions;
5588
5589         sc->stat_EtherStatsCollisions =
5590                 stats->stat_EtherStatsCollisions;
5591
5592         sc->stat_EtherStatsFragments =
5593                 stats->stat_EtherStatsFragments;
5594
5595         sc->stat_EtherStatsJabbers =
5596                 stats->stat_EtherStatsJabbers;
5597
5598         sc->stat_EtherStatsUndersizePkts =
5599                 stats->stat_EtherStatsUndersizePkts;
5600
5601         sc->stat_EtherStatsOverrsizePkts =
5602                 stats->stat_EtherStatsOverrsizePkts;
5603
5604         sc->stat_EtherStatsPktsRx64Octets =
5605                 stats->stat_EtherStatsPktsRx64Octets;
5606
5607         sc->stat_EtherStatsPktsRx65Octetsto127Octets =
5608                 stats->stat_EtherStatsPktsRx65Octetsto127Octets;
5609
5610         sc->stat_EtherStatsPktsRx128Octetsto255Octets =
5611                 stats->stat_EtherStatsPktsRx128Octetsto255Octets;
5612
5613         sc->stat_EtherStatsPktsRx256Octetsto511Octets =
5614                 stats->stat_EtherStatsPktsRx256Octetsto511Octets;
5615
5616         sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
5617                 stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
5618
5619         sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
5620                 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
5621
5622         sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
5623                 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
5624
5625         sc->stat_EtherStatsPktsTx64Octets =
5626                 stats->stat_EtherStatsPktsTx64Octets;
5627
5628         sc->stat_EtherStatsPktsTx65Octetsto127Octets =
5629                 stats->stat_EtherStatsPktsTx65Octetsto127Octets;
5630
5631         sc->stat_EtherStatsPktsTx128Octetsto255Octets =
5632                 stats->stat_EtherStatsPktsTx128Octetsto255Octets;
5633
5634         sc->stat_EtherStatsPktsTx256Octetsto511Octets =
5635                 stats->stat_EtherStatsPktsTx256Octetsto511Octets;
5636
5637         sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
5638                 stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
5639
5640         sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
5641                 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
5642
5643         sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
5644                 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
5645
5646         sc->stat_XonPauseFramesReceived =
5647                 stats->stat_XonPauseFramesReceived;
5648
5649         sc->stat_XoffPauseFramesReceived =
5650                 stats->stat_XoffPauseFramesReceived;
5651
5652         sc->stat_OutXonSent =
5653                 stats->stat_OutXonSent;
5654
5655         sc->stat_OutXoffSent =
5656                 stats->stat_OutXoffSent;
5657
5658         sc->stat_FlowControlDone =
5659                 stats->stat_FlowControlDone;
5660
5661         sc->stat_MacControlFramesReceived =
5662                 stats->stat_MacControlFramesReceived;
5663
5664         sc->stat_XoffStateEntered =
5665                 stats->stat_XoffStateEntered;
5666
5667         sc->stat_IfInFramesL2FilterDiscards =
5668                 stats->stat_IfInFramesL2FilterDiscards;
5669
5670         sc->stat_IfInRuleCheckerDiscards =
5671                 stats->stat_IfInRuleCheckerDiscards;
5672
5673         sc->stat_IfInFTQDiscards =
5674                 stats->stat_IfInFTQDiscards;
5675
5676         sc->stat_IfInMBUFDiscards =
5677                 stats->stat_IfInMBUFDiscards;
5678
5679         sc->stat_IfInRuleCheckerP4Hit =
5680                 stats->stat_IfInRuleCheckerP4Hit;
5681
5682         sc->stat_CatchupInRuleCheckerDiscards =
5683                 stats->stat_CatchupInRuleCheckerDiscards;
5684
5685         sc->stat_CatchupInFTQDiscards =
5686                 stats->stat_CatchupInFTQDiscards;
5687
5688         sc->stat_CatchupInMBUFDiscards =
5689                 stats->stat_CatchupInMBUFDiscards;
5690
5691         sc->stat_CatchupInRuleCheckerP4Hit =
5692                 stats->stat_CatchupInRuleCheckerP4Hit;
5693
5694         sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
5695
5696         /*
5697          * Update the interface statistics from the
5698          * hardware statistics.
5699          */
5700         ifp->if_collisions = (u_long)sc->stat_EtherStatsCollisions;
5701
5702         ifp->if_ierrors = (u_long)sc->stat_EtherStatsUndersizePkts +
5703             (u_long)sc->stat_EtherStatsOverrsizePkts +
5704             (u_long)sc->stat_IfInMBUFDiscards +
5705             (u_long)sc->stat_Dot3StatsAlignmentErrors +
5706             (u_long)sc->stat_Dot3StatsFCSErrors +
5707             (u_long)sc->stat_IfInRuleCheckerDiscards +
5708             (u_long)sc->stat_IfInFTQDiscards +
5709             (u_long)sc->com_no_buffers;
5710
5711         ifp->if_oerrors =
5712             (u_long)sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
5713             (u_long)sc->stat_Dot3StatsExcessiveCollisions +
5714             (u_long)sc->stat_Dot3StatsLateCollisions;
5715
5716         DBPRINT(sc, BCE_EXCESSIVE, "Exiting %s()\n", __func__);
5717 }
5718
5719
5720 /****************************************************************************/
5721 /* Periodic function to notify the bootcode that the driver is still        */
5722 /* present.                                                                 */
5723 /*                                                                          */
5724 /* Returns:                                                                 */
5725 /*   Nothing.                                                               */
5726 /****************************************************************************/
5727 static void
5728 bce_pulse(void *xsc)
5729 {
5730         struct bce_softc *sc = xsc;
5731         struct ifnet *ifp = &sc->arpcom.ac_if;
5732         uint32_t msg;
5733
5734         lwkt_serialize_enter(ifp->if_serializer);
5735
5736         /* Tell the firmware that the driver is still running. */
5737         msg = (uint32_t)++sc->bce_fw_drv_pulse_wr_seq;
5738         bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg);
5739
5740         /* Schedule the next pulse. */
5741         callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc);
5742
5743         lwkt_serialize_exit(ifp->if_serializer);
5744 }
5745
5746
5747 /****************************************************************************/
5748 /* Periodic function to perform maintenance tasks.                          */
5749 /*                                                                          */
5750 /* Returns:                                                                 */
5751 /*   Nothing.                                                               */
5752 /****************************************************************************/
5753 static void
5754 bce_tick_serialized(struct bce_softc *sc)
5755 {
5756         struct ifnet *ifp = &sc->arpcom.ac_if;
5757         struct mii_data *mii;
5758
5759         ASSERT_SERIALIZED(ifp->if_serializer);
5760
5761         /* Update the statistics from the hardware statistics block. */
5762         bce_stats_update(sc);
5763
5764         /* Schedule the next tick. */
5765         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
5766
5767         /* If link is up already up then we're done. */
5768         if (sc->bce_link)
5769                 return;
5770
5771         mii = device_get_softc(sc->bce_miibus);
5772         mii_tick(mii);
5773
5774         /* Check if the link has come up. */
5775         if ((mii->mii_media_status & IFM_ACTIVE) &&
5776             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
5777                 sc->bce_link++;
5778                 /* Now that link is up, handle any outstanding TX traffic. */
5779                 if (!ifq_is_empty(&ifp->if_snd))
5780                         if_devstart(ifp);
5781         }
5782 }
5783
5784
5785 static void
5786 bce_tick(void *xsc)
5787 {
5788         struct bce_softc *sc = xsc;
5789         struct ifnet *ifp = &sc->arpcom.ac_if;
5790
5791         lwkt_serialize_enter(ifp->if_serializer);
5792         bce_tick_serialized(sc);
5793         lwkt_serialize_exit(ifp->if_serializer);
5794 }
5795
5796
5797 #ifdef BCE_DEBUG
5798 /****************************************************************************/
5799 /* Allows the driver state to be dumped through the sysctl interface.       */
5800 /*                                                                          */
5801 /* Returns:                                                                 */
5802 /*   0 for success, positive value for failure.                             */
5803 /****************************************************************************/
5804 static int
5805 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
5806 {
5807         int error;
5808         int result;
5809         struct bce_softc *sc;
5810
5811         result = -1;
5812         error = sysctl_handle_int(oidp, &result, 0, req);
5813
5814         if (error || !req->newptr)
5815                 return (error);
5816
5817         if (result == 1) {
5818                 sc = (struct bce_softc *)arg1;
5819                 bce_dump_driver_state(sc);
5820         }
5821
5822         return error;
5823 }
5824
5825
5826 /****************************************************************************/
5827 /* Allows the hardware state to be dumped through the sysctl interface.     */
5828 /*                                                                          */
5829 /* Returns:                                                                 */
5830 /*   0 for success, positive value for failure.                             */
5831 /****************************************************************************/
5832 static int
5833 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
5834 {
5835         int error;
5836         int result;
5837         struct bce_softc *sc;
5838
5839         result = -1;
5840         error = sysctl_handle_int(oidp, &result, 0, req);
5841
5842         if (error || !req->newptr)
5843                 return (error);
5844
5845         if (result == 1) {
5846                 sc = (struct bce_softc *)arg1;
5847                 bce_dump_hw_state(sc);
5848         }
5849
5850         return error;
5851 }
5852
5853
5854 /****************************************************************************/
5855 /* Provides a sysctl interface to allows dumping the RX chain.              */
5856 /*                                                                          */
5857 /* Returns:                                                                 */
5858 /*   0 for success, positive value for failure.                             */
5859 /****************************************************************************/
5860 static int
5861 bce_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS)
5862 {
5863         int error;
5864         int result;
5865         struct bce_softc *sc;
5866
5867         result = -1;
5868         error = sysctl_handle_int(oidp, &result, 0, req);
5869
5870         if (error || !req->newptr)
5871                 return (error);
5872
5873         if (result == 1) {
5874                 sc = (struct bce_softc *)arg1;
5875                 bce_dump_rx_chain(sc, 0, USABLE_RX_BD);
5876         }
5877
5878         return error;
5879 }
5880
5881
5882 /****************************************************************************/
5883 /* Provides a sysctl interface to allows dumping the TX chain.              */
5884 /*                                                                          */
5885 /* Returns:                                                                 */
5886 /*   0 for success, positive value for failure.                             */
5887 /****************************************************************************/
5888 static int
5889 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
5890 {
5891         int error;
5892         int result;
5893         struct bce_softc *sc;
5894
5895         result = -1;
5896         error = sysctl_handle_int(oidp, &result, 0, req);
5897
5898         if (error || !req->newptr)
5899                 return (error);
5900
5901         if (result == 1) {
5902                 sc = (struct bce_softc *)arg1;
5903                 bce_dump_tx_chain(sc, 0, USABLE_TX_BD);
5904         }
5905
5906         return error;
5907 }
5908
5909
5910 /****************************************************************************/
5911 /* Provides a sysctl interface to allow reading arbitrary registers in the  */
5912 /* device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                            */
5913 /*                                                                          */
5914 /* Returns:                                                                 */
5915 /*   0 for success, positive value for failure.                             */
5916 /****************************************************************************/
5917 static int
5918 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
5919 {
5920         struct bce_softc *sc;
5921         int error;
5922         uint32_t val, result;
5923
5924         result = -1;
5925         error = sysctl_handle_int(oidp, &result, 0, req);
5926         if (error || (req->newptr == NULL))
5927                 return (error);
5928
5929         /* Make sure the register is accessible. */
5930         if (result < 0x8000) {
5931                 sc = (struct bce_softc *)arg1;
5932                 val = REG_RD(sc, result);
5933                 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
5934                           result, val);
5935         } else if (result < 0x0280000) {
5936                 sc = (struct bce_softc *)arg1;
5937                 val = REG_RD_IND(sc, result);
5938                 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
5939                           result, val);
5940         }
5941         return (error);
5942 }
5943
5944
5945 /****************************************************************************/
5946 /* Provides a sysctl interface to allow reading arbitrary PHY registers in  */
5947 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */
5948 /*                                                                          */
5949 /* Returns:                                                                 */
5950 /*   0 for success, positive value for failure.                             */
5951 /****************************************************************************/
5952 static int
5953 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
5954 {
5955         struct bce_softc *sc;
5956         device_t dev;
5957         int error, result;
5958         uint16_t val;
5959
5960         result = -1;
5961         error = sysctl_handle_int(oidp, &result, 0, req);
5962         if (error || (req->newptr == NULL))
5963                 return (error);
5964
5965         /* Make sure the register is accessible. */
5966         if (result < 0x20) {
5967                 sc = (struct bce_softc *)arg1;
5968                 dev = sc->bce_dev;
5969                 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
5970                 if_printf(&sc->arpcom.ac_if,
5971                           "phy 0x%02X = 0x%04X\n", result, val);
5972         }
5973         return (error);
5974 }
5975
5976
5977 /****************************************************************************/
5978 /* Provides a sysctl interface to forcing the driver to dump state and      */
5979 /* enter the debugger.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                */
5980 /*                                                                          */
5981 /* Returns:                                                                 */
5982 /*   0 for success, positive value for failure.                             */
5983 /****************************************************************************/
5984 static int
5985 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
5986 {
5987         int error;
5988         int result;
5989         struct bce_softc *sc;
5990
5991         result = -1;
5992         error = sysctl_handle_int(oidp, &result, 0, req);
5993
5994         if (error || !req->newptr)
5995                 return (error);
5996
5997         if (result == 1) {
5998                 sc = (struct bce_softc *)arg1;
5999                 bce_breakpoint(sc);
6000         }
6001
6002         return error;
6003 }
6004 #endif
6005
6006
6007 /****************************************************************************/
6008 /* Adds any sysctl parameters for tuning or debugging purposes.             */
6009 /*                                                                          */
6010 /* Returns:                                                                 */
6011 /*   0 for success, positive value for failure.                             */
6012 /****************************************************************************/
6013 static void
6014 bce_add_sysctls(struct bce_softc *sc)
6015 {
6016         struct sysctl_ctx_list *ctx;
6017         struct sysctl_oid_list *children;
6018
6019         sysctl_ctx_init(&sc->bce_sysctl_ctx);
6020         sc->bce_sysctl_tree = SYSCTL_ADD_NODE(&sc->bce_sysctl_ctx,
6021                                               SYSCTL_STATIC_CHILDREN(_hw),
6022                                               OID_AUTO,
6023                                               device_get_nameunit(sc->bce_dev),
6024                                               CTLFLAG_RD, 0, "");
6025         if (sc->bce_sysctl_tree == NULL) {
6026                 device_printf(sc->bce_dev, "can't add sysctl node\n");
6027                 return;
6028         }
6029
6030         ctx = &sc->bce_sysctl_ctx;
6031         children = SYSCTL_CHILDREN(sc->bce_sysctl_tree);
6032
6033         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds_int",
6034                         CTLTYPE_INT | CTLFLAG_RW,
6035                         sc, 0, bce_sysctl_tx_bds_int, "I",
6036                         "Send max coalesced BD count during interrupt");
6037         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds",
6038                         CTLTYPE_INT | CTLFLAG_RW,
6039                         sc, 0, bce_sysctl_tx_bds, "I",
6040                         "Send max coalesced BD count");
6041         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks_int",
6042                         CTLTYPE_INT | CTLFLAG_RW,
6043                         sc, 0, bce_sysctl_tx_ticks_int, "I",
6044                         "Send coalescing ticks during interrupt");
6045         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks",
6046                         CTLTYPE_INT | CTLFLAG_RW,
6047                         sc, 0, bce_sysctl_tx_ticks, "I",
6048                         "Send coalescing ticks");
6049
6050         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds_int",
6051                         CTLTYPE_INT | CTLFLAG_RW,
6052                         sc, 0, bce_sysctl_rx_bds_int, "I",
6053                         "Receive max coalesced BD count during interrupt");
6054         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds",
6055                         CTLTYPE_INT | CTLFLAG_RW,
6056                         sc, 0, bce_sysctl_rx_bds, "I",
6057                         "Receive max coalesced BD count");
6058         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks_int",
6059                         CTLTYPE_INT | CTLFLAG_RW,
6060                         sc, 0, bce_sysctl_rx_ticks_int, "I",
6061                         "Receive coalescing ticks during interrupt");
6062         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks",
6063                         CTLTYPE_INT | CTLFLAG_RW,
6064                         sc, 0, bce_sysctl_rx_ticks, "I",
6065                         "Receive coalescing ticks");
6066
6067 #ifdef BCE_DEBUG
6068         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6069                 "rx_low_watermark",
6070                 CTLFLAG_RD, &sc->rx_low_watermark,
6071                 0, "Lowest level of free rx_bd's");
6072
6073         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6074                 "rx_empty_count",
6075                 CTLFLAG_RD, &sc->rx_empty_count,
6076                 0, "Number of times the RX chain was empty");
6077
6078         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6079                 "tx_hi_watermark",
6080                 CTLFLAG_RD, &sc->tx_hi_watermark,
6081                 0, "Highest level of used tx_bd's");
6082
6083         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6084                 "tx_full_count",
6085                 CTLFLAG_RD, &sc->tx_full_count,
6086                 0, "Number of times the TX chain was full");
6087
6088         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6089                 "l2fhdr_status_errors",
6090                 CTLFLAG_RD, &sc->l2fhdr_status_errors,
6091                 0, "l2_fhdr status errors");
6092
6093         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6094                 "unexpected_attentions",
6095                 CTLFLAG_RD, &sc->unexpected_attentions,
6096                 0, "unexpected attentions");
6097
6098         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6099                 "lost_status_block_updates",
6100                 CTLFLAG_RD, &sc->lost_status_block_updates,
6101                 0, "lost status block updates");
6102
6103         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6104                 "mbuf_alloc_failed",
6105                 CTLFLAG_RD, &sc->mbuf_alloc_failed,
6106                 0, "mbuf cluster allocation failures");
6107 #endif
6108
6109         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6110                 "stat_IfHCInOctets",
6111                 CTLFLAG_RD, &sc->stat_IfHCInOctets,
6112                 "Bytes received");
6113
6114         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6115                 "stat_IfHCInBadOctets",
6116                 CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
6117                 "Bad bytes received");
6118
6119         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6120                 "stat_IfHCOutOctets",
6121                 CTLFLAG_RD, &sc->stat_IfHCOutOctets,
6122                 "Bytes sent");
6123
6124         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6125                 "stat_IfHCOutBadOctets",
6126                 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
6127                 "Bad bytes sent");
6128
6129         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6130                 "stat_IfHCInUcastPkts",
6131                 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
6132                 "Unicast packets received");
6133
6134         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6135                 "stat_IfHCInMulticastPkts",
6136                 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
6137                 "Multicast packets received");
6138
6139         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6140                 "stat_IfHCInBroadcastPkts",
6141                 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
6142                 "Broadcast packets received");
6143
6144         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6145                 "stat_IfHCOutUcastPkts",
6146                 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
6147                 "Unicast packets sent");
6148
6149         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6150                 "stat_IfHCOutMulticastPkts",
6151                 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
6152                 "Multicast packets sent");
6153
6154         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6155                 "stat_IfHCOutBroadcastPkts",
6156                 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
6157                 "Broadcast packets sent");
6158
6159         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6160                 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
6161                 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
6162                 0, "Internal MAC transmit errors");
6163
6164         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6165                 "stat_Dot3StatsCarrierSenseErrors",
6166                 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
6167                 0, "Carrier sense errors");
6168
6169         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6170                 "stat_Dot3StatsFCSErrors",
6171                 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
6172                 0, "Frame check sequence errors");
6173
6174         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6175                 "stat_Dot3StatsAlignmentErrors",
6176                 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
6177                 0, "Alignment errors");
6178
6179         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6180                 "stat_Dot3StatsSingleCollisionFrames",
6181                 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
6182                 0, "Single Collision Frames");
6183
6184         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6185                 "stat_Dot3StatsMultipleCollisionFrames",
6186                 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
6187                 0, "Multiple Collision Frames");
6188
6189         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6190                 "stat_Dot3StatsDeferredTransmissions",
6191                 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
6192                 0, "Deferred Transmissions");
6193
6194         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6195                 "stat_Dot3StatsExcessiveCollisions",
6196                 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
6197                 0, "Excessive Collisions");
6198
6199         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6200                 "stat_Dot3StatsLateCollisions",
6201                 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
6202                 0, "Late Collisions");
6203
6204         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6205                 "stat_EtherStatsCollisions",
6206                 CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
6207                 0, "Collisions");
6208
6209         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6210                 "stat_EtherStatsFragments",
6211                 CTLFLAG_RD, &sc->stat_EtherStatsFragments,
6212                 0, "Fragments");
6213
6214         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6215                 "stat_EtherStatsJabbers",
6216                 CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
6217                 0, "Jabbers");
6218
6219         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6220                 "stat_EtherStatsUndersizePkts",
6221                 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
6222                 0, "Undersize packets");
6223
6224         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6225                 "stat_EtherStatsOverrsizePkts",
6226                 CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts,
6227                 0, "stat_EtherStatsOverrsizePkts");
6228
6229         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6230                 "stat_EtherStatsPktsRx64Octets",
6231                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
6232                 0, "Bytes received in 64 byte packets");
6233
6234         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6235                 "stat_EtherStatsPktsRx65Octetsto127Octets",
6236                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
6237                 0, "Bytes received in 65 to 127 byte packets");
6238
6239         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6240                 "stat_EtherStatsPktsRx128Octetsto255Octets",
6241                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
6242                 0, "Bytes received in 128 to 255 byte packets");
6243
6244         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6245                 "stat_EtherStatsPktsRx256Octetsto511Octets",
6246                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
6247                 0, "Bytes received in 256 to 511 byte packets");
6248
6249         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6250                 "stat_EtherStatsPktsRx512Octetsto1023Octets",
6251                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
6252                 0, "Bytes received in 512 to 1023 byte packets");
6253
6254         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6255                 "stat_EtherStatsPktsRx1024Octetsto1522Octets",
6256                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
6257                 0, "Bytes received in 1024 t0 1522 byte packets");
6258
6259         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6260                 "stat_EtherStatsPktsRx1523Octetsto9022Octets",
6261                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
6262                 0, "Bytes received in 1523 to 9022 byte packets");
6263
6264         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6265                 "stat_EtherStatsPktsTx64Octets",
6266                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
6267                 0, "Bytes sent in 64 byte packets");
6268
6269         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6270                 "stat_EtherStatsPktsTx65Octetsto127Octets",
6271                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
6272                 0, "Bytes sent in 65 to 127 byte packets");
6273
6274         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6275                 "stat_EtherStatsPktsTx128Octetsto255Octets",
6276                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
6277                 0, "Bytes sent in 128 to 255 byte packets");
6278
6279         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6280                 "stat_EtherStatsPktsTx256Octetsto511Octets",
6281                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
6282                 0, "Bytes sent in 256 to 511 byte packets");
6283
6284         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6285                 "stat_EtherStatsPktsTx512Octetsto1023Octets",
6286                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
6287                 0, "Bytes sent in 512 to 1023 byte packets");
6288
6289         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6290                 "stat_EtherStatsPktsTx1024Octetsto1522Octets",
6291                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
6292                 0, "Bytes sent in 1024 to 1522 byte packets");
6293
6294         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6295                 "stat_EtherStatsPktsTx1523Octetsto9022Octets",
6296                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
6297                 0, "Bytes sent in 1523 to 9022 byte packets");
6298
6299         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6300                 "stat_XonPauseFramesReceived",
6301                 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
6302                 0, "XON pause frames receved");
6303
6304         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6305                 "stat_XoffPauseFramesReceived",
6306                 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
6307                 0, "XOFF pause frames received");
6308
6309         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6310                 "stat_OutXonSent",
6311                 CTLFLAG_RD, &sc->stat_OutXonSent,
6312                 0, "XON pause frames sent");
6313
6314         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6315                 "stat_OutXoffSent",
6316                 CTLFLAG_RD, &sc->stat_OutXoffSent,
6317                 0, "XOFF pause frames sent");
6318
6319         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6320                 "stat_FlowControlDone",
6321                 CTLFLAG_RD, &sc->stat_FlowControlDone,
6322                 0, "Flow control done");
6323
6324         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6325                 "stat_MacControlFramesReceived",
6326                 CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
6327                 0, "MAC control frames received");
6328
6329         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6330                 "stat_XoffStateEntered",
6331                 CTLFLAG_RD, &sc->stat_XoffStateEntered,
6332                 0, "XOFF state entered");
6333
6334         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6335                 "stat_IfInFramesL2FilterDiscards",
6336                 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
6337                 0, "Received L2 packets discarded");
6338
6339         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6340                 "stat_IfInRuleCheckerDiscards",
6341                 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
6342                 0, "Received packets discarded by rule");
6343
6344         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6345                 "stat_IfInFTQDiscards",
6346                 CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
6347                 0, "Received packet FTQ discards");
6348
6349         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6350                 "stat_IfInMBUFDiscards",
6351                 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
6352                 0, "Received packets discarded due to lack of controller buffer memory");
6353
6354         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6355                 "stat_IfInRuleCheckerP4Hit",
6356                 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
6357                 0, "Received packets rule checker hits");
6358
6359         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6360                 "stat_CatchupInRuleCheckerDiscards",
6361                 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
6362                 0, "Received packets discarded in Catchup path");
6363
6364         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6365                 "stat_CatchupInFTQDiscards",
6366                 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
6367                 0, "Received packets discarded in FTQ in Catchup path");
6368
6369         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6370                 "stat_CatchupInMBUFDiscards",
6371                 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
6372                 0, "Received packets discarded in controller buffer memory in Catchup path");
6373
6374         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6375                 "stat_CatchupInRuleCheckerP4Hit",
6376                 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
6377                 0, "Received packets rule checker hits in Catchup path");
6378
6379         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6380                 "com_no_buffers",
6381                 CTLFLAG_RD, &sc->com_no_buffers,
6382                 0, "Valid packets received but no RX buffers available");
6383
6384 #ifdef BCE_DEBUG
6385         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6386                 "driver_state", CTLTYPE_INT | CTLFLAG_RW,
6387                 (void *)sc, 0,
6388                 bce_sysctl_driver_state, "I", "Drive state information");
6389
6390         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6391                 "hw_state", CTLTYPE_INT | CTLFLAG_RW,
6392                 (void *)sc, 0,
6393                 bce_sysctl_hw_state, "I", "Hardware state information");
6394
6395         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6396                 "dump_rx_chain", CTLTYPE_INT | CTLFLAG_RW,
6397                 (void *)sc, 0,
6398                 bce_sysctl_dump_rx_chain, "I", "Dump rx_bd chain");
6399
6400         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6401                 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
6402                 (void *)sc, 0,
6403                 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
6404
6405         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6406                 "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
6407                 (void *)sc, 0,
6408                 bce_sysctl_breakpoint, "I", "Driver breakpoint");
6409
6410         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6411                 "reg_read", CTLTYPE_INT | CTLFLAG_RW,
6412                 (void *)sc, 0,
6413                 bce_sysctl_reg_read, "I", "Register read");
6414
6415         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6416                 "phy_read", CTLTYPE_INT | CTLFLAG_RW,
6417                 (void *)sc, 0,
6418                 bce_sysctl_phy_read, "I", "PHY register read");
6419
6420 #endif
6421
6422 }
6423
6424
6425 /****************************************************************************/
6426 /* BCE Debug Routines                                                       */
6427 /****************************************************************************/
6428 #ifdef BCE_DEBUG
6429
6430 /****************************************************************************/
6431 /* Freezes the controller to allow for a cohesive state dump.               */
6432 /*                                                                          */
6433 /* Returns:                                                                 */
6434 /*   Nothing.                                                               */
6435 /****************************************************************************/
6436 static void
6437 bce_freeze_controller(struct bce_softc *sc)
6438 {
6439         uint32_t val;
6440
6441         val = REG_RD(sc, BCE_MISC_COMMAND);
6442         val |= BCE_MISC_COMMAND_DISABLE_ALL;
6443         REG_WR(sc, BCE_MISC_COMMAND, val);
6444 }
6445
6446
6447 /****************************************************************************/
6448 /* Unfreezes the controller after a freeze operation.  This may not always  */
6449 /* work and the controller will require a reset!                            */
6450 /*                                                                          */
6451 /* Returns:                                                                 */
6452 /*   Nothing.                                                               */
6453 /****************************************************************************/
6454 static void
6455 bce_unfreeze_controller(struct bce_softc *sc)
6456 {
6457         uint32_t val;
6458
6459         val = REG_RD(sc, BCE_MISC_COMMAND);
6460         val |= BCE_MISC_COMMAND_ENABLE_ALL;
6461         REG_WR(sc, BCE_MISC_COMMAND, val);
6462 }
6463
6464
6465 /****************************************************************************/
6466 /* Prints out information about an mbuf.                                    */
6467 /*                                                                          */
6468 /* Returns:                                                                 */
6469 /*   Nothing.                                                               */
6470 /****************************************************************************/
6471 static void
6472 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
6473 {
6474         struct ifnet *ifp = &sc->arpcom.ac_if;
6475         uint32_t val_hi, val_lo;
6476         struct mbuf *mp = m;
6477
6478         if (m == NULL) {
6479                 /* Index out of range. */
6480                 if_printf(ifp, "mbuf: null pointer\n");
6481                 return;
6482         }
6483
6484         while (mp) {
6485                 val_hi = BCE_ADDR_HI(mp);
6486                 val_lo = BCE_ADDR_LO(mp);
6487                 if_printf(ifp, "mbuf: vaddr = 0x%08X:%08X, m_len = %d, "
6488                           "m_flags = ( ", val_hi, val_lo, mp->m_len);
6489
6490                 if (mp->m_flags & M_EXT)
6491                         kprintf("M_EXT ");
6492                 if (mp->m_flags & M_PKTHDR)
6493                         kprintf("M_PKTHDR ");
6494                 if (mp->m_flags & M_EOR)
6495                         kprintf("M_EOR ");
6496 #ifdef M_RDONLY
6497                 if (mp->m_flags & M_RDONLY)
6498                         kprintf("M_RDONLY ");
6499 #endif
6500
6501                 val_hi = BCE_ADDR_HI(mp->m_data);
6502                 val_lo = BCE_ADDR_LO(mp->m_data);
6503                 kprintf(") m_data = 0x%08X:%08X\n", val_hi, val_lo);
6504
6505                 if (mp->m_flags & M_PKTHDR) {
6506                         if_printf(ifp, "- m_pkthdr: flags = ( ");
6507                         if (mp->m_flags & M_BCAST)
6508                                 kprintf("M_BCAST ");
6509                         if (mp->m_flags & M_MCAST)
6510                                 kprintf("M_MCAST ");
6511                         if (mp->m_flags & M_FRAG)
6512                                 kprintf("M_FRAG ");
6513                         if (mp->m_flags & M_FIRSTFRAG)
6514                                 kprintf("M_FIRSTFRAG ");
6515                         if (mp->m_flags & M_LASTFRAG)
6516                                 kprintf("M_LASTFRAG ");
6517 #ifdef M_VLANTAG
6518                         if (mp->m_flags & M_VLANTAG)
6519                                 kprintf("M_VLANTAG ");
6520 #endif
6521 #ifdef M_PROMISC
6522                         if (mp->m_flags & M_PROMISC)
6523                                 kprintf("M_PROMISC ");
6524 #endif
6525                         kprintf(") csum_flags = ( ");
6526                         if (mp->m_pkthdr.csum_flags & CSUM_IP)
6527                                 kprintf("CSUM_IP ");
6528                         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
6529                                 kprintf("CSUM_TCP ");
6530                         if (mp->m_pkthdr.csum_flags & CSUM_UDP)
6531                                 kprintf("CSUM_UDP ");
6532                         if (mp->m_pkthdr.csum_flags & CSUM_IP_FRAGS)
6533                                 kprintf("CSUM_IP_FRAGS ");
6534                         if (mp->m_pkthdr.csum_flags & CSUM_FRAGMENT)
6535                                 kprintf("CSUM_FRAGMENT ");
6536 #ifdef CSUM_TSO
6537                         if (mp->m_pkthdr.csum_flags & CSUM_TSO)
6538                                 kprintf("CSUM_TSO ");
6539 #endif
6540                         if (mp->m_pkthdr.csum_flags & CSUM_IP_CHECKED)
6541                                 kprintf("CSUM_IP_CHECKED ");
6542                         if (mp->m_pkthdr.csum_flags & CSUM_IP_VALID)
6543                                 kprintf("CSUM_IP_VALID ");
6544                         if (mp->m_pkthdr.csum_flags & CSUM_DATA_VALID)
6545                                 kprintf("CSUM_DATA_VALID ");
6546                         kprintf(")\n");
6547                 }
6548
6549                 if (mp->m_flags & M_EXT) {
6550                         val_hi = BCE_ADDR_HI(mp->m_ext.ext_buf);
6551                         val_lo = BCE_ADDR_LO(mp->m_ext.ext_buf);
6552                         if_printf(ifp, "- m_ext: vaddr = 0x%08X:%08X, "
6553                                   "ext_size = %d\n",
6554                                   val_hi, val_lo, mp->m_ext.ext_size);
6555                 }
6556                 mp = mp->m_next;
6557         }
6558 }
6559
6560
6561 /****************************************************************************/
6562 /* Prints out the mbufs in the TX mbuf chain.                               */
6563 /*                                                                          */
6564 /* Returns:                                                                 */
6565 /*   Nothing.                                                               */
6566 /****************************************************************************/
6567 static void
6568 bce_dump_tx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6569 {
6570         struct ifnet *ifp = &sc->arpcom.ac_if;
6571         int i;
6572
6573         if_printf(ifp,
6574         "----------------------------"
6575         "  tx mbuf data  "
6576         "----------------------------\n");
6577
6578         for (i = 0; i < count; i++) {
6579                 if_printf(ifp, "txmbuf[%d]\n", chain_prod);
6580                 bce_dump_mbuf(sc, sc->tx_mbuf_ptr[chain_prod]);
6581                 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod));
6582         }
6583
6584         if_printf(ifp,
6585         "----------------------------"
6586         "----------------"
6587         "----------------------------\n");
6588 }
6589
6590
6591 /****************************************************************************/
6592 /* Prints out the mbufs in the RX mbuf chain.                               */
6593 /*                                                                          */
6594 /* Returns:                                                                 */
6595 /*   Nothing.                                                               */
6596 /****************************************************************************/
6597 static void
6598 bce_dump_rx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6599 {
6600         struct ifnet *ifp = &sc->arpcom.ac_if;
6601         int i;
6602
6603         if_printf(ifp,
6604         "----------------------------"
6605         "  rx mbuf data  "
6606         "----------------------------\n");
6607
6608         for (i = 0; i < count; i++) {
6609                 if_printf(ifp, "rxmbuf[0x%04X]\n", chain_prod);
6610                 bce_dump_mbuf(sc, sc->rx_mbuf_ptr[chain_prod]);
6611                 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod));
6612         }
6613
6614         if_printf(ifp,
6615         "----------------------------"
6616         "----------------"
6617         "----------------------------\n");
6618 }
6619
6620
6621 /****************************************************************************/
6622 /* Prints out a tx_bd structure.                                            */
6623 /*                                                                          */
6624 /* Returns:                                                                 */
6625 /*   Nothing.                                                               */
6626 /****************************************************************************/
6627 static void
6628 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
6629 {
6630         struct ifnet *ifp = &sc->arpcom.ac_if;
6631
6632         if (idx > MAX_TX_BD) {
6633                 /* Index out of range. */
6634                 if_printf(ifp, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
6635         } else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) {
6636                 /* TX Chain page pointer. */
6637                 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6638                           "chain page pointer\n",
6639                           idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo);
6640         } else {
6641                 /* Normal tx_bd entry. */
6642                 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6643                           "nbytes = 0x%08X, "
6644                           "vlan tag= 0x%04X, flags = 0x%04X (",
6645                           idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo,
6646                           txbd->tx_bd_mss_nbytes,
6647                           txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
6648
6649                 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT)
6650                         kprintf(" CONN_FAULT");
6651
6652                 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM)
6653                         kprintf(" TCP_UDP_CKSUM");
6654
6655                 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM)
6656                         kprintf(" IP_CKSUM");
6657
6658                 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG)
6659                         kprintf("  VLAN");
6660
6661                 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW)
6662                         kprintf(" COAL_NOW");
6663
6664                 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC)
6665                         kprintf(" DONT_GEN_CRC");
6666
6667                 if (txbd->tx_bd_flags & TX_BD_FLAGS_START)
6668                         kprintf(" START");
6669
6670                 if (txbd->tx_bd_flags & TX_BD_FLAGS_END)
6671                         kprintf(" END");
6672
6673                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO)
6674                         kprintf(" LSO");
6675
6676                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD)
6677                         kprintf(" OPTION_WORD");
6678
6679                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS)
6680                         kprintf(" FLAGS");
6681
6682                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP)
6683                         kprintf(" SNAP");
6684
6685                 kprintf(" )\n");
6686         }
6687 }
6688
6689
6690 /****************************************************************************/
6691 /* Prints out a rx_bd structure.                                            */
6692 /*                                                                          */
6693 /* Returns:                                                                 */
6694 /*   Nothing.                                                               */
6695 /****************************************************************************/
6696 static void
6697 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
6698 {
6699         struct ifnet *ifp = &sc->arpcom.ac_if;
6700
6701         if (idx > MAX_RX_BD) {
6702                 /* Index out of range. */
6703                 if_printf(ifp, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
6704         } else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) {
6705                 /* TX Chain page pointer. */
6706                 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6707                           "chain page pointer\n",
6708                           idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo);
6709         } else {
6710                 /* Normal tx_bd entry. */
6711                 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6712                           "nbytes = 0x%08X, flags = 0x%08X\n",
6713                           idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo,
6714                           rxbd->rx_bd_len, rxbd->rx_bd_flags);
6715         }
6716 }
6717
6718
6719 /****************************************************************************/
6720 /* Prints out a l2_fhdr structure.                                          */
6721 /*                                                                          */
6722 /* Returns:                                                                 */
6723 /*   Nothing.                                                               */
6724 /****************************************************************************/
6725 static void
6726 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
6727 {
6728         if_printf(&sc->arpcom.ac_if, "l2_fhdr[0x%04X]: status = 0x%08X, "
6729                   "pkt_len = 0x%04X, vlan = 0x%04x, "
6730                   "ip_xsum = 0x%04X, tcp_udp_xsum = 0x%04X\n",
6731                   idx, l2fhdr->l2_fhdr_status,
6732                   l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
6733                   l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
6734 }
6735
6736
6737 /****************************************************************************/
6738 /* Prints out the tx chain.                                                 */
6739 /*                                                                          */
6740 /* Returns:                                                                 */
6741 /*   Nothing.                                                               */
6742 /****************************************************************************/
6743 static void
6744 bce_dump_tx_chain(struct bce_softc *sc, int tx_prod, int count)
6745 {
6746         struct ifnet *ifp = &sc->arpcom.ac_if;
6747         int i;
6748
6749         /* First some info about the tx_bd chain structure. */
6750         if_printf(ifp,
6751         "----------------------------"
6752         "  tx_bd  chain  "
6753         "----------------------------\n");
6754
6755         if_printf(ifp, "page size      = 0x%08X, "
6756                   "tx chain pages        = 0x%08X\n",
6757                   (uint32_t)BCM_PAGE_SIZE, (uint32_t)TX_PAGES);
6758
6759         if_printf(ifp, "tx_bd per page = 0x%08X, "
6760                   "usable tx_bd per page = 0x%08X\n",
6761                   (uint32_t)TOTAL_TX_BD_PER_PAGE,
6762                   (uint32_t)USABLE_TX_BD_PER_PAGE);
6763
6764         if_printf(ifp, "total tx_bd    = 0x%08X\n", (uint32_t)TOTAL_TX_BD);
6765
6766         if_printf(ifp,
6767         "----------------------------"
6768         "  tx_bd data    "
6769         "----------------------------\n");
6770
6771         /* Now print out the tx_bd's themselves. */
6772         for (i = 0; i < count; i++) {
6773                 struct tx_bd *txbd;
6774
6775                 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
6776                 bce_dump_txbd(sc, tx_prod, txbd);
6777                 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod));
6778         }
6779
6780         if_printf(ifp,
6781         "----------------------------"
6782         "----------------"
6783         "----------------------------\n");
6784 }
6785
6786
6787 /****************************************************************************/
6788 /* Prints out the rx chain.                                                 */
6789 /*                                                                          */
6790 /* Returns:                                                                 */
6791 /*   Nothing.                                                               */
6792 /****************************************************************************/
6793 static void
6794 bce_dump_rx_chain(struct bce_softc *sc, int rx_prod, int count)
6795 {
6796         struct ifnet *ifp = &sc->arpcom.ac_if;
6797         int i;
6798
6799         /* First some info about the tx_bd chain structure. */
6800         if_printf(ifp,
6801         "----------------------------"
6802         "  rx_bd  chain  "
6803         "----------------------------\n");
6804
6805         if_printf(ifp, "page size      = 0x%08X, "
6806                   "rx chain pages        = 0x%08X\n",
6807                   (uint32_t)BCM_PAGE_SIZE, (uint32_t)RX_PAGES);
6808
6809         if_printf(ifp, "rx_bd per page = 0x%08X, "
6810                   "usable rx_bd per page = 0x%08X\n",
6811                   (uint32_t)TOTAL_RX_BD_PER_PAGE,
6812                   (uint32_t)USABLE_RX_BD_PER_PAGE);
6813
6814         if_printf(ifp, "total rx_bd    = 0x%08X\n", (uint32_t)TOTAL_RX_BD);
6815
6816         if_printf(ifp,
6817         "----------------------------"
6818         "   rx_bd data   "
6819         "----------------------------\n");
6820
6821         /* Now print out the rx_bd's themselves. */
6822         for (i = 0; i < count; i++) {
6823                 struct rx_bd *rxbd;
6824
6825                 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
6826                 bce_dump_rxbd(sc, rx_prod, rxbd);
6827                 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod));
6828         }
6829
6830         if_printf(ifp,
6831         "----------------------------"
6832         "----------------"
6833         "----------------------------\n");
6834 }
6835
6836
6837 /****************************************************************************/
6838 /* Prints out the status block from host memory.                            */
6839 /*                                                                          */
6840 /* Returns:                                                                 */
6841 /*   Nothing.                                                               */
6842 /****************************************************************************/
6843 static void
6844 bce_dump_status_block(struct bce_softc *sc)
6845 {
6846         struct status_block *sblk = sc->status_block;
6847         struct ifnet *ifp = &sc->arpcom.ac_if;
6848
6849         if_printf(ifp,
6850         "----------------------------"
6851         "  Status Block  "
6852         "----------------------------\n");
6853
6854         if_printf(ifp, "    0x%08X - attn_bits\n", sblk->status_attn_bits);
6855
6856         if_printf(ifp, "    0x%08X - attn_bits_ack\n",
6857                   sblk->status_attn_bits_ack);
6858
6859         if_printf(ifp, "0x%04X(0x%04X) - rx_cons0\n",
6860             sblk->status_rx_quick_consumer_index0,
6861             (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index0));
6862
6863         if_printf(ifp, "0x%04X(0x%04X) - tx_cons0\n",
6864             sblk->status_tx_quick_consumer_index0,
6865             (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index0));
6866
6867         if_printf(ifp, "        0x%04X - status_idx\n", sblk->status_idx);
6868
6869         /* Theses indices are not used for normal L2 drivers. */
6870         if (sblk->status_rx_quick_consumer_index1) {
6871                 if_printf(ifp, "0x%04X(0x%04X) - rx_cons1\n",
6872                 sblk->status_rx_quick_consumer_index1,
6873                 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index1));
6874         }
6875
6876         if (sblk->status_tx_quick_consumer_index1) {
6877                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons1\n",
6878                 sblk->status_tx_quick_consumer_index1,
6879                 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index1));
6880         }
6881
6882         if (sblk->status_rx_quick_consumer_index2) {
6883                 if_printf(ifp, "0x%04X(0x%04X)- rx_cons2\n",
6884                 sblk->status_rx_quick_consumer_index2,
6885                 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index2));
6886         }
6887
6888         if (sblk->status_tx_quick_consumer_index2) {
6889                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons2\n",
6890                 sblk->status_tx_quick_consumer_index2,
6891                 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index2));
6892         }
6893
6894         if (sblk->status_rx_quick_consumer_index3) {
6895                 if_printf(ifp, "0x%04X(0x%04X) - rx_cons3\n",
6896                 sblk->status_rx_quick_consumer_index3,
6897                 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index3));
6898         }
6899
6900         if (sblk->status_tx_quick_consumer_index3) {
6901                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons3\n",
6902                 sblk->status_tx_quick_consumer_index3,
6903                 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index3));
6904         }
6905
6906         if (sblk->status_rx_quick_consumer_index4 ||
6907             sblk->status_rx_quick_consumer_index5) {
6908                 if_printf(ifp, "rx_cons4  = 0x%08X, rx_cons5      = 0x%08X\n",
6909                           sblk->status_rx_quick_consumer_index4,
6910                           sblk->status_rx_quick_consumer_index5);
6911         }
6912
6913         if (sblk->status_rx_quick_consumer_index6 ||
6914             sblk->status_rx_quick_consumer_index7) {
6915                 if_printf(ifp, "rx_cons6  = 0x%08X, rx_cons7      = 0x%08X\n",
6916                           sblk->status_rx_quick_consumer_index6,
6917                           sblk->status_rx_quick_consumer_index7);
6918         }
6919
6920         if (sblk->status_rx_quick_consumer_index8 ||
6921             sblk->status_rx_quick_consumer_index9) {
6922                 if_printf(ifp, "rx_cons8  = 0x%08X, rx_cons9      = 0x%08X\n",
6923                           sblk->status_rx_quick_consumer_index8,
6924                           sblk->status_rx_quick_consumer_index9);
6925         }
6926
6927         if (sblk->status_rx_quick_consumer_index10 ||
6928             sblk->status_rx_quick_consumer_index11) {
6929                 if_printf(ifp, "rx_cons10 = 0x%08X, rx_cons11     = 0x%08X\n",
6930                           sblk->status_rx_quick_consumer_index10,
6931                           sblk->status_rx_quick_consumer_index11);
6932         }
6933
6934         if (sblk->status_rx_quick_consumer_index12 ||
6935             sblk->status_rx_quick_consumer_index13) {
6936                 if_printf(ifp, "rx_cons12 = 0x%08X, rx_cons13     = 0x%08X\n",
6937                           sblk->status_rx_quick_consumer_index12,
6938                           sblk->status_rx_quick_consumer_index13);
6939         }
6940
6941         if (sblk->status_rx_quick_consumer_index14 ||
6942             sblk->status_rx_quick_consumer_index15) {
6943                 if_printf(ifp, "rx_cons14 = 0x%08X, rx_cons15     = 0x%08X\n",
6944                           sblk->status_rx_quick_consumer_index14,
6945                           sblk->status_rx_quick_consumer_index15);
6946         }
6947
6948         if (sblk->status_completion_producer_index ||
6949             sblk->status_cmd_consumer_index) {
6950                 if_printf(ifp, "com_prod  = 0x%08X, cmd_cons      = 0x%08X\n",
6951                           sblk->status_completion_producer_index,
6952                           sblk->status_cmd_consumer_index);
6953         }
6954
6955         if_printf(ifp,
6956         "----------------------------"
6957         "----------------"
6958         "----------------------------\n");
6959 }
6960
6961
6962 /****************************************************************************/
6963 /* Prints out the statistics block.                                         */
6964 /*                                                                          */
6965 /* Returns:                                                                 */
6966 /*   Nothing.                                                               */
6967 /****************************************************************************/
6968 static void
6969 bce_dump_stats_block(struct bce_softc *sc)
6970 {
6971         struct statistics_block *sblk = sc->stats_block;
6972         struct ifnet *ifp = &sc->arpcom.ac_if;
6973
6974         if_printf(ifp,
6975         "---------------"
6976         " Stats Block  (All Stats Not Shown Are 0) "
6977         "---------------\n");
6978
6979         if (sblk->stat_IfHCInOctets_hi || sblk->stat_IfHCInOctets_lo) {
6980                 if_printf(ifp, "0x%08X:%08X : IfHcInOctets\n",
6981                           sblk->stat_IfHCInOctets_hi,
6982                           sblk->stat_IfHCInOctets_lo);
6983         }
6984
6985         if (sblk->stat_IfHCInBadOctets_hi || sblk->stat_IfHCInBadOctets_lo) {
6986                 if_printf(ifp, "0x%08X:%08X : IfHcInBadOctets\n",
6987                           sblk->stat_IfHCInBadOctets_hi,
6988                           sblk->stat_IfHCInBadOctets_lo);
6989         }
6990
6991         if (sblk->stat_IfHCOutOctets_hi || sblk->stat_IfHCOutOctets_lo) {
6992                 if_printf(ifp, "0x%08X:%08X : IfHcOutOctets\n",
6993                           sblk->stat_IfHCOutOctets_hi,
6994                           sblk->stat_IfHCOutOctets_lo);
6995         }
6996
6997         if (sblk->stat_IfHCOutBadOctets_hi || sblk->stat_IfHCOutBadOctets_lo) {
6998                 if_printf(ifp, "0x%08X:%08X : IfHcOutBadOctets\n",
6999                           sblk->stat_IfHCOutBadOctets_hi,
7000                           sblk->stat_IfHCOutBadOctets_lo);
7001         }
7002
7003         if (sblk->stat_IfHCInUcastPkts_hi || sblk->stat_IfHCInUcastPkts_lo) {
7004                 if_printf(ifp, "0x%08X:%08X : IfHcInUcastPkts\n",
7005                           sblk->stat_IfHCInUcastPkts_hi,
7006                           sblk->stat_IfHCInUcastPkts_lo);
7007         }
7008
7009         if (sblk->stat_IfHCInBroadcastPkts_hi ||
7010             sblk->stat_IfHCInBroadcastPkts_lo) {
7011                 if_printf(ifp, "0x%08X:%08X : IfHcInBroadcastPkts\n",
7012                           sblk->stat_IfHCInBroadcastPkts_hi,
7013                           sblk->stat_IfHCInBroadcastPkts_lo);
7014         }
7015
7016         if (sblk->stat_IfHCInMulticastPkts_hi ||
7017             sblk->stat_IfHCInMulticastPkts_lo) {
7018                 if_printf(ifp, "0x%08X:%08X : IfHcInMulticastPkts\n",
7019                           sblk->stat_IfHCInMulticastPkts_hi,
7020                           sblk->stat_IfHCInMulticastPkts_lo);
7021         }
7022
7023         if (sblk->stat_IfHCOutUcastPkts_hi || sblk->stat_IfHCOutUcastPkts_lo) {
7024                 if_printf(ifp, "0x%08X:%08X : IfHcOutUcastPkts\n",
7025                           sblk->stat_IfHCOutUcastPkts_hi,
7026                           sblk->stat_IfHCOutUcastPkts_lo);
7027         }
7028
7029         if (sblk->stat_IfHCOutBroadcastPkts_hi ||
7030             sblk->stat_IfHCOutBroadcastPkts_lo) {
7031                 if_printf(ifp, "0x%08X:%08X : IfHcOutBroadcastPkts\n",
7032                           sblk->stat_IfHCOutBroadcastPkts_hi,
7033                           sblk->stat_IfHCOutBroadcastPkts_lo);
7034         }
7035
7036         if (sblk->stat_IfHCOutMulticastPkts_hi ||
7037             sblk->stat_IfHCOutMulticastPkts_lo) {
7038                 if_printf(ifp, "0x%08X:%08X : IfHcOutMulticastPkts\n",
7039                           sblk->stat_IfHCOutMulticastPkts_hi,
7040                           sblk->stat_IfHCOutMulticastPkts_lo);
7041         }
7042
7043         if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) {
7044                 if_printf(ifp, "         0x%08X : "
7045                 "emac_tx_stat_dot3statsinternalmactransmiterrors\n",
7046                 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
7047         }
7048
7049         if (sblk->stat_Dot3StatsCarrierSenseErrors) {
7050                 if_printf(ifp, "         0x%08X : "
7051                           "Dot3StatsCarrierSenseErrors\n",
7052                           sblk->stat_Dot3StatsCarrierSenseErrors);
7053         }
7054
7055         if (sblk->stat_Dot3StatsFCSErrors) {
7056                 if_printf(ifp, "         0x%08X : Dot3StatsFCSErrors\n",
7057                           sblk->stat_Dot3StatsFCSErrors);
7058         }
7059
7060         if (sblk->stat_Dot3StatsAlignmentErrors) {
7061                 if_printf(ifp, "         0x%08X : Dot3StatsAlignmentErrors\n",
7062                           sblk->stat_Dot3StatsAlignmentErrors);
7063         }
7064
7065         if (sblk->stat_Dot3StatsSingleCollisionFrames) {
7066                 if_printf(ifp, "         0x%08X : "
7067                           "Dot3StatsSingleCollisionFrames\n",
7068                           sblk->stat_Dot3StatsSingleCollisionFrames);
7069         }
7070
7071         if (sblk->stat_Dot3StatsMultipleCollisionFrames) {
7072                 if_printf(ifp, "         0x%08X : "
7073                           "Dot3StatsMultipleCollisionFrames\n",
7074                           sblk->stat_Dot3StatsMultipleCollisionFrames);
7075         }
7076
7077         if (sblk->stat_Dot3StatsDeferredTransmissions) {
7078                 if_printf(ifp, "         0x%08X : "
7079                           "Dot3StatsDeferredTransmissions\n",
7080                           sblk->stat_Dot3StatsDeferredTransmissions);
7081         }
7082
7083         if (sblk->stat_Dot3StatsExcessiveCollisions) {
7084                 if_printf(ifp, "         0x%08X : "
7085                           "Dot3StatsExcessiveCollisions\n",
7086                           sblk->stat_Dot3StatsExcessiveCollisions);
7087         }
7088
7089         if (sblk->stat_Dot3StatsLateCollisions) {
7090                 if_printf(ifp, "         0x%08X : Dot3StatsLateCollisions\n",
7091                           sblk->stat_Dot3StatsLateCollisions);
7092         }
7093
7094         if (sblk->stat_EtherStatsCollisions) {
7095                 if_printf(ifp, "         0x%08X : EtherStatsCollisions\n",
7096                           sblk->stat_EtherStatsCollisions);
7097         }
7098
7099         if (sblk->stat_EtherStatsFragments)  {
7100                 if_printf(ifp, "         0x%08X : EtherStatsFragments\n",
7101                           sblk->stat_EtherStatsFragments);
7102         }
7103
7104         if (sblk->stat_EtherStatsJabbers) {
7105                 if_printf(ifp, "         0x%08X : EtherStatsJabbers\n",
7106                           sblk->stat_EtherStatsJabbers);
7107         }
7108
7109         if (sblk->stat_EtherStatsUndersizePkts) {
7110                 if_printf(ifp, "         0x%08X : EtherStatsUndersizePkts\n",
7111                           sblk->stat_EtherStatsUndersizePkts);
7112         }
7113
7114         if (sblk->stat_EtherStatsOverrsizePkts) {
7115                 if_printf(ifp, "         0x%08X : EtherStatsOverrsizePkts\n",
7116                           sblk->stat_EtherStatsOverrsizePkts);
7117         }
7118
7119         if (sblk->stat_EtherStatsPktsRx64Octets) {
7120                 if_printf(ifp, "         0x%08X : EtherStatsPktsRx64Octets\n",
7121                           sblk->stat_EtherStatsPktsRx64Octets);
7122         }
7123
7124         if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) {
7125                 if_printf(ifp, "         0x%08X : "
7126                           "EtherStatsPktsRx65Octetsto127Octets\n",
7127                           sblk->stat_EtherStatsPktsRx65Octetsto127Octets);
7128         }
7129
7130         if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) {
7131                 if_printf(ifp, "         0x%08X : "
7132                           "EtherStatsPktsRx128Octetsto255Octets\n",
7133                           sblk->stat_EtherStatsPktsRx128Octetsto255Octets);
7134         }
7135
7136         if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) {
7137                 if_printf(ifp, "         0x%08X : "
7138                           "EtherStatsPktsRx256Octetsto511Octets\n",
7139                           sblk->stat_EtherStatsPktsRx256Octetsto511Octets);
7140         }
7141
7142         if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) {
7143                 if_printf(ifp, "         0x%08X : "
7144                           "EtherStatsPktsRx512Octetsto1023Octets\n",
7145                           sblk->stat_EtherStatsPktsRx512Octetsto1023Octets);
7146         }
7147
7148         if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) {
7149                 if_printf(ifp, "         0x%08X : "
7150                           "EtherStatsPktsRx1024Octetsto1522Octets\n",
7151                           sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets);
7152         }
7153
7154         if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) {
7155                 if_printf(ifp, "         0x%08X : "
7156                           "EtherStatsPktsRx1523Octetsto9022Octets\n",
7157                           sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets);
7158         }
7159
7160         if (sblk->stat_EtherStatsPktsTx64Octets) {
7161                 if_printf(ifp, "         0x%08X : EtherStatsPktsTx64Octets\n",
7162                           sblk->stat_EtherStatsPktsTx64Octets);
7163         }
7164
7165         if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) {
7166                 if_printf(ifp, "         0x%08X : "
7167                           "EtherStatsPktsTx65Octetsto127Octets\n",
7168                           sblk->stat_EtherStatsPktsTx65Octetsto127Octets);
7169         }
7170
7171         if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) {
7172                 if_printf(ifp, "         0x%08X : "
7173                           "EtherStatsPktsTx128Octetsto255Octets\n",
7174                           sblk->stat_EtherStatsPktsTx128Octetsto255Octets);
7175         }
7176
7177         if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) {
7178                 if_printf(ifp, "         0x%08X : "
7179                           "EtherStatsPktsTx256Octetsto511Octets\n",
7180                           sblk->stat_EtherStatsPktsTx256Octetsto511Octets);
7181         }
7182
7183         if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) {
7184                 if_printf(ifp, "         0x%08X : "
7185                           "EtherStatsPktsTx512Octetsto1023Octets\n",
7186                           sblk->stat_EtherStatsPktsTx512Octetsto1023Octets);
7187         }
7188
7189         if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) {
7190                 if_printf(ifp, "         0x%08X : "
7191                           "EtherStatsPktsTx1024Octetsto1522Octets\n",
7192                           sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets);
7193         }
7194
7195         if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) {
7196                 if_printf(ifp, "         0x%08X : "
7197                           "EtherStatsPktsTx1523Octetsto9022Octets\n",
7198                           sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets);
7199         }
7200
7201         if (sblk->stat_XonPauseFramesReceived) {
7202                 if_printf(ifp, "         0x%08X : XonPauseFramesReceived\n",
7203                           sblk->stat_XonPauseFramesReceived);
7204         }
7205
7206         if (sblk->stat_XoffPauseFramesReceived) {
7207                 if_printf(ifp, "          0x%08X : XoffPauseFramesReceived\n",
7208                           sblk->stat_XoffPauseFramesReceived);
7209         }
7210
7211         if (sblk->stat_OutXonSent) {
7212                 if_printf(ifp, "         0x%08X : OutXoffSent\n",
7213                           sblk->stat_OutXonSent);
7214         }
7215
7216         if (sblk->stat_OutXoffSent) {
7217                 if_printf(ifp, "         0x%08X : OutXoffSent\n",
7218                           sblk->stat_OutXoffSent);
7219         }
7220
7221         if (sblk->stat_FlowControlDone) {
7222                 if_printf(ifp, "         0x%08X : FlowControlDone\n",
7223                           sblk->stat_FlowControlDone);
7224         }
7225
7226         if (sblk->stat_MacControlFramesReceived) {
7227                 if_printf(ifp, "         0x%08X : MacControlFramesReceived\n",
7228                           sblk->stat_MacControlFramesReceived);
7229         }
7230
7231         if (sblk->stat_XoffStateEntered) {
7232                 if_printf(ifp, "         0x%08X : XoffStateEntered\n",
7233                           sblk->stat_XoffStateEntered);
7234         }
7235
7236         if (sblk->stat_IfInFramesL2FilterDiscards) {
7237                 if_printf(ifp, "         0x%08X : IfInFramesL2FilterDiscards\n",                          sblk->stat_IfInFramesL2FilterDiscards);
7238         }
7239
7240         if (sblk->stat_IfInRuleCheckerDiscards) {
7241                 if_printf(ifp, "         0x%08X : IfInRuleCheckerDiscards\n",
7242                           sblk->stat_IfInRuleCheckerDiscards);
7243         }
7244
7245         if (sblk->stat_IfInFTQDiscards) {
7246                 if_printf(ifp, "         0x%08X : IfInFTQDiscards\n",
7247                           sblk->stat_IfInFTQDiscards);
7248         }
7249
7250         if (sblk->stat_IfInMBUFDiscards) {
7251                 if_printf(ifp, "         0x%08X : IfInMBUFDiscards\n",
7252                           sblk->stat_IfInMBUFDiscards);
7253         }
7254
7255         if (sblk->stat_IfInRuleCheckerP4Hit) {
7256                 if_printf(ifp, "         0x%08X : IfInRuleCheckerP4Hit\n",
7257                           sblk->stat_IfInRuleCheckerP4Hit);
7258         }
7259
7260         if (sblk->stat_CatchupInRuleCheckerDiscards) {
7261                 if_printf(ifp, "         0x%08X : "
7262                           "CatchupInRuleCheckerDiscards\n",
7263                           sblk->stat_CatchupInRuleCheckerDiscards);
7264         }
7265
7266         if (sblk->stat_CatchupInFTQDiscards) {
7267                 if_printf(ifp, "         0x%08X : CatchupInFTQDiscards\n",
7268                           sblk->stat_CatchupInFTQDiscards);
7269         }
7270
7271         if (sblk->stat_CatchupInMBUFDiscards) {
7272                 if_printf(ifp, "         0x%08X : CatchupInMBUFDiscards\n",
7273                           sblk->stat_CatchupInMBUFDiscards);
7274         }
7275
7276         if (sblk->stat_CatchupInRuleCheckerP4Hit) {
7277                 if_printf(ifp, "         0x%08X : CatchupInRuleCheckerP4Hit\n",
7278                           sblk->stat_CatchupInRuleCheckerP4Hit);
7279         }
7280
7281         if_printf(ifp,
7282         "----------------------------"
7283         "----------------"
7284         "----------------------------\n");
7285 }
7286
7287
7288 /****************************************************************************/
7289 /* Prints out a summary of the driver state.                                */
7290 /*                                                                          */
7291 /* Returns:                                                                 */
7292 /*   Nothing.                                                               */
7293 /****************************************************************************/
7294 static void
7295 bce_dump_driver_state(struct bce_softc *sc)
7296 {
7297         struct ifnet *ifp = &sc->arpcom.ac_if;
7298         uint32_t val_hi, val_lo;
7299
7300         if_printf(ifp,
7301         "-----------------------------"
7302         " Driver State "
7303         "-----------------------------\n");
7304
7305         val_hi = BCE_ADDR_HI(sc);
7306         val_lo = BCE_ADDR_LO(sc);
7307         if_printf(ifp, "0x%08X:%08X - (sc) driver softc structure "
7308                   "virtual address\n", val_hi, val_lo);
7309
7310         val_hi = BCE_ADDR_HI(sc->status_block);
7311         val_lo = BCE_ADDR_LO(sc->status_block);
7312         if_printf(ifp, "0x%08X:%08X - (sc->status_block) status block "
7313                   "virtual address\n", val_hi, val_lo);
7314
7315         val_hi = BCE_ADDR_HI(sc->stats_block);
7316         val_lo = BCE_ADDR_LO(sc->stats_block);
7317         if_printf(ifp, "0x%08X:%08X - (sc->stats_block) statistics block "
7318                   "virtual address\n", val_hi, val_lo);
7319
7320         val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
7321         val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
7322         if_printf(ifp, "0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
7323                   "virtual adddress\n", val_hi, val_lo);
7324
7325         val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
7326         val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
7327         if_printf(ifp, "0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
7328                   "virtual address\n", val_hi, val_lo);
7329
7330         val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
7331         val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
7332         if_printf(ifp, "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
7333                   "virtual address\n", val_hi, val_lo);
7334
7335         val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
7336         val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
7337         if_printf(ifp, "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
7338                   "virtual address\n", val_hi, val_lo);
7339
7340         if_printf(ifp, "         0x%08X - (sc->interrupts_generated) "
7341                   "h/w intrs\n", sc->interrupts_generated);
7342
7343         if_printf(ifp, "         0x%08X - (sc->rx_interrupts) "
7344                   "rx interrupts handled\n", sc->rx_interrupts);
7345
7346         if_printf(ifp, "         0x%08X - (sc->tx_interrupts) "
7347                   "tx interrupts handled\n", sc->tx_interrupts);
7348
7349         if_printf(ifp, "         0x%08X - (sc->last_status_idx) "
7350                   "status block index\n", sc->last_status_idx);
7351
7352         if_printf(ifp, "     0x%04X(0x%04X) - (sc->tx_prod) "
7353                   "tx producer index\n",
7354                   sc->tx_prod, (uint16_t)TX_CHAIN_IDX(sc->tx_prod));
7355
7356         if_printf(ifp, "     0x%04X(0x%04X) - (sc->tx_cons) "
7357                   "tx consumer index\n",
7358                   sc->tx_cons, (uint16_t)TX_CHAIN_IDX(sc->tx_cons));
7359
7360         if_printf(ifp, "         0x%08X - (sc->tx_prod_bseq) "
7361                   "tx producer bseq index\n", sc->tx_prod_bseq);
7362
7363         if_printf(ifp, "     0x%04X(0x%04X) - (sc->rx_prod) "
7364                   "rx producer index\n",
7365                   sc->rx_prod, (uint16_t)RX_CHAIN_IDX(sc->rx_prod));
7366
7367         if_printf(ifp, "     0x%04X(0x%04X) - (sc->rx_cons) "
7368                   "rx consumer index\n",
7369                   sc->rx_cons, (uint16_t)RX_CHAIN_IDX(sc->rx_cons));
7370
7371         if_printf(ifp, "         0x%08X - (sc->rx_prod_bseq) "
7372                   "rx producer bseq index\n", sc->rx_prod_bseq);
7373
7374         if_printf(ifp, "         0x%08X - (sc->rx_mbuf_alloc) "
7375                   "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7376
7377         if_printf(ifp, "         0x%08X - (sc->free_rx_bd) "
7378                   "free rx_bd's\n", sc->free_rx_bd);
7379
7380         if_printf(ifp, "0x%08X/%08X - (sc->rx_low_watermark) rx "
7381                   "low watermark\n", sc->rx_low_watermark, sc->max_rx_bd);
7382
7383         if_printf(ifp, "         0x%08X - (sc->txmbuf_alloc) "
7384                   "tx mbufs allocated\n", sc->tx_mbuf_alloc);
7385
7386         if_printf(ifp, "         0x%08X - (sc->rx_mbuf_alloc) "
7387                   "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7388
7389         if_printf(ifp, "         0x%08X - (sc->used_tx_bd) used tx_bd's\n",
7390                   sc->used_tx_bd);
7391
7392         if_printf(ifp, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n",
7393                   sc->tx_hi_watermark, sc->max_tx_bd);
7394
7395         if_printf(ifp, "         0x%08X - (sc->mbuf_alloc_failed) "
7396                   "failed mbuf alloc\n", sc->mbuf_alloc_failed);
7397
7398         if_printf(ifp,
7399         "----------------------------"
7400         "----------------"
7401         "----------------------------\n");
7402 }
7403
7404
7405 /****************************************************************************/
7406 /* Prints out the hardware state through a summary of important registers,  */
7407 /* followed by a complete register dump.                                    */
7408 /*                                                                          */
7409 /* Returns:                                                                 */
7410 /*   Nothing.                                                               */
7411 /****************************************************************************/
7412 static void
7413 bce_dump_hw_state(struct bce_softc *sc)
7414 {
7415         struct ifnet *ifp = &sc->arpcom.ac_if;
7416         uint32_t val1;
7417         int i;
7418
7419         if_printf(ifp,
7420         "----------------------------"
7421         " Hardware State "
7422         "----------------------------\n");
7423
7424         if_printf(ifp, "0x%08X - bootcode version\n", sc->bce_bc_ver);
7425
7426         val1 = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
7427         if_printf(ifp, "0x%08X - (0x%06X) misc_enable_status_bits\n",
7428                   val1, BCE_MISC_ENABLE_STATUS_BITS);
7429
7430         val1 = REG_RD(sc, BCE_DMA_STATUS);
7431         if_printf(ifp, "0x%08X - (0x%04X) dma_status\n", val1, BCE_DMA_STATUS);
7432
7433         val1 = REG_RD(sc, BCE_CTX_STATUS);
7434         if_printf(ifp, "0x%08X - (0x%04X) ctx_status\n", val1, BCE_CTX_STATUS);
7435
7436         val1 = REG_RD(sc, BCE_EMAC_STATUS);
7437         if_printf(ifp, "0x%08X - (0x%04X) emac_status\n",
7438                   val1, BCE_EMAC_STATUS);
7439
7440         val1 = REG_RD(sc, BCE_RPM_STATUS);
7441         if_printf(ifp, "0x%08X - (0x%04X) rpm_status\n", val1, BCE_RPM_STATUS);
7442
7443         val1 = REG_RD(sc, BCE_TBDR_STATUS);
7444         if_printf(ifp, "0x%08X - (0x%04X) tbdr_status\n",
7445                   val1, BCE_TBDR_STATUS);
7446
7447         val1 = REG_RD(sc, BCE_TDMA_STATUS);
7448         if_printf(ifp, "0x%08X - (0x%04X) tdma_status\n",
7449                   val1, BCE_TDMA_STATUS);
7450
7451         val1 = REG_RD(sc, BCE_HC_STATUS);
7452         if_printf(ifp, "0x%08X - (0x%06X) hc_status\n", val1, BCE_HC_STATUS);
7453
7454         val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7455         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7456                   val1, BCE_TXP_CPU_STATE);
7457
7458         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7459         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7460                   val1, BCE_TPAT_CPU_STATE);
7461
7462         val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7463         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7464                   val1, BCE_RXP_CPU_STATE);
7465
7466         val1 = REG_RD_IND(sc, BCE_COM_CPU_STATE);
7467         if_printf(ifp, "0x%08X - (0x%06X) com_cpu_state\n",
7468                   val1, BCE_COM_CPU_STATE);
7469
7470         val1 = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
7471         if_printf(ifp, "0x%08X - (0x%06X) mcp_cpu_state\n",
7472                   val1, BCE_MCP_CPU_STATE);
7473
7474         val1 = REG_RD_IND(sc, BCE_CP_CPU_STATE);
7475         if_printf(ifp, "0x%08X - (0x%06X) cp_cpu_state\n",
7476                   val1, BCE_CP_CPU_STATE);
7477
7478         if_printf(ifp,
7479         "----------------------------"
7480         "----------------"
7481         "----------------------------\n");
7482
7483         if_printf(ifp,
7484         "----------------------------"
7485         " Register  Dump "
7486         "----------------------------\n");
7487
7488         for (i = 0x400; i < 0x8000; i += 0x10) {
7489                 if_printf(ifp, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7490                           REG_RD(sc, i),
7491                           REG_RD(sc, i + 0x4),
7492                           REG_RD(sc, i + 0x8),
7493                           REG_RD(sc, i + 0xc));
7494         }
7495
7496         if_printf(ifp,
7497         "----------------------------"
7498         "----------------"
7499         "----------------------------\n");
7500 }
7501
7502
7503 /****************************************************************************/
7504 /* Prints out the TXP state.                                                */
7505 /*                                                                          */
7506 /* Returns:                                                                 */
7507 /*   Nothing.                                                               */
7508 /****************************************************************************/
7509 static void
7510 bce_dump_txp_state(struct bce_softc *sc)
7511 {
7512         struct ifnet *ifp = &sc->arpcom.ac_if;
7513         uint32_t val1;
7514         int i;
7515
7516         if_printf(ifp,
7517         "----------------------------"
7518         "   TXP  State   "
7519         "----------------------------\n");
7520
7521         val1 = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
7522         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_mode\n",
7523                   val1, BCE_TXP_CPU_MODE);
7524
7525         val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7526         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7527                   val1, BCE_TXP_CPU_STATE);
7528
7529         val1 = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
7530         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_event_mask\n",
7531                   val1, BCE_TXP_CPU_EVENT_MASK);
7532
7533         if_printf(ifp,
7534         "----------------------------"
7535         " Register  Dump "
7536         "----------------------------\n");
7537
7538         for (i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
7539                 /* Skip the big blank spaces */
7540                 if (i < 0x454000 && i > 0x5ffff) {
7541                         if_printf(ifp, "0x%04X: "
7542                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7543                                   REG_RD_IND(sc, i),
7544                                   REG_RD_IND(sc, i + 0x4),
7545                                   REG_RD_IND(sc, i + 0x8),
7546                                   REG_RD_IND(sc, i + 0xc));
7547                 }
7548         }
7549
7550         if_printf(ifp,
7551         "----------------------------"
7552         "----------------"
7553         "----------------------------\n");
7554 }
7555
7556
7557 /****************************************************************************/
7558 /* Prints out the RXP state.                                                */
7559 /*                                                                          */
7560 /* Returns:                                                                 */
7561 /*   Nothing.                                                               */
7562 /****************************************************************************/
7563 static void
7564 bce_dump_rxp_state(struct bce_softc *sc)
7565 {
7566         struct ifnet *ifp = &sc->arpcom.ac_if;
7567         uint32_t val1;
7568         int i;
7569
7570         if_printf(ifp,
7571         "----------------------------"
7572         "   RXP  State   "
7573         "----------------------------\n");
7574
7575         val1 = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
7576         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_mode\n",
7577                   val1, BCE_RXP_CPU_MODE);
7578
7579         val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7580         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7581                   val1, BCE_RXP_CPU_STATE);
7582
7583         val1 = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
7584         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_event_mask\n",
7585                   val1, BCE_RXP_CPU_EVENT_MASK);
7586
7587         if_printf(ifp,
7588         "----------------------------"
7589         " Register  Dump "
7590         "----------------------------\n");
7591
7592         for (i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
7593                 /* Skip the big blank sapces */
7594                 if (i < 0xc5400 && i > 0xdffff) {
7595                         if_printf(ifp, "0x%04X: "
7596                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7597                                   REG_RD_IND(sc, i),
7598                                   REG_RD_IND(sc, i + 0x4),
7599                                   REG_RD_IND(sc, i + 0x8),
7600                                   REG_RD_IND(sc, i + 0xc));
7601                 }
7602         }
7603
7604         if_printf(ifp,
7605         "----------------------------"
7606         "----------------"
7607         "----------------------------\n");
7608 }
7609
7610
7611 /****************************************************************************/
7612 /* Prints out the TPAT state.                                               */
7613 /*                                                                          */
7614 /* Returns:                                                                 */
7615 /*   Nothing.                                                               */
7616 /****************************************************************************/
7617 static void
7618 bce_dump_tpat_state(struct bce_softc *sc)
7619 {
7620         struct ifnet *ifp = &sc->arpcom.ac_if;
7621         uint32_t val1;
7622         int i;
7623
7624         if_printf(ifp,
7625         "----------------------------"
7626         "   TPAT State   "
7627         "----------------------------\n");
7628
7629         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
7630         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_mode\n",
7631                   val1, BCE_TPAT_CPU_MODE);
7632
7633         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7634         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7635                   val1, BCE_TPAT_CPU_STATE);
7636
7637         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
7638         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_event_mask\n",
7639                   val1, BCE_TPAT_CPU_EVENT_MASK);
7640
7641         if_printf(ifp,
7642         "----------------------------"
7643         " Register  Dump "
7644         "----------------------------\n");
7645
7646         for (i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
7647                 /* Skip the big blank spaces */
7648                 if (i < 0x854000 && i > 0x9ffff) {
7649                         if_printf(ifp, "0x%04X: "
7650                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7651                                   REG_RD_IND(sc, i),
7652                                   REG_RD_IND(sc, i + 0x4),
7653                                   REG_RD_IND(sc, i + 0x8),
7654                                   REG_RD_IND(sc, i + 0xc));
7655                 }
7656         }
7657
7658         if_printf(ifp,
7659         "----------------------------"
7660         "----------------"
7661         "----------------------------\n");
7662 }
7663
7664
7665 /****************************************************************************/
7666 /* Prints out the driver state and then enters the debugger.                */
7667 /*                                                                          */
7668 /* Returns:                                                                 */
7669 /*   Nothing.                                                               */
7670 /****************************************************************************/
7671 static void
7672 bce_breakpoint(struct bce_softc *sc)
7673 {
7674 #if 0
7675         bce_freeze_controller(sc);
7676 #endif
7677
7678         bce_dump_driver_state(sc);
7679         bce_dump_status_block(sc);
7680         bce_dump_tx_chain(sc, 0, TOTAL_TX_BD);
7681         bce_dump_hw_state(sc);
7682         bce_dump_txp_state(sc);
7683
7684 #if 0
7685         bce_unfreeze_controller(sc);
7686 #endif
7687
7688         /* Call the debugger. */
7689         breakpoint();
7690 }
7691
7692 #endif  /* BCE_DEBUG */
7693
7694 static int
7695 bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS)
7696 {
7697         struct bce_softc *sc = arg1;
7698
7699         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7700                         &sc->bce_tx_quick_cons_trip_int,
7701                         BCE_COALMASK_TX_BDS_INT);
7702 }
7703
7704 static int
7705 bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS)
7706 {
7707         struct bce_softc *sc = arg1;
7708
7709         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7710                         &sc->bce_tx_quick_cons_trip,
7711                         BCE_COALMASK_TX_BDS);
7712 }
7713
7714 static int
7715 bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS)
7716 {
7717         struct bce_softc *sc = arg1;
7718
7719         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7720                         &sc->bce_tx_ticks_int,
7721                         BCE_COALMASK_TX_TICKS_INT);
7722 }
7723
7724 static int
7725 bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS)
7726 {
7727         struct bce_softc *sc = arg1;
7728
7729         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7730                         &sc->bce_tx_ticks,
7731                         BCE_COALMASK_TX_TICKS);
7732 }
7733
7734 static int
7735 bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS)
7736 {
7737         struct bce_softc *sc = arg1;
7738
7739         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7740                         &sc->bce_rx_quick_cons_trip_int,
7741                         BCE_COALMASK_RX_BDS_INT);
7742 }
7743
7744 static int
7745 bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS)
7746 {
7747         struct bce_softc *sc = arg1;
7748
7749         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7750                         &sc->bce_rx_quick_cons_trip,
7751                         BCE_COALMASK_RX_BDS);
7752 }
7753
7754 static int
7755 bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS)
7756 {
7757         struct bce_softc *sc = arg1;
7758
7759         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7760                         &sc->bce_rx_ticks_int,
7761                         BCE_COALMASK_RX_TICKS_INT);
7762 }
7763
7764 static int
7765 bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS)
7766 {
7767         struct bce_softc *sc = arg1;
7768
7769         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7770                         &sc->bce_rx_ticks,
7771                         BCE_COALMASK_RX_TICKS);
7772 }
7773
7774 static int
7775 bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS, uint32_t *coal,
7776                        uint32_t coalchg_mask)
7777 {
7778         struct bce_softc *sc = arg1;
7779         struct ifnet *ifp = &sc->arpcom.ac_if;
7780         int error = 0, v;
7781
7782         lwkt_serialize_enter(ifp->if_serializer);
7783
7784         v = *coal;
7785         error = sysctl_handle_int(oidp, &v, 0, req);
7786         if (!error && req->newptr != NULL) {
7787                 if (v < 0) {
7788                         error = EINVAL;
7789                 } else {
7790                         *coal = v;
7791                         sc->bce_coalchg_mask |= coalchg_mask;
7792                 }
7793         }
7794
7795         lwkt_serialize_exit(ifp->if_serializer);
7796         return error;
7797 }
7798
7799 static void
7800 bce_coal_change(struct bce_softc *sc)
7801 {
7802         struct ifnet *ifp = &sc->arpcom.ac_if;
7803
7804         ASSERT_SERIALIZED(ifp->if_serializer);
7805
7806         if ((ifp->if_flags & IFF_RUNNING) == 0) {
7807                 sc->bce_coalchg_mask = 0;
7808                 return;
7809         }
7810
7811         if (sc->bce_coalchg_mask &
7812             (BCE_COALMASK_TX_BDS | BCE_COALMASK_TX_BDS_INT)) {
7813                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
7814                        (sc->bce_tx_quick_cons_trip_int << 16) |
7815                        sc->bce_tx_quick_cons_trip);
7816                 if (bootverbose) {
7817                         if_printf(ifp, "tx_bds %u, tx_bds_int %u\n",
7818                                   sc->bce_tx_quick_cons_trip,
7819                                   sc->bce_tx_quick_cons_trip_int);
7820                 }
7821         }
7822
7823         if (sc->bce_coalchg_mask &
7824             (BCE_COALMASK_TX_TICKS | BCE_COALMASK_TX_TICKS_INT)) {
7825                 REG_WR(sc, BCE_HC_TX_TICKS,
7826                        (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
7827                 if (bootverbose) {
7828                         if_printf(ifp, "tx_ticks %u, tx_ticks_int %u\n",
7829                                   sc->bce_tx_ticks, sc->bce_tx_ticks_int);
7830                 }
7831         }
7832
7833         if (sc->bce_coalchg_mask &
7834             (BCE_COALMASK_RX_BDS | BCE_COALMASK_RX_BDS_INT)) {
7835                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
7836                        (sc->bce_rx_quick_cons_trip_int << 16) |
7837                        sc->bce_rx_quick_cons_trip);
7838                 if (bootverbose) {
7839                         if_printf(ifp, "rx_bds %u, rx_bds_int %u\n",
7840                                   sc->bce_rx_quick_cons_trip,
7841                                   sc->bce_rx_quick_cons_trip_int);
7842                 }
7843         }
7844
7845         if (sc->bce_coalchg_mask &
7846             (BCE_COALMASK_RX_TICKS | BCE_COALMASK_RX_TICKS_INT)) {
7847                 REG_WR(sc, BCE_HC_RX_TICKS,
7848                        (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
7849                 if (bootverbose) {
7850                         if_printf(ifp, "rx_ticks %u, rx_ticks_int %u\n",
7851                                   sc->bce_rx_ticks, sc->bce_rx_ticks_int);
7852                 }
7853         }
7854
7855         sc->bce_coalchg_mask = 0;
7856 }