1 /******************************************************************************
3 Copyright (c) 2001-2009, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
35 #include "e1000_api.h"
37 #ifdef NO_82542_SUPPORT
38 static void e1000_stop_nvm(struct e1000_hw *hw);
40 static void e1000_reload_nvm_generic(struct e1000_hw *hw);
43 * e1000_init_nvm_ops_generic - Initialize NVM function pointers
44 * @hw: pointer to the HW structure
46 * Setups up the function pointers to no-op functions
48 void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
50 struct e1000_nvm_info *nvm = &hw->nvm;
51 DEBUGFUNC("e1000_init_nvm_ops_generic");
53 /* Initialize function pointers */
54 nvm->ops.init_params = e1000_null_ops_generic;
55 nvm->ops.acquire = e1000_null_ops_generic;
56 nvm->ops.read = e1000_null_read_nvm;
57 nvm->ops.release = e1000_null_nvm_generic;
58 nvm->ops.reload = e1000_reload_nvm_generic;
59 nvm->ops.update = e1000_null_ops_generic;
60 nvm->ops.valid_led_default = e1000_null_led_default;
61 nvm->ops.validate = e1000_null_ops_generic;
62 nvm->ops.write = e1000_null_write_nvm;
66 * e1000_null_nvm_read - No-op function, return 0
67 * @hw: pointer to the HW structure
69 s32 e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
71 DEBUGFUNC("e1000_null_read_nvm");
76 * e1000_null_nvm_generic - No-op function, return void
77 * @hw: pointer to the HW structure
79 void e1000_null_nvm_generic(struct e1000_hw *hw)
81 DEBUGFUNC("e1000_null_nvm_generic");
86 * e1000_null_led_default - No-op function, return 0
87 * @hw: pointer to the HW structure
89 s32 e1000_null_led_default(struct e1000_hw *hw, u16 *data)
91 DEBUGFUNC("e1000_null_led_default");
96 * e1000_null_write_nvm - No-op function, return 0
97 * @hw: pointer to the HW structure
99 s32 e1000_null_write_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
101 DEBUGFUNC("e1000_null_write_nvm");
102 return E1000_SUCCESS;
106 * e1000_raise_eec_clk - Raise EEPROM clock
107 * @hw: pointer to the HW structure
108 * @eecd: pointer to the EEPROM
110 * Enable/Raise the EEPROM clock bit.
112 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
114 *eecd = *eecd | E1000_EECD_SK;
115 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
116 E1000_WRITE_FLUSH(hw);
117 usec_delay(hw->nvm.delay_usec);
121 * e1000_lower_eec_clk - Lower EEPROM clock
122 * @hw: pointer to the HW structure
123 * @eecd: pointer to the EEPROM
125 * Clear/Lower the EEPROM clock bit.
127 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
129 *eecd = *eecd & ~E1000_EECD_SK;
130 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
131 E1000_WRITE_FLUSH(hw);
132 usec_delay(hw->nvm.delay_usec);
136 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
137 * @hw: pointer to the HW structure
138 * @data: data to send to the EEPROM
139 * @count: number of bits to shift out
141 * We need to shift 'count' bits out to the EEPROM. So, the value in the
142 * "data" parameter will be shifted out to the EEPROM one bit at a time.
143 * In order to do this, "data" must be broken down into bits.
145 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
147 struct e1000_nvm_info *nvm = &hw->nvm;
148 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
151 DEBUGFUNC("e1000_shift_out_eec_bits");
153 mask = 0x01 << (count - 1);
154 if (nvm->type == e1000_nvm_eeprom_microwire)
155 eecd &= ~E1000_EECD_DO;
157 if (nvm->type == e1000_nvm_eeprom_spi)
158 eecd |= E1000_EECD_DO;
161 eecd &= ~E1000_EECD_DI;
164 eecd |= E1000_EECD_DI;
166 E1000_WRITE_REG(hw, E1000_EECD, eecd);
167 E1000_WRITE_FLUSH(hw);
169 usec_delay(nvm->delay_usec);
171 e1000_raise_eec_clk(hw, &eecd);
172 e1000_lower_eec_clk(hw, &eecd);
177 eecd &= ~E1000_EECD_DI;
178 E1000_WRITE_REG(hw, E1000_EECD, eecd);
182 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
183 * @hw: pointer to the HW structure
184 * @count: number of bits to shift in
186 * In order to read a register from the EEPROM, we need to shift 'count' bits
187 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
188 * the EEPROM (setting the SK bit), and then reading the value of the data out
189 * "DO" bit. During this "shifting in" process the data in "DI" bit should
192 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
198 DEBUGFUNC("e1000_shift_in_eec_bits");
200 eecd = E1000_READ_REG(hw, E1000_EECD);
202 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
205 for (i = 0; i < count; i++) {
207 e1000_raise_eec_clk(hw, &eecd);
209 eecd = E1000_READ_REG(hw, E1000_EECD);
211 eecd &= ~E1000_EECD_DI;
212 if (eecd & E1000_EECD_DO)
215 e1000_lower_eec_clk(hw, &eecd);
222 * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
223 * @hw: pointer to the HW structure
224 * @ee_reg: EEPROM flag for polling
226 * Polls the EEPROM status bit for either read or write completion based
227 * upon the value of 'ee_reg'.
229 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
231 u32 attempts = 100000;
233 s32 ret_val = -E1000_ERR_NVM;
235 DEBUGFUNC("e1000_poll_eerd_eewr_done");
237 for (i = 0; i < attempts; i++) {
238 if (ee_reg == E1000_NVM_POLL_READ)
239 reg = E1000_READ_REG(hw, E1000_EERD);
241 reg = E1000_READ_REG(hw, E1000_EEWR);
243 if (reg & E1000_NVM_RW_REG_DONE) {
244 ret_val = E1000_SUCCESS;
255 * e1000_acquire_nvm_generic - Generic request for access to EEPROM
256 * @hw: pointer to the HW structure
258 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
259 * Return successful if access grant bit set, else clear the request for
260 * EEPROM access and return -E1000_ERR_NVM (-1).
262 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
264 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
265 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
266 s32 ret_val = E1000_SUCCESS;
268 DEBUGFUNC("e1000_acquire_nvm_generic");
270 E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
271 eecd = E1000_READ_REG(hw, E1000_EECD);
274 if (eecd & E1000_EECD_GNT)
277 eecd = E1000_READ_REG(hw, E1000_EECD);
282 eecd &= ~E1000_EECD_REQ;
283 E1000_WRITE_REG(hw, E1000_EECD, eecd);
284 DEBUGOUT("Could not acquire NVM grant\n");
285 ret_val = -E1000_ERR_NVM;
292 * e1000_standby_nvm - Return EEPROM to standby state
293 * @hw: pointer to the HW structure
295 * Return the EEPROM to a standby state.
297 static void e1000_standby_nvm(struct e1000_hw *hw)
299 struct e1000_nvm_info *nvm = &hw->nvm;
300 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
302 DEBUGFUNC("e1000_standby_nvm");
304 if (nvm->type == e1000_nvm_eeprom_microwire) {
305 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
306 E1000_WRITE_REG(hw, E1000_EECD, eecd);
307 E1000_WRITE_FLUSH(hw);
308 usec_delay(nvm->delay_usec);
310 e1000_raise_eec_clk(hw, &eecd);
313 eecd |= E1000_EECD_CS;
314 E1000_WRITE_REG(hw, E1000_EECD, eecd);
315 E1000_WRITE_FLUSH(hw);
316 usec_delay(nvm->delay_usec);
318 e1000_lower_eec_clk(hw, &eecd);
320 if (nvm->type == e1000_nvm_eeprom_spi) {
321 /* Toggle CS to flush commands */
322 eecd |= E1000_EECD_CS;
323 E1000_WRITE_REG(hw, E1000_EECD, eecd);
324 E1000_WRITE_FLUSH(hw);
325 usec_delay(nvm->delay_usec);
326 eecd &= ~E1000_EECD_CS;
327 E1000_WRITE_REG(hw, E1000_EECD, eecd);
328 E1000_WRITE_FLUSH(hw);
329 usec_delay(nvm->delay_usec);
334 * e1000_stop_nvm - Terminate EEPROM command
335 * @hw: pointer to the HW structure
337 * Terminates the current command by inverting the EEPROM's chip select pin.
339 #ifdef NO_82542_SUPPORT
340 static void e1000_stop_nvm(struct e1000_hw *hw)
342 void e1000_stop_nvm(struct e1000_hw *hw)
347 DEBUGFUNC("e1000_stop_nvm");
349 eecd = E1000_READ_REG(hw, E1000_EECD);
350 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
352 eecd |= E1000_EECD_CS;
353 e1000_lower_eec_clk(hw, &eecd);
354 } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
355 /* CS on Microwire is active-high */
356 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
357 E1000_WRITE_REG(hw, E1000_EECD, eecd);
358 e1000_raise_eec_clk(hw, &eecd);
359 e1000_lower_eec_clk(hw, &eecd);
364 * e1000_release_nvm_generic - Release exclusive access to EEPROM
365 * @hw: pointer to the HW structure
367 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
369 void e1000_release_nvm_generic(struct e1000_hw *hw)
373 DEBUGFUNC("e1000_release_nvm_generic");
377 eecd = E1000_READ_REG(hw, E1000_EECD);
378 eecd &= ~E1000_EECD_REQ;
379 E1000_WRITE_REG(hw, E1000_EECD, eecd);
383 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
384 * @hw: pointer to the HW structure
386 * Setups the EEPROM for reading and writing.
388 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
390 struct e1000_nvm_info *nvm = &hw->nvm;
391 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
392 s32 ret_val = E1000_SUCCESS;
395 DEBUGFUNC("e1000_ready_nvm_eeprom");
397 if (nvm->type == e1000_nvm_eeprom_microwire) {
398 /* Clear SK and DI */
399 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
400 E1000_WRITE_REG(hw, E1000_EECD, eecd);
402 eecd |= E1000_EECD_CS;
403 E1000_WRITE_REG(hw, E1000_EECD, eecd);
405 if (nvm->type == e1000_nvm_eeprom_spi) {
406 u16 timeout = NVM_MAX_RETRY_SPI;
408 /* Clear SK and CS */
409 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
410 E1000_WRITE_REG(hw, E1000_EECD, eecd);
414 * Read "Status Register" repeatedly until the LSB is cleared.
415 * The EEPROM will signal that the command has been completed
416 * by clearing bit 0 of the internal status register. If it's
417 * not cleared within 'timeout', then error out.
420 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
421 hw->nvm.opcode_bits);
422 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
423 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
427 e1000_standby_nvm(hw);
432 DEBUGOUT("SPI NVM Status error\n");
433 ret_val = -E1000_ERR_NVM;
443 * e1000_read_nvm_spi - Read EEPROM's using SPI
444 * @hw: pointer to the HW structure
445 * @offset: offset of word in the EEPROM to read
446 * @words: number of words to read
447 * @data: word read from the EEPROM
449 * Reads a 16 bit word from the EEPROM.
451 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
453 struct e1000_nvm_info *nvm = &hw->nvm;
457 u8 read_opcode = NVM_READ_OPCODE_SPI;
459 DEBUGFUNC("e1000_read_nvm_spi");
462 * A check for invalid values: offset too large, too many words,
463 * and not enough words.
465 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
467 DEBUGOUT("nvm parameter(s) out of bounds\n");
468 ret_val = -E1000_ERR_NVM;
472 ret_val = nvm->ops.acquire(hw);
476 ret_val = e1000_ready_nvm_eeprom(hw);
480 e1000_standby_nvm(hw);
482 if ((nvm->address_bits == 8) && (offset >= 128))
483 read_opcode |= NVM_A8_OPCODE_SPI;
485 /* Send the READ command (opcode + addr) */
486 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
487 e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
490 * Read the data. SPI NVMs increment the address with each byte
491 * read and will roll over if reading beyond the end. This allows
492 * us to read the whole NVM from any offset
494 for (i = 0; i < words; i++) {
495 word_in = e1000_shift_in_eec_bits(hw, 16);
496 data[i] = (word_in >> 8) | (word_in << 8);
500 nvm->ops.release(hw);
507 * e1000_read_nvm_microwire - Reads EEPROM's using microwire
508 * @hw: pointer to the HW structure
509 * @offset: offset of word in the EEPROM to read
510 * @words: number of words to read
511 * @data: word read from the EEPROM
513 * Reads a 16 bit word from the EEPROM.
515 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
518 struct e1000_nvm_info *nvm = &hw->nvm;
521 u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
523 DEBUGFUNC("e1000_read_nvm_microwire");
526 * A check for invalid values: offset too large, too many words,
527 * and not enough words.
529 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
531 DEBUGOUT("nvm parameter(s) out of bounds\n");
532 ret_val = -E1000_ERR_NVM;
536 ret_val = nvm->ops.acquire(hw);
540 ret_val = e1000_ready_nvm_eeprom(hw);
544 for (i = 0; i < words; i++) {
545 /* Send the READ command (opcode + addr) */
546 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
547 e1000_shift_out_eec_bits(hw, (u16)(offset + i),
551 * Read the data. For microwire, each word requires the
552 * overhead of setup and tear-down.
554 data[i] = e1000_shift_in_eec_bits(hw, 16);
555 e1000_standby_nvm(hw);
559 nvm->ops.release(hw);
566 * e1000_read_nvm_eerd - Reads EEPROM using EERD register
567 * @hw: pointer to the HW structure
568 * @offset: offset of word in the EEPROM to read
569 * @words: number of words to read
570 * @data: word read from the EEPROM
572 * Reads a 16 bit word from the EEPROM using the EERD register.
574 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
576 struct e1000_nvm_info *nvm = &hw->nvm;
578 s32 ret_val = E1000_SUCCESS;
580 DEBUGFUNC("e1000_read_nvm_eerd");
583 * A check for invalid values: offset too large, too many words,
584 * too many words for the offset, and not enough words.
586 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
588 DEBUGOUT("nvm parameter(s) out of bounds\n");
589 ret_val = -E1000_ERR_NVM;
593 for (i = 0; i < words; i++) {
594 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
595 E1000_NVM_RW_REG_START;
597 E1000_WRITE_REG(hw, E1000_EERD, eerd);
598 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
602 data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
603 E1000_NVM_RW_REG_DATA);
611 * e1000_write_nvm_spi - Write to EEPROM using SPI
612 * @hw: pointer to the HW structure
613 * @offset: offset within the EEPROM to be written to
614 * @words: number of words to write
615 * @data: 16 bit word(s) to be written to the EEPROM
617 * Writes data to EEPROM at offset using SPI interface.
619 * If e1000_update_nvm_checksum is not called after this function , the
620 * EEPROM will most likely contain an invalid checksum.
622 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
624 struct e1000_nvm_info *nvm = &hw->nvm;
628 DEBUGFUNC("e1000_write_nvm_spi");
631 * A check for invalid values: offset too large, too many words,
632 * and not enough words.
634 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
636 DEBUGOUT("nvm parameter(s) out of bounds\n");
637 ret_val = -E1000_ERR_NVM;
641 ret_val = nvm->ops.acquire(hw);
645 while (widx < words) {
646 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
648 ret_val = e1000_ready_nvm_eeprom(hw);
652 e1000_standby_nvm(hw);
654 /* Send the WRITE ENABLE command (8 bit opcode) */
655 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
658 e1000_standby_nvm(hw);
661 * Some SPI eeproms use the 8th address bit embedded in the
664 if ((nvm->address_bits == 8) && (offset >= 128))
665 write_opcode |= NVM_A8_OPCODE_SPI;
667 /* Send the Write command (8-bit opcode + addr) */
668 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
669 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
672 /* Loop to allow for up to whole page write of eeprom */
673 while (widx < words) {
674 u16 word_out = data[widx];
675 word_out = (word_out >> 8) | (word_out << 8);
676 e1000_shift_out_eec_bits(hw, word_out, 16);
679 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
680 e1000_standby_nvm(hw);
688 nvm->ops.release(hw);
695 * e1000_write_nvm_microwire - Writes EEPROM using microwire
696 * @hw: pointer to the HW structure
697 * @offset: offset within the EEPROM to be written to
698 * @words: number of words to write
699 * @data: 16 bit word(s) to be written to the EEPROM
701 * Writes data to EEPROM at offset using microwire interface.
703 * If e1000_update_nvm_checksum is not called after this function , the
704 * EEPROM will most likely contain an invalid checksum.
706 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
709 struct e1000_nvm_info *nvm = &hw->nvm;
712 u16 words_written = 0;
715 DEBUGFUNC("e1000_write_nvm_microwire");
718 * A check for invalid values: offset too large, too many words,
719 * and not enough words.
721 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
723 DEBUGOUT("nvm parameter(s) out of bounds\n");
724 ret_val = -E1000_ERR_NVM;
728 ret_val = nvm->ops.acquire(hw);
732 ret_val = e1000_ready_nvm_eeprom(hw);
736 e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
737 (u16)(nvm->opcode_bits + 2));
739 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
741 e1000_standby_nvm(hw);
743 while (words_written < words) {
744 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
747 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
750 e1000_shift_out_eec_bits(hw, data[words_written], 16);
752 e1000_standby_nvm(hw);
754 for (widx = 0; widx < 200; widx++) {
755 eecd = E1000_READ_REG(hw, E1000_EECD);
756 if (eecd & E1000_EECD_DO)
762 DEBUGOUT("NVM Write did not complete\n");
763 ret_val = -E1000_ERR_NVM;
767 e1000_standby_nvm(hw);
772 e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
773 (u16)(nvm->opcode_bits + 2));
775 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
778 nvm->ops.release(hw);
785 * e1000_read_pba_string_generic - Read device part number
786 * @hw: pointer to the HW structure
787 * @pba_num: pointer to device part number
788 * @pba_num_size: size of part number buffer
790 * Reads the product board assembly (PBA) number from the EEPROM and stores
791 * the value in pba_num.
793 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
802 DEBUGFUNC("e1000_read_pba_string_generic");
804 if (pba_num == NULL) {
805 DEBUGOUT("PBA string buffer was null\n");
806 ret_val = E1000_ERR_INVALID_ARGUMENT;
810 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
812 DEBUGOUT("NVM Read Error\n");
816 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
818 DEBUGOUT("NVM Read Error\n");
823 * if nvm_data is not ptr guard the PBA must be in legacy format which
824 * means pba_ptr is actually our second data word for the PBA number
825 * and we can decode it into an ascii string
827 if (nvm_data != NVM_PBA_PTR_GUARD) {
828 DEBUGOUT("NVM PBA number is not stored as string\n");
830 /* we will need 11 characters to store the PBA */
831 if (pba_num_size < 11) {
832 DEBUGOUT("PBA string buffer too small\n");
833 return E1000_ERR_NO_SPACE;
836 /* extract hex string from data and pba_ptr */
837 pba_num[0] = (nvm_data >> 12) & 0xF;
838 pba_num[1] = (nvm_data >> 8) & 0xF;
839 pba_num[2] = (nvm_data >> 4) & 0xF;
840 pba_num[3] = nvm_data & 0xF;
841 pba_num[4] = (pba_ptr >> 12) & 0xF;
842 pba_num[5] = (pba_ptr >> 8) & 0xF;
845 pba_num[8] = (pba_ptr >> 4) & 0xF;
846 pba_num[9] = pba_ptr & 0xF;
848 /* put a null character on the end of our string */
851 /* switch all the data but the '-' to hex char */
852 for (offset = 0; offset < 10; offset++) {
853 if (pba_num[offset] < 0xA)
854 pba_num[offset] += '0';
855 else if (pba_num[offset] < 0x10)
856 pba_num[offset] += 'A' - 0xA;
862 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
864 DEBUGOUT("NVM Read Error\n");
868 if (length == 0xFFFF || length == 0) {
869 DEBUGOUT("NVM PBA number section invalid length\n");
870 ret_val = E1000_ERR_NVM_PBA_SECTION;
873 /* check if pba_num buffer is big enough */
874 if (pba_num_size < (((u32)length * 2) - 1)) {
875 DEBUGOUT("PBA string buffer too small\n");
876 ret_val = E1000_ERR_NO_SPACE;
880 /* trim pba length from start of string */
884 for (offset = 0; offset < length; offset++) {
885 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
887 DEBUGOUT("NVM Read Error\n");
890 pba_num[offset * 2] = (u8)(nvm_data >> 8);
891 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
893 pba_num[offset * 2] = '\0';
900 * e1000_read_pba_length_generic - Read device part number length
901 * @hw: pointer to the HW structure
902 * @pba_num_size: size of part number buffer
904 * Reads the product board assembly (PBA) number length from the EEPROM and
905 * stores the value in pba_num_size.
907 s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size)
914 DEBUGFUNC("e1000_read_pba_length_generic");
916 if (pba_num_size == NULL) {
917 DEBUGOUT("PBA buffer size was null\n");
918 ret_val = E1000_ERR_INVALID_ARGUMENT;
922 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
924 DEBUGOUT("NVM Read Error\n");
928 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
930 DEBUGOUT("NVM Read Error\n");
934 /* if data is not ptr guard the PBA must be in legacy format */
935 if (nvm_data != NVM_PBA_PTR_GUARD) {
940 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
942 DEBUGOUT("NVM Read Error\n");
946 if (length == 0xFFFF || length == 0) {
947 DEBUGOUT("NVM PBA number section invalid length\n");
948 ret_val = E1000_ERR_NVM_PBA_SECTION;
953 * Convert from length in u16 values to u8 chars, add 1 for NULL,
954 * and subtract 2 because length field is included in length.
956 *pba_num_size = ((u32)length * 2) - 1;
963 * e1000_read_pba_num_generic - Read device part number
964 * @hw: pointer to the HW structure
965 * @pba_num: pointer to device part number
967 * Reads the product board assembly (PBA) number from the EEPROM and stores
968 * the value in pba_num.
970 s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num)
975 DEBUGFUNC("e1000_read_pba_num_generic");
977 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
979 DEBUGOUT("NVM Read Error\n");
981 } else if (nvm_data == NVM_PBA_PTR_GUARD) {
982 DEBUGOUT("NVM Not Supported\n");
983 ret_val = E1000_NOT_IMPLEMENTED;
986 *pba_num = (u32)(nvm_data << 16);
988 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
990 DEBUGOUT("NVM Read Error\n");
993 *pba_num |= nvm_data;
1000 * e1000_read_mac_addr_generic - Read device MAC address
1001 * @hw: pointer to the HW structure
1003 * Reads the device MAC address from the EEPROM and stores the value.
1004 * Since devices with two ports use the same EEPROM, we increment the
1005 * last bit in the MAC address for the second port.
1007 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
1013 rar_high = E1000_READ_REG(hw, E1000_RAH(0));
1014 rar_low = E1000_READ_REG(hw, E1000_RAL(0));
1016 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
1017 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
1019 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
1020 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
1022 for (i = 0; i < ETH_ADDR_LEN; i++)
1023 hw->mac.addr[i] = hw->mac.perm_addr[i];
1025 return E1000_SUCCESS;
1029 * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
1030 * @hw: pointer to the HW structure
1032 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
1033 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
1035 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
1037 s32 ret_val = E1000_SUCCESS;
1041 DEBUGFUNC("e1000_validate_nvm_checksum_generic");
1043 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1044 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1046 DEBUGOUT("NVM Read Error\n");
1049 checksum += nvm_data;
1052 if (checksum != (u16) NVM_SUM) {
1053 DEBUGOUT("NVM Checksum Invalid\n");
1054 ret_val = -E1000_ERR_NVM;
1063 * e1000_update_nvm_checksum_generic - Update EEPROM checksum
1064 * @hw: pointer to the HW structure
1066 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
1067 * up to the checksum. Then calculates the EEPROM checksum and writes the
1068 * value to the EEPROM.
1070 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
1076 DEBUGFUNC("e1000_update_nvm_checksum");
1078 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
1079 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1081 DEBUGOUT("NVM Read Error while updating checksum.\n");
1084 checksum += nvm_data;
1086 checksum = (u16) NVM_SUM - checksum;
1087 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
1089 DEBUGOUT("NVM Write Error while updating checksum.\n");
1096 * e1000_reload_nvm_generic - Reloads EEPROM
1097 * @hw: pointer to the HW structure
1099 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
1100 * extended control register.
1102 static void e1000_reload_nvm_generic(struct e1000_hw *hw)
1106 DEBUGFUNC("e1000_reload_nvm_generic");
1109 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1110 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1111 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1112 E1000_WRITE_FLUSH(hw);