2 * Copyright (c) 2014 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Matthew Dillon <dillon@backplane.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * Intel 4th generation mobile cpus integrated I2C device, smbus driver.
37 * See ig4_reg.h for datasheet reference and notes.
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/errno.h>
46 #include <sys/mutex.h>
47 #include <sys/syslog.h>
52 #include <bus/pci/pcivar.h>
53 #include <bus/pci/pcireg.h>
54 #include <bus/smbus/smbconf.h>
61 #define TRANS_NORMAL 1
65 static void ig4iic_intr(void *cookie);
68 * Low-level inline support functions
72 reg_write(ig4iic_softc_t *sc, uint32_t reg, uint32_t value)
74 bus_space_write_4(sc->regs_t, sc->regs_h, reg, value);
75 bus_space_barrier(sc->regs_t, sc->regs_h, reg, 4,
76 BUS_SPACE_BARRIER_WRITE);
81 reg_read(ig4iic_softc_t *sc, uint32_t reg)
85 bus_space_barrier(sc->regs_t, sc->regs_h, reg, 4,
86 BUS_SPACE_BARRIER_READ);
87 value = bus_space_read_4(sc->regs_t, sc->regs_h, reg);
92 * Enable or disable the controller and wait for the controller to acknowledge
97 set_controller(ig4iic_softc_t *sc, uint32_t ctl)
103 reg_write(sc, IG4_REG_I2C_EN, ctl);
104 error = SMB_ETIMEOUT;
106 for (retry = 100; retry > 0; --retry) {
107 v = reg_read(sc, IG4_REG_ENABLE_STATUS);
108 if (((v ^ ctl) & IG4_I2C_ENABLE) == 0) {
112 tsleep(sc, 0, "i2cslv", 1);
118 * Wait up to 25ms for the requested status using a 25uS polling loop.
122 wait_status(ig4iic_softc_t *sc, uint32_t status)
130 error = SMB_ETIMEOUT;
131 count = sys_cputimer->count();
132 limit = sys_cputimer->freq / 40;
134 while (sys_cputimer->count() - count <= limit) {
136 * Check requested status
138 v = reg_read(sc, IG4_REG_I2C_STA);
145 * Shim RX_NOTEMPTY of the data was read by the
148 if (status & IG4_STATUS_RX_NOTEMPTY) {
149 if (sc->rpos != sc->rnext) {
156 * Shim TX_EMPTY by resetting the retry timer if we
157 * see a change in the transmit fifo level.
159 if (status & IG4_STATUS_TX_EMPTY) {
160 v = reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK;
163 count = sys_cputimer->count();
168 * The interrupt will wake us up if we are waiting for
169 * read data, otherwise poll.
171 if (status & IG4_STATUS_RX_NOTEMPTY) {
172 lksleep(sc, &sc->lk, 0, "i2cwait", (hz + 99) / 100);
181 * Read I2C data. The data might have already been read by
182 * the interrupt code, otherwise it is sitting in the data
187 data_read(ig4iic_softc_t *sc)
191 if (sc->rpos == sc->rnext) {
192 c = (uint8_t)reg_read(sc, IG4_REG_DATA_CMD);
194 c = sc->rbuf[sc->rpos & IG4_RBUFMASK];
201 * Set the slave address. The controller must be disabled when
202 * changing the address.
204 * This operation does not issue anything to the I2C bus but sets
205 * the target address for when the controller later issues a START.
209 set_slave_addr(ig4iic_softc_t *sc, uint8_t slave, int trans_op)
215 use_10bit = sc->use_10bit;
216 if (trans_op & SMB_TRANS_7BIT)
218 if (trans_op & SMB_TRANS_10BIT)
221 if (sc->slave_valid && sc->last_slave == slave &&
222 sc->use_10bit == use_10bit) {
225 sc->use_10bit = use_10bit;
228 * Wait for TXFIFO to drain before disabling the controller.
230 * If a write message has not been completed it's really a
231 * programming error, but for now in that case issue an extra
234 * If a read message has not been completed it's also a programming
235 * error, for now just ignore it.
237 wait_status(sc, IG4_STATUS_TX_NOTFULL);
238 if (sc->write_started) {
239 reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_STOP);
240 sc->write_started = 0;
242 if (sc->read_started)
243 sc->read_started = 0;
244 wait_status(sc, IG4_STATUS_TX_EMPTY);
246 set_controller(sc, 0);
247 ctl = reg_read(sc, IG4_REG_CTL);
248 ctl &= ~IG4_CTL_10BIT;
249 ctl |= IG4_CTL_RESTARTEN;
253 tar |= IG4_TAR_10BIT;
254 ctl |= IG4_CTL_10BIT;
256 reg_write(sc, IG4_REG_CTL, ctl);
257 reg_write(sc, IG4_REG_TAR_ADD, tar);
258 set_controller(sc, IG4_I2C_ENABLE);
260 sc->last_slave = slave;
264 * Issue START with byte command, possible count, and a variable length
265 * read or write buffer, then possible turn-around read. The read also
266 * has a possible count received.
270 * Quick: START+ADDR+RD/WR STOP
272 * Normal: START+ADDR+WR COMM DATA..DATA STOP
275 * RESTART+ADDR RDATA..RDATA STOP
276 * (can also be used for I2C transactions)
278 * Process Call: START+ADDR+WR COMM DATAL DATAH
279 * RESTART+ADDR+RD RDATAL RDATAH STOP
281 * Block: START+ADDR+RD COMM
282 * RESTART+ADDR+RD RCOUNT DATA... STOP
285 * RESTART+ADDR+WR WCOUNT DATA... STOP
287 * For I2C - basically, no *COUNT fields.
289 * Generally speaking, the START+ADDR / RESTART+ADDR is handled automatically
290 * by the controller at the beginning of a command sequence or on a data
291 * direction turn-around, and we only need to tell it when to issue the STOP.
294 smb_transaction(ig4iic_softc_t *sc, char cmd, int op,
295 char *wbuf, int wcount, char *rbuf, int rcount, int *actualp)
301 * Issue START or RESTART with next data byte, clear any previous
302 * abort condition that may have been holding the txfifo in reset.
304 last = IG4_DATA_RESTART;
305 reg_read(sc, IG4_REG_CLR_TX_ABORT);
310 * Issue command if not told otherwise (smbus).
312 if ((op & SMB_TRANS_NOCMD) == 0) {
313 error = wait_status(sc, IG4_STATUS_TX_NOTFULL);
317 if (wcount == 0 && rcount == 0 && (op & SMB_TRANS_NOSTOP) == 0)
318 last |= IG4_DATA_STOP;
319 reg_write(sc, IG4_REG_DATA_CMD, last);
323 * Clean out any previously received data
330 * If writing and not told otherwise, issue the write count (smbus).
332 if (wcount && (op & SMB_TRANS_NOCNT) == 0) {
333 error = wait_status(sc, IG4_STATUS_TX_NOTFULL);
337 reg_write(sc, IG4_REG_DATA_CMD, last);
345 error = wait_status(sc, IG4_STATUS_TX_NOTFULL);
348 last |= (u_char)*wbuf;
349 if (wcount == 1 && rcount == 0 && (op & SMB_TRANS_NOSTOP) == 0)
350 last |= IG4_DATA_STOP;
351 reg_write(sc, IG4_REG_DATA_CMD, last);
358 * Issue reads to xmit FIFO (strange, I know) to tell the controller
359 * to clock in data. At the moment just issue one read ahead to
360 * pipeline the incoming data.
362 * NOTE: In the case of NOCMD and wcount == 0 we still issue a
363 * RESTART here, even if the data direction has not changed
364 * from the previous CHAINing call. This we force the RESTART.
365 * (A new START is issued automatically by the controller in
366 * the other nominal cases such as a data direction change or
367 * a previous STOP was issued).
369 * If this will be the last byte read we must also issue the STOP
370 * at the end of the read.
373 last = IG4_DATA_RESTART | IG4_DATA_COMMAND_RD;
375 (op & (SMB_TRANS_NOSTOP | SMB_TRANS_NOCNT)) ==
377 last |= IG4_DATA_STOP;
379 reg_write(sc, IG4_REG_DATA_CMD, last);
380 last = IG4_DATA_COMMAND_RD;
384 * Bulk read (i2c) and count field handling (smbus)
388 * Maintain a pipeline by queueing the allowance for the next
389 * read before waiting for the current read.
392 if (op & SMB_TRANS_NOCNT)
393 last = (rcount == 2) ? IG4_DATA_STOP : 0;
396 reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_COMMAND_RD |
399 error = wait_status(sc, IG4_STATUS_RX_NOTEMPTY);
402 last = data_read(sc);
404 if (op & SMB_TRANS_NOCNT) {
405 *rbuf = (u_char)last;
412 * Handle count field (smbus), which is not part of
413 * the rcount'ed buffer. The first read data in a
414 * bulk transfer is the count.
416 * XXX if rcount is loaded as 0 how do I generate a
417 * STOP now without issuing another RD or WR?
419 if (rcount > (u_char)last)
420 rcount = (u_char)last;
421 op |= SMB_TRANS_NOCNT;
426 /* XXX wait for xmit buffer to become empty */
427 last = reg_read(sc, IG4_REG_TX_ABRT_SOURCE);
433 * SMBUS API FUNCTIONS
435 * Called from ig4iic_pci_attach/detach()
438 ig4iic_attach(ig4iic_softc_t *sc)
443 lockmgr(&sc->lk, LK_EXCLUSIVE);
445 v = reg_read(sc, IG4_REG_COMP_TYPE);
446 kprintf("type %08x\n", v);
447 v = reg_read(sc, IG4_REG_COMP_PARAM1);
448 kprintf("params %08x\n", v);
449 v = reg_read(sc, IG4_REG_COMP_VER);
450 kprintf("version %08x\n", v);
451 if (v != IG4_COMP_VER) {
456 v = reg_read(sc, IG4_REG_SS_SCL_HCNT);
457 kprintf("SS_SCL_HCNT %08x\n", v);
458 v = reg_read(sc, IG4_REG_SS_SCL_LCNT);
459 kprintf("SS_SCL_LCNT %08x\n", v);
460 v = reg_read(sc, IG4_REG_FS_SCL_HCNT);
461 kprintf("FS_SCL_HCNT %08x\n", v);
462 v = reg_read(sc, IG4_REG_FS_SCL_LCNT);
463 kprintf("FS_SCL_LCNT %08x\n", v);
464 v = reg_read(sc, IG4_REG_SDA_HOLD);
465 kprintf("HOLD %08x\n", v);
467 v = reg_read(sc, IG4_REG_SS_SCL_HCNT);
468 reg_write(sc, IG4_REG_FS_SCL_HCNT, v);
469 v = reg_read(sc, IG4_REG_SS_SCL_LCNT);
470 reg_write(sc, IG4_REG_FS_SCL_LCNT, v);
473 * Program based on a 25000 Hz clock. This is a bit of a
474 * hack (obviously). The defaults are 400 and 470 for standard
475 * and 60 and 130 for fast. The defaults for standard fail
476 * utterly (presumably cause an abort) because the clock time
477 * is ~18.8ms by default. This brings it down to ~4ms (for now).
479 reg_write(sc, IG4_REG_SS_SCL_HCNT, 100);
480 reg_write(sc, IG4_REG_SS_SCL_LCNT, 125);
481 reg_write(sc, IG4_REG_FS_SCL_HCNT, 100);
482 reg_write(sc, IG4_REG_FS_SCL_LCNT, 125);
485 * Use a threshold of 1 so we get interrupted on each character,
486 * allowing us to use lksleep() in our poll code. Not perfect
487 * but this is better than using DELAY() for receiving data.
489 reg_write(sc, IG4_REG_RX_TL, 1);
491 reg_write(sc, IG4_REG_CTL,
493 IG4_CTL_SLAVE_DISABLE |
497 sc->smb = device_add_child(sc->dev, "smbus", -1);
498 if (sc->smb == NULL) {
499 device_printf(sc->dev, "smbus driver not found\n");
506 * Don't do this, it blows up the PCI config
508 reg_write(sc, IG4_REG_RESETS, IG4_RESETS_ASSERT);
509 reg_write(sc, IG4_REG_RESETS, IG4_RESETS_DEASSERT);
513 * Interrupt on STOP detect or receive character ready
515 reg_write(sc, IG4_REG_INTR_MASK, IG4_INTR_STOP_DET |
517 if (set_controller(sc, 0))
518 device_printf(sc->dev, "controller error during attach-1\n");
519 if (set_controller(sc, IG4_I2C_ENABLE))
520 device_printf(sc->dev, "controller error during attach-2\n");
521 error = bus_setup_intr(sc->dev, sc->intr_res, 0,
522 ig4iic_intr, sc, &sc->intr_handle, NULL);
524 device_printf(sc->dev,
525 "Unable to setup irq: error %d\n", error);
529 /* Attach us to the smbus */
530 lockmgr(&sc->lk, LK_RELEASE);
531 error = bus_generic_attach(sc->dev);
532 lockmgr(&sc->lk, LK_EXCLUSIVE);
534 device_printf(sc->dev,
535 "failed to attach child: error %d\n", error);
538 sc->generic_attached = 1;
541 lockmgr(&sc->lk, LK_RELEASE);
546 ig4iic_detach(ig4iic_softc_t *sc)
550 lockmgr(&sc->lk, LK_EXCLUSIVE);
552 reg_write(sc, IG4_REG_INTR_MASK, 0);
553 reg_read(sc, IG4_REG_CLR_INTR);
554 set_controller(sc, 0);
556 if (sc->generic_attached) {
557 error = bus_generic_detach(sc->dev);
560 sc->generic_attached = 0;
563 device_delete_child(sc->dev, sc->smb);
566 if (sc->intr_handle) {
567 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_handle);
568 sc->intr_handle = NULL;
573 lockmgr(&sc->lk, LK_RELEASE);
578 ig4iic_smb_callback(device_t dev, int index, void *data)
580 ig4iic_softc_t *sc = device_get_softc(dev);
583 lockmgr(&sc->lk, LK_EXCLUSIVE);
586 case SMB_REQUEST_BUS:
589 case SMB_RELEASE_BUS:
597 lockmgr(&sc->lk, LK_RELEASE);
603 * Quick command. i.e. START + cmd + R/W + STOP and no data. It is
604 * unclear to me how I could implement this with the intel i2c controller
605 * because the controler sends STARTs and STOPs automatically with data.
608 ig4iic_smb_quick(device_t dev, u_char slave, int how)
610 ig4iic_softc_t *sc = device_get_softc(dev);
613 lockmgr(&sc->lk, LK_EXCLUSIVE);
617 error = SMB_ENOTSUPP;
620 error = SMB_ENOTSUPP;
623 error = SMB_ENOTSUPP;
626 lockmgr(&sc->lk, LK_RELEASE);
632 * Incremental send byte without stop (?). It is unclear why the slave
633 * address is specified if this presumably is used in combination with
634 * ig4iic_smb_quick().
636 * (Also, how would this work anyway? Issue the last byte with writeb()?)
639 ig4iic_smb_sendb(device_t dev, u_char slave, char byte)
641 ig4iic_softc_t *sc = device_get_softc(dev);
645 lockmgr(&sc->lk, LK_EXCLUSIVE);
647 set_slave_addr(sc, slave, 0);
649 if (wait_status(sc, IG4_STATUS_TX_NOTFULL) == 0) {
650 reg_write(sc, IG4_REG_DATA_CMD, cmd);
653 error = SMB_ETIMEOUT;
656 lockmgr(&sc->lk, LK_RELEASE);
661 * Incremental receive byte without stop (?). It is unclear why the slave
662 * address is specified if this presumably is used in combination with
663 * ig4iic_smb_quick().
666 ig4iic_smb_recvb(device_t dev, u_char slave, char *byte)
668 ig4iic_softc_t *sc = device_get_softc(dev);
671 lockmgr(&sc->lk, LK_EXCLUSIVE);
673 set_slave_addr(sc, slave, 0);
674 reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_COMMAND_RD);
675 if (wait_status(sc, IG4_STATUS_RX_NOTEMPTY) == 0) {
676 *byte = data_read(sc);
680 error = SMB_ETIMEOUT;
683 lockmgr(&sc->lk, LK_RELEASE);
688 * Write command and single byte in transaction.
691 ig4iic_smb_writeb(device_t dev, u_char slave, char cmd, char byte)
693 ig4iic_softc_t *sc = device_get_softc(dev);
696 lockmgr(&sc->lk, LK_EXCLUSIVE);
698 set_slave_addr(sc, slave, 0);
699 error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT,
700 &byte, 1, NULL, 0, NULL);
702 lockmgr(&sc->lk, LK_RELEASE);
707 * Write command and single word in transaction.
710 ig4iic_smb_writew(device_t dev, u_char slave, char cmd, short word)
712 ig4iic_softc_t *sc = device_get_softc(dev);
716 lockmgr(&sc->lk, LK_EXCLUSIVE);
718 set_slave_addr(sc, slave, 0);
719 buf[0] = word & 0xFF;
721 error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT,
722 buf, 2, NULL, 0, NULL);
724 lockmgr(&sc->lk, LK_RELEASE);
729 * write command and read single byte in transaction.
732 ig4iic_smb_readb(device_t dev, u_char slave, char cmd, char *byte)
734 ig4iic_softc_t *sc = device_get_softc(dev);
737 lockmgr(&sc->lk, LK_EXCLUSIVE);
739 set_slave_addr(sc, slave, 0);
740 error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT,
741 NULL, 0, byte, 1, NULL);
743 lockmgr(&sc->lk, LK_RELEASE);
748 * write command and read word in transaction.
751 ig4iic_smb_readw(device_t dev, u_char slave, char cmd, short *word)
753 ig4iic_softc_t *sc = device_get_softc(dev);
757 lockmgr(&sc->lk, LK_EXCLUSIVE);
759 set_slave_addr(sc, slave, 0);
760 if ((error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT,
761 NULL, 0, buf, 2, NULL)) == 0) {
762 *word = (u_char)buf[0] | ((u_char)buf[1] << 8);
765 lockmgr(&sc->lk, LK_RELEASE);
770 * write command and word and read word in transaction
773 ig4iic_smb_pcall(device_t dev, u_char slave, char cmd,
774 short sdata, short *rdata)
776 ig4iic_softc_t *sc = device_get_softc(dev);
781 lockmgr(&sc->lk, LK_EXCLUSIVE);
783 set_slave_addr(sc, slave, 0);
784 wbuf[0] = sdata & 0xFF;
785 wbuf[1] = sdata >> 8;
786 if ((error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT,
787 wbuf, 2, rbuf, 2, NULL)) == 0) {
788 *rdata = (u_char)rbuf[0] | ((u_char)rbuf[1] << 8);
791 lockmgr(&sc->lk, LK_RELEASE);
796 ig4iic_smb_bwrite(device_t dev, u_char slave, char cmd,
797 u_char wcount, char *buf)
799 ig4iic_softc_t *sc = device_get_softc(dev);
802 lockmgr(&sc->lk, LK_EXCLUSIVE);
804 set_slave_addr(sc, slave, 0);
805 error = smb_transaction(sc, cmd, 0,
806 buf, wcount, NULL, 0, NULL);
808 lockmgr(&sc->lk, LK_RELEASE);
813 ig4iic_smb_bread(device_t dev, u_char slave, char cmd,
814 u_char *countp_char, char *buf)
816 ig4iic_softc_t *sc = device_get_softc(dev);
817 int rcount = *countp_char;
820 lockmgr(&sc->lk, LK_EXCLUSIVE);
822 set_slave_addr(sc, slave, 0);
823 error = smb_transaction(sc, cmd, 0,
824 NULL, 0, buf, rcount, &rcount);
825 *countp_char = rcount;
827 lockmgr(&sc->lk, LK_RELEASE);
832 ig4iic_smb_trans(device_t dev, int slave, char cmd, int op,
833 char *wbuf, int wcount, char *rbuf, int rcount,
836 ig4iic_softc_t *sc = device_get_softc(dev);
839 lockmgr(&sc->lk, LK_EXCLUSIVE);
841 set_slave_addr(sc, slave, op);
842 error = smb_transaction(sc, cmd, op,
843 wbuf, wcount, rbuf, rcount, actualp);
845 lockmgr(&sc->lk, LK_RELEASE);
850 * Interrupt Operation
854 ig4iic_intr(void *cookie)
856 ig4iic_softc_t *sc = cookie;
859 lockmgr(&sc->lk, LK_EXCLUSIVE);
860 /* reg_write(sc, IG4_REG_INTR_MASK, IG4_INTR_STOP_DET);*/
861 status = reg_read(sc, IG4_REG_I2C_STA);
862 if (status & IG4_STATUS_RX_NOTEMPTY) {
863 sc->rbuf[sc->rnext & IG4_RBUFMASK] =
864 (uint8_t)reg_read(sc, IG4_REG_DATA_CMD);
867 reg_read(sc, IG4_REG_CLR_INTR);
869 lockmgr(&sc->lk, LK_RELEASE);
872 DRIVER_MODULE(smbus, ig4iic, smbus_driver, smbus_devclass, NULL, NULL);