1 /******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
35 #include "e1000_api.h"
37 static void e1000_reload_nvm_generic(struct e1000_hw *hw);
40 * e1000_init_nvm_ops_generic - Initialize NVM function pointers
41 * @hw: pointer to the HW structure
43 * Setups up the function pointers to no-op functions
45 void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
47 struct e1000_nvm_info *nvm = &hw->nvm;
48 DEBUGFUNC("e1000_init_nvm_ops_generic");
50 /* Initialize function pointers */
51 nvm->ops.init_params = e1000_null_ops_generic;
52 nvm->ops.acquire = e1000_null_ops_generic;
53 nvm->ops.read = e1000_null_read_nvm;
54 nvm->ops.release = e1000_null_nvm_generic;
55 nvm->ops.reload = e1000_reload_nvm_generic;
56 nvm->ops.update = e1000_null_ops_generic;
57 nvm->ops.valid_led_default = e1000_null_led_default;
58 nvm->ops.validate = e1000_null_ops_generic;
59 nvm->ops.write = e1000_null_write_nvm;
63 * e1000_null_nvm_read - No-op function, return 0
64 * @hw: pointer to the HW structure
66 s32 e1000_null_read_nvm(struct e1000_hw E1000_UNUSEDARG *hw,
67 u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,
68 u16 E1000_UNUSEDARG *c)
70 DEBUGFUNC("e1000_null_read_nvm");
75 * e1000_null_nvm_generic - No-op function, return void
76 * @hw: pointer to the HW structure
78 void e1000_null_nvm_generic(struct e1000_hw E1000_UNUSEDARG *hw)
80 DEBUGFUNC("e1000_null_nvm_generic");
85 * e1000_null_led_default - No-op function, return 0
86 * @hw: pointer to the HW structure
88 s32 e1000_null_led_default(struct e1000_hw E1000_UNUSEDARG *hw,
89 u16 E1000_UNUSEDARG *data)
91 DEBUGFUNC("e1000_null_led_default");
96 * e1000_null_write_nvm - No-op function, return 0
97 * @hw: pointer to the HW structure
99 s32 e1000_null_write_nvm(struct e1000_hw E1000_UNUSEDARG *hw,
100 u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,
101 u16 E1000_UNUSEDARG *c)
103 DEBUGFUNC("e1000_null_write_nvm");
104 return E1000_SUCCESS;
108 * e1000_raise_eec_clk - Raise EEPROM clock
109 * @hw: pointer to the HW structure
110 * @eecd: pointer to the EEPROM
112 * Enable/Raise the EEPROM clock bit.
114 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
116 *eecd = *eecd | E1000_EECD_SK;
117 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
118 E1000_WRITE_FLUSH(hw);
119 usec_delay(hw->nvm.delay_usec);
123 * e1000_lower_eec_clk - Lower EEPROM clock
124 * @hw: pointer to the HW structure
125 * @eecd: pointer to the EEPROM
127 * Clear/Lower the EEPROM clock bit.
129 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
131 *eecd = *eecd & ~E1000_EECD_SK;
132 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
133 E1000_WRITE_FLUSH(hw);
134 usec_delay(hw->nvm.delay_usec);
138 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
139 * @hw: pointer to the HW structure
140 * @data: data to send to the EEPROM
141 * @count: number of bits to shift out
143 * We need to shift 'count' bits out to the EEPROM. So, the value in the
144 * "data" parameter will be shifted out to the EEPROM one bit at a time.
145 * In order to do this, "data" must be broken down into bits.
147 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
149 struct e1000_nvm_info *nvm = &hw->nvm;
150 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
153 DEBUGFUNC("e1000_shift_out_eec_bits");
155 mask = 0x01 << (count - 1);
156 if (nvm->type == e1000_nvm_eeprom_microwire)
157 eecd &= ~E1000_EECD_DO;
159 if (nvm->type == e1000_nvm_eeprom_spi)
160 eecd |= E1000_EECD_DO;
163 eecd &= ~E1000_EECD_DI;
166 eecd |= E1000_EECD_DI;
168 E1000_WRITE_REG(hw, E1000_EECD, eecd);
169 E1000_WRITE_FLUSH(hw);
171 usec_delay(nvm->delay_usec);
173 e1000_raise_eec_clk(hw, &eecd);
174 e1000_lower_eec_clk(hw, &eecd);
179 eecd &= ~E1000_EECD_DI;
180 E1000_WRITE_REG(hw, E1000_EECD, eecd);
184 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
185 * @hw: pointer to the HW structure
186 * @count: number of bits to shift in
188 * In order to read a register from the EEPROM, we need to shift 'count' bits
189 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
190 * the EEPROM (setting the SK bit), and then reading the value of the data out
191 * "DO" bit. During this "shifting in" process the data in "DI" bit should
194 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
200 DEBUGFUNC("e1000_shift_in_eec_bits");
202 eecd = E1000_READ_REG(hw, E1000_EECD);
204 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
207 for (i = 0; i < count; i++) {
209 e1000_raise_eec_clk(hw, &eecd);
211 eecd = E1000_READ_REG(hw, E1000_EECD);
213 eecd &= ~E1000_EECD_DI;
214 if (eecd & E1000_EECD_DO)
217 e1000_lower_eec_clk(hw, &eecd);
224 * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
225 * @hw: pointer to the HW structure
226 * @ee_reg: EEPROM flag for polling
228 * Polls the EEPROM status bit for either read or write completion based
229 * upon the value of 'ee_reg'.
231 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
233 u32 attempts = 100000;
236 DEBUGFUNC("e1000_poll_eerd_eewr_done");
238 for (i = 0; i < attempts; i++) {
239 if (ee_reg == E1000_NVM_POLL_READ)
240 reg = E1000_READ_REG(hw, E1000_EERD);
242 reg = E1000_READ_REG(hw, E1000_EEWR);
244 if (reg & E1000_NVM_RW_REG_DONE)
245 return E1000_SUCCESS;
250 return -E1000_ERR_NVM;
254 * e1000_acquire_nvm_generic - Generic request for access to EEPROM
255 * @hw: pointer to the HW structure
257 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
258 * Return successful if access grant bit set, else clear the request for
259 * EEPROM access and return -E1000_ERR_NVM (-1).
261 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
263 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
264 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
266 DEBUGFUNC("e1000_acquire_nvm_generic");
268 E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
269 eecd = E1000_READ_REG(hw, E1000_EECD);
272 if (eecd & E1000_EECD_GNT)
275 eecd = E1000_READ_REG(hw, E1000_EECD);
280 eecd &= ~E1000_EECD_REQ;
281 E1000_WRITE_REG(hw, E1000_EECD, eecd);
282 DEBUGOUT("Could not acquire NVM grant\n");
283 return -E1000_ERR_NVM;
286 return E1000_SUCCESS;
290 * e1000_standby_nvm - Return EEPROM to standby state
291 * @hw: pointer to the HW structure
293 * Return the EEPROM to a standby state.
295 static void e1000_standby_nvm(struct e1000_hw *hw)
297 struct e1000_nvm_info *nvm = &hw->nvm;
298 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
300 DEBUGFUNC("e1000_standby_nvm");
302 if (nvm->type == e1000_nvm_eeprom_microwire) {
303 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
304 E1000_WRITE_REG(hw, E1000_EECD, eecd);
305 E1000_WRITE_FLUSH(hw);
306 usec_delay(nvm->delay_usec);
308 e1000_raise_eec_clk(hw, &eecd);
311 eecd |= E1000_EECD_CS;
312 E1000_WRITE_REG(hw, E1000_EECD, eecd);
313 E1000_WRITE_FLUSH(hw);
314 usec_delay(nvm->delay_usec);
316 e1000_lower_eec_clk(hw, &eecd);
317 } else if (nvm->type == e1000_nvm_eeprom_spi) {
318 /* Toggle CS to flush commands */
319 eecd |= E1000_EECD_CS;
320 E1000_WRITE_REG(hw, E1000_EECD, eecd);
321 E1000_WRITE_FLUSH(hw);
322 usec_delay(nvm->delay_usec);
323 eecd &= ~E1000_EECD_CS;
324 E1000_WRITE_REG(hw, E1000_EECD, eecd);
325 E1000_WRITE_FLUSH(hw);
326 usec_delay(nvm->delay_usec);
331 * e1000_stop_nvm - Terminate EEPROM command
332 * @hw: pointer to the HW structure
334 * Terminates the current command by inverting the EEPROM's chip select pin.
336 #ifdef NO_82542_SUPPORT
337 static void e1000_stop_nvm(struct e1000_hw *hw)
339 void e1000_stop_nvm(struct e1000_hw *hw)
344 DEBUGFUNC("e1000_stop_nvm");
346 eecd = E1000_READ_REG(hw, E1000_EECD);
347 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
349 eecd |= E1000_EECD_CS;
350 e1000_lower_eec_clk(hw, &eecd);
351 } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
352 /* CS on Microwire is active-high */
353 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
354 E1000_WRITE_REG(hw, E1000_EECD, eecd);
355 e1000_raise_eec_clk(hw, &eecd);
356 e1000_lower_eec_clk(hw, &eecd);
361 * e1000_release_nvm_generic - Release exclusive access to EEPROM
362 * @hw: pointer to the HW structure
364 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
366 void e1000_release_nvm_generic(struct e1000_hw *hw)
370 DEBUGFUNC("e1000_release_nvm_generic");
374 eecd = E1000_READ_REG(hw, E1000_EECD);
375 eecd &= ~E1000_EECD_REQ;
376 E1000_WRITE_REG(hw, E1000_EECD, eecd);
380 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
381 * @hw: pointer to the HW structure
383 * Setups the EEPROM for reading and writing.
385 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
387 struct e1000_nvm_info *nvm = &hw->nvm;
388 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
391 DEBUGFUNC("e1000_ready_nvm_eeprom");
393 if (nvm->type == e1000_nvm_eeprom_microwire) {
394 /* Clear SK and DI */
395 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
396 E1000_WRITE_REG(hw, E1000_EECD, eecd);
398 eecd |= E1000_EECD_CS;
399 E1000_WRITE_REG(hw, E1000_EECD, eecd);
400 } else if (nvm->type == e1000_nvm_eeprom_spi) {
401 u16 timeout = NVM_MAX_RETRY_SPI;
403 /* Clear SK and CS */
404 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
405 E1000_WRITE_REG(hw, E1000_EECD, eecd);
406 E1000_WRITE_FLUSH(hw);
409 /* Read "Status Register" repeatedly until the LSB is cleared.
410 * The EEPROM will signal that the command has been completed
411 * by clearing bit 0 of the internal status register. If it's
412 * not cleared within 'timeout', then error out.
415 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
416 hw->nvm.opcode_bits);
417 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
418 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
422 e1000_standby_nvm(hw);
427 DEBUGOUT("SPI NVM Status error\n");
428 return -E1000_ERR_NVM;
432 return E1000_SUCCESS;
436 * e1000_read_nvm_spi - Read EEPROM's using SPI
437 * @hw: pointer to the HW structure
438 * @offset: offset of word in the EEPROM to read
439 * @words: number of words to read
440 * @data: word read from the EEPROM
442 * Reads a 16 bit word from the EEPROM.
444 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
446 struct e1000_nvm_info *nvm = &hw->nvm;
450 u8 read_opcode = NVM_READ_OPCODE_SPI;
452 DEBUGFUNC("e1000_read_nvm_spi");
454 /* A check for invalid values: offset too large, too many words,
455 * and not enough words.
457 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
459 DEBUGOUT("nvm parameter(s) out of bounds\n");
460 return -E1000_ERR_NVM;
463 ret_val = nvm->ops.acquire(hw);
467 ret_val = e1000_ready_nvm_eeprom(hw);
471 e1000_standby_nvm(hw);
473 if ((nvm->address_bits == 8) && (offset >= 128))
474 read_opcode |= NVM_A8_OPCODE_SPI;
476 /* Send the READ command (opcode + addr) */
477 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
478 e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
480 /* Read the data. SPI NVMs increment the address with each byte
481 * read and will roll over if reading beyond the end. This allows
482 * us to read the whole NVM from any offset
484 for (i = 0; i < words; i++) {
485 word_in = e1000_shift_in_eec_bits(hw, 16);
486 data[i] = (word_in >> 8) | (word_in << 8);
490 nvm->ops.release(hw);
496 * e1000_read_nvm_microwire - Reads EEPROM's using microwire
497 * @hw: pointer to the HW structure
498 * @offset: offset of word in the EEPROM to read
499 * @words: number of words to read
500 * @data: word read from the EEPROM
502 * Reads a 16 bit word from the EEPROM.
504 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
507 struct e1000_nvm_info *nvm = &hw->nvm;
510 u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
512 DEBUGFUNC("e1000_read_nvm_microwire");
514 /* A check for invalid values: offset too large, too many words,
515 * and not enough words.
517 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
519 DEBUGOUT("nvm parameter(s) out of bounds\n");
520 return -E1000_ERR_NVM;
523 ret_val = nvm->ops.acquire(hw);
527 ret_val = e1000_ready_nvm_eeprom(hw);
531 for (i = 0; i < words; i++) {
532 /* Send the READ command (opcode + addr) */
533 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
534 e1000_shift_out_eec_bits(hw, (u16)(offset + i),
537 /* Read the data. For microwire, each word requires the
538 * overhead of setup and tear-down.
540 data[i] = e1000_shift_in_eec_bits(hw, 16);
541 e1000_standby_nvm(hw);
545 nvm->ops.release(hw);
551 * e1000_read_nvm_eerd - Reads EEPROM using EERD register
552 * @hw: pointer to the HW structure
553 * @offset: offset of word in the EEPROM to read
554 * @words: number of words to read
555 * @data: word read from the EEPROM
557 * Reads a 16 bit word from the EEPROM using the EERD register.
559 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
561 struct e1000_nvm_info *nvm = &hw->nvm;
563 s32 ret_val = E1000_SUCCESS;
565 DEBUGFUNC("e1000_read_nvm_eerd");
567 /* A check for invalid values: offset too large, too many words,
568 * too many words for the offset, and not enough words.
570 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
572 DEBUGOUT("nvm parameter(s) out of bounds\n");
573 return -E1000_ERR_NVM;
576 for (i = 0; i < words; i++) {
577 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
578 E1000_NVM_RW_REG_START;
580 E1000_WRITE_REG(hw, E1000_EERD, eerd);
581 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
585 data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
586 E1000_NVM_RW_REG_DATA);
593 * e1000_write_nvm_spi - Write to EEPROM using SPI
594 * @hw: pointer to the HW structure
595 * @offset: offset within the EEPROM to be written to
596 * @words: number of words to write
597 * @data: 16 bit word(s) to be written to the EEPROM
599 * Writes data to EEPROM at offset using SPI interface.
601 * If e1000_update_nvm_checksum is not called after this function , the
602 * EEPROM will most likely contain an invalid checksum.
604 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
606 struct e1000_nvm_info *nvm = &hw->nvm;
607 s32 ret_val = -E1000_ERR_NVM;
610 DEBUGFUNC("e1000_write_nvm_spi");
612 /* A check for invalid values: offset too large, too many words,
613 * and not enough words.
615 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
617 DEBUGOUT("nvm parameter(s) out of bounds\n");
618 return -E1000_ERR_NVM;
621 while (widx < words) {
622 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
624 ret_val = nvm->ops.acquire(hw);
628 ret_val = e1000_ready_nvm_eeprom(hw);
630 nvm->ops.release(hw);
634 e1000_standby_nvm(hw);
636 /* Send the WRITE ENABLE command (8 bit opcode) */
637 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
640 e1000_standby_nvm(hw);
642 /* Some SPI eeproms use the 8th address bit embedded in the
645 if ((nvm->address_bits == 8) && (offset >= 128))
646 write_opcode |= NVM_A8_OPCODE_SPI;
648 /* Send the Write command (8-bit opcode + addr) */
649 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
650 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
653 /* Loop to allow for up to whole page write of eeprom */
654 while (widx < words) {
655 u16 word_out = data[widx];
656 word_out = (word_out >> 8) | (word_out << 8);
657 e1000_shift_out_eec_bits(hw, word_out, 16);
660 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
661 e1000_standby_nvm(hw);
666 nvm->ops.release(hw);
673 * e1000_write_nvm_microwire - Writes EEPROM using microwire
674 * @hw: pointer to the HW structure
675 * @offset: offset within the EEPROM to be written to
676 * @words: number of words to write
677 * @data: 16 bit word(s) to be written to the EEPROM
679 * Writes data to EEPROM at offset using microwire interface.
681 * If e1000_update_nvm_checksum is not called after this function , the
682 * EEPROM will most likely contain an invalid checksum.
684 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
687 struct e1000_nvm_info *nvm = &hw->nvm;
690 u16 words_written = 0;
693 DEBUGFUNC("e1000_write_nvm_microwire");
695 /* A check for invalid values: offset too large, too many words,
696 * and not enough words.
698 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
700 DEBUGOUT("nvm parameter(s) out of bounds\n");
701 return -E1000_ERR_NVM;
704 ret_val = nvm->ops.acquire(hw);
708 ret_val = e1000_ready_nvm_eeprom(hw);
712 e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
713 (u16)(nvm->opcode_bits + 2));
715 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
717 e1000_standby_nvm(hw);
719 while (words_written < words) {
720 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
723 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
726 e1000_shift_out_eec_bits(hw, data[words_written], 16);
728 e1000_standby_nvm(hw);
730 for (widx = 0; widx < 200; widx++) {
731 eecd = E1000_READ_REG(hw, E1000_EECD);
732 if (eecd & E1000_EECD_DO)
738 DEBUGOUT("NVM Write did not complete\n");
739 ret_val = -E1000_ERR_NVM;
743 e1000_standby_nvm(hw);
748 e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
749 (u16)(nvm->opcode_bits + 2));
751 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
754 nvm->ops.release(hw);
760 * e1000_read_pba_string_generic - Read device part number
761 * @hw: pointer to the HW structure
762 * @pba_num: pointer to device part number
763 * @pba_num_size: size of part number buffer
765 * Reads the product board assembly (PBA) number from the EEPROM and stores
766 * the value in pba_num.
768 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
777 DEBUGFUNC("e1000_read_pba_string_generic");
779 if (pba_num == NULL) {
780 DEBUGOUT("PBA string buffer was null\n");
781 return -E1000_ERR_INVALID_ARGUMENT;
784 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
786 DEBUGOUT("NVM Read Error\n");
790 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
792 DEBUGOUT("NVM Read Error\n");
796 /* if nvm_data is not ptr guard the PBA must be in legacy format which
797 * means pba_ptr is actually our second data word for the PBA number
798 * and we can decode it into an ascii string
800 if (nvm_data != NVM_PBA_PTR_GUARD) {
801 DEBUGOUT("NVM PBA number is not stored as string\n");
803 /* make sure callers buffer is big enough to store the PBA */
804 if (pba_num_size < E1000_PBANUM_LENGTH) {
805 DEBUGOUT("PBA string buffer too small\n");
806 return E1000_ERR_NO_SPACE;
809 /* extract hex string from data and pba_ptr */
810 pba_num[0] = (nvm_data >> 12) & 0xF;
811 pba_num[1] = (nvm_data >> 8) & 0xF;
812 pba_num[2] = (nvm_data >> 4) & 0xF;
813 pba_num[3] = nvm_data & 0xF;
814 pba_num[4] = (pba_ptr >> 12) & 0xF;
815 pba_num[5] = (pba_ptr >> 8) & 0xF;
818 pba_num[8] = (pba_ptr >> 4) & 0xF;
819 pba_num[9] = pba_ptr & 0xF;
821 /* put a null character on the end of our string */
824 /* switch all the data but the '-' to hex char */
825 for (offset = 0; offset < 10; offset++) {
826 if (pba_num[offset] < 0xA)
827 pba_num[offset] += '0';
828 else if (pba_num[offset] < 0x10)
829 pba_num[offset] += 'A' - 0xA;
832 return E1000_SUCCESS;
835 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
837 DEBUGOUT("NVM Read Error\n");
841 if (length == 0xFFFF || length == 0) {
842 DEBUGOUT("NVM PBA number section invalid length\n");
843 return -E1000_ERR_NVM_PBA_SECTION;
845 /* check if pba_num buffer is big enough */
846 if (pba_num_size < (((u32)length * 2) - 1)) {
847 DEBUGOUT("PBA string buffer too small\n");
848 return -E1000_ERR_NO_SPACE;
851 /* trim pba length from start of string */
855 for (offset = 0; offset < length; offset++) {
856 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
858 DEBUGOUT("NVM Read Error\n");
861 pba_num[offset * 2] = (u8)(nvm_data >> 8);
862 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
864 pba_num[offset * 2] = '\0';
866 return E1000_SUCCESS;
870 * e1000_read_pba_length_generic - Read device part number length
871 * @hw: pointer to the HW structure
872 * @pba_num_size: size of part number buffer
874 * Reads the product board assembly (PBA) number length from the EEPROM and
875 * stores the value in pba_num_size.
877 s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size)
884 DEBUGFUNC("e1000_read_pba_length_generic");
886 if (pba_num_size == NULL) {
887 DEBUGOUT("PBA buffer size was null\n");
888 return -E1000_ERR_INVALID_ARGUMENT;
891 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
893 DEBUGOUT("NVM Read Error\n");
897 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
899 DEBUGOUT("NVM Read Error\n");
903 /* if data is not ptr guard the PBA must be in legacy format */
904 if (nvm_data != NVM_PBA_PTR_GUARD) {
905 *pba_num_size = E1000_PBANUM_LENGTH;
906 return E1000_SUCCESS;
909 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
911 DEBUGOUT("NVM Read Error\n");
915 if (length == 0xFFFF || length == 0) {
916 DEBUGOUT("NVM PBA number section invalid length\n");
917 return -E1000_ERR_NVM_PBA_SECTION;
920 /* Convert from length in u16 values to u8 chars, add 1 for NULL,
921 * and subtract 2 because length field is included in length.
923 *pba_num_size = ((u32)length * 2) - 1;
925 return E1000_SUCCESS;
929 * e1000_read_pba_num_generic - Read device part number
930 * @hw: pointer to the HW structure
931 * @pba_num: pointer to device part number
933 * Reads the product board assembly (PBA) number from the EEPROM and stores
934 * the value in pba_num.
936 s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num)
941 DEBUGFUNC("e1000_read_pba_num_generic");
943 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
945 DEBUGOUT("NVM Read Error\n");
947 } else if (nvm_data == NVM_PBA_PTR_GUARD) {
948 DEBUGOUT("NVM Not Supported\n");
949 return -E1000_NOT_IMPLEMENTED;
951 *pba_num = (u32)(nvm_data << 16);
953 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
955 DEBUGOUT("NVM Read Error\n");
958 *pba_num |= nvm_data;
960 return E1000_SUCCESS;
965 * @hw: pointer to the HW structure
966 * @eeprom_buf: optional pointer to EEPROM image
967 * @eeprom_buf_size: size of EEPROM image in words
968 * @max_pba_block_size: PBA block size limit
969 * @pba: pointer to output PBA structure
971 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
972 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
975 s32 e1000_read_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
976 u32 eeprom_buf_size, u16 max_pba_block_size,
977 struct e1000_pba *pba)
983 return -E1000_ERR_PARAM;
985 if (eeprom_buf == NULL) {
986 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2,
991 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
992 pba->word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
993 pba->word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
995 return -E1000_ERR_PARAM;
999 if (pba->word[0] == NVM_PBA_PTR_GUARD) {
1000 if (pba->pba_block == NULL)
1001 return -E1000_ERR_PARAM;
1003 ret_val = e1000_get_pba_block_size(hw, eeprom_buf,
1009 if (pba_block_size > max_pba_block_size)
1010 return -E1000_ERR_PARAM;
1012 if (eeprom_buf == NULL) {
1013 ret_val = e1000_read_nvm(hw, pba->word[1],
1019 if (eeprom_buf_size > (u32)(pba->word[1] +
1020 pba->pba_block[0])) {
1021 memcpy(pba->pba_block,
1022 &eeprom_buf[pba->word[1]],
1023 pba_block_size * sizeof(u16));
1025 return -E1000_ERR_PARAM;
1030 return E1000_SUCCESS;
1034 * e1000_write_pba_raw
1035 * @hw: pointer to the HW structure
1036 * @eeprom_buf: optional pointer to EEPROM image
1037 * @eeprom_buf_size: size of EEPROM image in words
1038 * @pba: pointer to PBA structure
1040 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
1041 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
1044 s32 e1000_write_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
1045 u32 eeprom_buf_size, struct e1000_pba *pba)
1050 return -E1000_ERR_PARAM;
1052 if (eeprom_buf == NULL) {
1053 ret_val = e1000_write_nvm(hw, NVM_PBA_OFFSET_0, 2,
1058 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1059 eeprom_buf[NVM_PBA_OFFSET_0] = pba->word[0];
1060 eeprom_buf[NVM_PBA_OFFSET_1] = pba->word[1];
1062 return -E1000_ERR_PARAM;
1066 if (pba->word[0] == NVM_PBA_PTR_GUARD) {
1067 if (pba->pba_block == NULL)
1068 return -E1000_ERR_PARAM;
1070 if (eeprom_buf == NULL) {
1071 ret_val = e1000_write_nvm(hw, pba->word[1],
1077 if (eeprom_buf_size > (u32)(pba->word[1] +
1078 pba->pba_block[0])) {
1079 memcpy(&eeprom_buf[pba->word[1]],
1081 pba->pba_block[0] * sizeof(u16));
1083 return -E1000_ERR_PARAM;
1088 return E1000_SUCCESS;
1092 * e1000_get_pba_block_size
1093 * @hw: pointer to the HW structure
1094 * @eeprom_buf: optional pointer to EEPROM image
1095 * @eeprom_buf_size: size of EEPROM image in words
1096 * @pba_data_size: pointer to output variable
1098 * Returns the size of the PBA block in words. Function operates on EEPROM
1099 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
1103 s32 e1000_get_pba_block_size(struct e1000_hw *hw, u16 *eeprom_buf,
1104 u32 eeprom_buf_size, u16 *pba_block_size)
1110 DEBUGFUNC("e1000_get_pba_block_size");
1112 if (eeprom_buf == NULL) {
1113 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, &pba_word[0]);
1117 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1118 pba_word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
1119 pba_word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
1121 return -E1000_ERR_PARAM;
1125 if (pba_word[0] == NVM_PBA_PTR_GUARD) {
1126 if (eeprom_buf == NULL) {
1127 ret_val = e1000_read_nvm(hw, pba_word[1] + 0, 1,
1132 if (eeprom_buf_size > pba_word[1])
1133 length = eeprom_buf[pba_word[1] + 0];
1135 return -E1000_ERR_PARAM;
1138 if (length == 0xFFFF || length == 0)
1139 return -E1000_ERR_NVM_PBA_SECTION;
1141 /* PBA number in legacy format, there is no PBA Block. */
1145 if (pba_block_size != NULL)
1146 *pba_block_size = length;
1148 return E1000_SUCCESS;
1152 * e1000_read_mac_addr_generic - Read device MAC address
1153 * @hw: pointer to the HW structure
1155 * Reads the device MAC address from the EEPROM and stores the value.
1156 * Since devices with two ports use the same EEPROM, we increment the
1157 * last bit in the MAC address for the second port.
1159 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
1165 rar_high = E1000_READ_REG(hw, E1000_RAH(0));
1166 rar_low = E1000_READ_REG(hw, E1000_RAL(0));
1168 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
1169 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
1171 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
1172 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
1174 for (i = 0; i < ETH_ADDR_LEN; i++)
1175 hw->mac.addr[i] = hw->mac.perm_addr[i];
1177 return E1000_SUCCESS;
1181 * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
1182 * @hw: pointer to the HW structure
1184 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
1185 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
1187 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
1193 DEBUGFUNC("e1000_validate_nvm_checksum_generic");
1195 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1196 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1198 DEBUGOUT("NVM Read Error\n");
1201 checksum += nvm_data;
1204 if (checksum != (u16) NVM_SUM) {
1205 DEBUGOUT("NVM Checksum Invalid\n");
1206 return -E1000_ERR_NVM;
1209 return E1000_SUCCESS;
1213 * e1000_update_nvm_checksum_generic - Update EEPROM checksum
1214 * @hw: pointer to the HW structure
1216 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
1217 * up to the checksum. Then calculates the EEPROM checksum and writes the
1218 * value to the EEPROM.
1220 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
1226 DEBUGFUNC("e1000_update_nvm_checksum");
1228 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
1229 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1231 DEBUGOUT("NVM Read Error while updating checksum.\n");
1234 checksum += nvm_data;
1236 checksum = (u16) NVM_SUM - checksum;
1237 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
1239 DEBUGOUT("NVM Write Error while updating checksum.\n");
1245 * e1000_reload_nvm_generic - Reloads EEPROM
1246 * @hw: pointer to the HW structure
1248 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
1249 * extended control register.
1251 static void e1000_reload_nvm_generic(struct e1000_hw *hw)
1255 DEBUGFUNC("e1000_reload_nvm_generic");
1258 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1259 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1260 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1261 E1000_WRITE_FLUSH(hw);
1265 * e1000_get_fw_version - Get firmware version information
1266 * @hw: pointer to the HW structure
1267 * @fw_vers: pointer to output version structure
1269 * unsupported/not present features return 0 in version structure
1271 void e1000_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers)
1273 u16 eeprom_verh, eeprom_verl, etrack_test, fw_version;
1274 u8 q, hval, rem, result;
1275 u16 comb_verh, comb_verl, comb_offset;
1277 memset(fw_vers, 0, sizeof(struct e1000_fw_version));
1279 /* basic eeprom version numbers, bits used vary by part and by tool
1280 * used to create the nvm images */
1281 /* Check which data format we have */
1282 hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
1283 switch (hw->mac.type) {
1285 e1000_read_invm_version(hw, fw_vers);
1290 /* Use this format, unless EETRACK ID exists,
1291 * then use alternate format
1293 if ((etrack_test & NVM_MAJOR_MASK) != NVM_ETRACK_VALID) {
1294 hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
1295 fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
1297 fw_vers->eep_minor = (fw_version & NVM_MINOR_MASK)
1299 fw_vers->eep_build = (fw_version & NVM_IMAGE_ID_MASK);
1305 /* find combo image version */
1306 hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset);
1307 if ((comb_offset != 0x0) &&
1308 (comb_offset != NVM_VER_INVALID)) {
1310 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset
1311 + 1), 1, &comb_verh);
1312 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset),
1315 /* get Option Rom version if it exists and is valid */
1316 if ((comb_verh && comb_verl) &&
1317 ((comb_verh != NVM_VER_INVALID) &&
1318 (comb_verl != NVM_VER_INVALID))) {
1320 fw_vers->or_valid = TRUE;
1322 comb_verl >> NVM_COMB_VER_SHFT;
1324 (comb_verl << NVM_COMB_VER_SHFT)
1325 | (comb_verh >> NVM_COMB_VER_SHFT);
1327 comb_verh & NVM_COMB_VER_MASK;
1334 hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
1335 fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
1338 /* check for old style version format in newer images*/
1339 if ((fw_version & NVM_NEW_DEC_MASK) == 0x0) {
1340 eeprom_verl = (fw_version & NVM_COMB_VER_MASK);
1342 eeprom_verl = (fw_version & NVM_MINOR_MASK)
1345 /* Convert minor value to hex before assigning to output struct
1346 * Val to be converted will not be higher than 99, per tool output
1348 q = eeprom_verl / NVM_HEX_CONV;
1349 hval = q * NVM_HEX_TENS;
1350 rem = eeprom_verl % NVM_HEX_CONV;
1351 result = hval + rem;
1352 fw_vers->eep_minor = result;
1355 if ((etrack_test & NVM_MAJOR_MASK) == NVM_ETRACK_VALID) {
1356 hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl);
1357 hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh);
1358 fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT)