2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
26 * Copyright (c) 2011 The FreeBSD Foundation
27 * All rights reserved.
29 * This software was developed by Konstantin Belousov under sponsorship from
30 * the FreeBSD Foundation.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
35 * 1. Redistributions of source code must retain the above copyright
36 * notice, this list of conditions and the following disclaimer.
37 * 2. Redistributions in binary form must reproduce the above copyright
38 * notice, this list of conditions and the following disclaimer in the
39 * documentation and/or other materials provided with the distribution.
41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
55 #include <machine/md_var.h>
58 #include <drm/drm_vma_manager.h>
59 #include <drm/i915_drm.h>
61 #include "i915_trace.h"
62 #include "intel_drv.h"
63 #include <linux/shmem_fs.h>
64 #include <linux/slab.h>
65 #include <linux/swap.h>
66 #include <linux/pci.h>
68 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
69 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
71 static __must_check int
72 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
75 i915_gem_object_retire(struct drm_i915_gem_object *obj);
77 static void i915_gem_write_fence(struct drm_device *dev, int reg,
78 struct drm_i915_gem_object *obj);
79 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
80 struct drm_i915_fence_reg *fence,
83 static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
84 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
86 static bool cpu_cache_is_coherent(struct drm_device *dev,
87 enum i915_cache_level level)
89 return HAS_LLC(dev) || level != I915_CACHE_NONE;
92 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
94 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
97 return obj->pin_display;
100 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
102 if (obj->tiling_mode)
103 i915_gem_release_mmap(obj);
105 /* As we do not have an associated fence register, we will force
106 * a tiling change if we ever need to acquire one.
108 obj->fence_dirty = false;
109 obj->fence_reg = I915_FENCE_REG_NONE;
112 /* some bookkeeping */
113 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
116 spin_lock(&dev_priv->mm.object_stat_lock);
117 dev_priv->mm.object_count++;
118 dev_priv->mm.object_memory += size;
119 spin_unlock(&dev_priv->mm.object_stat_lock);
122 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
125 spin_lock(&dev_priv->mm.object_stat_lock);
126 dev_priv->mm.object_count--;
127 dev_priv->mm.object_memory -= size;
128 spin_unlock(&dev_priv->mm.object_stat_lock);
132 i915_gem_wait_for_error(struct i915_gpu_error *error)
136 #define EXIT_COND (!i915_reset_in_progress(error) || \
137 i915_terminally_wedged(error))
142 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
143 * userspace. If it takes that long something really bad is going on and
144 * we should simply try to bail out and fail as gracefully as possible.
146 ret = wait_event_interruptible_timeout(error->reset_queue,
150 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
152 } else if (ret < 0) {
160 int i915_mutex_lock_interruptible(struct drm_device *dev)
162 struct drm_i915_private *dev_priv = dev->dev_private;
165 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
169 ret = mutex_lock_interruptible(&dev->struct_mutex);
173 WARN_ON(i915_verify_lists(dev));
178 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
180 return i915_gem_obj_bound_any(obj) && !obj->active;
184 i915_gem_init_ioctl(struct drm_device *dev, void *data,
185 struct drm_file *file)
187 struct drm_i915_private *dev_priv = dev->dev_private;
188 struct drm_i915_gem_init *args = data;
190 if (drm_core_check_feature(dev, DRIVER_MODESET))
193 if (args->gtt_start >= args->gtt_end ||
194 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
197 /* GEM with user mode setting was never supported on ilk and later. */
198 if (INTEL_INFO(dev)->gen >= 5)
201 mutex_lock(&dev->struct_mutex);
202 kprintf("INITGLOBALGTT GTT_START %016jx\n", (uintmax_t)args->gtt_start);
203 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
205 dev_priv->gtt.mappable_end = args->gtt_end;
206 mutex_unlock(&dev->struct_mutex);
212 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
213 struct drm_file *file)
215 struct drm_i915_private *dev_priv = dev->dev_private;
216 struct drm_i915_gem_get_aperture *args = data;
217 struct drm_i915_gem_object *obj;
221 mutex_lock(&dev->struct_mutex);
222 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
223 if (i915_gem_obj_is_pinned(obj))
224 pinned += i915_gem_obj_ggtt_size(obj);
225 mutex_unlock(&dev->struct_mutex);
227 args->aper_size = dev_priv->gtt.base.total;
228 args->aper_available_size = args->aper_size - pinned;
233 static void i915_gem_object_detach_phys(struct drm_i915_gem_object *obj)
235 drm_dma_handle_t *phys = obj->phys_handle;
240 if (obj->madv == I915_MADV_WILLNEED) {
241 struct vm_object *mapping = obj->base.vm_obj;
242 char *vaddr = phys->vaddr;
245 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
246 struct vm_page *page = shmem_read_mapping_page(mapping, i);
248 char *dst = kmap_atomic(page);
249 memcpy(dst, vaddr, PAGE_SIZE);
250 drm_clflush_virt_range(dst, PAGE_SIZE);
253 set_page_dirty(page);
254 mark_page_accessed(page);
256 page_cache_release(page);
261 i915_gem_chipset_flush(obj->base.dev);
265 set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE);
267 drm_pci_free(obj->base.dev, phys);
268 obj->phys_handle = NULL;
272 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
275 drm_dma_handle_t *phys;
276 struct vm_object *mapping;
280 if (obj->phys_handle) {
281 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
287 if (obj->madv != I915_MADV_WILLNEED)
291 if (obj->base.filp == NULL)
295 /* create a new object */
296 phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
302 set_memory_wc((unsigned long)vaddr, phys->size / PAGE_SIZE);
304 mapping = obj->base.vm_obj;
305 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
306 struct vm_page *page;
309 page = shmem_read_mapping_page(mapping, i);
312 set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE);
314 drm_pci_free(obj->base.dev, phys);
315 return PTR_ERR(page);
318 src = kmap_atomic(page);
319 memcpy(vaddr, src, PAGE_SIZE);
322 mark_page_accessed(page);
324 page_cache_release(page);
330 obj->phys_handle = phys;
335 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
336 struct drm_i915_gem_pwrite *args,
337 struct drm_file *file_priv)
339 struct drm_device *dev = obj->base.dev;
340 void *vaddr = (char *)obj->phys_handle->vaddr + args->offset;
341 char __user *user_data = to_user_ptr(args->data_ptr);
343 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
344 unsigned long unwritten;
346 /* The physical object once assigned is fixed for the lifetime
347 * of the obj, so we can safely drop the lock and continue
350 mutex_unlock(&dev->struct_mutex);
351 unwritten = copy_from_user(vaddr, user_data, args->size);
352 mutex_lock(&dev->struct_mutex);
357 i915_gem_chipset_flush(dev);
361 void *i915_gem_object_alloc(struct drm_device *dev)
363 return kmalloc(sizeof(struct drm_i915_gem_object),
364 M_DRM, M_WAITOK | M_ZERO);
367 void i915_gem_object_free(struct drm_i915_gem_object *obj)
373 i915_gem_create(struct drm_file *file,
374 struct drm_device *dev,
378 struct drm_i915_gem_object *obj;
382 size = roundup(size, PAGE_SIZE);
386 /* Allocate the new object */
387 obj = i915_gem_alloc_object(dev, size);
391 ret = drm_gem_handle_create(file, &obj->base, &handle);
392 /* drop reference from allocate - handle holds it now */
393 drm_gem_object_unreference_unlocked(&obj->base);
402 i915_gem_dumb_create(struct drm_file *file,
403 struct drm_device *dev,
404 struct drm_mode_create_dumb *args)
406 /* have to work out size/pitch and return them */
407 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
408 args->size = args->pitch * args->height;
409 return i915_gem_create(file, dev,
410 args->size, &args->handle);
414 * Creates a new mm object and returns a handle to it.
417 i915_gem_create_ioctl(struct drm_device *dev, void *data,
418 struct drm_file *file)
420 struct drm_i915_gem_create *args = data;
422 return i915_gem_create(file, dev,
423 args->size, &args->handle);
427 __copy_to_user_swizzled(char __user *cpu_vaddr,
428 const char *gpu_vaddr, int gpu_offset,
431 int ret, cpu_offset = 0;
434 int cacheline_end = ALIGN(gpu_offset + 1, 64);
435 int this_length = min(cacheline_end - gpu_offset, length);
436 int swizzled_gpu_offset = gpu_offset ^ 64;
438 ret = __copy_to_user(cpu_vaddr + cpu_offset,
439 gpu_vaddr + swizzled_gpu_offset,
444 cpu_offset += this_length;
445 gpu_offset += this_length;
446 length -= this_length;
453 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
454 const char __user *cpu_vaddr,
457 int ret, cpu_offset = 0;
460 int cacheline_end = ALIGN(gpu_offset + 1, 64);
461 int this_length = min(cacheline_end - gpu_offset, length);
462 int swizzled_gpu_offset = gpu_offset ^ 64;
464 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
465 cpu_vaddr + cpu_offset,
470 cpu_offset += this_length;
471 gpu_offset += this_length;
472 length -= this_length;
479 * Pins the specified object's pages and synchronizes the object with
480 * GPU accesses. Sets needs_clflush to non-zero if the caller should
481 * flush the object from the CPU cache.
483 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
495 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
496 /* If we're not in the cpu read domain, set ourself into the gtt
497 * read domain and manually flush cachelines (if required). This
498 * optimizes for the case when the gpu will dirty the data
499 * anyway again before the next pread happens. */
500 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
502 ret = i915_gem_object_wait_rendering(obj, true);
506 i915_gem_object_retire(obj);
509 ret = i915_gem_object_get_pages(obj);
513 i915_gem_object_pin_pages(obj);
518 /* Per-page copy function for the shmem pread fastpath.
519 * Flushes invalid cachelines before reading the target if
520 * needs_clflush is set. */
522 shmem_pread_fast(struct vm_page *page, int shmem_page_offset, int page_length,
523 char __user *user_data,
524 bool page_do_bit17_swizzling, bool needs_clflush)
529 if (unlikely(page_do_bit17_swizzling))
532 vaddr = kmap_atomic(page);
534 drm_clflush_virt_range(vaddr + shmem_page_offset,
536 ret = __copy_to_user_inatomic(user_data,
537 vaddr + shmem_page_offset,
539 kunmap_atomic(vaddr);
541 return ret ? -EFAULT : 0;
545 shmem_clflush_swizzled_range(char *addr, unsigned long length,
548 if (unlikely(swizzled)) {
549 unsigned long start = (unsigned long) addr;
550 unsigned long end = (unsigned long) addr + length;
552 /* For swizzling simply ensure that we always flush both
553 * channels. Lame, but simple and it works. Swizzled
554 * pwrite/pread is far from a hotpath - current userspace
555 * doesn't use it at all. */
556 start = round_down(start, 128);
557 end = round_up(end, 128);
559 drm_clflush_virt_range((void *)start, end - start);
561 drm_clflush_virt_range(addr, length);
566 /* Only difference to the fast-path function is that this can handle bit17
567 * and uses non-atomic copy and kmap functions. */
569 shmem_pread_slow(struct vm_page *page, int shmem_page_offset, int page_length,
570 char __user *user_data,
571 bool page_do_bit17_swizzling, bool needs_clflush)
578 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
580 page_do_bit17_swizzling);
582 if (page_do_bit17_swizzling)
583 ret = __copy_to_user_swizzled(user_data,
584 vaddr, shmem_page_offset,
587 ret = __copy_to_user(user_data,
588 vaddr + shmem_page_offset,
592 return ret ? - EFAULT : 0;
596 i915_gem_shmem_pread(struct drm_device *dev,
597 struct drm_i915_gem_object *obj,
598 struct drm_i915_gem_pread *args,
599 struct drm_file *file)
601 char __user *user_data;
604 int shmem_page_offset, page_length, ret = 0;
605 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
607 int needs_clflush = 0;
610 user_data = to_user_ptr(args->data_ptr);
613 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
615 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
619 offset = args->offset;
621 for (i = 0; i < (obj->base.size >> PAGE_SHIFT); i++) {
622 struct vm_page *page = obj->pages[i];
627 /* Operation in this page
629 * shmem_page_offset = offset within page in shmem file
630 * page_length = bytes to copy for this page
632 shmem_page_offset = offset_in_page(offset);
633 page_length = remain;
634 if ((shmem_page_offset + page_length) > PAGE_SIZE)
635 page_length = PAGE_SIZE - shmem_page_offset;
637 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
638 (page_to_phys(page) & (1 << 17)) != 0;
640 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
641 user_data, page_do_bit17_swizzling,
646 mutex_unlock(&dev->struct_mutex);
648 if (likely(!i915.prefault_disable) && !prefaulted) {
649 ret = fault_in_multipages_writeable(user_data, remain);
650 /* Userspace is tricking us, but we've already clobbered
651 * its pages with the prefault and promised to write the
652 * data up to the first fault. Hence ignore any errors
653 * and just continue. */
658 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
659 user_data, page_do_bit17_swizzling,
662 mutex_lock(&dev->struct_mutex);
668 remain -= page_length;
669 user_data += page_length;
670 offset += page_length;
674 i915_gem_object_unpin_pages(obj);
680 * Reads data from the object referenced by handle.
682 * On error, the contents of *data are undefined.
685 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
686 struct drm_file *file)
688 struct drm_i915_gem_pread *args = data;
689 struct drm_i915_gem_object *obj;
695 ret = i915_mutex_lock_interruptible(dev);
699 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
700 if (&obj->base == NULL) {
705 /* Bounds check source. */
706 if (args->offset > obj->base.size ||
707 args->size > obj->base.size - args->offset) {
712 trace_i915_gem_object_pread(obj, args->offset, args->size);
714 ret = i915_gem_shmem_pread(dev, obj, args, file);
717 drm_gem_object_unreference(&obj->base);
719 mutex_unlock(&dev->struct_mutex);
723 /* This is the fast write path which cannot handle
724 * page faults in the source data
727 #if 0 /* XXX: buggy on core2 machines */
729 fast_user_write(struct io_mapping *mapping,
730 loff_t page_base, int page_offset,
731 char __user *user_data,
734 void __iomem *vaddr_atomic;
736 unsigned long unwritten;
738 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
739 /* We can use the cpu mem copy function because this is X86. */
740 vaddr = (char __force*)vaddr_atomic + page_offset;
741 unwritten = __copy_from_user_inatomic_nocache(vaddr,
743 io_mapping_unmap_atomic(vaddr_atomic);
749 i915_gem_gtt_write(struct drm_device *dev, struct drm_i915_gem_object *obj,
750 uint64_t data_ptr, uint64_t size, uint64_t offset, struct drm_file *file)
756 * Pass the unaligned physical address and size to pmap_mapdev_attr()
757 * so it can properly calculate whether an extra page needs to be
758 * mapped or not to cover the requested range. The function will
759 * add the page offset into the returned mkva for us.
761 mkva = (vm_offset_t)pmap_mapdev_attr(dev->agp->base +
762 i915_gem_obj_ggtt_offset(obj) + offset, size, PAT_WRITE_COMBINING);
763 ret = -copyin_nofault((void *)(uintptr_t)data_ptr, (char *)mkva, size);
764 pmap_unmapdev(mkva, size);
769 * This is the fast pwrite path, where we copy the data directly from the
770 * user into the GTT, uncached.
773 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
774 struct drm_i915_gem_object *obj,
775 struct drm_i915_gem_pwrite *args,
776 struct drm_file *file)
779 loff_t offset, page_base;
780 char __user *user_data;
781 int page_offset, page_length, ret;
783 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
787 ret = i915_gem_object_set_to_gtt_domain(obj, true);
791 ret = i915_gem_object_put_fence(obj);
795 user_data = to_user_ptr(args->data_ptr);
798 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
801 /* Operation in this page
803 * page_base = page offset within aperture
804 * page_offset = offset within page
805 * page_length = bytes to copy for this page
807 page_base = offset & ~PAGE_MASK;
808 page_offset = offset_in_page(offset);
809 page_length = remain;
810 if ((page_offset + remain) > PAGE_SIZE)
811 page_length = PAGE_SIZE - page_offset;
813 /* If we get a fault while copying data, then (presumably) our
814 * source page isn't available. Return the error and we'll
815 * retry in the slow path.
818 if (fast_user_write(dev_priv->gtt.mappable, page_base,
819 page_offset, user_data, page_length)) {
821 if (i915_gem_gtt_write(dev, obj, args->data_ptr, args->size, args->offset, file)) {
827 remain -= page_length;
828 user_data += page_length;
829 offset += page_length;
833 i915_gem_object_ggtt_unpin(obj);
838 /* Per-page copy function for the shmem pwrite fastpath.
839 * Flushes invalid cachelines before writing to the target if
840 * needs_clflush_before is set and flushes out any written cachelines after
841 * writing if needs_clflush is set. */
843 shmem_pwrite_fast(struct vm_page *page, int shmem_page_offset, int page_length,
844 char __user *user_data,
845 bool page_do_bit17_swizzling,
846 bool needs_clflush_before,
847 bool needs_clflush_after)
852 if (unlikely(page_do_bit17_swizzling))
855 vaddr = kmap_atomic(page);
856 if (needs_clflush_before)
857 drm_clflush_virt_range(vaddr + shmem_page_offset,
859 ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
860 user_data, page_length);
861 if (needs_clflush_after)
862 drm_clflush_virt_range(vaddr + shmem_page_offset,
864 kunmap_atomic(vaddr);
866 return ret ? -EFAULT : 0;
869 /* Only difference to the fast-path function is that this can handle bit17
870 * and uses non-atomic copy and kmap functions. */
872 shmem_pwrite_slow(struct vm_page *page, int shmem_page_offset, int page_length,
873 char __user *user_data,
874 bool page_do_bit17_swizzling,
875 bool needs_clflush_before,
876 bool needs_clflush_after)
882 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
883 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
885 page_do_bit17_swizzling);
886 if (page_do_bit17_swizzling)
887 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
891 ret = __copy_from_user(vaddr + shmem_page_offset,
894 if (needs_clflush_after)
895 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
897 page_do_bit17_swizzling);
900 return ret ? -EFAULT : 0;
904 i915_gem_shmem_pwrite(struct drm_device *dev,
905 struct drm_i915_gem_object *obj,
906 struct drm_i915_gem_pwrite *args,
907 struct drm_file *file)
911 char __user *user_data;
912 int shmem_page_offset, page_length, ret = 0;
913 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
914 int hit_slowpath = 0;
915 int needs_clflush_after = 0;
916 int needs_clflush_before = 0;
919 user_data = to_user_ptr(args->data_ptr);
922 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
924 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
925 /* If we're not in the cpu write domain, set ourself into the gtt
926 * write domain and manually flush cachelines (if required). This
927 * optimizes for the case when the gpu will use the data
928 * right away and we therefore have to clflush anyway. */
929 needs_clflush_after = cpu_write_needs_clflush(obj);
930 ret = i915_gem_object_wait_rendering(obj, false);
934 i915_gem_object_retire(obj);
936 /* Same trick applies to invalidate partially written cachelines read
938 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
939 needs_clflush_before =
940 !cpu_cache_is_coherent(dev, obj->cache_level);
942 ret = i915_gem_object_get_pages(obj);
946 i915_gem_object_pin_pages(obj);
948 offset = args->offset;
951 VM_OBJECT_LOCK(obj->base.vm_obj);
952 vm_object_pip_add(obj->base.vm_obj, 1);
953 for (i = 0; i < (obj->base.size >> PAGE_SHIFT); i++) {
954 struct vm_page *page = obj->pages[i];
955 int partial_cacheline_write;
957 if (i < offset >> PAGE_SHIFT)
963 /* Operation in this page
965 * shmem_page_offset = offset within page in shmem file
966 * page_length = bytes to copy for this page
968 shmem_page_offset = offset_in_page(offset);
970 page_length = remain;
971 if ((shmem_page_offset + page_length) > PAGE_SIZE)
972 page_length = PAGE_SIZE - shmem_page_offset;
974 /* If we don't overwrite a cacheline completely we need to be
975 * careful to have up-to-date data by first clflushing. Don't
976 * overcomplicate things and flush the entire patch. */
977 partial_cacheline_write = needs_clflush_before &&
978 ((shmem_page_offset | page_length)
979 & (cpu_clflush_line_size - 1));
981 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
982 (page_to_phys(page) & (1 << 17)) != 0;
984 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
985 user_data, page_do_bit17_swizzling,
986 partial_cacheline_write,
987 needs_clflush_after);
992 mutex_unlock(&dev->struct_mutex);
993 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
994 user_data, page_do_bit17_swizzling,
995 partial_cacheline_write,
996 needs_clflush_after);
998 mutex_lock(&dev->struct_mutex);
1004 remain -= page_length;
1005 user_data += page_length;
1006 offset += page_length;
1008 vm_object_pip_wakeup(obj->base.vm_obj);
1009 VM_OBJECT_UNLOCK(obj->base.vm_obj);
1012 i915_gem_object_unpin_pages(obj);
1016 * Fixup: Flush cpu caches in case we didn't flush the dirty
1017 * cachelines in-line while writing and the object moved
1018 * out of the cpu write domain while we've dropped the lock.
1020 if (!needs_clflush_after &&
1021 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1022 if (i915_gem_clflush_object(obj, obj->pin_display))
1023 i915_gem_chipset_flush(dev);
1027 if (needs_clflush_after)
1028 i915_gem_chipset_flush(dev);
1034 * Writes data to the object referenced by handle.
1036 * On error, the contents of the buffer that were to be modified are undefined.
1039 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1040 struct drm_file *file)
1042 struct drm_i915_gem_pwrite *args = data;
1043 struct drm_i915_gem_object *obj;
1046 if (args->size == 0)
1049 if (likely(!i915.prefault_disable)) {
1050 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1056 ret = i915_mutex_lock_interruptible(dev);
1060 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1061 if (&obj->base == NULL) {
1066 /* Bounds check destination. */
1067 if (args->offset > obj->base.size ||
1068 args->size > obj->base.size - args->offset) {
1073 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1076 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1077 * it would end up going through the fenced access, and we'll get
1078 * different detiling behavior between reading and writing.
1079 * pread/pwrite currently are reading and writing from the CPU
1080 * perspective, requiring manual detiling by the client.
1082 if (obj->phys_handle) {
1083 ret = i915_gem_phys_pwrite(obj, args, file);
1087 if (obj->tiling_mode == I915_TILING_NONE &&
1088 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1089 cpu_write_needs_clflush(obj)) {
1090 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1091 /* Note that the gtt paths might fail with non-page-backed user
1092 * pointers (e.g. gtt mappings when moving data between
1093 * textures). Fallback to the shmem path in that case. */
1096 if (ret == -EFAULT || ret == -ENOSPC)
1097 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1100 drm_gem_object_unreference(&obj->base);
1102 mutex_unlock(&dev->struct_mutex);
1107 i915_gem_check_wedge(struct i915_gpu_error *error,
1110 if (i915_reset_in_progress(error)) {
1111 /* Non-interruptible callers can't handle -EAGAIN, hence return
1112 * -EIO unconditionally for these. */
1116 /* Recovery complete, but the reset failed ... */
1117 if (i915_terminally_wedged(error))
1127 * Compare seqno against outstanding lazy request. Emit a request if they are
1131 i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno)
1135 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1138 if (seqno == ring->outstanding_lazy_seqno)
1139 ret = i915_add_request(ring, NULL);
1145 static void fake_irq(unsigned long data)
1147 wake_up_process((struct task_struct *)data);
1150 static bool missed_irq(struct drm_i915_private *dev_priv,
1151 struct intel_engine_cs *ring)
1153 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1156 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
1158 if (file_priv == NULL)
1161 return !atomic_xchg(&file_priv->rps_wait_boost, true);
1166 * __wait_seqno - wait until execution of seqno has finished
1167 * @ring: the ring expected to report seqno
1169 * @reset_counter: reset sequence associated with the given seqno
1170 * @interruptible: do an interruptible wait (normally yes)
1171 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1173 * Note: It is of utmost importance that the passed in seqno and reset_counter
1174 * values have been read by the caller in an smp safe manner. Where read-side
1175 * locks are involved, it is sufficient to read the reset_counter before
1176 * unlocking the lock that protects the seqno. For lockless tricks, the
1177 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1180 * Returns 0 if the seqno was found within the alloted time. Else returns the
1181 * errno with remaining time filled in timeout argument.
1183 static int __wait_seqno(struct intel_engine_cs *ring, u32 seqno,
1184 unsigned reset_counter,
1186 struct timespec *timeout,
1187 struct drm_i915_file_private *file_priv)
1189 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1190 struct timespec before, now, wait_time={1,0};
1191 unsigned long timeout_jiffies;
1193 bool wait_forever = true;
1196 WARN(dev_priv->pm.irqs_disabled, "IRQs disabled\n");
1198 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1201 if (timeout != NULL) {
1202 wait_time = *timeout;
1203 wait_forever = false;
1206 timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
1208 if (WARN_ON(!ring->irq_get(ring)))
1211 /* Record current time in case interrupted by signal, or wedged */
1212 trace_i915_gem_request_wait_begin(ring, seqno);
1213 getrawmonotonic(&before);
1216 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1217 i915_reset_in_progress(&dev_priv->gpu_error) || \
1218 reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1221 end = wait_event_interruptible_timeout(ring->irq_queue,
1225 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1228 /* We need to check whether any gpu reset happened in between
1229 * the caller grabbing the seqno and now ... */
1230 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1233 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1235 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1238 } while (end == 0 && wait_forever);
1240 getrawmonotonic(&now);
1242 ring->irq_put(ring);
1243 trace_i915_gem_request_wait_end(ring, seqno);
1247 struct timespec sleep_time = timespec_sub(now, before);
1248 *timeout = timespec_sub(*timeout, sleep_time);
1249 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1250 set_normalized_timespec(timeout, 0, 0);
1255 case -EAGAIN: /* Wedged */
1256 case -ERESTARTSYS: /* Signal */
1258 case 0: /* Timeout */
1259 return -ETIMEDOUT; /* -ETIME on Linux */
1260 default: /* Completed */
1261 WARN_ON(end < 0); /* We're not aware of other errors */
1267 * Waits for a sequence number to be signaled, and cleans up the
1268 * request and object lists appropriately for that event.
1271 i915_wait_seqno(struct intel_engine_cs *ring, uint32_t seqno)
1273 struct drm_device *dev = ring->dev;
1274 struct drm_i915_private *dev_priv = dev->dev_private;
1275 bool interruptible = dev_priv->mm.interruptible;
1278 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1281 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1285 ret = i915_gem_check_olr(ring, seqno);
1289 return __wait_seqno(ring, seqno,
1290 atomic_read(&dev_priv->gpu_error.reset_counter),
1291 interruptible, NULL, NULL);
1295 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1296 struct intel_engine_cs *ring)
1301 /* Manually manage the write flush as we may have not yet
1302 * retired the buffer.
1304 * Note that the last_write_seqno is always the earlier of
1305 * the two (read/write) seqno, so if we haved successfully waited,
1306 * we know we have passed the last write.
1308 obj->last_write_seqno = 0;
1314 * Ensures that all rendering to the object has completed and the object is
1315 * safe to unbind from the GTT or access from the CPU.
1317 static __must_check int
1318 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1321 struct intel_engine_cs *ring = obj->ring;
1325 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1329 ret = i915_wait_seqno(ring, seqno);
1333 return i915_gem_object_wait_rendering__tail(obj, ring);
1336 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1337 * as the object state may change during this call.
1339 static __must_check int
1340 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1341 struct drm_i915_file_private *file_priv,
1344 struct drm_device *dev = obj->base.dev;
1345 struct drm_i915_private *dev_priv = dev->dev_private;
1346 struct intel_engine_cs *ring = obj->ring;
1347 unsigned reset_counter;
1351 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1352 BUG_ON(!dev_priv->mm.interruptible);
1354 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1358 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1362 ret = i915_gem_check_olr(ring, seqno);
1366 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1367 mutex_unlock(&dev->struct_mutex);
1368 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file_priv);
1369 mutex_lock(&dev->struct_mutex);
1373 return i915_gem_object_wait_rendering__tail(obj, ring);
1377 * Called when user space prepares to use an object with the CPU, either
1378 * through the mmap ioctl's mapping or a GTT mapping.
1381 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1382 struct drm_file *file)
1384 struct drm_i915_gem_set_domain *args = data;
1385 struct drm_i915_gem_object *obj;
1386 uint32_t read_domains = args->read_domains;
1387 uint32_t write_domain = args->write_domain;
1390 /* Only handle setting domains to types used by the CPU. */
1391 if (write_domain & I915_GEM_GPU_DOMAINS)
1394 if (read_domains & I915_GEM_GPU_DOMAINS)
1397 /* Having something in the write domain implies it's in the read
1398 * domain, and only that read domain. Enforce that in the request.
1400 if (write_domain != 0 && read_domains != write_domain)
1403 ret = i915_mutex_lock_interruptible(dev);
1407 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1408 if (&obj->base == NULL) {
1413 /* Try to flush the object off the GPU without holding the lock.
1414 * We will repeat the flush holding the lock in the normal manner
1415 * to catch cases where we are gazumped.
1417 ret = i915_gem_object_wait_rendering__nonblocking(obj,
1423 if (read_domains & I915_GEM_DOMAIN_GTT) {
1424 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1426 /* Silently promote "you're not bound, there was nothing to do"
1427 * to success, since the client was just asking us to
1428 * make sure everything was done.
1433 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1437 drm_gem_object_unreference(&obj->base);
1439 mutex_unlock(&dev->struct_mutex);
1444 * Called when user space has done writes to this buffer
1447 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1448 struct drm_file *file)
1450 struct drm_i915_gem_sw_finish *args = data;
1451 struct drm_i915_gem_object *obj;
1454 ret = i915_mutex_lock_interruptible(dev);
1458 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1459 if (&obj->base == NULL) {
1464 /* Pinned buffers may be scanout, so flush the cache */
1465 if (obj->pin_display)
1466 i915_gem_object_flush_cpu_write_domain(obj, true);
1468 drm_gem_object_unreference(&obj->base);
1470 mutex_unlock(&dev->struct_mutex);
1475 * Maps the contents of an object, returning the address it is mapped
1478 * While the mapping holds a reference on the contents of the object, it doesn't
1479 * imply a ref on the object itself.
1482 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1483 struct drm_file *file)
1485 struct drm_i915_gem_mmap *args = data;
1486 struct drm_gem_object *obj;
1488 struct proc *p = curproc;
1489 vm_map_t map = &p->p_vmspace->vm_map;
1493 obj = drm_gem_object_lookup(dev, file, args->handle);
1497 if (args->size == 0)
1500 size = round_page(args->size);
1501 if (map->size + size > p->p_rlimit[RLIMIT_VMEM].rlim_cur) {
1507 * Call hint to ensure that NULL is not returned as a valid address
1508 * and to reduce vm_map traversals. XXX causes instability, use a
1509 * fixed low address as the start point instead to avoid the NULL
1515 * Use 256KB alignment. It is unclear why this matters for a
1516 * virtual address but it appears to fix a number of application/X
1517 * crashes and kms console switching is much faster.
1519 vm_object_hold(obj->vm_obj);
1520 vm_object_reference_locked(obj->vm_obj);
1521 vm_object_drop(obj->vm_obj);
1523 rv = vm_map_find(map, obj->vm_obj, NULL,
1524 args->offset, &addr, args->size,
1525 256 * 1024, /* align */
1527 VM_MAPTYPE_NORMAL, /* maptype */
1528 VM_PROT_READ | VM_PROT_WRITE, /* prot */
1529 VM_PROT_READ | VM_PROT_WRITE, /* max */
1530 MAP_SHARED /* cow */);
1531 if (rv != KERN_SUCCESS) {
1532 vm_object_deallocate(obj->vm_obj);
1533 error = -vm_mmap_to_errno(rv);
1535 args->addr_ptr = (uint64_t)addr;
1538 drm_gem_object_unreference(obj);
1543 * i915_gem_fault - fault a page into the GTT
1545 * vm_obj is locked on entry and expected to be locked on return.
1547 * The vm_pager has placemarked the object with an anonymous memory page
1548 * which we must replace atomically to avoid races against concurrent faults
1549 * on the same page. XXX we currently are unable to do this atomically.
1551 * If we are to return an error we should not touch the anonymous page,
1552 * the caller will deallocate it.
1554 * XXX Most GEM calls appear to be interruptable, but we can't hard loop
1555 * in that case. Release all resources and wait 1 tick before retrying.
1556 * This is a huge problem which needs to be fixed by getting rid of most
1557 * of the interruptability. The linux code does not retry but does appear
1558 * to have some sort of mechanism (VM_FAULT_NOPAGE ?) for the higher level
1559 * to be able to retry.
1563 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1564 * from userspace. The fault handler takes care of binding the object to
1565 * the GTT (if needed), allocating and programming a fence register (again,
1566 * only if needed based on whether the old reg is still valid or the object
1567 * is tiled) and inserting a new PTE into the faulting process.
1569 * Note that the faulting process may involve evicting existing objects
1570 * from the GTT and/or fence registers to make room. So performance may
1571 * suffer if the GTT working set is large or there are few fence registers
1574 * vm_obj is locked on entry and expected to be locked on return. The VM
1575 * pager has placed an anonymous memory page at (obj,offset) which we have
1578 int i915_gem_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot, vm_page_t *mres)
1580 struct drm_i915_gem_object *obj = to_intel_bo(vm_obj->handle);
1581 struct drm_device *dev = obj->base.dev;
1582 struct drm_i915_private *dev_priv = dev->dev_private;
1583 unsigned long page_offset;
1584 vm_page_t m, oldm = NULL;
1587 bool write = !!(prot & VM_PROT_WRITE);
1589 intel_runtime_pm_get(dev_priv);
1591 /* We don't use vmf->pgoff since that has the fake offset */
1592 page_offset = (unsigned long)offset;
1595 ret = i915_mutex_lock_interruptible(dev);
1599 trace_i915_gem_object_fault(obj, page_offset, true, write);
1601 /* Try to flush the object off the GPU first without holding the lock.
1602 * Upon reacquiring the lock, we will perform our sanity checks and then
1603 * repeat the flush holding the lock in the normal manner to catch cases
1604 * where we are gazumped.
1606 ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1610 /* Access to snoopable pages through the GTT is incoherent. */
1611 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1617 * START FREEBSD MAGIC
1619 * Add a pip count to avoid destruction and certain other
1620 * complex operations (such as collapses?) while unlocked.
1623 vm_object_pip_add(vm_obj, 1);
1628 * XXX We must currently remove the placeholder page now to avoid
1629 * a deadlock against a concurrent i915_gem_release_mmap().
1630 * Otherwise concurrent operation will block on the busy page
1631 * while holding locks which we need to obtain.
1633 if (*mres != NULL) {
1635 vm_page_remove(oldm);
1641 VM_OBJECT_UNLOCK(vm_obj);
1646 * Since the object lock was dropped, another thread might have
1647 * faulted on the same GTT address and instantiated the mapping.
1650 VM_OBJECT_LOCK(vm_obj);
1651 m = vm_page_lookup(vm_obj, OFF_TO_IDX(offset));
1654 * Try to busy the page, retry on failure (non-zero ret).
1656 if (vm_page_busy_try(m, false)) {
1657 kprintf("i915_gem_fault: PG_BUSY\n");
1658 VM_OBJECT_UNLOCK(vm_obj);
1659 mutex_unlock(&dev->struct_mutex);
1661 tsleep(&dummy, 0, "delay", 1); /* XXX */
1662 VM_OBJECT_LOCK(vm_obj);
1672 * Object must be unlocked here to avoid deadlock during
1673 * other GEM calls. All goto targets expect the object to
1676 VM_OBJECT_UNLOCK(vm_obj);
1678 /* Now bind it into the GTT if needed */
1679 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
1681 VM_OBJECT_LOCK(vm_obj);
1685 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1687 VM_OBJECT_LOCK(vm_obj);
1691 ret = i915_gem_object_get_fence(obj);
1693 VM_OBJECT_LOCK(vm_obj);
1697 obj->fault_mappable = true;
1700 * Relock object for insertion, leave locked for return.
1702 VM_OBJECT_LOCK(vm_obj);
1703 m = vm_phys_fictitious_to_vm_page(dev->agp->base +
1704 i915_gem_obj_ggtt_offset(obj) +
1710 KASSERT((m->flags & PG_FICTITIOUS) != 0, ("not fictitious %p", m));
1711 KASSERT(m->wire_count == 1, ("wire_count not 1 %p", m));
1714 * Try to busy the page. Fails on non-zero return.
1716 if (vm_page_busy_try(m, false)) {
1717 VM_OBJECT_UNLOCK(vm_obj);
1718 i915_gem_object_ggtt_unpin(obj);
1719 kprintf("i915_gem_fault: PG_BUSY(2)\n");
1720 i915_gem_object_ggtt_unpin(obj);
1721 mutex_unlock(&dev->struct_mutex);
1723 tsleep(&dummy, 0, "delay", 1); /* XXX */
1724 VM_OBJECT_LOCK(vm_obj);
1727 m->valid = VM_PAGE_BITS_ALL;
1730 * Finally, remap it using the new GTT offset.
1732 * (object expected to be in a locked state)
1734 vm_page_insert(m, vm_obj, OFF_TO_IDX(offset));
1738 i915_gem_object_ggtt_unpin(obj);
1739 mutex_unlock(&dev->struct_mutex);
1743 vm_object_pip_wakeup(vm_obj);
1744 return (VM_PAGER_OK);
1747 * ALTERNATIVE ERROR RETURN.
1749 * OBJECT EXPECTED TO BE LOCKED.
1752 i915_gem_object_ggtt_unpin(obj);
1754 mutex_unlock(&dev->struct_mutex);
1758 /* If this -EIO is due to a gpu hang, give the reset code a
1759 * chance to clean up the mess. Otherwise return the proper
1761 if (i915_terminally_wedged(&dev_priv->gpu_error)) {
1762 // ret = VM_FAULT_SIGBUS;
1768 * EAGAIN means the gpu is hung and we'll wait for the error
1769 * handler to reset everything when re-faulting in
1770 * i915_mutex_lock_interruptible.
1775 kprintf("i915_gem_fault: %d\n", ret);
1776 VM_OBJECT_UNLOCK(vm_obj);
1778 tsleep(&dummy, 0, "delay", 1); /* XXX */
1779 VM_OBJECT_LOCK(vm_obj);
1782 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1783 ret = VM_PAGER_ERROR;
1787 intel_runtime_pm_put(dev_priv);
1790 * Error return. We already NULL'd out *mres so we should be able
1791 * to free (oldm) here even though we are returning an error and the
1792 * caller usually handles the freeing.
1797 vm_object_pip_wakeup(vm_obj);
1803 * i915_gem_release_mmap - remove physical page mappings
1804 * @obj: obj in question
1806 * Preserve the reservation of the mmapping with the DRM core code, but
1807 * relinquish ownership of the pages back to the system.
1809 * It is vital that we remove the page mapping if we have mapped a tiled
1810 * object through the GTT and then lose the fence register due to
1811 * resource pressure. Similarly if the object has been moved out of the
1812 * aperture, than pages mapped into userspace must be revoked. Removing the
1813 * mapping will then trigger a page fault on the next user access, allowing
1814 * fixup by i915_gem_fault().
1817 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1823 if (!obj->fault_mappable)
1826 devobj = cdev_pager_lookup(obj);
1827 if (devobj != NULL) {
1828 page_count = OFF_TO_IDX(obj->base.size);
1830 VM_OBJECT_LOCK(devobj);
1831 for (i = 0; i < page_count; i++) {
1832 m = vm_page_lookup_busy_wait(devobj, i, TRUE, "915unm");
1835 cdev_pager_free_page(devobj, m);
1837 VM_OBJECT_UNLOCK(devobj);
1838 vm_object_deallocate(devobj);
1841 obj->fault_mappable = false;
1845 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1847 struct drm_i915_gem_object *obj;
1849 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1850 i915_gem_release_mmap(obj);
1854 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1858 if (INTEL_INFO(dev)->gen >= 4 ||
1859 tiling_mode == I915_TILING_NONE)
1862 /* Previous chips need a power-of-two fence region when tiling */
1863 if (INTEL_INFO(dev)->gen == 3)
1864 gtt_size = 1024*1024;
1866 gtt_size = 512*1024;
1868 while (gtt_size < size)
1875 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1876 * @obj: object to check
1878 * Return the required GTT alignment for an object, taking into account
1879 * potential fence register mapping.
1882 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1883 int tiling_mode, bool fenced)
1886 * Minimum alignment is 4k (GTT page size), but might be greater
1887 * if a fence register is needed for the object.
1889 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1890 tiling_mode == I915_TILING_NONE)
1894 * Previous chips need to be aligned to the size of the smallest
1895 * fence register that can contain the object.
1897 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1900 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1902 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1906 if (drm_vma_node_has_offset(&obj->base.vma_node))
1910 dev_priv->mm.shrinker_no_lock_stealing = true;
1912 ret = drm_gem_create_mmap_offset(&obj->base);
1916 /* Badly fragmented mmap space? The only way we can recover
1917 * space is by destroying unwanted objects. We can't randomly release
1918 * mmap_offsets as userspace expects them to be persistent for the
1919 * lifetime of the objects. The closest we can is to release the
1920 * offsets on purgeable objects by truncating it and marking it purged,
1921 * which prevents userspace from ever using that object again.
1923 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1924 ret = drm_gem_create_mmap_offset(&obj->base);
1928 i915_gem_shrink_all(dev_priv);
1929 ret = drm_gem_create_mmap_offset(&obj->base);
1931 dev_priv->mm.shrinker_no_lock_stealing = false;
1936 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1938 drm_gem_free_mmap_offset(&obj->base);
1942 i915_gem_mmap_gtt(struct drm_file *file,
1943 struct drm_device *dev,
1947 struct drm_i915_private *dev_priv = dev->dev_private;
1948 struct drm_i915_gem_object *obj;
1951 ret = i915_mutex_lock_interruptible(dev);
1955 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1956 if (&obj->base == NULL) {
1961 if (obj->base.size > dev_priv->gtt.mappable_end) {
1966 if (obj->madv != I915_MADV_WILLNEED) {
1967 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1972 ret = i915_gem_object_create_mmap_offset(obj);
1976 *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) |
1977 DRM_GEM_MAPPING_KEY;
1980 drm_gem_object_unreference(&obj->base);
1982 mutex_unlock(&dev->struct_mutex);
1987 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1989 * @data: GTT mapping ioctl data
1990 * @file: GEM object info
1992 * Simply returns the fake offset to userspace so it can mmap it.
1993 * The mmap call will end up in drm_gem_mmap(), which will set things
1994 * up so we can get faults in the handler above.
1996 * The fault handler will take care of binding the object into the GTT
1997 * (since it may have been evicted to make room for something), allocating
1998 * a fence register, and mapping the appropriate aperture address into
2002 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2003 struct drm_file *file)
2005 struct drm_i915_gem_mmap_gtt *args = data;
2007 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
2011 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
2013 return obj->madv == I915_MADV_DONTNEED;
2016 /* Immediately discard the backing storage */
2018 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2022 vm_obj = obj->base.vm_obj;
2023 VM_OBJECT_LOCK(vm_obj);
2024 vm_object_page_remove(vm_obj, 0, 0, false);
2025 VM_OBJECT_UNLOCK(vm_obj);
2027 obj->madv = __I915_MADV_PURGED;
2030 /* Try to discard unwanted pages */
2032 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2035 struct address_space *mapping;
2038 switch (obj->madv) {
2039 case I915_MADV_DONTNEED:
2040 i915_gem_object_truncate(obj);
2041 case __I915_MADV_PURGED:
2046 if (obj->base.filp == NULL)
2049 mapping = file_inode(obj->base.filp)->i_mapping,
2050 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2055 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
2057 int page_count = obj->base.size / PAGE_SIZE;
2063 BUG_ON(obj->madv == __I915_MADV_PURGED);
2065 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2067 /* In the event of a disaster, abandon all caches and
2068 * hope for the best.
2070 WARN_ON(ret != -EIO);
2071 i915_gem_clflush_object(obj, true);
2072 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2075 if (i915_gem_object_needs_bit17_swizzle(obj))
2076 i915_gem_object_save_bit_17_swizzle(obj);
2078 if (obj->madv == I915_MADV_DONTNEED)
2081 for (i = 0; i < page_count; i++) {
2082 struct vm_page *page = obj->pages[i];
2085 set_page_dirty(page);
2087 if (obj->madv == I915_MADV_WILLNEED)
2088 mark_page_accessed(page);
2090 vm_page_busy_wait(obj->pages[i], FALSE, "i915gem");
2091 vm_page_unwire(obj->pages[i], 1);
2092 vm_page_wakeup(obj->pages[i]);
2101 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2103 const struct drm_i915_gem_object_ops *ops = obj->ops;
2105 if (obj->pages == NULL)
2108 if (obj->pages_pin_count)
2111 BUG_ON(i915_gem_obj_bound_any(obj));
2113 /* ->put_pages might need to allocate memory for the bit17 swizzle
2114 * array, hence protect them from being reaped by removing them from gtt
2116 list_del(&obj->global_list);
2118 ops->put_pages(obj);
2121 i915_gem_object_invalidate(obj);
2126 static unsigned long
2127 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
2128 bool purgeable_only)
2130 struct list_head still_in_list;
2131 struct drm_i915_gem_object *obj;
2132 unsigned long count = 0;
2135 * As we may completely rewrite the (un)bound list whilst unbinding
2136 * (due to retiring requests) we have to strictly process only
2137 * one element of the list at the time, and recheck the list
2138 * on every iteration.
2140 * In particular, we must hold a reference whilst removing the
2141 * object as we may end up waiting for and/or retiring the objects.
2142 * This might release the final reference (held by the active list)
2143 * and result in the object being freed from under us. This is
2144 * similar to the precautions the eviction code must take whilst
2147 * Also note that although these lists do not hold a reference to
2148 * the object we can safely grab one here: The final object
2149 * unreferencing and the bound_list are both protected by the
2150 * dev->struct_mutex and so we won't ever be able to observe an
2151 * object on the bound_list with a reference count equals 0.
2153 INIT_LIST_HEAD(&still_in_list);
2154 while (count < target && !list_empty(&dev_priv->mm.unbound_list)) {
2155 obj = list_first_entry(&dev_priv->mm.unbound_list,
2156 typeof(*obj), global_list);
2157 list_move_tail(&obj->global_list, &still_in_list);
2159 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
2162 drm_gem_object_reference(&obj->base);
2164 if (i915_gem_object_put_pages(obj) == 0)
2165 count += obj->base.size >> PAGE_SHIFT;
2167 drm_gem_object_unreference(&obj->base);
2169 list_splice(&still_in_list, &dev_priv->mm.unbound_list);
2171 INIT_LIST_HEAD(&still_in_list);
2172 while (count < target && !list_empty(&dev_priv->mm.bound_list)) {
2173 struct i915_vma *vma, *v;
2175 obj = list_first_entry(&dev_priv->mm.bound_list,
2176 typeof(*obj), global_list);
2177 list_move_tail(&obj->global_list, &still_in_list);
2179 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
2182 drm_gem_object_reference(&obj->base);
2184 list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link)
2185 if (i915_vma_unbind(vma))
2188 if (i915_gem_object_put_pages(obj) == 0)
2189 count += obj->base.size >> PAGE_SHIFT;
2191 drm_gem_object_unreference(&obj->base);
2193 list_splice(&still_in_list, &dev_priv->mm.bound_list);
2198 static unsigned long
2199 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
2201 return __i915_gem_shrink(dev_priv, target, true);
2204 static unsigned long
2205 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
2207 i915_gem_evict_everything(dev_priv->dev);
2208 return __i915_gem_shrink(dev_priv, LONG_MAX, false);
2212 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2214 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2215 int page_count, i, j;
2217 struct vm_page *page;
2219 /* Assert that the object is not currently in any GPU domain. As it
2220 * wasn't in the GTT, there shouldn't be any way it could have been in
2223 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2224 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2226 page_count = obj->base.size / PAGE_SIZE;
2227 obj->pages = kmalloc(page_count * sizeof(vm_page_t), M_DRM,
2230 /* Get the list of pages out of our struct file. They'll be pinned
2231 * at this point until we release them.
2233 * Fail silently without starting the shrinker
2235 vm_obj = obj->base.vm_obj;
2236 VM_OBJECT_LOCK(vm_obj);
2237 for (i = 0; i < page_count; i++) {
2238 page = shmem_read_mapping_page(vm_obj, i);
2240 i915_gem_purge(dev_priv, page_count);
2241 page = shmem_read_mapping_page(vm_obj, i);
2244 /* We've tried hard to allocate the memory by reaping
2245 * our own buffer, now let the real VM do its job and
2246 * go down in flames if truly OOM.
2249 i915_gem_shrink_all(dev_priv);
2250 page = shmem_read_mapping_page(vm_obj, i);
2254 #ifdef CONFIG_SWIOTLB
2255 if (swiotlb_nr_tbl()) {
2257 sg_set_page(sg, page, PAGE_SIZE, 0);
2262 obj->pages[i] = page;
2264 #ifdef CONFIG_SWIOTLB
2265 if (!swiotlb_nr_tbl())
2267 VM_OBJECT_UNLOCK(vm_obj);
2269 if (i915_gem_object_needs_bit17_swizzle(obj))
2270 i915_gem_object_do_bit_17_swizzle(obj);
2275 for (j = 0; j < i; j++) {
2276 page = obj->pages[j];
2277 vm_page_busy_wait(page, FALSE, "i915gem");
2278 vm_page_unwire(page, 0);
2279 vm_page_wakeup(page);
2281 VM_OBJECT_UNLOCK(vm_obj);
2287 /* Ensure that the associated pages are gathered from the backing storage
2288 * and pinned into our object. i915_gem_object_get_pages() may be called
2289 * multiple times before they are released by a single call to
2290 * i915_gem_object_put_pages() - once the pages are no longer referenced
2291 * either as a result of memory pressure (reaping pages under the shrinker)
2292 * or as the object is itself released.
2295 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2297 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2298 const struct drm_i915_gem_object_ops *ops = obj->ops;
2304 if (obj->madv != I915_MADV_WILLNEED) {
2305 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2309 BUG_ON(obj->pages_pin_count);
2311 ret = ops->get_pages(obj);
2315 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2320 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2321 struct intel_engine_cs *ring)
2323 struct drm_device *dev = obj->base.dev;
2324 struct drm_i915_private *dev_priv = dev->dev_private;
2325 u32 seqno = intel_ring_get_seqno(ring);
2327 BUG_ON(ring == NULL);
2328 if (obj->ring != ring && obj->last_write_seqno) {
2329 /* Keep the seqno relative to the current ring */
2330 obj->last_write_seqno = seqno;
2334 /* Add a reference if we're newly entering the active list. */
2336 drm_gem_object_reference(&obj->base);
2340 list_move_tail(&obj->ring_list, &ring->active_list);
2342 obj->last_read_seqno = seqno;
2344 if (obj->fenced_gpu_access) {
2345 obj->last_fenced_seqno = seqno;
2347 /* Bump MRU to take account of the delayed flush */
2348 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2349 struct drm_i915_fence_reg *reg;
2351 reg = &dev_priv->fence_regs[obj->fence_reg];
2352 list_move_tail(®->lru_list,
2353 &dev_priv->mm.fence_list);
2358 void i915_vma_move_to_active(struct i915_vma *vma,
2359 struct intel_engine_cs *ring)
2361 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2362 return i915_gem_object_move_to_active(vma->obj, ring);
2366 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2368 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2369 struct i915_address_space *vm;
2370 struct i915_vma *vma;
2372 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2373 BUG_ON(!obj->active);
2375 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2376 vma = i915_gem_obj_to_vma(obj, vm);
2377 if (vma && !list_empty(&vma->mm_list))
2378 list_move_tail(&vma->mm_list, &vm->inactive_list);
2381 list_del_init(&obj->ring_list);
2384 obj->last_read_seqno = 0;
2385 obj->last_write_seqno = 0;
2386 obj->base.write_domain = 0;
2388 obj->last_fenced_seqno = 0;
2389 obj->fenced_gpu_access = false;
2392 drm_gem_object_unreference(&obj->base);
2394 WARN_ON(i915_verify_lists(dev));
2398 i915_gem_object_retire(struct drm_i915_gem_object *obj)
2400 struct intel_engine_cs *ring = obj->ring;
2405 if (i915_seqno_passed(ring->get_seqno(ring, true),
2406 obj->last_read_seqno))
2407 i915_gem_object_move_to_inactive(obj);
2411 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2413 struct drm_i915_private *dev_priv = dev->dev_private;
2414 struct intel_engine_cs *ring;
2417 /* Carefully retire all requests without writing to the rings */
2418 for_each_ring(ring, dev_priv, i) {
2419 ret = intel_ring_idle(ring);
2423 i915_gem_retire_requests(dev);
2425 /* Finally reset hw state */
2426 for_each_ring(ring, dev_priv, i) {
2427 intel_ring_init_seqno(ring, seqno);
2429 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2430 ring->semaphore.sync_seqno[j] = 0;
2436 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2438 struct drm_i915_private *dev_priv = dev->dev_private;
2444 /* HWS page needs to be set less than what we
2445 * will inject to ring
2447 ret = i915_gem_init_seqno(dev, seqno - 1);
2451 /* Carefully set the last_seqno value so that wrap
2452 * detection still works
2454 dev_priv->next_seqno = seqno;
2455 dev_priv->last_seqno = seqno - 1;
2456 if (dev_priv->last_seqno == 0)
2457 dev_priv->last_seqno--;
2463 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2465 struct drm_i915_private *dev_priv = dev->dev_private;
2467 /* reserve 0 for non-seqno */
2468 if (dev_priv->next_seqno == 0) {
2469 int ret = i915_gem_init_seqno(dev, 0);
2473 dev_priv->next_seqno = 1;
2476 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2480 int __i915_add_request(struct intel_engine_cs *ring,
2481 struct drm_file *file,
2482 struct drm_i915_gem_object *obj,
2485 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2486 struct drm_i915_gem_request *request;
2487 u32 request_ring_position, request_start;
2490 request_start = intel_ring_get_tail(ring);
2492 * Emit any outstanding flushes - execbuf can fail to emit the flush
2493 * after having emitted the batchbuffer command. Hence we need to fix
2494 * things up similar to emitting the lazy request. The difference here
2495 * is that the flush _must_ happen before the next request, no matter
2498 ret = intel_ring_flush_all_caches(ring);
2502 request = ring->preallocated_lazy_request;
2503 if (WARN_ON(request == NULL))
2506 /* Record the position of the start of the request so that
2507 * should we detect the updated seqno part-way through the
2508 * GPU processing the request, we never over-estimate the
2509 * position of the head.
2511 request_ring_position = intel_ring_get_tail(ring);
2513 ret = ring->add_request(ring);
2517 request->seqno = intel_ring_get_seqno(ring);
2518 request->ring = ring;
2519 request->head = request_start;
2520 request->tail = request_ring_position;
2522 /* Whilst this request exists, batch_obj will be on the
2523 * active_list, and so will hold the active reference. Only when this
2524 * request is retired will the the batch_obj be moved onto the
2525 * inactive_list and lose its active reference. Hence we do not need
2526 * to explicitly hold another reference here.
2528 request->batch_obj = obj;
2530 /* Hold a reference to the current context so that we can inspect
2531 * it later in case a hangcheck error event fires.
2533 request->ctx = ring->last_context;
2535 i915_gem_context_reference(request->ctx);
2537 request->emitted_jiffies = jiffies;
2538 list_add_tail(&request->list, &ring->request_list);
2539 request->file_priv = NULL;
2542 struct drm_i915_file_private *file_priv = file->driver_priv;
2544 spin_lock(&file_priv->mm.lock);
2545 request->file_priv = file_priv;
2546 list_add_tail(&request->client_list,
2547 &file_priv->mm.request_list);
2548 spin_unlock(&file_priv->mm.lock);
2551 trace_i915_gem_request_add(ring, request->seqno);
2552 ring->outstanding_lazy_seqno = 0;
2553 ring->preallocated_lazy_request = NULL;
2555 if (!dev_priv->ums.mm_suspended) {
2556 i915_queue_hangcheck(ring->dev);
2558 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2559 queue_delayed_work(dev_priv->wq,
2560 &dev_priv->mm.retire_work,
2561 round_jiffies_up_relative(HZ));
2562 intel_mark_busy(dev_priv->dev);
2566 *out_seqno = request->seqno;
2571 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2573 struct drm_i915_file_private *file_priv = request->file_priv;
2578 spin_lock(&file_priv->mm.lock);
2579 list_del(&request->client_list);
2580 request->file_priv = NULL;
2581 spin_unlock(&file_priv->mm.lock);
2584 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2585 const struct intel_context *ctx)
2587 unsigned long elapsed;
2589 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2591 if (ctx->hang_stats.banned)
2594 if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2595 if (!i915_gem_context_is_default(ctx)) {
2596 DRM_DEBUG("context hanging too fast, banning!\n");
2598 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2599 if (i915_stop_ring_allow_warn(dev_priv))
2600 DRM_ERROR("gpu hanging too fast, banning!\n");
2608 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2609 struct intel_context *ctx,
2612 struct i915_ctx_hang_stats *hs;
2617 hs = &ctx->hang_stats;
2620 hs->banned = i915_context_is_banned(dev_priv, ctx);
2622 hs->guilty_ts = get_seconds();
2624 hs->batch_pending++;
2628 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2630 list_del(&request->list);
2631 i915_gem_request_remove_from_client(request);
2634 i915_gem_context_unreference(request->ctx);
2639 struct drm_i915_gem_request *
2640 i915_gem_find_active_request(struct intel_engine_cs *ring)
2642 struct drm_i915_gem_request *request;
2643 u32 completed_seqno;
2645 completed_seqno = ring->get_seqno(ring, false);
2647 list_for_each_entry(request, &ring->request_list, list) {
2648 if (i915_seqno_passed(completed_seqno, request->seqno))
2657 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2658 struct intel_engine_cs *ring)
2660 struct drm_i915_gem_request *request;
2663 request = i915_gem_find_active_request(ring);
2665 if (request == NULL)
2668 ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2670 i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2672 list_for_each_entry_continue(request, &ring->request_list, list)
2673 i915_set_reset_status(dev_priv, request->ctx, false);
2676 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2677 struct intel_engine_cs *ring)
2679 while (!list_empty(&ring->active_list)) {
2680 struct drm_i915_gem_object *obj;
2682 obj = list_first_entry(&ring->active_list,
2683 struct drm_i915_gem_object,
2686 i915_gem_object_move_to_inactive(obj);
2690 * We must free the requests after all the corresponding objects have
2691 * been moved off active lists. Which is the same order as the normal
2692 * retire_requests function does. This is important if object hold
2693 * implicit references on things like e.g. ppgtt address spaces through
2696 while (!list_empty(&ring->request_list)) {
2697 struct drm_i915_gem_request *request;
2699 request = list_first_entry(&ring->request_list,
2700 struct drm_i915_gem_request,
2703 i915_gem_free_request(request);
2706 /* These may not have been flush before the reset, do so now */
2707 kfree(ring->preallocated_lazy_request);
2708 ring->preallocated_lazy_request = NULL;
2709 ring->outstanding_lazy_seqno = 0;
2712 void i915_gem_restore_fences(struct drm_device *dev)
2714 struct drm_i915_private *dev_priv = dev->dev_private;
2717 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2718 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2721 * Commit delayed tiling changes if we have an object still
2722 * attached to the fence, otherwise just clear the fence.
2725 i915_gem_object_update_fence(reg->obj, reg,
2726 reg->obj->tiling_mode);
2728 i915_gem_write_fence(dev, i, NULL);
2733 void i915_gem_reset(struct drm_device *dev)
2735 struct drm_i915_private *dev_priv = dev->dev_private;
2736 struct intel_engine_cs *ring;
2740 * Before we free the objects from the requests, we need to inspect
2741 * them for finding the guilty party. As the requests only borrow
2742 * their reference to the objects, the inspection must be done first.
2744 for_each_ring(ring, dev_priv, i)
2745 i915_gem_reset_ring_status(dev_priv, ring);
2747 for_each_ring(ring, dev_priv, i)
2748 i915_gem_reset_ring_cleanup(dev_priv, ring);
2750 i915_gem_context_reset(dev);
2752 i915_gem_restore_fences(dev);
2756 * This function clears the request list as sequence numbers are passed.
2759 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2763 if (list_empty(&ring->request_list))
2766 WARN_ON(i915_verify_lists(ring->dev));
2768 seqno = ring->get_seqno(ring, true);
2770 /* Move any buffers on the active list that are no longer referenced
2771 * by the ringbuffer to the flushing/inactive lists as appropriate,
2772 * before we free the context associated with the requests.
2774 while (!list_empty(&ring->active_list)) {
2775 struct drm_i915_gem_object *obj;
2777 obj = list_first_entry(&ring->active_list,
2778 struct drm_i915_gem_object,
2781 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2784 i915_gem_object_move_to_inactive(obj);
2788 while (!list_empty(&ring->request_list)) {
2789 struct drm_i915_gem_request *request;
2791 request = list_first_entry(&ring->request_list,
2792 struct drm_i915_gem_request,
2795 if (!i915_seqno_passed(seqno, request->seqno))
2798 trace_i915_gem_request_retire(ring, request->seqno);
2799 /* We know the GPU must have read the request to have
2800 * sent us the seqno + interrupt, so use the position
2801 * of tail of the request to update the last known position
2804 ring->buffer->last_retired_head = request->tail;
2806 i915_gem_free_request(request);
2809 if (unlikely(ring->trace_irq_seqno &&
2810 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2811 ring->irq_put(ring);
2812 ring->trace_irq_seqno = 0;
2815 WARN_ON(i915_verify_lists(ring->dev));
2819 i915_gem_retire_requests(struct drm_device *dev)
2821 struct drm_i915_private *dev_priv = dev->dev_private;
2822 struct intel_engine_cs *ring;
2826 for_each_ring(ring, dev_priv, i) {
2827 i915_gem_retire_requests_ring(ring);
2828 idle &= list_empty(&ring->request_list);
2832 mod_delayed_work(dev_priv->wq,
2833 &dev_priv->mm.idle_work,
2834 msecs_to_jiffies(100));
2840 i915_gem_retire_work_handler(struct work_struct *work)
2842 struct drm_i915_private *dev_priv =
2843 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2844 struct drm_device *dev = dev_priv->dev;
2847 /* Come back later if the device is busy... */
2849 if (mutex_trylock(&dev->struct_mutex)) {
2850 idle = i915_gem_retire_requests(dev);
2851 mutex_unlock(&dev->struct_mutex);
2854 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2855 round_jiffies_up_relative(HZ));
2859 i915_gem_idle_work_handler(struct work_struct *work)
2861 struct drm_i915_private *dev_priv =
2862 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2864 intel_mark_idle(dev_priv->dev);
2868 * Ensures that an object will eventually get non-busy by flushing any required
2869 * write domains, emitting any outstanding lazy request and retiring and
2870 * completed requests.
2873 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2878 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2882 i915_gem_retire_requests_ring(obj->ring);
2889 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2890 * @DRM_IOCTL_ARGS: standard ioctl arguments
2892 * Returns 0 if successful, else an error is returned with the remaining time in
2893 * the timeout parameter.
2894 * -ETIME: object is still busy after timeout
2895 * -ERESTARTSYS: signal interrupted the wait
2896 * -ENONENT: object doesn't exist
2897 * Also possible, but rare:
2898 * -EAGAIN: GPU wedged
2900 * -ENODEV: Internal IRQ fail
2901 * -E?: The add request failed
2903 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2904 * non-zero timeout parameter the wait ioctl will wait for the given number of
2905 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2906 * without holding struct_mutex the object may become re-busied before this
2907 * function completes. A similar but shorter * race condition exists in the busy
2911 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2913 struct drm_i915_private *dev_priv = dev->dev_private;
2914 struct drm_i915_gem_wait *args = data;
2915 struct drm_i915_gem_object *obj;
2916 struct intel_engine_cs *ring = NULL;
2917 struct timespec timeout_stack, *timeout = NULL;
2918 unsigned reset_counter;
2922 if (args->timeout_ns >= 0) {
2923 timeout_stack = ns_to_timespec(args->timeout_ns);
2924 timeout = &timeout_stack;
2927 ret = i915_mutex_lock_interruptible(dev);
2931 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2932 if (&obj->base == NULL) {
2933 mutex_unlock(&dev->struct_mutex);
2937 /* Need to make sure the object gets inactive eventually. */
2938 ret = i915_gem_object_flush_active(obj);
2943 seqno = obj->last_read_seqno;
2950 /* Do this after OLR check to make sure we make forward progress polling
2951 * on this IOCTL with a 0 timeout (like busy ioctl)
2953 if (!args->timeout_ns) {
2958 drm_gem_object_unreference(&obj->base);
2959 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2960 mutex_unlock(&dev->struct_mutex);
2962 ret = __wait_seqno(ring, seqno, reset_counter, true, timeout, file->driver_priv);
2964 args->timeout_ns = timespec_to_ns(timeout);
2968 drm_gem_object_unreference(&obj->base);
2969 mutex_unlock(&dev->struct_mutex);
2974 * i915_gem_object_sync - sync an object to a ring.
2976 * @obj: object which may be in use on another ring.
2977 * @to: ring we wish to use the object on. May be NULL.
2979 * This code is meant to abstract object synchronization with the GPU.
2980 * Calling with NULL implies synchronizing the object with the CPU
2981 * rather than a particular GPU ring.
2983 * Returns 0 if successful, else propagates up the lower layer error.
2986 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2987 struct intel_engine_cs *to)
2989 struct intel_engine_cs *from = obj->ring;
2993 if (from == NULL || to == from)
2996 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2997 return i915_gem_object_wait_rendering(obj, false);
2999 idx = intel_ring_sync_index(from, to);
3001 seqno = obj->last_read_seqno;
3002 if (seqno <= from->semaphore.sync_seqno[idx])
3005 ret = i915_gem_check_olr(obj->ring, seqno);
3009 trace_i915_gem_ring_sync_to(from, to, seqno);
3010 ret = to->semaphore.sync_to(to, from, seqno);
3012 /* We use last_read_seqno because sync_to()
3013 * might have just caused seqno wrap under
3016 from->semaphore.sync_seqno[idx] = obj->last_read_seqno;
3021 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3023 u32 old_write_domain, old_read_domains;
3025 /* Force a pagefault for domain tracking on next user access */
3026 i915_gem_release_mmap(obj);
3028 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3031 /* Wait for any direct GTT access to complete */
3034 old_read_domains = obj->base.read_domains;
3035 old_write_domain = obj->base.write_domain;
3037 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3038 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3040 trace_i915_gem_object_change_domain(obj,
3045 int i915_vma_unbind(struct i915_vma *vma)
3047 struct drm_i915_gem_object *obj = vma->obj;
3048 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3051 if (list_empty(&vma->vma_link))
3054 if (!drm_mm_node_allocated(&vma->node)) {
3055 i915_gem_vma_destroy(vma);
3062 BUG_ON(obj->pages == NULL);
3064 ret = i915_gem_object_finish_gpu(obj);
3067 /* Continue on if we fail due to EIO, the GPU is hung so we
3068 * should be safe and we need to cleanup or else we might
3069 * cause memory corruption through use-after-free.
3072 if (i915_is_ggtt(vma->vm)) {
3073 i915_gem_object_finish_gtt(obj);
3075 /* release the fence reg _after_ flushing */
3076 ret = i915_gem_object_put_fence(obj);
3081 trace_i915_vma_unbind(vma);
3083 vma->unbind_vma(vma);
3085 i915_gem_gtt_finish_object(obj);
3087 list_del_init(&vma->mm_list);
3088 /* Avoid an unnecessary call to unbind on rebind. */
3089 if (i915_is_ggtt(vma->vm))
3090 obj->map_and_fenceable = true;
3092 drm_mm_remove_node(&vma->node);
3093 i915_gem_vma_destroy(vma);
3095 /* Since the unbound list is global, only move to that list if
3096 * no more VMAs exist. */
3097 if (list_empty(&obj->vma_list))
3098 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3100 /* And finally now the object is completely decoupled from this vma,
3101 * we can drop its hold on the backing storage and allow it to be
3102 * reaped by the shrinker.
3104 i915_gem_object_unpin_pages(obj);
3109 int i915_gpu_idle(struct drm_device *dev)
3111 struct drm_i915_private *dev_priv = dev->dev_private;
3112 struct intel_engine_cs *ring;
3115 /* Flush everything onto the inactive list. */
3116 for_each_ring(ring, dev_priv, i) {
3117 ret = i915_switch_context(ring, ring->default_context);
3121 ret = intel_ring_idle(ring);
3129 static void i965_write_fence_reg(struct drm_device *dev, int reg,
3130 struct drm_i915_gem_object *obj)
3132 struct drm_i915_private *dev_priv = dev->dev_private;
3134 int fence_pitch_shift;
3136 if (INTEL_INFO(dev)->gen >= 6) {
3137 fence_reg = FENCE_REG_SANDYBRIDGE_0;
3138 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
3140 fence_reg = FENCE_REG_965_0;
3141 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
3144 fence_reg += reg * 8;
3146 /* To w/a incoherency with non-atomic 64-bit register updates,
3147 * we split the 64-bit update into two 32-bit writes. In order
3148 * for a partial fence not to be evaluated between writes, we
3149 * precede the update with write to turn off the fence register,
3150 * and only enable the fence as the last step.
3152 * For extra levels of paranoia, we make sure each step lands
3153 * before applying the next step.
3155 I915_WRITE(fence_reg, 0);
3156 POSTING_READ(fence_reg);
3159 u32 size = i915_gem_obj_ggtt_size(obj);
3162 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
3164 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
3165 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
3166 if (obj->tiling_mode == I915_TILING_Y)
3167 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3168 val |= I965_FENCE_REG_VALID;
3170 I915_WRITE(fence_reg + 4, val >> 32);
3171 POSTING_READ(fence_reg + 4);
3173 I915_WRITE(fence_reg + 0, val);
3174 POSTING_READ(fence_reg);
3176 I915_WRITE(fence_reg + 4, 0);
3177 POSTING_READ(fence_reg + 4);
3181 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3182 struct drm_i915_gem_object *obj)
3184 struct drm_i915_private *dev_priv = dev->dev_private;
3188 u32 size = i915_gem_obj_ggtt_size(obj);
3192 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3193 (size & -size) != size ||
3194 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3195 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3196 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3198 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3203 /* Note: pitch better be a power of two tile widths */
3204 pitch_val = obj->stride / tile_width;
3205 pitch_val = ffs(pitch_val) - 1;
3207 val = i915_gem_obj_ggtt_offset(obj);
3208 if (obj->tiling_mode == I915_TILING_Y)
3209 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3210 val |= I915_FENCE_SIZE_BITS(size);
3211 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3212 val |= I830_FENCE_REG_VALID;
3217 reg = FENCE_REG_830_0 + reg * 4;
3219 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3221 I915_WRITE(reg, val);
3225 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3226 struct drm_i915_gem_object *obj)
3228 struct drm_i915_private *dev_priv = dev->dev_private;
3232 u32 size = i915_gem_obj_ggtt_size(obj);
3235 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3236 (size & -size) != size ||
3237 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3238 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3239 i915_gem_obj_ggtt_offset(obj), size);
3241 pitch_val = obj->stride / 128;
3242 pitch_val = ffs(pitch_val) - 1;
3244 val = i915_gem_obj_ggtt_offset(obj);
3245 if (obj->tiling_mode == I915_TILING_Y)
3246 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3247 val |= I830_FENCE_SIZE_BITS(size);
3248 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3249 val |= I830_FENCE_REG_VALID;
3253 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3254 POSTING_READ(FENCE_REG_830_0 + reg * 4);
3257 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3259 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3262 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3263 struct drm_i915_gem_object *obj)
3265 struct drm_i915_private *dev_priv = dev->dev_private;
3267 /* Ensure that all CPU reads are completed before installing a fence
3268 * and all writes before removing the fence.
3270 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3273 WARN(obj && (!obj->stride || !obj->tiling_mode),
3274 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3275 obj->stride, obj->tiling_mode);
3277 switch (INTEL_INFO(dev)->gen) {
3282 case 4: i965_write_fence_reg(dev, reg, obj); break;
3283 case 3: i915_write_fence_reg(dev, reg, obj); break;
3284 case 2: i830_write_fence_reg(dev, reg, obj); break;
3288 /* And similarly be paranoid that no direct access to this region
3289 * is reordered to before the fence is installed.
3291 if (i915_gem_object_needs_mb(obj))
3295 static inline int fence_number(struct drm_i915_private *dev_priv,
3296 struct drm_i915_fence_reg *fence)
3298 return fence - dev_priv->fence_regs;
3301 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3302 struct drm_i915_fence_reg *fence,
3305 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3306 int reg = fence_number(dev_priv, fence);
3308 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3311 obj->fence_reg = reg;
3313 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3315 obj->fence_reg = I915_FENCE_REG_NONE;
3317 list_del_init(&fence->lru_list);
3319 obj->fence_dirty = false;
3323 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3325 if (obj->last_fenced_seqno) {
3326 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
3330 obj->last_fenced_seqno = 0;
3333 obj->fenced_gpu_access = false;
3338 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3340 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3341 struct drm_i915_fence_reg *fence;
3344 ret = i915_gem_object_wait_fence(obj);
3348 if (obj->fence_reg == I915_FENCE_REG_NONE)
3351 fence = &dev_priv->fence_regs[obj->fence_reg];
3353 if (WARN_ON(fence->pin_count))
3356 i915_gem_object_fence_lost(obj);
3357 i915_gem_object_update_fence(obj, fence, false);
3362 static struct drm_i915_fence_reg *
3363 i915_find_fence_reg(struct drm_device *dev)
3365 struct drm_i915_private *dev_priv = dev->dev_private;
3366 struct drm_i915_fence_reg *reg, *avail;
3369 /* First try to find a free reg */
3371 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3372 reg = &dev_priv->fence_regs[i];
3376 if (!reg->pin_count)
3383 /* None available, try to steal one or wait for a user to finish */
3384 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3392 /* Wait for completion of pending flips which consume fences */
3393 if (intel_has_pending_fb_unpin(dev))
3394 return ERR_PTR(-EAGAIN);
3396 return ERR_PTR(-EDEADLK);
3400 * i915_gem_object_get_fence - set up fencing for an object
3401 * @obj: object to map through a fence reg
3403 * When mapping objects through the GTT, userspace wants to be able to write
3404 * to them without having to worry about swizzling if the object is tiled.
3405 * This function walks the fence regs looking for a free one for @obj,
3406 * stealing one if it can't find any.
3408 * It then sets up the reg based on the object's properties: address, pitch
3409 * and tiling format.
3411 * For an untiled surface, this removes any existing fence.
3414 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3416 struct drm_device *dev = obj->base.dev;
3417 struct drm_i915_private *dev_priv = dev->dev_private;
3418 bool enable = obj->tiling_mode != I915_TILING_NONE;
3419 struct drm_i915_fence_reg *reg;
3422 /* Have we updated the tiling parameters upon the object and so
3423 * will need to serialise the write to the associated fence register?
3425 if (obj->fence_dirty) {
3426 ret = i915_gem_object_wait_fence(obj);
3431 /* Just update our place in the LRU if our fence is getting reused. */
3432 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3433 reg = &dev_priv->fence_regs[obj->fence_reg];
3434 if (!obj->fence_dirty) {
3435 list_move_tail(®->lru_list,
3436 &dev_priv->mm.fence_list);
3439 } else if (enable) {
3440 reg = i915_find_fence_reg(dev);
3442 return PTR_ERR(reg);
3445 struct drm_i915_gem_object *old = reg->obj;
3447 ret = i915_gem_object_wait_fence(old);
3451 i915_gem_object_fence_lost(old);
3456 i915_gem_object_update_fence(obj, reg, enable);
3461 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3462 struct drm_mm_node *gtt_space,
3463 unsigned long cache_level)
3465 struct drm_mm_node *other;
3467 /* On non-LLC machines we have to be careful when putting differing
3468 * types of snoopable memory together to avoid the prefetcher
3469 * crossing memory domains and dying.
3474 if (!drm_mm_node_allocated(gtt_space))
3477 if (list_empty(>t_space->node_list))
3480 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3481 if (other->allocated && !other->hole_follows && other->color != cache_level)
3484 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3485 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3491 static void i915_gem_verify_gtt(struct drm_device *dev)
3494 struct drm_i915_private *dev_priv = dev->dev_private;
3495 struct drm_i915_gem_object *obj;
3498 list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3499 if (obj->gtt_space == NULL) {
3500 printk(KERN_ERR "object found on GTT list with no space reserved\n");
3505 if (obj->cache_level != obj->gtt_space->color) {
3506 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3507 i915_gem_obj_ggtt_offset(obj),
3508 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3510 obj->gtt_space->color);
3515 if (!i915_gem_valid_gtt_space(dev,
3517 obj->cache_level)) {
3518 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3519 i915_gem_obj_ggtt_offset(obj),
3520 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3532 * Finds free space in the GTT aperture and binds the object there.
3534 static struct i915_vma *
3535 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3536 struct i915_address_space *vm,
3540 struct drm_device *dev = obj->base.dev;
3541 struct drm_i915_private *dev_priv = dev->dev_private;
3542 u32 size, fence_size, fence_alignment, unfenced_alignment;
3543 unsigned long start =
3544 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3546 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3547 struct i915_vma *vma;
3550 fence_size = i915_gem_get_gtt_size(dev,
3553 fence_alignment = i915_gem_get_gtt_alignment(dev,
3555 obj->tiling_mode, true);
3556 unfenced_alignment =
3557 i915_gem_get_gtt_alignment(dev,
3559 obj->tiling_mode, false);
3562 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3564 if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3565 DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
3566 return ERR_PTR(-EINVAL);
3569 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3571 /* If the object is bigger than the entire aperture, reject it early
3572 * before evicting everything in a vain attempt to find space.
3574 if (obj->base.size > end) {
3575 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3577 flags & PIN_MAPPABLE ? "mappable" : "total",
3579 return ERR_PTR(-E2BIG);
3582 ret = i915_gem_object_get_pages(obj);
3584 return ERR_PTR(ret);
3586 i915_gem_object_pin_pages(obj);
3588 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3593 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3597 DRM_MM_SEARCH_DEFAULT,
3598 DRM_MM_CREATE_DEFAULT);
3600 ret = i915_gem_evict_something(dev, vm, size, alignment,
3609 if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3610 obj->cache_level))) {
3612 goto err_remove_node;
3615 ret = i915_gem_gtt_prepare_object(obj);
3617 goto err_remove_node;
3619 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3620 list_add_tail(&vma->mm_list, &vm->inactive_list);
3622 if (i915_is_ggtt(vm)) {
3623 bool mappable, fenceable;
3625 fenceable = (vma->node.size == fence_size &&
3626 (vma->node.start & (fence_alignment - 1)) == 0);
3628 mappable = (vma->node.start + obj->base.size <=
3629 dev_priv->gtt.mappable_end);
3631 obj->map_and_fenceable = mappable && fenceable;
3634 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
3636 trace_i915_vma_bind(vma, flags);
3637 vma->bind_vma(vma, obj->cache_level,
3638 flags & (PIN_MAPPABLE | PIN_GLOBAL) ? GLOBAL_BIND : 0);
3640 i915_gem_verify_gtt(dev);
3644 drm_mm_remove_node(&vma->node);
3646 i915_gem_vma_destroy(vma);
3649 i915_gem_object_unpin_pages(obj);
3654 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3657 /* If we don't have a page list set up, then we're not pinned
3658 * to GPU, and we can ignore the cache flush because it'll happen
3659 * again at bind time.
3661 if (obj->pages == NULL)
3665 * Stolen memory is always coherent with the GPU as it is explicitly
3666 * marked as wc by the system, or the system is cache-coherent.
3671 /* If the GPU is snooping the contents of the CPU cache,
3672 * we do not need to manually clear the CPU cache lines. However,
3673 * the caches are only snooped when the render cache is
3674 * flushed/invalidated. As we always have to emit invalidations
3675 * and flushes when moving into and out of the RENDER domain, correct
3676 * snooping behaviour occurs naturally as the result of our domain
3679 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3682 trace_i915_gem_object_clflush(obj);
3683 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
3688 /** Flushes the GTT write domain for the object if it's dirty. */
3690 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3692 uint32_t old_write_domain;
3694 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3697 /* No actual flushing is required for the GTT write domain. Writes
3698 * to it immediately go to main memory as far as we know, so there's
3699 * no chipset flush. It also doesn't land in render cache.
3701 * However, we do have to enforce the order so that all writes through
3702 * the GTT land before any writes to the device, such as updates to
3707 old_write_domain = obj->base.write_domain;
3708 obj->base.write_domain = 0;
3710 trace_i915_gem_object_change_domain(obj,
3711 obj->base.read_domains,
3715 /** Flushes the CPU write domain for the object if it's dirty. */
3717 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3720 uint32_t old_write_domain;
3722 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3725 if (i915_gem_clflush_object(obj, force))
3726 i915_gem_chipset_flush(obj->base.dev);
3728 old_write_domain = obj->base.write_domain;
3729 obj->base.write_domain = 0;
3731 trace_i915_gem_object_change_domain(obj,
3732 obj->base.read_domains,
3737 * Moves a single object to the GTT read, and possibly write domain.
3739 * This function returns when the move is complete, including waiting on
3743 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3745 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3746 uint32_t old_write_domain, old_read_domains;
3749 /* Not valid to be called on unbound objects. */
3750 if (!i915_gem_obj_bound_any(obj))
3753 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3756 ret = i915_gem_object_wait_rendering(obj, !write);
3760 i915_gem_object_retire(obj);
3761 i915_gem_object_flush_cpu_write_domain(obj, false);
3763 /* Serialise direct access to this object with the barriers for
3764 * coherent writes from the GPU, by effectively invalidating the
3765 * GTT domain upon first access.
3767 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3770 old_write_domain = obj->base.write_domain;
3771 old_read_domains = obj->base.read_domains;
3773 /* It should now be out of any other write domains, and we can update
3774 * the domain values for our changes.
3776 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3777 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3779 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3780 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3784 trace_i915_gem_object_change_domain(obj,
3788 /* And bump the LRU for this access */
3789 if (i915_gem_object_is_inactive(obj)) {
3790 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3792 list_move_tail(&vma->mm_list,
3793 &dev_priv->gtt.base.inactive_list);
3800 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3801 enum i915_cache_level cache_level)
3803 struct drm_device *dev = obj->base.dev;
3804 struct i915_vma *vma, *next;
3807 if (obj->cache_level == cache_level)
3810 if (i915_gem_obj_is_pinned(obj)) {
3811 DRM_DEBUG("can not change the cache level of pinned objects\n");
3815 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3816 if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3817 ret = i915_vma_unbind(vma);
3823 if (i915_gem_obj_bound_any(obj)) {
3824 ret = i915_gem_object_finish_gpu(obj);
3828 i915_gem_object_finish_gtt(obj);
3830 /* Before SandyBridge, you could not use tiling or fence
3831 * registers with snooped memory, so relinquish any fences
3832 * currently pointing to our region in the aperture.
3834 if (INTEL_INFO(dev)->gen < 6) {
3835 ret = i915_gem_object_put_fence(obj);
3840 list_for_each_entry(vma, &obj->vma_list, vma_link)
3841 if (drm_mm_node_allocated(&vma->node))
3842 vma->bind_vma(vma, cache_level,
3843 obj->has_global_gtt_mapping ? GLOBAL_BIND : 0);
3846 list_for_each_entry(vma, &obj->vma_list, vma_link)
3847 vma->node.color = cache_level;
3848 obj->cache_level = cache_level;
3850 if (cpu_write_needs_clflush(obj)) {
3851 u32 old_read_domains, old_write_domain;
3853 /* If we're coming from LLC cached, then we haven't
3854 * actually been tracking whether the data is in the
3855 * CPU cache or not, since we only allow one bit set
3856 * in obj->write_domain and have been skipping the clflushes.
3857 * Just set it to the CPU cache for now.
3859 i915_gem_object_retire(obj);
3860 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3862 old_read_domains = obj->base.read_domains;
3863 old_write_domain = obj->base.write_domain;
3865 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3866 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3868 trace_i915_gem_object_change_domain(obj,
3873 i915_gem_verify_gtt(dev);
3877 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3878 struct drm_file *file)
3880 struct drm_i915_gem_caching *args = data;
3881 struct drm_i915_gem_object *obj;
3884 ret = i915_mutex_lock_interruptible(dev);
3888 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3889 if (&obj->base == NULL) {
3894 switch (obj->cache_level) {
3895 case I915_CACHE_LLC:
3896 case I915_CACHE_L3_LLC:
3897 args->caching = I915_CACHING_CACHED;
3901 args->caching = I915_CACHING_DISPLAY;
3905 args->caching = I915_CACHING_NONE;
3909 drm_gem_object_unreference(&obj->base);
3911 mutex_unlock(&dev->struct_mutex);
3915 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3916 struct drm_file *file)
3918 struct drm_i915_gem_caching *args = data;
3919 struct drm_i915_gem_object *obj;
3920 enum i915_cache_level level;
3923 switch (args->caching) {
3924 case I915_CACHING_NONE:
3925 level = I915_CACHE_NONE;
3927 case I915_CACHING_CACHED:
3928 level = I915_CACHE_LLC;
3930 case I915_CACHING_DISPLAY:
3931 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3937 ret = i915_mutex_lock_interruptible(dev);
3941 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3942 if (&obj->base == NULL) {
3947 ret = i915_gem_object_set_cache_level(obj, level);
3949 drm_gem_object_unreference(&obj->base);
3951 mutex_unlock(&dev->struct_mutex);
3955 static bool is_pin_display(struct drm_i915_gem_object *obj)
3957 struct i915_vma *vma;
3959 if (list_empty(&obj->vma_list))
3962 vma = i915_gem_obj_to_ggtt(obj);
3966 /* There are 3 sources that pin objects:
3967 * 1. The display engine (scanouts, sprites, cursors);
3968 * 2. Reservations for execbuffer;
3971 * We can ignore reservations as we hold the struct_mutex and
3972 * are only called outside of the reservation path. The user
3973 * can only increment pin_count once, and so if after
3974 * subtracting the potential reference by the user, any pin_count
3975 * remains, it must be due to another use by the display engine.
3977 return vma->pin_count - !!obj->user_pin_count;
3981 * Prepare buffer for display plane (scanout, cursors, etc).
3982 * Can be called from an uninterruptible phase (modesetting) and allows
3983 * any flushes to be pipelined (for pageflips).
3986 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3988 struct intel_engine_cs *pipelined)
3990 u32 old_read_domains, old_write_domain;
3991 bool was_pin_display;
3994 if (pipelined != obj->ring) {
3995 ret = i915_gem_object_sync(obj, pipelined);
4000 /* Mark the pin_display early so that we account for the
4001 * display coherency whilst setting up the cache domains.
4003 was_pin_display = obj->pin_display;
4004 obj->pin_display = true;
4006 /* The display engine is not coherent with the LLC cache on gen6. As
4007 * a result, we make sure that the pinning that is about to occur is
4008 * done with uncached PTEs. This is lowest common denominator for all
4011 * However for gen6+, we could do better by using the GFDT bit instead
4012 * of uncaching, which would allow us to flush all the LLC-cached data
4013 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
4015 ret = i915_gem_object_set_cache_level(obj,
4016 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
4018 goto err_unpin_display;
4020 /* As the user may map the buffer once pinned in the display plane
4021 * (e.g. libkms for the bootup splash), we have to ensure that we
4022 * always use map_and_fenceable for all scanout buffers.
4024 ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
4026 goto err_unpin_display;
4028 i915_gem_object_flush_cpu_write_domain(obj, true);
4030 old_write_domain = obj->base.write_domain;
4031 old_read_domains = obj->base.read_domains;
4033 /* It should now be out of any other write domains, and we can update
4034 * the domain values for our changes.
4036 obj->base.write_domain = 0;
4037 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
4039 trace_i915_gem_object_change_domain(obj,
4046 WARN_ON(was_pin_display != is_pin_display(obj));
4047 obj->pin_display = was_pin_display;
4052 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
4054 i915_gem_object_ggtt_unpin(obj);
4055 obj->pin_display = is_pin_display(obj);
4059 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
4063 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
4066 ret = i915_gem_object_wait_rendering(obj, false);
4070 /* Ensure that we invalidate the GPU's caches and TLBs. */
4071 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
4076 * Moves a single object to the CPU read, and possibly write domain.
4078 * This function returns when the move is complete, including waiting on
4082 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4084 uint32_t old_write_domain, old_read_domains;
4087 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4090 ret = i915_gem_object_wait_rendering(obj, !write);
4094 i915_gem_object_retire(obj);
4095 i915_gem_object_flush_gtt_write_domain(obj);
4097 old_write_domain = obj->base.write_domain;
4098 old_read_domains = obj->base.read_domains;
4100 /* Flush the CPU cache if it's still invalid. */
4101 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4102 i915_gem_clflush_object(obj, false);
4104 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4107 /* It should now be out of any other write domains, and we can update
4108 * the domain values for our changes.
4110 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4112 /* If we're writing through the CPU, then the GPU read domains will
4113 * need to be invalidated at next use.
4116 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4117 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4120 trace_i915_gem_object_change_domain(obj,
4127 /* Throttle our rendering by waiting until the ring has completed our requests
4128 * emitted over 20 msec ago.
4130 * Note that if we were to use the current jiffies each time around the loop,
4131 * we wouldn't escape the function with any frames outstanding if the time to
4132 * render a frame was over 20ms.
4134 * This should get us reasonable parallelism between CPU and GPU but also
4135 * relatively low latency when blocking on a particular request to finish.
4138 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4140 struct drm_i915_private *dev_priv = dev->dev_private;
4141 struct drm_i915_file_private *file_priv = file->driver_priv;
4142 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
4143 struct drm_i915_gem_request *request;
4144 struct intel_engine_cs *ring = NULL;
4145 unsigned reset_counter;
4149 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4153 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4157 spin_lock(&file_priv->mm.lock);
4158 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4159 if (time_after_eq(request->emitted_jiffies, recent_enough))
4162 ring = request->ring;
4163 seqno = request->seqno;
4165 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4166 spin_unlock(&file_priv->mm.lock);
4171 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL);
4173 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4179 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4181 struct drm_i915_gem_object *obj = vma->obj;
4184 vma->node.start & (alignment - 1))
4187 if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4190 if (flags & PIN_OFFSET_BIAS &&
4191 vma->node.start < (flags & PIN_OFFSET_MASK))
4198 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4199 struct i915_address_space *vm,
4203 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4204 struct i915_vma *vma;
4207 if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4210 if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4213 vma = i915_gem_obj_to_vma(obj, vm);
4215 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4218 if (i915_vma_misplaced(vma, alignment, flags)) {
4219 WARN(vma->pin_count,
4220 "bo is already pinned with incorrect alignment:"
4221 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4222 " obj->map_and_fenceable=%d\n",
4223 i915_gem_obj_offset(obj, vm), alignment,
4224 !!(flags & PIN_MAPPABLE),
4225 obj->map_and_fenceable);
4226 ret = i915_vma_unbind(vma);
4234 if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4235 vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags);
4237 return PTR_ERR(vma);
4240 if (flags & PIN_GLOBAL && !obj->has_global_gtt_mapping)
4241 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
4244 if (flags & PIN_MAPPABLE)
4245 obj->pin_mappable |= true;
4251 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
4253 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
4256 BUG_ON(vma->pin_count == 0);
4257 BUG_ON(!i915_gem_obj_ggtt_bound(obj));
4259 if (--vma->pin_count == 0)
4260 obj->pin_mappable = false;
4264 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4266 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4267 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4268 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4270 WARN_ON(!ggtt_vma ||
4271 dev_priv->fence_regs[obj->fence_reg].pin_count >
4272 ggtt_vma->pin_count);
4273 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4280 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4282 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4283 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4284 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4285 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4290 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4291 struct drm_file *file)
4293 struct drm_i915_gem_pin *args = data;
4294 struct drm_i915_gem_object *obj;
4297 if (INTEL_INFO(dev)->gen >= 6)
4300 ret = i915_mutex_lock_interruptible(dev);
4304 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4305 if (&obj->base == NULL) {
4310 if (obj->madv != I915_MADV_WILLNEED) {
4311 DRM_DEBUG("Attempting to pin a purgeable buffer\n");
4316 if (obj->pin_filp != NULL && obj->pin_filp != file) {
4317 DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n",
4323 if (obj->user_pin_count == ULONG_MAX) {
4328 if (obj->user_pin_count == 0) {
4329 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE);
4334 obj->user_pin_count++;
4335 obj->pin_filp = file;
4337 args->offset = i915_gem_obj_ggtt_offset(obj);
4339 drm_gem_object_unreference(&obj->base);
4341 mutex_unlock(&dev->struct_mutex);
4346 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4347 struct drm_file *file)
4349 struct drm_i915_gem_pin *args = data;
4350 struct drm_i915_gem_object *obj;
4353 ret = i915_mutex_lock_interruptible(dev);
4357 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4358 if (&obj->base == NULL) {
4363 if (obj->pin_filp != file) {
4364 DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4369 obj->user_pin_count--;
4370 if (obj->user_pin_count == 0) {
4371 obj->pin_filp = NULL;
4372 i915_gem_object_ggtt_unpin(obj);
4376 drm_gem_object_unreference(&obj->base);
4378 mutex_unlock(&dev->struct_mutex);
4383 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4384 struct drm_file *file)
4386 struct drm_i915_gem_busy *args = data;
4387 struct drm_i915_gem_object *obj;
4390 ret = i915_mutex_lock_interruptible(dev);
4394 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4395 if (&obj->base == NULL) {
4400 /* Count all active objects as busy, even if they are currently not used
4401 * by the gpu. Users of this interface expect objects to eventually
4402 * become non-busy without any further actions, therefore emit any
4403 * necessary flushes here.
4405 ret = i915_gem_object_flush_active(obj);
4407 args->busy = obj->active;
4409 args->busy |= intel_ring_flag(obj->ring) << 16;
4412 drm_gem_object_unreference(&obj->base);
4414 mutex_unlock(&dev->struct_mutex);
4419 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4420 struct drm_file *file_priv)
4422 return i915_gem_ring_throttle(dev, file_priv);
4426 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4427 struct drm_file *file_priv)
4429 struct drm_i915_gem_madvise *args = data;
4430 struct drm_i915_gem_object *obj;
4433 switch (args->madv) {
4434 case I915_MADV_DONTNEED:
4435 case I915_MADV_WILLNEED:
4441 ret = i915_mutex_lock_interruptible(dev);
4445 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4446 if (&obj->base == NULL) {
4451 if (i915_gem_obj_is_pinned(obj)) {
4456 if (obj->madv != __I915_MADV_PURGED)
4457 obj->madv = args->madv;
4459 /* if the object is no longer attached, discard its backing storage */
4460 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4461 i915_gem_object_truncate(obj);
4463 args->retained = obj->madv != __I915_MADV_PURGED;
4466 drm_gem_object_unreference(&obj->base);
4468 mutex_unlock(&dev->struct_mutex);
4472 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4473 const struct drm_i915_gem_object_ops *ops)
4475 INIT_LIST_HEAD(&obj->global_list);
4476 INIT_LIST_HEAD(&obj->ring_list);
4477 INIT_LIST_HEAD(&obj->obj_exec_link);
4478 INIT_LIST_HEAD(&obj->vma_list);
4482 obj->fence_reg = I915_FENCE_REG_NONE;
4483 obj->madv = I915_MADV_WILLNEED;
4484 /* Avoid an unnecessary call to unbind on the first bind. */
4485 obj->map_and_fenceable = true;
4487 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4490 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4491 .get_pages = i915_gem_object_get_pages_gtt,
4492 .put_pages = i915_gem_object_put_pages_gtt,
4495 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4498 struct drm_i915_gem_object *obj;
4500 struct address_space *mapping;
4504 obj = i915_gem_object_alloc(dev);
4508 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4509 i915_gem_object_free(obj);
4514 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4515 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4516 /* 965gm cannot relocate objects above 4GiB. */
4517 mask &= ~__GFP_HIGHMEM;
4518 mask |= __GFP_DMA32;
4521 mapping = file_inode(obj->base.filp)->i_mapping;
4522 mapping_set_gfp_mask(mapping, mask);
4525 i915_gem_object_init(obj, &i915_gem_object_ops);
4527 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4528 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4531 /* On some devices, we can have the GPU use the LLC (the CPU
4532 * cache) for about a 10% performance improvement
4533 * compared to uncached. Graphics requests other than
4534 * display scanout are coherent with the CPU in
4535 * accessing this cache. This means in this mode we
4536 * don't need to clflush on the CPU side, and on the
4537 * GPU side we only need to flush internal caches to
4538 * get data visible to the CPU.
4540 * However, we maintain the display planes as UC, and so
4541 * need to rebind when first used as such.
4543 obj->cache_level = I915_CACHE_LLC;
4545 obj->cache_level = I915_CACHE_NONE;
4547 trace_i915_gem_object_create(obj);
4552 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4554 /* If we are the last user of the backing storage (be it shmemfs
4555 * pages or stolen etc), we know that the pages are going to be
4556 * immediately released. In this case, we can then skip copying
4557 * back the contents from the GPU.
4560 if (obj->madv != I915_MADV_WILLNEED)
4563 if (obj->base.vm_obj == NULL)
4566 /* At first glance, this looks racy, but then again so would be
4567 * userspace racing mmap against close. However, the first external
4568 * reference to the filp can only be obtained through the
4569 * i915_gem_mmap_ioctl() which safeguards us against the user
4570 * acquiring such a reference whilst we are in the middle of
4571 * freeing the object.
4574 return atomic_long_read(&obj->base.filp->f_count) == 1;
4580 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4582 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4583 struct drm_device *dev = obj->base.dev;
4584 struct drm_i915_private *dev_priv = dev->dev_private;
4585 struct i915_vma *vma, *next;
4587 intel_runtime_pm_get(dev_priv);
4589 trace_i915_gem_object_destroy(obj);
4591 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4595 ret = i915_vma_unbind(vma);
4596 if (WARN_ON(ret == -ERESTARTSYS)) {
4597 bool was_interruptible;
4599 was_interruptible = dev_priv->mm.interruptible;
4600 dev_priv->mm.interruptible = false;
4602 WARN_ON(i915_vma_unbind(vma));
4604 dev_priv->mm.interruptible = was_interruptible;
4608 i915_gem_object_detach_phys(obj);
4610 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4611 * before progressing. */
4613 i915_gem_object_unpin_pages(obj);
4615 if (WARN_ON(obj->pages_pin_count))
4616 obj->pages_pin_count = 0;
4617 if (discard_backing_storage(obj))
4618 obj->madv = I915_MADV_DONTNEED;
4619 i915_gem_object_put_pages(obj);
4620 i915_gem_object_free_mmap_offset(obj);
4625 if (obj->base.import_attach)
4626 drm_prime_gem_destroy(&obj->base, NULL);
4629 if (obj->ops->release)
4630 obj->ops->release(obj);
4632 drm_gem_object_release(&obj->base);
4633 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4636 i915_gem_object_free(obj);
4638 intel_runtime_pm_put(dev_priv);
4641 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4642 struct i915_address_space *vm)
4644 struct i915_vma *vma;
4645 list_for_each_entry(vma, &obj->vma_list, vma_link)
4652 void i915_gem_vma_destroy(struct i915_vma *vma)
4654 WARN_ON(vma->node.allocated);
4656 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4657 if (!list_empty(&vma->exec_list))
4660 list_del(&vma->vma_link);
4666 i915_gem_stop_ringbuffers(struct drm_device *dev)
4668 struct drm_i915_private *dev_priv = dev->dev_private;
4669 struct intel_engine_cs *ring;
4672 for_each_ring(ring, dev_priv, i)
4673 intel_stop_ring_buffer(ring);
4677 i915_gem_suspend(struct drm_device *dev)
4679 struct drm_i915_private *dev_priv = dev->dev_private;
4682 mutex_lock(&dev->struct_mutex);
4683 if (dev_priv->ums.mm_suspended)
4686 ret = i915_gpu_idle(dev);
4690 i915_gem_retire_requests(dev);
4692 /* Under UMS, be paranoid and evict. */
4693 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4694 i915_gem_evict_everything(dev);
4696 i915_kernel_lost_context(dev);
4697 i915_gem_stop_ringbuffers(dev);
4699 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4700 * We need to replace this with a semaphore, or something.
4701 * And not confound ums.mm_suspended!
4703 dev_priv->ums.mm_suspended = !drm_core_check_feature(dev,
4705 mutex_unlock(&dev->struct_mutex);
4707 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4708 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4709 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
4714 mutex_unlock(&dev->struct_mutex);
4718 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
4720 struct drm_device *dev = ring->dev;
4721 struct drm_i915_private *dev_priv = dev->dev_private;
4722 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4723 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4726 if (!HAS_L3_DPF(dev) || !remap_info)
4729 ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4734 * Note: We do not worry about the concurrent register cacheline hang
4735 * here because no other code should access these registers other than
4736 * at initialization time.
4738 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4739 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4740 intel_ring_emit(ring, reg_base + i);
4741 intel_ring_emit(ring, remap_info[i/4]);
4744 intel_ring_advance(ring);
4749 void i915_gem_init_swizzling(struct drm_device *dev)
4751 struct drm_i915_private *dev_priv = dev->dev_private;
4753 if (INTEL_INFO(dev)->gen < 5 ||
4754 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4757 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4758 DISP_TILE_SURFACE_SWIZZLING);
4763 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4765 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4766 else if (IS_GEN7(dev))
4767 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4768 else if (IS_GEN8(dev))
4769 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4775 intel_enable_blt(struct drm_device *dev)
4782 /* The blitter was dysfunctional on early prototypes */
4783 revision = pci_read_config(dev->dev, PCIR_REVID, 1);
4784 if (IS_GEN6(dev) && revision < 8) {
4785 DRM_INFO("BLT not supported on this pre-production hardware;"
4786 " graphics performance will be degraded.\n");
4793 static int i915_gem_init_rings(struct drm_device *dev)
4795 struct drm_i915_private *dev_priv = dev->dev_private;
4798 ret = intel_init_render_ring_buffer(dev);
4803 ret = intel_init_bsd_ring_buffer(dev);
4805 goto cleanup_render_ring;
4808 if (intel_enable_blt(dev)) {
4809 ret = intel_init_blt_ring_buffer(dev);
4811 goto cleanup_bsd_ring;
4814 if (HAS_VEBOX(dev)) {
4815 ret = intel_init_vebox_ring_buffer(dev);
4817 goto cleanup_blt_ring;
4820 if (HAS_BSD2(dev)) {
4821 ret = intel_init_bsd2_ring_buffer(dev);
4823 goto cleanup_vebox_ring;
4826 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4828 goto cleanup_bsd2_ring;
4833 intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4835 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4837 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4839 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4840 cleanup_render_ring:
4841 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4847 i915_gem_init_hw(struct drm_device *dev)
4849 struct drm_i915_private *dev_priv = dev->dev_private;
4853 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4857 if (dev_priv->ellc_size)
4858 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4860 if (IS_HASWELL(dev))
4861 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4862 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4864 if (HAS_PCH_NOP(dev)) {
4865 if (IS_IVYBRIDGE(dev)) {
4866 u32 temp = I915_READ(GEN7_MSG_CTL);
4867 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4868 I915_WRITE(GEN7_MSG_CTL, temp);
4869 } else if (INTEL_INFO(dev)->gen >= 7) {
4870 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4871 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4872 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4876 i915_gem_init_swizzling(dev);
4878 ret = i915_gem_init_rings(dev);
4882 for (i = 0; i < NUM_L3_SLICES(dev); i++)
4883 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4886 * XXX: Contexts should only be initialized once. Doing a switch to the
4887 * default context switch however is something we'd like to do after
4888 * reset or thaw (the latter may not actually be necessary for HW, but
4889 * goes with our code better). Context switching requires rings (for
4890 * the do_switch), but before enabling PPGTT. So don't move this.
4892 ret = i915_gem_context_enable(dev_priv);
4893 if (ret && ret != -EIO) {
4894 DRM_ERROR("Context enable failed %d\n", ret);
4895 i915_gem_cleanup_ringbuffer(dev);
4901 int i915_gem_init(struct drm_device *dev)
4903 struct drm_i915_private *dev_priv = dev->dev_private;
4906 mutex_lock(&dev->struct_mutex);
4908 if (IS_VALLEYVIEW(dev)) {
4909 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4910 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4911 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4912 VLV_GTLC_ALLOWWAKEACK), 10))
4913 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4916 i915_gem_init_userptr(dev);
4917 i915_gem_init_global_gtt(dev);
4919 ret = i915_gem_context_init(dev);
4921 mutex_unlock(&dev->struct_mutex);
4925 ret = i915_gem_init_hw(dev);
4927 /* Allow ring initialisation to fail by marking the GPU as
4928 * wedged. But we only want to do this where the GPU is angry,
4929 * for all other failure, such as an allocation failure, bail.
4931 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4932 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4935 mutex_unlock(&dev->struct_mutex);
4937 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4938 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4939 dev_priv->dri1.allow_batchbuffer = 1;
4944 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4946 struct drm_i915_private *dev_priv = dev->dev_private;
4947 struct intel_engine_cs *ring;
4950 for_each_ring(ring, dev_priv, i)
4951 intel_cleanup_ring_buffer(ring);
4955 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4956 struct drm_file *file_priv)
4958 struct drm_i915_private *dev_priv = dev->dev_private;
4961 if (drm_core_check_feature(dev, DRIVER_MODESET))
4964 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4965 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4966 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4969 mutex_lock(&dev->struct_mutex);
4970 dev_priv->ums.mm_suspended = 0;
4972 ret = i915_gem_init_hw(dev);
4974 mutex_unlock(&dev->struct_mutex);
4978 BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4980 ret = drm_irq_install(dev, dev->irq);
4982 goto cleanup_ringbuffer;
4983 mutex_unlock(&dev->struct_mutex);
4988 i915_gem_cleanup_ringbuffer(dev);
4989 dev_priv->ums.mm_suspended = 1;
4990 mutex_unlock(&dev->struct_mutex);
4996 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4997 struct drm_file *file_priv)
4999 if (drm_core_check_feature(dev, DRIVER_MODESET))
5002 mutex_lock(&dev->struct_mutex);
5003 drm_irq_uninstall(dev);
5004 mutex_unlock(&dev->struct_mutex);
5006 return i915_gem_suspend(dev);
5010 i915_gem_lastclose(struct drm_device *dev)
5014 if (drm_core_check_feature(dev, DRIVER_MODESET))
5017 ret = i915_gem_suspend(dev);
5019 DRM_ERROR("failed to idle hardware: %d\n", ret);
5023 init_ring_lists(struct intel_engine_cs *ring)
5025 INIT_LIST_HEAD(&ring->active_list);
5026 INIT_LIST_HEAD(&ring->request_list);
5029 void i915_init_vm(struct drm_i915_private *dev_priv,
5030 struct i915_address_space *vm)
5032 if (!i915_is_ggtt(vm))
5033 drm_mm_init(&vm->mm, vm->start, vm->total);
5034 vm->dev = dev_priv->dev;
5035 INIT_LIST_HEAD(&vm->active_list);
5036 INIT_LIST_HEAD(&vm->inactive_list);
5037 INIT_LIST_HEAD(&vm->global_link);
5038 list_add_tail(&vm->global_link, &dev_priv->vm_list);
5042 i915_gem_load(struct drm_device *dev)
5044 struct drm_i915_private *dev_priv = dev->dev_private;
5047 INIT_LIST_HEAD(&dev_priv->vm_list);
5048 i915_init_vm(dev_priv, &dev_priv->gtt.base);
5050 INIT_LIST_HEAD(&dev_priv->context_list);
5051 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
5052 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
5053 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5054 for (i = 0; i < I915_NUM_RINGS; i++)
5055 init_ring_lists(&dev_priv->ring[i]);
5056 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
5057 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
5058 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
5059 i915_gem_retire_work_handler);
5060 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
5061 i915_gem_idle_work_handler);
5062 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
5064 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
5065 if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {
5066 I915_WRITE(MI_ARB_STATE,
5067 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
5070 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
5072 /* Old X drivers will take 0-2 for front, back, depth buffers */
5073 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5074 dev_priv->fence_reg_start = 3;
5076 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
5077 dev_priv->num_fence_regs = 32;
5078 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5079 dev_priv->num_fence_regs = 16;
5081 dev_priv->num_fence_regs = 8;
5083 /* Initialize fence registers to zero */
5084 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5085 i915_gem_restore_fences(dev);
5087 i915_gem_detect_bit_6_swizzle(dev);
5088 init_waitqueue_head(&dev_priv->pending_flip_queue);
5090 dev_priv->mm.interruptible = true;
5093 dev_priv->mm.inactive_shrinker.scan_objects = i915_gem_inactive_scan;
5094 dev_priv->mm.inactive_shrinker.count_objects = i915_gem_inactive_count;
5095 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
5096 register_shrinker(&dev_priv->mm.inactive_shrinker);
5097 /* Old FreeBSD code */
5098 dev_priv->mm.inactive_shrinker = EVENTHANDLER_REGISTER(vm_lowmem,
5099 i915_gem_inactive_shrink, dev, EVENTHANDLER_PRI_ANY);
5103 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5105 struct drm_i915_file_private *file_priv = file->driver_priv;
5107 cancel_delayed_work_sync(&file_priv->mm.idle_work);
5109 /* Clean up our request list when the client is going away, so that
5110 * later retire_requests won't dereference our soon-to-be-gone
5113 spin_lock(&file_priv->mm.lock);
5114 while (!list_empty(&file_priv->mm.request_list)) {
5115 struct drm_i915_gem_request *request;
5117 request = list_first_entry(&file_priv->mm.request_list,
5118 struct drm_i915_gem_request,
5120 list_del(&request->client_list);
5121 request->file_priv = NULL;
5123 spin_unlock(&file_priv->mm.lock);
5127 i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot,
5128 vm_ooffset_t foff, struct ucred *cred, u_short *color)
5130 *color = 0; /* XXXKIB */
5135 i915_gem_pager_dtor(void *handle)
5137 struct drm_gem_object *obj;
5138 struct drm_device *dev;
5143 mutex_lock(&dev->struct_mutex);
5144 drm_gem_free_mmap_offset(obj);
5145 i915_gem_release_mmap(to_intel_bo(obj));
5146 drm_gem_object_unreference(obj);
5147 mutex_unlock(&dev->struct_mutex);
5151 i915_gem_file_idle_work_handler(struct work_struct *work)
5153 struct drm_i915_file_private *file_priv =
5154 container_of(work, typeof(*file_priv), mm.idle_work.work);
5156 atomic_set(&file_priv->rps_wait_boost, false);
5159 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5161 struct drm_i915_file_private *file_priv;
5164 DRM_DEBUG_DRIVER("\n");
5166 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5170 file->driver_priv = file_priv;
5171 file_priv->dev_priv = dev->dev_private;
5172 file_priv->file = file;
5174 spin_init(&file_priv->mm.lock, "i915_priv");
5175 INIT_LIST_HEAD(&file_priv->mm.request_list);
5176 INIT_DELAYED_WORK(&file_priv->mm.idle_work,
5177 i915_gem_file_idle_work_handler);
5179 ret = i915_gem_context_open(dev, file);
5187 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
5189 if (!mutex_is_locked(mutex))
5192 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
5193 return mutex->owner == task;
5195 /* Since UP may be pre-empted, we cannot assume that we own the lock */
5202 static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock)
5204 if (!mutex_trylock(&dev->struct_mutex)) {
5205 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5208 if (to_i915(dev)->mm.shrinker_no_lock_stealing)
5218 static int num_vma_bound(struct drm_i915_gem_object *obj)
5220 struct i915_vma *vma;
5223 list_for_each_entry(vma, &obj->vma_list, vma_link)
5224 if (drm_mm_node_allocated(&vma->node))
5230 static unsigned long
5231 i915_gem_inactive_count(struct shrinker *shrinker, struct shrink_control *sc)
5233 struct drm_i915_private *dev_priv =
5234 container_of(shrinker,
5235 struct drm_i915_private,
5236 mm.inactive_shrinker);
5237 struct drm_device *dev = dev_priv->dev;
5238 struct drm_i915_gem_object *obj;
5239 unsigned long count;
5242 if (!i915_gem_shrinker_lock(dev, &unlock))
5246 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
5247 if (obj->pages_pin_count == 0)
5248 count += obj->base.size >> PAGE_SHIFT;
5250 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5251 if (!i915_gem_obj_is_pinned(obj) &&
5252 obj->pages_pin_count == num_vma_bound(obj))
5253 count += obj->base.size >> PAGE_SHIFT;
5257 mutex_unlock(&dev->struct_mutex);
5263 /* All the new VM stuff */
5264 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
5265 struct i915_address_space *vm)
5267 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5268 struct i915_vma *vma;
5270 if (!dev_priv->mm.aliasing_ppgtt ||
5271 vm == &dev_priv->mm.aliasing_ppgtt->base)
5272 vm = &dev_priv->gtt.base;
5274 BUG_ON(list_empty(&o->vma_list));
5275 list_for_each_entry(vma, &o->vma_list, vma_link) {
5277 return vma->node.start;
5283 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5284 struct i915_address_space *vm)
5286 struct i915_vma *vma;
5288 list_for_each_entry(vma, &o->vma_list, vma_link)
5289 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5295 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5297 struct i915_vma *vma;
5299 list_for_each_entry(vma, &o->vma_list, vma_link)
5300 if (drm_mm_node_allocated(&vma->node))
5306 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5307 struct i915_address_space *vm)
5309 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5310 struct i915_vma *vma;
5312 if (!dev_priv->mm.aliasing_ppgtt ||
5313 vm == &dev_priv->mm.aliasing_ppgtt->base)
5314 vm = &dev_priv->gtt.base;
5316 BUG_ON(list_empty(&o->vma_list));
5318 list_for_each_entry(vma, &o->vma_list, vma_link)
5320 return vma->node.size;
5326 static unsigned long
5327 i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc)
5329 struct drm_i915_private *dev_priv =
5330 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5331 struct drm_device *dev = dev_priv->dev;
5332 unsigned long freed;
5335 if (!i915_gem_shrinker_lock(dev, &unlock))
5338 freed = i915_gem_purge(dev_priv, sc->nr_to_scan);
5339 if (freed < sc->nr_to_scan)
5340 freed += __i915_gem_shrink(dev_priv,
5341 sc->nr_to_scan - freed,
5343 if (freed < sc->nr_to_scan)
5344 freed += i915_gem_shrink_all(dev_priv);
5347 mutex_unlock(&dev->struct_mutex);
5353 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5355 struct i915_vma *vma;
5357 /* This WARN has probably outlived its usefulness (callers already
5358 * WARN if they don't find the GGTT vma they expect). When removing,
5359 * remember to remove the pre-check in is_pin_display() as well */
5360 if (WARN_ON(list_empty(&obj->vma_list)))
5363 vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
5364 if (vma->vm != obj_to_ggtt(obj))