1 /*******************************************************************************
2 Copyright (c) 2001-2005, Intel Corporation
5 Redistribution and use in source and binary forms, with or without
6 modification, are permitted provided that the following conditions are met:
8 1. Redistributions of source code must retain the above copyright notice,
9 this list of conditions and the following disclaimer.
11 2. Redistributions in binary form must reproduce the above copyright
12 notice, this list of conditions and the following disclaimer in the
13 documentation and/or other materials provided with the distribution.
15 3. Neither the name of the Intel Corporation nor the names of its
16 contributors may be used to endorse or promote products derived from
17 this software without specific prior written permission.
19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 POSSIBILITY OF SUCH DAMAGE.
30 *******************************************************************************/
32 /*$FreeBSD: src/sys/dev/em/if_em_hw.c,v 1.1.2.8 2003/06/09 21:43:41 pdeuskar Exp $*/
33 /*$DragonFly: src/sys/dev/netif/em/if_em_hw.c,v 1.11 2006/12/23 10:39:16 sephe Exp $*/
36 * Shared functions for accessing and configuring the MAC
44 #include <dev/netif/em/if_em_hw.h>
47 static int32_t em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask);
48 static void em_swfw_sync_release(struct em_hw *hw, uint16_t mask);
49 static int32_t em_read_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *data);
50 static int32_t em_write_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data);
51 static int32_t em_get_software_semaphore(struct em_hw *hw);
52 static void em_release_software_semaphore(struct em_hw *hw);
54 static uint8_t em_arc_subsystem_valid(struct em_hw *hw);
55 static int32_t em_check_downshift(struct em_hw *hw);
56 static int32_t em_check_polarity(struct em_hw *hw, em_rev_polarity *polarity);
57 static void em_clear_vfta(struct em_hw *hw);
58 static int32_t em_commit_shadow_ram(struct em_hw *hw);
59 static int32_t em_config_dsp_after_link_change(struct em_hw *hw, boolean_t link_up);
60 static int32_t em_config_fc_after_link_up(struct em_hw *hw);
61 static int32_t em_detect_gig_phy(struct em_hw *hw);
62 static int32_t em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t bank);
63 static int32_t em_get_auto_rd_done(struct em_hw *hw);
64 static int32_t em_get_cable_length(struct em_hw *hw, uint16_t *min_length, uint16_t *max_length);
65 static int32_t em_get_hw_eeprom_semaphore(struct em_hw *hw);
66 static int32_t em_get_phy_cfg_done(struct em_hw *hw);
67 static int32_t em_get_software_flag(struct em_hw *hw);
68 static int32_t em_ich8_cycle_init(struct em_hw *hw);
69 static int32_t em_ich8_flash_cycle(struct em_hw *hw, uint32_t timeout);
70 static int32_t em_id_led_init(struct em_hw *hw);
71 static int32_t em_init_lcd_from_nvm_config_region(struct em_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size);
72 static int32_t em_init_lcd_from_nvm(struct em_hw *hw);
73 static void em_init_rx_addrs(struct em_hw *hw);
74 static void em_initialize_hardware_bits(struct em_hw *hw);
75 static boolean_t em_is_onboard_nvm_eeprom(struct em_hw *hw);
76 static int32_t em_kumeran_lock_loss_workaround(struct em_hw *hw);
77 static int32_t em_mng_enable_host_if(struct em_hw *hw);
78 static int32_t em_mng_host_if_write(struct em_hw *hw, uint8_t *buffer, uint16_t length, uint16_t offset, uint8_t *sum);
79 static int32_t em_mng_write_cmd_header(struct em_hw* hw, struct em_host_mng_command_header* hdr);
80 static int32_t em_mng_write_commit(struct em_hw *hw);
81 static int32_t em_phy_ife_get_info(struct em_hw *hw, struct em_phy_info *phy_info);
82 static int32_t em_phy_igp_get_info(struct em_hw *hw, struct em_phy_info *phy_info);
83 static int32_t em_read_eeprom_eerd(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
84 static int32_t em_write_eeprom_eewr(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
85 static int32_t em_poll_eerd_eewr_done(struct em_hw *hw, int eerd);
86 static int32_t em_phy_m88_get_info(struct em_hw *hw, struct em_phy_info *phy_info);
87 static void em_put_hw_eeprom_semaphore(struct em_hw *hw);
88 static int32_t em_read_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t *data);
89 static int32_t em_verify_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t byte);
90 static int32_t em_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t byte);
91 static int32_t em_read_ich8_word(struct em_hw *hw, uint32_t index, uint16_t *data);
92 static int32_t em_read_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, uint16_t *data);
93 static int32_t em_write_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, uint16_t data);
94 static int32_t em_read_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
95 static int32_t em_write_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
96 static void em_release_software_flag(struct em_hw *hw);
97 static int32_t em_set_d3_lplu_state(struct em_hw *hw, boolean_t active);
98 static int32_t em_set_d0_lplu_state(struct em_hw *hw, boolean_t active);
99 static int32_t em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop);
100 static void em_set_pci_express_master_disable(struct em_hw *hw);
101 static int32_t em_wait_autoneg(struct em_hw *hw);
102 static void em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value);
103 static int32_t em_set_phy_type(struct em_hw *hw);
104 static void em_phy_init_script(struct em_hw *hw);
105 static int32_t em_setup_copper_link(struct em_hw *hw);
106 static int32_t em_setup_fiber_serdes_link(struct em_hw *hw);
107 static int32_t em_adjust_serdes_amplitude(struct em_hw *hw);
108 static int32_t em_phy_force_speed_duplex(struct em_hw *hw);
109 static int32_t em_config_mac_to_phy(struct em_hw *hw);
110 static void em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl);
111 static void em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl);
112 static void em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data,
114 static uint16_t em_shift_in_mdi_bits(struct em_hw *hw);
115 static int32_t em_phy_reset_dsp(struct em_hw *hw);
116 static int32_t em_write_eeprom_spi(struct em_hw *hw, uint16_t offset,
117 uint16_t words, uint16_t *data);
118 static int32_t em_write_eeprom_microwire(struct em_hw *hw,
119 uint16_t offset, uint16_t words,
121 static int32_t em_spi_eeprom_ready(struct em_hw *hw);
122 static void em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd);
123 static void em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd);
124 static void em_shift_out_ee_bits(struct em_hw *hw, uint16_t data,
126 static int32_t em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr,
128 static int32_t em_read_phy_reg_ex(struct em_hw *hw,uint32_t reg_addr,
130 static uint16_t em_shift_in_ee_bits(struct em_hw *hw, uint16_t count);
131 static int32_t em_acquire_eeprom(struct em_hw *hw);
132 static void em_release_eeprom(struct em_hw *hw);
133 static void em_standby_eeprom(struct em_hw *hw);
134 static int32_t em_set_vco_speed(struct em_hw *hw);
135 static int32_t em_polarity_reversal_workaround(struct em_hw *hw);
136 static int32_t em_set_phy_mode(struct em_hw *hw);
137 static int32_t em_host_if_read_cookie(struct em_hw *hw, uint8_t *buffer);
138 static uint8_t em_calculate_mng_checksum(char *buffer, uint32_t length);
139 static int32_t em_configure_kmrn_for_10_100(struct em_hw *hw,
141 static int32_t em_configure_kmrn_for_1000(struct em_hw *hw);
143 /* IGP cable length table */
145 uint16_t em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
146 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
147 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
148 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
149 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
150 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
151 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
152 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
153 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
156 uint16_t em_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
157 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
158 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
159 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
160 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
161 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
162 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
163 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
164 104, 109, 114, 118, 121, 124};
166 /******************************************************************************
167 * Set the phy type member in the hw struct.
169 * hw - Struct containing variables accessed by shared code
170 *****************************************************************************/
172 em_set_phy_type(struct em_hw *hw)
174 DEBUGFUNC("em_set_phy_type");
176 if (hw->mac_type == em_undefined)
177 return -E1000_ERR_PHY_TYPE;
179 switch (hw->phy_id) {
180 case M88E1000_E_PHY_ID:
181 case M88E1000_I_PHY_ID:
182 case M88E1011_I_PHY_ID:
183 case M88E1111_I_PHY_ID:
184 hw->phy_type = em_phy_m88;
186 case IGP01E1000_I_PHY_ID:
187 if (hw->mac_type == em_82541 ||
188 hw->mac_type == em_82541_rev_2 ||
189 hw->mac_type == em_82547 ||
190 hw->mac_type == em_82547_rev_2) {
191 hw->phy_type = em_phy_igp;
194 case IGP03E1000_E_PHY_ID:
195 hw->phy_type = em_phy_igp_3;
198 case IFE_PLUS_E_PHY_ID:
200 hw->phy_type = em_phy_ife;
202 case GG82563_E_PHY_ID:
203 if (hw->mac_type == em_80003es2lan) {
204 hw->phy_type = em_phy_gg82563;
209 /* Should never have loaded on this device */
210 hw->phy_type = em_phy_undefined;
211 return -E1000_ERR_PHY_TYPE;
214 return E1000_SUCCESS;
217 /******************************************************************************
218 * IGP phy init script - initializes the GbE PHY
220 * hw - Struct containing variables accessed by shared code
221 *****************************************************************************/
223 em_phy_init_script(struct em_hw *hw)
226 uint16_t phy_saved_data;
228 DEBUGFUNC("em_phy_init_script");
230 if (hw->phy_init_script) {
233 /* Save off the current value of register 0x2F5B to be restored at
234 * the end of this routine. */
235 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
237 /* Disabled the PHY transmitter */
238 em_write_phy_reg(hw, 0x2F5B, 0x0003);
242 em_write_phy_reg(hw,0x0000,0x0140);
246 switch (hw->mac_type) {
249 em_write_phy_reg(hw, 0x1F95, 0x0001);
251 em_write_phy_reg(hw, 0x1F71, 0xBD21);
253 em_write_phy_reg(hw, 0x1F79, 0x0018);
255 em_write_phy_reg(hw, 0x1F30, 0x1600);
257 em_write_phy_reg(hw, 0x1F31, 0x0014);
259 em_write_phy_reg(hw, 0x1F32, 0x161C);
261 em_write_phy_reg(hw, 0x1F94, 0x0003);
263 em_write_phy_reg(hw, 0x1F96, 0x003F);
265 em_write_phy_reg(hw, 0x2010, 0x0008);
270 em_write_phy_reg(hw, 0x1F73, 0x0099);
276 em_write_phy_reg(hw, 0x0000, 0x3300);
280 /* Now enable the transmitter */
281 em_write_phy_reg(hw, 0x2F5B, phy_saved_data);
283 if (hw->mac_type == em_82547) {
284 uint16_t fused, fine, coarse;
286 /* Move to analog registers page */
287 em_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
289 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
290 em_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
292 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
293 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
295 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
296 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
297 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
298 } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
299 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
301 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
302 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
303 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
305 em_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
306 em_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
307 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
313 /******************************************************************************
314 * Set the mac type member in the hw struct.
316 * hw - Struct containing variables accessed by shared code
317 *****************************************************************************/
319 em_set_mac_type(struct em_hw *hw)
321 DEBUGFUNC("em_set_mac_type");
323 switch (hw->device_id) {
324 case E1000_DEV_ID_82542:
325 switch (hw->revision_id) {
326 case E1000_82542_2_0_REV_ID:
327 hw->mac_type = em_82542_rev2_0;
329 case E1000_82542_2_1_REV_ID:
330 hw->mac_type = em_82542_rev2_1;
333 /* Invalid 82542 revision ID */
334 return -E1000_ERR_MAC_TYPE;
337 case E1000_DEV_ID_82543GC_FIBER:
338 case E1000_DEV_ID_82543GC_COPPER:
339 hw->mac_type = em_82543;
341 case E1000_DEV_ID_82544EI_COPPER:
342 case E1000_DEV_ID_82544EI_FIBER:
343 case E1000_DEV_ID_82544GC_COPPER:
344 case E1000_DEV_ID_82544GC_LOM:
345 hw->mac_type = em_82544;
347 case E1000_DEV_ID_82540EM:
348 case E1000_DEV_ID_82540EM_LOM:
349 case E1000_DEV_ID_82540EP:
350 case E1000_DEV_ID_82540EP_LOM:
351 case E1000_DEV_ID_82540EP_LP:
352 hw->mac_type = em_82540;
354 case E1000_DEV_ID_82545EM_COPPER:
355 case E1000_DEV_ID_82545EM_FIBER:
356 hw->mac_type = em_82545;
358 case E1000_DEV_ID_82545GM_COPPER:
359 case E1000_DEV_ID_82545GM_FIBER:
360 case E1000_DEV_ID_82545GM_SERDES:
361 hw->mac_type = em_82545_rev_3;
363 case E1000_DEV_ID_82546EB_COPPER:
364 case E1000_DEV_ID_82546EB_FIBER:
365 case E1000_DEV_ID_82546EB_QUAD_COPPER:
366 hw->mac_type = em_82546;
368 case E1000_DEV_ID_82546GB_COPPER:
369 case E1000_DEV_ID_82546GB_FIBER:
370 case E1000_DEV_ID_82546GB_SERDES:
371 case E1000_DEV_ID_82546GB_PCIE:
372 case E1000_DEV_ID_82546GB_QUAD_COPPER:
373 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
374 hw->mac_type = em_82546_rev_3;
376 case E1000_DEV_ID_82541EI:
377 case E1000_DEV_ID_82541EI_MOBILE:
378 case E1000_DEV_ID_82541ER_LOM:
379 hw->mac_type = em_82541;
381 case E1000_DEV_ID_82541ER:
382 case E1000_DEV_ID_82541GI:
383 case E1000_DEV_ID_82541GI_LF:
384 case E1000_DEV_ID_82541GI_MOBILE:
385 hw->mac_type = em_82541_rev_2;
387 case E1000_DEV_ID_82547EI:
388 case E1000_DEV_ID_82547EI_MOBILE:
389 hw->mac_type = em_82547;
391 case E1000_DEV_ID_82547GI:
392 hw->mac_type = em_82547_rev_2;
394 case E1000_DEV_ID_82571EB_COPPER:
395 case E1000_DEV_ID_82571EB_FIBER:
396 case E1000_DEV_ID_82571EB_SERDES:
397 case E1000_DEV_ID_82571EB_QUAD_COPPER:
398 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
399 hw->mac_type = em_82571;
401 case E1000_DEV_ID_82572EI_COPPER:
402 case E1000_DEV_ID_82572EI_FIBER:
403 case E1000_DEV_ID_82572EI_SERDES:
404 case E1000_DEV_ID_82572EI:
405 hw->mac_type = em_82572;
407 case E1000_DEV_ID_82573E:
408 case E1000_DEV_ID_82573E_IAMT:
409 case E1000_DEV_ID_82573L:
410 hw->mac_type = em_82573;
412 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
413 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
414 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
415 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
416 hw->mac_type = em_80003es2lan;
418 case E1000_DEV_ID_ICH8_IGP_M_AMT:
419 case E1000_DEV_ID_ICH8_IGP_AMT:
420 case E1000_DEV_ID_ICH8_IGP_C:
421 case E1000_DEV_ID_ICH8_IFE:
422 case E1000_DEV_ID_ICH8_IFE_GT:
423 case E1000_DEV_ID_ICH8_IFE_G:
424 case E1000_DEV_ID_ICH8_IGP_M:
425 hw->mac_type = em_ich8lan;
428 /* Should never have loaded on this device */
429 return -E1000_ERR_MAC_TYPE;
432 switch (hw->mac_type) {
434 hw->swfwhw_semaphore_present = TRUE;
435 hw->asf_firmware_present = TRUE;
438 hw->swfw_sync_present = TRUE;
443 hw->eeprom_semaphore_present = TRUE;
449 hw->asf_firmware_present = TRUE;
455 return E1000_SUCCESS;
458 /*****************************************************************************
459 * Set media type and TBI compatibility.
461 * hw - Struct containing variables accessed by shared code
462 * **************************************************************************/
464 em_set_media_type(struct em_hw *hw)
468 DEBUGFUNC("em_set_media_type");
470 if (hw->mac_type != em_82543) {
471 /* tbi_compatibility is only valid on 82543 */
472 hw->tbi_compatibility_en = FALSE;
475 switch (hw->device_id) {
476 case E1000_DEV_ID_82545GM_SERDES:
477 case E1000_DEV_ID_82546GB_SERDES:
478 case E1000_DEV_ID_82571EB_SERDES:
479 case E1000_DEV_ID_82572EI_SERDES:
480 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
481 hw->media_type = em_media_type_internal_serdes;
484 switch (hw->mac_type) {
485 case em_82542_rev2_0:
486 case em_82542_rev2_1:
487 hw->media_type = em_media_type_fiber;
491 /* The STATUS_TBIMODE bit is reserved or reused for the this
494 hw->media_type = em_media_type_copper;
497 status = E1000_READ_REG(hw, STATUS);
498 if (status & E1000_STATUS_TBIMODE) {
499 hw->media_type = em_media_type_fiber;
500 /* tbi_compatibility not valid on fiber */
501 hw->tbi_compatibility_en = FALSE;
503 hw->media_type = em_media_type_copper;
510 /******************************************************************************
511 * Reset the transmit and receive units; mask and clear all interrupts.
513 * hw - Struct containing variables accessed by shared code
514 *****************************************************************************/
516 em_reset_hw(struct em_hw *hw)
524 uint32_t extcnf_ctrl;
527 DEBUGFUNC("em_reset_hw");
529 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
530 if (hw->mac_type == em_82542_rev2_0) {
531 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
532 em_pci_clear_mwi(hw);
535 if (hw->bus_type == em_bus_type_pci_express) {
536 /* Prevent the PCI-E bus from sticking if there is no TLP connection
537 * on the last TLP read/write transaction when MAC is reset.
539 if (em_disable_pciex_master(hw) != E1000_SUCCESS) {
540 DEBUGOUT("PCI-E Master disable polling has failed.\n");
544 /* Clear interrupt mask to stop board from generating interrupts */
545 DEBUGOUT("Masking off all interrupts\n");
546 E1000_WRITE_REG(hw, IMC, 0xffffffff);
548 /* Disable the Transmit and Receive units. Then delay to allow
549 * any pending transactions to complete before we hit the MAC with
552 E1000_WRITE_REG(hw, RCTL, 0);
553 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
554 E1000_WRITE_FLUSH(hw);
556 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
557 hw->tbi_compatibility_on = FALSE;
559 /* Delay to allow any outstanding PCI transactions to complete before
560 * resetting the device
564 ctrl = E1000_READ_REG(hw, CTRL);
566 /* Must reset the PHY before resetting the MAC */
567 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
568 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
572 /* Must acquire the MDIO ownership before MAC reset.
573 * Ownership defaults to firmware after a reset. */
574 if (hw->mac_type == em_82573) {
577 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
578 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
581 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
582 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
584 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
587 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
594 /* Workaround for ICH8 bit corruption issue in FIFO memory */
595 if (hw->mac_type == em_ich8lan) {
596 /* Set Tx and Rx buffer allocation to 8k apiece. */
597 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);
598 /* Set Packet Buffer Size to 16k. */
599 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);
602 /* Issue a global reset to the MAC. This will reset the chip's
603 * transmit, receive, DMA, and link units. It will not effect
604 * the current PCI configuration. The global reset bit is self-
605 * clearing, and should clear within a microsecond.
607 DEBUGOUT("Issuing a global reset to MAC\n");
609 switch (hw->mac_type) {
616 /* These controllers can't ack the 64-bit write when issuing the
617 * reset, so use IO-mapping as a workaround to issue the reset */
618 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
622 /* Reset is performed on a shadow of the control register */
623 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
626 if (!hw->phy_reset_disable &&
627 em_check_phy_reset_block(hw) == E1000_SUCCESS) {
628 /* em_ich8lan PHY HW reset requires MAC CORE reset
629 * at the same time to make sure the interface between
630 * MAC and the external PHY is reset.
632 ctrl |= E1000_CTRL_PHY_RST;
635 em_get_software_flag(hw);
636 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
640 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
644 /* After MAC reset, force reload of EEPROM to restore power-on settings to
645 * device. Later controllers reload the EEPROM automatically, so just wait
646 * for reload to complete.
648 switch (hw->mac_type) {
649 case em_82542_rev2_0:
650 case em_82542_rev2_1:
653 /* Wait for reset to complete */
655 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
656 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
657 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
658 E1000_WRITE_FLUSH(hw);
659 /* Wait for EEPROM reload */
666 /* Wait for EEPROM reload */
670 if (em_is_onboard_nvm_eeprom(hw) == FALSE) {
672 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
673 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
674 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
675 E1000_WRITE_FLUSH(hw);
679 /* Auto read done will delay 5ms or poll based on mac type */
680 ret_val = em_get_auto_rd_done(hw);
686 /* Disable HW ARPs on ASF enabled adapters */
687 if (hw->mac_type >= em_82540 && hw->mac_type <= em_82547_rev_2) {
688 manc = E1000_READ_REG(hw, MANC);
689 manc &= ~(E1000_MANC_ARP_EN);
690 E1000_WRITE_REG(hw, MANC, manc);
693 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
694 em_phy_init_script(hw);
696 /* Configure activity LED after PHY reset */
697 led_ctrl = E1000_READ_REG(hw, LEDCTL);
698 led_ctrl &= IGP_ACTIVITY_LED_MASK;
699 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
700 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
703 /* Clear interrupt mask to stop board from generating interrupts */
704 DEBUGOUT("Masking off all interrupts\n");
705 E1000_WRITE_REG(hw, IMC, 0xffffffff);
707 /* Clear any pending interrupt events. */
708 icr = E1000_READ_REG(hw, ICR);
710 /* If MWI was previously enabled, reenable it. */
711 if (hw->mac_type == em_82542_rev2_0) {
712 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
716 if (hw->mac_type == em_ich8lan) {
717 uint32_t kab = E1000_READ_REG(hw, KABGTXD);
718 kab |= E1000_KABGTXD_BGSQLBIAS;
719 E1000_WRITE_REG(hw, KABGTXD, kab);
722 return E1000_SUCCESS;
725 /******************************************************************************
727 * Initialize a number of hardware-dependent bits
729 * hw: Struct containing variables accessed by shared code
731 *****************************************************************************/
733 em_initialize_hardware_bits(struct em_hw *hw)
735 if ((hw->mac_type >= em_82571) && (!hw->initialize_hw_bits_disable)) {
736 /* Settings common to all silicon */
737 uint32_t reg_ctrl, reg_ctrl_ext;
738 uint32_t reg_tarc0, reg_tarc1;
740 uint32_t reg_txdctl, reg_txdctl1;
742 reg_tarc0 = E1000_READ_REG(hw, TARC0);
743 reg_tarc0 &= ~0x78000000; /* Clear bits 30, 29, 28, and 27 */
745 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
746 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; /* Set bit 22 */
747 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
749 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
750 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; /* Set bit 22 */
751 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
753 switch (hw->mac_type) {
756 reg_tarc1 = E1000_READ_REG(hw, TARC1);
757 reg_tctl = E1000_READ_REG(hw, TCTL);
759 /* Set the phy Tx compatible mode bits */
760 reg_tarc1 &= ~0x60000000; /* Clear bits 30 and 29 */
762 reg_tarc0 |= 0x07800000; /* Set TARC0 bits 23-26 */
763 reg_tarc1 |= 0x07000000; /* Set TARC1 bits 24-26 */
765 if (reg_tctl & E1000_TCTL_MULR)
766 reg_tarc1 &= ~0x10000000; /* Clear bit 28 if MULR is 1b */
768 reg_tarc1 |= 0x10000000; /* Set bit 28 if MULR is 0b */
770 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
773 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
774 reg_ctrl = E1000_READ_REG(hw, CTRL);
776 reg_ctrl_ext &= ~0x00800000; /* Clear bit 23 */
777 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */
778 reg_ctrl &= ~0x20000000; /* Clear bit 29 */
780 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
781 E1000_WRITE_REG(hw, CTRL, reg_ctrl);
784 if ((hw->media_type == em_media_type_fiber) ||
785 (hw->media_type == em_media_type_internal_serdes)) {
786 reg_tarc0 &= ~0x00100000; /* Clear bit 20 */
789 reg_tctl = E1000_READ_REG(hw, TCTL);
790 reg_tarc1 = E1000_READ_REG(hw, TARC1);
791 if (reg_tctl & E1000_TCTL_MULR)
792 reg_tarc1 &= ~0x10000000; /* Clear bit 28 if MULR is 1b */
794 reg_tarc1 |= 0x10000000; /* Set bit 28 if MULR is 0b */
796 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
799 if ((hw->revision_id < 3) ||
800 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
801 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
802 reg_tarc0 |= 0x30000000; /* Set TARC0 bits 29 and 28 */
803 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
804 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */
805 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
807 reg_tarc0 |= 0x0d800000; /* Set TARC0 bits 23, 24, 26, 27 */
809 reg_tarc1 = E1000_READ_REG(hw, TARC1);
810 reg_tctl = E1000_READ_REG(hw, TCTL);
812 if (reg_tctl & E1000_TCTL_MULR)
813 reg_tarc1 &= ~0x10000000; /* Clear bit 28 if MULR is 1b */
815 reg_tarc1 |= 0x10000000; /* Set bit 28 if MULR is 0b */
817 reg_tarc1 |= 0x45000000; /* Set bit 24, 26 and 30 */
819 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
825 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
829 /******************************************************************************
830 * Performs basic configuration of the adapter.
832 * hw - Struct containing variables accessed by shared code
834 * Assumes that the controller has previously been reset and is in a
835 * post-reset uninitialized state. Initializes the receive address registers,
836 * multicast table, and VLAN filter table. Calls routines to setup link
837 * configuration and flow control settings. Clears all on-chip counters. Leaves
838 * the transmit and receive units disabled and uninitialized.
839 *****************************************************************************/
841 em_init_hw(struct em_hw *hw)
846 uint16_t pcix_cmd_word;
847 uint16_t pcix_stat_hi_word;
854 DEBUGFUNC("em_init_hw");
856 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
857 if ((hw->mac_type == em_ich8lan) &&
858 ((hw->revision_id < 3) ||
859 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
860 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
861 reg_data = E1000_READ_REG(hw, STATUS);
862 reg_data &= ~0x80000000;
863 E1000_WRITE_REG(hw, STATUS, reg_data);
866 /* Initialize Identification LED */
867 ret_val = em_id_led_init(hw);
869 DEBUGOUT("Error Initializing Identification LED\n");
873 /* Set the media type and TBI compatibility */
874 em_set_media_type(hw);
876 /* Disabling VLAN filtering. */
877 DEBUGOUT("Initializing the IEEE VLAN\n");
878 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
879 if (hw->mac_type != em_ich8lan) {
880 if (hw->mac_type < em_82545_rev_3)
881 E1000_WRITE_REG(hw, VET, 0);
885 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
886 if (hw->mac_type == em_82542_rev2_0) {
887 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
888 em_pci_clear_mwi(hw);
889 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
890 E1000_WRITE_FLUSH(hw);
894 /* Setup the receive address. This involves initializing all of the Receive
895 * Address Registers (RARs 0 - 15).
897 em_init_rx_addrs(hw);
899 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
900 if (hw->mac_type == em_82542_rev2_0) {
901 E1000_WRITE_REG(hw, RCTL, 0);
902 E1000_WRITE_FLUSH(hw);
904 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
908 /* Zero out the Multicast HASH table */
909 DEBUGOUT("Zeroing the MTA\n");
910 mta_size = E1000_MC_TBL_SIZE;
911 if (hw->mac_type == em_ich8lan)
912 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
913 for (i = 0; i < mta_size; i++) {
914 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
915 /* use write flush to prevent Memory Write Block (MWB) from
916 * occuring when accessing our register space */
917 E1000_WRITE_FLUSH(hw);
920 /* Set the PCI priority bit correctly in the CTRL register. This
921 * determines if the adapter gives priority to receives, or if it
922 * gives equal priority to transmits and receives. Valid only on
923 * 82542 and 82543 silicon.
925 if (hw->dma_fairness && hw->mac_type <= em_82543) {
926 ctrl = E1000_READ_REG(hw, CTRL);
927 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
930 switch (hw->mac_type) {
935 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
936 if (hw->bus_type == em_bus_type_pcix) {
937 em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
938 em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
940 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
941 PCIX_COMMAND_MMRBC_SHIFT;
942 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
943 PCIX_STATUS_HI_MMRBC_SHIFT;
944 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
945 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
946 if (cmd_mmrbc > stat_mmrbc) {
947 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
948 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
949 em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
956 /* More time needed for PHY to initialize */
957 if (hw->mac_type == em_ich8lan)
960 /* Call a subroutine to configure the link and setup flow control. */
961 ret_val = em_setup_link(hw);
963 /* Set the transmit descriptor write-back policy */
964 if (hw->mac_type > em_82544) {
965 ctrl = E1000_READ_REG(hw, TXDCTL);
966 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
967 E1000_WRITE_REG(hw, TXDCTL, ctrl);
970 if (hw->mac_type == em_82573) {
971 em_enable_tx_pkt_filtering(hw);
974 switch (hw->mac_type) {
978 /* Enable retransmit on late collisions */
979 reg_data = E1000_READ_REG(hw, TCTL);
980 reg_data |= E1000_TCTL_RTLC;
981 E1000_WRITE_REG(hw, TCTL, reg_data);
983 /* Configure Gigabit Carry Extend Padding */
984 reg_data = E1000_READ_REG(hw, TCTL_EXT);
985 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
986 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
987 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
989 /* Configure Transmit Inter-Packet Gap */
990 reg_data = E1000_READ_REG(hw, TIPG);
991 reg_data &= ~E1000_TIPG_IPGT_MASK;
992 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
993 E1000_WRITE_REG(hw, TIPG, reg_data);
995 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
996 reg_data &= ~0x00100000;
997 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1002 ctrl = E1000_READ_REG(hw, TXDCTL1);
1003 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
1004 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1009 if (hw->mac_type == em_82573) {
1010 uint32_t gcr = E1000_READ_REG(hw, GCR);
1011 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1012 E1000_WRITE_REG(hw, GCR, gcr);
1015 /* Clear all of the statistics registers (clear on read). It is
1016 * important that we do this after we have tried to establish link
1017 * because the symbol error count will increment wildly if there
1020 em_clear_hw_cntrs(hw);
1022 /* ICH8 No-snoop bits are opposite polarity.
1023 * Set to snoop by default after reset. */
1024 if (hw->mac_type == em_ich8lan)
1025 em_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
1027 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1028 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1029 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1030 /* Relaxed ordering must be disabled to avoid a parity
1031 * error crash in a PCI slot. */
1032 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1033 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1036 /* Must be called after em_set_media_type because media_type is used */
1037 em_initialize_hardware_bits(hw);
1042 /******************************************************************************
1043 * Adjust SERDES output amplitude based on EEPROM setting.
1045 * hw - Struct containing variables accessed by shared code.
1046 *****************************************************************************/
1048 em_adjust_serdes_amplitude(struct em_hw *hw)
1050 uint16_t eeprom_data;
1053 DEBUGFUNC("em_adjust_serdes_amplitude");
1055 if (hw->media_type != em_media_type_internal_serdes)
1056 return E1000_SUCCESS;
1058 switch (hw->mac_type) {
1059 case em_82545_rev_3:
1060 case em_82546_rev_3:
1063 return E1000_SUCCESS;
1066 ret_val = em_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
1071 if (eeprom_data != EEPROM_RESERVED_WORD) {
1072 /* Adjust SERDES output amplitude only. */
1073 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
1074 ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
1079 return E1000_SUCCESS;
1082 /******************************************************************************
1083 * Configures flow control and link settings.
1085 * hw - Struct containing variables accessed by shared code
1087 * Determines which flow control settings to use. Calls the apropriate media-
1088 * specific link configuration function. Configures the flow control settings.
1089 * Assuming the adapter has a valid link partner, a valid link should be
1090 * established. Assumes the hardware has previously been reset and the
1091 * transmitter and receiver are not enabled.
1092 *****************************************************************************/
1094 em_setup_link(struct em_hw *hw)
1098 uint16_t eeprom_data;
1100 DEBUGFUNC("em_setup_link");
1102 /* In the case of the phy reset being blocked, we already have a link.
1103 * We do not have to set it up again. */
1104 if (em_check_phy_reset_block(hw))
1105 return E1000_SUCCESS;
1107 /* Read and store word 0x0F of the EEPROM. This word contains bits
1108 * that determine the hardware's default PAUSE (flow control) mode,
1109 * a bit that determines whether the HW defaults to enabling or
1110 * disabling auto-negotiation, and the direction of the
1111 * SW defined pins. If there is no SW over-ride of the flow
1112 * control setting, then the variable hw->fc will
1113 * be initialized based on a value in the EEPROM.
1115 if (hw->fc == E1000_FC_DEFAULT) {
1116 switch (hw->mac_type) {
1119 hw->fc = E1000_FC_FULL;
1122 ret_val = em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1125 DEBUGOUT("EEPROM Read Error\n");
1126 return -E1000_ERR_EEPROM;
1128 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1129 hw->fc = E1000_FC_NONE;
1130 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1131 EEPROM_WORD0F_ASM_DIR)
1132 hw->fc = E1000_FC_TX_PAUSE;
1134 hw->fc = E1000_FC_FULL;
1139 /* We want to save off the original Flow Control configuration just
1140 * in case we get disconnected and then reconnected into a different
1141 * hub or switch with different Flow Control capabilities.
1143 if (hw->mac_type == em_82542_rev2_0)
1144 hw->fc &= (~E1000_FC_TX_PAUSE);
1146 if ((hw->mac_type < em_82543) && (hw->report_tx_early == 1))
1147 hw->fc &= (~E1000_FC_RX_PAUSE);
1149 hw->original_fc = hw->fc;
1151 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
1153 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1154 * polarity value for the SW controlled pins, and setup the
1155 * Extended Device Control reg with that info.
1156 * This is needed because one of the SW controlled pins is used for
1157 * signal detection. So this should be done before em_setup_pcs_link()
1158 * or em_phy_setup() is called.
1160 if (hw->mac_type == em_82543) {
1161 ret_val = em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1164 DEBUGOUT("EEPROM Read Error\n");
1165 return -E1000_ERR_EEPROM;
1167 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1169 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1172 /* Call the necessary subroutine to configure the link. */
1173 ret_val = (hw->media_type == em_media_type_copper) ?
1174 em_setup_copper_link(hw) :
1175 em_setup_fiber_serdes_link(hw);
1177 /* Initialize the flow control address, type, and PAUSE timer
1178 * registers to their default values. This is done even if flow
1179 * control is disabled, because it does not hurt anything to
1180 * initialize these registers.
1182 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1184 /* FCAL/H and FCT are hardcoded to standard values in em_ich8lan. */
1185 if (hw->mac_type != em_ich8lan) {
1186 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1187 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1188 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1191 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1193 /* Set the flow control receive threshold registers. Normally,
1194 * these registers will be set to a default threshold that may be
1195 * adjusted later by the driver's runtime code. However, if the
1196 * ability to transmit pause frames in not enabled, then these
1197 * registers will be set to 0.
1199 if (!(hw->fc & E1000_FC_TX_PAUSE)) {
1200 E1000_WRITE_REG(hw, FCRTL, 0);
1201 E1000_WRITE_REG(hw, FCRTH, 0);
1203 /* We need to set up the Receive Threshold high and low water marks
1204 * as well as (optionally) enabling the transmission of XON frames.
1206 if (hw->fc_send_xon) {
1207 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
1208 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1210 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1211 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1217 /******************************************************************************
1218 * Sets up link for a fiber based or serdes based adapter
1220 * hw - Struct containing variables accessed by shared code
1222 * Manipulates Physical Coding Sublayer functions in order to configure
1223 * link. Assumes the hardware has been previously reset and the transmitter
1224 * and receiver are not enabled.
1225 *****************************************************************************/
1227 em_setup_fiber_serdes_link(struct em_hw *hw)
1233 uint32_t signal = 0;
1236 DEBUGFUNC("em_setup_fiber_serdes_link");
1238 /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
1239 * until explicitly turned off or a power cycle is performed. A read to
1240 * the register does not indicate its status. Therefore, we ensure
1241 * loopback mode is disabled during initialization.
1243 if (hw->mac_type == em_82571 || hw->mac_type == em_82572)
1244 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
1246 /* On adapters with a MAC newer than 82544, SWDP 1 will be
1247 * set when the optics detect a signal. On older adapters, it will be
1248 * cleared when there is a signal. This applies to fiber media only.
1249 * If we're on serdes media, adjust the output amplitude to value
1250 * set in the EEPROM.
1252 ctrl = E1000_READ_REG(hw, CTRL);
1253 if (hw->media_type == em_media_type_fiber)
1254 signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0;
1256 ret_val = em_adjust_serdes_amplitude(hw);
1260 /* Take the link out of reset */
1261 ctrl &= ~(E1000_CTRL_LRST);
1263 /* Adjust VCO speed to improve BER performance */
1264 ret_val = em_set_vco_speed(hw);
1268 em_config_collision_dist(hw);
1270 /* Check for a software override of the flow control settings, and setup
1271 * the device accordingly. If auto-negotiation is enabled, then software
1272 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1273 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
1274 * auto-negotiation is disabled, then software will have to manually
1275 * configure the two flow control enable bits in the CTRL register.
1277 * The possible values of the "fc" parameter are:
1278 * 0: Flow control is completely disabled
1279 * 1: Rx flow control is enabled (we can receive pause frames, but
1280 * not send pause frames).
1281 * 2: Tx flow control is enabled (we can send pause frames but we do
1282 * not support receiving pause frames).
1283 * 3: Both Rx and TX flow control (symmetric) are enabled.
1287 /* Flow control is completely disabled by a software over-ride. */
1288 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1290 case E1000_FC_RX_PAUSE:
1291 /* RX Flow control is enabled and TX Flow control is disabled by a
1292 * software over-ride. Since there really isn't a way to advertise
1293 * that we are capable of RX Pause ONLY, we will advertise that we
1294 * support both symmetric and asymmetric RX PAUSE. Later, we will
1295 * disable the adapter's ability to send PAUSE frames.
1297 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1299 case E1000_FC_TX_PAUSE:
1300 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1301 * software over-ride.
1303 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1306 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1307 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1310 DEBUGOUT("Flow control param set incorrectly\n");
1311 return -E1000_ERR_CONFIG;
1315 /* Since auto-negotiation is enabled, take the link out of reset (the link
1316 * will be in reset, because we previously reset the chip). This will
1317 * restart auto-negotiation. If auto-neogtiation is successful then the
1318 * link-up status bit will be set and the flow control enable bits (RFCE
1319 * and TFCE) will be set according to their negotiated value.
1321 DEBUGOUT("Auto-negotiation enabled\n");
1323 E1000_WRITE_REG(hw, TXCW, txcw);
1324 E1000_WRITE_REG(hw, CTRL, ctrl);
1325 E1000_WRITE_FLUSH(hw);
1330 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1331 * indication in the Device Status Register. Time-out if a link isn't
1332 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
1333 * less than 500 milliseconds even if the other end is doing it in SW).
1334 * For internal serdes, we just assume a signal is present, then poll.
1336 if (hw->media_type == em_media_type_internal_serdes ||
1337 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1338 DEBUGOUT("Looking for Link\n");
1339 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1341 status = E1000_READ_REG(hw, STATUS);
1342 if (status & E1000_STATUS_LU) break;
1344 if (i == (LINK_UP_TIMEOUT / 10)) {
1345 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1346 hw->autoneg_failed = 1;
1347 /* AutoNeg failed to achieve a link, so we'll call
1348 * em_check_for_link. This routine will force the link up if
1349 * we detect a signal. This will allow us to communicate with
1350 * non-autonegotiating link partners.
1352 ret_val = em_check_for_link(hw);
1354 DEBUGOUT("Error while checking for link\n");
1357 hw->autoneg_failed = 0;
1359 hw->autoneg_failed = 0;
1360 DEBUGOUT("Valid Link Found\n");
1363 DEBUGOUT("No Signal Detected\n");
1365 return E1000_SUCCESS;
1368 /******************************************************************************
1369 * Make sure we have a valid PHY and change PHY mode before link setup.
1371 * hw - Struct containing variables accessed by shared code
1372 ******************************************************************************/
1374 em_copper_link_preconfig(struct em_hw *hw)
1380 DEBUGFUNC("em_copper_link_preconfig");
1382 ctrl = E1000_READ_REG(hw, CTRL);
1383 /* With 82543, we need to force speed and duplex on the MAC equal to what
1384 * the PHY speed and duplex configuration is. In addition, we need to
1385 * perform a hardware reset on the PHY to take it out of reset.
1387 if (hw->mac_type > em_82543) {
1388 ctrl |= E1000_CTRL_SLU;
1389 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1390 E1000_WRITE_REG(hw, CTRL, ctrl);
1392 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1393 E1000_WRITE_REG(hw, CTRL, ctrl);
1394 ret_val = em_phy_hw_reset(hw);
1399 /* Make sure we have a valid PHY */
1400 ret_val = em_detect_gig_phy(hw);
1402 DEBUGOUT("Error, did not detect valid phy.\n");
1405 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1407 /* Set PHY to class A mode (if necessary) */
1408 ret_val = em_set_phy_mode(hw);
1412 if ((hw->mac_type == em_82545_rev_3) ||
1413 (hw->mac_type == em_82546_rev_3)) {
1414 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1415 phy_data |= 0x00000008;
1416 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1419 if (hw->mac_type <= em_82543 ||
1420 hw->mac_type == em_82541 || hw->mac_type == em_82547 ||
1421 hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2)
1422 hw->phy_reset_disable = FALSE;
1424 return E1000_SUCCESS;
1428 /********************************************************************
1429 * Copper link setup for em_phy_igp series.
1431 * hw - Struct containing variables accessed by shared code
1432 *********************************************************************/
1434 em_copper_link_igp_setup(struct em_hw *hw)
1440 DEBUGFUNC("em_copper_link_igp_setup");
1442 if (hw->phy_reset_disable)
1443 return E1000_SUCCESS;
1445 ret_val = em_phy_reset(hw);
1447 DEBUGOUT("Error Resetting the PHY\n");
1451 /* Wait 15ms for MAC to configure PHY from eeprom settings */
1453 if (hw->mac_type != em_ich8lan) {
1454 /* Configure activity LED after PHY reset */
1455 led_ctrl = E1000_READ_REG(hw, LEDCTL);
1456 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1457 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1458 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1461 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1462 if (hw->phy_type == em_phy_igp) {
1463 /* disable lplu d3 during driver init */
1464 ret_val = em_set_d3_lplu_state(hw, FALSE);
1466 DEBUGOUT("Error Disabling LPLU D3\n");
1471 /* disable lplu d0 during driver init */
1472 ret_val = em_set_d0_lplu_state(hw, FALSE);
1474 DEBUGOUT("Error Disabling LPLU D0\n");
1477 /* Configure mdi-mdix settings */
1478 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1482 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
1483 hw->dsp_config_state = em_dsp_config_disabled;
1484 /* Force MDI for earlier revs of the IGP PHY */
1485 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
1489 hw->dsp_config_state = em_dsp_config_enabled;
1490 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1494 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1497 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1501 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1505 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1509 /* set auto-master slave resolution settings */
1511 em_ms_type phy_ms_setting = hw->master_slave;
1513 if (hw->ffe_config_state == em_ffe_config_active)
1514 hw->ffe_config_state = em_ffe_config_enabled;
1516 if (hw->dsp_config_state == em_dsp_config_activated)
1517 hw->dsp_config_state = em_dsp_config_enabled;
1519 /* when autonegotiation advertisment is only 1000Mbps then we
1520 * should disable SmartSpeed and enable Auto MasterSlave
1521 * resolution as hardware default. */
1522 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1523 /* Disable SmartSpeed */
1524 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1528 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1529 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1533 /* Set auto Master/Slave resolution process */
1534 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1537 phy_data &= ~CR_1000T_MS_ENABLE;
1538 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1543 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1547 /* load defaults for future use */
1548 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1549 ((phy_data & CR_1000T_MS_VALUE) ?
1550 em_ms_force_master :
1551 em_ms_force_slave) :
1554 switch (phy_ms_setting) {
1555 case em_ms_force_master:
1556 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1558 case em_ms_force_slave:
1559 phy_data |= CR_1000T_MS_ENABLE;
1560 phy_data &= ~(CR_1000T_MS_VALUE);
1563 phy_data &= ~CR_1000T_MS_ENABLE;
1567 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1572 return E1000_SUCCESS;
1575 /********************************************************************
1576 * Copper link setup for em_phy_gg82563 series.
1578 * hw - Struct containing variables accessed by shared code
1579 *********************************************************************/
1581 em_copper_link_ggp_setup(struct em_hw *hw)
1587 DEBUGFUNC("em_copper_link_ggp_setup");
1589 if (!hw->phy_reset_disable) {
1591 /* Enable CRS on TX for half-duplex operation. */
1592 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1597 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1598 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
1599 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
1601 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1607 * MDI/MDI-X = 0 (default)
1608 * 0 - Auto for all speeds
1611 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1613 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
1617 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1621 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1624 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1628 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1633 * disable_polarity_correction = 0 (default)
1634 * Automatic Correction for Reversed Cable Polarity
1638 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1639 if (hw->disable_polarity_correction == 1)
1640 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1641 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
1646 /* SW Reset the PHY so all changes take effect */
1647 ret_val = em_phy_reset(hw);
1649 DEBUGOUT("Error Resetting the PHY\n");
1652 } /* phy_reset_disable */
1654 if (hw->mac_type == em_80003es2lan) {
1655 /* Bypass RX and TX FIFO's */
1656 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
1657 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
1658 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
1662 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
1666 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1667 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
1672 reg_data = E1000_READ_REG(hw, CTRL_EXT);
1673 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1674 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
1676 ret_val = em_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1681 /* Do not init these registers when the HW is in IAMT mode, since the
1682 * firmware will have already initialized them. We only initialize
1683 * them if the HW is not in IAMT mode.
1685 if (em_check_mng_mode(hw) == FALSE) {
1686 /* Enable Electrical Idle on the PHY */
1687 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1688 ret_val = em_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1693 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1698 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1699 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1706 /* Workaround: Disable padding in Kumeran interface in the MAC
1707 * and in the PHY to avoid CRC errors.
1709 ret_val = em_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1713 phy_data |= GG82563_ICR_DIS_PADDING;
1714 ret_val = em_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1720 return E1000_SUCCESS;
1723 /********************************************************************
1724 * Copper link setup for em_phy_m88 series.
1726 * hw - Struct containing variables accessed by shared code
1727 *********************************************************************/
1729 em_copper_link_mgp_setup(struct em_hw *hw)
1734 DEBUGFUNC("em_copper_link_mgp_setup");
1736 if (hw->phy_reset_disable)
1737 return E1000_SUCCESS;
1739 /* Enable CRS on TX. This must be set for half-duplex operation. */
1740 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1744 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1747 * MDI/MDI-X = 0 (default)
1748 * 0 - Auto for all speeds
1751 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1753 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1757 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1760 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1763 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1767 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1772 * disable_polarity_correction = 0 (default)
1773 * Automatic Correction for Reversed Cable Polarity
1777 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1778 if (hw->disable_polarity_correction == 1)
1779 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1780 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1784 if (hw->phy_revision < M88E1011_I_REV_4) {
1785 /* Force TX_CLK in the Extended PHY Specific Control Register
1788 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1792 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1794 if ((hw->phy_revision == E1000_REVISION_2) &&
1795 (hw->phy_id == M88E1111_I_PHY_ID)) {
1796 /* Vidalia Phy, set the downshift counter to 5x */
1797 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1798 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1799 ret_val = em_write_phy_reg(hw,
1800 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1804 /* Configure Master and Slave downshift values */
1805 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1806 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1807 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1808 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1809 ret_val = em_write_phy_reg(hw,
1810 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1816 /* SW Reset the PHY so all changes take effect */
1817 ret_val = em_phy_reset(hw);
1819 DEBUGOUT("Error Resetting the PHY\n");
1823 return E1000_SUCCESS;
1826 /********************************************************************
1827 * Setup auto-negotiation and flow control advertisements,
1828 * and then perform auto-negotiation.
1830 * hw - Struct containing variables accessed by shared code
1831 *********************************************************************/
1833 em_copper_link_autoneg(struct em_hw *hw)
1838 DEBUGFUNC("em_copper_link_autoneg");
1840 /* Perform some bounds checking on the hw->autoneg_advertised
1841 * parameter. If this variable is zero, then set it to the default.
1843 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1845 /* If autoneg_advertised is zero, we assume it was not defaulted
1846 * by the calling code so we set to advertise full capability.
1848 if (hw->autoneg_advertised == 0)
1849 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1851 /* IFE phy only supports 10/100 */
1852 if (hw->phy_type == em_phy_ife)
1853 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1855 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1856 ret_val = em_phy_setup_autoneg(hw);
1858 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1861 DEBUGOUT("Restarting Auto-Neg\n");
1863 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1864 * the Auto Neg Restart bit in the PHY control register.
1866 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data);
1870 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1871 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data);
1875 /* Does the user want to wait for Auto-Neg to complete here, or
1876 * check at a later time (for example, callback routine).
1878 if (hw->wait_autoneg_complete) {
1879 ret_val = em_wait_autoneg(hw);
1881 DEBUGOUT("Error while waiting for autoneg to complete\n");
1886 hw->get_link_status = TRUE;
1888 return E1000_SUCCESS;
1891 /******************************************************************************
1892 * Config the MAC and the PHY after link is up.
1893 * 1) Set up the MAC to the current PHY speed/duplex
1894 * if we are on 82543. If we
1895 * are on newer silicon, we only need to configure
1896 * collision distance in the Transmit Control Register.
1897 * 2) Set up flow control on the MAC to that established with
1899 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1901 * hw - Struct containing variables accessed by shared code
1902 ******************************************************************************/
1904 em_copper_link_postconfig(struct em_hw *hw)
1907 DEBUGFUNC("em_copper_link_postconfig");
1909 if (hw->mac_type >= em_82544) {
1910 em_config_collision_dist(hw);
1912 ret_val = em_config_mac_to_phy(hw);
1914 DEBUGOUT("Error configuring MAC to PHY settings\n");
1918 ret_val = em_config_fc_after_link_up(hw);
1920 DEBUGOUT("Error Configuring Flow Control\n");
1924 /* Config DSP to improve Giga link quality */
1925 if (hw->phy_type == em_phy_igp) {
1926 ret_val = em_config_dsp_after_link_change(hw, TRUE);
1928 DEBUGOUT("Error Configuring DSP after link up\n");
1933 return E1000_SUCCESS;
1936 /******************************************************************************
1937 * Detects which PHY is present and setup the speed and duplex
1939 * hw - Struct containing variables accessed by shared code
1940 ******************************************************************************/
1942 em_setup_copper_link(struct em_hw *hw)
1949 DEBUGFUNC("em_setup_copper_link");
1951 switch (hw->mac_type) {
1952 case em_80003es2lan:
1954 /* Set the mac to wait the maximum time between each
1955 * iteration and increase the max iterations when
1956 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
1957 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1960 ret_val = em_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data);
1964 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1971 /* Check if it is a valid PHY and set PHY mode if necessary. */
1972 ret_val = em_copper_link_preconfig(hw);
1976 switch (hw->mac_type) {
1977 case em_80003es2lan:
1978 /* Kumeran registers are written-only */
1979 reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
1980 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
1981 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
1990 if (hw->phy_type == em_phy_igp ||
1991 hw->phy_type == em_phy_igp_3 ||
1992 hw->phy_type == em_phy_igp_2) {
1993 ret_val = em_copper_link_igp_setup(hw);
1996 } else if (hw->phy_type == em_phy_m88) {
1997 ret_val = em_copper_link_mgp_setup(hw);
2000 } else if (hw->phy_type == em_phy_gg82563) {
2001 ret_val = em_copper_link_ggp_setup(hw);
2007 /* Setup autoneg and flow control advertisement
2008 * and perform autonegotiation */
2009 ret_val = em_copper_link_autoneg(hw);
2013 /* PHY will be set to 10H, 10F, 100H,or 100F
2014 * depending on value from forced_speed_duplex. */
2015 DEBUGOUT("Forcing speed and duplex\n");
2016 ret_val = em_phy_force_speed_duplex(hw);
2018 DEBUGOUT("Error Forcing Speed and Duplex\n");
2023 /* Check link status. Wait up to 100 microseconds for link to become
2026 for (i = 0; i < 10; i++) {
2027 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
2030 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
2034 if (phy_data & MII_SR_LINK_STATUS) {
2035 /* Config the MAC and PHY after link is up */
2036 ret_val = em_copper_link_postconfig(hw);
2040 DEBUGOUT("Valid link established!!!\n");
2041 return E1000_SUCCESS;
2046 DEBUGOUT("Unable to establish link!!!\n");
2047 return E1000_SUCCESS;
2050 /******************************************************************************
2051 * Configure the MAC-to-PHY interface for 10/100Mbps
2053 * hw - Struct containing variables accessed by shared code
2054 ******************************************************************************/
2056 em_configure_kmrn_for_10_100(struct em_hw *hw, uint16_t duplex)
2058 int32_t ret_val = E1000_SUCCESS;
2062 DEBUGFUNC("em_configure_kmrn_for_10_100");
2064 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
2065 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2070 /* Configure Transmit Inter-Packet Gap */
2071 tipg = E1000_READ_REG(hw, TIPG);
2072 tipg &= ~E1000_TIPG_IPGT_MASK;
2073 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
2074 E1000_WRITE_REG(hw, TIPG, tipg);
2076 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
2081 if (duplex == HALF_DUPLEX)
2082 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
2084 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2086 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2092 em_configure_kmrn_for_1000(struct em_hw *hw)
2094 int32_t ret_val = E1000_SUCCESS;
2098 DEBUGFUNC("em_configure_kmrn_for_1000");
2100 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
2101 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2106 /* Configure Transmit Inter-Packet Gap */
2107 tipg = E1000_READ_REG(hw, TIPG);
2108 tipg &= ~E1000_TIPG_IPGT_MASK;
2109 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
2110 E1000_WRITE_REG(hw, TIPG, tipg);
2112 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
2117 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2118 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2123 /******************************************************************************
2124 * Configures PHY autoneg and flow control advertisement settings
2126 * hw - Struct containing variables accessed by shared code
2127 ******************************************************************************/
2129 em_phy_setup_autoneg(struct em_hw *hw)
2132 uint16_t mii_autoneg_adv_reg;
2133 uint16_t mii_1000t_ctrl_reg;
2135 DEBUGFUNC("em_phy_setup_autoneg");
2137 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2138 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
2142 if (hw->phy_type != em_phy_ife) {
2143 /* Read the MII 1000Base-T Control Register (Address 9). */
2144 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
2148 mii_1000t_ctrl_reg=0;
2150 /* Need to parse both autoneg_advertised and fc and set up
2151 * the appropriate PHY registers. First we will parse for
2152 * autoneg_advertised software override. Since we can advertise
2153 * a plethora of combinations, we need to check each bit
2157 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2158 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2159 * the 1000Base-T Control Register (Address 9).
2161 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
2162 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
2164 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
2166 /* Do we want to advertise 10 Mb Half Duplex? */
2167 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
2168 DEBUGOUT("Advertise 10mb Half duplex\n");
2169 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
2172 /* Do we want to advertise 10 Mb Full Duplex? */
2173 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
2174 DEBUGOUT("Advertise 10mb Full duplex\n");
2175 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
2178 /* Do we want to advertise 100 Mb Half Duplex? */
2179 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
2180 DEBUGOUT("Advertise 100mb Half duplex\n");
2181 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
2184 /* Do we want to advertise 100 Mb Full Duplex? */
2185 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
2186 DEBUGOUT("Advertise 100mb Full duplex\n");
2187 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
2190 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
2191 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
2192 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
2195 /* Do we want to advertise 1000 Mb Full Duplex? */
2196 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
2197 DEBUGOUT("Advertise 1000mb Full duplex\n");
2198 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
2199 if (hw->phy_type == em_phy_ife) {
2200 DEBUGOUT("em_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
2204 /* Check for a software override of the flow control settings, and
2205 * setup the PHY advertisement registers accordingly. If
2206 * auto-negotiation is enabled, then software will have to set the
2207 * "PAUSE" bits to the correct value in the Auto-Negotiation
2208 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
2210 * The possible values of the "fc" parameter are:
2211 * 0: Flow control is completely disabled
2212 * 1: Rx flow control is enabled (we can receive pause frames
2213 * but not send pause frames).
2214 * 2: Tx flow control is enabled (we can send pause frames
2215 * but we do not support receiving pause frames).
2216 * 3: Both Rx and TX flow control (symmetric) are enabled.
2217 * other: No software override. The flow control configuration
2218 * in the EEPROM is used.
2221 case E1000_FC_NONE: /* 0 */
2222 /* Flow control (RX & TX) is completely disabled by a
2223 * software over-ride.
2225 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2227 case E1000_FC_RX_PAUSE: /* 1 */
2228 /* RX Flow control is enabled, and TX Flow control is
2229 * disabled, by a software over-ride.
2231 /* Since there really isn't a way to advertise that we are
2232 * capable of RX Pause ONLY, we will advertise that we
2233 * support both symmetric and asymmetric RX PAUSE. Later
2234 * (in em_config_fc_after_link_up) we will disable the
2235 *hw's ability to send PAUSE frames.
2237 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2239 case E1000_FC_TX_PAUSE: /* 2 */
2240 /* TX Flow control is enabled, and RX Flow control is
2241 * disabled, by a software over-ride.
2243 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
2244 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
2246 case E1000_FC_FULL: /* 3 */
2247 /* Flow control (both RX and TX) is enabled by a software
2250 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2253 DEBUGOUT("Flow control param set incorrectly\n");
2254 return -E1000_ERR_CONFIG;
2257 ret_val = em_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
2261 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
2263 if (hw->phy_type != em_phy_ife) {
2264 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
2269 return E1000_SUCCESS;
2272 /******************************************************************************
2273 * Force PHY speed and duplex settings to hw->forced_speed_duplex
2275 * hw - Struct containing variables accessed by shared code
2276 ******************************************************************************/
2278 em_phy_force_speed_duplex(struct em_hw *hw)
2282 uint16_t mii_ctrl_reg;
2283 uint16_t mii_status_reg;
2287 DEBUGFUNC("em_phy_force_speed_duplex");
2289 /* Turn off Flow control if we are forcing speed and duplex. */
2290 hw->fc = E1000_FC_NONE;
2292 DEBUGOUT1("hw->fc = %d\n", hw->fc);
2294 /* Read the Device Control Register. */
2295 ctrl = E1000_READ_REG(hw, CTRL);
2297 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
2298 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2299 ctrl &= ~(DEVICE_SPEED_MASK);
2301 /* Clear the Auto Speed Detect Enable bit. */
2302 ctrl &= ~E1000_CTRL_ASDE;
2304 /* Read the MII Control Register. */
2305 ret_val = em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
2309 /* We need to disable autoneg in order to force link and duplex. */
2311 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
2313 /* Are we forcing Full or Half Duplex? */
2314 if (hw->forced_speed_duplex == em_100_full ||
2315 hw->forced_speed_duplex == em_10_full) {
2316 /* We want to force full duplex so we SET the full duplex bits in the
2317 * Device and MII Control Registers.
2319 ctrl |= E1000_CTRL_FD;
2320 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
2321 DEBUGOUT("Full Duplex\n");
2323 /* We want to force half duplex so we CLEAR the full duplex bits in
2324 * the Device and MII Control Registers.
2326 ctrl &= ~E1000_CTRL_FD;
2327 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
2328 DEBUGOUT("Half Duplex\n");
2331 /* Are we forcing 100Mbps??? */
2332 if (hw->forced_speed_duplex == em_100_full ||
2333 hw->forced_speed_duplex == em_100_half) {
2334 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
2335 ctrl |= E1000_CTRL_SPD_100;
2336 mii_ctrl_reg |= MII_CR_SPEED_100;
2337 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
2338 DEBUGOUT("Forcing 100mb ");
2340 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
2341 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2342 mii_ctrl_reg |= MII_CR_SPEED_10;
2343 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2344 DEBUGOUT("Forcing 10mb ");
2347 em_config_collision_dist(hw);
2349 /* Write the configured values back to the Device Control Reg. */
2350 E1000_WRITE_REG(hw, CTRL, ctrl);
2352 if ((hw->phy_type == em_phy_m88) ||
2353 (hw->phy_type == em_phy_gg82563)) {
2354 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2358 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
2359 * forced whenever speed are duplex are forced.
2361 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2362 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2366 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
2368 /* Need to reset the PHY or these changes will be ignored */
2369 mii_ctrl_reg |= MII_CR_RESET;
2371 /* Disable MDI-X support for 10/100 */
2372 } else if (hw->phy_type == em_phy_ife) {
2373 ret_val = em_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
2377 phy_data &= ~IFE_PMC_AUTO_MDIX;
2378 phy_data &= ~IFE_PMC_FORCE_MDIX;
2380 ret_val = em_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
2385 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
2386 * forced whenever speed or duplex are forced.
2388 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2392 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2393 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2395 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2400 /* Write back the modified PHY MII control register. */
2401 ret_val = em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
2407 /* The wait_autoneg_complete flag may be a little misleading here.
2408 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
2409 * But we do want to delay for a period while forcing only so we
2410 * don't generate false No Link messages. So we will wait here
2411 * only if the user has set wait_autoneg_complete to 1, which is
2414 if (hw->wait_autoneg_complete) {
2415 /* We will wait for autoneg to complete. */
2416 DEBUGOUT("Waiting for forced speed/duplex link.\n");
2419 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2420 for (i = PHY_FORCE_TIME; i > 0; i--) {
2421 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2424 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2428 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2432 if (mii_status_reg & MII_SR_LINK_STATUS) break;
2436 ((hw->phy_type == em_phy_m88) ||
2437 (hw->phy_type == em_phy_gg82563))) {
2438 /* We didn't get link. Reset the DSP and wait again for link. */
2439 ret_val = em_phy_reset_dsp(hw);
2441 DEBUGOUT("Error Resetting PHY DSP\n");
2445 /* This loop will early-out if the link condition has been met. */
2446 for (i = PHY_FORCE_TIME; i > 0; i--) {
2447 if (mii_status_reg & MII_SR_LINK_STATUS) break;
2449 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2452 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2456 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2462 if (hw->phy_type == em_phy_m88) {
2463 /* Because we reset the PHY above, we need to re-force TX_CLK in the
2464 * Extended PHY Specific Control Register to 25MHz clock. This value
2465 * defaults back to a 2.5MHz clock when the PHY is reset.
2467 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2471 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2472 ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2476 /* In addition, because of the s/w reset above, we need to enable CRS on
2477 * TX. This must be set for both full and half duplex operation.
2479 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2483 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2484 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2488 if ((hw->mac_type == em_82544 || hw->mac_type == em_82543) &&
2489 (!hw->autoneg) && (hw->forced_speed_duplex == em_10_full ||
2490 hw->forced_speed_duplex == em_10_half)) {
2491 ret_val = em_polarity_reversal_workaround(hw);
2495 } else if (hw->phy_type == em_phy_gg82563) {
2496 /* The TX_CLK of the Extended PHY Specific Control Register defaults
2497 * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if
2498 * we're not in a forced 10/duplex configuration. */
2499 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2503 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
2504 if ((hw->forced_speed_duplex == em_10_full) ||
2505 (hw->forced_speed_duplex == em_10_half))
2506 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
2508 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
2510 /* Also due to the reset, we need to enable CRS on Tx. */
2511 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2513 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2517 return E1000_SUCCESS;
2520 /******************************************************************************
2521 * Sets the collision distance in the Transmit Control register
2523 * hw - Struct containing variables accessed by shared code
2525 * Link should have been established previously. Reads the speed and duplex
2526 * information from the Device Status register.
2527 ******************************************************************************/
2529 em_config_collision_dist(struct em_hw *hw)
2531 uint32_t tctl, coll_dist;
2533 DEBUGFUNC("em_config_collision_dist");
2535 if (hw->mac_type < em_82543)
2536 coll_dist = E1000_COLLISION_DISTANCE_82542;
2538 coll_dist = E1000_COLLISION_DISTANCE;
2540 tctl = E1000_READ_REG(hw, TCTL);
2542 tctl &= ~E1000_TCTL_COLD;
2543 tctl |= coll_dist << E1000_COLD_SHIFT;
2545 E1000_WRITE_REG(hw, TCTL, tctl);
2546 E1000_WRITE_FLUSH(hw);
2549 /******************************************************************************
2550 * Sets MAC speed and duplex settings to reflect the those in the PHY
2552 * hw - Struct containing variables accessed by shared code
2553 * mii_reg - data to write to the MII control register
2555 * The contents of the PHY register containing the needed information need to
2557 ******************************************************************************/
2559 em_config_mac_to_phy(struct em_hw *hw)
2565 DEBUGFUNC("em_config_mac_to_phy");
2567 /* 82544 or newer MAC, Auto Speed Detection takes care of
2568 * MAC speed/duplex configuration.*/
2569 if (hw->mac_type >= em_82544)
2570 return E1000_SUCCESS;
2572 /* Read the Device Control Register and set the bits to Force Speed
2575 ctrl = E1000_READ_REG(hw, CTRL);
2576 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2577 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
2579 /* Set up duplex in the Device Control and Transmit Control
2580 * registers depending on negotiated values.
2582 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2586 if (phy_data & M88E1000_PSSR_DPLX)
2587 ctrl |= E1000_CTRL_FD;
2589 ctrl &= ~E1000_CTRL_FD;
2591 em_config_collision_dist(hw);
2593 /* Set up speed in the Device Control register depending on
2594 * negotiated values.
2596 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2597 ctrl |= E1000_CTRL_SPD_1000;
2598 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
2599 ctrl |= E1000_CTRL_SPD_100;
2601 /* Write the configured values back to the Device Control Reg. */
2602 E1000_WRITE_REG(hw, CTRL, ctrl);
2603 return E1000_SUCCESS;
2606 /******************************************************************************
2607 * Forces the MAC's flow control settings.
2609 * hw - Struct containing variables accessed by shared code
2611 * Sets the TFCE and RFCE bits in the device control register to reflect
2612 * the adapter settings. TFCE and RFCE need to be explicitly set by
2613 * software when a Copper PHY is used because autonegotiation is managed
2614 * by the PHY rather than the MAC. Software must also configure these
2615 * bits when link is forced on a fiber connection.
2616 *****************************************************************************/
2618 em_force_mac_fc(struct em_hw *hw)
2622 DEBUGFUNC("em_force_mac_fc");
2624 /* Get the current configuration of the Device Control Register */
2625 ctrl = E1000_READ_REG(hw, CTRL);
2627 /* Because we didn't get link via the internal auto-negotiation
2628 * mechanism (we either forced link or we got link via PHY
2629 * auto-neg), we have to manually enable/disable transmit an
2630 * receive flow control.
2632 * The "Case" statement below enables/disable flow control
2633 * according to the "hw->fc" parameter.
2635 * The possible values of the "fc" parameter are:
2636 * 0: Flow control is completely disabled
2637 * 1: Rx flow control is enabled (we can receive pause
2638 * frames but not send pause frames).
2639 * 2: Tx flow control is enabled (we can send pause frames
2640 * frames but we do not receive pause frames).
2641 * 3: Both Rx and TX flow control (symmetric) is enabled.
2642 * other: No other values should be possible at this point.
2647 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2649 case E1000_FC_RX_PAUSE:
2650 ctrl &= (~E1000_CTRL_TFCE);
2651 ctrl |= E1000_CTRL_RFCE;
2653 case E1000_FC_TX_PAUSE:
2654 ctrl &= (~E1000_CTRL_RFCE);
2655 ctrl |= E1000_CTRL_TFCE;
2658 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2661 DEBUGOUT("Flow control param set incorrectly\n");
2662 return -E1000_ERR_CONFIG;
2665 /* Disable TX Flow Control for 82542 (rev 2.0) */
2666 if (hw->mac_type == em_82542_rev2_0)
2667 ctrl &= (~E1000_CTRL_TFCE);
2669 E1000_WRITE_REG(hw, CTRL, ctrl);
2670 return E1000_SUCCESS;
2673 /******************************************************************************
2674 * Configures flow control settings after link is established
2676 * hw - Struct containing variables accessed by shared code
2678 * Should be called immediately after a valid link has been established.
2679 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2680 * and autonegotiation is enabled, the MAC flow control settings will be set
2681 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2682 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
2683 *****************************************************************************/
2685 em_config_fc_after_link_up(struct em_hw *hw)
2688 uint16_t mii_status_reg;
2689 uint16_t mii_nway_adv_reg;
2690 uint16_t mii_nway_lp_ability_reg;
2694 DEBUGFUNC("em_config_fc_after_link_up");
2696 /* Check for the case where we have fiber media and auto-neg failed
2697 * so we had to force link. In this case, we need to force the
2698 * configuration of the MAC to match the "fc" parameter.
2700 if (((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed)) ||
2701 ((hw->media_type == em_media_type_internal_serdes) &&
2702 (hw->autoneg_failed)) ||
2703 ((hw->media_type == em_media_type_copper) && (!hw->autoneg))) {
2704 ret_val = em_force_mac_fc(hw);
2706 DEBUGOUT("Error forcing flow control settings\n");
2711 /* Check for the case where we have copper media and auto-neg is
2712 * enabled. In this case, we need to check and see if Auto-Neg
2713 * has completed, and if so, how the PHY and link partner has
2714 * flow control configured.
2716 if ((hw->media_type == em_media_type_copper) && hw->autoneg) {
2717 /* Read the MII Status Register and check to see if AutoNeg
2718 * has completed. We read this twice because this reg has
2719 * some "sticky" (latched) bits.
2721 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2724 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2728 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2729 /* The AutoNeg process has completed, so we now need to
2730 * read both the Auto Negotiation Advertisement Register
2731 * (Address 4) and the Auto_Negotiation Base Page Ability
2732 * Register (Address 5) to determine how flow control was
2735 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV,
2739 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY,
2740 &mii_nway_lp_ability_reg);
2744 /* Two bits in the Auto Negotiation Advertisement Register
2745 * (Address 4) and two bits in the Auto Negotiation Base
2746 * Page Ability Register (Address 5) determine flow control
2747 * for both the PHY and the link partner. The following
2748 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2749 * 1999, describes these PAUSE resolution bits and how flow
2750 * control is determined based upon these settings.
2751 * NOTE: DC = Don't Care
2753 * LOCAL DEVICE | LINK PARTNER
2754 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2755 *-------|---------|-------|---------|--------------------
2756 * 0 | 0 | DC | DC | em_fc_none
2757 * 0 | 1 | 0 | DC | em_fc_none
2758 * 0 | 1 | 1 | 0 | em_fc_none
2759 * 0 | 1 | 1 | 1 | em_fc_tx_pause
2760 * 1 | 0 | 0 | DC | em_fc_none
2761 * 1 | DC | 1 | DC | em_fc_full
2762 * 1 | 1 | 0 | 0 | em_fc_none
2763 * 1 | 1 | 0 | 1 | em_fc_rx_pause
2766 /* Are both PAUSE bits set to 1? If so, this implies
2767 * Symmetric Flow Control is enabled at both ends. The
2768 * ASM_DIR bits are irrelevant per the spec.
2770 * For Symmetric Flow Control:
2772 * LOCAL DEVICE | LINK PARTNER
2773 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2774 *-------|---------|-------|---------|--------------------
2775 * 1 | DC | 1 | DC | em_fc_full
2778 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2779 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2780 /* Now we need to check if the user selected RX ONLY
2781 * of pause frames. In this case, we had to advertise
2782 * FULL flow control because we could not advertise RX
2783 * ONLY. Hence, we must now check to see if we need to
2784 * turn OFF the TRANSMISSION of PAUSE frames.
2786 if (hw->original_fc == E1000_FC_FULL) {
2787 hw->fc = E1000_FC_FULL;
2788 DEBUGOUT("Flow Control = FULL.\n");
2790 hw->fc = E1000_FC_RX_PAUSE;
2791 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2794 /* For receiving PAUSE frames ONLY.
2796 * LOCAL DEVICE | LINK PARTNER
2797 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2798 *-------|---------|-------|---------|--------------------
2799 * 0 | 1 | 1 | 1 | em_fc_tx_pause
2802 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2803 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2804 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2805 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2806 hw->fc = E1000_FC_TX_PAUSE;
2807 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2809 /* For transmitting PAUSE frames ONLY.
2811 * LOCAL DEVICE | LINK PARTNER
2812 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2813 *-------|---------|-------|---------|--------------------
2814 * 1 | 1 | 0 | 1 | em_fc_rx_pause
2817 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2818 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2819 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2820 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2821 hw->fc = E1000_FC_RX_PAUSE;
2822 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2824 /* Per the IEEE spec, at this point flow control should be
2825 * disabled. However, we want to consider that we could
2826 * be connected to a legacy switch that doesn't advertise
2827 * desired flow control, but can be forced on the link
2828 * partner. So if we advertised no flow control, that is
2829 * what we will resolve to. If we advertised some kind of
2830 * receive capability (Rx Pause Only or Full Flow Control)
2831 * and the link partner advertised none, we will configure
2832 * ourselves to enable Rx Flow Control only. We can do
2833 * this safely for two reasons: If the link partner really
2834 * didn't want flow control enabled, and we enable Rx, no
2835 * harm done since we won't be receiving any PAUSE frames
2836 * anyway. If the intent on the link partner was to have
2837 * flow control enabled, then by us enabling RX only, we
2838 * can at least receive pause frames and process them.
2839 * This is a good idea because in most cases, since we are
2840 * predominantly a server NIC, more times than not we will
2841 * be asked to delay transmission of packets than asking
2842 * our link partner to pause transmission of frames.
2844 else if ((hw->original_fc == E1000_FC_NONE||
2845 hw->original_fc == E1000_FC_TX_PAUSE) ||
2846 hw->fc_strict_ieee) {
2847 hw->fc = E1000_FC_NONE;
2848 DEBUGOUT("Flow Control = NONE.\n");
2850 hw->fc = E1000_FC_RX_PAUSE;
2851 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2854 /* Now we need to do one last check... If we auto-
2855 * negotiated to HALF DUPLEX, flow control should not be
2856 * enabled per IEEE 802.3 spec.
2858 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex);
2860 DEBUGOUT("Error getting link speed and duplex\n");
2864 if (duplex == HALF_DUPLEX)
2865 hw->fc = E1000_FC_NONE;
2867 /* Now we call a subroutine to actually force the MAC
2868 * controller to use the correct flow control settings.
2870 ret_val = em_force_mac_fc(hw);
2872 DEBUGOUT("Error forcing flow control settings\n");
2876 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
2879 return E1000_SUCCESS;
2882 /******************************************************************************
2883 * Checks to see if the link status of the hardware has changed.
2885 * hw - Struct containing variables accessed by shared code
2887 * Called by any function that needs to check the link status of the adapter.
2888 *****************************************************************************/
2890 em_check_for_link(struct em_hw *hw)
2897 uint32_t signal = 0;
2901 DEBUGFUNC("em_check_for_link");
2903 ctrl = E1000_READ_REG(hw, CTRL);
2904 status = E1000_READ_REG(hw, STATUS);
2906 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
2907 * set when the optics detect a signal. On older adapters, it will be
2908 * cleared when there is a signal. This applies to fiber media only.
2910 if ((hw->media_type == em_media_type_fiber) ||
2911 (hw->media_type == em_media_type_internal_serdes)) {
2912 rxcw = E1000_READ_REG(hw, RXCW);
2914 if (hw->media_type == em_media_type_fiber) {
2915 signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0;
2916 if (status & E1000_STATUS_LU)
2917 hw->get_link_status = FALSE;
2921 /* If we have a copper PHY then we only want to go out to the PHY
2922 * registers to see if Auto-Neg has completed and/or if our link
2923 * status has changed. The get_link_status flag will be set if we
2924 * receive a Link Status Change interrupt or we have Rx Sequence
2927 if ((hw->media_type == em_media_type_copper) && hw->get_link_status) {
2928 /* First we want to see if the MII Status Register reports
2929 * link. If so, then we want to get the current speed/duplex
2931 * Read the register twice since the link bit is sticky.
2933 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
2936 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
2940 if (phy_data & MII_SR_LINK_STATUS) {
2941 hw->get_link_status = FALSE;
2942 /* Check if there was DownShift, must be checked immediately after
2944 em_check_downshift(hw);
2946 /* If we are on 82544 or 82543 silicon and speed/duplex
2947 * are forced to 10H or 10F, then we will implement the polarity
2948 * reversal workaround. We disable interrupts first, and upon
2949 * returning, place the devices interrupt state to its previous
2950 * value except for the link status change interrupt which will
2951 * happen due to the execution of this workaround.
2954 if ((hw->mac_type == em_82544 || hw->mac_type == em_82543) &&
2956 (hw->forced_speed_duplex == em_10_full ||
2957 hw->forced_speed_duplex == em_10_half)) {
2958 E1000_WRITE_REG(hw, IMC, 0xffffffff);
2959 ret_val = em_polarity_reversal_workaround(hw);
2960 icr = E1000_READ_REG(hw, ICR);
2961 E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC));
2962 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK);
2966 /* No link detected */
2967 em_config_dsp_after_link_change(hw, FALSE);
2971 /* If we are forcing speed/duplex, then we simply return since
2972 * we have already determined whether we have link or not.
2974 if (!hw->autoneg) return -E1000_ERR_CONFIG;
2976 /* optimize the dsp settings for the igp phy */
2977 em_config_dsp_after_link_change(hw, TRUE);
2979 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2980 * have Si on board that is 82544 or newer, Auto
2981 * Speed Detection takes care of MAC speed/duplex
2982 * configuration. So we only need to configure Collision
2983 * Distance in the MAC. Otherwise, we need to force
2984 * speed/duplex on the MAC to the current PHY speed/duplex
2987 if (hw->mac_type >= em_82544)
2988 em_config_collision_dist(hw);
2990 ret_val = em_config_mac_to_phy(hw);
2992 DEBUGOUT("Error configuring MAC to PHY settings\n");
2997 /* Configure Flow Control now that Auto-Neg has completed. First, we
2998 * need to restore the desired flow control settings because we may
2999 * have had to re-autoneg with a different link partner.
3001 ret_val = em_config_fc_after_link_up(hw);
3003 DEBUGOUT("Error configuring flow control\n");
3007 /* At this point we know that we are on copper and we have
3008 * auto-negotiated link. These are conditions for checking the link
3009 * partner capability register. We use the link speed to determine if
3010 * TBI compatibility needs to be turned on or off. If the link is not
3011 * at gigabit speed, then TBI compatibility is not needed. If we are
3012 * at gigabit speed, we turn on TBI compatibility.
3014 if (hw->tbi_compatibility_en) {
3015 uint16_t speed, duplex;
3016 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex);
3018 DEBUGOUT("Error getting link speed and duplex\n");
3021 if (speed != SPEED_1000) {
3022 /* If link speed is not set to gigabit speed, we do not need
3023 * to enable TBI compatibility.
3025 if (hw->tbi_compatibility_on) {
3026 /* If we previously were in the mode, turn it off. */
3027 rctl = E1000_READ_REG(hw, RCTL);
3028 rctl &= ~E1000_RCTL_SBP;
3029 E1000_WRITE_REG(hw, RCTL, rctl);
3030 hw->tbi_compatibility_on = FALSE;
3033 /* If TBI compatibility is was previously off, turn it on. For
3034 * compatibility with a TBI link partner, we will store bad
3035 * packets. Some frames have an additional byte on the end and
3036 * will look like CRC errors to to the hardware.
3038 if (!hw->tbi_compatibility_on) {
3039 hw->tbi_compatibility_on = TRUE;
3040 rctl = E1000_READ_REG(hw, RCTL);
3041 rctl |= E1000_RCTL_SBP;
3042 E1000_WRITE_REG(hw, RCTL, rctl);
3047 /* If we don't have link (auto-negotiation failed or link partner cannot
3048 * auto-negotiate), the cable is plugged in (we have signal), and our
3049 * link partner is not trying to auto-negotiate with us (we are receiving
3050 * idles or data), we need to force link up. We also need to give
3051 * auto-negotiation time to complete, in case the cable was just plugged
3052 * in. The autoneg_failed flag does this.
3054 else if ((((hw->media_type == em_media_type_fiber) &&
3055 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
3056 (hw->media_type == em_media_type_internal_serdes)) &&
3057 (!(status & E1000_STATUS_LU)) &&
3058 (!(rxcw & E1000_RXCW_C))) {
3059 if (hw->autoneg_failed == 0) {
3060 hw->autoneg_failed = 1;
3063 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
3065 /* Disable auto-negotiation in the TXCW register */
3066 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3068 /* Force link-up and also force full-duplex. */
3069 ctrl = E1000_READ_REG(hw, CTRL);
3070 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3071 E1000_WRITE_REG(hw, CTRL, ctrl);
3073 /* Configure Flow Control after forcing link up. */
3074 ret_val = em_config_fc_after_link_up(hw);
3076 DEBUGOUT("Error configuring flow control\n");
3080 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3081 * auto-negotiation in the TXCW register and disable forced link in the
3082 * Device Control register in an attempt to auto-negotiate with our link
3085 else if (((hw->media_type == em_media_type_fiber) ||
3086 (hw->media_type == em_media_type_internal_serdes)) &&
3087 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3088 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
3089 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3090 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3092 hw->serdes_link_down = FALSE;
3094 /* If we force link for non-auto-negotiation switch, check link status
3095 * based on MAC synchronization for internal serdes media type.
3097 else if ((hw->media_type == em_media_type_internal_serdes) &&
3098 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
3099 /* SYNCH bit and IV bit are sticky. */
3101 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
3102 if (!(rxcw & E1000_RXCW_IV)) {
3103 hw->serdes_link_down = FALSE;
3104 DEBUGOUT("SERDES: Link is up.\n");
3107 hw->serdes_link_down = TRUE;
3108 DEBUGOUT("SERDES: Link is down.\n");
3111 if ((hw->media_type == em_media_type_internal_serdes) &&
3112 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
3113 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
3115 return E1000_SUCCESS;
3118 /******************************************************************************
3119 * Detects the current speed and duplex settings of the hardware.
3121 * hw - Struct containing variables accessed by shared code
3122 * speed - Speed of the connection
3123 * duplex - Duplex setting of the connection
3124 *****************************************************************************/
3126 em_get_speed_and_duplex(struct em_hw *hw,
3134 DEBUGFUNC("em_get_speed_and_duplex");
3136 if (hw->mac_type >= em_82543) {
3137 status = E1000_READ_REG(hw, STATUS);
3138 if (status & E1000_STATUS_SPEED_1000) {
3139 *speed = SPEED_1000;
3140 DEBUGOUT("1000 Mbs, ");
3141 } else if (status & E1000_STATUS_SPEED_100) {
3143 DEBUGOUT("100 Mbs, ");
3146 DEBUGOUT("10 Mbs, ");
3149 if (status & E1000_STATUS_FD) {
3150 *duplex = FULL_DUPLEX;
3151 DEBUGOUT("Full Duplex\n");
3153 *duplex = HALF_DUPLEX;
3154 DEBUGOUT(" Half Duplex\n");
3157 DEBUGOUT("1000 Mbs, Full Duplex\n");
3158 *speed = SPEED_1000;
3159 *duplex = FULL_DUPLEX;
3162 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
3163 * if it is operating at half duplex. Here we set the duplex settings to
3164 * match the duplex in the link partner's capabilities.
3166 if (hw->phy_type == em_phy_igp && hw->speed_downgraded) {
3167 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3171 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3172 *duplex = HALF_DUPLEX;
3174 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
3177 if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
3178 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3179 *duplex = HALF_DUPLEX;
3183 if ((hw->mac_type == em_80003es2lan) &&
3184 (hw->media_type == em_media_type_copper)) {
3185 if (*speed == SPEED_1000)
3186 ret_val = em_configure_kmrn_for_1000(hw);
3188 ret_val = em_configure_kmrn_for_10_100(hw, *duplex);
3193 if ((hw->phy_type == em_phy_igp_3) && (*speed == SPEED_1000)) {
3194 ret_val = em_kumeran_lock_loss_workaround(hw);
3199 return E1000_SUCCESS;
3202 /******************************************************************************
3203 * Blocks until autoneg completes or times out (~4.5 seconds)
3205 * hw - Struct containing variables accessed by shared code
3206 ******************************************************************************/
3208 em_wait_autoneg(struct em_hw *hw)
3214 DEBUGFUNC("em_wait_autoneg");
3215 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3217 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
3218 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
3219 /* Read the MII Status Register and wait for Auto-Neg
3220 * Complete bit to be set.
3222 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
3225 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
3228 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
3229 return E1000_SUCCESS;
3233 return E1000_SUCCESS;
3236 /******************************************************************************
3237 * Raises the Management Data Clock
3239 * hw - Struct containing variables accessed by shared code
3240 * ctrl - Device control register's current value
3241 ******************************************************************************/
3243 em_raise_mdi_clk(struct em_hw *hw,
3246 /* Raise the clock input to the Management Data Clock (by setting the MDC
3247 * bit), and then delay 10 microseconds.
3249 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
3250 E1000_WRITE_FLUSH(hw);
3254 /******************************************************************************
3255 * Lowers the Management Data Clock
3257 * hw - Struct containing variables accessed by shared code
3258 * ctrl - Device control register's current value
3259 ******************************************************************************/
3261 em_lower_mdi_clk(struct em_hw *hw,
3264 /* Lower the clock input to the Management Data Clock (by clearing the MDC
3265 * bit), and then delay 10 microseconds.
3267 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
3268 E1000_WRITE_FLUSH(hw);
3272 /******************************************************************************
3273 * Shifts data bits out to the PHY
3275 * hw - Struct containing variables accessed by shared code
3276 * data - Data to send out to the PHY
3277 * count - Number of bits to shift out
3279 * Bits are shifted out in MSB to LSB order.
3280 ******************************************************************************/
3282 em_shift_out_mdi_bits(struct em_hw *hw,
3289 /* We need to shift "count" number of bits out to the PHY. So, the value
3290 * in the "data" parameter will be shifted out to the PHY one bit at a
3291 * time. In order to do this, "data" must be broken down into bits.
3294 mask <<= (count - 1);
3296 ctrl = E1000_READ_REG(hw, CTRL);
3298 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3299 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
3302 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
3303 * then raising and lowering the Management Data Clock. A "0" is
3304 * shifted out to the PHY by setting the MDIO bit to "0" and then
3305 * raising and lowering the clock.
3308 ctrl |= E1000_CTRL_MDIO;
3310 ctrl &= ~E1000_CTRL_MDIO;
3312 E1000_WRITE_REG(hw, CTRL, ctrl);
3313 E1000_WRITE_FLUSH(hw);
3317 em_raise_mdi_clk(hw, &ctrl);
3318 em_lower_mdi_clk(hw, &ctrl);
3324 /******************************************************************************
3325 * Shifts data bits in from the PHY
3327 * hw - Struct containing variables accessed by shared code
3329 * Bits are shifted in in MSB to LSB order.
3330 ******************************************************************************/
3332 em_shift_in_mdi_bits(struct em_hw *hw)
3338 /* In order to read a register from the PHY, we need to shift in a total
3339 * of 18 bits from the PHY. The first two bit (turnaround) times are used
3340 * to avoid contention on the MDIO pin when a read operation is performed.
3341 * These two bits are ignored by us and thrown away. Bits are "shifted in"
3342 * by raising the input to the Management Data Clock (setting the MDC bit),
3343 * and then reading the value of the MDIO bit.
3345 ctrl = E1000_READ_REG(hw, CTRL);
3347 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
3348 ctrl &= ~E1000_CTRL_MDIO_DIR;
3349 ctrl &= ~E1000_CTRL_MDIO;
3351 E1000_WRITE_REG(hw, CTRL, ctrl);
3352 E1000_WRITE_FLUSH(hw);
3354 /* Raise and Lower the clock before reading in the data. This accounts for
3355 * the turnaround bits. The first clock occurred when we clocked out the
3356 * last bit of the Register Address.
3358 em_raise_mdi_clk(hw, &ctrl);
3359 em_lower_mdi_clk(hw, &ctrl);
3361 for (data = 0, i = 0; i < 16; i++) {
3363 em_raise_mdi_clk(hw, &ctrl);
3364 ctrl = E1000_READ_REG(hw, CTRL);
3365 /* Check to see if we shifted in a "1". */
3366 if (ctrl & E1000_CTRL_MDIO)
3368 em_lower_mdi_clk(hw, &ctrl);
3371 em_raise_mdi_clk(hw, &ctrl);
3372 em_lower_mdi_clk(hw, &ctrl);
3378 em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask)
3380 uint32_t swfw_sync = 0;
3381 uint32_t swmask = mask;
3382 uint32_t fwmask = mask << 16;
3383 int32_t timeout = 200;
3385 DEBUGFUNC("em_swfw_sync_acquire");
3387 if (hw->swfwhw_semaphore_present)
3388 return em_get_software_flag(hw);
3390 if (!hw->swfw_sync_present)
3391 return em_get_hw_eeprom_semaphore(hw);
3394 if (em_get_hw_eeprom_semaphore(hw))
3395 return -E1000_ERR_SWFW_SYNC;
3397 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3398 if (!(swfw_sync & (fwmask | swmask))) {
3402 /* firmware currently using resource (fwmask) */
3403 /* or other software thread currently using resource (swmask) */
3404 em_put_hw_eeprom_semaphore(hw);
3410 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
3411 return -E1000_ERR_SWFW_SYNC;
3414 swfw_sync |= swmask;
3415 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3417 em_put_hw_eeprom_semaphore(hw);
3418 return E1000_SUCCESS;
3422 em_swfw_sync_release(struct em_hw *hw, uint16_t mask)
3425 uint32_t swmask = mask;
3427 DEBUGFUNC("em_swfw_sync_release");
3429 if (hw->swfwhw_semaphore_present) {
3430 em_release_software_flag(hw);
3434 if (!hw->swfw_sync_present) {
3435 em_put_hw_eeprom_semaphore(hw);
3439 /* if (em_get_hw_eeprom_semaphore(hw))
3440 * return -E1000_ERR_SWFW_SYNC; */
3441 while (em_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
3444 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3445 swfw_sync &= ~swmask;
3446 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3448 em_put_hw_eeprom_semaphore(hw);
3451 /*****************************************************************************
3452 * Reads the value from a PHY register, if the value is on a specific non zero
3453 * page, sets the page first.
3454 * hw - Struct containing variables accessed by shared code
3455 * reg_addr - address of the PHY register to read
3456 ******************************************************************************/
3458 em_read_phy_reg(struct em_hw *hw,
3465 DEBUGFUNC("em_read_phy_reg");
3467 if ((hw->mac_type == em_80003es2lan) &&
3468 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3469 swfw = E1000_SWFW_PHY1_SM;
3471 swfw = E1000_SWFW_PHY0_SM;
3473 if (em_swfw_sync_acquire(hw, swfw))
3474 return -E1000_ERR_SWFW_SYNC;
3476 if ((hw->phy_type == em_phy_igp ||
3477 hw->phy_type == em_phy_igp_3 ||
3478 hw->phy_type == em_phy_igp_2) &&
3479 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3480 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3481 (uint16_t)reg_addr);
3483 em_swfw_sync_release(hw, swfw);
3486 } else if (hw->phy_type == em_phy_gg82563) {
3487 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3488 (hw->mac_type == em_80003es2lan)) {
3489 /* Select Configuration Page */
3490 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3491 ret_val = em_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3492 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3494 /* Use Alternative Page Select register to access
3495 * registers 30 and 31
3497 ret_val = em_write_phy_reg_ex(hw,
3498 GG82563_PHY_PAGE_SELECT_ALT,
3499 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3503 em_swfw_sync_release(hw, swfw);
3509 ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3512 em_swfw_sync_release(hw, swfw);
3517 em_read_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr,
3522 const uint32_t phy_addr = 1;
3524 DEBUGFUNC("em_read_phy_reg_ex");
3526 if (reg_addr > MAX_PHY_REG_ADDRESS) {
3527 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3528 return -E1000_ERR_PARAM;
3531 if (hw->mac_type > em_82543) {
3532 /* Set up Op-code, Phy Address, and register address in the MDI
3533 * Control register. The MAC will take care of interfacing with the
3534 * PHY to retrieve the desired data.
3536 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
3537 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3538 (E1000_MDIC_OP_READ));
3540 E1000_WRITE_REG(hw, MDIC, mdic);
3542 /* Poll the ready bit to see if the MDI read completed */
3543 for (i = 0; i < 64; i++) {
3545 mdic = E1000_READ_REG(hw, MDIC);
3546 if (mdic & E1000_MDIC_READY) break;
3548 if (!(mdic & E1000_MDIC_READY)) {
3549 DEBUGOUT("MDI Read did not complete\n");
3550 return -E1000_ERR_PHY;
3552 if (mdic & E1000_MDIC_ERROR) {
3553 DEBUGOUT("MDI Error\n");
3554 return -E1000_ERR_PHY;
3556 *phy_data = (uint16_t) mdic;
3558 /* We must first send a preamble through the MDIO pin to signal the
3559 * beginning of an MII instruction. This is done by sending 32
3560 * consecutive "1" bits.
3562 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3564 /* Now combine the next few fields that are required for a read
3565 * operation. We use this method instead of calling the
3566 * em_shift_out_mdi_bits routine five different times. The format of
3567 * a MII read instruction consists of a shift out of 14 bits and is
3568 * defined as follows:
3569 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
3570 * followed by a shift in of 18 bits. This first two bits shifted in
3571 * are TurnAround bits used to avoid contention on the MDIO pin when a
3572 * READ operation is performed. These two bits are thrown away
3573 * followed by a shift in of 16 bits which contains the desired data.
3575 mdic = ((reg_addr) | (phy_addr << 5) |
3576 (PHY_OP_READ << 10) | (PHY_SOF << 12));
3578 em_shift_out_mdi_bits(hw, mdic, 14);
3580 /* Now that we've shifted out the read command to the MII, we need to
3581 * "shift in" the 16-bit value (18 total bits) of the requested PHY
3584 *phy_data = em_shift_in_mdi_bits(hw);
3586 return E1000_SUCCESS;
3589 /******************************************************************************
3590 * Writes a value to a PHY register
3592 * hw - Struct containing variables accessed by shared code
3593 * reg_addr - address of the PHY register to write
3594 * data - data to write to the PHY
3595 ******************************************************************************/
3597 em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr,
3603 DEBUGFUNC("em_write_phy_reg");
3605 if ((hw->mac_type == em_80003es2lan) &&
3606 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3607 swfw = E1000_SWFW_PHY1_SM;
3609 swfw = E1000_SWFW_PHY0_SM;
3611 if (em_swfw_sync_acquire(hw, swfw))
3612 return -E1000_ERR_SWFW_SYNC;
3614 if ((hw->phy_type == em_phy_igp ||
3615 hw->phy_type == em_phy_igp_3 ||
3616 hw->phy_type == em_phy_igp_2) &&
3617 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3618 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3619 (uint16_t)reg_addr);
3621 em_swfw_sync_release(hw, swfw);
3624 } else if (hw->phy_type == em_phy_gg82563) {
3625 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3626 (hw->mac_type == em_80003es2lan)) {
3627 /* Select Configuration Page */
3628 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3629 ret_val = em_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3630 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3632 /* Use Alternative Page Select register to access
3633 * registers 30 and 31
3635 ret_val = em_write_phy_reg_ex(hw,
3636 GG82563_PHY_PAGE_SELECT_ALT,
3637 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3641 em_swfw_sync_release(hw, swfw);
3647 ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3650 em_swfw_sync_release(hw, swfw);
3655 em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr,
3660 const uint32_t phy_addr = 1;
3662 DEBUGFUNC("em_write_phy_reg_ex");
3664 if (reg_addr > MAX_PHY_REG_ADDRESS) {
3665 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3666 return -E1000_ERR_PARAM;
3669 if (hw->mac_type > em_82543) {
3670 /* Set up Op-code, Phy Address, register address, and data intended
3671 * for the PHY register in the MDI Control register. The MAC will take
3672 * care of interfacing with the PHY to send the desired data.
3674 mdic = (((uint32_t) phy_data) |
3675 (reg_addr << E1000_MDIC_REG_SHIFT) |
3676 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3677 (E1000_MDIC_OP_WRITE));
3679 E1000_WRITE_REG(hw, MDIC, mdic);
3681 /* Poll the ready bit to see if the MDI read completed */
3682 for (i = 0; i < 641; i++) {
3684 mdic = E1000_READ_REG(hw, MDIC);
3685 if (mdic & E1000_MDIC_READY) break;
3687 if (!(mdic & E1000_MDIC_READY)) {
3688 DEBUGOUT("MDI Write did not complete\n");
3689 return -E1000_ERR_PHY;
3692 /* We'll need to use the SW defined pins to shift the write command
3693 * out to the PHY. We first send a preamble to the PHY to signal the
3694 * beginning of the MII instruction. This is done by sending 32
3695 * consecutive "1" bits.
3697 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3699 /* Now combine the remaining required fields that will indicate a
3700 * write operation. We use this method instead of calling the
3701 * em_shift_out_mdi_bits routine for each field in the command. The
3702 * format of a MII write instruction is as follows:
3703 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
3705 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3706 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3708 mdic |= (uint32_t) phy_data;
3710 em_shift_out_mdi_bits(hw, mdic, 32);
3713 return E1000_SUCCESS;
3717 em_read_kmrn_reg(struct em_hw *hw,
3723 DEBUGFUNC("em_read_kmrn_reg");
3725 if ((hw->mac_type == em_80003es2lan) &&
3726 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3727 swfw = E1000_SWFW_PHY1_SM;
3729 swfw = E1000_SWFW_PHY0_SM;
3731 if (em_swfw_sync_acquire(hw, swfw))
3732 return -E1000_ERR_SWFW_SYNC;
3734 /* Write register address */
3735 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3736 E1000_KUMCTRLSTA_OFFSET) |
3737 E1000_KUMCTRLSTA_REN;
3738 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3741 /* Read the data returned */
3742 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
3743 *data = (uint16_t)reg_val;
3745 em_swfw_sync_release(hw, swfw);
3746 return E1000_SUCCESS;
3750 em_write_kmrn_reg(struct em_hw *hw,
3756 DEBUGFUNC("em_write_kmrn_reg");
3758 if ((hw->mac_type == em_80003es2lan) &&
3759 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3760 swfw = E1000_SWFW_PHY1_SM;
3762 swfw = E1000_SWFW_PHY0_SM;
3764 if (em_swfw_sync_acquire(hw, swfw))
3765 return -E1000_ERR_SWFW_SYNC;
3767 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3768 E1000_KUMCTRLSTA_OFFSET) | data;
3769 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3772 em_swfw_sync_release(hw, swfw);
3773 return E1000_SUCCESS;
3776 /******************************************************************************
3777 * Returns the PHY to the power-on reset state
3779 * hw - Struct containing variables accessed by shared code
3780 ******************************************************************************/
3782 em_phy_hw_reset(struct em_hw *hw)
3784 uint32_t ctrl, ctrl_ext;
3789 DEBUGFUNC("em_phy_hw_reset");
3791 /* In the case of the phy reset being blocked, it's not an error, we
3792 * simply return success without performing the reset. */
3793 ret_val = em_check_phy_reset_block(hw);
3795 return E1000_SUCCESS;
3797 DEBUGOUT("Resetting Phy...\n");
3799 if (hw->mac_type > em_82543) {
3800 if ((hw->mac_type == em_80003es2lan) &&
3801 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3802 swfw = E1000_SWFW_PHY1_SM;
3804 swfw = E1000_SWFW_PHY0_SM;
3806 if (em_swfw_sync_acquire(hw, swfw)) {
3807 DEBUGOUT("Unable to acquire swfw sync\n");
3808 return -E1000_ERR_SWFW_SYNC;
3810 /* Read the device control register and assert the E1000_CTRL_PHY_RST
3811 * bit. Then, take it out of reset.
3812 * For pre-em_82571 hardware, we delay for 10ms between the assert
3813 * and deassert. For em_82571 hardware and later, we instead delay
3814 * for 50us between and 10ms after the deassertion.
3816 ctrl = E1000_READ_REG(hw, CTRL);
3817 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
3818 E1000_WRITE_FLUSH(hw);
3820 if (hw->mac_type < em_82571)
3825 E1000_WRITE_REG(hw, CTRL, ctrl);
3826 E1000_WRITE_FLUSH(hw);
3828 if (hw->mac_type >= em_82571)
3831 em_swfw_sync_release(hw, swfw);
3833 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3834 * bit to put the PHY into reset. Then, take it out of reset.
3836 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
3837 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3838 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3839 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3840 E1000_WRITE_FLUSH(hw);
3842 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3843 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3844 E1000_WRITE_FLUSH(hw);
3848 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
3849 /* Configure activity LED after PHY reset */
3850 led_ctrl = E1000_READ_REG(hw, LEDCTL);
3851 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3852 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3853 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
3856 /* Wait for FW to finish PHY configuration. */
3857 ret_val = em_get_phy_cfg_done(hw);
3858 if (ret_val != E1000_SUCCESS)
3860 em_release_software_semaphore(hw);
3862 if ((hw->mac_type == em_ich8lan) && (hw->phy_type == em_phy_igp_3))
3863 ret_val = em_init_lcd_from_nvm(hw);
3868 /******************************************************************************
3871 * hw - Struct containing variables accessed by shared code
3873 * Sets bit 15 of the MII Control regiser
3874 ******************************************************************************/
3876 em_phy_reset(struct em_hw *hw)
3881 DEBUGFUNC("em_phy_reset");
3883 /* In the case of the phy reset being blocked, it's not an error, we
3884 * simply return success without performing the reset. */
3885 ret_val = em_check_phy_reset_block(hw);
3887 return E1000_SUCCESS;
3889 switch (hw->phy_type) {
3894 ret_val = em_phy_hw_reset(hw);
3899 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data);
3903 phy_data |= MII_CR_RESET;
3904 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data);
3912 if (hw->phy_type == em_phy_igp || hw->phy_type == em_phy_igp_2)
3913 em_phy_init_script(hw);
3915 return E1000_SUCCESS;
3918 /******************************************************************************
3919 * Work-around for 82566 power-down: on D3 entry-
3920 * 1) disable gigabit link
3921 * 2) write VR power-down enable
3923 * if successful continue, else issue LCD reset and repeat
3925 * hw - struct containing variables accessed by shared code
3926 ******************************************************************************/
3928 em_phy_powerdown_workaround(struct em_hw *hw)
3934 DEBUGFUNC("em_phy_powerdown_workaround");
3936 if (hw->phy_type != em_phy_igp_3)
3941 reg = E1000_READ_REG(hw, PHY_CTRL);
3942 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3943 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3945 /* Write VR power-down enable - bits 9:8 should be 10b */
3946 em_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3947 phy_data |= (1 << 9);
3948 phy_data &= ~(1 << 8);
3949 em_write_phy_reg(hw, IGP3_VR_CTRL, phy_data);
3951 /* Read it back and test */
3952 em_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3953 if (((phy_data & IGP3_VR_CTRL_MODE_MASK) == IGP3_VR_CTRL_MODE_SHUT) || retry)
3956 /* Issue PHY reset and repeat at most one more time */
3957 reg = E1000_READ_REG(hw, CTRL);
3958 E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST);
3966 /******************************************************************************
3967 * Work-around for 82566 Kumeran PCS lock loss:
3968 * On link status change (i.e. PCI reset, speed change) and link is up and
3970 * 0) if workaround is optionally disabled do nothing
3971 * 1) wait 1ms for Kumeran link to come up
3972 * 2) check Kumeran Diagnostic register PCS lock loss bit
3973 * 3) if not set the link is locked (all is good), otherwise...
3975 * 5) repeat up to 10 times
3976 * Note: this is only called for IGP3 copper when speed is 1gb.
3978 * hw - struct containing variables accessed by shared code
3979 ******************************************************************************/
3981 em_kumeran_lock_loss_workaround(struct em_hw *hw)
3988 if (hw->kmrn_lock_loss_workaround_disabled)
3989 return E1000_SUCCESS;
3991 /* Make sure link is up before proceeding. If not just return.
3992 * Attempting this while link is negotiating fouled up link
3994 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
3995 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
3997 if (phy_data & MII_SR_LINK_STATUS) {
3998 for (cnt = 0; cnt < 10; cnt++) {
3999 /* read once to clear */
4000 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
4003 /* and again to get new status */
4004 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
4008 /* check for PCS lock */
4009 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4010 return E1000_SUCCESS;
4012 /* Issue PHY reset */
4013 em_phy_hw_reset(hw);
4016 /* Disable GigE link negotiation */
4017 reg = E1000_READ_REG(hw, PHY_CTRL);
4018 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
4019 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4021 /* unable to acquire PCS lock */
4022 return E1000_ERR_PHY;
4025 return E1000_SUCCESS;
4028 /******************************************************************************
4029 * Probes the expected PHY address for known PHY IDs
4031 * hw - Struct containing variables accessed by shared code
4032 ******************************************************************************/
4034 em_detect_gig_phy(struct em_hw *hw)
4036 int32_t phy_init_status, ret_val;
4037 uint16_t phy_id_high, phy_id_low;
4038 boolean_t match = FALSE;
4040 DEBUGFUNC("em_detect_gig_phy");
4042 if (hw->phy_id != 0)
4043 return E1000_SUCCESS;
4045 /* The 82571 firmware may still be configuring the PHY. In this
4046 * case, we cannot access the PHY until the configuration is done. So
4047 * we explicitly set the PHY values. */
4048 if (hw->mac_type == em_82571 ||
4049 hw->mac_type == em_82572) {
4050 hw->phy_id = IGP01E1000_I_PHY_ID;
4051 hw->phy_type = em_phy_igp_2;
4052 return E1000_SUCCESS;
4055 /* ESB-2 PHY reads require em_phy_gg82563 to be set because of a work-
4056 * around that forces PHY page 0 to be set or the reads fail. The rest of
4057 * the code in this routine uses em_read_phy_reg to read the PHY ID.
4058 * So for ESB-2 we need to have this set so our reads won't fail. If the
4059 * attached PHY is not a em_phy_gg82563, the routines below will figure
4060 * this out as well. */
4061 if (hw->mac_type == em_80003es2lan)
4062 hw->phy_type = em_phy_gg82563;
4064 /* Read the PHY ID Registers to identify which PHY is onboard. */
4065 ret_val = em_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4069 hw->phy_id = (uint32_t) (phy_id_high << 16);
4071 ret_val = em_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4075 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4076 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4078 switch (hw->mac_type) {
4080 if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
4083 if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
4087 case em_82545_rev_3:
4089 case em_82546_rev_3:
4090 if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
4093 case em_82541_rev_2:
4095 case em_82547_rev_2:
4096 if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
4099 if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
4101 case em_80003es2lan:
4102 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
4105 if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE;
4106 if (hw->phy_id == IFE_E_PHY_ID) match = TRUE;
4107 if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
4108 if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
4111 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
4112 return -E1000_ERR_CONFIG;
4114 phy_init_status = em_set_phy_type(hw);
4116 if ((match) && (phy_init_status == E1000_SUCCESS)) {
4117 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
4118 return E1000_SUCCESS;
4120 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
4121 return -E1000_ERR_PHY;
4124 /******************************************************************************
4125 * Resets the PHY's DSP
4127 * hw - Struct containing variables accessed by shared code
4128 ******************************************************************************/
4130 em_phy_reset_dsp(struct em_hw *hw)
4133 DEBUGFUNC("em_phy_reset_dsp");
4136 if (hw->phy_type != em_phy_gg82563) {
4137 ret_val = em_write_phy_reg(hw, 29, 0x001d);
4140 ret_val = em_write_phy_reg(hw, 30, 0x00c1);
4142 ret_val = em_write_phy_reg(hw, 30, 0x0000);
4144 ret_val = E1000_SUCCESS;
4150 /******************************************************************************
4151 * Get PHY information from various PHY registers for igp PHY only.
4153 * hw - Struct containing variables accessed by shared code
4154 * phy_info - PHY information structure
4155 ******************************************************************************/
4157 em_phy_igp_get_info(struct em_hw *hw,
4158 struct em_phy_info *phy_info)
4161 uint16_t phy_data, min_length, max_length, average;
4162 em_rev_polarity polarity;
4164 DEBUGFUNC("em_phy_igp_get_info");
4166 /* The downshift status is checked only once, after link is established,
4167 * and it stored in the hw->speed_downgraded parameter. */
4168 phy_info->downshift = (em_downshift)hw->speed_downgraded;
4170 /* IGP01E1000 does not need to support it. */
4171 phy_info->extended_10bt_distance = em_10bt_ext_dist_enable_normal;
4173 /* IGP01E1000 always correct polarity reversal */
4174 phy_info->polarity_correction = em_polarity_reversal_enabled;
4176 /* Check polarity status */
4177 ret_val = em_check_polarity(hw, &polarity);
4181 phy_info->cable_polarity = polarity;
4183 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
4187 phy_info->mdix_mode = (em_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >>
4188 IGP01E1000_PSSR_MDIX_SHIFT);
4190 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
4191 IGP01E1000_PSSR_SPEED_1000MBPS) {
4192 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
4193 ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4197 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4198 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4199 em_1000t_rx_status_ok : em_1000t_rx_status_not_ok;
4200 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4201 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4202 em_1000t_rx_status_ok : em_1000t_rx_status_not_ok;
4204 /* Get cable length */
4205 ret_val = em_get_cable_length(hw, &min_length, &max_length);
4209 /* Translate to old method */
4210 average = (max_length + min_length) / 2;
4212 if (average <= em_igp_cable_length_50)
4213 phy_info->cable_length = em_cable_length_50;
4214 else if (average <= em_igp_cable_length_80)
4215 phy_info->cable_length = em_cable_length_50_80;
4216 else if (average <= em_igp_cable_length_110)
4217 phy_info->cable_length = em_cable_length_80_110;
4218 else if (average <= em_igp_cable_length_140)
4219 phy_info->cable_length = em_cable_length_110_140;
4221 phy_info->cable_length = em_cable_length_140;
4224 return E1000_SUCCESS;
4227 /******************************************************************************
4228 * Get PHY information from various PHY registers for ife PHY only.
4230 * hw - Struct containing variables accessed by shared code
4231 * phy_info - PHY information structure
4232 ******************************************************************************/
4234 em_phy_ife_get_info(struct em_hw *hw,
4235 struct em_phy_info *phy_info)
4239 em_rev_polarity polarity;
4241 DEBUGFUNC("em_phy_ife_get_info");
4243 phy_info->downshift = (em_downshift)hw->speed_downgraded;
4244 phy_info->extended_10bt_distance = em_10bt_ext_dist_enable_normal;
4246 ret_val = em_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
4249 phy_info->polarity_correction =
4250 ((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
4251 IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ?
4252 em_polarity_reversal_disabled : em_polarity_reversal_enabled;
4254 if (phy_info->polarity_correction == em_polarity_reversal_enabled) {
4255 ret_val = em_check_polarity(hw, &polarity);
4259 /* Polarity is forced. */
4260 polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >>
4261 IFE_PSC_FORCE_POLARITY_SHIFT) ?
4262 em_rev_polarity_reversed : em_rev_polarity_normal;
4264 phy_info->cable_polarity = polarity;
4266 ret_val = em_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
4270 phy_info->mdix_mode = (em_auto_x_mode)
4271 ((phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >>
4272 IFE_PMC_MDIX_MODE_SHIFT);
4274 return E1000_SUCCESS;
4277 /******************************************************************************
4278 * Get PHY information from various PHY registers fot m88 PHY only.
4280 * hw - Struct containing variables accessed by shared code
4281 * phy_info - PHY information structure
4282 ******************************************************************************/
4284 em_phy_m88_get_info(struct em_hw *hw,
4285 struct em_phy_info *phy_info)
4289 em_rev_polarity polarity;
4291 DEBUGFUNC("em_phy_m88_get_info");
4293 /* The downshift status is checked only once, after link is established,
4294 * and it stored in the hw->speed_downgraded parameter. */
4295 phy_info->downshift = (em_downshift)hw->speed_downgraded;
4297 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
4301 phy_info->extended_10bt_distance =
4302 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
4303 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
4304 em_10bt_ext_dist_enable_lower : em_10bt_ext_dist_enable_normal;
4306 phy_info->polarity_correction =
4307 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
4308 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
4309 em_polarity_reversal_disabled : em_polarity_reversal_enabled;
4311 /* Check polarity status */
4312 ret_val = em_check_polarity(hw, &polarity);
4315 phy_info->cable_polarity = polarity;
4317 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
4321 phy_info->mdix_mode = (em_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >>
4322 M88E1000_PSSR_MDIX_SHIFT);
4324 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
4325 /* Cable Length Estimation and Local/Remote Receiver Information
4326 * are only valid at 1000 Mbps.
4328 if (hw->phy_type != em_phy_gg82563) {
4329 phy_info->cable_length = (em_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4330 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
4332 ret_val = em_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
4337 phy_info->cable_length = (em_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH);
4340 ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4344 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4345 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4346 em_1000t_rx_status_ok : em_1000t_rx_status_not_ok;
4347 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4348 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4349 em_1000t_rx_status_ok : em_1000t_rx_status_not_ok;
4353 return E1000_SUCCESS;
4356 /******************************************************************************
4357 * Get PHY information from various PHY registers
4359 * hw - Struct containing variables accessed by shared code
4360 * phy_info - PHY information structure
4361 ******************************************************************************/
4363 em_phy_get_info(struct em_hw *hw,
4364 struct em_phy_info *phy_info)
4369 DEBUGFUNC("em_phy_get_info");
4371 phy_info->cable_length = em_cable_length_undefined;
4372 phy_info->extended_10bt_distance = em_10bt_ext_dist_enable_undefined;
4373 phy_info->cable_polarity = em_rev_polarity_undefined;
4374 phy_info->downshift = em_downshift_undefined;
4375 phy_info->polarity_correction = em_polarity_reversal_undefined;
4376 phy_info->mdix_mode = em_auto_x_mode_undefined;
4377 phy_info->local_rx = em_1000t_rx_status_undefined;
4378 phy_info->remote_rx = em_1000t_rx_status_undefined;
4380 if (hw->media_type != em_media_type_copper) {
4381 DEBUGOUT("PHY info is only valid for copper media\n");
4382 return -E1000_ERR_CONFIG;
4385 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
4389 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
4393 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
4394 DEBUGOUT("PHY info is only valid if link is up\n");
4395 return -E1000_ERR_CONFIG;
4398 if (hw->phy_type == em_phy_igp ||
4399 hw->phy_type == em_phy_igp_3 ||
4400 hw->phy_type == em_phy_igp_2)
4401 return em_phy_igp_get_info(hw, phy_info);
4402 else if (hw->phy_type == em_phy_ife)
4403 return em_phy_ife_get_info(hw, phy_info);
4405 return em_phy_m88_get_info(hw, phy_info);
4409 em_validate_mdi_setting(struct em_hw *hw)
4411 DEBUGFUNC("em_validate_mdi_settings");
4413 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
4414 DEBUGOUT("Invalid MDI setting detected\n");
4416 return -E1000_ERR_CONFIG;
4418 return E1000_SUCCESS;
4422 /******************************************************************************
4423 * Sets up eeprom variables in the hw struct. Must be called after mac_type
4424 * is configured. Additionally, if this is ICH8, the flash controller GbE
4425 * registers must be mapped, or this will crash.
4427 * hw - Struct containing variables accessed by shared code
4428 *****************************************************************************/
4430 em_init_eeprom_params(struct em_hw *hw)
4432 struct em_eeprom_info *eeprom = &hw->eeprom;
4433 uint32_t eecd = E1000_READ_REG(hw, EECD);
4434 int32_t ret_val = E1000_SUCCESS;
4435 uint16_t eeprom_size;
4437 DEBUGFUNC("em_init_eeprom_params");
4439 switch (hw->mac_type) {
4440 case em_82542_rev2_0:
4441 case em_82542_rev2_1:
4444 eeprom->type = em_eeprom_microwire;
4445 eeprom->word_size = 64;
4446 eeprom->opcode_bits = 3;
4447 eeprom->address_bits = 6;
4448 eeprom->delay_usec = 50;
4449 eeprom->use_eerd = FALSE;
4450 eeprom->use_eewr = FALSE;
4454 case em_82545_rev_3:
4456 case em_82546_rev_3:
4457 eeprom->type = em_eeprom_microwire;
4458 eeprom->opcode_bits = 3;
4459 eeprom->delay_usec = 50;
4460 if (eecd & E1000_EECD_SIZE) {
4461 eeprom->word_size = 256;
4462 eeprom->address_bits = 8;
4464 eeprom->word_size = 64;
4465 eeprom->address_bits = 6;
4467 eeprom->use_eerd = FALSE;
4468 eeprom->use_eewr = FALSE;
4471 case em_82541_rev_2:
4473 case em_82547_rev_2:
4474 if (eecd & E1000_EECD_TYPE) {
4475 eeprom->type = em_eeprom_spi;
4476 eeprom->opcode_bits = 8;
4477 eeprom->delay_usec = 1;
4478 if (eecd & E1000_EECD_ADDR_BITS) {
4479 eeprom->page_size = 32;
4480 eeprom->address_bits = 16;
4482 eeprom->page_size = 8;
4483 eeprom->address_bits = 8;
4486 eeprom->type = em_eeprom_microwire;
4487 eeprom->opcode_bits = 3;
4488 eeprom->delay_usec = 50;
4489 if (eecd & E1000_EECD_ADDR_BITS) {
4490 eeprom->word_size = 256;
4491 eeprom->address_bits = 8;
4493 eeprom->word_size = 64;
4494 eeprom->address_bits = 6;
4497 eeprom->use_eerd = FALSE;
4498 eeprom->use_eewr = FALSE;
4502 eeprom->type = em_eeprom_spi;
4503 eeprom->opcode_bits = 8;
4504 eeprom->delay_usec = 1;
4505 if (eecd & E1000_EECD_ADDR_BITS) {
4506 eeprom->page_size = 32;
4507 eeprom->address_bits = 16;
4509 eeprom->page_size = 8;
4510 eeprom->address_bits = 8;
4512 eeprom->use_eerd = FALSE;
4513 eeprom->use_eewr = FALSE;
4516 eeprom->type = em_eeprom_spi;
4517 eeprom->opcode_bits = 8;
4518 eeprom->delay_usec = 1;
4519 if (eecd & E1000_EECD_ADDR_BITS) {
4520 eeprom->page_size = 32;
4521 eeprom->address_bits = 16;
4523 eeprom->page_size = 8;
4524 eeprom->address_bits = 8;
4526 eeprom->use_eerd = TRUE;
4527 eeprom->use_eewr = TRUE;
4528 if (em_is_onboard_nvm_eeprom(hw) == FALSE) {
4529 eeprom->type = em_eeprom_flash;
4530 eeprom->word_size = 2048;
4532 /* Ensure that the Autonomous FLASH update bit is cleared due to
4533 * Flash update issue on parts which use a FLASH for NVM. */
4534 eecd &= ~E1000_EECD_AUPDEN;
4535 E1000_WRITE_REG(hw, EECD, eecd);
4538 case em_80003es2lan:
4539 eeprom->type = em_eeprom_spi;
4540 eeprom->opcode_bits = 8;
4541 eeprom->delay_usec = 1;
4542 if (eecd & E1000_EECD_ADDR_BITS) {
4543 eeprom->page_size = 32;
4544 eeprom->address_bits = 16;
4546 eeprom->page_size = 8;
4547 eeprom->address_bits = 8;
4549 eeprom->use_eerd = TRUE;
4550 eeprom->use_eewr = FALSE;
4555 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG);
4557 eeprom->type = em_eeprom_ich8;
4558 eeprom->use_eerd = FALSE;
4559 eeprom->use_eewr = FALSE;
4560 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
4562 /* Zero the shadow RAM structure. But don't load it from NVM
4563 * so as to save time for driver init */
4564 if (hw->eeprom_shadow_ram != NULL) {
4565 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4566 hw->eeprom_shadow_ram[i].modified = FALSE;
4567 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
4571 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
4572 ICH_FLASH_SECTOR_SIZE;
4574 hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1;
4575 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
4577 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
4579 hw->flash_bank_size /= 2 * sizeof(uint16_t);
4587 if (eeprom->type == em_eeprom_spi) {
4588 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
4589 * 32KB (incremented by powers of 2).
4591 if (hw->mac_type <= em_82547_rev_2) {
4592 /* Set to default value for initial eeprom read. */
4593 eeprom->word_size = 64;
4594 ret_val = em_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
4597 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
4598 /* 256B eeprom size was not supported in earlier hardware, so we
4599 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
4600 * is never the result used in the shifting logic below. */
4604 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
4605 E1000_EECD_SIZE_EX_SHIFT);
4608 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
4613 /******************************************************************************
4614 * Raises the EEPROM's clock input.
4616 * hw - Struct containing variables accessed by shared code
4617 * eecd - EECD's current value
4618 *****************************************************************************/
4620 em_raise_ee_clk(struct em_hw *hw,
4623 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
4624 * wait <delay> microseconds.
4626 *eecd = *eecd | E1000_EECD_SK;
4627 E1000_WRITE_REG(hw, EECD, *eecd);
4628 E1000_WRITE_FLUSH(hw);
4629 usec_delay(hw->eeprom.delay_usec);
4632 /******************************************************************************
4633 * Lowers the EEPROM's clock input.
4635 * hw - Struct containing variables accessed by shared code
4636 * eecd - EECD's current value
4637 *****************************************************************************/
4639 em_lower_ee_clk(struct em_hw *hw,
4642 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
4643 * wait 50 microseconds.
4645 *eecd = *eecd & ~E1000_EECD_SK;
4646 E1000_WRITE_REG(hw, EECD, *eecd);
4647 E1000_WRITE_FLUSH(hw);
4648 usec_delay(hw->eeprom.delay_usec);
4651 /******************************************************************************
4652 * Shift data bits out to the EEPROM.
4654 * hw - Struct containing variables accessed by shared code
4655 * data - data to send to the EEPROM
4656 * count - number of bits to shift out
4657 *****************************************************************************/
4659 em_shift_out_ee_bits(struct em_hw *hw,
4663 struct em_eeprom_info *eeprom = &hw->eeprom;
4667 /* We need to shift "count" bits out to the EEPROM. So, value in the
4668 * "data" parameter will be shifted out to the EEPROM one bit at a time.
4669 * In order to do this, "data" must be broken down into bits.
4671 mask = 0x01 << (count - 1);
4672 eecd = E1000_READ_REG(hw, EECD);
4673 if (eeprom->type == em_eeprom_microwire) {
4674 eecd &= ~E1000_EECD_DO;
4675 } else if (eeprom->type == em_eeprom_spi) {
4676 eecd |= E1000_EECD_DO;
4679 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
4680 * and then raising and then lowering the clock (the SK bit controls
4681 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
4682 * by setting "DI" to "0" and then raising and then lowering the clock.
4684 eecd &= ~E1000_EECD_DI;
4687 eecd |= E1000_EECD_DI;
4689 E1000_WRITE_REG(hw, EECD, eecd);
4690 E1000_WRITE_FLUSH(hw);
4692 usec_delay(eeprom->delay_usec);
4694 em_raise_ee_clk(hw, &eecd);
4695 em_lower_ee_clk(hw, &eecd);
4701 /* We leave the "DI" bit set to "0" when we leave this routine. */
4702 eecd &= ~E1000_EECD_DI;
4703 E1000_WRITE_REG(hw, EECD, eecd);
4706 /******************************************************************************
4707 * Shift data bits in from the EEPROM
4709 * hw - Struct containing variables accessed by shared code
4710 *****************************************************************************/
4712 em_shift_in_ee_bits(struct em_hw *hw,
4719 /* In order to read a register from the EEPROM, we need to shift 'count'
4720 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
4721 * input to the EEPROM (setting the SK bit), and then reading the value of
4722 * the "DO" bit. During this "shifting in" process the "DI" bit should
4726 eecd = E1000_READ_REG(hw, EECD);
4728 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
4731 for (i = 0; i < count; i++) {
4733 em_raise_ee_clk(hw, &eecd);
4735 eecd = E1000_READ_REG(hw, EECD);
4737 eecd &= ~(E1000_EECD_DI);
4738 if (eecd & E1000_EECD_DO)
4741 em_lower_ee_clk(hw, &eecd);
4747 /******************************************************************************
4748 * Prepares EEPROM for access
4750 * hw - Struct containing variables accessed by shared code
4752 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
4753 * function should be called before issuing a command to the EEPROM.
4754 *****************************************************************************/
4756 em_acquire_eeprom(struct em_hw *hw)
4758 struct em_eeprom_info *eeprom = &hw->eeprom;
4761 DEBUGFUNC("em_acquire_eeprom");
4763 if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
4764 return -E1000_ERR_SWFW_SYNC;
4765 eecd = E1000_READ_REG(hw, EECD);
4767 if (hw->mac_type != em_82573) {
4768 /* Request EEPROM Access */
4769 if (hw->mac_type > em_82544) {
4770 eecd |= E1000_EECD_REQ;
4771 E1000_WRITE_REG(hw, EECD, eecd);
4772 eecd = E1000_READ_REG(hw, EECD);
4773 while ((!(eecd & E1000_EECD_GNT)) &&
4774 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
4777 eecd = E1000_READ_REG(hw, EECD);
4779 if (!(eecd & E1000_EECD_GNT)) {
4780 eecd &= ~E1000_EECD_REQ;
4781 E1000_WRITE_REG(hw, EECD, eecd);
4782 DEBUGOUT("Could not acquire EEPROM grant\n");
4783 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4784 return -E1000_ERR_EEPROM;
4789 /* Setup EEPROM for Read/Write */
4791 if (eeprom->type == em_eeprom_microwire) {
4792 /* Clear SK and DI */
4793 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
4794 E1000_WRITE_REG(hw, EECD, eecd);
4797 eecd |= E1000_EECD_CS;
4798 E1000_WRITE_REG(hw, EECD, eecd);
4799 } else if (eeprom->type == em_eeprom_spi) {
4800 /* Clear SK and CS */
4801 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4802 E1000_WRITE_REG(hw, EECD, eecd);
4806 return E1000_SUCCESS;
4809 /******************************************************************************
4810 * Returns EEPROM to a "standby" state
4812 * hw - Struct containing variables accessed by shared code
4813 *****************************************************************************/
4815 em_standby_eeprom(struct em_hw *hw)
4817 struct em_eeprom_info *eeprom = &hw->eeprom;
4820 eecd = E1000_READ_REG(hw, EECD);
4822 if (eeprom->type == em_eeprom_microwire) {
4823 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4824 E1000_WRITE_REG(hw, EECD, eecd);
4825 E1000_WRITE_FLUSH(hw);
4826 usec_delay(eeprom->delay_usec);
4829 eecd |= E1000_EECD_SK;
4830 E1000_WRITE_REG(hw, EECD, eecd);
4831 E1000_WRITE_FLUSH(hw);
4832 usec_delay(eeprom->delay_usec);
4835 eecd |= E1000_EECD_CS;
4836 E1000_WRITE_REG(hw, EECD, eecd);
4837 E1000_WRITE_FLUSH(hw);
4838 usec_delay(eeprom->delay_usec);
4841 eecd &= ~E1000_EECD_SK;
4842 E1000_WRITE_REG(hw, EECD, eecd);
4843 E1000_WRITE_FLUSH(hw);
4844 usec_delay(eeprom->delay_usec);
4845 } else if (eeprom->type == em_eeprom_spi) {
4846 /* Toggle CS to flush commands */
4847 eecd |= E1000_EECD_CS;
4848 E1000_WRITE_REG(hw, EECD, eecd);
4849 E1000_WRITE_FLUSH(hw);
4850 usec_delay(eeprom->delay_usec);
4851 eecd &= ~E1000_EECD_CS;
4852 E1000_WRITE_REG(hw, EECD, eecd);
4853 E1000_WRITE_FLUSH(hw);
4854 usec_delay(eeprom->delay_usec);
4858 /******************************************************************************
4859 * Terminates a command by inverting the EEPROM's chip select pin
4861 * hw - Struct containing variables accessed by shared code
4862 *****************************************************************************/
4864 em_release_eeprom(struct em_hw *hw)
4868 DEBUGFUNC("em_release_eeprom");
4870 eecd = E1000_READ_REG(hw, EECD);
4872 if (hw->eeprom.type == em_eeprom_spi) {
4873 eecd |= E1000_EECD_CS; /* Pull CS high */
4874 eecd &= ~E1000_EECD_SK; /* Lower SCK */
4876 E1000_WRITE_REG(hw, EECD, eecd);
4878 usec_delay(hw->eeprom.delay_usec);
4879 } else if (hw->eeprom.type == em_eeprom_microwire) {
4880 /* cleanup eeprom */
4882 /* CS on Microwire is active-high */
4883 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
4885 E1000_WRITE_REG(hw, EECD, eecd);
4887 /* Rising edge of clock */
4888 eecd |= E1000_EECD_SK;
4889 E1000_WRITE_REG(hw, EECD, eecd);
4890 E1000_WRITE_FLUSH(hw);
4891 usec_delay(hw->eeprom.delay_usec);
4893 /* Falling edge of clock */
4894 eecd &= ~E1000_EECD_SK;
4895 E1000_WRITE_REG(hw, EECD, eecd);
4896 E1000_WRITE_FLUSH(hw);
4897 usec_delay(hw->eeprom.delay_usec);
4900 /* Stop requesting EEPROM access */
4901 if (hw->mac_type > em_82544) {
4902 eecd &= ~E1000_EECD_REQ;
4903 E1000_WRITE_REG(hw, EECD, eecd);
4906 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4909 /******************************************************************************
4910 * Reads a 16 bit word from the EEPROM.
4912 * hw - Struct containing variables accessed by shared code
4913 *****************************************************************************/
4915 em_spi_eeprom_ready(struct em_hw *hw)
4917 uint16_t retry_count = 0;
4918 uint8_t spi_stat_reg;
4920 DEBUGFUNC("em_spi_eeprom_ready");
4922 /* Read "Status Register" repeatedly until the LSB is cleared. The
4923 * EEPROM will signal that the command has been completed by clearing
4924 * bit 0 of the internal status register. If it's not cleared within
4925 * 5 milliseconds, then error out.
4929 em_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
4930 hw->eeprom.opcode_bits);
4931 spi_stat_reg = (uint8_t)em_shift_in_ee_bits(hw, 8);
4932 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
4938 em_standby_eeprom(hw);
4939 } while (retry_count < EEPROM_MAX_RETRY_SPI);
4941 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
4942 * only 0-5mSec on 5V devices)
4944 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
4945 DEBUGOUT("SPI EEPROM Status error\n");
4946 return -E1000_ERR_EEPROM;
4949 return E1000_SUCCESS;
4952 /******************************************************************************
4953 * Reads a 16 bit word from the EEPROM.
4955 * hw - Struct containing variables accessed by shared code
4956 * offset - offset of word in the EEPROM to read
4957 * data - word read from the EEPROM
4958 * words - number of words to read
4959 *****************************************************************************/
4961 em_read_eeprom(struct em_hw *hw,
4966 struct em_eeprom_info *eeprom = &hw->eeprom;
4969 DEBUGFUNC("em_read_eeprom");
4971 /* If eeprom is not yet detected, do so now */
4972 if (eeprom->word_size == 0)
4973 em_init_eeprom_params(hw);
4975 /* A check for invalid values: offset too large, too many words, and not
4978 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
4980 DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size);
4981 return -E1000_ERR_EEPROM;
4984 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
4985 * directly. In this case, we need to acquire the EEPROM so that
4986 * FW or other port software does not interrupt.
4988 if (em_is_onboard_nvm_eeprom(hw) == TRUE &&
4989 hw->eeprom.use_eerd == FALSE) {
4990 /* Prepare the EEPROM for bit-bang reading */
4991 if (em_acquire_eeprom(hw) != E1000_SUCCESS)
4992 return -E1000_ERR_EEPROM;
4995 /* Eerd register EEPROM access requires no eeprom aquire/release */
4996 if (eeprom->use_eerd == TRUE)
4997 return em_read_eeprom_eerd(hw, offset, words, data);
4999 /* ICH EEPROM access is done via the ICH flash controller */
5000 if (eeprom->type == em_eeprom_ich8)
5001 return em_read_eeprom_ich8(hw, offset, words, data);
5003 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
5004 * acquired the EEPROM at this point, so any returns should relase it */
5005 if (eeprom->type == em_eeprom_spi) {
5007 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
5009 if (em_spi_eeprom_ready(hw)) {
5010 em_release_eeprom(hw);
5011 return -E1000_ERR_EEPROM;
5014 em_standby_eeprom(hw);
5016 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
5017 if ((eeprom->address_bits == 8) && (offset >= 128))
5018 read_opcode |= EEPROM_A8_OPCODE_SPI;
5020 /* Send the READ command (opcode + addr) */
5021 em_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
5022 em_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
5024 /* Read the data. The address of the eeprom internally increments with
5025 * each byte (spi) being read, saving on the overhead of eeprom setup
5026 * and tear-down. The address counter will roll over if reading beyond
5027 * the size of the eeprom, thus allowing the entire memory to be read
5028 * starting from any offset. */
5029 for (i = 0; i < words; i++) {
5030 word_in = em_shift_in_ee_bits(hw, 16);
5031 data[i] = (word_in >> 8) | (word_in << 8);
5033 } else if (eeprom->type == em_eeprom_microwire) {
5034 for (i = 0; i < words; i++) {
5035 /* Send the READ command (opcode + addr) */
5036 em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
5037 eeprom->opcode_bits);
5038 em_shift_out_ee_bits(hw, (uint16_t)(offset + i),
5039 eeprom->address_bits);
5041 /* Read the data. For microwire, each word requires the overhead
5042 * of eeprom setup and tear-down. */
5043 data[i] = em_shift_in_ee_bits(hw, 16);
5044 em_standby_eeprom(hw);
5048 /* End this read operation */
5049 em_release_eeprom(hw);
5051 return E1000_SUCCESS;
5054 /******************************************************************************
5055 * Reads a 16 bit word from the EEPROM using the EERD register.
5057 * hw - Struct containing variables accessed by shared code
5058 * offset - offset of word in the EEPROM to read
5059 * data - word read from the EEPROM
5060 * words - number of words to read
5061 *****************************************************************************/
5063 em_read_eeprom_eerd(struct em_hw *hw,
5068 uint32_t i, eerd = 0;
5071 for (i = 0; i < words; i++) {
5072 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
5073 E1000_EEPROM_RW_REG_START;
5075 E1000_WRITE_REG(hw, EERD, eerd);
5076 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
5081 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
5088 /******************************************************************************
5089 * Writes a 16 bit word from the EEPROM using the EEWR register.
5091 * hw - Struct containing variables accessed by shared code
5092 * offset - offset of word in the EEPROM to read
5093 * data - word read from the EEPROM
5094 * words - number of words to read
5095 *****************************************************************************/
5097 em_write_eeprom_eewr(struct em_hw *hw,
5102 uint32_t register_value = 0;
5106 if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
5107 return -E1000_ERR_SWFW_SYNC;
5109 for (i = 0; i < words; i++) {
5110 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
5111 ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
5112 E1000_EEPROM_RW_REG_START;
5114 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5119 E1000_WRITE_REG(hw, EEWR, register_value);
5121 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5128 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
5132 /******************************************************************************
5133 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
5135 * hw - Struct containing variables accessed by shared code
5136 *****************************************************************************/
5138 em_poll_eerd_eewr_done(struct em_hw *hw, int eerd)
5140 uint32_t attempts = 100000;
5141 uint32_t i, reg = 0;
5142 int32_t done = E1000_ERR_EEPROM;
5144 for (i = 0; i < attempts; i++) {
5145 if (eerd == E1000_EEPROM_POLL_READ)
5146 reg = E1000_READ_REG(hw, EERD);
5148 reg = E1000_READ_REG(hw, EEWR);
5150 if (reg & E1000_EEPROM_RW_REG_DONE) {
5151 done = E1000_SUCCESS;
5160 /***************************************************************************
5161 * Description: Determines if the onboard NVM is FLASH or EEPROM.
5163 * hw - Struct containing variables accessed by shared code
5164 ****************************************************************************/
5166 em_is_onboard_nvm_eeprom(struct em_hw *hw)
5170 DEBUGFUNC("em_is_onboard_nvm_eeprom");
5172 if (hw->mac_type == em_ich8lan)
5175 if (hw->mac_type == em_82573) {
5176 eecd = E1000_READ_REG(hw, EECD);
5178 /* Isolate bits 15 & 16 */
5179 eecd = ((eecd >> 15) & 0x03);
5181 /* If both bits are set, device is Flash type */
5189 /******************************************************************************
5190 * Verifies that the EEPROM has a valid checksum
5192 * hw - Struct containing variables accessed by shared code
5194 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
5195 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
5197 *****************************************************************************/
5199 em_validate_eeprom_checksum(struct em_hw *hw)
5201 uint16_t checksum = 0;
5202 uint16_t i, eeprom_data;
5204 DEBUGFUNC("em_validate_eeprom_checksum");
5206 if ((hw->mac_type == em_82573) &&
5207 (em_is_onboard_nvm_eeprom(hw) == FALSE)) {
5208 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
5209 * 10h-12h. Checksum may need to be fixed. */
5210 em_read_eeprom(hw, 0x10, 1, &eeprom_data);
5211 if ((eeprom_data & 0x10) == 0) {
5212 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum
5213 * has already been fixed. If the checksum is still wrong and this
5214 * bit is a 1, we need to return bad checksum. Otherwise, we need
5215 * to set this bit to a 1 and update the checksum. */
5216 em_read_eeprom(hw, 0x23, 1, &eeprom_data);
5217 if ((eeprom_data & 0x8000) == 0) {
5218 eeprom_data |= 0x8000;
5219 em_write_eeprom(hw, 0x23, 1, &eeprom_data);
5220 em_update_eeprom_checksum(hw);
5225 if (hw->mac_type == em_ich8lan) {
5226 /* Drivers must allocate the shadow ram structure for the
5227 * EEPROM checksum to be updated. Otherwise, this bit as well
5228 * as the checksum must both be set correctly for this
5229 * validation to pass.
5231 em_read_eeprom(hw, 0x19, 1, &eeprom_data);
5232 if ((eeprom_data & 0x40) == 0) {
5233 eeprom_data |= 0x40;
5234 em_write_eeprom(hw, 0x19, 1, &eeprom_data);
5235 em_update_eeprom_checksum(hw);
5239 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
5240 if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5241 DEBUGOUT("EEPROM Read Error\n");
5242 return -E1000_ERR_EEPROM;
5244 checksum += eeprom_data;
5247 if (checksum == (uint16_t) EEPROM_SUM)
5248 return E1000_SUCCESS;
5250 DEBUGOUT("EEPROM Checksum Invalid\n");
5251 return -E1000_ERR_EEPROM;
5255 /******************************************************************************
5256 * Calculates the EEPROM checksum and writes it to the EEPROM
5258 * hw - Struct containing variables accessed by shared code
5260 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
5261 * Writes the difference to word offset 63 of the EEPROM.
5262 *****************************************************************************/
5264 em_update_eeprom_checksum(struct em_hw *hw)
5267 uint16_t checksum = 0;
5268 uint16_t i, eeprom_data;
5270 DEBUGFUNC("em_update_eeprom_checksum");
5272 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
5273 if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5274 DEBUGOUT("EEPROM Read Error\n");
5275 return -E1000_ERR_EEPROM;
5277 checksum += eeprom_data;
5279 checksum = (uint16_t) EEPROM_SUM - checksum;
5280 if (em_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
5281 DEBUGOUT("EEPROM Write Error\n");
5282 return -E1000_ERR_EEPROM;
5283 } else if (hw->eeprom.type == em_eeprom_flash) {
5284 em_commit_shadow_ram(hw);
5285 } else if (hw->eeprom.type == em_eeprom_ich8) {
5286 em_commit_shadow_ram(hw);
5287 /* Reload the EEPROM, or else modifications will not appear
5288 * until after next adapter reset. */
5289 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5290 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
5291 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5294 return E1000_SUCCESS;
5297 /******************************************************************************
5298 * Parent function for writing words to the different EEPROM types.
5300 * hw - Struct containing variables accessed by shared code
5301 * offset - offset within the EEPROM to be written to
5302 * words - number of words to write
5303 * data - 16 bit word to be written to the EEPROM
5305 * If em_update_eeprom_checksum is not called after this function, the
5306 * EEPROM will most likely contain an invalid checksum.
5307 *****************************************************************************/
5309 em_write_eeprom(struct em_hw *hw,
5314 struct em_eeprom_info *eeprom = &hw->eeprom;
5317 DEBUGFUNC("em_write_eeprom");
5319 /* If eeprom is not yet detected, do so now */
5320 if (eeprom->word_size == 0)
5321 em_init_eeprom_params(hw);
5323 /* A check for invalid values: offset too large, too many words, and not
5326 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
5328 DEBUGOUT("\"words\" parameter out of bounds\n");
5329 return -E1000_ERR_EEPROM;
5332 /* 82573 writes only through eewr */
5333 if (eeprom->use_eewr == TRUE)
5334 return em_write_eeprom_eewr(hw, offset, words, data);
5336 if (eeprom->type == em_eeprom_ich8)
5337 return em_write_eeprom_ich8(hw, offset, words, data);
5339 /* Prepare the EEPROM for writing */
5340 if (em_acquire_eeprom(hw) != E1000_SUCCESS)
5341 return -E1000_ERR_EEPROM;
5343 if (eeprom->type == em_eeprom_microwire) {
5344 status = em_write_eeprom_microwire(hw, offset, words, data);
5346 status = em_write_eeprom_spi(hw, offset, words, data);
5350 /* Done with writing */
5351 em_release_eeprom(hw);
5356 /******************************************************************************
5357 * Writes a 16 bit word to a given offset in an SPI EEPROM.
5359 * hw - Struct containing variables accessed by shared code
5360 * offset - offset within the EEPROM to be written to
5361 * words - number of words to write
5362 * data - pointer to array of 8 bit words to be written to the EEPROM
5364 *****************************************************************************/
5366 em_write_eeprom_spi(struct em_hw *hw,
5371 struct em_eeprom_info *eeprom = &hw->eeprom;
5374 DEBUGFUNC("em_write_eeprom_spi");
5376 while (widx < words) {
5377 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
5379 if (em_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
5381 em_standby_eeprom(hw);
5383 /* Send the WRITE ENABLE command (8 bit opcode ) */
5384 em_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
5385 eeprom->opcode_bits);
5387 em_standby_eeprom(hw);
5389 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
5390 if ((eeprom->address_bits == 8) && (offset >= 128))
5391 write_opcode |= EEPROM_A8_OPCODE_SPI;
5393 /* Send the Write command (8-bit opcode + addr) */
5394 em_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
5396 em_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
5397 eeprom->address_bits);
5401 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
5402 while (widx < words) {
5403 uint16_t word_out = data[widx];
5404 word_out = (word_out >> 8) | (word_out << 8);
5405 em_shift_out_ee_bits(hw, word_out, 16);
5408 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
5409 * operation, while the smaller eeproms are capable of an 8-byte
5410 * PAGE WRITE operation. Break the inner loop to pass new address
5412 if ((((offset + widx)*2) % eeprom->page_size) == 0) {
5413 em_standby_eeprom(hw);
5419 return E1000_SUCCESS;
5422 /******************************************************************************
5423 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
5425 * hw - Struct containing variables accessed by shared code
5426 * offset - offset within the EEPROM to be written to
5427 * words - number of words to write
5428 * data - pointer to array of 16 bit words to be written to the EEPROM
5430 *****************************************************************************/
5432 em_write_eeprom_microwire(struct em_hw *hw,
5437 struct em_eeprom_info *eeprom = &hw->eeprom;
5439 uint16_t words_written = 0;
5442 DEBUGFUNC("em_write_eeprom_microwire");
5444 /* Send the write enable command to the EEPROM (3-bit opcode plus
5445 * 6/8-bit dummy address beginning with 11). It's less work to include
5446 * the 11 of the dummy address as part of the opcode than it is to shift
5447 * it over the correct number of bits for the address. This puts the
5448 * EEPROM into write/erase mode.
5450 em_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
5451 (uint16_t)(eeprom->opcode_bits + 2));
5453 em_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5455 /* Prepare the EEPROM */
5456 em_standby_eeprom(hw);
5458 while (words_written < words) {
5459 /* Send the Write command (3-bit opcode + addr) */
5460 em_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
5461 eeprom->opcode_bits);
5463 em_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
5464 eeprom->address_bits);
5467 em_shift_out_ee_bits(hw, data[words_written], 16);
5469 /* Toggle the CS line. This in effect tells the EEPROM to execute
5470 * the previous command.
5472 em_standby_eeprom(hw);
5474 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
5475 * signal that the command has been completed by raising the DO signal.
5476 * If DO does not go high in 10 milliseconds, then error out.
5478 for (i = 0; i < 200; i++) {
5479 eecd = E1000_READ_REG(hw, EECD);
5480 if (eecd & E1000_EECD_DO) break;
5484 DEBUGOUT("EEPROM Write did not complete\n");
5485 return -E1000_ERR_EEPROM;
5488 /* Recover from write */
5489 em_standby_eeprom(hw);
5494 /* Send the write disable command to the EEPROM (3-bit opcode plus
5495 * 6/8-bit dummy address beginning with 10). It's less work to include
5496 * the 10 of the dummy address as part of the opcode than it is to shift
5497 * it over the correct number of bits for the address. This takes the
5498 * EEPROM out of write/erase mode.
5500 em_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
5501 (uint16_t)(eeprom->opcode_bits + 2));
5503 em_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5505 return E1000_SUCCESS;
5508 /******************************************************************************
5509 * Flushes the cached eeprom to NVM. This is done by saving the modified values
5510 * in the eeprom cache and the non modified values in the currently active bank
5513 * hw - Struct containing variables accessed by shared code
5514 * offset - offset of word in the EEPROM to read
5515 * data - word read from the EEPROM
5516 * words - number of words to read
5517 *****************************************************************************/
5519 em_commit_shadow_ram(struct em_hw *hw)
5521 uint32_t attempts = 100000;
5525 int32_t error = E1000_SUCCESS;
5526 uint32_t old_bank_offset = 0;
5527 uint32_t new_bank_offset = 0;
5528 uint8_t low_byte = 0;
5529 uint8_t high_byte = 0;
5530 boolean_t sector_write_failed = FALSE;
5532 if (hw->mac_type == em_82573) {
5533 /* The flop register will be used to determine if flash type is STM */
5534 flop = E1000_READ_REG(hw, FLOP);
5535 for (i=0; i < attempts; i++) {
5536 eecd = E1000_READ_REG(hw, EECD);
5537 if ((eecd & E1000_EECD_FLUPD) == 0) {
5543 if (i == attempts) {
5544 return -E1000_ERR_EEPROM;
5547 /* If STM opcode located in bits 15:8 of flop, reset firmware */
5548 if ((flop & 0xFF00) == E1000_STM_OPCODE) {
5549 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
5552 /* Perform the flash update */
5553 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD);
5555 for (i=0; i < attempts; i++) {
5556 eecd = E1000_READ_REG(hw, EECD);
5557 if ((eecd & E1000_EECD_FLUPD) == 0) {
5563 if (i == attempts) {
5564 return -E1000_ERR_EEPROM;
5568 if (hw->mac_type == em_ich8lan && hw->eeprom_shadow_ram != NULL) {
5569 /* We're writing to the opposite bank so if we're on bank 1,
5570 * write to bank 0 etc. We also need to erase the segment that
5571 * is going to be written */
5572 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) {
5573 new_bank_offset = hw->flash_bank_size * 2;
5574 old_bank_offset = 0;
5575 em_erase_ich8_4k_segment(hw, 1);
5577 old_bank_offset = hw->flash_bank_size * 2;
5578 new_bank_offset = 0;
5579 em_erase_ich8_4k_segment(hw, 0);
5582 sector_write_failed = FALSE;
5583 /* Loop for every byte in the shadow RAM,
5584 * which is in units of words. */
5585 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5586 /* Determine whether to write the value stored
5587 * in the other NVM bank or a modified value stored
5588 * in the shadow RAM */
5589 if (hw->eeprom_shadow_ram[i].modified == TRUE) {
5590 low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word;
5592 error = em_verify_write_ich8_byte(hw,
5593 (i << 1) + new_bank_offset, low_byte);
5595 if (error != E1000_SUCCESS)
5596 sector_write_failed = TRUE;
5599 (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
5603 em_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5606 error = em_verify_write_ich8_byte(hw,
5607 (i << 1) + new_bank_offset, low_byte);
5609 if (error != E1000_SUCCESS)
5610 sector_write_failed = TRUE;
5612 em_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5618 /* If the write of the low byte was successful, go ahread and
5619 * write the high byte while checking to make sure that if it
5620 * is the signature byte, then it is handled properly */
5621 if (sector_write_failed == FALSE) {
5622 /* If the word is 0x13, then make sure the signature bits
5623 * (15:14) are 11b until the commit has completed.
5624 * This will allow us to write 10b which indicates the
5625 * signature is valid. We want to do this after the write
5626 * has completed so that we don't mark the segment valid
5627 * while the write is still in progress */
5628 if (i == E1000_ICH_NVM_SIG_WORD)
5629 high_byte = E1000_ICH_NVM_SIG_MASK | high_byte;
5631 error = em_verify_write_ich8_byte(hw,
5632 (i << 1) + new_bank_offset + 1, high_byte);
5633 if (error != E1000_SUCCESS)
5634 sector_write_failed = TRUE;
5637 /* If the write failed then break from the loop and
5638 * return an error */
5643 /* Don't bother writing the segment valid bits if sector
5644 * programming failed. */
5645 if (sector_write_failed == FALSE) {
5646 /* Finally validate the new segment by setting bit 15:14
5647 * to 10b in word 0x13 , this can be done without an
5648 * erase as well since these bits are 11 to start with
5649 * and we need to change bit 14 to 0b */
5650 em_read_ich8_byte(hw,
5651 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5654 error = em_verify_write_ich8_byte(hw,
5655 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte);
5656 /* And invalidate the previously valid segment by setting
5657 * its signature word (0x13) high_byte to 0b. This can be
5658 * done without an erase because flash erase sets all bits
5659 * to 1's. We can write 1's to 0's without an erase */
5660 if (error == E1000_SUCCESS) {
5661 error = em_verify_write_ich8_byte(hw,
5662 E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0);
5665 /* Clear the now not used entry in the cache */
5666 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5667 hw->eeprom_shadow_ram[i].modified = FALSE;
5668 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
5676 /******************************************************************************
5677 * Reads the adapter's part number from the EEPROM
5679 * hw - Struct containing variables accessed by shared code
5680 * part_num - Adapter's part number
5681 *****************************************************************************/
5683 em_read_part_num(struct em_hw *hw,
5686 uint16_t offset = EEPROM_PBA_BYTE_1;
5687 uint16_t eeprom_data;
5689 DEBUGFUNC("em_read_part_num");
5691 /* Get word 0 from EEPROM */
5692 if (em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
5693 DEBUGOUT("EEPROM Read Error\n");
5694 return -E1000_ERR_EEPROM;
5696 /* Save word 0 in upper half of part_num */
5697 *part_num = (uint32_t) (eeprom_data << 16);
5699 /* Get word 1 from EEPROM */
5700 if (em_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) {
5701 DEBUGOUT("EEPROM Read Error\n");
5702 return -E1000_ERR_EEPROM;
5704 /* Save word 1 in lower half of part_num */
5705 *part_num |= eeprom_data;
5707 return E1000_SUCCESS;
5710 /******************************************************************************
5711 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
5712 * second function of dual function devices
5714 * hw - Struct containing variables accessed by shared code
5715 *****************************************************************************/
5717 em_read_mac_addr(struct em_hw * hw)
5720 uint16_t eeprom_data, i;
5722 DEBUGFUNC("em_read_mac_addr");
5724 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
5726 if (em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
5727 DEBUGOUT("EEPROM Read Error\n");
5728 return -E1000_ERR_EEPROM;
5730 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
5731 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
5734 switch (hw->mac_type) {
5738 case em_82546_rev_3:
5740 case em_80003es2lan:
5741 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
5742 hw->perm_mac_addr[5] ^= 0x01;
5746 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
5747 hw->mac_addr[i] = hw->perm_mac_addr[i];
5748 return E1000_SUCCESS;
5751 /******************************************************************************
5752 * Initializes receive address filters.
5754 * hw - Struct containing variables accessed by shared code
5756 * Places the MAC address in receive address register 0 and clears the rest
5757 * of the receive addresss registers. Clears the multicast table. Assumes
5758 * the receiver is in reset when the routine is called.
5759 *****************************************************************************/
5761 em_init_rx_addrs(struct em_hw *hw)
5766 DEBUGFUNC("em_init_rx_addrs");
5768 /* Setup the receive address. */
5769 DEBUGOUT("Programming MAC Address into RAR[0]\n");
5771 em_rar_set(hw, hw->mac_addr, 0);
5773 rar_num = E1000_RAR_ENTRIES;
5775 /* Reserve a spot for the Locally Administered Address to work around
5776 * an 82571 issue in which a reset on one port will reload the MAC on
5777 * the other port. */
5778 if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE))
5780 if (hw->mac_type == em_ich8lan)
5781 rar_num = E1000_RAR_ENTRIES_ICH8LAN;
5783 /* Zero out the other 15 receive addresses. */
5784 DEBUGOUT("Clearing RAR[1-15]\n");
5785 for (i = 1; i < rar_num; i++) {
5786 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5787 E1000_WRITE_FLUSH(hw);
5788 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5789 E1000_WRITE_FLUSH(hw);
5793 /******************************************************************************
5794 * Updates the MAC's list of multicast addresses.
5796 * hw - Struct containing variables accessed by shared code
5797 * mc_addr_list - the list of new multicast addresses
5798 * mc_addr_count - number of addresses
5799 * pad - number of bytes between addresses in the list
5800 * rar_used_count - offset where to start adding mc addresses into the RAR's
5802 * The given list replaces any existing list. Clears the last 15 receive
5803 * address registers and the multicast table. Uses receive address registers
5804 * for the first 15 multicast addresses, and hashes the rest into the
5806 *****************************************************************************/
5808 em_mc_addr_list_update(struct em_hw *hw,
5809 uint8_t *mc_addr_list,
5810 uint32_t mc_addr_count,
5812 uint32_t rar_used_count)
5814 uint32_t hash_value;
5816 uint32_t num_rar_entry;
5817 uint32_t num_mta_entry;
5819 DEBUGFUNC("em_mc_addr_list_update");
5821 /* Set the new number of MC addresses that we are being requested to use. */
5822 hw->num_mc_addrs = mc_addr_count;
5824 /* Clear RAR[1-15] */
5825 DEBUGOUT(" Clearing RAR[1-15]\n");
5826 num_rar_entry = E1000_RAR_ENTRIES;
5827 if (hw->mac_type == em_ich8lan)
5828 num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN;
5830 /* Reserve a spot for the Locally Administered Address to work around
5831 * an 82571 issue in which a reset on one port will reload the MAC on
5832 * the other port. */
5833 if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE))
5836 for (i = rar_used_count; i < num_rar_entry; i++) {
5837 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5838 E1000_WRITE_FLUSH(hw);
5839 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5840 E1000_WRITE_FLUSH(hw);
5844 DEBUGOUT(" Clearing MTA\n");
5845 num_mta_entry = E1000_NUM_MTA_REGISTERS;
5846 if (hw->mac_type == em_ich8lan)
5847 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN;
5849 for (i = 0; i < num_mta_entry; i++) {
5850 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
5851 E1000_WRITE_FLUSH(hw);
5854 /* Add the new addresses */
5855 for (i = 0; i < mc_addr_count; i++) {
5856 DEBUGOUT(" Adding the multicast addresses:\n");
5857 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
5858 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
5859 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1],
5860 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2],
5861 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3],
5862 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4],
5863 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]);
5865 hash_value = em_hash_mc_addr(hw,
5867 (i * (ETH_LENGTH_OF_ADDRESS + pad)));
5869 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
5871 /* Place this multicast address in the RAR if there is room, *
5872 * else put it in the MTA
5874 if (rar_used_count < num_rar_entry) {
5876 mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
5880 em_mta_set(hw, hash_value);
5883 DEBUGOUT("MC Update Complete\n");
5886 /******************************************************************************
5887 * Hashes an address to determine its location in the multicast table
5889 * hw - Struct containing variables accessed by shared code
5890 * mc_addr - the multicast address to hash
5891 *****************************************************************************/
5893 em_hash_mc_addr(struct em_hw *hw,
5896 uint32_t hash_value = 0;
5898 /* The portion of the address that is used for the hash table is
5899 * determined by the mc_filter_type setting.
5901 switch (hw->mc_filter_type) {
5902 /* [0] [1] [2] [3] [4] [5]
5907 if (hw->mac_type == em_ich8lan) {
5908 /* [47:38] i.e. 0x158 for above example address */
5909 hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2));
5911 /* [47:36] i.e. 0x563 for above example address */
5912 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5916 if (hw->mac_type == em_ich8lan) {
5917 /* [46:37] i.e. 0x2B1 for above example address */
5918 hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3));
5920 /* [46:35] i.e. 0xAC6 for above example address */
5921 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
5925 if (hw->mac_type == em_ich8lan) {
5926 /*[45:36] i.e. 0x163 for above example address */
5927 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5929 /* [45:34] i.e. 0x5D8 for above example address */
5930 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5934 if (hw->mac_type == em_ich8lan) {
5935 /* [43:34] i.e. 0x18D for above example address */
5936 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5938 /* [43:32] i.e. 0x634 for above example address */
5939 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
5944 hash_value &= 0xFFF;
5945 if (hw->mac_type == em_ich8lan)
5946 hash_value &= 0x3FF;
5951 /******************************************************************************
5952 * Sets the bit in the multicast table corresponding to the hash value.
5954 * hw - Struct containing variables accessed by shared code
5955 * hash_value - Multicast address hash value
5956 *****************************************************************************/
5958 em_mta_set(struct em_hw *hw,
5959 uint32_t hash_value)
5961 uint32_t hash_bit, hash_reg;
5965 /* The MTA is a register array of 128 32-bit registers.
5966 * It is treated like an array of 4096 bits. We want to set
5967 * bit BitArray[hash_value]. So we figure out what register
5968 * the bit is in, read it, OR in the new bit, then write
5969 * back the new value. The register is determined by the
5970 * upper 7 bits of the hash value and the bit within that
5971 * register are determined by the lower 5 bits of the value.
5973 hash_reg = (hash_value >> 5) & 0x7F;
5974 if (hw->mac_type == em_ich8lan)
5977 hash_bit = hash_value & 0x1F;
5979 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
5981 mta |= (1 << hash_bit);
5983 /* If we are on an 82544 and we are trying to write an odd offset
5984 * in the MTA, save off the previous entry before writing and
5985 * restore the old value after writing.
5987 if ((hw->mac_type == em_82544) && ((hash_reg & 0x1) == 1)) {
5988 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
5989 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5990 E1000_WRITE_FLUSH(hw);
5991 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
5992 E1000_WRITE_FLUSH(hw);
5994 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5995 E1000_WRITE_FLUSH(hw);
5999 /******************************************************************************
6000 * Puts an ethernet address into a receive address register.
6002 * hw - Struct containing variables accessed by shared code
6003 * addr - Address to put into receive address register
6004 * index - Receive address register to write
6005 *****************************************************************************/
6007 em_rar_set(struct em_hw *hw,
6011 uint32_t rar_low, rar_high;
6013 /* HW expects these in little endian so we reverse the byte order
6014 * from network order (big endian) to little endian
6016 rar_low = ((uint32_t) addr[0] |
6017 ((uint32_t) addr[1] << 8) |
6018 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
6019 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8));
6021 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
6025 * If there are any Rx frames queued up or otherwise present in the HW
6026 * before RSS is enabled, and then we enable RSS, the HW Rx unit will
6027 * hang. To work around this issue, we have to disable receives and
6028 * flush out all Rx frames before we enable RSS. To do so, we modify we
6029 * redirect all Rx traffic to manageability and then reset the HW.
6030 * This flushes away Rx frames, and (since the redirections to
6031 * manageability persists across resets) keeps new ones from coming in
6032 * while we work. Then, we clear the Address Valid AV bit for all MAC
6033 * addresses and undo the re-direction to manageability.
6034 * Now, frames are coming in again, but the MAC won't accept them, so
6035 * far so good. We now proceed to initialize RSS (if necessary) and
6036 * configure the Rx unit. Last, we re-enable the AV bits and continue
6039 switch (hw->mac_type) {
6042 case em_80003es2lan:
6043 if (hw->leave_av_bit_off == TRUE)
6046 /* Indicate to hardware the Address is Valid. */
6047 rar_high |= E1000_RAH_AV;
6051 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
6052 E1000_WRITE_FLUSH(hw);
6053 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
6054 E1000_WRITE_FLUSH(hw);
6057 /******************************************************************************
6058 * Writes a value to the specified offset in the VLAN filter table.
6060 * hw - Struct containing variables accessed by shared code
6061 * offset - Offset in VLAN filer table to write
6062 * value - Value to write into VLAN filter table
6063 *****************************************************************************/
6065 em_write_vfta(struct em_hw *hw,
6071 if (hw->mac_type == em_ich8lan)
6074 if ((hw->mac_type == em_82544) && ((offset & 0x1) == 1)) {
6075 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
6076 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
6077 E1000_WRITE_FLUSH(hw);
6078 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
6079 E1000_WRITE_FLUSH(hw);
6081 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
6082 E1000_WRITE_FLUSH(hw);
6086 /******************************************************************************
6087 * Clears the VLAN filer table
6089 * hw - Struct containing variables accessed by shared code
6090 *****************************************************************************/
6092 em_clear_vfta(struct em_hw *hw)
6095 uint32_t vfta_value = 0;
6096 uint32_t vfta_offset = 0;
6097 uint32_t vfta_bit_in_reg = 0;
6099 if (hw->mac_type == em_ich8lan)
6102 if (hw->mac_type == em_82573) {
6103 if (hw->mng_cookie.vlan_id != 0) {
6104 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
6105 * ID. The following operations determine which 32b entry
6106 * (i.e. offset) into the array we want to set the VLAN ID
6107 * (i.e. bit) of the manageability unit. */
6108 vfta_offset = (hw->mng_cookie.vlan_id >>
6109 E1000_VFTA_ENTRY_SHIFT) &
6110 E1000_VFTA_ENTRY_MASK;
6111 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
6112 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
6115 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
6116 /* If the offset we want to clear is the same offset of the
6117 * manageability VLAN ID, then clear all bits except that of the
6118 * manageability unit */
6119 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
6120 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
6121 E1000_WRITE_FLUSH(hw);
6126 em_id_led_init(struct em_hw * hw)
6129 const uint32_t ledctl_mask = 0x000000FF;
6130 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
6131 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
6132 uint16_t eeprom_data, i, temp;
6133 const uint16_t led_mask = 0x0F;
6135 DEBUGFUNC("em_id_led_init");
6137 if (hw->mac_type < em_82540) {
6139 return E1000_SUCCESS;
6142 ledctl = E1000_READ_REG(hw, LEDCTL);
6143 hw->ledctl_default = ledctl;
6144 hw->ledctl_mode1 = hw->ledctl_default;
6145 hw->ledctl_mode2 = hw->ledctl_default;
6147 if (em_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
6148 DEBUGOUT("EEPROM Read Error\n");
6149 return -E1000_ERR_EEPROM;
6152 if ((hw->mac_type == em_82573) &&
6153 (eeprom_data == ID_LED_RESERVED_82573))
6154 eeprom_data = ID_LED_DEFAULT_82573;
6155 else if ((eeprom_data == ID_LED_RESERVED_0000) ||
6156 (eeprom_data == ID_LED_RESERVED_FFFF)) {
6157 if (hw->mac_type == em_ich8lan)
6158 eeprom_data = ID_LED_DEFAULT_ICH8LAN;
6160 eeprom_data = ID_LED_DEFAULT;
6163 for (i = 0; i < 4; i++) {
6164 temp = (eeprom_data >> (i << 2)) & led_mask;
6166 case ID_LED_ON1_DEF2:
6167 case ID_LED_ON1_ON2:
6168 case ID_LED_ON1_OFF2:
6169 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6170 hw->ledctl_mode1 |= ledctl_on << (i << 3);
6172 case ID_LED_OFF1_DEF2:
6173 case ID_LED_OFF1_ON2:
6174 case ID_LED_OFF1_OFF2:
6175 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6176 hw->ledctl_mode1 |= ledctl_off << (i << 3);
6183 case ID_LED_DEF1_ON2:
6184 case ID_LED_ON1_ON2:
6185 case ID_LED_OFF1_ON2:
6186 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6187 hw->ledctl_mode2 |= ledctl_on << (i << 3);
6189 case ID_LED_DEF1_OFF2:
6190 case ID_LED_ON1_OFF2:
6191 case ID_LED_OFF1_OFF2:
6192 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6193 hw->ledctl_mode2 |= ledctl_off << (i << 3);
6200 return E1000_SUCCESS;
6203 /******************************************************************************
6204 * Prepares SW controlable LED for use and saves the current state of the LED.
6206 * hw - Struct containing variables accessed by shared code
6207 *****************************************************************************/
6209 em_setup_led(struct em_hw *hw)
6212 int32_t ret_val = E1000_SUCCESS;
6214 DEBUGFUNC("em_setup_led");
6216 switch (hw->mac_type) {
6217 case em_82542_rev2_0:
6218 case em_82542_rev2_1:
6221 /* No setup necessary */
6225 case em_82541_rev_2:
6226 case em_82547_rev_2:
6227 /* Turn off PHY Smart Power Down (if enabled) */
6228 ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
6229 &hw->phy_spd_default);
6232 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6233 (uint16_t)(hw->phy_spd_default &
6234 ~IGP01E1000_GMII_SPD));
6239 if (hw->media_type == em_media_type_fiber) {
6240 ledctl = E1000_READ_REG(hw, LEDCTL);
6241 /* Save current LEDCTL settings */
6242 hw->ledctl_default = ledctl;
6244 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
6245 E1000_LEDCTL_LED0_BLINK |
6246 E1000_LEDCTL_LED0_MODE_MASK);
6247 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
6248 E1000_LEDCTL_LED0_MODE_SHIFT);
6249 E1000_WRITE_REG(hw, LEDCTL, ledctl);
6250 } else if (hw->media_type == em_media_type_copper)
6251 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6255 return E1000_SUCCESS;
6259 /******************************************************************************
6260 * Used on 82571 and later Si that has LED blink bits.
6261 * Callers must use their own timer and should have already called
6263 * Call em_cleanup led() to stop blinking
6265 * hw - Struct containing variables accessed by shared code
6266 *****************************************************************************/
6268 em_blink_led_start(struct em_hw *hw)
6271 uint32_t ledctl_blink = 0;
6273 DEBUGFUNC("em_id_led_blink_on");
6275 if (hw->mac_type < em_82571) {
6277 return E1000_SUCCESS;
6279 if (hw->media_type == em_media_type_fiber) {
6280 /* always blink LED0 for PCI-E fiber */
6281 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
6282 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
6284 /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */
6285 ledctl_blink = hw->ledctl_mode2;
6286 for (i=0; i < 4; i++)
6287 if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) ==
6288 E1000_LEDCTL_MODE_LED_ON)
6289 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8));
6292 E1000_WRITE_REG(hw, LEDCTL, ledctl_blink);
6294 return E1000_SUCCESS;
6297 /******************************************************************************
6298 * Restores the saved state of the SW controlable LED.
6300 * hw - Struct containing variables accessed by shared code
6301 *****************************************************************************/
6303 em_cleanup_led(struct em_hw *hw)
6305 int32_t ret_val = E1000_SUCCESS;
6307 DEBUGFUNC("em_cleanup_led");
6309 switch (hw->mac_type) {
6310 case em_82542_rev2_0:
6311 case em_82542_rev2_1:
6314 /* No cleanup necessary */
6318 case em_82541_rev_2:
6319 case em_82547_rev_2:
6320 /* Turn on PHY Smart Power Down (if previously enabled) */
6321 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6322 hw->phy_spd_default);
6327 if (hw->phy_type == em_phy_ife) {
6328 em_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
6331 /* Restore LEDCTL settings */
6332 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
6336 return E1000_SUCCESS;
6339 /******************************************************************************
6340 * Turns on the software controllable LED
6342 * hw - Struct containing variables accessed by shared code
6343 *****************************************************************************/
6345 em_led_on(struct em_hw *hw)
6347 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6349 DEBUGFUNC("em_led_on");
6351 switch (hw->mac_type) {
6352 case em_82542_rev2_0:
6353 case em_82542_rev2_1:
6355 /* Set SW Defineable Pin 0 to turn on the LED */
6356 ctrl |= E1000_CTRL_SWDPIN0;
6357 ctrl |= E1000_CTRL_SWDPIO0;
6360 if (hw->media_type == em_media_type_fiber) {
6361 /* Set SW Defineable Pin 0 to turn on the LED */
6362 ctrl |= E1000_CTRL_SWDPIN0;
6363 ctrl |= E1000_CTRL_SWDPIO0;
6365 /* Clear SW Defineable Pin 0 to turn on the LED */
6366 ctrl &= ~E1000_CTRL_SWDPIN0;
6367 ctrl |= E1000_CTRL_SWDPIO0;
6371 if (hw->media_type == em_media_type_fiber) {
6372 /* Clear SW Defineable Pin 0 to turn on the LED */
6373 ctrl &= ~E1000_CTRL_SWDPIN0;
6374 ctrl |= E1000_CTRL_SWDPIO0;
6375 } else if (hw->phy_type == em_phy_ife) {
6376 em_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6377 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
6378 } else if (hw->media_type == em_media_type_copper) {
6379 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
6380 return E1000_SUCCESS;
6385 E1000_WRITE_REG(hw, CTRL, ctrl);
6387 return E1000_SUCCESS;
6390 /******************************************************************************
6391 * Turns off the software controllable LED
6393 * hw - Struct containing variables accessed by shared code
6394 *****************************************************************************/
6396 em_led_off(struct em_hw *hw)
6398 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6400 DEBUGFUNC("em_led_off");
6402 switch (hw->mac_type) {
6403 case em_82542_rev2_0:
6404 case em_82542_rev2_1:
6406 /* Clear SW Defineable Pin 0 to turn off the LED */
6407 ctrl &= ~E1000_CTRL_SWDPIN0;
6408 ctrl |= E1000_CTRL_SWDPIO0;
6411 if (hw->media_type == em_media_type_fiber) {
6412 /* Clear SW Defineable Pin 0 to turn off the LED */
6413 ctrl &= ~E1000_CTRL_SWDPIN0;
6414 ctrl |= E1000_CTRL_SWDPIO0;
6416 /* Set SW Defineable Pin 0 to turn off the LED */
6417 ctrl |= E1000_CTRL_SWDPIN0;
6418 ctrl |= E1000_CTRL_SWDPIO0;
6422 if (hw->media_type == em_media_type_fiber) {
6423 /* Set SW Defineable Pin 0 to turn off the LED */
6424 ctrl |= E1000_CTRL_SWDPIN0;
6425 ctrl |= E1000_CTRL_SWDPIO0;
6426 } else if (hw->phy_type == em_phy_ife) {
6427 em_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6428 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
6429 } else if (hw->media_type == em_media_type_copper) {
6430 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6431 return E1000_SUCCESS;
6436 E1000_WRITE_REG(hw, CTRL, ctrl);
6438 return E1000_SUCCESS;
6441 /******************************************************************************
6442 * Clears all hardware statistics counters.
6444 * hw - Struct containing variables accessed by shared code
6445 *****************************************************************************/
6447 em_clear_hw_cntrs(struct em_hw *hw)
6449 volatile uint32_t temp;
6451 temp = E1000_READ_REG(hw, CRCERRS);
6452 temp = E1000_READ_REG(hw, SYMERRS);
6453 temp = E1000_READ_REG(hw, MPC);
6454 temp = E1000_READ_REG(hw, SCC);
6455 temp = E1000_READ_REG(hw, ECOL);
6456 temp = E1000_READ_REG(hw, MCC);
6457 temp = E1000_READ_REG(hw, LATECOL);
6458 temp = E1000_READ_REG(hw, COLC);
6459 temp = E1000_READ_REG(hw, DC);
6460 temp = E1000_READ_REG(hw, SEC);
6461 temp = E1000_READ_REG(hw, RLEC);
6462 temp = E1000_READ_REG(hw, XONRXC);
6463 temp = E1000_READ_REG(hw, XONTXC);
6464 temp = E1000_READ_REG(hw, XOFFRXC);
6465 temp = E1000_READ_REG(hw, XOFFTXC);
6466 temp = E1000_READ_REG(hw, FCRUC);
6468 if (hw->mac_type != em_ich8lan) {
6469 temp = E1000_READ_REG(hw, PRC64);
6470 temp = E1000_READ_REG(hw, PRC127);
6471 temp = E1000_READ_REG(hw, PRC255);
6472 temp = E1000_READ_REG(hw, PRC511);
6473 temp = E1000_READ_REG(hw, PRC1023);
6474 temp = E1000_READ_REG(hw, PRC1522);
6477 temp = E1000_READ_REG(hw, GPRC);
6478 temp = E1000_READ_REG(hw, BPRC);
6479 temp = E1000_READ_REG(hw, MPRC);
6480 temp = E1000_READ_REG(hw, GPTC);
6481 temp = E1000_READ_REG(hw, GORCL);
6482 temp = E1000_READ_REG(hw, GORCH);
6483 temp = E1000_READ_REG(hw, GOTCL);
6484 temp = E1000_READ_REG(hw, GOTCH);
6485 temp = E1000_READ_REG(hw, RNBC);
6486 temp = E1000_READ_REG(hw, RUC);
6487 temp = E1000_READ_REG(hw, RFC);
6488 temp = E1000_READ_REG(hw, ROC);
6489 temp = E1000_READ_REG(hw, RJC);
6490 temp = E1000_READ_REG(hw, TORL);
6491 temp = E1000_READ_REG(hw, TORH);
6492 temp = E1000_READ_REG(hw, TOTL);
6493 temp = E1000_READ_REG(hw, TOTH);
6494 temp = E1000_READ_REG(hw, TPR);
6495 temp = E1000_READ_REG(hw, TPT);
6497 if (hw->mac_type != em_ich8lan) {
6498 temp = E1000_READ_REG(hw, PTC64);
6499 temp = E1000_READ_REG(hw, PTC127);
6500 temp = E1000_READ_REG(hw, PTC255);
6501 temp = E1000_READ_REG(hw, PTC511);
6502 temp = E1000_READ_REG(hw, PTC1023);
6503 temp = E1000_READ_REG(hw, PTC1522);
6506 temp = E1000_READ_REG(hw, MPTC);
6507 temp = E1000_READ_REG(hw, BPTC);
6509 if (hw->mac_type < em_82543) return;
6511 temp = E1000_READ_REG(hw, ALGNERRC);
6512 temp = E1000_READ_REG(hw, RXERRC);
6513 temp = E1000_READ_REG(hw, TNCRS);
6514 temp = E1000_READ_REG(hw, CEXTERR);
6515 temp = E1000_READ_REG(hw, TSCTC);
6516 temp = E1000_READ_REG(hw, TSCTFC);
6518 if (hw->mac_type <= em_82544) return;
6520 temp = E1000_READ_REG(hw, MGTPRC);
6521 temp = E1000_READ_REG(hw, MGTPDC);
6522 temp = E1000_READ_REG(hw, MGTPTC);
6524 if (hw->mac_type <= em_82547_rev_2) return;
6526 temp = E1000_READ_REG(hw, IAC);
6527 temp = E1000_READ_REG(hw, ICRXOC);
6529 if (hw->mac_type == em_ich8lan) return;
6531 temp = E1000_READ_REG(hw, ICRXPTC);
6532 temp = E1000_READ_REG(hw, ICRXATC);
6533 temp = E1000_READ_REG(hw, ICTXPTC);
6534 temp = E1000_READ_REG(hw, ICTXATC);
6535 temp = E1000_READ_REG(hw, ICTXQEC);
6536 temp = E1000_READ_REG(hw, ICTXQMTC);
6537 temp = E1000_READ_REG(hw, ICRXDMTC);
6541 /******************************************************************************
6542 * Resets Adaptive IFS to its default state.
6544 * hw - Struct containing variables accessed by shared code
6546 * Call this after em_init_hw. You may override the IFS defaults by setting
6547 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
6548 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
6549 * before calling this function.
6550 *****************************************************************************/
6552 em_reset_adaptive(struct em_hw *hw)
6554 DEBUGFUNC("em_reset_adaptive");
6556 if (hw->adaptive_ifs) {
6557 if (!hw->ifs_params_forced) {
6558 hw->current_ifs_val = 0;
6559 hw->ifs_min_val = IFS_MIN;
6560 hw->ifs_max_val = IFS_MAX;
6561 hw->ifs_step_size = IFS_STEP;
6562 hw->ifs_ratio = IFS_RATIO;
6564 hw->in_ifs_mode = FALSE;
6565 E1000_WRITE_REG(hw, AIT, 0);
6567 DEBUGOUT("Not in Adaptive IFS mode!\n");
6571 /******************************************************************************
6572 * Called during the callback/watchdog routine to update IFS value based on
6573 * the ratio of transmits to collisions.
6575 * hw - Struct containing variables accessed by shared code
6576 * tx_packets - Number of transmits since last callback
6577 * total_collisions - Number of collisions since last callback
6578 *****************************************************************************/
6580 em_update_adaptive(struct em_hw *hw)
6582 DEBUGFUNC("em_update_adaptive");
6584 if (hw->adaptive_ifs) {
6585 if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
6586 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
6587 hw->in_ifs_mode = TRUE;
6588 if (hw->current_ifs_val < hw->ifs_max_val) {
6589 if (hw->current_ifs_val == 0)
6590 hw->current_ifs_val = hw->ifs_min_val;
6592 hw->current_ifs_val += hw->ifs_step_size;
6593 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
6597 if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
6598 hw->current_ifs_val = 0;
6599 hw->in_ifs_mode = FALSE;
6600 E1000_WRITE_REG(hw, AIT, 0);
6604 DEBUGOUT("Not in Adaptive IFS mode!\n");
6608 /******************************************************************************
6609 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
6611 * hw - Struct containing variables accessed by shared code
6612 * frame_len - The length of the frame in question
6613 * mac_addr - The Ethernet destination address of the frame in question
6614 *****************************************************************************/
6616 em_tbi_adjust_stats(struct em_hw *hw,
6617 struct em_hw_stats *stats,
6623 /* First adjust the frame length. */
6625 /* We need to adjust the statistics counters, since the hardware
6626 * counters overcount this packet as a CRC error and undercount
6627 * the packet as a good packet
6629 /* This packet should not be counted as a CRC error. */
6631 /* This packet does count as a Good Packet Received. */
6634 /* Adjust the Good Octets received counters */
6635 carry_bit = 0x80000000 & stats->gorcl;
6636 stats->gorcl += frame_len;
6637 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
6638 * Received Count) was one before the addition,
6639 * AND it is zero after, then we lost the carry out,
6640 * need to add one to Gorch (Good Octets Received Count High).
6641 * This could be simplified if all environments supported
6644 if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
6646 /* Is this a broadcast or multicast? Check broadcast first,
6647 * since the test for a multicast frame will test positive on
6648 * a broadcast frame.
6650 if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
6651 /* Broadcast packet */
6653 else if (*mac_addr & 0x01)
6654 /* Multicast packet */
6657 if (frame_len == hw->max_frame_size) {
6658 /* In this case, the hardware has overcounted the number of
6665 /* Adjust the bin counters when the extra byte put the frame in the
6666 * wrong bin. Remember that the frame_len was adjusted above.
6668 if (frame_len == 64) {
6671 } else if (frame_len == 127) {
6674 } else if (frame_len == 255) {
6677 } else if (frame_len == 511) {
6680 } else if (frame_len == 1023) {
6683 } else if (frame_len == 1522) {
6688 /******************************************************************************
6689 * Gets the current PCI bus type, speed, and width of the hardware
6691 * hw - Struct containing variables accessed by shared code
6692 *****************************************************************************/
6694 em_get_bus_info(struct em_hw *hw)
6697 uint16_t pci_ex_link_status;
6700 switch (hw->mac_type) {
6701 case em_82542_rev2_0:
6702 case em_82542_rev2_1:
6703 hw->bus_type = em_bus_type_unknown;
6704 hw->bus_speed = em_bus_speed_unknown;
6705 hw->bus_width = em_bus_width_unknown;
6710 case em_80003es2lan:
6711 hw->bus_type = em_bus_type_pci_express;
6712 hw->bus_speed = em_bus_speed_2500;
6713 ret_val = em_read_pcie_cap_reg(hw,
6715 &pci_ex_link_status);
6717 hw->bus_width = em_bus_width_unknown;
6719 hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >>
6720 PCI_EX_LINK_WIDTH_SHIFT;
6723 hw->bus_type = em_bus_type_pci_express;
6724 hw->bus_speed = em_bus_speed_2500;
6725 hw->bus_width = em_bus_width_pciex_1;
6728 status = E1000_READ_REG(hw, STATUS);
6729 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
6730 em_bus_type_pcix : em_bus_type_pci;
6732 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
6733 hw->bus_speed = (hw->bus_type == em_bus_type_pci) ?
6734 em_bus_speed_66 : em_bus_speed_120;
6735 } else if (hw->bus_type == em_bus_type_pci) {
6736 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
6737 em_bus_speed_66 : em_bus_speed_33;
6739 switch (status & E1000_STATUS_PCIX_SPEED) {
6740 case E1000_STATUS_PCIX_SPEED_66:
6741 hw->bus_speed = em_bus_speed_66;
6743 case E1000_STATUS_PCIX_SPEED_100:
6744 hw->bus_speed = em_bus_speed_100;
6746 case E1000_STATUS_PCIX_SPEED_133:
6747 hw->bus_speed = em_bus_speed_133;
6750 hw->bus_speed = em_bus_speed_reserved;
6754 hw->bus_width = (status & E1000_STATUS_BUS64) ?
6755 em_bus_width_64 : em_bus_width_32;
6760 /******************************************************************************
6761 * Writes a value to one of the devices registers using port I/O (as opposed to
6762 * memory mapped I/O). Only 82544 and newer devices support port I/O.
6764 * hw - Struct containing variables accessed by shared code
6765 * offset - offset to write to
6766 * value - value to write
6767 *****************************************************************************/
6769 em_write_reg_io(struct em_hw *hw,
6773 unsigned long io_addr = hw->io_base;
6774 unsigned long io_data = hw->io_base + 4;
6776 em_io_write(hw, io_addr, offset);
6777 em_io_write(hw, io_data, value);
6780 /******************************************************************************
6781 * Estimates the cable length.
6783 * hw - Struct containing variables accessed by shared code
6784 * min_length - The estimated minimum length
6785 * max_length - The estimated maximum length
6787 * returns: - E1000_ERR_XXX
6790 * This function always returns a ranged length (minimum & maximum).
6791 * So for M88 phy's, this function interprets the one value returned from the
6792 * register to the minimum and maximum range.
6793 * For IGP phy's, the function calculates the range by the AGC registers.
6794 *****************************************************************************/
6796 em_get_cable_length(struct em_hw *hw,
6797 uint16_t *min_length,
6798 uint16_t *max_length)
6801 uint16_t agc_value = 0;
6802 uint16_t i, phy_data;
6803 uint16_t cable_length;
6805 DEBUGFUNC("em_get_cable_length");
6807 *min_length = *max_length = 0;
6809 /* Use old method for Phy older than IGP */
6810 if (hw->phy_type == em_phy_m88) {
6812 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6816 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
6817 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
6819 /* Convert the enum value to ranged values */
6820 switch (cable_length) {
6821 case em_cable_length_50:
6823 *max_length = em_igp_cable_length_50;
6825 case em_cable_length_50_80:
6826 *min_length = em_igp_cable_length_50;
6827 *max_length = em_igp_cable_length_80;
6829 case em_cable_length_80_110:
6830 *min_length = em_igp_cable_length_80;
6831 *max_length = em_igp_cable_length_110;
6833 case em_cable_length_110_140:
6834 *min_length = em_igp_cable_length_110;
6835 *max_length = em_igp_cable_length_140;
6837 case em_cable_length_140:
6838 *min_length = em_igp_cable_length_140;
6839 *max_length = em_igp_cable_length_170;
6842 return -E1000_ERR_PHY;
6845 } else if (hw->phy_type == em_phy_gg82563) {
6846 ret_val = em_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
6850 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
6852 switch (cable_length) {
6853 case em_gg_cable_length_60:
6855 *max_length = em_igp_cable_length_60;
6857 case em_gg_cable_length_60_115:
6858 *min_length = em_igp_cable_length_60;
6859 *max_length = em_igp_cable_length_115;
6861 case em_gg_cable_length_115_150:
6862 *min_length = em_igp_cable_length_115;
6863 *max_length = em_igp_cable_length_150;
6865 case em_gg_cable_length_150:
6866 *min_length = em_igp_cable_length_150;
6867 *max_length = em_igp_cable_length_180;
6870 return -E1000_ERR_PHY;
6873 } else if (hw->phy_type == em_phy_igp) { /* For IGP PHY */
6874 uint16_t cur_agc_value;
6875 uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6876 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6877 {IGP01E1000_PHY_AGC_A,
6878 IGP01E1000_PHY_AGC_B,
6879 IGP01E1000_PHY_AGC_C,
6880 IGP01E1000_PHY_AGC_D};
6881 /* Read the AGC registers for all channels */
6882 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6884 ret_val = em_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6888 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
6890 /* Value bound check. */
6891 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
6892 (cur_agc_value == 0))
6893 return -E1000_ERR_PHY;
6895 agc_value += cur_agc_value;
6897 /* Update minimal AGC value. */
6898 if (min_agc_value > cur_agc_value)
6899 min_agc_value = cur_agc_value;
6902 /* Remove the minimal AGC result for length < 50m */
6903 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * em_igp_cable_length_50) {
6904 agc_value -= min_agc_value;
6906 /* Get the average length of the remaining 3 channels */
6907 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
6909 /* Get the average length of all the 4 channels. */
6910 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
6913 /* Set the range of the calculated length. */
6914 *min_length = ((em_igp_cable_length_table[agc_value] -
6915 IGP01E1000_AGC_RANGE) > 0) ?
6916 (em_igp_cable_length_table[agc_value] -
6917 IGP01E1000_AGC_RANGE) : 0;
6918 *max_length = em_igp_cable_length_table[agc_value] +
6919 IGP01E1000_AGC_RANGE;
6920 } else if (hw->phy_type == em_phy_igp_2 ||
6921 hw->phy_type == em_phy_igp_3) {
6922 uint16_t cur_agc_index, max_agc_index = 0;
6923 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
6924 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
6925 {IGP02E1000_PHY_AGC_A,
6926 IGP02E1000_PHY_AGC_B,
6927 IGP02E1000_PHY_AGC_C,
6928 IGP02E1000_PHY_AGC_D};
6929 /* Read the AGC registers for all channels */
6930 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
6931 ret_val = em_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6935 /* Getting bits 15:9, which represent the combination of course and
6936 * fine gain values. The result is a number that can be put into
6937 * the lookup table to obtain the approximate cable length. */
6938 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
6939 IGP02E1000_AGC_LENGTH_MASK;
6941 /* Array index bound check. */
6942 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) ||
6943 (cur_agc_index == 0))
6944 return -E1000_ERR_PHY;
6946 /* Remove min & max AGC values from calculation. */
6947 if (em_igp_2_cable_length_table[min_agc_index] >
6948 em_igp_2_cable_length_table[cur_agc_index])
6949 min_agc_index = cur_agc_index;
6950 if (em_igp_2_cable_length_table[max_agc_index] <
6951 em_igp_2_cable_length_table[cur_agc_index])
6952 max_agc_index = cur_agc_index;
6954 agc_value += em_igp_2_cable_length_table[cur_agc_index];
6957 agc_value -= (em_igp_2_cable_length_table[min_agc_index] +
6958 em_igp_2_cable_length_table[max_agc_index]);
6959 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
6961 /* Calculate cable length with the error range of +/- 10 meters. */
6962 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
6963 (agc_value - IGP02E1000_AGC_RANGE) : 0;
6964 *max_length = agc_value + IGP02E1000_AGC_RANGE;
6967 return E1000_SUCCESS;
6970 /******************************************************************************
6971 * Check the cable polarity
6973 * hw - Struct containing variables accessed by shared code
6974 * polarity - output parameter : 0 - Polarity is not reversed
6975 * 1 - Polarity is reversed.
6977 * returns: - E1000_ERR_XXX
6980 * For phy's older then IGP, this function simply reads the polarity bit in the
6981 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
6982 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
6983 * return 0. If the link speed is 1000 Mbps the polarity status is in the
6984 * IGP01E1000_PHY_PCS_INIT_REG.
6985 *****************************************************************************/
6987 em_check_polarity(struct em_hw *hw,
6988 em_rev_polarity *polarity)
6993 DEBUGFUNC("em_check_polarity");
6995 if ((hw->phy_type == em_phy_m88) ||
6996 (hw->phy_type == em_phy_gg82563)) {
6997 /* return the Polarity bit in the Status register. */
6998 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
7002 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
7003 M88E1000_PSSR_REV_POLARITY_SHIFT) ?
7004 em_rev_polarity_reversed : em_rev_polarity_normal;
7006 } else if (hw->phy_type == em_phy_igp ||
7007 hw->phy_type == em_phy_igp_3 ||
7008 hw->phy_type == em_phy_igp_2) {
7009 /* Read the Status register to check the speed */
7010 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
7015 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
7016 * find the polarity status */
7017 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
7018 IGP01E1000_PSSR_SPEED_1000MBPS) {
7020 /* Read the GIG initialization PCS register (0x00B4) */
7021 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
7026 /* Check the polarity bits */
7027 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
7028 em_rev_polarity_reversed : em_rev_polarity_normal;
7030 /* For 10 Mbps, read the polarity bit in the status register. (for
7031 * 100 Mbps this bit is always 0) */
7032 *polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
7033 em_rev_polarity_reversed : em_rev_polarity_normal;
7035 } else if (hw->phy_type == em_phy_ife) {
7036 ret_val = em_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL,
7040 *polarity = ((phy_data & IFE_PESC_POLARITY_REVERSED) >>
7041 IFE_PESC_POLARITY_REVERSED_SHIFT) ?
7042 em_rev_polarity_reversed : em_rev_polarity_normal;
7044 return E1000_SUCCESS;
7047 /******************************************************************************
7048 * Check if Downshift occured
7050 * hw - Struct containing variables accessed by shared code
7051 * downshift - output parameter : 0 - No Downshift ocured.
7052 * 1 - Downshift ocured.
7054 * returns: - E1000_ERR_XXX
7057 * For phy's older then IGP, this function reads the Downshift bit in the Phy
7058 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
7059 * Link Health register. In IGP this bit is latched high, so the driver must
7060 * read it immediately after link is established.
7061 *****************************************************************************/
7063 em_check_downshift(struct em_hw *hw)
7068 DEBUGFUNC("em_check_downshift");
7070 if (hw->phy_type == em_phy_igp ||
7071 hw->phy_type == em_phy_igp_3 ||
7072 hw->phy_type == em_phy_igp_2) {
7073 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
7078 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
7079 } else if ((hw->phy_type == em_phy_m88) ||
7080 (hw->phy_type == em_phy_gg82563)) {
7081 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
7086 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
7087 M88E1000_PSSR_DOWNSHIFT_SHIFT;
7088 } else if (hw->phy_type == em_phy_ife) {
7089 /* em_phy_ife supports 10/100 speed only */
7090 hw->speed_downgraded = FALSE;
7093 return E1000_SUCCESS;
7096 /*****************************************************************************
7098 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
7099 * gigabit link is achieved to improve link quality.
7101 * hw: Struct containing variables accessed by shared code
7103 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7104 * E1000_SUCCESS at any other case.
7106 ****************************************************************************/
7109 em_config_dsp_after_link_change(struct em_hw *hw,
7113 uint16_t phy_data, phy_saved_data, speed, duplex, i;
7114 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
7115 {IGP01E1000_PHY_AGC_PARAM_A,
7116 IGP01E1000_PHY_AGC_PARAM_B,
7117 IGP01E1000_PHY_AGC_PARAM_C,
7118 IGP01E1000_PHY_AGC_PARAM_D};
7119 uint16_t min_length, max_length;
7121 DEBUGFUNC("em_config_dsp_after_link_change");
7123 if (hw->phy_type != em_phy_igp)
7124 return E1000_SUCCESS;
7127 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex);
7129 DEBUGOUT("Error getting link speed and duplex\n");
7133 if (speed == SPEED_1000) {
7135 ret_val = em_get_cable_length(hw, &min_length, &max_length);
7139 if ((hw->dsp_config_state == em_dsp_config_enabled) &&
7140 min_length >= em_igp_cable_length_50) {
7142 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
7143 ret_val = em_read_phy_reg(hw, dsp_reg_array[i],
7148 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7150 ret_val = em_write_phy_reg(hw, dsp_reg_array[i],
7155 hw->dsp_config_state = em_dsp_config_activated;
7158 if ((hw->ffe_config_state == em_ffe_config_enabled) &&
7159 (min_length < em_igp_cable_length_50)) {
7161 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
7162 uint32_t idle_errs = 0;
7164 /* clear previous idle error counts */
7165 ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS,
7170 for (i = 0; i < ffe_idle_err_timeout; i++) {
7172 ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS,
7177 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
7178 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
7179 hw->ffe_config_state = em_ffe_config_active;
7181 ret_val = em_write_phy_reg(hw,
7182 IGP01E1000_PHY_DSP_FFE,
7183 IGP01E1000_PHY_DSP_FFE_CM_CP);
7190 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
7195 if (hw->dsp_config_state == em_dsp_config_activated) {
7196 /* Save off the current value of register 0x2F5B to be restored at
7197 * the end of the routines. */
7198 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7203 /* Disable the PHY transmitter */
7204 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003);
7211 ret_val = em_write_phy_reg(hw, 0x0000,
7212 IGP01E1000_IEEE_FORCE_GIGA);
7215 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
7216 ret_val = em_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
7220 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7221 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
7223 ret_val = em_write_phy_reg(hw,dsp_reg_array[i], phy_data);
7228 ret_val = em_write_phy_reg(hw, 0x0000,
7229 IGP01E1000_IEEE_RESTART_AUTONEG);
7235 /* Now enable the transmitter */
7236 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7241 hw->dsp_config_state = em_dsp_config_enabled;
7244 if (hw->ffe_config_state == em_ffe_config_active) {
7245 /* Save off the current value of register 0x2F5B to be restored at
7246 * the end of the routines. */
7247 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7252 /* Disable the PHY transmitter */
7253 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003);
7260 ret_val = em_write_phy_reg(hw, 0x0000,
7261 IGP01E1000_IEEE_FORCE_GIGA);
7264 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
7265 IGP01E1000_PHY_DSP_FFE_DEFAULT);
7269 ret_val = em_write_phy_reg(hw, 0x0000,
7270 IGP01E1000_IEEE_RESTART_AUTONEG);
7276 /* Now enable the transmitter */
7277 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7282 hw->ffe_config_state = em_ffe_config_enabled;
7285 return E1000_SUCCESS;
7288 /*****************************************************************************
7289 * Set PHY to class A mode
7290 * Assumes the following operations will follow to enable the new class mode.
7291 * 1. Do a PHY soft reset
7292 * 2. Restart auto-negotiation or force link.
7294 * hw - Struct containing variables accessed by shared code
7295 ****************************************************************************/
7297 em_set_phy_mode(struct em_hw *hw)
7300 uint16_t eeprom_data;
7302 DEBUGFUNC("em_set_phy_mode");
7304 if ((hw->mac_type == em_82545_rev_3) &&
7305 (hw->media_type == em_media_type_copper)) {
7306 ret_val = em_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
7311 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
7312 (eeprom_data & EEPROM_PHY_CLASS_A)) {
7313 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
7316 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
7320 hw->phy_reset_disable = FALSE;
7324 return E1000_SUCCESS;
7327 /*****************************************************************************
7329 * This function sets the lplu state according to the active flag. When
7330 * activating lplu this function also disables smart speed and vise versa.
7331 * lplu will not be activated unless the device autonegotiation advertisment
7332 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7333 * hw: Struct containing variables accessed by shared code
7334 * active - true to enable lplu false to disable lplu.
7336 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7337 * E1000_SUCCESS at any other case.
7339 ****************************************************************************/
7342 em_set_d3_lplu_state(struct em_hw *hw,
7345 uint32_t phy_ctrl = 0;
7348 DEBUGFUNC("em_set_d3_lplu_state");
7350 if (hw->phy_type != em_phy_igp && hw->phy_type != em_phy_igp_2
7351 && hw->phy_type != em_phy_igp_3)
7352 return E1000_SUCCESS;
7354 /* During driver activity LPLU should not be used or it will attain link
7355 * from the lowest speeds starting from 10Mbps. The capability is used for
7356 * Dx transitions and states */
7357 if (hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) {
7358 ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
7361 } else if (hw->mac_type == em_ich8lan) {
7362 /* MAC writes into PHY register based on the state transition
7363 * and start auto-negotiation. SW driver can overwrite the settings
7364 * in CSR PHY power control E1000_PHY_CTRL register. */
7365 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7367 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7373 if (hw->mac_type == em_82541_rev_2 ||
7374 hw->mac_type == em_82547_rev_2) {
7375 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
7376 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7380 if (hw->mac_type == em_ich8lan) {
7381 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
7382 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7384 phy_data &= ~IGP02E1000_PM_D3_LPLU;
7385 ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7392 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7393 * Dx states where the power conservation is most important. During
7394 * driver activity we should enable SmartSpeed, so performance is
7396 if (hw->smart_speed == em_smart_speed_on) {
7397 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7402 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7403 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7407 } else if (hw->smart_speed == em_smart_speed_off) {
7408 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7413 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7414 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7420 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
7421 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
7422 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
7424 if (hw->mac_type == em_82541_rev_2 ||
7425 hw->mac_type == em_82547_rev_2) {
7426 phy_data |= IGP01E1000_GMII_FLEX_SPD;
7427 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7431 if (hw->mac_type == em_ich8lan) {
7432 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
7433 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7435 phy_data |= IGP02E1000_PM_D3_LPLU;
7436 ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7443 /* When LPLU is enabled we should disable SmartSpeed */
7444 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7448 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7449 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7454 return E1000_SUCCESS;
7457 /*****************************************************************************
7459 * This function sets the lplu d0 state according to the active flag. When
7460 * activating lplu this function also disables smart speed and vise versa.
7461 * lplu will not be activated unless the device autonegotiation advertisment
7462 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7463 * hw: Struct containing variables accessed by shared code
7464 * active - true to enable lplu false to disable lplu.
7466 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7467 * E1000_SUCCESS at any other case.
7469 ****************************************************************************/
7472 em_set_d0_lplu_state(struct em_hw *hw,
7475 uint32_t phy_ctrl = 0;
7478 DEBUGFUNC("em_set_d0_lplu_state");
7480 if (hw->mac_type <= em_82547_rev_2)
7481 return E1000_SUCCESS;
7483 if (hw->mac_type == em_ich8lan) {
7484 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7486 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7492 if (hw->mac_type == em_ich8lan) {
7493 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
7494 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7496 phy_data &= ~IGP02E1000_PM_D0_LPLU;
7497 ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7502 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7503 * Dx states where the power conservation is most important. During
7504 * driver activity we should enable SmartSpeed, so performance is
7506 if (hw->smart_speed == em_smart_speed_on) {
7507 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7512 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7513 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7517 } else if (hw->smart_speed == em_smart_speed_off) {
7518 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7523 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7524 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7533 if (hw->mac_type == em_ich8lan) {
7534 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
7535 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7537 phy_data |= IGP02E1000_PM_D0_LPLU;
7538 ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7543 /* When LPLU is enabled we should disable SmartSpeed */
7544 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7548 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7549 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7554 return E1000_SUCCESS;
7557 /******************************************************************************
7558 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
7560 * hw - Struct containing variables accessed by shared code
7561 *****************************************************************************/
7563 em_set_vco_speed(struct em_hw *hw)
7566 uint16_t default_page = 0;
7569 DEBUGFUNC("em_set_vco_speed");
7571 switch (hw->mac_type) {
7572 case em_82545_rev_3:
7573 case em_82546_rev_3:
7576 return E1000_SUCCESS;
7579 /* Set PHY register 30, page 5, bit 8 to 0 */
7581 ret_val = em_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
7585 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
7589 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7593 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
7594 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7598 /* Set PHY register 30, page 4, bit 11 to 1 */
7600 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
7604 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7608 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
7609 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7613 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
7617 return E1000_SUCCESS;
7621 /*****************************************************************************
7622 * This function reads the cookie from ARC ram.
7624 * returns: - E1000_SUCCESS .
7625 ****************************************************************************/
7627 em_host_if_read_cookie(struct em_hw * hw, uint8_t *buffer)
7630 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET;
7631 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH;
7633 length = (length >> 2);
7634 offset = (offset >> 2);
7636 for (i = 0; i < length; i++) {
7637 *((uint32_t *) buffer + i) =
7638 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
7640 return E1000_SUCCESS;
7644 /*****************************************************************************
7645 * This function checks whether the HOST IF is enabled for command operaton
7646 * and also checks whether the previous command is completed.
7647 * It busy waits in case of previous command is not completed.
7649 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
7651 * - E1000_SUCCESS for success.
7652 ****************************************************************************/
7654 em_mng_enable_host_if(struct em_hw * hw)
7659 /* Check that the host interface is enabled. */
7660 hicr = E1000_READ_REG(hw, HICR);
7661 if ((hicr & E1000_HICR_EN) == 0) {
7662 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
7663 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7665 /* check the previous command is completed */
7666 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
7667 hicr = E1000_READ_REG(hw, HICR);
7668 if (!(hicr & E1000_HICR_C))
7673 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
7674 DEBUGOUT("Previous command timeout failed .\n");
7675 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7677 return E1000_SUCCESS;
7680 /*****************************************************************************
7681 * This function writes the buffer content at the offset given on the host if.
7682 * It also does alignment considerations to do the writes in most efficient way.
7683 * Also fills up the sum of the buffer in *buffer parameter.
7685 * returns - E1000_SUCCESS for success.
7686 ****************************************************************************/
7688 em_mng_host_if_write(struct em_hw * hw, uint8_t *buffer,
7689 uint16_t length, uint16_t offset, uint8_t *sum)
7692 uint8_t *bufptr = buffer;
7694 uint16_t remaining, i, j, prev_bytes;
7696 /* sum = only sum of the data and it is not checksum */
7698 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
7699 return -E1000_ERR_PARAM;
7702 tmp = (uint8_t *)&data;
7703 prev_bytes = offset & 0x3;
7708 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
7709 for (j = prev_bytes; j < sizeof(uint32_t); j++) {
7710 *(tmp + j) = *bufptr++;
7713 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
7714 length -= j - prev_bytes;
7718 remaining = length & 0x3;
7719 length -= remaining;
7721 /* Calculate length in DWORDs */
7724 /* The device driver writes the relevant command block into the
7726 for (i = 0; i < length; i++) {
7727 for (j = 0; j < sizeof(uint32_t); j++) {
7728 *(tmp + j) = *bufptr++;
7732 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7735 for (j = 0; j < sizeof(uint32_t); j++) {
7737 *(tmp + j) = *bufptr++;
7743 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7746 return E1000_SUCCESS;
7750 /*****************************************************************************
7751 * This function writes the command header after does the checksum calculation.
7753 * returns - E1000_SUCCESS for success.
7754 ****************************************************************************/
7756 em_mng_write_cmd_header(struct em_hw * hw,
7757 struct em_host_mng_command_header * hdr)
7763 /* Write the whole command header structure which includes sum of
7766 uint16_t length = sizeof(struct em_host_mng_command_header);
7768 sum = hdr->checksum;
7771 buffer = (uint8_t *) hdr;
7776 hdr->checksum = 0 - sum;
7779 /* The device driver writes the relevant command block into the ram area. */
7780 for (i = 0; i < length; i++) {
7781 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i));
7782 E1000_WRITE_FLUSH(hw);
7785 return E1000_SUCCESS;
7789 /*****************************************************************************
7790 * This function indicates to ARC that a new command is pending which completes
7791 * one write operation by the driver.
7793 * returns - E1000_SUCCESS for success.
7794 ****************************************************************************/
7796 em_mng_write_commit(struct em_hw * hw)
7800 hicr = E1000_READ_REG(hw, HICR);
7801 /* Setting this bit tells the ARC that a new command is pending. */
7802 E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C);
7804 return E1000_SUCCESS;
7808 /*****************************************************************************
7809 * This function checks the mode of the firmware.
7811 * returns - TRUE when the mode is IAMT or FALSE.
7812 ****************************************************************************/
7814 em_check_mng_mode(struct em_hw *hw)
7818 fwsm = E1000_READ_REG(hw, FWSM);
7820 if (hw->mac_type == em_ich8lan) {
7821 if ((fwsm & E1000_FWSM_MODE_MASK) ==
7822 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7824 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
7825 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7832 /*****************************************************************************
7833 * This function writes the dhcp info .
7834 ****************************************************************************/
7836 em_mng_write_dhcp_info(struct em_hw * hw, uint8_t *buffer,
7840 struct em_host_mng_command_header hdr;
7842 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
7843 hdr.command_length = length;
7848 ret_val = em_mng_enable_host_if(hw);
7849 if (ret_val == E1000_SUCCESS) {
7850 ret_val = em_mng_host_if_write(hw, buffer, length, sizeof(hdr),
7852 if (ret_val == E1000_SUCCESS) {
7853 ret_val = em_mng_write_cmd_header(hw, &hdr);
7854 if (ret_val == E1000_SUCCESS)
7855 ret_val = em_mng_write_commit(hw);
7862 /*****************************************************************************
7863 * This function calculates the checksum.
7865 * returns - checksum of buffer contents.
7866 ****************************************************************************/
7868 em_calculate_mng_checksum(char *buffer, uint32_t length)
7876 for (i=0; i < length; i++)
7879 return (uint8_t) (0 - sum);
7882 /*****************************************************************************
7883 * This function checks whether tx pkt filtering needs to be enabled or not.
7885 * returns - TRUE for packet filtering or FALSE.
7886 ****************************************************************************/
7888 em_enable_tx_pkt_filtering(struct em_hw *hw)
7890 /* called in init as well as watchdog timer functions */
7892 int32_t ret_val, checksum;
7893 boolean_t tx_filter = FALSE;
7894 struct em_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
7895 uint8_t *buffer = (uint8_t *) &(hw->mng_cookie);
7897 if (em_check_mng_mode(hw)) {
7898 ret_val = em_mng_enable_host_if(hw);
7899 if (ret_val == E1000_SUCCESS) {
7900 ret_val = em_host_if_read_cookie(hw, buffer);
7901 if (ret_val == E1000_SUCCESS) {
7902 checksum = hdr->checksum;
7904 if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
7905 checksum == em_calculate_mng_checksum((char *)buffer,
7906 E1000_MNG_DHCP_COOKIE_LENGTH)) {
7908 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
7917 hw->tx_pkt_filtering = tx_filter;
7921 /******************************************************************************
7922 * Verifies the hardware needs to allow ARPs to be processed by the host
7924 * hw - Struct containing variables accessed by shared code
7926 * returns: - TRUE/FALSE
7928 *****************************************************************************/
7930 em_enable_mng_pass_thru(struct em_hw *hw)
7933 uint32_t fwsm, factps;
7935 if (hw->asf_firmware_present) {
7936 manc = E1000_READ_REG(hw, MANC);
7938 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
7939 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
7941 if (em_arc_subsystem_valid(hw) == TRUE) {
7942 fwsm = E1000_READ_REG(hw, FWSM);
7943 factps = E1000_READ_REG(hw, FACTPS);
7945 if (((fwsm & E1000_FWSM_MODE_MASK) ==
7946 (em_mng_mode_pt << E1000_FWSM_MODE_SHIFT)) &&
7947 (factps & E1000_FACTPS_MNGCG))
7950 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
7957 em_polarity_reversal_workaround(struct em_hw *hw)
7960 uint16_t mii_status_reg;
7963 /* Polarity reversal workaround for forced 10F/10H links. */
7965 /* Disable the transmitter on the PHY */
7967 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7970 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
7974 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7978 /* This loop will early-out if the NO link condition has been met. */
7979 for (i = PHY_FORCE_TIME; i > 0; i--) {
7980 /* Read the MII Status Register and wait for Link Status bit
7984 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7988 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7992 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
7993 msec_delay_irq(100);
7996 /* Recommended delay time after link has been lost */
7997 msec_delay_irq(1000);
7999 /* Now we will re-enable th transmitter on the PHY */
8001 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
8005 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
8009 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
8013 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
8017 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
8021 /* This loop will early-out if the link condition has been met. */
8022 for (i = PHY_FORCE_TIME; i > 0; i--) {
8023 /* Read the MII Status Register and wait for Link Status bit
8027 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8031 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8035 if (mii_status_reg & MII_SR_LINK_STATUS) break;
8036 msec_delay_irq(100);
8038 return E1000_SUCCESS;
8041 /***************************************************************************
8043 * Disables PCI-Express master access.
8045 * hw: Struct containing variables accessed by shared code
8049 ***************************************************************************/
8051 em_set_pci_express_master_disable(struct em_hw *hw)
8055 DEBUGFUNC("em_set_pci_express_master_disable");
8057 if (hw->bus_type != em_bus_type_pci_express)
8060 ctrl = E1000_READ_REG(hw, CTRL);
8061 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
8062 E1000_WRITE_REG(hw, CTRL, ctrl);
8065 /*******************************************************************************
8067 * Disables PCI-Express master access and verifies there are no pending requests
8069 * hw: Struct containing variables accessed by shared code
8071 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
8072 * caused the master requests to be disabled.
8073 * E1000_SUCCESS master requests disabled.
8075 ******************************************************************************/
8077 em_disable_pciex_master(struct em_hw *hw)
8079 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
8081 DEBUGFUNC("em_disable_pciex_master");
8083 if (hw->bus_type != em_bus_type_pci_express)
8084 return E1000_SUCCESS;
8086 em_set_pci_express_master_disable(hw);
8089 if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
8097 DEBUGOUT("Master requests are pending.\n");
8098 return -E1000_ERR_MASTER_REQUESTS_PENDING;
8101 return E1000_SUCCESS;
8104 /*******************************************************************************
8106 * Check for EEPROM Auto Read bit done.
8108 * hw: Struct containing variables accessed by shared code
8110 * returns: - E1000_ERR_RESET if fail to reset MAC
8111 * E1000_SUCCESS at any other case.
8113 ******************************************************************************/
8115 em_get_auto_rd_done(struct em_hw *hw)
8117 int32_t timeout = AUTO_READ_DONE_TIMEOUT;
8119 DEBUGFUNC("em_get_auto_rd_done");
8121 switch (hw->mac_type) {
8128 case em_80003es2lan:
8131 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
8138 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
8139 return -E1000_ERR_RESET;
8144 /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high.
8145 * Need to wait for PHY configuration completion before accessing NVM
8147 if (hw->mac_type == em_82573)
8150 return E1000_SUCCESS;
8153 /***************************************************************************
8154 * Checks if the PHY configuration is done
8156 * hw: Struct containing variables accessed by shared code
8158 * returns: - E1000_ERR_RESET if fail to reset MAC
8159 * E1000_SUCCESS at any other case.
8161 ***************************************************************************/
8163 em_get_phy_cfg_done(struct em_hw *hw)
8165 int32_t timeout = PHY_CFG_TIMEOUT;
8166 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
8168 DEBUGFUNC("em_get_phy_cfg_done");
8170 switch (hw->mac_type) {
8174 case em_80003es2lan:
8175 /* Separate *_CFG_DONE_* bit for each port */
8176 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
8177 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
8182 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
8189 DEBUGOUT("MNG configuration cycle has not completed.\n");
8190 return -E1000_ERR_RESET;
8195 return E1000_SUCCESS;
8198 /***************************************************************************
8200 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
8201 * adapter or Eeprom access.
8203 * hw: Struct containing variables accessed by shared code
8205 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
8206 * E1000_SUCCESS at any other case.
8208 ***************************************************************************/
8210 em_get_hw_eeprom_semaphore(struct em_hw *hw)
8215 DEBUGFUNC("em_get_hw_eeprom_semaphore");
8217 if (!hw->eeprom_semaphore_present)
8218 return E1000_SUCCESS;
8220 if (hw->mac_type == em_80003es2lan) {
8221 /* Get the SW semaphore. */
8222 if (em_get_software_semaphore(hw) != E1000_SUCCESS)
8223 return -E1000_ERR_EEPROM;
8226 /* Get the FW semaphore. */
8227 timeout = hw->eeprom.word_size + 1;
8229 swsm = E1000_READ_REG(hw, SWSM);
8230 swsm |= E1000_SWSM_SWESMBI;
8231 E1000_WRITE_REG(hw, SWSM, swsm);
8232 /* if we managed to set the bit we got the semaphore. */
8233 swsm = E1000_READ_REG(hw, SWSM);
8234 if (swsm & E1000_SWSM_SWESMBI)
8242 /* Release semaphores */
8243 em_put_hw_eeprom_semaphore(hw);
8244 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
8245 return -E1000_ERR_EEPROM;
8248 return E1000_SUCCESS;
8251 /***************************************************************************
8252 * This function clears HW semaphore bits.
8254 * hw: Struct containing variables accessed by shared code
8258 ***************************************************************************/
8260 em_put_hw_eeprom_semaphore(struct em_hw *hw)
8264 DEBUGFUNC("em_put_hw_eeprom_semaphore");
8266 if (!hw->eeprom_semaphore_present)
8269 swsm = E1000_READ_REG(hw, SWSM);
8270 if (hw->mac_type == em_80003es2lan) {
8271 /* Release both semaphores. */
8272 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
8274 swsm &= ~(E1000_SWSM_SWESMBI);
8275 E1000_WRITE_REG(hw, SWSM, swsm);
8278 /***************************************************************************
8280 * Obtaining software semaphore bit (SMBI) before resetting PHY.
8282 * hw: Struct containing variables accessed by shared code
8284 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
8285 * E1000_SUCCESS at any other case.
8287 ***************************************************************************/
8289 em_get_software_semaphore(struct em_hw *hw)
8291 int32_t timeout = hw->eeprom.word_size + 1;
8294 DEBUGFUNC("em_get_software_semaphore");
8296 if (hw->mac_type != em_80003es2lan) {
8297 return E1000_SUCCESS;
8301 swsm = E1000_READ_REG(hw, SWSM);
8302 /* If SMBI bit cleared, it is now set and we hold the semaphore */
8303 if (!(swsm & E1000_SWSM_SMBI))
8310 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
8311 return -E1000_ERR_RESET;
8314 return E1000_SUCCESS;
8317 /***************************************************************************
8319 * Release semaphore bit (SMBI).
8321 * hw: Struct containing variables accessed by shared code
8323 ***************************************************************************/
8325 em_release_software_semaphore(struct em_hw *hw)
8329 DEBUGFUNC("em_release_software_semaphore");
8331 if (hw->mac_type != em_80003es2lan) {
8335 swsm = E1000_READ_REG(hw, SWSM);
8336 /* Release the SW semaphores.*/
8337 swsm &= ~E1000_SWSM_SMBI;
8338 E1000_WRITE_REG(hw, SWSM, swsm);
8341 /******************************************************************************
8342 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
8343 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
8344 * the caller to figure out how to deal with it.
8346 * hw - Struct containing variables accessed by shared code
8348 * returns: - E1000_BLK_PHY_RESET
8351 *****************************************************************************/
8353 em_check_phy_reset_block(struct em_hw *hw)
8358 if (hw->mac_type == em_ich8lan) {
8359 fwsm = E1000_READ_REG(hw, FWSM);
8360 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
8361 : E1000_BLK_PHY_RESET;
8364 if (hw->mac_type > em_82547_rev_2)
8365 manc = E1000_READ_REG(hw, MANC);
8366 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
8367 E1000_BLK_PHY_RESET : E1000_SUCCESS;
8371 em_arc_subsystem_valid(struct em_hw *hw)
8375 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
8376 * may not be provided a DMA clock when no manageability features are
8377 * enabled. We do not want to perform any reads/writes to these registers
8378 * if this is the case. We read FWSM to determine the manageability mode.
8380 switch (hw->mac_type) {
8384 case em_80003es2lan:
8385 fwsm = E1000_READ_REG(hw, FWSM);
8386 if ((fwsm & E1000_FWSM_MODE_MASK) != 0)
8398 /******************************************************************************
8399 * Configure PCI-Ex no-snoop
8401 * hw - Struct containing variables accessed by shared code.
8402 * no_snoop - Bitmap of no-snoop events.
8404 * returns: E1000_SUCCESS
8406 *****************************************************************************/
8408 em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop)
8410 uint32_t gcr_reg = 0;
8412 DEBUGFUNC("em_set_pci_ex_no_snoop");
8414 if (hw->bus_type == em_bus_type_unknown)
8415 em_get_bus_info(hw);
8417 if (hw->bus_type != em_bus_type_pci_express)
8418 return E1000_SUCCESS;
8421 gcr_reg = E1000_READ_REG(hw, GCR);
8422 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
8423 gcr_reg |= no_snoop;
8424 E1000_WRITE_REG(hw, GCR, gcr_reg);
8426 if (hw->mac_type == em_ich8lan) {
8429 E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL);
8431 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
8432 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
8433 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
8436 return E1000_SUCCESS;
8439 /***************************************************************************
8441 * Get software semaphore FLAG bit (SWFLAG).
8442 * SWFLAG is used to synchronize the access to all shared resource between
8445 * hw: Struct containing variables accessed by shared code
8447 ***************************************************************************/
8449 em_get_software_flag(struct em_hw *hw)
8451 int32_t timeout = PHY_CFG_TIMEOUT;
8452 uint32_t extcnf_ctrl;
8454 DEBUGFUNC("em_get_software_flag");
8456 if (hw->mac_type == em_ich8lan) {
8458 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8459 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
8460 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8462 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8463 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
8470 DEBUGOUT("FW or HW locks the resource too long.\n");
8471 return -E1000_ERR_CONFIG;
8475 return E1000_SUCCESS;
8478 /***************************************************************************
8480 * Release software semaphore FLAG bit (SWFLAG).
8481 * SWFLAG is used to synchronize the access to all shared resource between
8484 * hw: Struct containing variables accessed by shared code
8486 ***************************************************************************/
8488 em_release_software_flag(struct em_hw *hw)
8490 uint32_t extcnf_ctrl;
8492 DEBUGFUNC("em_release_software_flag");
8494 if (hw->mac_type == em_ich8lan) {
8495 extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL);
8496 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
8497 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8504 /******************************************************************************
8505 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
8508 * hw - Struct containing variables accessed by shared code
8509 * offset - offset of word in the EEPROM to read
8510 * data - word read from the EEPROM
8511 * words - number of words to read
8512 *****************************************************************************/
8514 em_read_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words,
8517 int32_t error = E1000_SUCCESS;
8518 uint32_t flash_bank = 0;
8519 uint32_t act_offset = 0;
8520 uint32_t bank_offset = 0;
8524 /* We need to know which is the valid flash bank. In the event
8525 * that we didn't allocate eeprom_shadow_ram, we may not be
8526 * managing flash_bank. So it cannot be trusted and needs
8527 * to be updated with each read.
8529 /* Value of bit 22 corresponds to the flash bank we're on. */
8530 flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
8532 /* Adjust offset appropriately if we're on bank 1 - adjust for word size */
8533 bank_offset = flash_bank * (hw->flash_bank_size * 2);
8535 error = em_get_software_flag(hw);
8536 if (error != E1000_SUCCESS)
8539 for (i = 0; i < words; i++) {
8540 if (hw->eeprom_shadow_ram != NULL &&
8541 hw->eeprom_shadow_ram[offset+i].modified == TRUE) {
8542 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
8544 /* The NVM part needs a byte offset, hence * 2 */
8545 act_offset = bank_offset + ((offset + i) * 2);
8546 error = em_read_ich8_word(hw, act_offset, &word);
8547 if (error != E1000_SUCCESS)
8553 em_release_software_flag(hw);
8558 /******************************************************************************
8559 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
8560 * register. Actually, writes are written to the shadow ram cache in the hw
8561 * structure hw->em_shadow_ram. em_commit_shadow_ram flushes this to
8562 * the NVM, which occurs when the NVM checksum is updated.
8564 * hw - Struct containing variables accessed by shared code
8565 * offset - offset of word in the EEPROM to write
8566 * words - number of words to write
8567 * data - words to write to the EEPROM
8568 *****************************************************************************/
8570 em_write_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words,
8574 int32_t error = E1000_SUCCESS;
8576 error = em_get_software_flag(hw);
8577 if (error != E1000_SUCCESS)
8580 /* A driver can write to the NVM only if it has eeprom_shadow_ram
8581 * allocated. Subsequent reads to the modified words are read from
8582 * this cached structure as well. Writes will only go into this
8583 * cached structure unless it's followed by a call to
8584 * em_update_eeprom_checksum() where it will commit the changes
8585 * and clear the "modified" field.
8587 if (hw->eeprom_shadow_ram != NULL) {
8588 for (i = 0; i < words; i++) {
8589 if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
8590 hw->eeprom_shadow_ram[offset+i].modified = TRUE;
8591 hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
8593 error = -E1000_ERR_EEPROM;
8598 /* Drivers have the option to not allocate eeprom_shadow_ram as long
8599 * as they don't perform any NVM writes. An attempt in doing so
8600 * will result in this error.
8602 error = -E1000_ERR_EEPROM;
8605 em_release_software_flag(hw);
8610 /******************************************************************************
8611 * This function does initial flash setup so that a new read/write/erase cycle
8614 * hw - The pointer to the hw structure
8615 ****************************************************************************/
8617 em_ich8_cycle_init(struct em_hw *hw)
8619 union ich8_hws_flash_status hsfsts;
8620 int32_t error = E1000_ERR_EEPROM;
8623 DEBUGFUNC("em_ich8_cycle_init");
8625 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8627 /* May be check the Flash Des Valid bit in Hw status */
8628 if (hsfsts.hsf_status.fldesvalid == 0) {
8629 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.");
8633 /* Clear FCERR in Hw status by writing 1 */
8634 /* Clear DAEL in Hw status by writing a 1 */
8635 hsfsts.hsf_status.flcerr = 1;
8636 hsfsts.hsf_status.dael = 1;
8638 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8640 /* Either we should have a hardware SPI cycle in progress bit to check
8641 * against, in order to start a new cycle or FDONE bit should be changed
8642 * in the hardware so that it is 1 after harware reset, which can then be
8643 * used as an indication whether a cycle is in progress or has been
8644 * completed .. we should also have some software semaphore mechanism to
8645 * guard FDONE or the cycle in progress bit so that two threads access to
8646 * those bits can be sequentiallized or a way so that 2 threads dont
8647 * start the cycle at the same time */
8649 if (hsfsts.hsf_status.flcinprog == 0) {
8650 /* There is no cycle running at present, so we can start a cycle */
8651 /* Begin by setting Flash Cycle Done. */
8652 hsfsts.hsf_status.flcdone = 1;
8653 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8654 error = E1000_SUCCESS;
8656 /* otherwise poll for sometime so the current cycle has a chance
8657 * to end before giving up. */
8658 for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) {
8659 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8660 if (hsfsts.hsf_status.flcinprog == 0) {
8661 error = E1000_SUCCESS;
8666 if (error == E1000_SUCCESS) {
8667 /* Successful in waiting for previous cycle to timeout,
8668 * now set the Flash Cycle Done. */
8669 hsfsts.hsf_status.flcdone = 1;
8670 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8672 DEBUGOUT("Flash controller busy, cannot get access");
8678 /******************************************************************************
8679 * This function starts a flash cycle and waits for its completion
8681 * hw - The pointer to the hw structure
8682 ****************************************************************************/
8684 em_ich8_flash_cycle(struct em_hw *hw, uint32_t timeout)
8686 union ich8_hws_flash_ctrl hsflctl;
8687 union ich8_hws_flash_status hsfsts;
8688 int32_t error = E1000_ERR_EEPROM;
8691 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
8692 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8693 hsflctl.hsf_ctrl.flcgo = 1;
8694 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8696 /* wait till FDONE bit is set to 1 */
8698 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8699 if (hsfsts.hsf_status.flcdone == 1)
8703 } while (i < timeout);
8704 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
8705 error = E1000_SUCCESS;
8710 /******************************************************************************
8711 * Reads a byte or word from the NVM using the ICH8 flash access registers.
8713 * hw - The pointer to the hw structure
8714 * index - The index of the byte or word to read.
8715 * size - Size of data to read, 1=byte 2=word
8716 * data - Pointer to the word to store the value read.
8717 *****************************************************************************/
8719 em_read_ich8_data(struct em_hw *hw, uint32_t index,
8720 uint32_t size, uint16_t* data)
8722 union ich8_hws_flash_status hsfsts;
8723 union ich8_hws_flash_ctrl hsflctl;
8724 uint32_t flash_linear_address;
8725 uint32_t flash_data = 0;
8726 int32_t error = -E1000_ERR_EEPROM;
8729 DEBUGFUNC("em_read_ich8_data");
8731 if (size < 1 || size > 2 || data == 0x0 ||
8732 index > ICH_FLASH_LINEAR_ADDR_MASK)
8735 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
8736 hw->flash_base_addr;
8741 error = em_ich8_cycle_init(hw);
8742 if (error != E1000_SUCCESS)
8745 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8746 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8747 hsflctl.hsf_ctrl.fldbcount = size - 1;
8748 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
8749 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8751 /* Write the last 24 bits of index into Flash Linear address field in
8753 /* TODO: TBD maybe check the index against the size of flash */
8755 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8757 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
8759 /* Check if FCERR is set to 1, if set to 1, clear it and try the whole
8760 * sequence a few more times, else read in (shift in) the Flash Data0,
8761 * the order is least significant byte first msb to lsb */
8762 if (error == E1000_SUCCESS) {
8763 flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0);
8765 *data = (uint8_t)(flash_data & 0x000000FF);
8766 } else if (size == 2) {
8767 *data = (uint16_t)(flash_data & 0x0000FFFF);
8771 /* If we've gotten here, then things are probably completely hosed,
8772 * but if the error condition is detected, it won't hurt to give
8773 * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
8775 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8776 if (hsfsts.hsf_status.flcerr == 1) {
8777 /* Repeat for some time before giving up. */
8779 } else if (hsfsts.hsf_status.flcdone == 0) {
8780 DEBUGOUT("Timeout error - flash cycle did not complete.");
8784 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
8789 /******************************************************************************
8790 * Writes One /two bytes to the NVM using the ICH8 flash access registers.
8792 * hw - The pointer to the hw structure
8793 * index - The index of the byte/word to read.
8794 * size - Size of data to read, 1=byte 2=word
8795 * data - The byte(s) to write to the NVM.
8796 *****************************************************************************/
8798 em_write_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size,
8801 union ich8_hws_flash_status hsfsts;
8802 union ich8_hws_flash_ctrl hsflctl;
8803 uint32_t flash_linear_address;
8804 uint32_t flash_data = 0;
8805 int32_t error = -E1000_ERR_EEPROM;
8808 DEBUGFUNC("em_write_ich8_data");
8810 if (size < 1 || size > 2 || data > size * 0xff ||
8811 index > ICH_FLASH_LINEAR_ADDR_MASK)
8814 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
8815 hw->flash_base_addr;
8820 error = em_ich8_cycle_init(hw);
8821 if (error != E1000_SUCCESS)
8824 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8825 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8826 hsflctl.hsf_ctrl.fldbcount = size -1;
8827 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
8828 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8830 /* Write the last 24 bits of index into Flash Linear address field in
8832 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8835 flash_data = (uint32_t)data & 0x00FF;
8837 flash_data = (uint32_t)data;
8839 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
8841 /* check if FCERR is set to 1 , if set to 1, clear it and try the whole
8842 * sequence a few more times else done */
8843 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
8844 if (error == E1000_SUCCESS) {
8847 /* If we're here, then things are most likely completely hosed,
8848 * but if the error condition is detected, it won't hurt to give
8849 * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
8851 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8852 if (hsfsts.hsf_status.flcerr == 1) {
8853 /* Repeat for some time before giving up. */
8855 } else if (hsfsts.hsf_status.flcdone == 0) {
8856 DEBUGOUT("Timeout error - flash cycle did not complete.");
8860 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
8865 /******************************************************************************
8866 * Reads a single byte from the NVM using the ICH8 flash access registers.
8868 * hw - pointer to em_hw structure
8869 * index - The index of the byte to read.
8870 * data - Pointer to a byte to store the value read.
8871 *****************************************************************************/
8873 em_read_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t* data)
8875 int32_t status = E1000_SUCCESS;
8878 status = em_read_ich8_data(hw, index, 1, &word);
8879 if (status == E1000_SUCCESS) {
8880 *data = (uint8_t)word;
8886 /******************************************************************************
8887 * Writes a single byte to the NVM using the ICH8 flash access registers.
8888 * Performs verification by reading back the value and then going through
8889 * a retry algorithm before giving up.
8891 * hw - pointer to em_hw structure
8892 * index - The index of the byte to write.
8893 * byte - The byte to write to the NVM.
8894 *****************************************************************************/
8896 em_verify_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t byte)
8898 int32_t error = E1000_SUCCESS;
8899 int32_t program_retries = 0;
8901 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index);
8903 error = em_write_ich8_byte(hw, index, byte);
8905 if (error != E1000_SUCCESS) {
8906 for (program_retries = 0; program_retries < 100; program_retries++) {
8907 DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", byte, index);
8908 error = em_write_ich8_byte(hw, index, byte);
8910 if (error == E1000_SUCCESS)
8915 if (program_retries == 100)
8916 error = E1000_ERR_EEPROM;
8921 /******************************************************************************
8922 * Writes a single byte to the NVM using the ICH8 flash access registers.
8924 * hw - pointer to em_hw structure
8925 * index - The index of the byte to read.
8926 * data - The byte to write to the NVM.
8927 *****************************************************************************/
8929 em_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t data)
8931 int32_t status = E1000_SUCCESS;
8932 uint16_t word = (uint16_t)data;
8934 status = em_write_ich8_data(hw, index, 1, word);
8939 /******************************************************************************
8940 * Reads a word from the NVM using the ICH8 flash access registers.
8942 * hw - pointer to em_hw structure
8943 * index - The starting byte index of the word to read.
8944 * data - Pointer to a word to store the value read.
8945 *****************************************************************************/
8947 em_read_ich8_word(struct em_hw *hw, uint32_t index, uint16_t *data)
8949 int32_t status = E1000_SUCCESS;
8950 status = em_read_ich8_data(hw, index, 2, data);
8955 /******************************************************************************
8956 * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0
8959 * hw - pointer to em_hw structure
8960 * bank - 0 for first bank, 1 for second bank
8962 * Note that this function may actually erase as much as 8 or 64 KBytes. The
8963 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the
8964 * bank size may be 4, 8 or 64 KBytes
8965 *****************************************************************************/
8967 em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t bank)
8969 union ich8_hws_flash_status hsfsts;
8970 union ich8_hws_flash_ctrl hsflctl;
8971 uint32_t flash_linear_address;
8973 int32_t error = E1000_ERR_EEPROM;
8975 int32_t sub_sector_size = 0;
8978 int32_t error_flag = 0;
8980 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8982 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
8983 /* 00: The Hw sector is 256 bytes, hence we need to erase 16
8984 * consecutive sectors. The start index for the nth Hw sector can be
8985 * calculated as bank * 4096 + n * 256
8986 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
8987 * The start index for the nth Hw sector can be calculated
8989 * 10: The HW sector is 8K bytes
8990 * 11: The Hw sector size is 64K bytes */
8991 if (hsfsts.hsf_status.berasesz == 0x0) {
8992 /* Hw sector size 256 */
8993 sub_sector_size = ICH_FLASH_SEG_SIZE_256;
8994 bank_size = ICH_FLASH_SECTOR_SIZE;
8995 iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256;
8996 } else if (hsfsts.hsf_status.berasesz == 0x1) {
8997 bank_size = ICH_FLASH_SEG_SIZE_4K;
8999 } else if (hsfsts.hsf_status.berasesz == 0x3) {
9000 bank_size = ICH_FLASH_SEG_SIZE_64K;
9006 for (j = 0; j < iteration ; j++) {
9010 error = em_ich8_cycle_init(hw);
9011 if (error != E1000_SUCCESS) {
9016 /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash
9018 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
9019 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
9020 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
9022 /* Write the last 24 bits of an index within the block into Flash
9023 * Linear address field in Flash Address. This probably needs to
9024 * be calculated here based off the on-chip erase sector size and
9025 * the software bank size (4, 8 or 64 KBytes) */
9026 flash_linear_address = bank * bank_size + j * sub_sector_size;
9027 flash_linear_address += hw->flash_base_addr;
9028 flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK;
9030 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
9032 error = em_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT);
9033 /* Check if FCERR is set to 1. If 1, clear it and try the whole
9034 * sequence a few more times else Done */
9035 if (error == E1000_SUCCESS) {
9038 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
9039 if (hsfsts.hsf_status.flcerr == 1) {
9040 /* repeat for some time before giving up */
9042 } else if (hsfsts.hsf_status.flcdone == 0) {
9047 } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
9048 if (error_flag == 1)
9051 if (error_flag != 1)
9052 error = E1000_SUCCESS;
9058 em_init_lcd_from_nvm_config_region(struct em_hw *hw,
9059 uint32_t cnf_base_addr, uint32_t cnf_size)
9061 uint32_t ret_val = E1000_SUCCESS;
9062 uint16_t word_addr, reg_data, reg_addr;
9065 /* cnf_base_addr is in DWORD */
9066 word_addr = (uint16_t)(cnf_base_addr << 1);
9068 /* cnf_size is returned in size of dwords */
9069 for (i = 0; i < cnf_size; i++) {
9070 ret_val = em_read_eeprom(hw, (word_addr + i*2), 1, ®_data);
9074 ret_val = em_read_eeprom(hw, (word_addr + i*2 + 1), 1, ®_addr);
9078 ret_val = em_get_software_flag(hw);
9079 if (ret_val != E1000_SUCCESS)
9082 ret_val = em_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data);
9084 em_release_software_flag(hw);
9091 /******************************************************************************
9092 * This function initializes the PHY from the NVM on ICH8 platforms. This
9093 * is needed due to an issue where the NVM configuration is not properly
9094 * autoloaded after power transitions. Therefore, after each PHY reset, we
9095 * will load the configuration data out of the NVM manually.
9097 * hw: Struct containing variables accessed by shared code
9098 *****************************************************************************/
9100 em_init_lcd_from_nvm(struct em_hw *hw)
9102 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop;
9104 if (hw->phy_type != em_phy_igp_3)
9105 return E1000_SUCCESS;
9107 /* Check if SW needs configure the PHY */
9108 reg_data = E1000_READ_REG(hw, FEXTNVM);
9109 if (!(reg_data & FEXTNVM_SW_CONFIG))
9110 return E1000_SUCCESS;
9112 /* Wait for basic configuration completes before proceeding*/
9115 reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE;
9118 } while ((!reg_data) && (loop < 50));
9120 /* Clear the Init Done bit for the next init event */
9121 reg_data = E1000_READ_REG(hw, STATUS);
9122 reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
9123 E1000_WRITE_REG(hw, STATUS, reg_data);
9125 /* Make sure HW does not configure LCD from PHY extended configuration
9126 before SW configuration */
9127 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9128 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
9129 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE);
9130 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
9133 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9134 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
9135 /* cnf_base_addr is in DWORD */
9136 cnf_base_addr >>= 16;
9138 /* Configure LCD from extended configuration region. */
9139 ret_val = em_init_lcd_from_nvm_config_region(hw, cnf_base_addr,
9146 return E1000_SUCCESS;