1 /* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
37 /* Define the specific costs for a given cpu */
39 struct processor_costs {
40 const int add; /* cost of an add instruction */
41 const int lea; /* cost of a lea instruction */
42 const int shift_var; /* variable shift costs */
43 const int shift_const; /* constant shift costs */
44 const int mult_init[5]; /* cost of starting a multiply
45 in QImode, HImode, SImode, DImode, TImode*/
46 const int mult_bit; /* cost of multiply per each bit set */
47 const int divide[5]; /* cost of a divide/mod
48 in QImode, HImode, SImode, DImode, TImode*/
49 int movsx; /* The cost of movsx operation. */
50 int movzx; /* The cost of movzx operation. */
51 const int large_insn; /* insns larger than this cost more */
52 const int move_ratio; /* The threshold of number of scalar
53 memory-to-memory move insns. */
54 const int movzbl_load; /* cost of loading using movzbl */
55 const int int_load[3]; /* cost of loading integer registers
56 in QImode, HImode and SImode relative
57 to reg-reg move (2). */
58 const int int_store[3]; /* cost of storing integer register
59 in QImode, HImode and SImode */
60 const int fp_move; /* cost of reg,reg fld/fst */
61 const int fp_load[3]; /* cost of loading FP register
62 in SFmode, DFmode and XFmode */
63 const int fp_store[3]; /* cost of storing FP register
64 in SFmode, DFmode and XFmode */
65 const int mmx_move; /* cost of moving MMX register. */
66 const int mmx_load[2]; /* cost of loading MMX register
67 in SImode and DImode */
68 const int mmx_store[2]; /* cost of storing MMX register
69 in SImode and DImode */
70 const int sse_move; /* cost of moving SSE register. */
71 const int sse_load[3]; /* cost of loading SSE register
72 in SImode, DImode and TImode*/
73 const int sse_store[3]; /* cost of storing SSE register
74 in SImode, DImode and TImode*/
75 const int mmxsse_to_integer; /* cost of moving mmxsse register to
76 integer and vice versa. */
77 const int prefetch_block; /* bytes moved to cache for prefetch. */
78 const int simultaneous_prefetches; /* number of parallel prefetch
80 const int branch_cost; /* Default value for BRANCH_COST. */
81 const int fadd; /* cost of FADD and FSUB instructions. */
82 const int fmul; /* cost of FMUL instruction. */
83 const int fdiv; /* cost of FDIV instruction. */
84 const int fabs; /* cost of FABS instruction. */
85 const int fchs; /* cost of FCHS instruction. */
86 const int fsqrt; /* cost of FSQRT instruction. */
89 extern const struct processor_costs *ix86_cost;
91 /* Macros used in the machine description to test the flags. */
93 /* configure can arrange to make this 2, to force a 486. */
95 #ifndef TARGET_CPU_DEFAULT
96 #ifdef TARGET_64BIT_DEFAULT
97 #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_k8
99 #define TARGET_CPU_DEFAULT 0
103 #ifndef TARGET_FPMATH_DEFAULT
104 #define TARGET_FPMATH_DEFAULT \
105 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
108 #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS
110 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
111 compile-time constant. */
115 #define TARGET_64BIT 1
117 #define TARGET_64BIT 0
120 #ifndef TARGET_BI_ARCH
122 #if TARGET_64BIT_DEFAULT
123 #define TARGET_64BIT 1
125 #define TARGET_64BIT 0
130 #define HAS_LONG_COND_BRANCH 1
131 #define HAS_LONG_UNCOND_BRANCH 1
133 #define TARGET_386 (ix86_tune == PROCESSOR_I386)
134 #define TARGET_486 (ix86_tune == PROCESSOR_I486)
135 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
136 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
137 #define TARGET_K6 (ix86_tune == PROCESSOR_K6)
138 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
139 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
140 #define TARGET_K8 (ix86_tune == PROCESSOR_K8)
141 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
142 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
144 #define TUNEMASK (1 << ix86_tune)
145 extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
146 extern const int x86_use_bit_test, x86_cmove, x86_fisttp, x86_deep_branch;
147 extern const int x86_branch_hints, x86_unroll_strlen;
148 extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
149 extern const int x86_use_himode_fiop, x86_use_simode_fiop;
150 extern const int x86_use_mov0, x86_use_cltd, x86_read_modify_write;
151 extern const int x86_read_modify, x86_split_long_moves;
152 extern const int x86_promote_QImode, x86_single_stringop, x86_fast_prefix;
153 extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs;
154 extern const int x86_promote_hi_regs, x86_integer_DFmode_moves;
155 extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8;
156 extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
157 extern const int x86_accumulate_outgoing_args, x86_prologue_using_move;
158 extern const int x86_epilogue_using_move, x86_decompose_lea;
159 extern const int x86_arch_always_fancy_math_387, x86_shift1;
160 extern const int x86_sse_partial_reg_dependency, x86_sse_split_regs;
161 extern const int x86_sse_typeless_stores, x86_sse_load0_by_pxor;
162 extern const int x86_use_ffreep;
163 extern const int x86_inter_unit_moves, x86_schedule;
164 extern const int x86_use_bt;
165 extern const int x86_cmpxchg, x86_xadd;
166 extern int x86_prefetch_sse;
168 #define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK)
169 #define TARGET_PUSH_MEMORY (x86_push_memory & TUNEMASK)
170 #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & TUNEMASK)
171 #define TARGET_USE_BIT_TEST (x86_use_bit_test & TUNEMASK)
172 #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & TUNEMASK)
173 /* For sane SSE instruction set generation we need fcomi instruction. It is
174 safe to enable all CMOVE instructions. */
175 #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
176 #define TARGET_FISTTP (((x86_fisttp & (1 << ix86_arch)) || TARGET_SSE3) \
178 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & TUNEMASK)
179 #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & TUNEMASK)
180 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & TUNEMASK)
181 #define TARGET_USE_SAHF ((x86_use_sahf & TUNEMASK) && !TARGET_64BIT)
182 #define TARGET_MOVX (x86_movx & TUNEMASK)
183 #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & TUNEMASK)
184 #define TARGET_USE_HIMODE_FIOP (x86_use_himode_fiop & TUNEMASK)
185 #define TARGET_USE_SIMODE_FIOP (x86_use_simode_fiop & TUNEMASK)
186 #define TARGET_USE_MOV0 (x86_use_mov0 & TUNEMASK)
187 #define TARGET_USE_CLTD (x86_use_cltd & TUNEMASK)
188 #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & TUNEMASK)
189 #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & TUNEMASK)
190 #define TARGET_READ_MODIFY (x86_read_modify & TUNEMASK)
191 #define TARGET_PROMOTE_QImode (x86_promote_QImode & TUNEMASK)
192 #define TARGET_FAST_PREFIX (x86_fast_prefix & TUNEMASK)
193 #define TARGET_SINGLE_STRINGOP (x86_single_stringop & TUNEMASK)
194 #define TARGET_QIMODE_MATH (x86_qimode_math & TUNEMASK)
195 #define TARGET_HIMODE_MATH (x86_himode_math & TUNEMASK)
196 #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & TUNEMASK)
197 #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & TUNEMASK)
198 #define TARGET_ADD_ESP_4 (x86_add_esp_4 & TUNEMASK)
199 #define TARGET_ADD_ESP_8 (x86_add_esp_8 & TUNEMASK)
200 #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & TUNEMASK)
201 #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & TUNEMASK)
202 #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & TUNEMASK)
203 #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & TUNEMASK)
204 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
205 (x86_sse_partial_reg_dependency & TUNEMASK)
206 #define TARGET_SSE_SPLIT_REGS (x86_sse_split_regs & TUNEMASK)
207 #define TARGET_SSE_TYPELESS_STORES (x86_sse_typeless_stores & TUNEMASK)
208 #define TARGET_SSE_LOAD0_BY_PXOR (x86_sse_load0_by_pxor & TUNEMASK)
209 #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & TUNEMASK)
210 #define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & TUNEMASK)
211 #define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & TUNEMASK)
212 #define TARGET_DECOMPOSE_LEA (x86_decompose_lea & TUNEMASK)
213 #define TARGET_PREFETCH_SSE (x86_prefetch_sse)
214 #define TARGET_SHIFT1 (x86_shift1 & TUNEMASK)
215 #define TARGET_USE_FFREEP (x86_use_ffreep & TUNEMASK)
216 #define TARGET_REP_MOVL_OPTIMAL (x86_rep_movl_optimal & TUNEMASK)
217 #define TARGET_INTER_UNIT_MOVES (x86_inter_unit_moves & TUNEMASK)
218 #define TARGET_FOUR_JUMP_LIMIT (x86_four_jump_limit & TUNEMASK)
219 #define TARGET_SCHEDULE (x86_schedule & TUNEMASK)
220 #define TARGET_USE_BT (x86_use_bt & TUNEMASK)
222 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
224 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
225 #define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
226 && (ix86_fpmath & FPMATH_387))
228 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
229 #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
231 #define TARGET_CMPXCHG (x86_cmpxchg & (1 << ix86_arch))
232 #define TARGET_XADD (x86_xadd & (1 << ix86_arch))
234 #ifndef TARGET_64BIT_DEFAULT
235 #define TARGET_64BIT_DEFAULT 0
237 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
238 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
241 /* Once GDB has been enhanced to deal with functions without frame
242 pointers, we can change this to allow for elimination of
243 the frame pointer in leaf functions. */
244 #define TARGET_DEFAULT 0
246 /* This is not really a target flag, but is done this way so that
247 it's analogous to similar code for Mach-O on PowerPC. darwin.h
248 redefines this to 1. */
249 #define TARGET_MACHO 0
251 /* Subtargets may reset this to 1 in order to enable 96-bit long double
252 with the rounding mode forced to 53 bits. */
253 #define TARGET_96_ROUND_53_LONG_DOUBLE 0
255 /* Sometimes certain combinations of command options do not make
256 sense on a particular target machine. You can define a macro
257 `OVERRIDE_OPTIONS' to take account of this. This macro, if
258 defined, is executed once just after all the command options have
261 Don't use this macro to turn on various extra optimizations for
262 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
264 #define OVERRIDE_OPTIONS override_options ()
266 /* Define this to change the optimizations performed by default. */
267 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
268 optimization_options ((LEVEL), (SIZE))
270 /* Support for configure-time defaults of some command line options. */
271 #define OPTION_DEFAULT_SPECS \
272 {"arch", "%{!march=*:-march=%(VALUE)}"}, \
273 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
274 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }
276 /* Specs for the compiler proper */
279 #define CC1_CPU_SPEC "\
282 %n`-m386' is deprecated. Use `-march=i386' or `-mtune=i386' instead.\n} \
284 %n`-m486' is deprecated. Use `-march=i486' or `-mtune=i486' instead.\n} \
285 %{mpentium:-mtune=pentium \
286 %n`-mpentium' is deprecated. Use `-march=pentium' or `-mtune=pentium' instead.\n} \
287 %{mpentiumpro:-mtune=pentiumpro \
288 %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mtune=pentiumpro' instead.\n} \
290 %n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n}} \
292 %{mintel-syntax:-masm=intel \
293 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
294 %{mno-intel-syntax:-masm=att \
295 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
298 /* Target CPU builtins. */
299 #define TARGET_CPU_CPP_BUILTINS() \
302 size_t arch_len = strlen (ix86_arch_string); \
303 size_t tune_len = strlen (ix86_tune_string); \
304 int last_arch_char = ix86_arch_string[arch_len - 1]; \
305 int last_tune_char = ix86_tune_string[tune_len - 1]; \
309 builtin_assert ("cpu=x86_64"); \
310 builtin_assert ("machine=x86_64"); \
311 builtin_define ("__amd64"); \
312 builtin_define ("__amd64__"); \
313 builtin_define ("__x86_64"); \
314 builtin_define ("__x86_64__"); \
318 builtin_assert ("cpu=i386"); \
319 builtin_assert ("machine=i386"); \
320 builtin_define_std ("i386"); \
323 /* Built-ins based on -mtune= (or -march= if no \
326 builtin_define ("__tune_i386__"); \
327 else if (TARGET_486) \
328 builtin_define ("__tune_i486__"); \
329 else if (TARGET_PENTIUM) \
331 builtin_define ("__tune_i586__"); \
332 builtin_define ("__tune_pentium__"); \
333 if (last_tune_char == 'x') \
334 builtin_define ("__tune_pentium_mmx__"); \
336 else if (TARGET_PENTIUMPRO) \
338 builtin_define ("__tune_i686__"); \
339 builtin_define ("__tune_pentiumpro__"); \
340 switch (last_tune_char) \
343 builtin_define ("__tune_pentium3__"); \
346 builtin_define ("__tune_pentium2__"); \
350 else if (TARGET_K6) \
352 builtin_define ("__tune_k6__"); \
353 if (last_tune_char == '2') \
354 builtin_define ("__tune_k6_2__"); \
355 else if (last_tune_char == '3') \
356 builtin_define ("__tune_k6_3__"); \
358 else if (TARGET_ATHLON) \
360 builtin_define ("__tune_athlon__"); \
361 /* Only plain "athlon" lacks SSE. */ \
362 if (last_tune_char != 'n') \
363 builtin_define ("__tune_athlon_sse__"); \
365 else if (TARGET_K8) \
366 builtin_define ("__tune_k8__"); \
367 else if (TARGET_PENTIUM4) \
368 builtin_define ("__tune_pentium4__"); \
369 else if (TARGET_NOCONA) \
370 builtin_define ("__tune_nocona__"); \
373 builtin_define ("__MMX__"); \
375 builtin_define ("__3dNOW__"); \
376 if (TARGET_3DNOW_A) \
377 builtin_define ("__3dNOW_A__"); \
379 builtin_define ("__SSE__"); \
381 builtin_define ("__SSE2__"); \
383 builtin_define ("__SSE3__"); \
384 if (TARGET_SSE_MATH && TARGET_SSE) \
385 builtin_define ("__SSE_MATH__"); \
386 if (TARGET_SSE_MATH && TARGET_SSE2) \
387 builtin_define ("__SSE2_MATH__"); \
389 /* Built-ins based on -march=. */ \
390 if (ix86_arch == PROCESSOR_I486) \
392 builtin_define ("__i486"); \
393 builtin_define ("__i486__"); \
395 else if (ix86_arch == PROCESSOR_PENTIUM) \
397 builtin_define ("__i586"); \
398 builtin_define ("__i586__"); \
399 builtin_define ("__pentium"); \
400 builtin_define ("__pentium__"); \
401 if (last_arch_char == 'x') \
402 builtin_define ("__pentium_mmx__"); \
404 else if (ix86_arch == PROCESSOR_PENTIUMPRO) \
406 builtin_define ("__i686"); \
407 builtin_define ("__i686__"); \
408 builtin_define ("__pentiumpro"); \
409 builtin_define ("__pentiumpro__"); \
411 else if (ix86_arch == PROCESSOR_K6) \
414 builtin_define ("__k6"); \
415 builtin_define ("__k6__"); \
416 if (last_arch_char == '2') \
417 builtin_define ("__k6_2__"); \
418 else if (last_arch_char == '3') \
419 builtin_define ("__k6_3__"); \
421 else if (ix86_arch == PROCESSOR_ATHLON) \
423 builtin_define ("__athlon"); \
424 builtin_define ("__athlon__"); \
425 /* Only plain "athlon" lacks SSE. */ \
426 if (last_arch_char != 'n') \
427 builtin_define ("__athlon_sse__"); \
429 else if (ix86_arch == PROCESSOR_K8) \
431 builtin_define ("__k8"); \
432 builtin_define ("__k8__"); \
434 else if (ix86_arch == PROCESSOR_PENTIUM4) \
436 builtin_define ("__pentium4"); \
437 builtin_define ("__pentium4__"); \
439 else if (ix86_arch == PROCESSOR_NOCONA) \
441 builtin_define ("__nocona"); \
442 builtin_define ("__nocona__"); \
447 #define TARGET_CPU_DEFAULT_i386 0
448 #define TARGET_CPU_DEFAULT_i486 1
449 #define TARGET_CPU_DEFAULT_pentium 2
450 #define TARGET_CPU_DEFAULT_pentium_mmx 3
451 #define TARGET_CPU_DEFAULT_pentiumpro 4
452 #define TARGET_CPU_DEFAULT_pentium2 5
453 #define TARGET_CPU_DEFAULT_pentium3 6
454 #define TARGET_CPU_DEFAULT_pentium4 7
455 #define TARGET_CPU_DEFAULT_k6 8
456 #define TARGET_CPU_DEFAULT_k6_2 9
457 #define TARGET_CPU_DEFAULT_k6_3 10
458 #define TARGET_CPU_DEFAULT_athlon 11
459 #define TARGET_CPU_DEFAULT_athlon_sse 12
460 #define TARGET_CPU_DEFAULT_k8 13
461 #define TARGET_CPU_DEFAULT_pentium_m 14
462 #define TARGET_CPU_DEFAULT_prescott 15
463 #define TARGET_CPU_DEFAULT_nocona 16
465 #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
466 "pentiumpro", "pentium2", "pentium3", \
467 "pentium4", "k6", "k6-2", "k6-3",\
468 "athlon", "athlon-4", "k8", \
469 "pentium-m", "prescott", "nocona"}
472 #define CC1_SPEC "%(cc1_cpu) "
475 /* This macro defines names of additional specifications to put in the
476 specs that can be used in various specifications like CC1_SPEC. Its
477 definition is an initializer with a subgrouping for each command option.
479 Each subgrouping contains a string constant, that defines the
480 specification name, and a string constant that used by the GCC driver
483 Do not define this macro if it does not need to do anything. */
485 #ifndef SUBTARGET_EXTRA_SPECS
486 #define SUBTARGET_EXTRA_SPECS
489 #define EXTRA_SPECS \
490 { "cc1_cpu", CC1_CPU_SPEC }, \
491 SUBTARGET_EXTRA_SPECS
493 /* target machine storage layout */
495 #define LONG_DOUBLE_TYPE_SIZE 80
497 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the
498 FPU, assume that the fpcw is set to extended precision; when using
499 only SSE, rounding is correct; when using both SSE and the FPU,
500 the rounding precision is indeterminate, since either may be chosen
501 apparently at random. */
502 #define TARGET_FLT_EVAL_METHOD \
503 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)
505 #define SHORT_TYPE_SIZE 16
506 #define INT_TYPE_SIZE 32
507 #define FLOAT_TYPE_SIZE 32
508 #define LONG_TYPE_SIZE BITS_PER_WORD
509 #define DOUBLE_TYPE_SIZE 64
510 #define LONG_LONG_TYPE_SIZE 64
512 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
513 #define MAX_BITS_PER_WORD 64
515 #define MAX_BITS_PER_WORD 32
518 /* Define this if most significant byte of a word is the lowest numbered. */
519 /* That is true on the 80386. */
521 #define BITS_BIG_ENDIAN 0
523 /* Define this if most significant byte of a word is the lowest numbered. */
524 /* That is not true on the 80386. */
525 #define BYTES_BIG_ENDIAN 0
527 /* Define this if most significant word of a multiword number is the lowest
529 /* Not true for 80386 */
530 #define WORDS_BIG_ENDIAN 0
532 /* Width of a word, in units (bytes). */
533 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
535 #define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
537 #define MIN_UNITS_PER_WORD 4
540 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
541 #define PARM_BOUNDARY BITS_PER_WORD
543 /* Boundary (in *bits*) on which stack pointer should be aligned. */
544 #define STACK_BOUNDARY BITS_PER_WORD
546 /* Boundary (in *bits*) on which the stack pointer prefers to be
547 aligned; the compiler cannot rely on having this alignment. */
548 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
550 /* As of July 2001, many runtimes to not align the stack properly when
551 entering main. This causes expand_main_function to forcibly align
552 the stack, which results in aligned frames for functions called from
553 main, though it does nothing for the alignment of main itself. */
554 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
555 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
557 /* Minimum allocation boundary for the code of a function. */
558 #define FUNCTION_BOUNDARY 8
560 /* C++ stores the virtual bit in the lowest bit of function pointers. */
561 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
563 /* Alignment of field after `int : 0' in a structure. */
565 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
567 /* Minimum size in bits of the largest boundary to which any
568 and all fundamental data types supported by the hardware
569 might need to be aligned. No data type wants to be aligned
572 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
573 and Pentium Pro XFmode values at 128 bit boundaries. */
575 #define BIGGEST_ALIGNMENT 128
577 /* Decide whether a variable of mode MODE should be 128 bit aligned. */
578 #define ALIGN_MODE_128(MODE) \
579 ((MODE) == XFmode || (MODE) == TFmode || SSE_REG_MODE_P (MODE))
581 /* The published ABIs say that doubles should be aligned on word
582 boundaries, so lower the alignment for structure fields unless
583 -malign-double is set. */
585 /* ??? Blah -- this macro is used directly by libobjc. Since it
586 supports no vector modes, cut out the complexity and fall back
587 on BIGGEST_FIELD_ALIGNMENT. */
588 #ifdef IN_TARGET_LIBS
590 #define BIGGEST_FIELD_ALIGNMENT 128
592 #define BIGGEST_FIELD_ALIGNMENT 32
595 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
596 x86_field_alignment (FIELD, COMPUTED)
599 /* If defined, a C expression to compute the alignment given to a
600 constant that is being placed in memory. EXP is the constant
601 and ALIGN is the alignment that the object would ordinarily have.
602 The value of this macro is used instead of that alignment to align
605 If this macro is not defined, then ALIGN is used.
607 The typical use of this macro is to increase alignment for string
608 constants to be word aligned so that `strcpy' calls that copy
609 constants can be done inline. */
611 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
613 /* If defined, a C expression to compute the alignment for a static
614 variable. TYPE is the data type, and ALIGN is the alignment that
615 the object would ordinarily have. The value of this macro is used
616 instead of that alignment to align the object.
618 If this macro is not defined, then ALIGN is used.
620 One use of this macro is to increase alignment of medium-size
621 data to make it all fit in fewer cache lines. Another is to
622 cause character arrays to be word-aligned so that `strcpy' calls
623 that copy constants to character arrays can be done inline. */
625 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
627 /* If defined, a C expression to compute the alignment for a local
628 variable. TYPE is the data type, and ALIGN is the alignment that
629 the object would ordinarily have. The value of this macro is used
630 instead of that alignment to align the object.
632 If this macro is not defined, then ALIGN is used.
634 One use of this macro is to increase alignment of medium-size
635 data to make it all fit in fewer cache lines. */
637 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN))
639 /* If defined, a C expression that gives the alignment boundary, in
640 bits, of an argument with the specified mode and type. If it is
641 not defined, `PARM_BOUNDARY' is used for all arguments. */
643 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
644 ix86_function_arg_boundary ((MODE), (TYPE))
646 /* Set this nonzero if move instructions will actually fail to work
647 when given unaligned data. */
648 #define STRICT_ALIGNMENT 0
650 /* If bit field type is int, don't let it cross an int,
651 and give entire struct the alignment of an int. */
652 /* Required on the 386 since it doesn't have bit-field insns. */
653 #define PCC_BITFIELD_TYPE_MATTERS 1
655 /* Standard register usage. */
657 /* This processor has special stack-like registers. See reg-stack.c
661 #define IS_STACK_MODE(MODE) \
662 ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode) \
664 /* Number of actual hardware registers.
665 The hardware registers are assigned numbers for the compiler
666 from 0 to just below FIRST_PSEUDO_REGISTER.
667 All registers that the compiler knows about must be given numbers,
668 even those that are not normally considered general registers.
670 In the 80386 we give the 8 general purpose registers the numbers 0-7.
671 We number the floating point registers 8-15.
672 Note that registers 0-7 can be accessed as a short or int,
673 while only 0-3 may be used with byte `mov' instructions.
675 Reg 16 does not correspond to any hardware register, but instead
676 appears in the RTL as an argument pointer prior to reload, and is
677 eliminated during reloading in favor of either the stack or frame
680 #define FIRST_PSEUDO_REGISTER 53
682 /* Number of hardware registers that go into the DWARF-2 unwind info.
683 If not defined, equals FIRST_PSEUDO_REGISTER. */
685 #define DWARF_FRAME_REGISTERS 17
687 /* 1 for registers that have pervasive standard uses
688 and are not available for the register allocator.
689 On the 80386, the stack pointer is such, as is the arg pointer.
691 The value is zero if the register is not fixed on either 32 or
692 64 bit targets, one if the register if fixed on both 32 and 64
693 bit targets, two if it is only fixed on 32bit targets and three
694 if its only fixed on 64bit targets.
695 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
697 #define FIXED_REGISTERS \
698 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
699 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
700 /*arg,flags,fpsr,dir,frame*/ \
702 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
703 0, 0, 0, 0, 0, 0, 0, 0, \
704 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
705 0, 0, 0, 0, 0, 0, 0, 0, \
706 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
707 2, 2, 2, 2, 2, 2, 2, 2, \
708 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
709 2, 2, 2, 2, 2, 2, 2, 2}
712 /* 1 for registers not available across function calls.
713 These must include the FIXED_REGISTERS and also any
714 registers that can be used without being saved.
715 The latter must include the registers where values are returned
716 and the register where structure-value addresses are passed.
717 Aside from that, you can include as many other registers as you like.
719 The value is zero if the register is not call used on either 32 or
720 64 bit targets, one if the register if call used on both 32 and 64
721 bit targets, two if it is only call used on 32bit targets and three
722 if its only call used on 64bit targets.
723 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
725 #define CALL_USED_REGISTERS \
726 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
727 { 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
728 /*arg,flags,fpsr,dir,frame*/ \
730 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
731 1, 1, 1, 1, 1, 1, 1, 1, \
732 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
733 1, 1, 1, 1, 1, 1, 1, 1, \
734 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
735 1, 1, 1, 1, 2, 2, 2, 2, \
736 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
737 1, 1, 1, 1, 1, 1, 1, 1} \
739 /* Order in which to allocate registers. Each register must be
740 listed once, even those in FIXED_REGISTERS. List frame pointer
741 late and fixed registers last. Note that, in general, we prefer
742 registers listed in CALL_USED_REGISTERS, keeping the others
743 available for storage of persistent values.
745 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
746 so this is just empty initializer for array. */
748 #define REG_ALLOC_ORDER \
749 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
750 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
751 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
754 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
755 to be rearranged based on a particular function. When using sse math,
756 we want to allocate SSE before x87 registers and vice vera. */
758 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
761 /* Macro to conditionally modify fixed_regs/call_used_regs. */
762 #define CONDITIONAL_REGISTER_USAGE \
765 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
767 if (fixed_regs[i] > 1) \
768 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \
769 if (call_used_regs[i] > 1) \
770 call_used_regs[i] = (call_used_regs[i] \
771 == (TARGET_64BIT ? 3 : 2)); \
773 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
775 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
776 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
781 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
782 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
783 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
788 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
789 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
790 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
792 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
796 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
797 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
798 if (TEST_HARD_REG_BIT (x, i)) \
799 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
801 if (! TARGET_64BIT) \
804 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++) \
806 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \
811 /* Return number of consecutive hard regs needed starting at reg REGNO
812 to hold something of mode MODE.
813 This is ordinarily the length in words of a value of mode MODE
814 but can be less for certain modes in special long registers.
816 Actually there are no two word move instructions for consecutive
817 registers. And only registers 0-3 may have mov byte instructions
821 #define HARD_REGNO_NREGS(REGNO, MODE) \
822 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
823 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
824 : ((MODE) == XFmode \
825 ? (TARGET_64BIT ? 2 : 3) \
827 ? (TARGET_64BIT ? 4 : 6) \
828 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
830 #define VALID_SSE2_REG_MODE(MODE) \
831 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
832 || (MODE) == V2DImode || (MODE) == DFmode)
834 #define VALID_SSE_REG_MODE(MODE) \
835 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
836 || (MODE) == SFmode || (MODE) == TFmode)
838 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
839 ((MODE) == V2SFmode || (MODE) == SFmode)
841 #define VALID_MMX_REG_MODE(MODE) \
842 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
843 || (MODE) == V2SImode || (MODE) == SImode)
845 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
846 place emms and femms instructions. */
847 #define UNITS_PER_SIMD_WORD (TARGET_SSE ? 16 : UNITS_PER_WORD)
849 #define VALID_FP_MODE_P(MODE) \
850 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
851 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \
853 #define VALID_INT_MODE_P(MODE) \
854 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
855 || (MODE) == DImode \
856 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
857 || (MODE) == CDImode \
858 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \
859 || (MODE) == TFmode || (MODE) == TCmode)))
861 /* Return true for modes passed in SSE registers. */
862 #define SSE_REG_MODE_P(MODE) \
863 ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \
864 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \
865 || (MODE) == V4SFmode || (MODE) == V4SImode)
867 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
869 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
870 ix86_hard_regno_mode_ok ((REGNO), (MODE))
872 /* Value is 1 if it is a good idea to tie two pseudo registers
873 when one has mode MODE1 and one has mode MODE2.
874 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
875 for any hard reg, then this must be 0 for correct output. */
877 #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2)
879 /* It is possible to write patterns to move flags; but until someone
881 #define AVOID_CCMODE_COPIES
883 /* Specify the modes required to caller save a given hard regno.
884 We do this on i386 to prevent flags from being saved at all.
886 Kill any attempts to combine saving of modes. */
888 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
889 (CC_REGNO_P (REGNO) ? VOIDmode \
890 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
891 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false)\
892 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
893 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
895 /* Specify the registers used for certain standard purposes.
896 The values of these macros are register numbers. */
898 /* on the 386 the pc register is %eip, and is not usable as a general
899 register. The ordinary mov instructions won't work */
900 /* #define PC_REGNUM */
902 /* Register to use for pushing function arguments. */
903 #define STACK_POINTER_REGNUM 7
905 /* Base register for access to local variables of the function. */
906 #define HARD_FRAME_POINTER_REGNUM 6
908 /* Base register for access to local variables of the function. */
909 #define FRAME_POINTER_REGNUM 20
911 /* First floating point reg */
912 #define FIRST_FLOAT_REG 8
914 /* First & last stack-like regs */
915 #define FIRST_STACK_REG FIRST_FLOAT_REG
916 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
918 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
919 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
921 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
922 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
924 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
925 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
927 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
928 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
930 /* Value should be nonzero if functions must have frame pointers.
931 Zero means the frame pointer need not be set up (and parms
932 may be accessed via the stack pointer) in functions that seem suitable.
933 This is computed in `reload', in reload1.c. */
934 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
936 /* Override this in other tm.h files to cope with various OS lossage
937 requiring a frame pointer. */
938 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
939 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
942 /* Make sure we can access arbitrary call frames. */
943 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
945 /* Base register for access to arguments of the function. */
946 #define ARG_POINTER_REGNUM 16
948 /* Register in which static-chain is passed to a function.
949 We do use ECX as static chain register for 32 bit ABI. On the
950 64bit ABI, ECX is an argument register, so we use R10 instead. */
951 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
953 /* Register to hold the addressing base for position independent
954 code access to data items. We don't use PIC pointer for 64bit
955 mode. Define the regnum to dummy value to prevent gcc from
956 pessimizing code dealing with EBX.
958 To avoid clobbering a call-saved register unnecessarily, we renumber
959 the pic register when possible. The change is visible after the
960 prologue has been emitted. */
962 #define REAL_PIC_OFFSET_TABLE_REGNUM 3
964 #define PIC_OFFSET_TABLE_REGNUM \
965 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \
966 || !flag_pic ? INVALID_REGNUM \
967 : reload_completed ? REGNO (pic_offset_table_rtx) \
968 : REAL_PIC_OFFSET_TABLE_REGNUM)
970 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
972 /* A C expression which can inhibit the returning of certain function
973 values in registers, based on the type of value. A nonzero value
974 says to return the function value in memory, just as large
975 structures are always returned. Here TYPE will be a C expression
976 of type `tree', representing the data type of the value.
978 Note that values of mode `BLKmode' must be explicitly handled by
979 this macro. Also, the option `-fpcc-struct-return' takes effect
980 regardless of this macro. On most systems, it is possible to
981 leave the macro undefined; this causes a default definition to be
982 used, whose value is the constant 1 for `BLKmode' values, and 0
985 Do not use this macro to indicate that structures and unions
986 should always be returned in memory. You should instead use
987 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
989 #define RETURN_IN_MEMORY(TYPE) \
990 ix86_return_in_memory (TYPE)
992 /* This is overridden by <cygwin.h>. */
993 #define MS_AGGREGATE_RETURN 0
995 /* This is overridden by <netware.h>. */
996 #define KEEP_AGGREGATE_RETURN_POINTER 0
998 /* Define the classes of registers for register constraints in the
999 machine description. Also define ranges of constants.
1001 One of the classes must always be named ALL_REGS and include all hard regs.
1002 If there is more than one class, another class must be named NO_REGS
1003 and contain no registers.
1005 The name GENERAL_REGS must be the name of a class (or an alias for
1006 another name such as ALL_REGS). This is the class of registers
1007 that is allowed by "g" or "r" in a register constraint.
1008 Also, registers outside this class are allocated only when
1009 instructions express preferences for them.
1011 The classes must be numbered in nondecreasing order; that is,
1012 a larger-numbered class must never be contained completely
1013 in a smaller-numbered class.
1015 For any two classes, it is very desirable that there be another
1016 class that represents their union.
1018 It might seem that class BREG is unnecessary, since no useful 386
1019 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1020 and the "b" register constraint is useful in asms for syscalls.
1022 The flags and fpsr registers are in no class. */
1027 AREG, DREG, CREG, BREG, SIREG, DIREG,
1028 AD_REGS, /* %eax/%edx for DImode */
1029 Q_REGS, /* %eax %ebx %ecx %edx */
1030 NON_Q_REGS, /* %esi %edi %ebp %esp */
1031 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1032 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1033 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1034 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1044 ALL_REGS, LIM_REG_CLASSES
1047 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1049 #define INTEGER_CLASS_P(CLASS) \
1050 reg_class_subset_p ((CLASS), GENERAL_REGS)
1051 #define FLOAT_CLASS_P(CLASS) \
1052 reg_class_subset_p ((CLASS), FLOAT_REGS)
1053 #define SSE_CLASS_P(CLASS) \
1054 ((CLASS) == SSE_REGS)
1055 #define MMX_CLASS_P(CLASS) \
1056 ((CLASS) == MMX_REGS)
1057 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1058 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1059 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1060 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1061 #define MAYBE_SSE_CLASS_P(CLASS) \
1062 reg_classes_intersect_p (SSE_REGS, (CLASS))
1063 #define MAYBE_MMX_CLASS_P(CLASS) \
1064 reg_classes_intersect_p (MMX_REGS, (CLASS))
1066 #define Q_CLASS_P(CLASS) \
1067 reg_class_subset_p ((CLASS), Q_REGS)
1069 /* Give names of register classes as strings for dump file. */
1071 #define REG_CLASS_NAMES \
1073 "AREG", "DREG", "CREG", "BREG", \
1076 "Q_REGS", "NON_Q_REGS", \
1080 "FP_TOP_REG", "FP_SECOND_REG", \
1084 "FP_TOP_SSE_REGS", \
1085 "FP_SECOND_SSE_REGS", \
1089 "FLOAT_INT_SSE_REGS", \
1092 /* Define which registers fit in which classes.
1093 This is an initializer for a vector of HARD_REG_SET
1094 of length N_REG_CLASSES. */
1096 #define REG_CLASS_CONTENTS \
1098 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1099 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1100 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1101 { 0x03, 0x0 }, /* AD_REGS */ \
1102 { 0x0f, 0x0 }, /* Q_REGS */ \
1103 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1104 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1105 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1106 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1107 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1108 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1109 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1110 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1111 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1112 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1113 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1114 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1115 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1116 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1117 { 0xffffffff,0x1fffff } \
1120 /* The same information, inverted:
1121 Return the class number of the smallest class containing
1122 reg number REGNO. This could be a conditional expression
1123 or could index an array. */
1125 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1127 /* When defined, the compiler allows registers explicitly used in the
1128 rtl to be used as spill registers but prevents the compiler from
1129 extending the lifetime of these registers. */
1131 #define SMALL_REGISTER_CLASSES 1
1133 #define QI_REG_P(X) \
1134 (REG_P (X) && REGNO (X) < 4)
1136 #define GENERAL_REGNO_P(N) \
1137 ((N) < 8 || REX_INT_REGNO_P (N))
1139 #define GENERAL_REG_P(X) \
1140 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1142 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1144 #define NON_QI_REG_P(X) \
1145 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
1147 #define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG)
1148 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1150 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1151 #define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG)
1152 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1153 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1155 #define SSE_REGNO_P(N) \
1156 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \
1157 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG))
1159 #define REX_SSE_REGNO_P(N) \
1160 ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG)
1162 #define SSE_REGNO(N) \
1163 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1164 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1166 #define SSE_FLOAT_MODE_P(MODE) \
1167 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1169 #define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG)
1170 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1172 #define STACK_REG_P(XOP) \
1174 REGNO (XOP) >= FIRST_STACK_REG && \
1175 REGNO (XOP) <= LAST_STACK_REG)
1177 #define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP))
1179 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1181 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1182 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1184 /* The class value for index registers, and the one for base regs. */
1186 #define INDEX_REG_CLASS INDEX_REGS
1187 #define BASE_REG_CLASS GENERAL_REGS
1194 /* Get reg_class from a letter such as appears in the machine description. */
1196 #define REG_CLASS_FROM_LETTER(C) \
1197 ((C) == 'r' ? GENERAL_REGS : \
1198 (C) == 'R' ? LEGACY_REGS : \
1199 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \
1200 (C) == 'Q' ? Q_REGS : \
1201 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1204 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1207 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1210 (C) == 'a' ? AREG : \
1211 (C) == 'b' ? BREG : \
1212 (C) == 'c' ? CREG : \
1213 (C) == 'd' ? DREG : \
1214 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \
1215 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \
1216 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \
1217 (C) == 'A' ? AD_REGS : \
1218 (C) == 'D' ? DIREG : \
1219 (C) == 'S' ? SIREG : \
1220 (C) == 'l' ? INDEX_REGS : \
1223 /* The letters I, J, K, L, M, N, and O in a register constraint string
1224 can be used to stand for particular ranges of immediate operands.
1225 This macro defines what the ranges are.
1226 C is the letter, and VALUE is a constant value.
1227 Return 1 if VALUE is in the range specified by C.
1229 I is for non-DImode shifts.
1230 J is for DImode shifts.
1231 K is for signed imm8 operands.
1232 L is for andsi as zero-extending move.
1233 M is for shifts that can be executed by the "lea" opcode.
1234 N is for immediate operands for out/in instructions (0-255)
1235 O is for TImode shifts.
1238 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1239 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \
1240 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \
1241 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \
1242 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \
1243 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \
1244 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \
1245 : (C) == 'O' ? (VALUE) >= 0 && (VALUE) <= 127 \
1248 /* Similar, but for floating constants, and defining letters G and H.
1249 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if
1250 TARGET_387 isn't set, because the stack register converter may need to
1251 load 0.0 into the function value register. */
1253 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1254 ((C) == 'G' ? standard_80387_constant_p (VALUE) \
1257 /* A C expression that defines the optional machine-dependent
1258 constraint letters that can be used to segregate specific types of
1259 operands, usually memory references, for the target machine. Any
1260 letter that is not elsewhere defined and not matched by
1261 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not
1264 If it is required for a particular target machine, it should
1265 return 1 if VALUE corresponds to the operand type represented by
1266 the constraint letter C. If C is not defined as an extra
1267 constraint, the value returned should be 0 regardless of VALUE. */
1269 #define EXTRA_CONSTRAINT(VALUE, D) \
1270 ((D) == 'e' ? x86_64_immediate_operand (VALUE, VOIDmode) \
1271 : (D) == 'Z' ? x86_64_zext_immediate_operand (VALUE, VOIDmode) \
1272 : (D) == 'C' ? standard_sse_constant_p (VALUE) \
1275 /* Place additional restrictions on the register class to use when it
1276 is necessary to be able to hold a value of mode MODE in a reload
1277 register for which class CLASS would ordinarily be used. */
1279 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1280 ((MODE) == QImode && !TARGET_64BIT \
1281 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1282 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1285 /* Given an rtx X being reloaded into a reg required to be
1286 in class CLASS, return the class of reg to actually use.
1287 In general this is just CLASS; but on some machines
1288 in some cases it is preferable to use a more restrictive class.
1289 On the 80386 series, we prevent floating constants from being
1290 reloaded into floating registers (since no move-insn can do that)
1291 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1293 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1294 QImode must go into class Q_REGS.
1295 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1296 movdf to do mem-to-mem moves through integer regs. */
1298 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1299 ix86_preferred_reload_class ((X), (CLASS))
1301 /* If we are copying between general and FP registers, we need a memory
1302 location. The same is true for SSE and MMX registers. */
1303 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1304 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1306 /* QImode spills from non-QI registers need a scratch. This does not
1307 happen often -- the only example so far requires an uninitialized
1310 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
1311 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \
1312 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \
1315 /* Return the maximum number of consecutive registers
1316 needed to represent mode MODE in a register of class CLASS. */
1317 /* On the 80386, this is the size of MODE in words,
1318 except in the FP regs, where a single reg is always enough. */
1319 #define CLASS_MAX_NREGS(CLASS, MODE) \
1320 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1321 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1322 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \
1323 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1325 /* A C expression whose value is nonzero if pseudos that have been
1326 assigned to registers of class CLASS would likely be spilled
1327 because registers of CLASS are needed for spill registers.
1329 The default value of this macro returns 1 if CLASS has exactly one
1330 register and zero otherwise. On most machines, this default
1331 should be used. Only define this macro to some other expression
1332 if pseudo allocated by `local-alloc.c' end up in memory because
1333 their hard registers were needed for spill registers. If this
1334 macro returns nonzero for those classes, those pseudos will only
1335 be allocated by `global.c', which knows how to reallocate the
1336 pseudo to another register. If there would not be another
1337 register available for reallocation, you should not change the
1338 definition of this macro since the only effect of such a
1339 definition would be to slow down register allocation. */
1341 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1342 (((CLASS) == AREG) \
1343 || ((CLASS) == DREG) \
1344 || ((CLASS) == CREG) \
1345 || ((CLASS) == BREG) \
1346 || ((CLASS) == AD_REGS) \
1347 || ((CLASS) == SIREG) \
1348 || ((CLASS) == DIREG) \
1349 || ((CLASS) == FP_TOP_REG) \
1350 || ((CLASS) == FP_SECOND_REG))
1352 /* Return a class of registers that cannot change FROM mode to TO mode. */
1354 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1355 ix86_cannot_change_mode_class (FROM, TO, CLASS)
1357 /* Stack layout; function entry, exit and calling. */
1359 /* Define this if pushing a word on the stack
1360 makes the stack pointer a smaller address. */
1361 #define STACK_GROWS_DOWNWARD
1363 /* Define this to nonzero if the nominal address of the stack frame
1364 is at the high-address end of the local variables;
1365 that is, each additional local variable allocated
1366 goes at a more negative offset in the frame. */
1367 #define FRAME_GROWS_DOWNWARD 1
1369 /* Offset within stack frame to start allocating local variables at.
1370 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1371 first local allocated. Otherwise, it is the offset to the BEGINNING
1372 of the first local allocated. */
1373 #define STARTING_FRAME_OFFSET 0
1375 /* If we generate an insn to push BYTES bytes,
1376 this says how many the stack pointer really advances by.
1377 On 386, we have pushw instruction that decrements by exactly 2 no
1378 matter what the position was, there is no pushb.
1379 But as CIE data alignment factor on this arch is -4, we need to make
1380 sure all stack pointer adjustments are in multiple of 4.
1382 For 64bit ABI we round up to 8 bytes.
1385 #define PUSH_ROUNDING(BYTES) \
1387 ? (((BYTES) + 7) & (-8)) \
1388 : (((BYTES) + 3) & (-4)))
1390 /* If defined, the maximum amount of space required for outgoing arguments will
1391 be computed and placed into the variable
1392 `current_function_outgoing_args_size'. No space will be pushed onto the
1393 stack for each call; instead, the function prologue should increase the stack
1394 frame size by this amount. */
1396 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1398 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1399 instructions to pass outgoing arguments. */
1401 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1403 /* We want the stack and args grow in opposite directions, even if
1405 #define PUSH_ARGS_REVERSED 1
1407 /* Offset of first parameter from the argument pointer register value. */
1408 #define FIRST_PARM_OFFSET(FNDECL) 0
1410 /* Define this macro if functions should assume that stack space has been
1411 allocated for arguments even when their values are passed in registers.
1413 The value of this macro is the size, in bytes, of the area reserved for
1414 arguments passed in registers for the function represented by FNDECL.
1416 This space can be allocated by the caller, or be a part of the
1417 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1419 #define REG_PARM_STACK_SPACE(FNDECL) 0
1421 /* Value is the number of bytes of arguments automatically
1422 popped when returning from a subroutine call.
1423 FUNDECL is the declaration node of the function (as a tree),
1424 FUNTYPE is the data type of the function (as a tree),
1425 or for a library call it is an identifier node for the subroutine name.
1426 SIZE is the number of bytes of arguments passed on the stack.
1428 On the 80386, the RTD insn may be used to pop them if the number
1429 of args is fixed, but if the number is variable then the caller
1430 must pop them all. RTD can't be used for library calls now
1431 because the library is compiled with the Unix compiler.
1432 Use of RTD is a selectable option, since it is incompatible with
1433 standard Unix calling sequences. If the option is not selected,
1434 the caller must always pop the args.
1436 The attribute stdcall is equivalent to RTD on a per module basis. */
1438 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1439 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1441 #define FUNCTION_VALUE_REGNO_P(N) \
1442 ix86_function_value_regno_p (N)
1444 /* Define how to find the value returned by a library function
1445 assuming the value has mode MODE. */
1447 #define LIBCALL_VALUE(MODE) \
1448 ix86_libcall_value (MODE)
1450 /* Define the size of the result block used for communication between
1451 untyped_call and untyped_return. The block contains a DImode value
1452 followed by the block used by fnsave and frstor. */
1454 #define APPLY_RESULT_SIZE (8+108)
1456 /* 1 if N is a possible register number for function argument passing. */
1457 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1459 /* Define a data type for recording info about an argument list
1460 during the scan of that argument list. This data type should
1461 hold all necessary information about the function itself
1462 and about the args processed so far, enough to enable macros
1463 such as FUNCTION_ARG to determine where the next arg should go. */
1465 typedef struct ix86_args {
1466 int words; /* # words passed so far */
1467 int nregs; /* # registers available for passing */
1468 int regno; /* next available register number */
1469 int fastcall; /* fastcall calling convention is used */
1470 int sse_words; /* # sse words passed so far */
1471 int sse_nregs; /* # sse registers available for passing */
1472 int warn_sse; /* True when we want to warn about SSE ABI. */
1473 int warn_mmx; /* True when we want to warn about MMX ABI. */
1474 int sse_regno; /* next available sse register number */
1475 int mmx_words; /* # mmx words passed so far */
1476 int mmx_nregs; /* # mmx registers available for passing */
1477 int mmx_regno; /* next available mmx register number */
1478 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1479 int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should
1480 be passed in SSE registers. Otherwise 0. */
1483 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1484 for a call to a function whose data type is FNTYPE.
1485 For a library call, FNTYPE is 0. */
1487 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1488 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1490 /* Update the data in CUM to advance over an argument
1491 of mode MODE and data type TYPE.
1492 (TYPE is null for libcalls where that information may not be available.) */
1494 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1495 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1497 /* Define where to put the arguments to a function.
1498 Value is zero to push the argument on the stack,
1499 or a hard register in which to store the argument.
1501 MODE is the argument's machine mode.
1502 TYPE is the data type of the argument (as a tree).
1503 This is null for libcalls where that information may
1505 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1506 the preceding args and about the function being called.
1507 NAMED is nonzero if this argument is a named parameter
1508 (otherwise it is an extra parameter matching an ellipsis). */
1510 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1511 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1513 /* Implement `va_start' for varargs and stdarg. */
1514 #define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \
1515 ix86_va_start (VALIST, NEXTARG)
1517 #define TARGET_ASM_FILE_END ix86_file_end
1518 #define NEED_INDICATE_EXEC_STACK 0
1520 /* Output assembler code to FILE to increment profiler label # LABELNO
1521 for profiling a function entry. */
1523 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO)
1525 #define MCOUNT_NAME "_mcount"
1527 #define PROFILE_COUNT_REGISTER "edx"
1529 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1530 the stack pointer does not matter. The value is tested only in
1531 functions that have frame pointers.
1532 No definition is equivalent to always zero. */
1533 /* Note on the 386 it might be more efficient not to define this since
1534 we have to restore it ourselves from the frame pointer, in order to
1537 #define EXIT_IGNORE_STACK 1
1539 /* Output assembler code for a block containing the constant parts
1540 of a trampoline, leaving space for the variable parts. */
1542 /* On the 386, the trampoline contains two instructions:
1545 The trampoline is generated entirely at runtime. The operand of JMP
1546 is the address of FUNCTION relative to the instruction following the
1547 JMP (which is 5 bytes long). */
1549 /* Length in units of the trampoline for entering a nested function. */
1551 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1553 /* Emit RTL insns to initialize the variable parts of a trampoline.
1554 FNADDR is an RTX for the address of the function's pure code.
1555 CXT is an RTX for the static chain value for the function. */
1557 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1558 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1560 /* Definitions for register eliminations.
1562 This is an array of structures. Each structure initializes one pair
1563 of eliminable registers. The "from" register number is given first,
1564 followed by "to". Eliminations of the same "from" register are listed
1565 in order of preference.
1567 There are two registers that can always be eliminated on the i386.
1568 The frame pointer and the arg pointer can be replaced by either the
1569 hard frame pointer or to the stack pointer, depending upon the
1570 circumstances. The hard frame pointer is not used before reload and
1571 so it is not eligible for elimination. */
1573 #define ELIMINABLE_REGS \
1574 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1575 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1576 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1577 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1579 /* Given FROM and TO register numbers, say whether this elimination is
1580 allowed. Frame pointer elimination is automatically handled.
1582 All other eliminations are valid. */
1584 #define CAN_ELIMINATE(FROM, TO) \
1585 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1587 /* Define the offset between two registers, one to be eliminated, and the other
1588 its replacement, at the start of a routine. */
1590 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1591 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1593 /* Addressing modes, and classification of registers for them. */
1595 /* Macros to check register numbers against specific register classes. */
1597 /* These assume that REGNO is a hard or pseudo reg number.
1598 They give nonzero only if REGNO is a hard reg of the suitable class
1599 or a pseudo reg currently allocated to a suitable hard reg.
1600 Since they use reg_renumber, they are safe only once reg_renumber
1601 has been allocated, which happens in local-alloc.c. */
1603 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1604 ((REGNO) < STACK_POINTER_REGNUM \
1605 || (REGNO >= FIRST_REX_INT_REG \
1606 && (REGNO) <= LAST_REX_INT_REG) \
1607 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1608 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1609 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM)
1611 #define REGNO_OK_FOR_BASE_P(REGNO) \
1612 ((REGNO) <= STACK_POINTER_REGNUM \
1613 || (REGNO) == ARG_POINTER_REGNUM \
1614 || (REGNO) == FRAME_POINTER_REGNUM \
1615 || (REGNO >= FIRST_REX_INT_REG \
1616 && (REGNO) <= LAST_REX_INT_REG) \
1617 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1618 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1619 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM)
1621 #define REGNO_OK_FOR_SIREG_P(REGNO) \
1622 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4)
1623 #define REGNO_OK_FOR_DIREG_P(REGNO) \
1624 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5)
1626 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1627 and check its validity for a certain class.
1628 We have two alternate definitions for each of them.
1629 The usual definition accepts all pseudo regs; the other rejects
1630 them unless they have been allocated suitable hard regs.
1631 The symbol REG_OK_STRICT causes the latter definition to be used.
1633 Most source files want to accept pseudo regs in the hope that
1634 they will get allocated to the class that the insn wants them to be in.
1635 Source files for reload pass need to be strict.
1636 After reload, it makes no difference, since pseudo regs have
1637 been eliminated by then. */
1640 /* Non strict versions, pseudos are ok. */
1641 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1642 (REGNO (X) < STACK_POINTER_REGNUM \
1643 || (REGNO (X) >= FIRST_REX_INT_REG \
1644 && REGNO (X) <= LAST_REX_INT_REG) \
1645 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1647 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1648 (REGNO (X) <= STACK_POINTER_REGNUM \
1649 || REGNO (X) == ARG_POINTER_REGNUM \
1650 || REGNO (X) == FRAME_POINTER_REGNUM \
1651 || (REGNO (X) >= FIRST_REX_INT_REG \
1652 && REGNO (X) <= LAST_REX_INT_REG) \
1653 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1655 /* Strict versions, hard registers only */
1656 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1657 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1659 #ifndef REG_OK_STRICT
1660 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1661 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1664 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1665 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1668 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1669 that is a valid memory address for an instruction.
1670 The MODE argument is the machine mode for the MEM expression
1671 that wants to use this address.
1673 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1674 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1676 See legitimize_pic_address in i386.c for details as to what
1677 constitutes a legitimate address when -fpic is used. */
1679 #define MAX_REGS_PER_ADDRESS 2
1681 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1683 /* Nonzero if the constant value X is a legitimate general operand.
1684 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1686 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1688 #ifdef REG_OK_STRICT
1689 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1691 if (legitimate_address_p ((MODE), (X), 1)) \
1696 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1698 if (legitimate_address_p ((MODE), (X), 0)) \
1704 /* If defined, a C expression to determine the base term of address X.
1705 This macro is used in only one place: `find_base_term' in alias.c.
1707 It is always safe for this macro to not be defined. It exists so
1708 that alias analysis can understand machine-dependent addresses.
1710 The typical use of this macro is to handle addresses containing
1711 a label_ref or symbol_ref within an UNSPEC. */
1713 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1715 /* Try machine-dependent ways of modifying an illegitimate address
1716 to be legitimate. If we find one, return the new, valid address.
1717 This macro is used in only one place: `memory_address' in explow.c.
1719 OLDX is the address as it was before break_out_memory_refs was called.
1720 In some cases it is useful to look at this to decide what needs to be done.
1722 MODE and WIN are passed so that this macro can use
1723 GO_IF_LEGITIMATE_ADDRESS.
1725 It is always safe for this macro to do nothing. It exists to recognize
1726 opportunities to optimize the output.
1728 For the 80386, we handle X+REG by loading X into a register R and
1729 using R+REG. R will go in a general reg and indexing will be used.
1730 However, if REG is a broken-out memory address or multiplication,
1731 nothing needs to be done because REG can certainly go in a general reg.
1733 When -fpic is used, special handling is needed for symbolic references.
1734 See comments by legitimize_pic_address in i386.c for details. */
1736 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1738 (X) = legitimize_address ((X), (OLDX), (MODE)); \
1739 if (memory_address_p ((MODE), (X))) \
1743 #define REWRITE_ADDRESS(X) rewrite_address (X)
1745 /* Nonzero if the constant value X is a legitimate general operand
1746 when generating PIC code. It is given that flag_pic is on and
1747 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1749 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1751 #define SYMBOLIC_CONST(X) \
1752 (GET_CODE (X) == SYMBOL_REF \
1753 || GET_CODE (X) == LABEL_REF \
1754 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1756 /* Go to LABEL if ADDR (a legitimate address expression)
1757 has an effect that depends on the machine mode it is used for.
1758 On the 80386, only postdecrement and postincrement address depend thus
1759 (the amount of decrement or increment being the length of the operand). */
1760 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1762 if (GET_CODE (ADDR) == POST_INC \
1763 || GET_CODE (ADDR) == POST_DEC) \
1767 /* Max number of args passed in registers. If this is more than 3, we will
1768 have problems with ebx (register #4), since it is a caller save register and
1769 is also used as the pic register in ELF. So for now, don't allow more than
1770 3 registers to be passed in registers. */
1772 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
1774 #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : (TARGET_SSE ? 3 : 0))
1776 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0))
1779 /* Specify the machine mode that this machine uses
1780 for the index in the tablejump instruction. */
1781 #define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode)
1783 /* Define this as 1 if `char' should by default be signed; else as 0. */
1784 #define DEFAULT_SIGNED_CHAR 1
1786 /* Number of bytes moved into a data cache for a single prefetch operation. */
1787 #define PREFETCH_BLOCK ix86_cost->prefetch_block
1789 /* Number of prefetch operations that can be done in parallel. */
1790 #define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches
1792 /* Max number of bytes we can move from memory to memory
1793 in one reasonably fast instruction. */
1796 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
1797 move efficiently, as opposed to MOVE_MAX which is the maximum
1798 number of bytes we can move with a single instruction. */
1799 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
1801 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1802 move-instruction pairs, we will do a movmem or libcall instead.
1803 Increasing the value will always make code faster, but eventually
1804 incurs high cost in increased code size.
1806 If you don't define this, a reasonable default is used. */
1808 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
1810 /* If a clear memory operation would take CLEAR_RATIO or more simple
1811 move-instruction sequences, we will do a clrmem or libcall instead. */
1813 #define CLEAR_RATIO (optimize_size ? 2 \
1814 : ix86_cost->move_ratio > 6 ? 6 : ix86_cost->move_ratio)
1816 /* Define if shifts truncate the shift count
1817 which implies one can omit a sign-extension or zero-extension
1818 of a shift count. */
1819 /* On i386, shifts do truncate the count. But bit opcodes don't. */
1821 /* #define SHIFT_COUNT_TRUNCATED */
1823 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1824 is done just by pretending it is already truncated. */
1825 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1827 /* A macro to update M and UNSIGNEDP when an object whose type is
1828 TYPE and which has the specified mode and signedness is to be
1829 stored in a register. This macro is only called when TYPE is a
1832 On i386 it is sometimes useful to promote HImode and QImode
1833 quantities to SImode. The choice depends on target type. */
1835 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1837 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
1838 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
1842 /* Specify the machine mode that pointers have.
1843 After generation of rtl, the compiler makes no further distinction
1844 between pointers and any other objects of this machine mode. */
1845 #define Pmode (TARGET_64BIT ? DImode : SImode)
1847 /* A function address in a call instruction
1848 is a byte address (for indexing purposes)
1849 so give the MEM rtx a byte's mode. */
1850 #define FUNCTION_MODE QImode
1852 /* A C expression for the cost of moving data from a register in class FROM to
1853 one in class TO. The classes are expressed using the enumeration values
1854 such as `GENERAL_REGS'. A value of 2 is the default; other values are
1855 interpreted relative to that.
1857 It is not required that the cost always equal 2 when FROM is the same as TO;
1858 on some machines it is expensive to move between registers if they are not
1859 general registers. */
1861 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1862 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
1864 /* A C expression for the cost of moving data of mode M between a
1865 register and memory. A value of 2 is the default; this cost is
1866 relative to those in `REGISTER_MOVE_COST'.
1868 If moving between registers and memory is more expensive than
1869 between two registers, you should define this macro to express the
1872 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
1873 ix86_memory_move_cost ((MODE), (CLASS), (IN))
1875 /* A C expression for the cost of a branch instruction. A value of 1
1876 is the default; other values are interpreted relative to that. */
1878 #define BRANCH_COST ix86_branch_cost
1880 /* Define this macro as a C expression which is nonzero if accessing
1881 less than a word of memory (i.e. a `char' or a `short') is no
1882 faster than accessing a word of memory, i.e., if such access
1883 require more than one instruction or if there is no difference in
1884 cost between byte and (aligned) word loads.
1886 When this macro is not defined, the compiler will access a field by
1887 finding the smallest containing object; when it is defined, a
1888 fullword load will be used if alignment permits. Unless bytes
1889 accesses are faster than word accesses, using word accesses is
1890 preferable since it may eliminate subsequent memory access if
1891 subsequent accesses occur to other fields in the same word of the
1892 structure, but to different bytes. */
1894 #define SLOW_BYTE_ACCESS 0
1896 /* Nonzero if access to memory by shorts is slow and undesirable. */
1897 #define SLOW_SHORT_ACCESS 0
1899 /* Define this macro to be the value 1 if unaligned accesses have a
1900 cost many times greater than aligned accesses, for example if they
1901 are emulated in a trap handler.
1903 When this macro is nonzero, the compiler will act as if
1904 `STRICT_ALIGNMENT' were nonzero when generating code for block
1905 moves. This can cause significantly more instructions to be
1906 produced. Therefore, do not set this macro nonzero if unaligned
1907 accesses only add a cycle or two to the time for a memory access.
1909 If the value of this macro is always zero, it need not be defined. */
1911 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
1913 /* Define this macro if it is as good or better to call a constant
1914 function address than to call an address kept in a register.
1916 Desirable on the 386 because a CALL with a constant address is
1917 faster than one with a register address. */
1919 #define NO_FUNCTION_CSE
1921 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1922 return the mode to be used for the comparison.
1924 For floating-point equality comparisons, CCFPEQmode should be used.
1925 VOIDmode should be used in all other cases.
1927 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
1928 possible, to allow for more combinations. */
1930 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
1932 /* Return nonzero if MODE implies a floating point inequality can be
1935 #define REVERSIBLE_CC_MODE(MODE) 1
1937 /* A C expression whose value is reversed condition code of the CODE for
1938 comparison done in CC_MODE mode. */
1939 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
1942 /* Control the assembler format that we output, to the extent
1943 this does not vary between assemblers. */
1945 /* How to refer to registers in assembler output.
1946 This sequence is indexed by compiler's hard-register-number (see above). */
1948 /* In order to refer to the first 8 regs as 32 bit regs, prefix an "e".
1949 For non floating point regs, the following are the HImode names.
1951 For float regs, the stack top is sometimes referred to as "%st(0)"
1952 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */
1954 #define HI_REGISTER_NAMES \
1955 {"ax","dx","cx","bx","si","di","bp","sp", \
1956 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
1957 "argp", "flags", "fpsr", "dirflag", "frame", \
1958 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
1959 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \
1960 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1961 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
1963 #define REGISTER_NAMES HI_REGISTER_NAMES
1965 /* Table of additional register names to use in user input. */
1967 #define ADDITIONAL_REGISTER_NAMES \
1968 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
1969 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
1970 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
1971 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
1972 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
1973 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } }
1975 /* Note we are omitting these since currently I don't know how
1976 to get gcc to use these, since they want the same but different
1977 number as al, and ax.
1980 #define QI_REGISTER_NAMES \
1981 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
1983 /* These parallel the array above, and can be used to access bits 8:15
1984 of regs 0 through 3. */
1986 #define QI_HIGH_REGISTER_NAMES \
1987 {"ah", "dh", "ch", "bh", }
1989 /* How to renumber registers for dbx and gdb. */
1991 #define DBX_REGISTER_NUMBER(N) \
1992 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
1994 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
1995 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
1996 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
1998 /* Before the prologue, RA is at 0(%esp). */
1999 #define INCOMING_RETURN_ADDR_RTX \
2000 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2002 /* After the prologue, RA is at -4(AP) in the current frame. */
2003 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2005 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2006 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2008 /* PC is dbx register 8; let's use that column for RA. */
2009 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2011 /* Before the prologue, the top of the frame is at 4(%esp). */
2012 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2014 /* Describe how we implement __builtin_eh_return. */
2015 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2016 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2019 /* Select a format to encode pointers in exception handling data. CODE
2020 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2021 true if the symbol may be affected by dynamic relocations.
2023 ??? All x86 object file formats are capable of representing this.
2024 After all, the relocation needed is the same as for the call insn.
2025 Whether or not a particular assembler allows us to enter such, I
2026 guess we'll have to see. */
2027 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2028 asm_preferred_eh_data_format ((CODE), (GLOBAL))
2030 /* This is how to output an insn to push a register on the stack.
2031 It need not be very fast code. */
2033 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2036 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \
2037 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2039 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \
2042 /* This is how to output an insn to pop a register from the stack.
2043 It need not be very fast code. */
2045 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2048 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \
2049 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2051 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \
2054 /* This is how to output an element of a case-vector that is absolute. */
2056 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2057 ix86_output_addr_vec_elt ((FILE), (VALUE))
2059 /* This is how to output an element of a case-vector that is relative. */
2061 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2062 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2064 /* Under some conditions we need jump tables in the text section, because
2065 the assembler cannot handle label differences between sections. */
2067 #define JUMP_TABLES_IN_TEXT_SECTION \
2068 (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA)
2070 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2071 and switch back. For x86 we do this only to save a few bytes that
2072 would otherwise be unused in the text section. */
2073 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2074 asm (SECTION_OP "\n\t" \
2075 "call " USER_LABEL_PREFIX #FUNC "\n" \
2076 TEXT_SECTION_ASM_OP);
2078 /* Print operand X (an rtx) in assembler syntax to file FILE.
2079 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2080 Effect of various CODE letters is described in i386.c near
2081 print_operand function. */
2083 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2084 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&')
2086 #define PRINT_OPERAND(FILE, X, CODE) \
2087 print_operand ((FILE), (X), (CODE))
2089 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2090 print_operand_address ((FILE), (ADDR))
2092 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2094 if (! output_addr_const_extra (FILE, (X))) \
2098 /* a letter which is not needed by the normal asm syntax, which
2099 we can use for operand syntax in the extended asm */
2101 #define ASM_OPERAND_LETTER '#'
2102 #define RET return ""
2103 #define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx))
2105 /* Which processor to schedule for. The cpu attribute defines a list that
2106 mirrors this list, so changes to i386.md must be made at the same time. */
2110 PROCESSOR_I386, /* 80386 */
2111 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
2113 PROCESSOR_PENTIUMPRO,
2122 extern enum processor_type ix86_tune;
2123 extern enum processor_type ix86_arch;
2131 extern enum fpmath_unit ix86_fpmath;
2139 extern enum tls_dialect ix86_tls_dialect;
2142 CM_32, /* The traditional 32-bit ABI. */
2143 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */
2144 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */
2145 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */
2146 CM_LARGE, /* No assumptions. */
2147 CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */
2148 CM_MEDIUM_PIC /* Assumes code+got/plt fits in a 31 bit region. */
2151 extern enum cmodel ix86_cmodel;
2153 /* Size of the RED_ZONE area. */
2154 #define RED_ZONE_SIZE 128
2155 /* Reserved area of the red zone for temporaries. */
2156 #define RED_ZONE_RESERVE 8
2163 extern enum asm_dialect ix86_asm_dialect;
2164 extern unsigned int ix86_preferred_stack_boundary;
2165 extern int ix86_branch_cost, ix86_section_threshold;
2167 /* Smallest class containing REGNO. */
2168 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
2170 extern rtx ix86_compare_op0; /* operand 0 for comparisons */
2171 extern rtx ix86_compare_op1; /* operand 1 for comparisons */
2172 extern rtx ix86_compare_emitted;
2174 /* To properly truncate FP values into integers, we need to set i387 control
2175 word. We can't emit proper mode switching code before reload, as spills
2176 generated by reload may truncate values incorrectly, but we still can avoid
2177 redundant computation of new control word by the mode switching pass.
2178 The fldcw instructions are still emitted redundantly, but this is probably
2179 not going to be noticeable problem, as most CPUs do have fast path for
2182 The machinery is to emit simple truncation instructions and split them
2183 before reload to instructions having USEs of two memory locations that
2184 are filled by this code to old and new control word.
2186 Post-reload pass may be later used to eliminate the redundant fildcw if
2198 enum ix86_stack_slot
2206 MAX_386_STACK_LOCALS
2209 /* Define this macro if the port needs extra instructions inserted
2210 for mode switching in an optimizing compilation. */
2212 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \
2213 ix86_optimize_mode_switching[(ENTITY)]
2215 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2216 initializer for an array of integers. Each initializer element N
2217 refers to an entity that needs mode switching, and specifies the
2218 number of different modes that might need to be set for this
2219 entity. The position of the initializer in the initializer -
2220 starting counting at zero - determines the integer that is used to
2221 refer to the mode-switched entity in question. */
2223 #define NUM_MODES_FOR_MODE_SWITCHING \
2224 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2226 /* ENTITY is an integer specifying a mode-switched entity. If
2227 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
2228 return an integer value not larger than the corresponding element
2229 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
2230 must be switched into prior to the execution of INSN. */
2232 #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I))
2234 /* This macro specifies the order in which modes for ENTITY are
2235 processed. 0 is the highest priority. */
2237 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
2239 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
2240 is the set of hard registers live at the point where the insn(s)
2241 are to be inserted. */
2243 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2244 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \
2245 ? emit_i387_cw_initialization (MODE), 0 \
2249 /* Avoid renaming of stack registers, as doing so in combination with
2250 scheduling just increases amount of live registers at time and in
2251 the turn amount of fxch instructions needed.
2253 ??? Maybe Pentium chips benefits from renaming, someone can try.... */
2255 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
2256 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG)
2259 #define DLL_IMPORT_EXPORT_PREFIX '#'
2261 #define FASTCALL_PREFIX '@'
2263 struct machine_function GTY(())
2265 struct stack_local_entry *stack_locals;
2266 const char *some_ld_name;
2267 rtx force_align_arg_pointer;
2268 int save_varrargs_registers;
2269 int accesses_prev_frame;
2270 int optimize_mode_switching[MAX_386_ENTITIES];
2271 /* Set by ix86_compute_frame_layout and used by prologue/epilogue expander to
2272 determine the style used. */
2273 int use_fast_prologue_epilogue;
2274 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed
2276 int use_fast_prologue_epilogue_nregs;
2279 #define ix86_stack_locals (cfun->machine->stack_locals)
2280 #define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers)
2281 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2283 /* Control behavior of x86_file_start. */
2284 #define X86_FILE_START_VERSION_DIRECTIVE false
2285 #define X86_FILE_START_FLTUSED false
2287 /* Flag to mark data that is in the large address area. */
2288 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
2289 #define SYMBOL_REF_FAR_ADDR_P(X) \
2290 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
projects / dragonfly.git / blob