sys/dev/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/export.h>
  30 #include <drm/drmP.h>
  31 #include <linux/slab.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  40
  41 struct dp_link_dpll {
  42         int link_bw;
  43         struct dpll dpll;
  44 };
  45
  46 static const struct dp_link_dpll gen4_dpll[] = {
  47         { DP_LINK_BW_1_62,
  48                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  49         { DP_LINK_BW_2_7,
  50                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  51 };
  52
  53 static const struct dp_link_dpll pch_dpll[] = {
  54         { DP_LINK_BW_1_62,
  55                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  56         { DP_LINK_BW_2_7,
  57                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  58 };
  59
  60 static const struct dp_link_dpll vlv_dpll[] = {
  61         { DP_LINK_BW_1_62,
  62                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  63         { DP_LINK_BW_2_7,
  64                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  65 };
  66
  67 /*
  68  * CHV supports eDP 1.4 that have  more link rates.
  69  * Below only provides the fixed rate but exclude variable rate.
  70  */
  71 static const struct dp_link_dpll chv_dpll[] = {
  72         /*
  73          * CHV requires to program fractional division for m2.
  74          * m2 is stored in fixed point format using formula below
  75          * (m2_int << 22) | m2_fraction
  76          */
  77         { DP_LINK_BW_1_62,      /* m2_int = 32, m2_fraction = 1677722 */
  78                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  79         { DP_LINK_BW_2_7,       /* m2_int = 27, m2_fraction = 0 */
  80                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  81         { DP_LINK_BW_5_4,       /* m2_int = 27, m2_fraction = 0 */
  82                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  83 };
  84
  85 /**
  86  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  87  * @intel_dp: DP struct
  88  *
  89  * If a CPU or PCH DP output is attached to an eDP panel, this function
  90  * will return true, and false otherwise.
  91  */
  92 static bool is_edp(struct intel_dp *intel_dp)
  93 {
  94         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  95
  96         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  97 }
  98
  99 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 100 {
 101         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 102
 103         return intel_dig_port->base.base.dev;
 104 }
 105
 106 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 107 {
 108         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 109 }
 110
 111 static void intel_dp_link_down(struct intel_dp *intel_dp);
 112 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 113
 114 int
 115 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 116 {
 117         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 118         struct drm_device *dev = intel_dp->attached_connector->base.dev;
 119
 120         switch (max_link_bw) {
 121         case DP_LINK_BW_1_62:
 122         case DP_LINK_BW_2_7:
 123                 break;
 124         case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
 125                 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
 126                      INTEL_INFO(dev)->gen >= 8) &&
 127                     intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
 128                         max_link_bw = DP_LINK_BW_5_4;
 129                 else
 130                         max_link_bw = DP_LINK_BW_2_7;
 131                 break;
 132         default:
 133                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 134                      max_link_bw);
 135                 max_link_bw = DP_LINK_BW_1_62;
 136                 break;
 137         }
 138         return max_link_bw;
 139 }
 140
 141 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 142 {
 143         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 144         struct drm_device *dev = intel_dig_port->base.base.dev;
 145         u8 source_max, sink_max;
 146
 147         source_max = 4;
 148         if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
 149             (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
 150                 source_max = 2;
 151
 152         sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 153
 154         return min(source_max, sink_max);
 155 }
 156
 157 /*
 158  * The units on the numbers in the next two are... bizarre.  Examples will
 159  * make it clearer; this one parallels an example in the eDP spec.
 160  *
 161  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 162  *
 163  *     270000 * 1 * 8 / 10 == 216000
 164  *
 165  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 166  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 167  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 168  * 119000.  At 18bpp that's 2142000 kilobits per second.
 169  *
 170  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 171  * get the result in decakilobits instead of kilobits.
 172  */
 173
 174 static int
 175 intel_dp_link_required(int pixel_clock, int bpp)
 176 {
 177         return (pixel_clock * bpp + 9) / 10;
 178 }
 179
 180 static int
 181 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 182 {
 183         return (max_link_clock * max_lanes * 8) / 10;
 184 }
 185
 186 static enum drm_mode_status
 187 intel_dp_mode_valid(struct drm_connector *connector,
 188                     struct drm_display_mode *mode)
 189 {
 190         struct intel_dp *intel_dp = intel_attached_dp(connector);
 191         struct intel_connector *intel_connector = to_intel_connector(connector);
 192         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 193         int target_clock = mode->clock;
 194         int max_rate, mode_rate, max_lanes, max_link_clock;
 195
 196         if (is_edp(intel_dp) && fixed_mode) {
 197                 if (mode->hdisplay > fixed_mode->hdisplay)
 198                         return MODE_PANEL;
 199
 200                 if (mode->vdisplay > fixed_mode->vdisplay)
 201                         return MODE_PANEL;
 202
 203                 target_clock = fixed_mode->clock;
 204         }
 205
 206         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 207         max_lanes = intel_dp_max_lane_count(intel_dp);
 208
 209         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 210         mode_rate = intel_dp_link_required(target_clock, 18);
 211
 212         if (mode_rate > max_rate)
 213                 return MODE_CLOCK_HIGH;
 214
 215         if (mode->clock < 10000)
 216                 return MODE_CLOCK_LOW;
 217
 218         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 219                 return MODE_H_ILLEGAL;
 220
 221         return MODE_OK;
 222 }
 223
 224 static uint32_t
 225 pack_aux(uint8_t *src, int src_bytes)
 226 {
 227         int     i;
 228         uint32_t v = 0;
 229
 230         if (src_bytes > 4)
 231                 src_bytes = 4;
 232         for (i = 0; i < src_bytes; i++)
 233                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 234         return v;
 235 }
 236
 237 static void
 238 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 239 {
 240         int i;
 241         if (dst_bytes > 4)
 242                 dst_bytes = 4;
 243         for (i = 0; i < dst_bytes; i++)
 244                 dst[i] = src >> ((3-i) * 8);
 245 }
 246
 247 /* hrawclock is 1/4 the FSB frequency */
 248 static int
 249 intel_hrawclk(struct drm_device *dev)
 250 {
 251         struct drm_i915_private *dev_priv = dev->dev_private;
 252         uint32_t clkcfg;
 253
 254         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 255         if (IS_VALLEYVIEW(dev))
 256                 return 200;
 257
 258         clkcfg = I915_READ(CLKCFG);
 259         switch (clkcfg & CLKCFG_FSB_MASK) {
 260         case CLKCFG_FSB_400:
 261                 return 100;
 262         case CLKCFG_FSB_533:
 263                 return 133;
 264         case CLKCFG_FSB_667:
 265                 return 166;
 266         case CLKCFG_FSB_800:
 267                 return 200;
 268         case CLKCFG_FSB_1067:
 269                 return 266;
 270         case CLKCFG_FSB_1333:
 271                 return 333;
 272         /* these two are just a guess; one of them might be right */
 273         case CLKCFG_FSB_1600:
 274         case CLKCFG_FSB_1600_ALT:
 275                 return 400;
 276         default:
 277                 return 133;
 278         }
 279 }
 280
 281 static void
 282 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 283                                     struct intel_dp *intel_dp,
 284                                     struct edp_power_seq *out);
 285 static void
 286 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 287                                               struct intel_dp *intel_dp,
 288                                               struct edp_power_seq *out);
 289
 290 static enum i915_pipe
 291 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 292 {
 293         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 294         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
 295         struct drm_device *dev = intel_dig_port->base.base.dev;
 296         struct drm_i915_private *dev_priv = dev->dev_private;
 297         enum port port = intel_dig_port->port;
 298         enum i915_pipe pipe;
 299
 300         /* modeset should have pipe */
 301         if (crtc)
 302                 return to_intel_crtc(crtc)->pipe;
 303
 304         /* init time, try to find a pipe with this port selected */
 305         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 306                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 307                         PANEL_PORT_SELECT_MASK;
 308                 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
 309                         return pipe;
 310                 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
 311                         return pipe;
 312         }
 313
 314         /* shrug */
 315         return PIPE_A;
 316 }
 317
 318 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
 319 {
 320         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 321
 322         if (HAS_PCH_SPLIT(dev))
 323                 return PCH_PP_CONTROL;
 324         else
 325                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 326 }
 327
 328 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
 329 {
 330         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 331
 332         if (HAS_PCH_SPLIT(dev))
 333                 return PCH_PP_STATUS;
 334         else
 335                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 336 }
 337
 338 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 339    This function only applicable when panel PM state is not to be tracked */
 340 #if 0
 341 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 342                               void *unused)
 343 {
 344         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 345                                                  edp_notifier);
 346         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 347         struct drm_i915_private *dev_priv = dev->dev_private;
 348         u32 pp_div;
 349         u32 pp_ctrl_reg, pp_div_reg;
 350         enum i915_pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 351
 352         if (!is_edp(intel_dp) || code != SYS_RESTART)
 353                 return 0;
 354
 355         if (IS_VALLEYVIEW(dev)) {
 356                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
 357                 pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
 358                 pp_div = I915_READ(pp_div_reg);
 359                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 360
 361                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 362                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 363                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 364                 msleep(intel_dp->panel_power_cycle_delay);
 365         }
 366
 367         return 0;
 368 }
 369 #endif
 370
 371 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 372 {
 373         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 374         struct drm_i915_private *dev_priv = dev->dev_private;
 375
 376         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 377 }
 378
 379 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 380 {
 381         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 382         struct drm_i915_private *dev_priv = dev->dev_private;
 383         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 384         struct intel_encoder *intel_encoder = &intel_dig_port->base;
 385         enum intel_display_power_domain power_domain;
 386
 387         power_domain = intel_display_port_power_domain(intel_encoder);
 388         return intel_display_power_enabled(dev_priv, power_domain) &&
 389                (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
 390 }
 391
 392 static void
 393 intel_dp_check_edp(struct intel_dp *intel_dp)
 394 {
 395         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 396         struct drm_i915_private *dev_priv = dev->dev_private;
 397
 398         if (!is_edp(intel_dp))
 399                 return;
 400
 401         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 402                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 403                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 404                               I915_READ(_pp_stat_reg(intel_dp)),
 405                               I915_READ(_pp_ctrl_reg(intel_dp)));
 406         }
 407 }
 408
 409 static uint32_t
 410 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 411 {
 412         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 413         struct drm_device *dev = intel_dig_port->base.base.dev;
 414         struct drm_i915_private *dev_priv = dev->dev_private;
 415         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 416         uint32_t status;
 417         bool done;
 418
 419 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 420         if (has_aux_irq)
 421                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 422                                           msecs_to_jiffies_timeout(10));
 423         else
 424                 done = wait_for_atomic(C, 10) == 0;
 425         if (!done)
 426                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 427                           has_aux_irq);
 428 #undef C
 429
 430         return status;
 431 }
 432
 433 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 434 {
 435         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 436         struct drm_device *dev = intel_dig_port->base.base.dev;
 437
 438         /*
 439          * The clock divider is based off the hrawclk, and would like to run at
 440          * 2MHz.  So, take the hrawclk value and divide by 2 and use that
 441          */
 442         return index ? 0 : intel_hrawclk(dev) / 2;
 443 }
 444
 445 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 446 {
 447         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 448         struct drm_device *dev = intel_dig_port->base.base.dev;
 449
 450         if (index)
 451                 return 0;
 452
 453         if (intel_dig_port->port == PORT_A) {
 454                 if (IS_GEN6(dev) || IS_GEN7(dev))
 455                         return 200; /* SNB & IVB eDP input clock at 400Mhz */
 456                 else
 457                         return 225; /* eDP input clock at 450Mhz */
 458         } else {
 459                 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 460         }
 461 }
 462
 463 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 464 {
 465         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 466         struct drm_device *dev = intel_dig_port->base.base.dev;
 467         struct drm_i915_private *dev_priv = dev->dev_private;
 468
 469         if (intel_dig_port->port == PORT_A) {
 470                 if (index)
 471                         return 0;
 472                 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
 473         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 474                 /* Workaround for non-ULT HSW */
 475                 switch (index) {
 476                 case 0: return 63;
 477                 case 1: return 72;
 478                 default: return 0;
 479                 }
 480         } else  {
 481                 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 482         }
 483 }
 484
 485 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 486 {
 487         return index ? 0 : 100;
 488 }
 489
 490 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
 491                                       bool has_aux_irq,
 492                                       int send_bytes,
 493                                       uint32_t aux_clock_divider)
 494 {
 495         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 496         struct drm_device *dev = intel_dig_port->base.base.dev;
 497         uint32_t precharge, timeout;
 498
 499         if (IS_GEN6(dev))
 500                 precharge = 3;
 501         else
 502                 precharge = 5;
 503
 504         if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
 505                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 506         else
 507                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 508
 509         return DP_AUX_CH_CTL_SEND_BUSY |
 510                DP_AUX_CH_CTL_DONE |
 511                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 512                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 513                timeout |
 514                DP_AUX_CH_CTL_RECEIVE_ERROR |
 515                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 516                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 517                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 518 }
 519
 520 static int
 521 intel_dp_aux_ch(struct intel_dp *intel_dp,
 522                 uint8_t *send, int send_bytes,
 523                 uint8_t *recv, int recv_size)
 524 {
 525         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 526         struct drm_device *dev = intel_dig_port->base.base.dev;
 527         struct drm_i915_private *dev_priv = dev->dev_private;
 528         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 529         uint32_t ch_data = ch_ctl + 4;
 530         uint32_t aux_clock_divider;
 531         int i, ret, recv_bytes;
 532         uint32_t status;
 533         int try, clock = 0;
 534         bool has_aux_irq = HAS_AUX_IRQ(dev);
 535
 536         /* dp aux is extremely sensitive to irq latency, hence request the
 537          * lowest possible wakeup latency and so prevent the cpu from going into
 538          * deep sleep states.
 539          */
 540         pm_qos_update_request(&dev_priv->pm_qos, 0);
 541
 542         intel_dp_check_edp(intel_dp);
 543
 544         intel_aux_display_runtime_get(dev_priv);
 545
 546         /* Try to wait for any previous AUX channel activity */
 547         for (try = 0; try < 3; try++) {
 548                 status = I915_READ_NOTRACE(ch_ctl);
 549                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 550                         break;
 551                 msleep(1);
 552         }
 553
 554         if (try == 3) {
 555                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 556                      I915_READ(ch_ctl));
 557                 ret = -EBUSY;
 558                 goto out;
 559         }
 560
 561         /* Only 5 data registers! */
 562         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 563                 ret = -E2BIG;
 564                 goto out;
 565         }
 566
 567         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 568                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
 569                                                           has_aux_irq,
 570                                                           send_bytes,
 571                                                           aux_clock_divider);
 572
 573                 /* Must try at least 3 times according to DP spec */
 574                 for (try = 0; try < 5; try++) {
 575                         /* Load the send data into the aux channel data registers */
 576                         for (i = 0; i < send_bytes; i += 4)
 577                                 I915_WRITE(ch_data + i,
 578                                            pack_aux(send + i, send_bytes - i));
 579
 580                         /* Send the command and wait for it to complete */
 581                         I915_WRITE(ch_ctl, send_ctl);
 582
 583                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 584
 585                         /* Clear done status and any errors */
 586                         I915_WRITE(ch_ctl,
 587                                    status |
 588                                    DP_AUX_CH_CTL_DONE |
 589                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 590                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 591
 592                         if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 593                                       DP_AUX_CH_CTL_RECEIVE_ERROR))
 594                                 continue;
 595                         if (status & DP_AUX_CH_CTL_DONE)
 596                                 break;
 597                 }
 598                 if (status & DP_AUX_CH_CTL_DONE)
 599                         break;
 600         }
 601
 602         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 603                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 604                 ret = -EBUSY;
 605                 goto out;
 606         }
 607
 608         /* Check for timeout or receive error.
 609          * Timeouts occur when the sink is not connected
 610          */
 611         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 612                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 613                 ret = -EIO;
 614                 goto out;
 615         }
 616
 617         /* Timeouts occur when the device isn't connected, so they're
 618          * "normal" -- don't fill the kernel log with these */
 619         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 620                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 621                 ret = -ETIMEDOUT;
 622                 goto out;
 623         }
 624
 625         /* Unload any bytes sent back from the other side */
 626         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 627                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 628         if (recv_bytes > recv_size)
 629                 recv_bytes = recv_size;
 630
 631         for (i = 0; i < recv_bytes; i += 4)
 632                 unpack_aux(I915_READ(ch_data + i),
 633                            recv + i, recv_bytes - i);
 634
 635         ret = recv_bytes;
 636 out:
 637         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 638         intel_aux_display_runtime_put(dev_priv);
 639
 640         return ret;
 641 }
 642
 643 #define BARE_ADDRESS_SIZE       3
 644 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
 645 static ssize_t
 646 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 647 {
 648         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
 649         uint8_t txbuf[20], rxbuf[20];
 650         size_t txsize, rxsize;
 651         int ret;
 652
 653         txbuf[0] = msg->request << 4;
 654         txbuf[1] = msg->address >> 8;
 655         txbuf[2] = msg->address & 0xff;
 656         txbuf[3] = msg->size - 1;
 657
 658         switch (msg->request & ~DP_AUX_I2C_MOT) {
 659         case DP_AUX_NATIVE_WRITE:
 660         case DP_AUX_I2C_WRITE:
 661                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
 662                 rxsize = 1;
 663
 664                 if (WARN_ON(txsize > 20))
 665                         return -E2BIG;
 666
 667                 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
 668
 669                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 670                 if (ret > 0) {
 671                         msg->reply = rxbuf[0] >> 4;
 672
 673                         /* Return payload size. */
 674                         ret = msg->size;
 675                 }
 676                 break;
 677
 678         case DP_AUX_NATIVE_READ:
 679         case DP_AUX_I2C_READ:
 680                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
 681                 rxsize = msg->size + 1;
 682
 683                 if (WARN_ON(rxsize > 20))
 684                         return -E2BIG;
 685
 686                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 687                 if (ret > 0) {
 688                         msg->reply = rxbuf[0] >> 4;
 689                         /*
 690                          * Assume happy day, and copy the data. The caller is
 691                          * expected to check msg->reply before touching it.
 692                          *
 693                          * Return payload size.
 694                          */
 695                         ret--;
 696                         memcpy(msg->buffer, rxbuf + 1, ret);
 697                 }
 698                 break;
 699
 700         default:
 701                 ret = -EINVAL;
 702                 break;
 703         }
 704
 705         return ret;
 706 }
 707
 708 /* Write data to the aux channel in native mode */
 709 static int
 710 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 711                           uint16_t address, uint8_t *send, int send_bytes)
 712 {
 713         int ret;
 714         uint8_t msg[20];
 715         int msg_bytes;
 716         uint8_t ack;
 717         int retry;
 718
 719         if (WARN_ON(send_bytes > 16))
 720                 return -E2BIG;
 721
 722         intel_dp_check_edp(intel_dp);
 723         msg[0] = DP_AUX_NATIVE_WRITE << 4;
 724         msg[1] = address >> 8;
 725         msg[2] = address & 0xff;
 726         msg[3] = send_bytes - 1;
 727         memcpy(&msg[4], send, send_bytes);
 728         msg_bytes = send_bytes + 4;
 729         for (retry = 0; retry < 7; retry++) {
 730                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 731                 if (ret < 0)
 732                         return ret;
 733                 ack >>= 4;
 734                 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
 735                         return send_bytes;
 736                 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
 737                         usleep_range(400, 500);
 738                 else
 739                         return -EIO;
 740         }
 741
 742         DRM_ERROR("too many retries, giving up\n");
 743         return -EIO;
 744 }
 745
 746 /* Write a single byte to the aux channel in native mode */
 747 static int
 748 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 749                             uint16_t address, uint8_t byte)
 750 {
 751         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 752 }
 753
 754 /* read bytes from a native aux channel */
 755 static int
 756 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 757                          uint16_t address, uint8_t *recv, int recv_bytes)
 758 {
 759         uint8_t msg[4];
 760         int msg_bytes;
 761         uint8_t reply[20];
 762         int reply_bytes;
 763         uint8_t ack;
 764         int ret;
 765         int retry;
 766
 767         if (WARN_ON(recv_bytes > 19))
 768                 return -E2BIG;
 769
 770         intel_dp_check_edp(intel_dp);
 771         msg[0] = DP_AUX_NATIVE_READ << 4;
 772         msg[1] = address >> 8;
 773         msg[2] = address & 0xff;
 774         msg[3] = recv_bytes - 1;
 775
 776         msg_bytes = 4;
 777         reply_bytes = recv_bytes + 1;
 778
 779         for (retry = 0; retry < 7; retry++) {
 780                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 781                                       reply, reply_bytes);
 782                 if (ret == 0)
 783                         return -EPROTO;
 784                 if (ret < 0)
 785                         return ret;
 786                 ack = reply[0] >> 4;
 787                 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) {
 788                         memcpy(recv, reply + 1, ret - 1);
 789                         return ret - 1;
 790                 }
 791                 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
 792                         usleep_range(400, 500);
 793                 else
 794                         return -EIO;
 795         }
 796
 797         DRM_ERROR("too many retries, giving up\n");
 798         return -EIO;
 799 }
 800
 801 static int
 802 intel_dp_i2c_aux_ch(struct device *adapter, int mode,
 803                     uint8_t write_byte, uint8_t *read_byte)
 804 {
 805         struct i2c_algo_dp_aux_data *data = device_get_softc(adapter);
 806         struct intel_dp *intel_dp = data->priv;
 807         uint16_t address = data->address;
 808         uint8_t msg[5];
 809         uint8_t reply[2];
 810         unsigned retry;
 811         int msg_bytes;
 812         int reply_bytes;
 813         int ret;
 814
 815         intel_edp_panel_vdd_on(intel_dp);
 816         intel_dp_check_edp(intel_dp);
 817         /* Set up the command byte */
 818         if (mode & MODE_I2C_READ)
 819                 msg[0] = DP_AUX_I2C_READ << 4;
 820         else
 821                 msg[0] = DP_AUX_I2C_WRITE << 4;
 822
 823         if (!(mode & MODE_I2C_STOP))
 824                 msg[0] |= DP_AUX_I2C_MOT << 4;
 825
 826         msg[1] = address >> 8;
 827         msg[2] = address;
 828
 829         switch (mode) {
 830         case MODE_I2C_WRITE:
 831                 msg[3] = 0;
 832                 msg[4] = write_byte;
 833                 msg_bytes = 5;
 834                 reply_bytes = 1;
 835                 break;
 836         case MODE_I2C_READ:
 837                 msg[3] = 0;
 838                 msg_bytes = 4;
 839                 reply_bytes = 2;
 840                 break;
 841         default:
 842                 msg_bytes = 3;
 843                 reply_bytes = 1;
 844                 break;
 845         }
 846
 847         /*
 848          * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
 849          * required to retry at least seven times upon receiving AUX_DEFER
 850          * before giving up the AUX transaction.
 851          */
 852         for (retry = 0; retry < 7; retry++) {
 853                 ret = intel_dp_aux_ch(intel_dp,
 854                                       msg, msg_bytes,
 855                                       reply, reply_bytes);
 856                 if (ret < 0) {
 857                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 858                         goto out;
 859                 }
 860
 861                 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
 862                 case DP_AUX_NATIVE_REPLY_ACK:
 863                         /* I2C-over-AUX Reply field is only valid
 864                          * when paired with AUX ACK.
 865                          */
 866                         break;
 867                 case DP_AUX_NATIVE_REPLY_NACK:
 868                         DRM_DEBUG_KMS("aux_ch native nack\n");
 869                         ret = -EREMOTEIO;
 870                         goto out;
 871                 case DP_AUX_NATIVE_REPLY_DEFER:
 872                         /*
 873                          * For now, just give more slack to branch devices. We
 874                          * could check the DPCD for I2C bit rate capabilities,
 875                          * and if available, adjust the interval. We could also
 876                          * be more careful with DP-to-Legacy adapters where a
 877                          * long legacy cable may force very low I2C bit rates.
 878                          */
 879                         if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
 880                             DP_DWN_STRM_PORT_PRESENT)
 881                                 usleep_range(500, 600);
 882                         else
 883                                 usleep_range(300, 400);
 884                         continue;
 885                 default:
 886                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 887                                   reply[0]);
 888                         ret = -EREMOTEIO;
 889                         goto out;
 890                 }
 891
 892                 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) {
 893                 case DP_AUX_I2C_REPLY_ACK:
 894                         if (mode == MODE_I2C_READ) {
 895                                 *read_byte = reply[1];
 896                         }
 897                         ret = 0;        /* reply_bytes - 1 */
 898                         goto out;
 899                 case DP_AUX_I2C_REPLY_NACK:
 900                         DRM_DEBUG_KMS("aux_i2c nack\n");
 901                         ret = -EREMOTEIO;
 902                         goto out;
 903                 case DP_AUX_I2C_REPLY_DEFER:
 904                         DRM_DEBUG_KMS("aux_i2c defer\n");
 905                         udelay(100);
 906                         break;
 907                 default:
 908                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 909                         ret = -EREMOTEIO;
 910                         goto out;
 911                 }
 912         }
 913
 914         DRM_ERROR("too many retries, giving up\n");
 915         ret = -EREMOTEIO;
 916
 917 out:
 918         return ret;
 919 }
 920
 921 static void
 922 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
 923 {
 924         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 925         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 926         enum port port = intel_dig_port->port;
 927         const char *name = NULL;
 928         int ret;
 929
 930         switch (port) {
 931         case PORT_A:
 932                 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
 933                 name = "DPDDC-A";
 934                 break;
 935         case PORT_B:
 936                 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
 937                 name = "DPDDC-B";
 938                 break;
 939         case PORT_C:
 940                 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
 941                 name = "DPDDC-C";
 942                 break;
 943         case PORT_D:
 944                 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
 945                 name = "DPDDC-D";
 946                 break;
 947         default:
 948                 BUG();
 949         }
 950
 951         if (!HAS_DDI(dev))
 952                 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
 953
 954         intel_dp->aux.name = name;
 955         intel_dp->aux.dev = dev->dev;
 956         intel_dp->aux.transfer = intel_dp_aux_transfer;
 957
 958         DRM_DEBUG_KMS("i2c_init %s\n", name);
 959         ret = iic_dp_aux_add_bus(connector->base.dev->dev, name,
 960             intel_dp_i2c_aux_ch, intel_dp, &intel_dp->dp_iic_bus,
 961             &intel_dp->aux.ddc);
 962         WARN(ret, "intel_dp_i2c_init failed with error %d for port %c\n",
 963              ret, port_name(port));
 964
 965 }
 966
 967 static void
 968 intel_dp_connector_unregister(struct intel_connector *intel_connector)
 969 {
 970         intel_connector_unregister(intel_connector);
 971 }
 972
 973 #if 0
 974 static int
 975 intel_dp_i2c_init(struct intel_dp *intel_dp,
 976                   struct intel_connector *intel_connector, const char *name)
 977 {
 978         int     ret;
 979
 980         DRM_DEBUG_KMS("i2c_init %s\n", name);
 981 #if 0
 982         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 983         intel_dp->adapter.owner = THIS_MODULE;
 984         intel_dp->adapter.class = I2C_CLASS_DDC;
 985         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 986         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 987         intel_dp->adapter.algo_data = &intel_dp->algo;
 988         intel_dp->adapter.dev.parent = intel_connector->base.dev->dev;
 989
 990         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 991         if (ret < 0)
 992                 return ret;
 993
 994         ret = sysfs_create_link(&intel_connector->base.kdev->kobj,
 995                                 &intel_dp->adapter.dev.kobj,
 996                                 intel_dp->adapter.dev.kobj.name);
 997 #endif
 998         ret = iic_dp_aux_add_bus(intel_connector->base.dev->dev, name,
 999             intel_dp_i2c_aux_ch, intel_dp, &intel_dp->dp_iic_bus,
1000             &intel_dp->adapter);
1001
1002         return ret;
1003 }
1004 #endif
1005
1006 static void
1007 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
1008 {
1009         switch (link_bw) {
1010         case DP_LINK_BW_1_62:
1011                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1012                 break;
1013         case DP_LINK_BW_2_7:
1014                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1015                 break;
1016         case DP_LINK_BW_5_4:
1017                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1018                 break;
1019         }
1020 }
1021
1022 static void
1023 intel_dp_set_clock(struct intel_encoder *encoder,
1024                    struct intel_crtc_config *pipe_config, int link_bw)
1025 {
1026         struct drm_device *dev = encoder->base.dev;
1027         const struct dp_link_dpll *divisor = NULL;
1028         int i, count = 0;
1029
1030         if (IS_G4X(dev)) {
1031                 divisor = gen4_dpll;
1032                 count = ARRAY_SIZE(gen4_dpll);
1033         } else if (HAS_PCH_SPLIT(dev)) {
1034                 divisor = pch_dpll;
1035                 count = ARRAY_SIZE(pch_dpll);
1036         } else if (IS_CHERRYVIEW(dev)) {
1037                 divisor = chv_dpll;
1038                 count = ARRAY_SIZE(chv_dpll);
1039         } else if (IS_VALLEYVIEW(dev)) {
1040                 divisor = vlv_dpll;
1041                 count = ARRAY_SIZE(vlv_dpll);
1042         }
1043
1044         if (divisor && count) {
1045                 for (i = 0; i < count; i++) {
1046                         if (link_bw == divisor[i].link_bw) {
1047                                 pipe_config->dpll = divisor[i].dpll;
1048                                 pipe_config->clock_set = true;
1049                                 break;
1050                         }
1051                 }
1052         }
1053 }
1054
1055 static void
1056 intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
1057 {
1058         struct drm_device *dev = crtc->base.dev;
1059         struct drm_i915_private *dev_priv = dev->dev_private;
1060         enum transcoder transcoder = crtc->config.cpu_transcoder;
1061
1062         I915_WRITE(PIPE_DATA_M2(transcoder),
1063                 TU_SIZE(m_n->tu) | m_n->gmch_m);
1064         I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
1065         I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
1066         I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
1067 }
1068
1069 bool
1070 intel_dp_compute_config(struct intel_encoder *encoder,
1071                         struct intel_crtc_config *pipe_config)
1072 {
1073         struct drm_device *dev = encoder->base.dev;
1074         struct drm_i915_private *dev_priv = dev->dev_private;
1075         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
1076         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1077         enum port port = dp_to_dig_port(intel_dp)->port;
1078         struct intel_crtc *intel_crtc = encoder->new_crtc;
1079         struct intel_connector *intel_connector = intel_dp->attached_connector;
1080         int lane_count, clock;
1081         int min_lane_count = 1;
1082         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1083         /* Conveniently, the link BW constants become indices with a shift...*/
1084         int min_clock = 0;
1085         int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
1086         int bpp, mode_rate;
1087         static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
1088         int link_avail, link_clock;
1089
1090         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1091                 pipe_config->has_pch_encoder = true;
1092
1093         pipe_config->has_dp_encoder = true;
1094         pipe_config->has_audio = intel_dp->has_audio;
1095
1096         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1097                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1098                                        adjusted_mode);
1099                 if (!HAS_PCH_SPLIT(dev))
1100                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1101                                                  intel_connector->panel.fitting_mode);
1102                 else
1103                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1104                                                 intel_connector->panel.fitting_mode);
1105         }
1106
1107         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1108                 return false;
1109
1110         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1111                       "max bw %02x pixel clock %iKHz\n",
1112                       max_lane_count, bws[max_clock],
1113                       adjusted_mode->crtc_clock);
1114
1115         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1116          * bpc in between. */
1117         bpp = pipe_config->pipe_bpp;
1118         if (is_edp(intel_dp)) {
1119                 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1120                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1121                                       dev_priv->vbt.edp_bpp);
1122                         bpp = dev_priv->vbt.edp_bpp;
1123                 }
1124
1125                 if (IS_BROADWELL(dev)) {
1126                         /* Yes, it's an ugly hack. */
1127                         min_lane_count = max_lane_count;
1128                         DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
1129                                       min_lane_count);
1130                 } else if (dev_priv->vbt.edp_lanes) {
1131                         min_lane_count = min(dev_priv->vbt.edp_lanes,
1132                                              max_lane_count);
1133                         DRM_DEBUG_KMS("using min %u lanes per VBT\n",
1134                                       min_lane_count);
1135                 }
1136
1137                 if (dev_priv->vbt.edp_rate) {
1138                         min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
1139                         DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
1140                                       bws[min_clock]);
1141                 }
1142         }
1143
1144         for (; bpp >= 6*3; bpp -= 2*3) {
1145                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1146                                                    bpp);
1147
1148                 for (clock = min_clock; clock <= max_clock; clock++) {
1149                         for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
1150                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1151                                 link_avail = intel_dp_max_data_rate(link_clock,
1152                                                                     lane_count);
1153
1154                                 if (mode_rate <= link_avail) {
1155                                         goto found;
1156                                 }
1157                         }
1158                 }
1159         }
1160
1161         return false;
1162
1163 found:
1164         if (intel_dp->color_range_auto) {
1165                 /*
1166                  * See:
1167                  * CEA-861-E - 5.1 Default Encoding Parameters
1168                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1169                  */
1170                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
1171                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
1172                 else
1173                         intel_dp->color_range = 0;
1174         }
1175
1176         if (intel_dp->color_range)
1177                 pipe_config->limited_color_range = true;
1178
1179         intel_dp->link_bw = bws[clock];
1180         intel_dp->lane_count = lane_count;
1181         pipe_config->pipe_bpp = bpp;
1182         pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
1183
1184         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1185                       intel_dp->link_bw, intel_dp->lane_count,
1186                       pipe_config->port_clock, bpp);
1187         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1188                       mode_rate, link_avail);
1189
1190         intel_link_compute_m_n(bpp, lane_count,
1191                                adjusted_mode->crtc_clock,
1192                                pipe_config->port_clock,
1193                                &pipe_config->dp_m_n);
1194
1195         if (intel_connector->panel.downclock_mode != NULL &&
1196                 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
1197                         intel_link_compute_m_n(bpp, lane_count,
1198                                 intel_connector->panel.downclock_mode->clock,
1199                                 pipe_config->port_clock,
1200                                 &pipe_config->dp_m2_n2);
1201         }
1202
1203         if (HAS_DDI(dev))
1204                 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1205         else
1206                 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
1207
1208         return true;
1209 }
1210
1211 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
1212 {
1213         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1214         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1215         struct drm_device *dev = crtc->base.dev;
1216         struct drm_i915_private *dev_priv = dev->dev_private;
1217         u32 dpa_ctl;
1218
1219         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
1220         dpa_ctl = I915_READ(DP_A);
1221         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1222
1223         if (crtc->config.port_clock == 162000) {
1224                 /* For a long time we've carried around a ILK-DevA w/a for the
1225                  * 160MHz clock. If we're really unlucky, it's still required.
1226                  */
1227                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1228                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1229                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
1230         } else {
1231                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1232                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1233         }
1234
1235         I915_WRITE(DP_A, dpa_ctl);
1236
1237         POSTING_READ(DP_A);
1238         udelay(500);
1239 }
1240
1241 static void intel_dp_prepare(struct intel_encoder *encoder)
1242 {
1243         struct drm_device *dev = encoder->base.dev;
1244         struct drm_i915_private *dev_priv = dev->dev_private;
1245         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1246         enum port port = dp_to_dig_port(intel_dp)->port;
1247         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1248         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
1249
1250         /*
1251          * There are four kinds of DP registers:
1252          *
1253          *      IBX PCH
1254          *      SNB CPU
1255          *      IVB CPU
1256          *      CPT PCH
1257          *
1258          * IBX PCH and CPU are the same for almost everything,
1259          * except that the CPU DP PLL is configured in this
1260          * register
1261          *
1262          * CPT PCH is quite different, having many bits moved
1263          * to the TRANS_DP_CTL register instead. That
1264          * configuration happens (oddly) in ironlake_pch_enable
1265          */
1266
1267         /* Preserve the BIOS-computed detected bit. This is
1268          * supposed to be read-only.
1269          */
1270         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1271
1272         /* Handle DP bits in common between all three register formats */
1273         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1274         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1275
1276         if (crtc->config.has_audio) {
1277                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1278                                  pipe_name(crtc->pipe));
1279                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1280                 intel_write_eld(&encoder->base, adjusted_mode);
1281         }
1282
1283         /* Split out the IBX/CPU vs CPT settings */
1284
1285         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1286                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1287                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1288                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1289                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1290                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1291
1292                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1293                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1294
1295                 intel_dp->DP |= crtc->pipe << 29;
1296         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1297                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1298                         intel_dp->DP |= intel_dp->color_range;
1299
1300                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1301                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1302                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1303                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1304                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1305
1306                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1307                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1308
1309                 if (!IS_CHERRYVIEW(dev)) {
1310                         if (crtc->pipe == 1)
1311                                 intel_dp->DP |= DP_PIPEB_SELECT;
1312                 } else {
1313                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1314                 }
1315         } else {
1316                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1317         }
1318 }
1319
1320 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1321 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1322
1323 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1324 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1325
1326 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1327 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1328
1329 static void wait_panel_status(struct intel_dp *intel_dp,
1330                                        u32 mask,
1331                                        u32 value)
1332 {
1333         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1334         struct drm_i915_private *dev_priv = dev->dev_private;
1335         u32 pp_stat_reg, pp_ctrl_reg;
1336
1337         pp_stat_reg = _pp_stat_reg(intel_dp);
1338         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1339
1340         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1341                         mask, value,
1342                         I915_READ(pp_stat_reg),
1343                         I915_READ(pp_ctrl_reg));
1344
1345         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1346                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1347                                 I915_READ(pp_stat_reg),
1348                                 I915_READ(pp_ctrl_reg));
1349         }
1350
1351         DRM_DEBUG_KMS("Wait complete\n");
1352 }
1353
1354 static void wait_panel_on(struct intel_dp *intel_dp)
1355 {
1356         DRM_DEBUG_KMS("Wait for panel power on\n");
1357         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1358 }
1359
1360 static void wait_panel_off(struct intel_dp *intel_dp)
1361 {
1362         DRM_DEBUG_KMS("Wait for panel power off time\n");
1363         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1364 }
1365
1366 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1367 {
1368         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1369
1370         /* When we disable the VDD override bit last we have to do the manual
1371          * wait. */
1372         wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1373                                        intel_dp->panel_power_cycle_delay);
1374
1375         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1376 }
1377
1378 static void wait_backlight_on(struct intel_dp *intel_dp)
1379 {
1380         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1381                                        intel_dp->backlight_on_delay);
1382 }
1383
1384 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1385 {
1386         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1387                                        intel_dp->backlight_off_delay);
1388 }
1389
1390 /* Read the current pp_control value, unlocking the register if it
1391  * is locked
1392  */
1393
1394 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1395 {
1396         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1397         struct drm_i915_private *dev_priv = dev->dev_private;
1398         u32 control;
1399
1400         control = I915_READ(_pp_ctrl_reg(intel_dp));
1401         control &= ~PANEL_UNLOCK_MASK;
1402         control |= PANEL_UNLOCK_REGS;
1403         return control;
1404 }
1405
1406 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1407 {
1408         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1409         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1410         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1411         struct drm_i915_private *dev_priv = dev->dev_private;
1412         enum intel_display_power_domain power_domain;
1413         u32 pp;
1414         u32 pp_stat_reg, pp_ctrl_reg;
1415
1416         if (!is_edp(intel_dp))
1417                 return;
1418
1419         WARN(intel_dp->want_panel_vdd,
1420              "eDP VDD already requested on\n");
1421
1422         intel_dp->want_panel_vdd = true;
1423
1424         if (edp_have_panel_vdd(intel_dp))
1425                 return;
1426
1427         power_domain = intel_display_port_power_domain(intel_encoder);
1428         intel_display_power_get(dev_priv, power_domain);
1429
1430         DRM_DEBUG_KMS("Turning eDP VDD on\n");
1431
1432         if (!edp_have_panel_power(intel_dp))
1433                 wait_panel_power_cycle(intel_dp);
1434
1435         pp = ironlake_get_pp_control(intel_dp);
1436         pp |= EDP_FORCE_VDD;
1437
1438         pp_stat_reg = _pp_stat_reg(intel_dp);
1439         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1440
1441         I915_WRITE(pp_ctrl_reg, pp);
1442         POSTING_READ(pp_ctrl_reg);
1443         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1444                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1445         /*
1446          * If the panel wasn't on, delay before accessing aux channel
1447          */
1448         if (!edp_have_panel_power(intel_dp)) {
1449                 DRM_DEBUG_KMS("eDP was not running\n");
1450                 msleep(intel_dp->panel_power_up_delay);
1451         }
1452 }
1453
1454 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1455 {
1456         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1457         struct drm_i915_private *dev_priv = dev->dev_private;
1458         u32 pp;
1459         u32 pp_stat_reg, pp_ctrl_reg;
1460
1461         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1462
1463         if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
1464                 struct intel_digital_port *intel_dig_port =
1465                                                 dp_to_dig_port(intel_dp);
1466                 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1467                 enum intel_display_power_domain power_domain;
1468
1469                 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1470
1471                 pp = ironlake_get_pp_control(intel_dp);
1472                 pp &= ~EDP_FORCE_VDD;
1473
1474                 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1475                 pp_stat_reg = _pp_stat_reg(intel_dp);
1476
1477                 I915_WRITE(pp_ctrl_reg, pp);
1478                 POSTING_READ(pp_ctrl_reg);
1479
1480                 /* Make sure sequencer is idle before allowing subsequent activity */
1481                 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1482                 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1483
1484                 if ((pp & POWER_TARGET_ON) == 0)
1485                         intel_dp->last_power_cycle = jiffies;
1486
1487                 power_domain = intel_display_port_power_domain(intel_encoder);
1488                 intel_display_power_put(dev_priv, power_domain);
1489         }
1490 }
1491
1492 static void edp_panel_vdd_work(struct work_struct *__work)
1493 {
1494         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1495                                                  struct intel_dp, panel_vdd_work);
1496         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1497
1498         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1499         edp_panel_vdd_off_sync(intel_dp);
1500         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1501 }
1502
1503 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1504 {
1505         unsigned long delay;
1506
1507         /*
1508          * Queue the timer to fire a long time from now (relative to the power
1509          * down delay) to keep the panel power up across a sequence of
1510          * operations.
1511          */
1512         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1513         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1514 }
1515
1516 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1517 {
1518         if (!is_edp(intel_dp))
1519                 return;
1520
1521         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1522
1523         intel_dp->want_panel_vdd = false;
1524
1525         if (sync)
1526                 edp_panel_vdd_off_sync(intel_dp);
1527         else
1528                 edp_panel_vdd_schedule_off(intel_dp);
1529 }
1530
1531 void intel_edp_panel_on(struct intel_dp *intel_dp)
1532 {
1533         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1534         struct drm_i915_private *dev_priv = dev->dev_private;
1535         u32 pp;
1536         u32 pp_ctrl_reg;
1537
1538         if (!is_edp(intel_dp))
1539                 return;
1540
1541         DRM_DEBUG_KMS("Turn eDP power on\n");
1542
1543         if (edp_have_panel_power(intel_dp)) {
1544                 DRM_DEBUG_KMS("eDP power already on\n");
1545                 return;
1546         }
1547
1548         wait_panel_power_cycle(intel_dp);
1549
1550         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1551         pp = ironlake_get_pp_control(intel_dp);
1552         if (IS_GEN5(dev)) {
1553                 /* ILK workaround: disable reset around power sequence */
1554                 pp &= ~PANEL_POWER_RESET;
1555                 I915_WRITE(pp_ctrl_reg, pp);
1556                 POSTING_READ(pp_ctrl_reg);
1557         }
1558
1559         pp |= POWER_TARGET_ON;
1560         if (!IS_GEN5(dev))
1561                 pp |= PANEL_POWER_RESET;
1562
1563         I915_WRITE(pp_ctrl_reg, pp);
1564         POSTING_READ(pp_ctrl_reg);
1565
1566         wait_panel_on(intel_dp);
1567         intel_dp->last_power_on = jiffies;
1568
1569         if (IS_GEN5(dev)) {
1570                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1571                 I915_WRITE(pp_ctrl_reg, pp);
1572                 POSTING_READ(pp_ctrl_reg);
1573         }
1574 }
1575
1576 void intel_edp_panel_off(struct intel_dp *intel_dp)
1577 {
1578         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1579         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1580         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1581         struct drm_i915_private *dev_priv = dev->dev_private;
1582         enum intel_display_power_domain power_domain;
1583         u32 pp;
1584         u32 pp_ctrl_reg;
1585
1586         if (!is_edp(intel_dp))
1587                 return;
1588
1589         DRM_DEBUG_KMS("Turn eDP power off\n");
1590
1591         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1592
1593         pp = ironlake_get_pp_control(intel_dp);
1594         /* We need to switch off panel power _and_ force vdd, for otherwise some
1595          * panels get very unhappy and cease to work. */
1596         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1597                 EDP_BLC_ENABLE);
1598
1599         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1600
1601         intel_dp->want_panel_vdd = false;
1602
1603         I915_WRITE(pp_ctrl_reg, pp);
1604         POSTING_READ(pp_ctrl_reg);
1605
1606         intel_dp->last_power_cycle = jiffies;
1607         wait_panel_off(intel_dp);
1608
1609         /* We got a reference when we enabled the VDD. */
1610         power_domain = intel_display_port_power_domain(intel_encoder);
1611         intel_display_power_put(dev_priv, power_domain);
1612 }
1613
1614 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1615 {
1616         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1617         struct drm_device *dev = intel_dig_port->base.base.dev;
1618         struct drm_i915_private *dev_priv = dev->dev_private;
1619         u32 pp;
1620         u32 pp_ctrl_reg;
1621
1622         if (!is_edp(intel_dp))
1623                 return;
1624
1625         DRM_DEBUG_KMS("\n");
1626
1627         intel_panel_enable_backlight(intel_dp->attached_connector);
1628
1629         /*
1630          * If we enable the backlight right away following a panel power
1631          * on, we may see slight flicker as the panel syncs with the eDP
1632          * link.  So delay a bit to make sure the image is solid before
1633          * allowing it to appear.
1634          */
1635         wait_backlight_on(intel_dp);
1636         pp = ironlake_get_pp_control(intel_dp);
1637         pp |= EDP_BLC_ENABLE;
1638
1639         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1640
1641         I915_WRITE(pp_ctrl_reg, pp);
1642         POSTING_READ(pp_ctrl_reg);
1643 }
1644
1645 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1646 {
1647         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1648         struct drm_i915_private *dev_priv = dev->dev_private;
1649         u32 pp;
1650         u32 pp_ctrl_reg;
1651
1652         if (!is_edp(intel_dp))
1653                 return;
1654
1655         DRM_DEBUG_KMS("\n");
1656         pp = ironlake_get_pp_control(intel_dp);
1657         pp &= ~EDP_BLC_ENABLE;
1658
1659         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1660
1661         I915_WRITE(pp_ctrl_reg, pp);
1662         POSTING_READ(pp_ctrl_reg);
1663         intel_dp->last_backlight_off = jiffies;
1664
1665         edp_wait_backlight_off(intel_dp);
1666
1667         intel_panel_disable_backlight(intel_dp->attached_connector);
1668 }
1669
1670 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1671 {
1672         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1673         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1674         struct drm_device *dev = crtc->dev;
1675         struct drm_i915_private *dev_priv = dev->dev_private;
1676         u32 dpa_ctl;
1677
1678         assert_pipe_disabled(dev_priv,
1679                              to_intel_crtc(crtc)->pipe);
1680
1681         DRM_DEBUG_KMS("\n");
1682         dpa_ctl = I915_READ(DP_A);
1683         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1684         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1685
1686         /* We don't adjust intel_dp->DP while tearing down the link, to
1687          * facilitate link retraining (e.g. after hotplug). Hence clear all
1688          * enable bits here to ensure that we don't enable too much. */
1689         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1690         intel_dp->DP |= DP_PLL_ENABLE;
1691         I915_WRITE(DP_A, intel_dp->DP);
1692         POSTING_READ(DP_A);
1693         udelay(200);
1694 }
1695
1696 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1697 {
1698         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1699         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1700         struct drm_device *dev = crtc->dev;
1701         struct drm_i915_private *dev_priv = dev->dev_private;
1702         u32 dpa_ctl;
1703
1704         assert_pipe_disabled(dev_priv,
1705                              to_intel_crtc(crtc)->pipe);
1706
1707         dpa_ctl = I915_READ(DP_A);
1708         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1709              "dp pll off, should be on\n");
1710         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1711
1712         /* We can't rely on the value tracked for the DP register in
1713          * intel_dp->DP because link_down must not change that (otherwise link
1714          * re-training will fail. */
1715         dpa_ctl &= ~DP_PLL_ENABLE;
1716         I915_WRITE(DP_A, dpa_ctl);
1717         POSTING_READ(DP_A);
1718         udelay(200);
1719 }
1720
1721 /* If the sink supports it, try to set the power state appropriately */
1722 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1723 {
1724         int ret, i;
1725
1726         /* Should have a valid DPCD by this point */
1727         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1728                 return;
1729
1730         if (mode != DRM_MODE_DPMS_ON) {
1731                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1732                                                   DP_SET_POWER_D3);
1733                 if (ret != 1)
1734                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1735         } else {
1736                 /*
1737                  * When turning on, we need to retry for 1ms to give the sink
1738                  * time to wake up.
1739                  */
1740                 for (i = 0; i < 3; i++) {
1741                         ret = intel_dp_aux_native_write_1(intel_dp,
1742                                                           DP_SET_POWER,
1743                                                           DP_SET_POWER_D0);
1744                         if (ret == 1)
1745                                 break;
1746                         msleep(1);
1747                 }
1748         }
1749 }
1750
1751 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1752                                   enum i915_pipe *pipe)
1753 {
1754         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1755         enum port port = dp_to_dig_port(intel_dp)->port;
1756         struct drm_device *dev = encoder->base.dev;
1757         struct drm_i915_private *dev_priv = dev->dev_private;
1758         enum intel_display_power_domain power_domain;
1759         u32 tmp;
1760
1761         power_domain = intel_display_port_power_domain(encoder);
1762         if (!intel_display_power_enabled(dev_priv, power_domain))
1763                 return false;
1764
1765         tmp = I915_READ(intel_dp->output_reg);
1766
1767         if (!(tmp & DP_PORT_EN))
1768                 return false;
1769
1770         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1771                 *pipe = PORT_TO_PIPE_CPT(tmp);
1772         } else if (IS_CHERRYVIEW(dev)) {
1773                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
1774         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1775                 *pipe = PORT_TO_PIPE(tmp);
1776         } else {
1777                 u32 trans_sel;
1778                 u32 trans_dp;
1779                 int i;
1780
1781                 switch (intel_dp->output_reg) {
1782                 case PCH_DP_B:
1783                         trans_sel = TRANS_DP_PORT_SEL_B;
1784                         break;
1785                 case PCH_DP_C:
1786                         trans_sel = TRANS_DP_PORT_SEL_C;
1787                         break;
1788                 case PCH_DP_D:
1789                         trans_sel = TRANS_DP_PORT_SEL_D;
1790                         break;
1791                 default:
1792                         return true;
1793                 }
1794
1795                 for_each_pipe(i) {
1796                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1797                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1798                                 *pipe = i;
1799                                 return true;
1800                         }
1801                 }
1802
1803                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1804                               intel_dp->output_reg);
1805         }
1806
1807         return true;
1808 }
1809
1810 static void intel_dp_get_config(struct intel_encoder *encoder,
1811                                 struct intel_crtc_config *pipe_config)
1812 {
1813         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1814         u32 tmp, flags = 0;
1815         struct drm_device *dev = encoder->base.dev;
1816         struct drm_i915_private *dev_priv = dev->dev_private;
1817         enum port port = dp_to_dig_port(intel_dp)->port;
1818         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1819         int dotclock;
1820
1821         tmp = I915_READ(intel_dp->output_reg);
1822         if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1823                 pipe_config->has_audio = true;
1824
1825         if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1826                 if (tmp & DP_SYNC_HS_HIGH)
1827                         flags |= DRM_MODE_FLAG_PHSYNC;
1828                 else
1829                         flags |= DRM_MODE_FLAG_NHSYNC;
1830
1831                 if (tmp & DP_SYNC_VS_HIGH)
1832                         flags |= DRM_MODE_FLAG_PVSYNC;
1833                 else
1834                         flags |= DRM_MODE_FLAG_NVSYNC;
1835         } else {
1836                 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1837                 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1838                         flags |= DRM_MODE_FLAG_PHSYNC;
1839                 else
1840                         flags |= DRM_MODE_FLAG_NHSYNC;
1841
1842                 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1843                         flags |= DRM_MODE_FLAG_PVSYNC;
1844                 else
1845                         flags |= DRM_MODE_FLAG_NVSYNC;
1846         }
1847
1848         pipe_config->adjusted_mode.flags |= flags;
1849
1850         if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
1851             tmp & DP_COLOR_RANGE_16_235)
1852                 pipe_config->limited_color_range = true;
1853
1854         pipe_config->has_dp_encoder = true;
1855
1856         intel_dp_get_m_n(crtc, pipe_config);
1857
1858         if (port == PORT_A) {
1859                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1860                         pipe_config->port_clock = 162000;
1861                 else
1862                         pipe_config->port_clock = 270000;
1863         }
1864
1865         dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1866                                             &pipe_config->dp_m_n);
1867
1868         if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1869                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1870
1871         pipe_config->adjusted_mode.crtc_clock = dotclock;
1872
1873         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1874             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1875                 /*
1876                  * This is a big fat ugly hack.
1877                  *
1878                  * Some machines in UEFI boot mode provide us a VBT that has 18
1879                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1880                  * unknown we fail to light up. Yet the same BIOS boots up with
1881                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1882                  * max, not what it tells us to use.
1883                  *
1884                  * Note: This will still be broken if the eDP panel is not lit
1885                  * up by the BIOS, and thus we can't get the mode at module
1886                  * load.
1887                  */
1888                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1889                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1890                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1891         }
1892 }
1893
1894 static bool is_edp_psr(struct intel_dp *intel_dp)
1895 {
1896         return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1897 }
1898
1899 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1900 {
1901         struct drm_i915_private *dev_priv = dev->dev_private;
1902
1903         if (!HAS_PSR(dev))
1904                 return false;
1905
1906         return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1907 }
1908
1909 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1910                                     struct edp_vsc_psr *vsc_psr)
1911 {
1912         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1913         struct drm_device *dev = dig_port->base.base.dev;
1914         struct drm_i915_private *dev_priv = dev->dev_private;
1915         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1916         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1917         u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1918         uint32_t *data = (uint32_t *) vsc_psr;
1919         unsigned int i;
1920
1921         /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1922            the video DIP being updated before program video DIP data buffer
1923            registers for DIP being updated. */
1924         I915_WRITE(ctl_reg, 0);
1925         POSTING_READ(ctl_reg);
1926
1927         for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1928                 if (i < sizeof(struct edp_vsc_psr))
1929                         I915_WRITE(data_reg + i, *data++);
1930                 else
1931                         I915_WRITE(data_reg + i, 0);
1932         }
1933
1934         I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1935         POSTING_READ(ctl_reg);
1936 }
1937
1938 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1939 {
1940         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1941         struct drm_i915_private *dev_priv = dev->dev_private;
1942         struct edp_vsc_psr psr_vsc;
1943
1944         /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1945         memset(&psr_vsc, 0, sizeof(psr_vsc));
1946         psr_vsc.sdp_header.HB0 = 0;
1947         psr_vsc.sdp_header.HB1 = 0x7;
1948         psr_vsc.sdp_header.HB2 = 0x2;
1949         psr_vsc.sdp_header.HB3 = 0x8;
1950         intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1951
1952         /* Avoid continuous PSR exit by masking memup and hpd */
1953         I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1954                    EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1955 }
1956
1957 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1958 {
1959         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1960         struct drm_device *dev = dig_port->base.base.dev;
1961         struct drm_i915_private *dev_priv = dev->dev_private;
1962         uint32_t aux_clock_divider;
1963         int precharge = 0x3;
1964         int msg_size = 5;       /* Header(4) + Message(1) */
1965         bool only_standby = false;
1966
1967         aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1968
1969         if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1970                 only_standby = true;
1971
1972         /* Enable PSR in sink */
1973         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
1974                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1975                                    DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
1976         else
1977                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1978                                    DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
1979
1980         /* Setup AUX registers */
1981         I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1982         I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1983         I915_WRITE(EDP_PSR_AUX_CTL(dev),
1984                    DP_AUX_CH_CTL_TIME_OUT_400us |
1985                    (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1986                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1987                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1988 }
1989
1990 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1991 {
1992         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1993         struct drm_device *dev = dig_port->base.base.dev;
1994         struct drm_i915_private *dev_priv = dev->dev_private;
1995         uint32_t max_sleep_time = 0x1f;
1996         uint32_t idle_frames = 1;
1997         uint32_t val = 0x0;
1998         const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1999         bool only_standby = false;
2000
2001         if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2002                 only_standby = true;
2003
2004         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2005                 val |= EDP_PSR_LINK_STANDBY;
2006                 val |= EDP_PSR_TP2_TP3_TIME_0us;
2007                 val |= EDP_PSR_TP1_TIME_0us;
2008                 val |= EDP_PSR_SKIP_AUX_EXIT;
2009                 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2010         } else
2011                 val |= EDP_PSR_LINK_DISABLE;
2012
2013         I915_WRITE(EDP_PSR_CTL(dev), val |
2014                    IS_BROADWELL(dev) ? 0 : link_entry_time |
2015                    max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
2016                    idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
2017                    EDP_PSR_ENABLE);
2018 }
2019
2020 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
2021 {
2022         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2023         struct drm_device *dev = dig_port->base.base.dev;
2024         struct drm_i915_private *dev_priv = dev->dev_private;
2025         struct drm_crtc *crtc = dig_port->base.base.crtc;
2026         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2027
2028 #if 0
2029         lockdep_assert_held(&dev_priv->psr.lock);
2030 #endif
2031         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
2032         WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
2033
2034         dev_priv->psr.source_ok = false;
2035
2036         if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
2037                 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
2038                 return false;
2039         }
2040
2041         if (!i915.enable_psr) {
2042                 DRM_DEBUG_KMS("PSR disable by flag\n");
2043                 return false;
2044         }
2045
2046         /* Below limitations aren't valid for Broadwell */
2047         if (IS_BROADWELL(dev))
2048                 goto out;
2049
2050         if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
2051             S3D_ENABLE) {
2052                 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
2053                 return false;
2054         }
2055
2056         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
2057                 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
2058                 return false;
2059         }
2060
2061  out:
2062         dev_priv->psr.source_ok = true;
2063         return true;
2064 }
2065
2066 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2067 {
2068         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2069         struct drm_device *dev = intel_dig_port->base.base.dev;
2070         struct drm_i915_private *dev_priv = dev->dev_private;
2071
2072         WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2073         WARN_ON(dev_priv->psr.active);
2074 #if 0
2075         lockdep_assert_held(&dev_priv->psr.lock);
2076 #endif
2077
2078         /* Enable PSR on the panel */
2079         intel_edp_psr_enable_sink(intel_dp);
2080
2081         /* Enable PSR on the host */
2082         intel_edp_psr_enable_source(intel_dp);
2083
2084         dev_priv->psr.active = true;
2085 }
2086
2087 void intel_edp_psr_enable(struct intel_dp *intel_dp)
2088 {
2089         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2090         struct drm_i915_private *dev_priv = dev->dev_private;
2091
2092         if (!HAS_PSR(dev)) {
2093                 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2094                 return;
2095         }
2096
2097         if (!is_edp_psr(intel_dp)) {
2098                 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2099                 return;
2100         }
2101
2102         mutex_lock(&dev_priv->psr.lock);
2103         if (dev_priv->psr.enabled) {
2104                 DRM_DEBUG_KMS("PSR already in use\n");
2105                 mutex_unlock(&dev_priv->psr.lock);
2106                 return;
2107         }
2108
2109         dev_priv->psr.busy_frontbuffer_bits = 0;
2110
2111         /* Setup PSR once */
2112         intel_edp_psr_setup(intel_dp);
2113
2114         if (intel_edp_psr_match_conditions(intel_dp))
2115                 dev_priv->psr.enabled = intel_dp;
2116         mutex_unlock(&dev_priv->psr.lock);
2117 }
2118
2119 void intel_edp_psr_disable(struct intel_dp *intel_dp)
2120 {
2121         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2122         struct drm_i915_private *dev_priv = dev->dev_private;
2123
2124         mutex_lock(&dev_priv->psr.lock);
2125         if (!dev_priv->psr.enabled) {
2126                 mutex_unlock(&dev_priv->psr.lock);
2127                 return;
2128         }
2129
2130         if (dev_priv->psr.active) {
2131                 I915_WRITE(EDP_PSR_CTL(dev),
2132                            I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2133
2134                 /* Wait till PSR is idle */
2135                 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2136                                EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
2137                         DRM_ERROR("Timed out waiting for PSR Idle State\n");
2138
2139                 dev_priv->psr.active = false;
2140         } else {
2141                 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2142         }
2143
2144         dev_priv->psr.enabled = NULL;
2145         mutex_unlock(&dev_priv->psr.lock);
2146
2147         cancel_delayed_work_sync(&dev_priv->psr.work);
2148 }
2149
2150 static void intel_edp_psr_work(struct work_struct *work)
2151 {
2152         struct drm_i915_private *dev_priv =
2153                 container_of(work, typeof(*dev_priv), psr.work.work);
2154         struct intel_dp *intel_dp = dev_priv->psr.enabled;
2155
2156         mutex_lock(&dev_priv->psr.lock);
2157         intel_dp = dev_priv->psr.enabled;
2158
2159         if (!intel_dp)
2160                 goto unlock;
2161
2162         /*
2163          * The delayed work can race with an invalidate hence we need to
2164          * recheck. Since psr_flush first clears this and then reschedules we
2165          * won't ever miss a flush when bailing out here.
2166          */
2167         if (dev_priv->psr.busy_frontbuffer_bits)
2168                 goto unlock;
2169
2170         intel_edp_psr_do_enable(intel_dp);
2171 unlock:
2172         mutex_unlock(&dev_priv->psr.lock);
2173 }
2174
2175 static void intel_edp_psr_do_exit(struct drm_device *dev)
2176 {
2177         struct drm_i915_private *dev_priv = dev->dev_private;
2178
2179         if (dev_priv->psr.active) {
2180                 u32 val = I915_READ(EDP_PSR_CTL(dev));
2181
2182                 WARN_ON(!(val & EDP_PSR_ENABLE));
2183
2184                 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
2185
2186                 dev_priv->psr.active = false;
2187         }
2188
2189 }
2190
2191 void intel_edp_psr_invalidate(struct drm_device *dev,
2192                               unsigned frontbuffer_bits)
2193 {
2194         struct drm_i915_private *dev_priv = dev->dev_private;
2195         struct drm_crtc *crtc;
2196         enum i915_pipe pipe;
2197
2198         mutex_lock(&dev_priv->psr.lock);
2199         if (!dev_priv->psr.enabled) {
2200                 mutex_unlock(&dev_priv->psr.lock);
2201                 return;
2202         }
2203
2204         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2205         pipe = to_intel_crtc(crtc)->pipe;
2206
2207         intel_edp_psr_do_exit(dev);
2208
2209         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2210
2211         dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2212         mutex_unlock(&dev_priv->psr.lock);
2213 }
2214
2215 void intel_edp_psr_flush(struct drm_device *dev,
2216                          unsigned frontbuffer_bits)
2217 {
2218         struct drm_i915_private *dev_priv = dev->dev_private;
2219         struct drm_crtc *crtc;
2220         enum i915_pipe pipe;
2221
2222         mutex_lock(&dev_priv->psr.lock);
2223         if (!dev_priv->psr.enabled) {
2224                 mutex_unlock(&dev_priv->psr.lock);
2225                 return;
2226         }
2227
2228         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2229         pipe = to_intel_crtc(crtc)->pipe;
2230         dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2231
2232         /*
2233          * On Haswell sprite plane updates don't result in a psr invalidating
2234          * signal in the hardware. Which means we need to manually fake this in
2235          * software for all flushes, not just when we've seen a preceding
2236          * invalidation through frontbuffer rendering.
2237          */
2238         if (IS_HASWELL(dev) &&
2239             (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2240                 intel_edp_psr_do_exit(dev);
2241
2242         if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2243                 schedule_delayed_work(&dev_priv->psr.work,
2244                                       msecs_to_jiffies(100));
2245         mutex_unlock(&dev_priv->psr.lock);
2246 }
2247
2248 void intel_edp_psr_init(struct drm_device *dev)
2249 {
2250         struct drm_i915_private *dev_priv = dev->dev_private;
2251
2252         INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
2253         lockinit(&dev_priv->psr.lock, "i915dpl", 0, LK_CANRECURSE);
2254 }
2255
2256 static void intel_disable_dp(struct intel_encoder *encoder)
2257 {
2258         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2259         enum port port = dp_to_dig_port(intel_dp)->port;
2260         struct drm_device *dev = encoder->base.dev;
2261
2262         /* Make sure the panel is off before trying to change the mode. But also
2263          * ensure that we have vdd while we switch off the panel. */
2264         intel_edp_panel_vdd_on(intel_dp);
2265         intel_edp_backlight_off(intel_dp);
2266         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2267         intel_edp_panel_off(intel_dp);
2268
2269         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
2270         if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
2271                 intel_dp_link_down(intel_dp);
2272 }
2273
2274 static void g4x_post_disable_dp(struct intel_encoder *encoder)
2275 {
2276         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2277         enum port port = dp_to_dig_port(intel_dp)->port;
2278
2279         if (port != PORT_A)
2280                 return;
2281
2282         intel_dp_link_down(intel_dp);
2283         ironlake_edp_pll_off(intel_dp);
2284 }
2285
2286 static void vlv_post_disable_dp(struct intel_encoder *encoder)
2287 {
2288         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2289
2290         intel_dp_link_down(intel_dp);
2291 }
2292
2293 static void chv_post_disable_dp(struct intel_encoder *encoder)
2294 {
2295         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2296         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2297         struct drm_device *dev = encoder->base.dev;
2298         struct drm_i915_private *dev_priv = dev->dev_private;
2299         struct intel_crtc *intel_crtc =
2300                 to_intel_crtc(encoder->base.crtc);
2301         enum dpio_channel ch = vlv_dport_to_channel(dport);
2302         enum i915_pipe pipe = intel_crtc->pipe;
2303         u32 val;
2304
2305         intel_dp_link_down(intel_dp);
2306
2307         mutex_lock(&dev_priv->dpio_lock);
2308
2309         /* Propagate soft reset to data lane reset */
2310         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2311         val |= CHV_PCS_REQ_SOFTRESET_EN;
2312         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2313
2314         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2315         val |= CHV_PCS_REQ_SOFTRESET_EN;
2316         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2317
2318         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2319         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2320         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2321
2322         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2323         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2324         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2325
2326         mutex_unlock(&dev_priv->dpio_lock);
2327 }
2328
2329 static void intel_enable_dp(struct intel_encoder *encoder)
2330 {
2331         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2332         struct drm_device *dev = encoder->base.dev;
2333         struct drm_i915_private *dev_priv = dev->dev_private;
2334         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2335
2336         if (WARN_ON(dp_reg & DP_PORT_EN))
2337                 return;
2338
2339         intel_edp_panel_vdd_on(intel_dp);
2340         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2341         intel_dp_start_link_train(intel_dp);
2342         intel_edp_panel_on(intel_dp);
2343         edp_panel_vdd_off(intel_dp, true);
2344         intel_dp_complete_link_train(intel_dp);
2345         intel_dp_stop_link_train(intel_dp);
2346 }
2347
2348 static void g4x_enable_dp(struct intel_encoder *encoder)
2349 {
2350         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2351
2352         intel_enable_dp(encoder);
2353         intel_edp_backlight_on(intel_dp);
2354 }
2355
2356 static void vlv_enable_dp(struct intel_encoder *encoder)
2357 {
2358         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2359
2360         intel_edp_backlight_on(intel_dp);
2361 }
2362
2363 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2364 {
2365         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2366         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2367
2368         intel_dp_prepare(encoder);
2369
2370         /* Only ilk+ has port A */
2371         if (dport->port == PORT_A) {
2372                 ironlake_set_pll_cpu_edp(intel_dp);
2373                 ironlake_edp_pll_on(intel_dp);
2374         }
2375 }
2376
2377 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2378 {
2379         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2380         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2381         struct drm_device *dev = encoder->base.dev;
2382         struct drm_i915_private *dev_priv = dev->dev_private;
2383         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2384         enum dpio_channel port = vlv_dport_to_channel(dport);
2385         int pipe = intel_crtc->pipe;
2386         struct edp_power_seq power_seq;
2387         u32 val;
2388
2389         mutex_lock(&dev_priv->dpio_lock);
2390
2391         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2392         val = 0;
2393         if (pipe)
2394                 val |= (1<<21);
2395         else
2396                 val &= ~(1<<21);
2397         val |= 0x001000c4;
2398         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2399         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2400         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2401
2402         mutex_unlock(&dev_priv->dpio_lock);
2403
2404         if (is_edp(intel_dp)) {
2405                 /* init power sequencer on this pipe and port */
2406                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2407                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2408                                                               &power_seq);
2409         }
2410
2411         intel_enable_dp(encoder);
2412
2413         vlv_wait_port_ready(dev_priv, dport);
2414 }
2415
2416 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2417 {
2418         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2419         struct drm_device *dev = encoder->base.dev;
2420         struct drm_i915_private *dev_priv = dev->dev_private;
2421         struct intel_crtc *intel_crtc =
2422                 to_intel_crtc(encoder->base.crtc);
2423         enum dpio_channel port = vlv_dport_to_channel(dport);
2424         int pipe = intel_crtc->pipe;
2425
2426         intel_dp_prepare(encoder);
2427
2428         /* Program Tx lane resets to default */
2429         mutex_lock(&dev_priv->dpio_lock);
2430         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2431                          DPIO_PCS_TX_LANE2_RESET |
2432                          DPIO_PCS_TX_LANE1_RESET);
2433         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2434                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2435                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2436                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2437                                  DPIO_PCS_CLK_SOFT_RESET);
2438
2439         /* Fix up inter-pair skew failure */
2440         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2441         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2442         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2443         mutex_unlock(&dev_priv->dpio_lock);
2444 }
2445
2446 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2447 {
2448         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2449         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2450         struct drm_device *dev = encoder->base.dev;
2451         struct drm_i915_private *dev_priv = dev->dev_private;
2452         struct edp_power_seq power_seq;
2453         struct intel_crtc *intel_crtc =
2454                 to_intel_crtc(encoder->base.crtc);
2455         enum dpio_channel ch = vlv_dport_to_channel(dport);
2456         int pipe = intel_crtc->pipe;
2457         int data, i;
2458         u32 val;
2459
2460         mutex_lock(&dev_priv->dpio_lock);
2461
2462         /* Deassert soft data lane reset*/
2463         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2464         val |= CHV_PCS_REQ_SOFTRESET_EN;
2465         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2466
2467         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2468         val |= CHV_PCS_REQ_SOFTRESET_EN;
2469         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2470
2471         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2472         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2473         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2474
2475         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2476         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2477         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2478
2479         /* Program Tx lane latency optimal setting*/
2480         for (i = 0; i < 4; i++) {
2481                 /* Set the latency optimal bit */
2482                 data = (i == 1) ? 0x0 : 0x6;
2483                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2484                                 data << DPIO_FRC_LATENCY_SHFIT);
2485
2486                 /* Set the upar bit */
2487                 data = (i == 1) ? 0x0 : 0x1;
2488                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2489                                 data << DPIO_UPAR_SHIFT);
2490         }
2491
2492         /* Data lane stagger programming */
2493         /* FIXME: Fix up value only after power analysis */
2494
2495         mutex_unlock(&dev_priv->dpio_lock);
2496
2497         if (is_edp(intel_dp)) {
2498                 /* init power sequencer on this pipe and port */
2499                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2500                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2501                                                               &power_seq);
2502         }
2503
2504         intel_enable_dp(encoder);
2505
2506         vlv_wait_port_ready(dev_priv, dport);
2507 }
2508
2509 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2510 {
2511         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2512         struct drm_device *dev = encoder->base.dev;
2513         struct drm_i915_private *dev_priv = dev->dev_private;
2514         struct intel_crtc *intel_crtc =
2515                 to_intel_crtc(encoder->base.crtc);
2516         enum dpio_channel ch = vlv_dport_to_channel(dport);
2517         enum i915_pipe pipe = intel_crtc->pipe;
2518         u32 val;
2519
2520         mutex_lock(&dev_priv->dpio_lock);
2521
2522         /* program left/right clock distribution */
2523         if (pipe != PIPE_B) {
2524                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2525                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2526                 if (ch == DPIO_CH0)
2527                         val |= CHV_BUFLEFTENA1_FORCE;
2528                 if (ch == DPIO_CH1)
2529                         val |= CHV_BUFRIGHTENA1_FORCE;
2530                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2531         } else {
2532                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2533                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2534                 if (ch == DPIO_CH0)
2535                         val |= CHV_BUFLEFTENA2_FORCE;
2536                 if (ch == DPIO_CH1)
2537                         val |= CHV_BUFRIGHTENA2_FORCE;
2538                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2539         }
2540
2541         /* program clock channel usage */
2542         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2543         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2544         if (pipe != PIPE_B)
2545                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2546         else
2547                 val |= CHV_PCS_USEDCLKCHANNEL;
2548         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2549
2550         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2551         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2552         if (pipe != PIPE_B)
2553                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2554         else
2555                 val |= CHV_PCS_USEDCLKCHANNEL;
2556         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2557
2558         /*
2559          * This a a bit weird since generally CL
2560          * matches the pipe, but here we need to
2561          * pick the CL based on the port.
2562          */
2563         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2564         if (pipe != PIPE_B)
2565                 val &= ~CHV_CMN_USEDCLKCHANNEL;
2566         else
2567                 val |= CHV_CMN_USEDCLKCHANNEL;
2568         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2569
2570         mutex_unlock(&dev_priv->dpio_lock);
2571 }
2572
2573 /*
2574  * Native read with retry for link status and receiver capability reads for
2575  * cases where the sink may still be asleep.
2576  */
2577 static bool
2578 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
2579                                uint8_t *recv, int recv_bytes)
2580 {
2581         int ret, i;
2582
2583         /*
2584          * Sinks are *supposed* to come up within 1ms from an off state,
2585          * but we're also supposed to retry 3 times per the spec.
2586          */
2587         for (i = 0; i < 3; i++) {
2588                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
2589                                                recv_bytes);
2590                 if (ret == recv_bytes)
2591                         return true;
2592                 msleep(1);
2593         }
2594
2595         return false;
2596 }
2597
2598 /*
2599  * Fetch AUX CH registers 0x202 - 0x207 which contain
2600  * link status information
2601  */
2602 static bool
2603 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2604 {
2605         return intel_dp_aux_native_read_retry(intel_dp,
2606                                               DP_LANE0_1_STATUS,
2607                                               link_status,
2608                                               DP_LINK_STATUS_SIZE);
2609 }
2610
2611 /* These are source-specific values. */
2612 static uint8_t
2613 intel_dp_voltage_max(struct intel_dp *intel_dp)
2614 {
2615         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2616         enum port port = dp_to_dig_port(intel_dp)->port;
2617
2618         if (IS_VALLEYVIEW(dev))
2619                 return DP_TRAIN_VOLTAGE_SWING_1200;
2620         else if (IS_GEN7(dev) && port == PORT_A)
2621                 return DP_TRAIN_VOLTAGE_SWING_800;
2622         else if (HAS_PCH_CPT(dev) && port != PORT_A)
2623                 return DP_TRAIN_VOLTAGE_SWING_1200;
2624         else
2625                 return DP_TRAIN_VOLTAGE_SWING_800;
2626 }
2627
2628 static uint8_t
2629 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2630 {
2631         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2632         enum port port = dp_to_dig_port(intel_dp)->port;
2633
2634         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2635                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2636                 case DP_TRAIN_VOLTAGE_SWING_400:
2637                         return DP_TRAIN_PRE_EMPHASIS_9_5;
2638                 case DP_TRAIN_VOLTAGE_SWING_600:
2639                         return DP_TRAIN_PRE_EMPHASIS_6;
2640                 case DP_TRAIN_VOLTAGE_SWING_800:
2641                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2642                 case DP_TRAIN_VOLTAGE_SWING_1200:
2643                 default:
2644                         return DP_TRAIN_PRE_EMPHASIS_0;
2645                 }
2646         } else if (IS_VALLEYVIEW(dev)) {
2647                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2648                 case DP_TRAIN_VOLTAGE_SWING_400:
2649                         return DP_TRAIN_PRE_EMPHASIS_9_5;
2650                 case DP_TRAIN_VOLTAGE_SWING_600:
2651                         return DP_TRAIN_PRE_EMPHASIS_6;
2652                 case DP_TRAIN_VOLTAGE_SWING_800:
2653                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2654                 case DP_TRAIN_VOLTAGE_SWING_1200:
2655                 default:
2656                         return DP_TRAIN_PRE_EMPHASIS_0;
2657                 }
2658         } else if (IS_GEN7(dev) && port == PORT_A) {
2659                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2660                 case DP_TRAIN_VOLTAGE_SWING_400:
2661                         return DP_TRAIN_PRE_EMPHASIS_6;
2662                 case DP_TRAIN_VOLTAGE_SWING_600:
2663                 case DP_TRAIN_VOLTAGE_SWING_800:
2664                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2665                 default:
2666                         return DP_TRAIN_PRE_EMPHASIS_0;
2667                 }
2668         } else {
2669                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2670                 case DP_TRAIN_VOLTAGE_SWING_400:
2671                         return DP_TRAIN_PRE_EMPHASIS_6;
2672                 case DP_TRAIN_VOLTAGE_SWING_600:
2673                         return DP_TRAIN_PRE_EMPHASIS_6;
2674                 case DP_TRAIN_VOLTAGE_SWING_800:
2675                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2676                 case DP_TRAIN_VOLTAGE_SWING_1200:
2677                 default:
2678                         return DP_TRAIN_PRE_EMPHASIS_0;
2679                 }
2680         }
2681 }
2682
2683 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2684 {
2685         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2686         struct drm_i915_private *dev_priv = dev->dev_private;
2687         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2688         struct intel_crtc *intel_crtc =
2689                 to_intel_crtc(dport->base.base.crtc);
2690         unsigned long demph_reg_value, preemph_reg_value,
2691                 uniqtranscale_reg_value;
2692         uint8_t train_set = intel_dp->train_set[0];
2693         enum dpio_channel port = vlv_dport_to_channel(dport);
2694         int pipe = intel_crtc->pipe;
2695
2696         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2697         case DP_TRAIN_PRE_EMPHASIS_0:
2698                 preemph_reg_value = 0x0004000;
2699                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2700                 case DP_TRAIN_VOLTAGE_SWING_400:
2701                         demph_reg_value = 0x2B405555;
2702                         uniqtranscale_reg_value = 0x552AB83A;
2703                         break;
2704                 case DP_TRAIN_VOLTAGE_SWING_600:
2705                         demph_reg_value = 0x2B404040;
2706                         uniqtranscale_reg_value = 0x5548B83A;
2707                         break;
2708                 case DP_TRAIN_VOLTAGE_SWING_800:
2709                         demph_reg_value = 0x2B245555;
2710                         uniqtranscale_reg_value = 0x5560B83A;
2711                         break;
2712                 case DP_TRAIN_VOLTAGE_SWING_1200:
2713                         demph_reg_value = 0x2B405555;
2714                         uniqtranscale_reg_value = 0x5598DA3A;
2715                         break;
2716                 default:
2717                         return 0;
2718                 }
2719                 break;
2720         case DP_TRAIN_PRE_EMPHASIS_3_5:
2721                 preemph_reg_value = 0x0002000;
2722                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2723                 case DP_TRAIN_VOLTAGE_SWING_400:
2724                         demph_reg_value = 0x2B404040;
2725                         uniqtranscale_reg_value = 0x5552B83A;
2726                         break;
2727                 case DP_TRAIN_VOLTAGE_SWING_600:
2728                         demph_reg_value = 0x2B404848;
2729                         uniqtranscale_reg_value = 0x5580B83A;
2730                         break;
2731                 case DP_TRAIN_VOLTAGE_SWING_800:
2732                         demph_reg_value = 0x2B404040;
2733                         uniqtranscale_reg_value = 0x55ADDA3A;
2734                         break;
2735                 default:
2736                         return 0;
2737                 }
2738                 break;
2739         case DP_TRAIN_PRE_EMPHASIS_6:
2740                 preemph_reg_value = 0x0000000;
2741                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2742                 case DP_TRAIN_VOLTAGE_SWING_400:
2743                         demph_reg_value = 0x2B305555;
2744                         uniqtranscale_reg_value = 0x5570B83A;
2745                         break;
2746                 case DP_TRAIN_VOLTAGE_SWING_600:
2747                         demph_reg_value = 0x2B2B4040;
2748                         uniqtranscale_reg_value = 0x55ADDA3A;
2749                         break;
2750                 default:
2751                         return 0;
2752                 }
2753                 break;
2754         case DP_TRAIN_PRE_EMPHASIS_9_5:
2755                 preemph_reg_value = 0x0006000;
2756                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2757                 case DP_TRAIN_VOLTAGE_SWING_400:
2758                         demph_reg_value = 0x1B405555;
2759                         uniqtranscale_reg_value = 0x55ADDA3A;
2760                         break;
2761                 default:
2762                         return 0;
2763                 }
2764                 break;
2765         default:
2766                 return 0;
2767         }
2768
2769         mutex_lock(&dev_priv->dpio_lock);
2770         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2771         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2772         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2773                          uniqtranscale_reg_value);
2774         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2775         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2776         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2777         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2778         mutex_unlock(&dev_priv->dpio_lock);
2779
2780         return 0;
2781 }
2782
2783 static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2784 {
2785         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2786         struct drm_i915_private *dev_priv = dev->dev_private;
2787         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2788         struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
2789         u32 deemph_reg_value, margin_reg_value, val;
2790         uint8_t train_set = intel_dp->train_set[0];
2791         enum dpio_channel ch = vlv_dport_to_channel(dport);
2792         enum i915_pipe pipe = intel_crtc->pipe;
2793         int i;
2794
2795         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2796         case DP_TRAIN_PRE_EMPHASIS_0:
2797                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2798                 case DP_TRAIN_VOLTAGE_SWING_400:
2799                         deemph_reg_value = 128;
2800                         margin_reg_value = 52;
2801                         break;
2802                 case DP_TRAIN_VOLTAGE_SWING_600:
2803                         deemph_reg_value = 128;
2804                         margin_reg_value = 77;
2805                         break;
2806                 case DP_TRAIN_VOLTAGE_SWING_800:
2807                         deemph_reg_value = 128;
2808                         margin_reg_value = 102;
2809                         break;
2810                 case DP_TRAIN_VOLTAGE_SWING_1200:
2811                         deemph_reg_value = 128;
2812                         margin_reg_value = 154;
2813                         /* FIXME extra to set for 1200 */
2814                         break;
2815                 default:
2816                         return 0;
2817                 }
2818                 break;
2819         case DP_TRAIN_PRE_EMPHASIS_3_5:
2820                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2821                 case DP_TRAIN_VOLTAGE_SWING_400:
2822                         deemph_reg_value = 85;
2823                         margin_reg_value = 78;
2824                         break;
2825                 case DP_TRAIN_VOLTAGE_SWING_600:
2826                         deemph_reg_value = 85;
2827                         margin_reg_value = 116;
2828                         break;
2829                 case DP_TRAIN_VOLTAGE_SWING_800:
2830                         deemph_reg_value = 85;
2831                         margin_reg_value = 154;
2832                         break;
2833                 default:
2834                         return 0;
2835                 }
2836                 break;
2837         case DP_TRAIN_PRE_EMPHASIS_6:
2838                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2839                 case DP_TRAIN_VOLTAGE_SWING_400:
2840                         deemph_reg_value = 64;
2841                         margin_reg_value = 104;
2842                         break;
2843                 case DP_TRAIN_VOLTAGE_SWING_600:
2844                         deemph_reg_value = 64;
2845                         margin_reg_value = 154;
2846                         break;
2847                 default:
2848                         return 0;
2849                 }
2850                 break;
2851         case DP_TRAIN_PRE_EMPHASIS_9_5:
2852                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2853                 case DP_TRAIN_VOLTAGE_SWING_400:
2854                         deemph_reg_value = 43;
2855                         margin_reg_value = 154;
2856                         break;
2857                 default:
2858                         return 0;
2859                 }
2860                 break;
2861         default:
2862                 return 0;
2863         }
2864
2865         mutex_lock(&dev_priv->dpio_lock);
2866
2867         /* Clear calc init */
2868         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2869         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2870         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2871
2872         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2873         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2874         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2875
2876         /* Program swing deemph */
2877         for (i = 0; i < 4; i++) {
2878                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2879                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2880                 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2881                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2882         }
2883
2884         /* Program swing margin */
2885         for (i = 0; i < 4; i++) {
2886                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2887                 val &= ~DPIO_SWING_MARGIN_MASK;
2888                 val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
2889                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2890         }
2891
2892         /* Disable unique transition scale */
2893         for (i = 0; i < 4; i++) {
2894                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2895                 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2896                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2897         }
2898
2899         if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2900                         == DP_TRAIN_PRE_EMPHASIS_0) &&
2901                 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2902                         == DP_TRAIN_VOLTAGE_SWING_1200)) {
2903
2904                 /*
2905                  * The document said it needs to set bit 27 for ch0 and bit 26
2906                  * for ch1. Might be a typo in the doc.
2907                  * For now, for this unique transition scale selection, set bit
2908                  * 27 for ch0 and ch1.
2909                  */
2910                 for (i = 0; i < 4; i++) {
2911                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2912                         val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2913                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2914                 }
2915
2916                 for (i = 0; i < 4; i++) {
2917                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2918                         val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2919                         val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2920                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2921                 }
2922         }
2923
2924         /* Start swing calculation */
2925         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2926         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2927         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2928
2929         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2930         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2931         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2932
2933         /* LRC Bypass */
2934         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2935         val |= DPIO_LRC_BYPASS;
2936         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2937
2938         mutex_unlock(&dev_priv->dpio_lock);
2939
2940         return 0;
2941 }
2942
2943 static void
2944 intel_get_adjust_train(struct intel_dp *intel_dp,
2945                        const uint8_t link_status[DP_LINK_STATUS_SIZE])
2946 {
2947         uint8_t v = 0;
2948         uint8_t p = 0;
2949         int lane;
2950         uint8_t voltage_max;
2951         uint8_t preemph_max;
2952
2953         for (lane = 0; lane < intel_dp->lane_count; lane++) {
2954                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2955                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2956
2957                 if (this_v > v)
2958                         v = this_v;
2959                 if (this_p > p)
2960                         p = this_p;
2961         }
2962
2963         voltage_max = intel_dp_voltage_max(intel_dp);
2964         if (v >= voltage_max)
2965                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2966
2967         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2968         if (p >= preemph_max)
2969                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2970
2971         for (lane = 0; lane < 4; lane++)
2972                 intel_dp->train_set[lane] = v | p;
2973 }
2974
2975 static uint32_t
2976 intel_gen4_signal_levels(uint8_t train_set)
2977 {
2978         uint32_t        signal_levels = 0;
2979
2980         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2981         case DP_TRAIN_VOLTAGE_SWING_400:
2982         default:
2983                 signal_levels |= DP_VOLTAGE_0_4;
2984                 break;
2985         case DP_TRAIN_VOLTAGE_SWING_600:
2986                 signal_levels |= DP_VOLTAGE_0_6;
2987                 break;
2988         case DP_TRAIN_VOLTAGE_SWING_800:
2989                 signal_levels |= DP_VOLTAGE_0_8;
2990                 break;
2991         case DP_TRAIN_VOLTAGE_SWING_1200:
2992                 signal_levels |= DP_VOLTAGE_1_2;
2993                 break;
2994         }
2995         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2996         case DP_TRAIN_PRE_EMPHASIS_0:
2997         default:
2998                 signal_levels |= DP_PRE_EMPHASIS_0;
2999                 break;
3000         case DP_TRAIN_PRE_EMPHASIS_3_5:
3001                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3002                 break;
3003         case DP_TRAIN_PRE_EMPHASIS_6:
3004                 signal_levels |= DP_PRE_EMPHASIS_6;
3005                 break;
3006         case DP_TRAIN_PRE_EMPHASIS_9_5:
3007                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3008                 break;
3009         }
3010         return signal_levels;
3011 }
3012
3013 /* Gen6's DP voltage swing and pre-emphasis control */
3014 static uint32_t
3015 intel_gen6_edp_signal_levels(uint8_t train_set)
3016 {
3017         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3018                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3019         switch (signal_levels) {
3020         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3021         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
3022                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3023         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
3024                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3025         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3026         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
3027                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3028         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3029         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
3030                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3031         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3032         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
3033                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3034         default:
3035                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3036                               "0x%x\n", signal_levels);
3037                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3038         }
3039 }
3040
3041 /* Gen7's DP voltage swing and pre-emphasis control */
3042 static uint32_t
3043 intel_gen7_edp_signal_levels(uint8_t train_set)
3044 {
3045         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3046                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3047         switch (signal_levels) {
3048         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3049                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3050         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
3051                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3052         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3053                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3054
3055         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
3056                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3057         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3058                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3059
3060         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3061                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3062         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
3063                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3064
3065         default:
3066                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3067                               "0x%x\n", signal_levels);
3068                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3069         }
3070 }
3071
3072 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3073 static uint32_t
3074 intel_hsw_signal_levels(uint8_t train_set)
3075 {
3076         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3077                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3078         switch (signal_levels) {
3079         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3080                 return DDI_BUF_EMP_400MV_0DB_HSW;
3081         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
3082                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
3083         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3084                 return DDI_BUF_EMP_400MV_6DB_HSW;
3085         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
3086                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
3087
3088         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
3089                 return DDI_BUF_EMP_600MV_0DB_HSW;
3090         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3091                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
3092         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
3093                 return DDI_BUF_EMP_600MV_6DB_HSW;
3094
3095         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3096                 return DDI_BUF_EMP_800MV_0DB_HSW;
3097         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
3098                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
3099         default:
3100                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3101                               "0x%x\n", signal_levels);
3102                 return DDI_BUF_EMP_400MV_0DB_HSW;
3103         }
3104 }
3105
3106 /* Properly updates "DP" with the correct signal levels. */
3107 static void
3108 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3109 {
3110         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3111         enum port port = intel_dig_port->port;
3112         struct drm_device *dev = intel_dig_port->base.base.dev;
3113         uint32_t signal_levels, mask;
3114         uint8_t train_set = intel_dp->train_set[0];
3115
3116         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3117                 signal_levels = intel_hsw_signal_levels(train_set);
3118                 mask = DDI_BUF_EMP_MASK;
3119         } else if (IS_CHERRYVIEW(dev)) {
3120                 signal_levels = intel_chv_signal_levels(intel_dp);
3121                 mask = 0;
3122         } else if (IS_VALLEYVIEW(dev)) {
3123                 signal_levels = intel_vlv_signal_levels(intel_dp);
3124                 mask = 0;
3125         } else if (IS_GEN7(dev) && port == PORT_A) {
3126                 signal_levels = intel_gen7_edp_signal_levels(train_set);
3127                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3128         } else if (IS_GEN6(dev) && port == PORT_A) {
3129                 signal_levels = intel_gen6_edp_signal_levels(train_set);
3130                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3131         } else {
3132                 signal_levels = intel_gen4_signal_levels(train_set);
3133                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3134         }
3135
3136         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3137
3138         *DP = (*DP & ~mask) | signal_levels;
3139 }
3140
3141 static bool
3142 intel_dp_set_link_train(struct intel_dp *intel_dp,
3143                         uint32_t *DP,
3144                         uint8_t dp_train_pat)
3145 {
3146         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3147         struct drm_device *dev = intel_dig_port->base.base.dev;
3148         struct drm_i915_private *dev_priv = dev->dev_private;
3149         enum port port = intel_dig_port->port;
3150         uint8_t buf[sizeof(intel_dp->train_set) + 1];
3151         int ret, len;
3152
3153         if (HAS_DDI(dev)) {
3154                 uint32_t temp = I915_READ(DP_TP_CTL(port));
3155
3156                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3157                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3158                 else
3159                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3160
3161                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3162                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3163                 case DP_TRAINING_PATTERN_DISABLE:
3164                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3165
3166                         break;
3167                 case DP_TRAINING_PATTERN_1:
3168                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3169                         break;
3170                 case DP_TRAINING_PATTERN_2:
3171                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3172                         break;
3173                 case DP_TRAINING_PATTERN_3:
3174                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3175                         break;
3176                 }
3177                 I915_WRITE(DP_TP_CTL(port), temp);
3178
3179         } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
3180                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3181
3182                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3183                 case DP_TRAINING_PATTERN_DISABLE:
3184                         *DP |= DP_LINK_TRAIN_OFF_CPT;
3185                         break;
3186                 case DP_TRAINING_PATTERN_1:
3187                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3188                         break;
3189                 case DP_TRAINING_PATTERN_2:
3190                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3191                         break;
3192                 case DP_TRAINING_PATTERN_3:
3193                         DRM_ERROR("DP training pattern 3 not supported\n");
3194                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3195                         break;
3196                 }
3197
3198         } else {
3199                 *DP &= ~DP_LINK_TRAIN_MASK;
3200
3201                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3202                 case DP_TRAINING_PATTERN_DISABLE:
3203                         *DP |= DP_LINK_TRAIN_OFF;
3204                         break;
3205                 case DP_TRAINING_PATTERN_1:
3206                         *DP |= DP_LINK_TRAIN_PAT_1;
3207                         break;
3208                 case DP_TRAINING_PATTERN_2:
3209                         *DP |= DP_LINK_TRAIN_PAT_2;
3210                         break;
3211                 case DP_TRAINING_PATTERN_3:
3212                         DRM_ERROR("DP training pattern 3 not supported\n");
3213                         *DP |= DP_LINK_TRAIN_PAT_2;
3214                         break;
3215                 }
3216         }
3217
3218         I915_WRITE(intel_dp->output_reg, *DP);
3219         POSTING_READ(intel_dp->output_reg);
3220
3221         buf[0] = dp_train_pat;
3222         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
3223             DP_TRAINING_PATTERN_DISABLE) {
3224                 /* don't write DP_TRAINING_LANEx_SET on disable */
3225                 len = 1;
3226         } else {
3227                 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3228                 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3229                 len = intel_dp->lane_count + 1;
3230         }
3231
3232         ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET,
3233                                         buf, len);
3234
3235         return ret == len;
3236 }
3237
3238 static bool
3239 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3240                         uint8_t dp_train_pat)
3241 {
3242         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3243         intel_dp_set_signal_levels(intel_dp, DP);
3244         return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3245 }
3246
3247 static bool
3248 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3249                            const uint8_t link_status[DP_LINK_STATUS_SIZE])
3250 {
3251         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3252         struct drm_device *dev = intel_dig_port->base.base.dev;
3253         struct drm_i915_private *dev_priv = dev->dev_private;
3254         int ret;
3255
3256         intel_get_adjust_train(intel_dp, link_status);
3257         intel_dp_set_signal_levels(intel_dp, DP);
3258
3259         I915_WRITE(intel_dp->output_reg, *DP);
3260         POSTING_READ(intel_dp->output_reg);
3261
3262         ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET,
3263                                         intel_dp->train_set,
3264                                         intel_dp->lane_count);
3265
3266         return ret == intel_dp->lane_count;
3267 }
3268
3269 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3270 {
3271         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3272         struct drm_device *dev = intel_dig_port->base.base.dev;
3273         struct drm_i915_private *dev_priv = dev->dev_private;
3274         enum port port = intel_dig_port->port;
3275         uint32_t val;
3276
3277         if (!HAS_DDI(dev))
3278                 return;
3279
3280         val = I915_READ(DP_TP_CTL(port));
3281         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3282         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3283         I915_WRITE(DP_TP_CTL(port), val);
3284
3285         /*
3286          * On PORT_A we can have only eDP in SST mode. There the only reason
3287          * we need to set idle transmission mode is to work around a HW issue
3288          * where we enable the pipe while not in idle link-training mode.
3289          * In this case there is requirement to wait for a minimum number of
3290          * idle patterns to be sent.
3291          */
3292         if (port == PORT_A)
3293                 return;
3294
3295         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3296                      1))
3297                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3298 }
3299
3300 /* Enable corresponding port and start training pattern 1 */
3301 void
3302 intel_dp_start_link_train(struct intel_dp *intel_dp)
3303 {
3304         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
3305         struct drm_device *dev = encoder->dev;
3306         int i;
3307         uint8_t voltage;
3308         int voltage_tries, loop_tries;
3309         uint32_t DP = intel_dp->DP;
3310         uint8_t link_config[2];
3311
3312         if (HAS_DDI(dev))
3313                 intel_ddi_prepare_link_retrain(encoder);
3314
3315         /* Write the link configuration data */
3316         link_config[0] = intel_dp->link_bw;
3317         link_config[1] = intel_dp->lane_count;
3318         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3319                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
3320         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2);
3321
3322         link_config[0] = 0;
3323         link_config[1] = DP_SET_ANSI_8B10B;
3324         intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2);
3325
3326         DP |= DP_PORT_EN;
3327
3328         /* clock recovery */
3329         if (!intel_dp_reset_link_train(intel_dp, &DP,
3330                                        DP_TRAINING_PATTERN_1 |
3331                                        DP_LINK_SCRAMBLING_DISABLE)) {
3332                 DRM_ERROR("failed to enable link training\n");
3333                 return;
3334         }
3335
3336         voltage = 0xff;
3337         voltage_tries = 0;
3338         loop_tries = 0;
3339         for (;;) {
3340                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3341
3342                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3343                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3344                         DRM_ERROR("failed to get link status\n");
3345                         break;
3346                 }
3347
3348                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3349                         DRM_DEBUG_KMS("clock recovery OK\n");
3350                         break;
3351                 }
3352
3353                 /* Check to see if we've tried the max voltage */
3354                 for (i = 0; i < intel_dp->lane_count; i++)
3355                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3356                                 break;
3357                 if (i == intel_dp->lane_count) {
3358                         ++loop_tries;
3359                         if (loop_tries == 5) {
3360                                 DRM_ERROR("too many full retries, give up\n");
3361                                 break;
3362                         }
3363                         intel_dp_reset_link_train(intel_dp, &DP,
3364                                                   DP_TRAINING_PATTERN_1 |
3365                                                   DP_LINK_SCRAMBLING_DISABLE);
3366                         voltage_tries = 0;
3367                         continue;
3368                 }
3369
3370                 /* Check to see if we've tried the same voltage 5 times */
3371                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3372                         ++voltage_tries;
3373                         if (voltage_tries == 5) {
3374                                 DRM_ERROR("too many voltage retries, give up\n");
3375                                 break;
3376                         }
3377                 } else
3378                         voltage_tries = 0;
3379                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3380
3381                 /* Update training set as requested by target */
3382                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3383                         DRM_ERROR("failed to update link training\n");
3384                         break;
3385                 }
3386         }
3387
3388         intel_dp->DP = DP;
3389 }
3390
3391 void
3392 intel_dp_complete_link_train(struct intel_dp *intel_dp)
3393 {
3394         bool channel_eq = false;
3395         int tries, cr_tries;
3396         uint32_t DP = intel_dp->DP;
3397         uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3398
3399         /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3400         if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3401                 training_pattern = DP_TRAINING_PATTERN_3;
3402
3403         /* channel equalization */
3404         if (!intel_dp_set_link_train(intel_dp, &DP,
3405                                      training_pattern |
3406                                      DP_LINK_SCRAMBLING_DISABLE)) {
3407                 DRM_ERROR("failed to start channel equalization\n");
3408                 return;
3409         }
3410
3411         tries = 0;
3412         cr_tries = 0;
3413         channel_eq = false;
3414         for (;;) {
3415                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3416
3417                 if (cr_tries > 5) {
3418                         DRM_ERROR("failed to train DP, aborting\n");
3419                         break;
3420                 }
3421
3422                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3423                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3424                         DRM_ERROR("failed to get link status\n");
3425                         break;
3426                 }
3427
3428                 /* Make sure clock is still ok */
3429                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3430                         intel_dp_start_link_train(intel_dp);
3431                         intel_dp_set_link_train(intel_dp, &DP,
3432                                                 training_pattern |
3433                                                 DP_LINK_SCRAMBLING_DISABLE);
3434                         cr_tries++;
3435                         continue;
3436                 }
3437
3438                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3439                         channel_eq = true;
3440                         break;
3441                 }
3442
3443                 /* Try 5 times, then try clock recovery if that fails */
3444                 if (tries > 5) {
3445                         intel_dp_link_down(intel_dp);
3446                         intel_dp_start_link_train(intel_dp);
3447                         intel_dp_set_link_train(intel_dp, &DP,
3448                                                 training_pattern |
3449                                                 DP_LINK_SCRAMBLING_DISABLE);
3450                         tries = 0;
3451                         cr_tries++;
3452                         continue;
3453                 }
3454
3455                 /* Update training set as requested by target */
3456                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3457                         DRM_ERROR("failed to update link training\n");
3458                         break;
3459                 }
3460                 ++tries;
3461         }
3462
3463         intel_dp_set_idle_link_train(intel_dp);
3464
3465         intel_dp->DP = DP;
3466
3467         if (channel_eq)
3468                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3469
3470 }
3471
3472 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3473 {
3474         intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3475                                 DP_TRAINING_PATTERN_DISABLE);
3476 }
3477
3478 static void
3479 intel_dp_link_down(struct intel_dp *intel_dp)
3480 {
3481         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3482         enum port port = intel_dig_port->port;
3483         struct drm_device *dev = intel_dig_port->base.base.dev;
3484         struct drm_i915_private *dev_priv = dev->dev_private;
3485         struct intel_crtc *intel_crtc =
3486                 to_intel_crtc(intel_dig_port->base.base.crtc);
3487         uint32_t DP = intel_dp->DP;
3488
3489         if (WARN_ON(HAS_DDI(dev)))
3490                 return;
3491
3492         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3493                 return;
3494
3495         DRM_DEBUG_KMS("\n");
3496
3497         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
3498                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3499                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
3500         } else {
3501                 DP &= ~DP_LINK_TRAIN_MASK;
3502                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
3503         }
3504         POSTING_READ(intel_dp->output_reg);
3505
3506         if (HAS_PCH_IBX(dev) &&
3507             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
3508                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
3509
3510                 /* Hardware workaround: leaving our transcoder select
3511                  * set to transcoder B while it's off will prevent the
3512                  * corresponding HDMI output on transcoder A.
3513                  *
3514                  * Combine this with another hardware workaround:
3515                  * transcoder select bit can only be cleared while the
3516                  * port is enabled.
3517                  */
3518                 DP &= ~DP_PIPEB_SELECT;
3519                 I915_WRITE(intel_dp->output_reg, DP);
3520
3521                 /* Changes to enable or select take place the vblank
3522                  * after being written.
3523                  */
3524                 if (WARN_ON(crtc == NULL)) {
3525                         /* We should never try to disable a port without a crtc
3526                          * attached. For paranoia keep the code around for a
3527                          * bit. */
3528                         POSTING_READ(intel_dp->output_reg);
3529                         msleep(50);
3530                 } else
3531                         intel_wait_for_vblank(dev, intel_crtc->pipe);
3532         }
3533
3534         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
3535         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3536         POSTING_READ(intel_dp->output_reg);
3537         msleep(intel_dp->panel_power_down_delay);
3538 }
3539
3540 static bool
3541 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3542 {
3543         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3544         struct drm_device *dev = dig_port->base.base.dev;
3545         struct drm_i915_private *dev_priv = dev->dev_private;
3546
3547         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3548
3549         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
3550                                            sizeof(intel_dp->dpcd)) == 0)
3551                 return false; /* aux transfer failed */
3552
3553         ksnprintf(dpcd_hex_dump,
3554                   sizeof(dpcd_hex_dump),
3555                   "%02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
3556                   intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
3557                   intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
3558                   intel_dp->dpcd[6], intel_dp->dpcd[7]);
3559         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3560
3561         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3562                 return false; /* DPCD not present */
3563
3564         /* Check if the panel supports PSR */
3565         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3566         if (is_edp(intel_dp)) {
3567                 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
3568                                                intel_dp->psr_dpcd,
3569                                                sizeof(intel_dp->psr_dpcd));
3570                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3571                         dev_priv->psr.sink_support = true;
3572                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3573                 }
3574         }
3575
3576         /* Training Pattern 3 support */
3577         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3578             intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3579                 intel_dp->use_tps3 = true;
3580                 DRM_DEBUG_KMS("Displayport TPS3 supported");
3581         } else
3582                 intel_dp->use_tps3 = false;
3583
3584         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3585               DP_DWN_STRM_PORT_PRESENT))
3586                 return true; /* native DP sink */
3587
3588         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3589                 return true; /* no per-port downstream info */
3590
3591         if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
3592                                            intel_dp->downstream_ports,
3593                                            DP_MAX_DOWNSTREAM_PORTS) == 0)
3594                 return false; /* downstream port status fetch failed */
3595
3596         return true;
3597 }
3598
3599 static void
3600 intel_dp_probe_oui(struct intel_dp *intel_dp)
3601 {
3602         u8 buf[3];
3603
3604         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3605                 return;
3606
3607         intel_edp_panel_vdd_on(intel_dp);
3608
3609         if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
3610                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3611                               buf[0], buf[1], buf[2]);
3612
3613         if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
3614                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3615                               buf[0], buf[1], buf[2]);
3616
3617         edp_panel_vdd_off(intel_dp, false);
3618 }
3619
3620 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3621 {
3622         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3623         struct drm_device *dev = intel_dig_port->base.base.dev;
3624         struct intel_crtc *intel_crtc =
3625                 to_intel_crtc(intel_dig_port->base.base.crtc);
3626         u8 buf[1];
3627
3628         if (!intel_dp_aux_native_read(intel_dp, DP_TEST_SINK_MISC, buf, 1))
3629                 return -EAGAIN;
3630
3631         if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3632                 return -ENOTTY;
3633
3634         if (!intel_dp_aux_native_write_1(intel_dp, DP_TEST_SINK,
3635                                          DP_TEST_SINK_START))
3636                 return -EAGAIN;
3637
3638         /* Wait 2 vblanks to be sure we will have the correct CRC value */
3639         intel_wait_for_vblank(dev, intel_crtc->pipe);
3640         intel_wait_for_vblank(dev, intel_crtc->pipe);
3641
3642         if (!intel_dp_aux_native_read(intel_dp, DP_TEST_CRC_R_CR, crc, 6))
3643                 return -EAGAIN;
3644
3645         intel_dp_aux_native_write_1(intel_dp, DP_TEST_SINK, 0);
3646         return 0;
3647 }
3648
3649 static bool
3650 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3651 {
3652         int ret;
3653
3654         ret = intel_dp_aux_native_read_retry(intel_dp,
3655                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
3656                                              sink_irq_vector, 1);
3657         if (!ret)
3658                 return false;
3659
3660         return true;
3661 }
3662
3663 static void
3664 intel_dp_handle_test_request(struct intel_dp *intel_dp)
3665 {
3666         /* NAK by default */
3667         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
3668 }
3669
3670 /*
3671  * According to DP spec
3672  * 5.1.2:
3673  *  1. Read DPCD
3674  *  2. Configure link according to Receiver Capabilities
3675  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
3676  *  4. Check link status on receipt of hot-plug interrupt
3677  */
3678
3679 void
3680 intel_dp_check_link_status(struct intel_dp *intel_dp)
3681 {
3682         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3683         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3684         u8 sink_irq_vector;
3685         u8 link_status[DP_LINK_STATUS_SIZE];
3686
3687         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3688
3689         if (!intel_encoder->connectors_active)
3690                 return;
3691
3692         if (WARN_ON(!intel_encoder->base.crtc))
3693                 return;
3694
3695         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3696                 return;
3697
3698         /* Try to read receiver status if the link appears to be up */
3699         if (!intel_dp_get_link_status(intel_dp, link_status)) {
3700                 return;
3701         }
3702
3703         /* Now read the DPCD to see if it's actually running */
3704         if (!intel_dp_get_dpcd(intel_dp)) {
3705                 return;
3706         }
3707
3708         /* Try to read the source of the interrupt */
3709         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3710             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3711                 /* Clear interrupt source */
3712                 intel_dp_aux_native_write_1(intel_dp,
3713                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
3714                                             sink_irq_vector);
3715
3716                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3717                         intel_dp_handle_test_request(intel_dp);
3718                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3719                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3720         }
3721
3722         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3723                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3724                               intel_encoder->base.name);
3725                 intel_dp_start_link_train(intel_dp);
3726                 intel_dp_complete_link_train(intel_dp);
3727                 intel_dp_stop_link_train(intel_dp);
3728         }
3729 }
3730
3731 /* XXX this is probably wrong for multiple downstream ports */
3732 static enum drm_connector_status
3733 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3734 {
3735         uint8_t *dpcd = intel_dp->dpcd;
3736         uint8_t type;
3737
3738         if (!intel_dp_get_dpcd(intel_dp))
3739                 return connector_status_disconnected;
3740
3741         /* if there's no downstream port, we're done */
3742         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3743                 return connector_status_connected;
3744
3745         /* If we're HPD-aware, SINK_COUNT changes dynamically */
3746         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3747             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3748                 uint8_t reg;
3749                 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
3750                                                     &reg, 1))
3751                         return connector_status_unknown;
3752                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3753                                               : connector_status_disconnected;
3754         }
3755
3756         /* If no HPD, poke DDC gently */
3757         if (drm_probe_ddc(intel_dp->aux.ddc))
3758                 return connector_status_connected;
3759
3760         /* Well we tried, say unknown for unreliable port types */
3761         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3762                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3763                 if (type == DP_DS_PORT_TYPE_VGA ||
3764                     type == DP_DS_PORT_TYPE_NON_EDID)
3765                         return connector_status_unknown;
3766         } else {
3767                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3768                         DP_DWN_STRM_PORT_TYPE_MASK;
3769                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3770                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
3771                         return connector_status_unknown;
3772         }
3773
3774         /* Anything else is out of spec, warn and ignore */
3775         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3776         return connector_status_disconnected;
3777 }
3778
3779 static enum drm_connector_status
3780 ironlake_dp_detect(struct intel_dp *intel_dp)
3781 {
3782         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3783         struct drm_i915_private *dev_priv = dev->dev_private;
3784         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3785         enum drm_connector_status status;
3786
3787         /* Can't disconnect eDP, but you can close the lid... */
3788         if (is_edp(intel_dp)) {
3789                 status = intel_panel_detect(dev);
3790                 if (status == connector_status_unknown)
3791                         status = connector_status_connected;
3792                 return status;
3793         }
3794
3795         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3796                 return connector_status_disconnected;
3797
3798         return intel_dp_detect_dpcd(intel_dp);
3799 }
3800
3801 static int g4x_digital_port_connected(struct drm_device *dev,
3802                                        struct intel_digital_port *intel_dig_port)
3803 {
3804         struct drm_i915_private *dev_priv = dev->dev_private;
3805         uint32_t bit;
3806
3807         if (IS_VALLEYVIEW(dev)) {
3808                 switch (intel_dig_port->port) {
3809                 case PORT_B:
3810                         bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3811                         break;
3812                 case PORT_C:
3813                         bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3814                         break;
3815                 case PORT_D:
3816                         bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3817                         break;
3818                 default:
3819                         return -EINVAL;
3820                 }
3821         } else {
3822                 switch (intel_dig_port->port) {
3823                 case PORT_B:
3824                         bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3825                         break;
3826                 case PORT_C:
3827                         bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3828                         break;
3829                 case PORT_D:
3830                         bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3831                         break;
3832                 default:
3833                         return -EINVAL;
3834                 }
3835         }
3836
3837         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3838                 return 0;
3839         return 1;
3840 }
3841
3842 static enum drm_connector_status
3843 g4x_dp_detect(struct intel_dp *intel_dp)
3844 {
3845         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3846         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3847         int ret;
3848
3849         /* Can't disconnect eDP, but you can close the lid... */
3850         if (is_edp(intel_dp)) {
3851                 enum drm_connector_status status;
3852
3853                 status = intel_panel_detect(dev);
3854                 if (status == connector_status_unknown)
3855                         status = connector_status_connected;
3856                 return status;
3857         }
3858
3859         ret = g4x_digital_port_connected(dev, intel_dig_port);
3860         if (ret == -EINVAL)
3861                 return connector_status_unknown;
3862         else if (ret == 0)
3863                 return connector_status_disconnected;
3864
3865         return intel_dp_detect_dpcd(intel_dp);
3866 }
3867
3868 static struct edid *
3869 intel_dp_get_edid(struct drm_connector *connector, struct device *adapter)
3870 {
3871         struct intel_connector *intel_connector = to_intel_connector(connector);
3872
3873         /* use cached edid if we have one */
3874         if (intel_connector->edid) {
3875                 /* invalid edid */
3876                 if (IS_ERR(intel_connector->edid))
3877                         return NULL;
3878
3879                 return drm_edid_duplicate(intel_connector->edid);
3880         }
3881
3882         return drm_get_edid(connector, adapter);
3883 }
3884
3885 static int
3886 intel_dp_get_edid_modes(struct drm_connector *connector, struct device *adapter)
3887 {
3888         struct intel_connector *intel_connector = to_intel_connector(connector);
3889
3890         /* use cached edid if we have one */
3891         if (intel_connector->edid) {
3892                 /* invalid edid */
3893                 if (IS_ERR(intel_connector->edid))
3894                         return 0;
3895
3896                 return intel_connector_update_modes(connector,
3897                                                     intel_connector->edid);
3898         }
3899
3900         return intel_ddc_get_modes(connector, adapter);
3901 }
3902
3903 static enum drm_connector_status
3904 intel_dp_detect(struct drm_connector *connector, bool force)
3905 {
3906         struct intel_dp *intel_dp = intel_attached_dp(connector);
3907         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3908         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3909         struct drm_device *dev = connector->dev;
3910         struct drm_i915_private *dev_priv = dev->dev_private;
3911         enum drm_connector_status status;
3912         enum intel_display_power_domain power_domain;
3913         struct edid *edid = NULL;
3914
3915         power_domain = intel_display_port_power_domain(intel_encoder);
3916         intel_display_power_get(dev_priv, power_domain);
3917
3918         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3919                       connector->base.id, connector->name);
3920
3921         intel_dp->has_audio = false;
3922
3923         if (HAS_PCH_SPLIT(dev))
3924                 status = ironlake_dp_detect(intel_dp);
3925         else
3926                 status = g4x_dp_detect(intel_dp);
3927
3928         if (status != connector_status_connected)
3929                 goto out;
3930
3931         intel_dp_probe_oui(intel_dp);
3932
3933         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3934                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3935         } else {
3936                 edid = intel_dp_get_edid(connector, intel_dp->aux.ddc);
3937                 if (edid) {
3938                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
3939                         kfree(edid);
3940                 }
3941         }
3942
3943         if (intel_encoder->type != INTEL_OUTPUT_EDP)
3944                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3945         status = connector_status_connected;
3946
3947 out:
3948         intel_display_power_put(dev_priv, power_domain);
3949         return status;
3950 }
3951
3952 static int intel_dp_get_modes(struct drm_connector *connector)
3953 {
3954         struct intel_dp *intel_dp = intel_attached_dp(connector);
3955         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3956         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3957         struct intel_connector *intel_connector = to_intel_connector(connector);
3958         struct drm_device *dev = connector->dev;
3959         struct drm_i915_private *dev_priv = dev->dev_private;
3960         enum intel_display_power_domain power_domain;
3961         int ret;
3962
3963         /* We should parse the EDID data and find out if it has an audio sink
3964          */
3965
3966         power_domain = intel_display_port_power_domain(intel_encoder);
3967         intel_display_power_get(dev_priv, power_domain);
3968
3969         ret = intel_dp_get_edid_modes(connector, intel_dp->aux.ddc);
3970         intel_display_power_put(dev_priv, power_domain);
3971         if (ret)
3972                 return ret;
3973
3974         /* if eDP has no EDID, fall back to fixed mode */
3975         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3976                 struct drm_display_mode *mode;
3977                 mode = drm_mode_duplicate(dev,
3978                                           intel_connector->panel.fixed_mode);
3979                 if (mode) {
3980                         drm_mode_probed_add(connector, mode);
3981                         return 1;
3982                 }
3983         }
3984         return 0;
3985 }
3986
3987 static bool
3988 intel_dp_detect_audio(struct drm_connector *connector)
3989 {
3990         struct intel_dp *intel_dp = intel_attached_dp(connector);
3991         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3992         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3993         struct drm_device *dev = connector->dev;
3994         struct drm_i915_private *dev_priv = dev->dev_private;
3995         enum intel_display_power_domain power_domain;
3996         struct edid *edid;
3997         bool has_audio = false;
3998
3999         power_domain = intel_display_port_power_domain(intel_encoder);
4000         intel_display_power_get(dev_priv, power_domain);
4001
4002         edid = intel_dp_get_edid(connector, intel_dp->aux.ddc);
4003         if (edid) {
4004                 has_audio = drm_detect_monitor_audio(edid);
4005                 kfree(edid);
4006         }
4007
4008         intel_display_power_put(dev_priv, power_domain);
4009
4010         return has_audio;
4011 }
4012
4013 static int
4014 intel_dp_set_property(struct drm_connector *connector,
4015                       struct drm_property *property,
4016                       uint64_t val)
4017 {
4018         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4019         struct intel_connector *intel_connector = to_intel_connector(connector);
4020         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4021         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4022         int ret;
4023
4024         ret = drm_object_property_set_value(&connector->base, property, val);
4025         if (ret)
4026                 return ret;
4027
4028         if (property == dev_priv->force_audio_property) {
4029                 int i = val;
4030                 bool has_audio;
4031
4032                 if (i == intel_dp->force_audio)
4033                         return 0;
4034
4035                 intel_dp->force_audio = i;
4036
4037                 if (i == HDMI_AUDIO_AUTO)
4038                         has_audio = intel_dp_detect_audio(connector);
4039                 else
4040                         has_audio = (i == HDMI_AUDIO_ON);
4041
4042                 if (has_audio == intel_dp->has_audio)
4043                         return 0;
4044
4045                 intel_dp->has_audio = has_audio;
4046                 goto done;
4047         }
4048
4049         if (property == dev_priv->broadcast_rgb_property) {
4050                 bool old_auto = intel_dp->color_range_auto;
4051                 uint32_t old_range = intel_dp->color_range;
4052
4053                 switch (val) {
4054                 case INTEL_BROADCAST_RGB_AUTO:
4055                         intel_dp->color_range_auto = true;
4056                         break;
4057                 case INTEL_BROADCAST_RGB_FULL:
4058                         intel_dp->color_range_auto = false;
4059                         intel_dp->color_range = 0;
4060                         break;
4061                 case INTEL_BROADCAST_RGB_LIMITED:
4062                         intel_dp->color_range_auto = false;
4063                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
4064                         break;
4065                 default:
4066                         return -EINVAL;
4067                 }
4068
4069                 if (old_auto == intel_dp->color_range_auto &&
4070                     old_range == intel_dp->color_range)
4071                         return 0;
4072
4073                 goto done;
4074         }
4075
4076         if (is_edp(intel_dp) &&
4077             property == connector->dev->mode_config.scaling_mode_property) {
4078                 if (val == DRM_MODE_SCALE_NONE) {
4079                         DRM_DEBUG_KMS("no scaling not supported\n");
4080                         return -EINVAL;
4081                 }
4082
4083                 if (intel_connector->panel.fitting_mode == val) {
4084                         /* the eDP scaling property is not changed */
4085                         return 0;
4086                 }
4087                 intel_connector->panel.fitting_mode = val;
4088
4089                 goto done;
4090         }
4091
4092         return -EINVAL;
4093
4094 done:
4095         if (intel_encoder->base.crtc)
4096                 intel_crtc_restore_mode(intel_encoder->base.crtc);
4097
4098         return 0;
4099 }
4100
4101 static void
4102 intel_dp_connector_destroy(struct drm_connector *connector)
4103 {
4104         struct intel_connector *intel_connector = to_intel_connector(connector);
4105
4106         if (!IS_ERR_OR_NULL(intel_connector->edid))
4107                 kfree(intel_connector->edid);
4108
4109         /* Can't call is_edp() since the encoder may have been destroyed
4110          * already. */
4111         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4112                 intel_panel_fini(&intel_connector->panel);
4113
4114         drm_connector_cleanup(connector);
4115         kfree(connector);
4116 }
4117
4118 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4119 {
4120         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4121         struct intel_dp *intel_dp = &intel_dig_port->dp;
4122         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4123
4124         if (intel_dp->dp_iic_bus != NULL) {
4125                 if (intel_dp->aux.ddc != NULL) {
4126                         device_delete_child(intel_dp->dp_iic_bus,
4127                             intel_dp->aux.ddc);
4128                 }
4129                 device_delete_child(dev->dev, intel_dp->dp_iic_bus);
4130         }
4131
4132         drm_encoder_cleanup(encoder);
4133         if (is_edp(intel_dp)) {
4134                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4135                 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4136                 edp_panel_vdd_off_sync(intel_dp);
4137                 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4138 #if 0
4139                 if (intel_dp->edp_notifier.notifier_call) {
4140                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4141                         intel_dp->edp_notifier.notifier_call = NULL;
4142                 }
4143 #endif
4144         }
4145         kfree(intel_dig_port);
4146 }
4147
4148 static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4149 {
4150         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4151
4152         if (!is_edp(intel_dp))
4153                 return;
4154
4155         edp_panel_vdd_off_sync(intel_dp);
4156 }
4157
4158 static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4159 {
4160         intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4161 }
4162
4163 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4164         .dpms = intel_connector_dpms,
4165         .detect = intel_dp_detect,
4166         .fill_modes = drm_helper_probe_single_connector_modes,
4167         .set_property = intel_dp_set_property,
4168         .destroy = intel_dp_connector_destroy,
4169 };
4170
4171 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4172         .get_modes = intel_dp_get_modes,
4173         .mode_valid = intel_dp_mode_valid,
4174         .best_encoder = intel_best_encoder,
4175 };
4176
4177 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4178         .reset = intel_dp_encoder_reset,
4179         .destroy = intel_dp_encoder_destroy,
4180 };
4181
4182 void
4183 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
4184 {
4185         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4186
4187         intel_dp_check_link_status(intel_dp);
4188 }
4189
4190 bool
4191 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4192 {
4193         struct intel_dp *intel_dp = &intel_dig_port->dp;
4194         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4195         struct drm_device *dev = intel_dig_port->base.base.dev;
4196         struct drm_i915_private *dev_priv = dev->dev_private;
4197         enum intel_display_power_domain power_domain;
4198         bool ret = true;
4199
4200         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4201                 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4202
4203         DRM_DEBUG_KMS("got hpd irq on port %d - %s\n", intel_dig_port->port,
4204                       long_hpd ? "long" : "short");
4205
4206         power_domain = intel_display_port_power_domain(intel_encoder);
4207         intel_display_power_get(dev_priv, power_domain);
4208
4209         if (long_hpd) {
4210                 ret = true;
4211                 goto put_power;
4212         }
4213
4214         /*
4215          * we'll check the link status via the normal hot plug path later -
4216          * but for short hpds we should check it now
4217          */
4218         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4219         intel_dp_check_link_status(intel_dp);
4220         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4221         ret = false;
4222
4223 put_power:
4224         intel_display_power_put(dev_priv, power_domain);
4225
4226         return ret;
4227 }
4228
4229 /* Return which DP Port should be selected for Transcoder DP control */
4230 int
4231 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4232 {
4233         struct drm_device *dev = crtc->dev;
4234         struct intel_encoder *intel_encoder;
4235         struct intel_dp *intel_dp;
4236
4237         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4238                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4239
4240                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4241                     intel_encoder->type == INTEL_OUTPUT_EDP)
4242                         return intel_dp->output_reg;
4243         }
4244
4245         return -1;
4246 }
4247
4248 /* check the VBT to see whether the eDP is on DP-D port */
4249 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4250 {
4251         struct drm_i915_private *dev_priv = dev->dev_private;
4252         union child_device_config *p_child;
4253         int i;
4254         static const short port_mapping[] = {
4255                 [PORT_B] = PORT_IDPB,
4256                 [PORT_C] = PORT_IDPC,
4257                 [PORT_D] = PORT_IDPD,
4258         };
4259
4260         if (port == PORT_A)
4261                 return true;
4262
4263         if (!dev_priv->vbt.child_dev_num)
4264                 return false;
4265
4266         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4267                 p_child = dev_priv->vbt.child_dev + i;
4268
4269                 if (p_child->common.dvo_port == port_mapping[port] &&
4270                     (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4271                     (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
4272                         return true;
4273         }
4274         return false;
4275 }
4276
4277 void
4278 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4279 {
4280         struct intel_connector *intel_connector = to_intel_connector(connector);
4281
4282         intel_attach_force_audio_property(connector);
4283         intel_attach_broadcast_rgb_property(connector);
4284         intel_dp->color_range_auto = true;
4285
4286         if (is_edp(intel_dp)) {
4287                 drm_mode_create_scaling_mode_property(connector->dev);
4288                 drm_object_attach_property(
4289                         &connector->base,
4290                         connector->dev->mode_config.scaling_mode_property,
4291                         DRM_MODE_SCALE_ASPECT);
4292                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4293         }
4294 }
4295
4296 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4297 {
4298         intel_dp->last_power_cycle = jiffies;
4299         intel_dp->last_power_on = jiffies;
4300         intel_dp->last_backlight_off = jiffies;
4301 }
4302
4303 static void
4304 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4305                                     struct intel_dp *intel_dp,
4306                                     struct edp_power_seq *out)
4307 {
4308         struct drm_i915_private *dev_priv = dev->dev_private;
4309         struct edp_power_seq cur, vbt, spec, final;
4310         u32 pp_on, pp_off, pp_div, pp;
4311         int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
4312
4313         if (HAS_PCH_SPLIT(dev)) {
4314                 pp_ctrl_reg = PCH_PP_CONTROL;
4315                 pp_on_reg = PCH_PP_ON_DELAYS;
4316                 pp_off_reg = PCH_PP_OFF_DELAYS;
4317                 pp_div_reg = PCH_PP_DIVISOR;
4318         } else {
4319                 enum i915_pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4320
4321                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4322                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4323                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4324                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4325         }
4326
4327         /* Workaround: Need to write PP_CONTROL with the unlock key as
4328          * the very first thing. */
4329         pp = ironlake_get_pp_control(intel_dp);
4330         I915_WRITE(pp_ctrl_reg, pp);
4331
4332         pp_on = I915_READ(pp_on_reg);
4333         pp_off = I915_READ(pp_off_reg);
4334         pp_div = I915_READ(pp_div_reg);
4335
4336         /* Pull timing values out of registers */
4337         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4338                 PANEL_POWER_UP_DELAY_SHIFT;
4339
4340         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4341                 PANEL_LIGHT_ON_DELAY_SHIFT;
4342
4343         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4344                 PANEL_LIGHT_OFF_DELAY_SHIFT;
4345
4346         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4347                 PANEL_POWER_DOWN_DELAY_SHIFT;
4348
4349         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4350                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4351
4352         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4353                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4354
4355         vbt = dev_priv->vbt.edp_pps;
4356
4357         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4358          * our hw here, which are all in 100usec. */
4359         spec.t1_t3 = 210 * 10;
4360         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4361         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4362         spec.t10 = 500 * 10;
4363         /* This one is special and actually in units of 100ms, but zero
4364          * based in the hw (so we need to add 100 ms). But the sw vbt
4365          * table multiplies it with 1000 to make it in units of 100usec,
4366          * too. */
4367         spec.t11_t12 = (510 + 100) * 10;
4368
4369         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4370                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4371
4372         /* Use the max of the register settings and vbt. If both are
4373          * unset, fall back to the spec limits. */
4374 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
4375                                        spec.field : \
4376                                        max(cur.field, vbt.field))
4377         assign_final(t1_t3);
4378         assign_final(t8);
4379         assign_final(t9);
4380         assign_final(t10);
4381         assign_final(t11_t12);
4382 #undef assign_final
4383
4384 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
4385         intel_dp->panel_power_up_delay = get_delay(t1_t3);
4386         intel_dp->backlight_on_delay = get_delay(t8);
4387         intel_dp->backlight_off_delay = get_delay(t9);
4388         intel_dp->panel_power_down_delay = get_delay(t10);
4389         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4390 #undef get_delay
4391
4392         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4393                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4394                       intel_dp->panel_power_cycle_delay);
4395
4396         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4397                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4398
4399         if (out)
4400                 *out = final;
4401 }
4402
4403 static void
4404 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4405                                               struct intel_dp *intel_dp,
4406                                               struct edp_power_seq *seq)
4407 {
4408         struct drm_i915_private *dev_priv = dev->dev_private;
4409         u32 pp_on, pp_off, pp_div, port_sel = 0;
4410         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4411         int pp_on_reg, pp_off_reg, pp_div_reg;
4412
4413         if (HAS_PCH_SPLIT(dev)) {
4414                 pp_on_reg = PCH_PP_ON_DELAYS;
4415                 pp_off_reg = PCH_PP_OFF_DELAYS;
4416                 pp_div_reg = PCH_PP_DIVISOR;
4417         } else {
4418                 enum i915_pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4419
4420                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4421                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4422                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4423         }
4424
4425         /*
4426          * And finally store the new values in the power sequencer. The
4427          * backlight delays are set to 1 because we do manual waits on them. For
4428          * T8, even BSpec recommends doing it. For T9, if we don't do this,
4429          * we'll end up waiting for the backlight off delay twice: once when we
4430          * do the manual sleep, and once when we disable the panel and wait for
4431          * the PP_STATUS bit to become zero.
4432          */
4433         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4434                 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4435         pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
4436                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
4437         /* Compute the divisor for the pp clock, simply match the Bspec
4438          * formula. */
4439         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4440         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4441                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
4442
4443         /* Haswell doesn't have any port selection bits for the panel
4444          * power sequencer any more. */
4445         if (IS_VALLEYVIEW(dev)) {
4446                 if (dp_to_dig_port(intel_dp)->port == PORT_B)
4447                         port_sel = PANEL_PORT_SELECT_DPB_VLV;
4448                 else
4449                         port_sel = PANEL_PORT_SELECT_DPC_VLV;
4450         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4451                 if (dp_to_dig_port(intel_dp)->port == PORT_A)
4452                         port_sel = PANEL_PORT_SELECT_DPA;
4453                 else
4454                         port_sel = PANEL_PORT_SELECT_DPD;
4455         }
4456
4457         pp_on |= port_sel;
4458
4459         I915_WRITE(pp_on_reg, pp_on);
4460         I915_WRITE(pp_off_reg, pp_off);
4461         I915_WRITE(pp_div_reg, pp_div);
4462
4463         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4464                       I915_READ(pp_on_reg),
4465                       I915_READ(pp_off_reg),
4466                       I915_READ(pp_div_reg));
4467 }
4468
4469 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4470 {
4471         struct drm_i915_private *dev_priv = dev->dev_private;
4472         struct intel_encoder *encoder;
4473         struct intel_dp *intel_dp = NULL;
4474         struct intel_crtc_config *config = NULL;
4475         struct intel_crtc *intel_crtc = NULL;
4476         struct intel_connector *intel_connector = dev_priv->drrs.connector;
4477         u32 reg, val;
4478         enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4479
4480         if (refresh_rate <= 0) {
4481                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4482                 return;
4483         }
4484
4485         if (intel_connector == NULL) {
4486                 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4487                 return;
4488         }
4489
4490         /*
4491          * FIXME: This needs proper synchronization with psr state. But really
4492          * hard to tell without seeing the user of this function of this code.
4493          * Check locking and ordering once that lands.
4494          */
4495         if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4496                 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4497                 return;
4498         }
4499
4500         encoder = intel_attached_encoder(&intel_connector->base);
4501         intel_dp = enc_to_intel_dp(&encoder->base);
4502         intel_crtc = encoder->new_crtc;
4503
4504         if (!intel_crtc) {
4505                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4506                 return;
4507         }
4508
4509         config = &intel_crtc->config;
4510
4511         if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4512                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4513                 return;
4514         }
4515
4516         if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4517                 index = DRRS_LOW_RR;
4518
4519         if (index == intel_dp->drrs_state.refresh_rate_type) {
4520                 DRM_DEBUG_KMS(
4521                         "DRRS requested for previously set RR...ignoring\n");
4522                 return;
4523         }
4524
4525         if (!intel_crtc->active) {
4526                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4527                 return;
4528         }
4529
4530         if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4531                 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4532                 val = I915_READ(reg);
4533                 if (index > DRRS_HIGH_RR) {
4534                         val |= PIPECONF_EDP_RR_MODE_SWITCH;
4535                         intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
4536                 } else {
4537                         val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4538                 }
4539                 I915_WRITE(reg, val);
4540         }
4541
4542         /*
4543          * mutex taken to ensure that there is no race between differnt
4544          * drrs calls trying to update refresh rate. This scenario may occur
4545          * in future when idleness detection based DRRS in kernel and
4546          * possible calls from user space to set differnt RR are made.
4547          */
4548
4549         mutex_lock(&intel_dp->drrs_state.mutex);
4550
4551         intel_dp->drrs_state.refresh_rate_type = index;
4552
4553         mutex_unlock(&intel_dp->drrs_state.mutex);
4554
4555         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4556 }
4557
4558 static struct drm_display_mode *
4559 intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4560                         struct intel_connector *intel_connector,
4561                         struct drm_display_mode *fixed_mode)
4562 {
4563         struct drm_connector *connector = &intel_connector->base;
4564         struct intel_dp *intel_dp = &intel_dig_port->dp;
4565         struct drm_device *dev = intel_dig_port->base.base.dev;
4566         struct drm_i915_private *dev_priv = dev->dev_private;
4567         struct drm_display_mode *downclock_mode = NULL;
4568
4569         if (INTEL_INFO(dev)->gen <= 6) {
4570                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4571                 return NULL;
4572         }
4573
4574         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4575                 DRM_INFO("VBT doesn't support DRRS\n");
4576                 return NULL;
4577         }
4578
4579         downclock_mode = intel_find_panel_downclock
4580                                         (dev, fixed_mode, connector);
4581
4582         if (!downclock_mode) {
4583                 DRM_INFO("DRRS not supported\n");
4584                 return NULL;
4585         }
4586
4587         dev_priv->drrs.connector = intel_connector;
4588
4589         lockinit(&intel_dp->drrs_state.mutex, "i915dsm", 0, LK_CANRECURSE);
4590
4591         intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4592
4593         intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4594         DRM_INFO("seamless DRRS supported for eDP panel.\n");
4595         return downclock_mode;
4596 }
4597
4598 void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4599 {
4600         struct drm_device *dev = intel_encoder->base.dev;
4601         struct drm_i915_private *dev_priv = dev->dev_private;
4602         struct intel_dp *intel_dp;
4603         enum intel_display_power_domain power_domain;
4604
4605         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4606                 return;
4607
4608         intel_dp = enc_to_intel_dp(&intel_encoder->base);
4609         if (!edp_have_panel_vdd(intel_dp))
4610                 return;
4611         /*
4612          * The VDD bit needs a power domain reference, so if the bit is
4613          * already enabled when we boot or resume, grab this reference and
4614          * schedule a vdd off, so we don't hold on to the reference
4615          * indefinitely.
4616          */
4617         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4618         power_domain = intel_display_port_power_domain(intel_encoder);
4619         intel_display_power_get(dev_priv, power_domain);
4620
4621         edp_panel_vdd_schedule_off(intel_dp);
4622 }
4623
4624 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
4625                                      struct intel_connector *intel_connector,
4626                                      struct edp_power_seq *power_seq)
4627 {
4628         struct drm_connector *connector = &intel_connector->base;
4629         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4630         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4631         struct drm_device *dev = intel_encoder->base.dev;
4632         struct drm_i915_private *dev_priv = dev->dev_private;
4633         struct drm_display_mode *fixed_mode = NULL;
4634         struct drm_display_mode *downclock_mode = NULL;
4635         bool has_dpcd;
4636         struct drm_display_mode *scan;
4637         struct edid *edid;
4638
4639         intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4640
4641         if (!is_edp(intel_dp))
4642                 return true;
4643
4644         intel_edp_panel_vdd_sanitize(intel_encoder);
4645
4646         /* Cache DPCD and EDID for edp. */
4647         intel_edp_panel_vdd_on(intel_dp);
4648         has_dpcd = intel_dp_get_dpcd(intel_dp);
4649         edp_panel_vdd_off(intel_dp, false);
4650
4651         if (has_dpcd) {
4652                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4653                         dev_priv->no_aux_handshake =
4654                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4655                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4656         } else {
4657                 /* if this fails, presume the device is a ghost */
4658                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
4659                 return false;
4660         }
4661
4662         /* We now know it's not a ghost, init power sequence regs. */
4663         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
4664
4665         mutex_lock(&dev->mode_config.mutex);
4666         edid = drm_get_edid(connector, intel_dp->aux.ddc);
4667         if (edid) {
4668                 if (drm_add_edid_modes(connector, edid)) {
4669                         drm_mode_connector_update_edid_property(connector,
4670                                                                 edid);
4671                         drm_edid_to_eld(connector, edid);
4672                 } else {
4673                         kfree(edid);
4674                         edid = ERR_PTR(-EINVAL);
4675                 }
4676         } else {
4677                 edid = ERR_PTR(-ENOENT);
4678         }
4679         intel_connector->edid = edid;
4680
4681         /* prefer fixed mode from EDID if available */
4682         list_for_each_entry(scan, &connector->probed_modes, head) {
4683                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4684                         fixed_mode = drm_mode_duplicate(dev, scan);
4685                         downclock_mode = intel_dp_drrs_init(
4686                                                 intel_dig_port,
4687                                                 intel_connector, fixed_mode);
4688                         break;
4689                 }
4690         }
4691
4692         /* fallback to VBT if available for eDP */
4693         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4694                 fixed_mode = drm_mode_duplicate(dev,
4695                                         dev_priv->vbt.lfp_lvds_vbt_mode);
4696                 if (fixed_mode)
4697                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4698         }
4699         mutex_unlock(&dev->mode_config.mutex);
4700
4701 #if 0
4702         if (IS_VALLEYVIEW(dev)) {
4703                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
4704                 register_reboot_notifier(&intel_dp->edp_notifier);
4705         }
4706 #endif
4707
4708         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
4709         intel_panel_setup_backlight(connector);
4710
4711         return true;
4712 }
4713
4714 bool
4715 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4716                         struct intel_connector *intel_connector)
4717 {
4718         struct drm_connector *connector = &intel_connector->base;
4719         struct intel_dp *intel_dp = &intel_dig_port->dp;
4720         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4721         struct drm_device *dev = intel_encoder->base.dev;
4722         struct drm_i915_private *dev_priv = dev->dev_private;
4723         enum port port = intel_dig_port->port;
4724         struct edp_power_seq power_seq = { 0 };
4725         int type;
4726
4727         /* intel_dp vfuncs */
4728         if (IS_VALLEYVIEW(dev))
4729                 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4730         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4731                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4732         else if (HAS_PCH_SPLIT(dev))
4733                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4734         else
4735                 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4736
4737         intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4738
4739         /* Preserve the current hw state. */
4740         intel_dp->DP = I915_READ(intel_dp->output_reg);
4741         intel_dp->attached_connector = intel_connector;
4742
4743         if (intel_dp_is_edp(dev, port))
4744                 type = DRM_MODE_CONNECTOR_eDP;
4745         else
4746                 type = DRM_MODE_CONNECTOR_DisplayPort;
4747
4748         /*
4749          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4750          * for DP the encoder type can be set by the caller to
4751          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4752          */
4753         if (type == DRM_MODE_CONNECTOR_eDP)
4754                 intel_encoder->type = INTEL_OUTPUT_EDP;
4755
4756         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4757                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4758                         port_name(port));
4759
4760         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
4761         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4762
4763         connector->interlace_allowed = true;
4764         connector->doublescan_allowed = 0;
4765
4766         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4767                           edp_panel_vdd_work);
4768
4769         intel_connector_attach_encoder(intel_connector, intel_encoder);
4770         drm_connector_register(connector);
4771
4772         if (HAS_DDI(dev))
4773                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4774         else
4775                 intel_connector->get_hw_state = intel_connector_get_hw_state;
4776         intel_connector->unregister = intel_dp_connector_unregister;
4777
4778         /* Set up the hotplug pin. */
4779         switch (port) {
4780         case PORT_A:
4781                 intel_encoder->hpd_pin = HPD_PORT_A;
4782                 break;
4783         case PORT_B:
4784                 intel_encoder->hpd_pin = HPD_PORT_B;
4785                 break;
4786         case PORT_C:
4787                 intel_encoder->hpd_pin = HPD_PORT_C;
4788                 break;
4789         case PORT_D:
4790                 intel_encoder->hpd_pin = HPD_PORT_D;
4791                 break;
4792         default:
4793                 BUG();
4794         }
4795
4796         if (is_edp(intel_dp)) {
4797                 intel_dp_init_panel_power_timestamps(intel_dp);
4798                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
4799         }
4800
4801         intel_dp_aux_init(intel_dp, intel_connector);
4802
4803         if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4804 #if 0
4805                 drm_dp_aux_unregister(&intel_dp->aux);
4806                 i2c_del_adapter(&intel_dp->adapter);
4807 #endif
4808                 if (is_edp(intel_dp)) {
4809                         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4810                         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4811                         edp_panel_vdd_off_sync(intel_dp);
4812                         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4813                 }
4814                 drm_connector_unregister(connector);
4815                 drm_connector_cleanup(connector);
4816                 return false;
4817         }
4818
4819         intel_dp_add_properties(intel_dp, connector);
4820
4821         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4822          * 0xd.  Failure to do so will result in spurious interrupts being
4823          * generated on the port when a cable is not attached.
4824          */
4825         if (IS_G4X(dev) && !IS_GM45(dev)) {
4826                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4827                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4828         }
4829
4830         return true;
4831 }
4832
4833 void
4834 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4835 {
4836         struct drm_i915_private *dev_priv = dev->dev_private;
4837         struct intel_digital_port *intel_dig_port;
4838         struct intel_encoder *intel_encoder;
4839         struct drm_encoder *encoder;
4840         struct intel_connector *intel_connector;
4841
4842         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4843         if (!intel_dig_port)
4844                 return;
4845
4846         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
4847         if (!intel_connector) {
4848                 kfree(intel_dig_port);
4849                 return;
4850         }
4851
4852         intel_encoder = &intel_dig_port->base;
4853         encoder = &intel_encoder->base;
4854
4855         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4856                          DRM_MODE_ENCODER_TMDS);
4857
4858         intel_encoder->compute_config = intel_dp_compute_config;
4859         intel_encoder->disable = intel_disable_dp;
4860         intel_encoder->get_hw_state = intel_dp_get_hw_state;
4861         intel_encoder->get_config = intel_dp_get_config;
4862         intel_encoder->suspend = intel_dp_encoder_suspend;
4863         if (IS_CHERRYVIEW(dev)) {
4864                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
4865                 intel_encoder->pre_enable = chv_pre_enable_dp;
4866                 intel_encoder->enable = vlv_enable_dp;
4867                 intel_encoder->post_disable = chv_post_disable_dp;
4868         } else if (IS_VALLEYVIEW(dev)) {
4869                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
4870                 intel_encoder->pre_enable = vlv_pre_enable_dp;
4871                 intel_encoder->enable = vlv_enable_dp;
4872                 intel_encoder->post_disable = vlv_post_disable_dp;
4873         } else {
4874                 intel_encoder->pre_enable = g4x_pre_enable_dp;
4875                 intel_encoder->enable = g4x_enable_dp;
4876                 intel_encoder->post_disable = g4x_post_disable_dp;
4877         }
4878
4879         intel_dig_port->port = port;
4880         intel_dig_port->dp.output_reg = output_reg;
4881
4882         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4883         if (IS_CHERRYVIEW(dev)) {
4884                 if (port == PORT_D)
4885                         intel_encoder->crtc_mask = 1 << 2;
4886                 else
4887                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4888         } else {
4889                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4890         }
4891         intel_encoder->cloneable = 0;
4892         intel_encoder->hot_plug = intel_dp_hot_plug;
4893
4894         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4895         dev_priv->hpd_irq_port[port] = intel_dig_port;
4896
4897         if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4898                 drm_encoder_cleanup(encoder);
4899                 kfree(intel_dig_port);
4900                 kfree(intel_connector);
4901         }
4902 }