2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2004 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c 187831 2009-01-28 18:00:22Z sam $
23 #include "ah_internal.h"
26 #include "ar5210/ar5210.h"
27 #include "ar5210/ar5210reg.h"
28 #include "ar5210/ar5210phy.h"
29 #include "ar5210/ar5210desc.h"
32 * Set the properties of the tx queue with the parameters
33 * from qInfo. The queue must previously have been setup
34 * with a call to ar5210SetupTxQueue.
37 ar5210SetTxQueueProps(struct ath_hal *ah, int q, const HAL_TXQ_INFO *qInfo)
39 struct ath_hal_5210 *ahp = AH5210(ah);
41 if (q >= HAL_NUM_TX_QUEUES) {
42 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
46 return ath_hal_setTxQProps(ah, &ahp->ah_txq[q], qInfo);
50 * Return the properties for the specified tx queue.
53 ar5210GetTxQueueProps(struct ath_hal *ah, int q, HAL_TXQ_INFO *qInfo)
55 struct ath_hal_5210 *ahp = AH5210(ah);
57 if (q >= HAL_NUM_TX_QUEUES) {
58 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
62 return ath_hal_getTxQProps(ah, qInfo, &ahp->ah_txq[q]);
66 * Allocate and initialize a tx DCU/QCU combination.
69 ar5210SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,
70 const HAL_TXQ_INFO *qInfo)
72 struct ath_hal_5210 *ahp = AH5210(ah);
73 HAL_TX_QUEUE_INFO *qi;
77 case HAL_TX_QUEUE_BEACON:
80 case HAL_TX_QUEUE_CAB:
83 case HAL_TX_QUEUE_DATA:
87 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad tx queue type %u\n",
92 HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);
95 if (qi->tqi_type != HAL_TX_QUEUE_INACTIVE) {
96 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: tx queue %u already active\n",
100 OS_MEMZERO(qi, sizeof(HAL_TX_QUEUE_INFO));
102 if (qInfo == AH_NULL) {
103 /* by default enable OK+ERR+DESC+URN interrupts */
105 HAL_TXQ_TXOKINT_ENABLE
106 | HAL_TXQ_TXERRINT_ENABLE
107 | HAL_TXQ_TXDESCINT_ENABLE
108 | HAL_TXQ_TXURNINT_ENABLE
110 qi->tqi_aifs = INIT_AIFS;
111 qi->tqi_cwmin = HAL_TXQ_USEDEFAULT; /* NB: do at reset */
112 qi->tqi_shretry = INIT_SH_RETRY;
113 qi->tqi_lgretry = INIT_LG_RETRY;
115 (void) ar5210SetTxQueueProps(ah, q, qInfo);
116 /* NB: must be followed by ar5210ResetTxQueue */
121 * Free a tx DCU/QCU combination.
124 ar5210ReleaseTxQueue(struct ath_hal *ah, u_int q)
126 struct ath_hal_5210 *ahp = AH5210(ah);
127 HAL_TX_QUEUE_INFO *qi;
129 if (q >= HAL_NUM_TX_QUEUES) {
130 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
134 qi = &ahp->ah_txq[q];
135 if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
136 HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: inactive queue %u\n",
141 HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: release queue %u\n", __func__, q);
143 qi->tqi_type = HAL_TX_QUEUE_INACTIVE;
144 ahp->ah_txOkInterruptMask &= ~(1 << q);
145 ahp->ah_txErrInterruptMask &= ~(1 << q);
146 ahp->ah_txDescInterruptMask &= ~(1 << q);
147 ahp->ah_txEolInterruptMask &= ~(1 << q);
148 ahp->ah_txUrnInterruptMask &= ~(1 << q);
155 ar5210ResetTxQueue(struct ath_hal *ah, u_int q)
157 struct ath_hal_5210 *ahp = AH5210(ah);
158 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
159 HAL_TX_QUEUE_INFO *qi;
162 if (q >= HAL_NUM_TX_QUEUES) {
163 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
167 qi = &ahp->ah_txq[q];
168 if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
169 HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: inactive queue %u\n",
175 * Ignore any non-data queue(s).
177 if (qi->tqi_type != HAL_TX_QUEUE_DATA)
180 /* Set turbo mode / base mode parameters on or off */
181 if (IEEE80211_IS_CHAN_TURBO(chan)) {
182 OS_REG_WRITE(ah, AR_SLOT_TIME, INIT_SLOT_TIME_TURBO);
183 OS_REG_WRITE(ah, AR_TIME_OUT, INIT_ACK_CTS_TIMEOUT_TURBO);
184 OS_REG_WRITE(ah, AR_USEC, INIT_TRANSMIT_LATENCY_TURBO);
185 OS_REG_WRITE(ah, AR_IFS0,
186 ((INIT_SIFS_TURBO + qi->tqi_aifs * INIT_SLOT_TIME_TURBO)
189 OS_REG_WRITE(ah, AR_IFS1, INIT_PROTO_TIME_CNTRL_TURBO);
190 OS_REG_WRITE(ah, AR_PHY(17),
191 (OS_REG_READ(ah, AR_PHY(17)) & ~0x7F) | 0x38);
192 OS_REG_WRITE(ah, AR_PHY_FRCTL,
193 AR_PHY_SERVICE_ERR | AR_PHY_TXURN_ERR |
194 AR_PHY_ILLLEN_ERR | AR_PHY_ILLRATE_ERR |
195 AR_PHY_PARITY_ERR | AR_PHY_TIMING_ERR |
197 AR_PHY_TURBO_MODE | AR_PHY_TURBO_SHORT);
199 OS_REG_WRITE(ah, AR_SLOT_TIME, INIT_SLOT_TIME);
200 OS_REG_WRITE(ah, AR_TIME_OUT, INIT_ACK_CTS_TIMEOUT);
201 OS_REG_WRITE(ah, AR_USEC, INIT_TRANSMIT_LATENCY);
202 OS_REG_WRITE(ah, AR_IFS0,
203 ((INIT_SIFS + qi->tqi_aifs * INIT_SLOT_TIME)
206 OS_REG_WRITE(ah, AR_IFS1, INIT_PROTO_TIME_CNTRL);
207 OS_REG_WRITE(ah, AR_PHY(17),
208 (OS_REG_READ(ah, AR_PHY(17)) & ~0x7F) | 0x1C);
209 OS_REG_WRITE(ah, AR_PHY_FRCTL,
210 AR_PHY_SERVICE_ERR | AR_PHY_TXURN_ERR |
211 AR_PHY_ILLLEN_ERR | AR_PHY_ILLRATE_ERR |
212 AR_PHY_PARITY_ERR | AR_PHY_TIMING_ERR | 0x1020);
215 if (qi->tqi_cwmin == HAL_TXQ_USEDEFAULT)
218 cwMin = qi->tqi_cwmin;
220 /* Set cwmin and retry limit values */
221 OS_REG_WRITE(ah, AR_RETRY_LMT,
222 (cwMin << AR_RETRY_LMT_CW_MIN_S)
223 | SM(INIT_SLG_RETRY, AR_RETRY_LMT_SLG_RETRY)
224 | SM(INIT_SSH_RETRY, AR_RETRY_LMT_SSH_RETRY)
225 | SM(qi->tqi_lgretry, AR_RETRY_LMT_LG_RETRY)
226 | SM(qi->tqi_shretry, AR_RETRY_LMT_SH_RETRY)
229 if (qi->tqi_qflags & HAL_TXQ_TXOKINT_ENABLE)
230 ahp->ah_txOkInterruptMask |= 1 << q;
232 ahp->ah_txOkInterruptMask &= ~(1 << q);
233 if (qi->tqi_qflags & HAL_TXQ_TXERRINT_ENABLE)
234 ahp->ah_txErrInterruptMask |= 1 << q;
236 ahp->ah_txErrInterruptMask &= ~(1 << q);
237 if (qi->tqi_qflags & HAL_TXQ_TXDESCINT_ENABLE)
238 ahp->ah_txDescInterruptMask |= 1 << q;
240 ahp->ah_txDescInterruptMask &= ~(1 << q);
241 if (qi->tqi_qflags & HAL_TXQ_TXEOLINT_ENABLE)
242 ahp->ah_txEolInterruptMask |= 1 << q;
244 ahp->ah_txEolInterruptMask &= ~(1 << q);
245 if (qi->tqi_qflags & HAL_TXQ_TXURNINT_ENABLE)
246 ahp->ah_txUrnInterruptMask |= 1 << q;
248 ahp->ah_txUrnInterruptMask &= ~(1 << q);
254 * Get the TXDP for the "main" data queue. Needs to be extended
255 * for multiple Q functionality
258 ar5210GetTxDP(struct ath_hal *ah, u_int q)
260 struct ath_hal_5210 *ahp = AH5210(ah);
261 HAL_TX_QUEUE_INFO *qi;
263 HALASSERT(q < HAL_NUM_TX_QUEUES);
265 qi = &ahp->ah_txq[q];
266 switch (qi->tqi_type) {
267 case HAL_TX_QUEUE_DATA:
268 return OS_REG_READ(ah, AR_TXDP0);
269 case HAL_TX_QUEUE_INACTIVE:
270 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: inactive queue %u\n",
280 * Set the TxDP for the "main" data queue.
283 ar5210SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp)
285 struct ath_hal_5210 *ahp = AH5210(ah);
286 HAL_TX_QUEUE_INFO *qi;
288 HALASSERT(q < HAL_NUM_TX_QUEUES);
290 HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u 0x%x\n",
292 qi = &ahp->ah_txq[q];
293 switch (qi->tqi_type) {
294 case HAL_TX_QUEUE_DATA:
297 * Make sure that TXE is deasserted before setting the
298 * TXDP. If TXE is still asserted, setting TXDP will
301 if (OS_REG_READ(ah, AR_CR) & AR_CR_TXE0)
302 ath_hal_printf(ah, "%s: TXE asserted; AR_CR=0x%x\n",
303 __func__, OS_REG_READ(ah, AR_CR));
305 OS_REG_WRITE(ah, AR_TXDP0, txdp);
307 case HAL_TX_QUEUE_BEACON:
308 case HAL_TX_QUEUE_CAB:
309 OS_REG_WRITE(ah, AR_TXDP1, txdp);
311 case HAL_TX_QUEUE_INACTIVE:
312 HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: inactive queue %u\n",
322 * Update Tx FIFO trigger level.
324 * Set bIncTrigLevel to TRUE to increase the trigger level.
325 * Set bIncTrigLevel to FALSE to decrease the trigger level.
327 * Returns TRUE if the trigger level was updated
330 ar5210UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel)
332 uint32_t curTrigLevel;
333 HAL_INT ints = ar5210GetInterrupts(ah);
336 * Disable chip interrupts. This is because halUpdateTxTrigLevel
337 * is called from both ISR and non-ISR contexts.
339 (void) ar5210SetInterrupts(ah, ints &~ HAL_INT_GLOBAL);
340 curTrigLevel = OS_REG_READ(ah, AR_TRIG_LEV);
342 /* increase the trigger level */
343 curTrigLevel = curTrigLevel +
344 ((MAX_TX_FIFO_THRESHOLD - curTrigLevel) / 2);
346 /* decrease the trigger level if not already at the minimum */
347 if (curTrigLevel > MIN_TX_FIFO_THRESHOLD) {
348 /* decrease the trigger level */
351 /* no update to the trigger level */
352 /* re-enable chip interrupts */
353 ar5210SetInterrupts(ah, ints);
357 /* Update the trigger level */
358 OS_REG_WRITE(ah, AR_TRIG_LEV, curTrigLevel);
359 /* re-enable chip interrupts */
360 ar5210SetInterrupts(ah, ints);
365 * Set Transmit Enable bits for the specified queues.
368 ar5210StartTxDma(struct ath_hal *ah, u_int q)
370 struct ath_hal_5210 *ahp = AH5210(ah);
371 HAL_TX_QUEUE_INFO *qi;
373 HALASSERT(q < HAL_NUM_TX_QUEUES);
375 HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);
376 qi = &ahp->ah_txq[q];
377 switch (qi->tqi_type) {
378 case HAL_TX_QUEUE_DATA:
379 OS_REG_WRITE(ah, AR_CR, AR_CR_TXE0);
381 case HAL_TX_QUEUE_CAB:
382 OS_REG_WRITE(ah, AR_CR, AR_CR_TXE1); /* enable altq xmit */
383 OS_REG_WRITE(ah, AR_BCR,
384 AR_BCR_TQ1V | AR_BCR_BDMAE | AR_BCR_TQ1FV);
386 case HAL_TX_QUEUE_BEACON:
387 /* XXX add CR_BCR_BCMD if IBSS mode */
388 OS_REG_WRITE(ah, AR_BCR, AR_BCR_TQ1V | AR_BCR_BDMAE);
390 case HAL_TX_QUEUE_INACTIVE:
391 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: inactive queue %u\n",
401 ar5210NumTxPending(struct ath_hal *ah, u_int q)
403 struct ath_hal_5210 *ahp = AH5210(ah);
404 HAL_TX_QUEUE_INFO *qi;
407 HALASSERT(q < HAL_NUM_TX_QUEUES);
409 HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);
410 qi = &ahp->ah_txq[q];
411 switch (qi->tqi_type) {
412 case HAL_TX_QUEUE_DATA:
413 v = OS_REG_READ(ah, AR_CFG);
414 return MS(v, AR_CFG_TXCNT);
415 case HAL_TX_QUEUE_INACTIVE:
416 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: inactive queue %u\n",
426 * Stop transmit on the specified queue
429 ar5210StopTxDma(struct ath_hal *ah, u_int q)
431 struct ath_hal_5210 *ahp = AH5210(ah);
432 HAL_TX_QUEUE_INFO *qi;
434 HALASSERT(q < HAL_NUM_TX_QUEUES);
436 HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);
437 qi = &ahp->ah_txq[q];
438 switch (qi->tqi_type) {
439 case HAL_TX_QUEUE_DATA: {
441 OS_REG_WRITE(ah, AR_CR, AR_CR_TXD0);
442 for (i = 0; i < 1000; i++) {
443 if ((OS_REG_READ(ah, AR_CFG) & AR_CFG_TXCNT) == 0)
447 OS_REG_WRITE(ah, AR_CR, 0);
450 case HAL_TX_QUEUE_BEACON:
451 return ath_hal_wait(ah, AR_BSR, AR_BSR_TXQ1F, 0);
452 case HAL_TX_QUEUE_INACTIVE:
453 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: inactive queue %u\n",
463 * Descriptor Access Functions
466 #define VALID_PKT_TYPES \
467 ((1<<HAL_PKT_TYPE_NORMAL)|(1<<HAL_PKT_TYPE_ATIM)|\
468 (1<<HAL_PKT_TYPE_PSPOLL)|(1<<HAL_PKT_TYPE_PROBE_RESP)|\
469 (1<<HAL_PKT_TYPE_BEACON))
470 #define isValidPktType(_t) ((1<<(_t)) & VALID_PKT_TYPES)
471 #define VALID_TX_RATES \
472 ((1<<0x0b)|(1<<0x0f)|(1<<0x0a)|(1<<0x0e)|(1<<0x09)|(1<<0x0d)|\
473 (1<<0x08)|(1<<0x0c)|(1<<0x1b)|(1<<0x1a)|(1<<0x1e)|(1<<0x19)|\
474 (1<<0x1d)|(1<<0x18)|(1<<0x1c))
475 #define isValidTxRate(_r) ((1<<(_r)) & VALID_TX_RATES)
478 ar5210SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,
483 u_int txRate0, u_int txTries0,
488 u_int rtsctsDuration,
493 struct ar5210_desc *ads = AR5210DESC(ds);
497 (void) rtsctsDuration;
499 HALASSERT(txTries0 != 0);
500 HALASSERT(isValidPktType(type));
501 HALASSERT(isValidTxRate(txRate0));
503 if (type == HAL_PKT_TYPE_BEACON || type == HAL_PKT_TYPE_PROBE_RESP)
504 frtype = AR_Frm_NoDelay;
507 ads->ds_ctl0 = (pktLen & AR_FrameLen)
508 | (txRate0 << AR_XmitRate_S)
509 | ((hdrLen << AR_HdrLen_S) & AR_HdrLen)
511 | (flags & HAL_TXDESC_CLRDMASK ? AR_ClearDestMask : 0)
512 | (flags & HAL_TXDESC_INTREQ ? AR_TxInterReq : 0)
513 | (antMode ? AR_AntModeXmit : 0)
515 if (keyIx != HAL_TXKEYIX_INVALID) {
516 ads->ds_ctl1 = (keyIx << AR_EncryptKeyIdx_S) & AR_EncryptKeyIdx;
517 ads->ds_ctl0 |= AR_EncryptKeyValid;
520 if (flags & HAL_TXDESC_RTSENA) {
521 ads->ds_ctl0 |= AR_RTSCTSEnable;
522 ads->ds_ctl1 |= rtsctsDuration & AR_RTSDuration;
528 ar5210SetupXTxDesc(struct ath_hal *ah, struct ath_desc *ds,
529 u_int txRate1, u_int txTries1,
530 u_int txRate2, u_int txTries2,
531 u_int txRate3, u_int txTries3)
533 (void) ah; (void) ds;
534 (void) txRate1; (void) txTries1;
535 (void) txRate2; (void) txTries2;
536 (void) txRate3; (void) txTries3;
541 ar5210IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *ds)
543 struct ar5210_desc *ads = AR5210DESC(ds);
545 ads->ds_ctl0 |= AR_TxInterReq;
549 ar5210FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,
550 u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
551 const struct ath_desc *ds0)
553 struct ar5210_desc *ads = AR5210DESC(ds);
555 HALASSERT((segLen &~ AR_BufLen) == 0);
559 * First descriptor, don't clobber xmit control data
560 * setup by ar5210SetupTxDesc.
562 ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_More);
563 } else if (lastSeg) { /* !firstSeg && lastSeg */
565 * Last descriptor in a multi-descriptor frame,
566 * copy the transmit parameters from the first
567 * frame for processing on completion.
569 ads->ds_ctl0 = AR5210DESC_CONST(ds0)->ds_ctl0;
570 ads->ds_ctl1 = segLen;
571 } else { /* !firstSeg && !lastSeg */
573 * Intermediate descriptor in a multi-descriptor frame.
576 ads->ds_ctl1 = segLen | AR_More;
578 ads->ds_status0 = ads->ds_status1 = 0;
583 * Processing of HW TX descriptor.
586 ar5210ProcTxDesc(struct ath_hal *ah,
587 struct ath_desc *ds, struct ath_tx_status *ts)
589 struct ar5210_desc *ads = AR5210DESC(ds);
591 if ((ads->ds_status1 & AR_Done) == 0)
592 return HAL_EINPROGRESS;
594 /* Update software copies of the HW status */
595 ts->ts_seqnum = ads->ds_status1 & AR_SeqNum;
596 ts->ts_tstamp = MS(ads->ds_status0, AR_SendTimestamp);
598 if ((ads->ds_status0 & AR_FrmXmitOK) == 0) {
599 if (ads->ds_status0 & AR_ExcessiveRetries)
600 ts->ts_status |= HAL_TXERR_XRETRY;
601 if (ads->ds_status0 & AR_Filtered)
602 ts->ts_status |= HAL_TXERR_FILT;
603 if (ads->ds_status0 & AR_FIFOUnderrun)
604 ts->ts_status |= HAL_TXERR_FIFO;
606 ts->ts_rate = MS(ads->ds_ctl0, AR_XmitRate);
607 ts->ts_rssi = MS(ads->ds_status1, AR_AckSigStrength);
608 ts->ts_shortretry = MS(ads->ds_status0, AR_ShortRetryCnt);
609 ts->ts_longretry = MS(ads->ds_status0, AR_LongRetryCnt);
610 ts->ts_antenna = 0; /* NB: don't know */
617 * Determine which tx queues need interrupt servicing.
621 ar5210GetTxIntrQueue(struct ath_hal *ah, uint32_t *txqs)