sys/dev/drm/i915/i915_gpu_error.c

   1 /*
   2  * Copyright (c) 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *    Mika Kuoppala <mika.kuoppala@intel.com>
  27  *
  28  */
  29
  30 #include "i915_drv.h"
  31
  32 static const char *ring_str(int ring)
  33 {
  34         switch (ring) {
  35         case RCS: return "render";
  36         case VCS: return "bsd";
  37         case BCS: return "blt";
  38         case VECS: return "vebox";
  39         case VCS2: return "bsd2";
  40         default: return "";
  41         }
  42 }
  43
  44 static const char *pin_flag(int pinned)
  45 {
  46         if (pinned > 0)
  47                 return " P";
  48         else if (pinned < 0)
  49                 return " p";
  50         else
  51                 return "";
  52 }
  53
  54 static const char *tiling_flag(int tiling)
  55 {
  56         switch (tiling) {
  57         default:
  58         case I915_TILING_NONE: return "";
  59         case I915_TILING_X: return " X";
  60         case I915_TILING_Y: return " Y";
  61         }
  62 }
  63
  64 static const char *dirty_flag(int dirty)
  65 {
  66         return dirty ? " dirty" : "";
  67 }
  68
  69 static const char *purgeable_flag(int purgeable)
  70 {
  71         return purgeable ? " purgeable" : "";
  72 }
  73
  74 static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
  75 {
  76
  77         if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
  78                 e->err = -ENOSPC;
  79                 return false;
  80         }
  81
  82         if (e->bytes == e->size - 1 || e->err)
  83                 return false;
  84
  85         return true;
  86 }
  87
  88 static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
  89                               unsigned len)
  90 {
  91         if (e->pos + len <= e->start) {
  92                 e->pos += len;
  93                 return false;
  94         }
  95
  96         /* First vsnprintf needs to fit in its entirety for memmove */
  97         if (len >= e->size) {
  98                 e->err = -EIO;
  99                 return false;
 100         }
 101
 102         return true;
 103 }
 104
 105 static void __i915_error_advance(struct drm_i915_error_state_buf *e,
 106                                  unsigned len)
 107 {
 108         /* If this is first printf in this window, adjust it so that
 109          * start position matches start of the buffer
 110          */
 111
 112         if (e->pos < e->start) {
 113                 const size_t off = e->start - e->pos;
 114
 115                 /* Should not happen but be paranoid */
 116                 if (off > len || e->bytes) {
 117                         e->err = -EIO;
 118                         return;
 119                 }
 120
 121                 memmove(e->buf, e->buf + off, len - off);
 122                 e->bytes = len - off;
 123                 e->pos = e->start;
 124                 return;
 125         }
 126
 127         e->bytes += len;
 128         e->pos += len;
 129 }
 130
 131 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
 132                                const char *f, va_list args)
 133 {
 134         unsigned len;
 135
 136         if (!__i915_error_ok(e))
 137                 return;
 138
 139         /* Seek the first printf which is hits start position */
 140         if (e->pos < e->start) {
 141                 va_list tmp;
 142
 143                 va_copy(tmp, args);
 144                 len = vsnprintf(NULL, 0, f, tmp);
 145                 va_end(tmp);
 146
 147                 if (!__i915_error_seek(e, len))
 148                         return;
 149         }
 150
 151         len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
 152         if (len >= e->size - e->bytes)
 153                 len = e->size - e->bytes - 1;
 154
 155         __i915_error_advance(e, len);
 156 }
 157
 158 static void i915_error_puts(struct drm_i915_error_state_buf *e,
 159                             const char *str)
 160 {
 161         unsigned len;
 162
 163         if (!__i915_error_ok(e))
 164                 return;
 165
 166         len = strlen(str);
 167
 168         /* Seek the first printf which is hits start position */
 169         if (e->pos < e->start) {
 170                 if (!__i915_error_seek(e, len))
 171                         return;
 172         }
 173
 174         if (len >= e->size - e->bytes)
 175                 len = e->size - e->bytes - 1;
 176         memcpy(e->buf + e->bytes, str, len);
 177
 178         __i915_error_advance(e, len);
 179 }
 180
 181 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
 182 #define err_puts(e, s) i915_error_puts(e, s)
 183
 184 static void print_error_buffers(struct drm_i915_error_state_buf *m,
 185                                 const char *name,
 186                                 struct drm_i915_error_buffer *err,
 187                                 int count)
 188 {
 189         int i;
 190
 191         err_printf(m, "  %s [%d]:\n", name, count);
 192
 193         while (count--) {
 194                 err_printf(m, "    %08x_%08x %8u %02x %02x [ ",
 195                            upper_32_bits(err->gtt_offset),
 196                            lower_32_bits(err->gtt_offset),
 197                            err->size,
 198                            err->read_domains,
 199                            err->write_domain);
 200                 for (i = 0; i < I915_NUM_ENGINES; i++)
 201                         err_printf(m, "%02x ", err->rseqno[i]);
 202
 203                 err_printf(m, "] %02x", err->wseqno);
 204                 err_puts(m, pin_flag(err->pinned));
 205                 err_puts(m, tiling_flag(err->tiling));
 206                 err_puts(m, dirty_flag(err->dirty));
 207                 err_puts(m, purgeable_flag(err->purgeable));
 208                 err_puts(m, err->userptr ? " userptr" : "");
 209                 err_puts(m, err->ring != -1 ? " " : "");
 210                 err_puts(m, ring_str(err->ring));
 211                 err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
 212
 213                 if (err->name)
 214                         err_printf(m, " (name: %d)", err->name);
 215                 if (err->fence_reg != I915_FENCE_REG_NONE)
 216                         err_printf(m, " (fence: %d)", err->fence_reg);
 217
 218                 err_puts(m, "\n");
 219                 err++;
 220         }
 221 }
 222
 223 static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
 224 {
 225         switch (a) {
 226         case HANGCHECK_IDLE:
 227                 return "idle";
 228         case HANGCHECK_WAIT:
 229                 return "wait";
 230         case HANGCHECK_ACTIVE:
 231                 return "active";
 232         case HANGCHECK_KICK:
 233                 return "kick";
 234         case HANGCHECK_HUNG:
 235                 return "hung";
 236         }
 237
 238         return "unknown";
 239 }
 240
 241 static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
 242                                   struct drm_device *dev,
 243                                   struct drm_i915_error_state *error,
 244                                   int ring_idx)
 245 {
 246         struct drm_i915_error_ring *ring = &error->ring[ring_idx];
 247
 248         if (!ring->valid)
 249                 return;
 250
 251         err_printf(m, "%s command stream:\n", ring_str(ring_idx));
 252         err_printf(m, "  START: 0x%08x\n", ring->start);
 253         err_printf(m, "  HEAD:  0x%08x\n", ring->head);
 254         err_printf(m, "  TAIL:  0x%08x\n", ring->tail);
 255         err_printf(m, "  CTL:   0x%08x\n", ring->ctl);
 256         err_printf(m, "  HWS:   0x%08x\n", ring->hws);
 257         err_printf(m, "  ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd);
 258         err_printf(m, "  IPEIR: 0x%08x\n", ring->ipeir);
 259         err_printf(m, "  IPEHR: 0x%08x\n", ring->ipehr);
 260         err_printf(m, "  INSTDONE: 0x%08x\n", ring->instdone);
 261         if (INTEL_INFO(dev)->gen >= 4) {
 262                 err_printf(m, "  BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr);
 263                 err_printf(m, "  BB_STATE: 0x%08x\n", ring->bbstate);
 264                 err_printf(m, "  INSTPS: 0x%08x\n", ring->instps);
 265         }
 266         err_printf(m, "  INSTPM: 0x%08x\n", ring->instpm);
 267         err_printf(m, "  FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr),
 268                    lower_32_bits(ring->faddr));
 269         if (INTEL_INFO(dev)->gen >= 6) {
 270                 err_printf(m, "  RC PSMI: 0x%08x\n", ring->rc_psmi);
 271                 err_printf(m, "  FAULT_REG: 0x%08x\n", ring->fault_reg);
 272                 err_printf(m, "  SYNC_0: 0x%08x [last synced 0x%08x]\n",
 273                            ring->semaphore_mboxes[0],
 274                            ring->semaphore_seqno[0]);
 275                 err_printf(m, "  SYNC_1: 0x%08x [last synced 0x%08x]\n",
 276                            ring->semaphore_mboxes[1],
 277                            ring->semaphore_seqno[1]);
 278                 if (HAS_VEBOX(dev)) {
 279                         err_printf(m, "  SYNC_2: 0x%08x [last synced 0x%08x]\n",
 280                                    ring->semaphore_mboxes[2],
 281                                    ring->semaphore_seqno[2]);
 282                 }
 283         }
 284         if (USES_PPGTT(dev)) {
 285                 err_printf(m, "  GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode);
 286
 287                 if (INTEL_INFO(dev)->gen >= 8) {
 288                         int i;
 289                         for (i = 0; i < 4; i++)
 290                                 err_printf(m, "  PDP%d: 0x%016llx\n",
 291                                            i, ring->vm_info.pdp[i]);
 292                 } else {
 293                         err_printf(m, "  PP_DIR_BASE: 0x%08x\n",
 294                                    ring->vm_info.pp_dir_base);
 295                 }
 296         }
 297         err_printf(m, "  seqno: 0x%08x\n", ring->seqno);
 298         err_printf(m, "  last_seqno: 0x%08x\n", ring->last_seqno);
 299         err_printf(m, "  waiting: %s\n", yesno(ring->waiting));
 300         err_printf(m, "  ring->head: 0x%08x\n", ring->cpu_ring_head);
 301         err_printf(m, "  ring->tail: 0x%08x\n", ring->cpu_ring_tail);
 302         err_printf(m, "  hangcheck: %s [%d]\n",
 303                    hangcheck_action_to_str(ring->hangcheck_action),
 304                    ring->hangcheck_score);
 305 }
 306
 307 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
 308 {
 309         va_list args;
 310
 311         va_start(args, f);
 312         i915_error_vprintf(e, f, args);
 313         va_end(args);
 314 }
 315
 316 static void print_error_obj(struct drm_i915_error_state_buf *m,
 317                             struct drm_i915_error_object *obj)
 318 {
 319         int page, offset, elt;
 320
 321         for (page = offset = 0; page < obj->page_count; page++) {
 322                 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
 323                         err_printf(m, "%08x :  %08x\n", offset,
 324                                    obj->pages[page][elt]);
 325                         offset += 4;
 326                 }
 327         }
 328 }
 329
 330 int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
 331                             const struct i915_error_state_file_priv *error_priv)
 332 {
 333         struct drm_device *dev = error_priv->dev;
 334         struct drm_i915_private *dev_priv = dev->dev_private;
 335         struct drm_i915_error_state *error = error_priv->error;
 336         struct drm_i915_error_object *obj;
 337         int i, j, offset, elt;
 338         int max_hangcheck_score;
 339
 340         if (!error) {
 341                 err_printf(m, "no error state collected\n");
 342                 goto out;
 343         }
 344
 345         err_printf(m, "%s\n", error->error_msg);
 346         err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
 347                    error->time.tv_usec);
 348         err_printf(m, "Kernel:  UTS_RELEASE \n");
 349         max_hangcheck_score = 0;
 350         for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
 351                 if (error->ring[i].hangcheck_score > max_hangcheck_score)
 352                         max_hangcheck_score = error->ring[i].hangcheck_score;
 353         }
 354         for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
 355                 if (error->ring[i].hangcheck_score == max_hangcheck_score &&
 356                     error->ring[i].pid != -1) {
 357                         err_printf(m, "Active process (on ring %s): %s [%d]\n",
 358                                    ring_str(i),
 359                                    error->ring[i].comm,
 360                                    error->ring[i].pid);
 361                 }
 362         }
 363         err_printf(m, "Reset count: %u\n", error->reset_count);
 364         err_printf(m, "Suspend count: %u\n", error->suspend_count);
 365         err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
 366         err_printf(m, "PCI Revision: 0x%02x\n", dev->pdev->revision);
 367         err_printf(m, "PCI Subsystem: %04x:%04x\n",
 368                    dev->pdev->subsystem_vendor,
 369                    dev->pdev->subsystem_device);
 370         err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
 371
 372         if (HAS_CSR(dev)) {
 373                 struct intel_csr *csr = &dev_priv->csr;
 374
 375                 err_printf(m, "DMC loaded: %s\n",
 376                            yesno(csr->dmc_payload != NULL));
 377                 err_printf(m, "DMC fw version: %d.%d\n",
 378                            CSR_VERSION_MAJOR(csr->version),
 379                            CSR_VERSION_MINOR(csr->version));
 380         }
 381
 382         err_printf(m, "EIR: 0x%08x\n", error->eir);
 383         err_printf(m, "IER: 0x%08x\n", error->ier);
 384         if (INTEL_INFO(dev)->gen >= 8) {
 385                 for (i = 0; i < 4; i++)
 386                         err_printf(m, "GTIER gt %d: 0x%08x\n", i,
 387                                    error->gtier[i]);
 388         } else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
 389                 err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]);
 390         err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
 391         err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
 392         err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
 393         err_printf(m, "CCID: 0x%08x\n", error->ccid);
 394         err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
 395
 396         for (i = 0; i < dev_priv->num_fence_regs; i++)
 397                 err_printf(m, "  fence[%d] = %08llx\n", i, error->fence[i]);
 398
 399         for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
 400                 err_printf(m, "  INSTDONE_%d: 0x%08x\n", i,
 401                            error->extra_instdone[i]);
 402
 403         if (INTEL_INFO(dev)->gen >= 6) {
 404                 err_printf(m, "ERROR: 0x%08x\n", error->error);
 405
 406                 if (INTEL_INFO(dev)->gen >= 8)
 407                         err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
 408                                    error->fault_data1, error->fault_data0);
 409
 410                 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
 411         }
 412
 413         if (INTEL_INFO(dev)->gen == 7)
 414                 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
 415
 416         for (i = 0; i < ARRAY_SIZE(error->ring); i++)
 417                 i915_ring_error_state(m, dev, error, i);
 418
 419         for (i = 0; i < error->vm_count; i++) {
 420                 err_printf(m, "vm[%d]\n", i);
 421
 422                 print_error_buffers(m, "Active",
 423                                     error->active_bo[i],
 424                                     error->active_bo_count[i]);
 425
 426                 print_error_buffers(m, "Pinned",
 427                                     error->pinned_bo[i],
 428                                     error->pinned_bo_count[i]);
 429         }
 430
 431         for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
 432                 obj = error->ring[i].batchbuffer;
 433                 if (obj) {
 434                         err_puts(m, dev_priv->engine[i].name);
 435                         if (error->ring[i].pid != -1)
 436                                 err_printf(m, " (submitted by %s [%d])",
 437                                            error->ring[i].comm,
 438                                            error->ring[i].pid);
 439                         err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
 440                                    upper_32_bits(obj->gtt_offset),
 441                                    lower_32_bits(obj->gtt_offset));
 442                         print_error_obj(m, obj);
 443                 }
 444
 445                 obj = error->ring[i].wa_batchbuffer;
 446                 if (obj) {
 447                         err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
 448                                    dev_priv->engine[i].name,
 449                                    lower_32_bits(obj->gtt_offset));
 450                         print_error_obj(m, obj);
 451                 }
 452
 453                 if (error->ring[i].num_requests) {
 454                         err_printf(m, "%s --- %d requests\n",
 455                                    dev_priv->engine[i].name,
 456                                    error->ring[i].num_requests);
 457                         for (j = 0; j < error->ring[i].num_requests; j++) {
 458                                 err_printf(m, "  seqno 0x%08x, emitted %ld, tail 0x%08x\n",
 459                                            error->ring[i].requests[j].seqno,
 460                                            error->ring[i].requests[j].jiffies,
 461                                            error->ring[i].requests[j].tail);
 462                         }
 463                 }
 464
 465                 if ((obj = error->ring[i].ringbuffer)) {
 466                         err_printf(m, "%s --- ringbuffer = 0x%08x\n",
 467                                    dev_priv->engine[i].name,
 468                                    lower_32_bits(obj->gtt_offset));
 469                         print_error_obj(m, obj);
 470                 }
 471
 472                 if ((obj = error->ring[i].hws_page)) {
 473                         u64 hws_offset = obj->gtt_offset;
 474                         u32 *hws_page = &obj->pages[0][0];
 475
 476                         if (i915.enable_execlists) {
 477                                 hws_offset += LRC_PPHWSP_PN * PAGE_SIZE;
 478                                 hws_page = &obj->pages[LRC_PPHWSP_PN][0];
 479                         }
 480                         err_printf(m, "%s --- HW Status = 0x%08llx\n",
 481                                    dev_priv->engine[i].name, hws_offset);
 482                         offset = 0;
 483                         for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
 484                                 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
 485                                            offset,
 486                                            hws_page[elt],
 487                                            hws_page[elt+1],
 488                                            hws_page[elt+2],
 489                                            hws_page[elt+3]);
 490                                         offset += 16;
 491                         }
 492                 }
 493
 494                 obj = error->ring[i].wa_ctx;
 495                 if (obj) {
 496                         u64 wa_ctx_offset = obj->gtt_offset;
 497                         u32 *wa_ctx_page = &obj->pages[0][0];
 498                         struct intel_engine_cs *engine = &dev_priv->engine[RCS];
 499                         u32 wa_ctx_size = (engine->wa_ctx.indirect_ctx.size +
 500                                            engine->wa_ctx.per_ctx.size);
 501
 502                         err_printf(m, "%s --- WA ctx batch buffer = 0x%08llx\n",
 503                                    dev_priv->engine[i].name, wa_ctx_offset);
 504                         offset = 0;
 505                         for (elt = 0; elt < wa_ctx_size; elt += 4) {
 506                                 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
 507                                            offset,
 508                                            wa_ctx_page[elt + 0],
 509                                            wa_ctx_page[elt + 1],
 510                                            wa_ctx_page[elt + 2],
 511                                            wa_ctx_page[elt + 3]);
 512                                 offset += 16;
 513                         }
 514                 }
 515
 516                 if ((obj = error->ring[i].ctx)) {
 517                         err_printf(m, "%s --- HW Context = 0x%08x\n",
 518                                    dev_priv->engine[i].name,
 519                                    lower_32_bits(obj->gtt_offset));
 520                         print_error_obj(m, obj);
 521                 }
 522         }
 523
 524         if ((obj = error->semaphore_obj)) {
 525                 err_printf(m, "Semaphore page = 0x%08x\n",
 526                            lower_32_bits(obj->gtt_offset));
 527                 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
 528                         err_printf(m, "[%04x] %08x %08x %08x %08x\n",
 529                                    elt * 4,
 530                                    obj->pages[0][elt],
 531                                    obj->pages[0][elt+1],
 532                                    obj->pages[0][elt+2],
 533                                    obj->pages[0][elt+3]);
 534                 }
 535         }
 536
 537         if (error->overlay)
 538                 intel_overlay_print_error_state(m, error->overlay);
 539
 540         if (error->display)
 541                 intel_display_print_error_state(m, dev, error->display);
 542
 543 out:
 544         if (m->bytes == 0 && m->err)
 545                 return m->err;
 546
 547         return 0;
 548 }
 549
 550 int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
 551                               struct drm_i915_private *i915,
 552                               size_t count, loff_t pos)
 553 {
 554         memset(ebuf, 0, sizeof(*ebuf));
 555         ebuf->i915 = i915;
 556
 557         /* We need to have enough room to store any i915_error_state printf
 558          * so that we can move it to start position.
 559          */
 560         ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
 561         ebuf->buf = kmalloc(ebuf->size, M_DRM, M_WAITOK);
 562
 563         if (ebuf->buf == NULL) {
 564                 ebuf->size = PAGE_SIZE;
 565                 ebuf->buf = kmalloc(ebuf->size, M_DRM, M_WAITOK);
 566         }
 567
 568         if (ebuf->buf == NULL) {
 569                 ebuf->size = 128;
 570                 ebuf->buf = kmalloc(ebuf->size, M_DRM, M_WAITOK);
 571         }
 572
 573         if (ebuf->buf == NULL)
 574                 return -ENOMEM;
 575
 576         ebuf->start = pos;
 577
 578         return 0;
 579 }
 580
 581 static void i915_error_object_free(struct drm_i915_error_object *obj)
 582 {
 583         int page;
 584
 585         if (obj == NULL)
 586                 return;
 587
 588         for (page = 0; page < obj->page_count; page++)
 589                 kfree(obj->pages[page]);
 590
 591         kfree(obj);
 592 }
 593
 594 static void i915_error_state_free(struct kref *error_ref)
 595 {
 596         struct drm_i915_error_state *error = container_of(error_ref,
 597                                                           typeof(*error), ref);
 598         int i;
 599
 600         for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
 601                 i915_error_object_free(error->ring[i].batchbuffer);
 602                 i915_error_object_free(error->ring[i].wa_batchbuffer);
 603                 i915_error_object_free(error->ring[i].ringbuffer);
 604                 i915_error_object_free(error->ring[i].hws_page);
 605                 i915_error_object_free(error->ring[i].ctx);
 606                 kfree(error->ring[i].requests);
 607                 i915_error_object_free(error->ring[i].wa_ctx);
 608         }
 609
 610         i915_error_object_free(error->semaphore_obj);
 611
 612         for (i = 0; i < error->vm_count; i++)
 613                 kfree(error->active_bo[i]);
 614
 615         kfree(error->active_bo);
 616         kfree(error->active_bo_count);
 617         kfree(error->pinned_bo);
 618         kfree(error->pinned_bo_count);
 619         kfree(error->overlay);
 620         kfree(error->display);
 621         kfree(error);
 622 }
 623
 624 static struct drm_i915_error_object *
 625 i915_error_object_create(struct drm_i915_private *dev_priv,
 626                          struct drm_i915_gem_object *src,
 627                          struct i915_address_space *vm)
 628 {
 629         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 630         struct drm_i915_error_object *dst;
 631         struct i915_vma *vma = NULL;
 632         int num_pages;
 633         bool use_ggtt;
 634         int i = 0;
 635         u64 reloc_offset;
 636
 637         if (src == NULL || src->pages == NULL)
 638                 return NULL;
 639
 640         num_pages = src->base.size >> PAGE_SHIFT;
 641
 642         dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), M_DRM, M_NOWAIT);
 643         if (dst == NULL)
 644                 return NULL;
 645
 646         if (i915_gem_obj_bound(src, vm))
 647                 dst->gtt_offset = i915_gem_obj_offset(src, vm);
 648         else
 649                 dst->gtt_offset = -1;
 650
 651         reloc_offset = dst->gtt_offset;
 652         if (i915_is_ggtt(vm))
 653                 vma = i915_gem_obj_to_ggtt(src);
 654         use_ggtt = (src->cache_level == I915_CACHE_NONE &&
 655                    vma && (vma->bound & GLOBAL_BIND) &&
 656                    reloc_offset + num_pages * PAGE_SIZE <= ggtt->mappable_end);
 657
 658         /* Cannot access stolen address directly, try to use the aperture */
 659         if (src->stolen) {
 660                 use_ggtt = true;
 661
 662                 if (!(vma && vma->bound & GLOBAL_BIND))
 663                         goto unwind;
 664
 665                 reloc_offset = i915_gem_obj_ggtt_offset(src);
 666                 if (reloc_offset + num_pages * PAGE_SIZE > ggtt->mappable_end)
 667                         goto unwind;
 668         }
 669
 670         /* Cannot access snooped pages through the aperture */
 671         if (use_ggtt && src->cache_level != I915_CACHE_NONE &&
 672             !HAS_LLC(dev_priv))
 673                 goto unwind;
 674
 675         dst->page_count = num_pages;
 676         while (num_pages--) {
 677 #if 0
 678                 unsigned long flags;
 679 #endif
 680                 void *d;
 681
 682                 d = kmalloc(PAGE_SIZE, M_DRM, M_NOWAIT);
 683                 if (d == NULL)
 684                         goto unwind;
 685
 686 #if 0
 687                 local_irq_save(flags);
 688 #endif
 689                 if (use_ggtt) {
 690                         void __iomem *s;
 691
 692                         /* Simply ignore tiling or any overlapping fence.
 693                          * It's part of the error state, and this hopefully
 694                          * captures what the GPU read.
 695                          */
 696
 697                         s = io_mapping_map_atomic_wc(ggtt->mappable,
 698                                                      reloc_offset);
 699                         memcpy_fromio(d, s, PAGE_SIZE);
 700                         io_mapping_unmap_atomic(s);
 701                 } else {
 702                         struct page *page;
 703                         void *s;
 704
 705                         page = i915_gem_object_get_page(src, i);
 706
 707                         drm_clflush_pages(&page, 1);
 708
 709                         s = kmap_atomic(page);
 710                         memcpy(d, s, PAGE_SIZE);
 711                         kunmap_atomic(s);
 712
 713                         drm_clflush_pages(&page, 1);
 714                 }
 715 #if 0
 716                 local_irq_restore(flags);
 717 #endif
 718
 719                 dst->pages[i++] = d;
 720                 reloc_offset += PAGE_SIZE;
 721         }
 722
 723         return dst;
 724
 725 unwind:
 726         while (i--)
 727                 kfree(dst->pages[i]);
 728         kfree(dst);
 729         return NULL;
 730 }
 731 #define i915_error_ggtt_object_create(dev_priv, src) \
 732         i915_error_object_create((dev_priv), (src), &(dev_priv)->ggtt.base)
 733
 734 static void capture_bo(struct drm_i915_error_buffer *err,
 735                        struct i915_vma *vma)
 736 {
 737         struct drm_i915_gem_object *obj = vma->obj;
 738         int i;
 739
 740         err->size = obj->base.size;
 741         err->name = obj->base.name;
 742         for (i = 0; i < I915_NUM_ENGINES; i++)
 743                 err->rseqno[i] = i915_gem_request_get_seqno(obj->last_read_req[i]);
 744         err->wseqno = i915_gem_request_get_seqno(obj->last_write_req);
 745         err->gtt_offset = vma->node.start;
 746         err->read_domains = obj->base.read_domains;
 747         err->write_domain = obj->base.write_domain;
 748         err->fence_reg = obj->fence_reg;
 749         err->pinned = 0;
 750         if (i915_gem_obj_is_pinned(obj))
 751                 err->pinned = 1;
 752         err->tiling = obj->tiling_mode;
 753         err->dirty = obj->dirty;
 754         err->purgeable = obj->madv != I915_MADV_WILLNEED;
 755         err->userptr = obj->userptr.mm != NULL;
 756         err->ring = obj->last_write_req ?
 757                         i915_gem_request_get_engine(obj->last_write_req)->id : -1;
 758         err->cache_level = obj->cache_level;
 759 }
 760
 761 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
 762                              int count, struct list_head *head)
 763 {
 764         struct i915_vma *vma;
 765         int i = 0;
 766
 767         list_for_each_entry(vma, head, vm_link) {
 768                 capture_bo(err++, vma);
 769                 if (++i == count)
 770                         break;
 771         }
 772
 773         return i;
 774 }
 775
 776 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
 777                              int count, struct list_head *head,
 778                              struct i915_address_space *vm)
 779 {
 780         struct drm_i915_gem_object *obj;
 781         struct drm_i915_error_buffer * const first = err;
 782         struct drm_i915_error_buffer * const last = err + count;
 783
 784         list_for_each_entry(obj, head, global_list) {
 785                 struct i915_vma *vma;
 786
 787                 if (err == last)
 788                         break;
 789
 790                 list_for_each_entry(vma, &obj->vma_list, obj_link)
 791                         if (vma->vm == vm && vma->pin_count > 0)
 792                                 capture_bo(err++, vma);
 793         }
 794
 795         return err - first;
 796 }
 797
 798 /* Generate a semi-unique error code. The code is not meant to have meaning, The
 799  * code's only purpose is to try to prevent false duplicated bug reports by
 800  * grossly estimating a GPU error state.
 801  *
 802  * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
 803  * the hang if we could strip the GTT offset information from it.
 804  *
 805  * It's only a small step better than a random number in its current form.
 806  */
 807 static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
 808                                          struct drm_i915_error_state *error,
 809                                          int *ring_id)
 810 {
 811         uint32_t error_code = 0;
 812         int i;
 813
 814         /* IPEHR would be an ideal way to detect errors, as it's the gross
 815          * measure of "the command that hung." However, has some very common
 816          * synchronization commands which almost always appear in the case
 817          * strictly a client bug. Use instdone to differentiate those some.
 818          */
 819         for (i = 0; i < I915_NUM_ENGINES; i++) {
 820                 if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) {
 821                         if (ring_id)
 822                                 *ring_id = i;
 823
 824                         return error->ring[i].ipehr ^ error->ring[i].instdone;
 825                 }
 826         }
 827
 828         return error_code;
 829 }
 830
 831 static void i915_gem_record_fences(struct drm_device *dev,
 832                                    struct drm_i915_error_state *error)
 833 {
 834         struct drm_i915_private *dev_priv = dev->dev_private;
 835         int i;
 836
 837         if (IS_GEN3(dev) || IS_GEN2(dev)) {
 838                 for (i = 0; i < dev_priv->num_fence_regs; i++)
 839                         error->fence[i] = I915_READ(FENCE_REG(i));
 840         } else if (IS_GEN5(dev) || IS_GEN4(dev)) {
 841                 for (i = 0; i < dev_priv->num_fence_regs; i++)
 842                         error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
 843         } else if (INTEL_INFO(dev)->gen >= 6) {
 844                 for (i = 0; i < dev_priv->num_fence_regs; i++)
 845                         error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
 846         }
 847 }
 848
 849
 850 static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
 851                                         struct drm_i915_error_state *error,
 852                                         struct intel_engine_cs *engine,
 853                                         struct drm_i915_error_ring *ering)
 854 {
 855         struct intel_engine_cs *to;
 856         enum intel_engine_id id;
 857
 858         if (!i915_semaphore_is_enabled(dev_priv->dev))
 859                 return;
 860
 861         if (!error->semaphore_obj)
 862                 error->semaphore_obj =
 863                         i915_error_ggtt_object_create(dev_priv,
 864                                                       dev_priv->semaphore_obj);
 865
 866         for_each_engine_id(to, dev_priv, id) {
 867                 int idx;
 868                 u16 signal_offset;
 869                 u32 *tmp;
 870
 871                 if (engine == to)
 872                         continue;
 873
 874                 signal_offset = (GEN8_SIGNAL_OFFSET(engine, id) & (PAGE_SIZE - 1))
 875                                 / 4;
 876                 tmp = error->semaphore_obj->pages[0];
 877                 idx = intel_ring_sync_index(engine, to);
 878
 879                 ering->semaphore_mboxes[idx] = tmp[signal_offset];
 880                 ering->semaphore_seqno[idx] = engine->semaphore.sync_seqno[idx];
 881         }
 882 }
 883
 884 static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv,
 885                                         struct intel_engine_cs *engine,
 886                                         struct drm_i915_error_ring *ering)
 887 {
 888         ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base));
 889         ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base));
 890         ering->semaphore_seqno[0] = engine->semaphore.sync_seqno[0];
 891         ering->semaphore_seqno[1] = engine->semaphore.sync_seqno[1];
 892
 893         if (HAS_VEBOX(dev_priv)) {
 894                 ering->semaphore_mboxes[2] =
 895                         I915_READ(RING_SYNC_2(engine->mmio_base));
 896                 ering->semaphore_seqno[2] = engine->semaphore.sync_seqno[2];
 897         }
 898 }
 899
 900 static void i915_record_ring_state(struct drm_device *dev,
 901                                    struct drm_i915_error_state *error,
 902                                    struct intel_engine_cs *engine,
 903                                    struct drm_i915_error_ring *ering)
 904 {
 905         struct drm_i915_private *dev_priv = dev->dev_private;
 906
 907         if (INTEL_INFO(dev)->gen >= 6) {
 908                 ering->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
 909                 ering->fault_reg = I915_READ(RING_FAULT_REG(engine));
 910                 if (INTEL_INFO(dev)->gen >= 8)
 911                         gen8_record_semaphore_state(dev_priv, error, engine,
 912                                                     ering);
 913                 else
 914                         gen6_record_semaphore_state(dev_priv, engine, ering);
 915         }
 916
 917         if (INTEL_INFO(dev)->gen >= 4) {
 918                 ering->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
 919                 ering->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
 920                 ering->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
 921                 ering->instdone = I915_READ(RING_INSTDONE(engine->mmio_base));
 922                 ering->instps = I915_READ(RING_INSTPS(engine->mmio_base));
 923                 ering->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
 924                 if (INTEL_INFO(dev)->gen >= 8) {
 925                         ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
 926                         ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
 927                 }
 928                 ering->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base));
 929         } else {
 930                 ering->faddr = I915_READ(DMA_FADD_I8XX);
 931                 ering->ipeir = I915_READ(IPEIR);
 932                 ering->ipehr = I915_READ(IPEHR);
 933                 ering->instdone = I915_READ(GEN2_INSTDONE);
 934         }
 935
 936         ering->waiting = waitqueue_active(&engine->irq_queue);
 937         ering->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
 938         ering->acthd = intel_ring_get_active_head(engine);
 939         ering->seqno = engine->get_seqno(engine);
 940         ering->last_seqno = engine->last_submitted_seqno;
 941         ering->start = I915_READ_START(engine);
 942         ering->head = I915_READ_HEAD(engine);
 943         ering->tail = I915_READ_TAIL(engine);
 944         ering->ctl = I915_READ_CTL(engine);
 945
 946         if (I915_NEED_GFX_HWS(dev)) {
 947                 i915_reg_t mmio;
 948
 949                 if (IS_GEN7(dev)) {
 950                         switch (engine->id) {
 951                         default:
 952                         case RCS:
 953                                 mmio = RENDER_HWS_PGA_GEN7;
 954                                 break;
 955                         case BCS:
 956                                 mmio = BLT_HWS_PGA_GEN7;
 957                                 break;
 958                         case VCS:
 959                                 mmio = BSD_HWS_PGA_GEN7;
 960                                 break;
 961                         case VECS:
 962                                 mmio = VEBOX_HWS_PGA_GEN7;
 963                                 break;
 964                         }
 965                 } else if (IS_GEN6(engine->dev)) {
 966                         mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
 967                 } else {
 968                         /* XXX: gen8 returns to sanity */
 969                         mmio = RING_HWS_PGA(engine->mmio_base);
 970                 }
 971
 972                 ering->hws = I915_READ(mmio);
 973         }
 974
 975         ering->hangcheck_score = engine->hangcheck.score;
 976         ering->hangcheck_action = engine->hangcheck.action;
 977
 978         if (USES_PPGTT(dev)) {
 979                 int i;
 980
 981                 ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
 982
 983                 if (IS_GEN6(dev))
 984                         ering->vm_info.pp_dir_base =
 985                                 I915_READ(RING_PP_DIR_BASE_READ(engine));
 986                 else if (IS_GEN7(dev))
 987                         ering->vm_info.pp_dir_base =
 988                                 I915_READ(RING_PP_DIR_BASE(engine));
 989                 else if (INTEL_INFO(dev)->gen >= 8)
 990                         for (i = 0; i < 4; i++) {
 991                                 ering->vm_info.pdp[i] =
 992                                         I915_READ(GEN8_RING_PDP_UDW(engine, i));
 993                                 ering->vm_info.pdp[i] <<= 32;
 994                                 ering->vm_info.pdp[i] |=
 995                                         I915_READ(GEN8_RING_PDP_LDW(engine, i));
 996                         }
 997         }
 998 }
 999
1000
1001 static void i915_gem_record_active_context(struct intel_engine_cs *engine,
1002                                            struct drm_i915_error_state *error,
1003                                            struct drm_i915_error_ring *ering)
1004 {
1005         struct drm_i915_private *dev_priv = engine->dev->dev_private;
1006         struct drm_i915_gem_object *obj;
1007
1008         /* Currently render ring is the only HW context user */
1009         if (engine->id != RCS || !error->ccid)
1010                 return;
1011
1012         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1013                 if (!i915_gem_obj_ggtt_bound(obj))
1014                         continue;
1015
1016                 if ((error->ccid & LINUX_PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
1017                         ering->ctx = i915_error_ggtt_object_create(dev_priv, obj);
1018                         break;
1019                 }
1020         }
1021 }
1022
1023 static void i915_gem_record_rings(struct drm_device *dev,
1024                                   struct drm_i915_error_state *error)
1025 {
1026         struct drm_i915_private *dev_priv = to_i915(dev);
1027         struct i915_ggtt *ggtt = &dev_priv->ggtt;
1028         struct drm_i915_gem_request *request;
1029         int i, count;
1030
1031         for (i = 0; i < I915_NUM_ENGINES; i++) {
1032                 struct intel_engine_cs *engine = &dev_priv->engine[i];
1033                 struct intel_ringbuffer *rbuf;
1034
1035                 error->ring[i].pid = -1;
1036
1037                 if (engine->dev == NULL)
1038                         continue;
1039
1040                 error->ring[i].valid = true;
1041
1042                 i915_record_ring_state(dev, error, engine, &error->ring[i]);
1043
1044                 request = i915_gem_find_active_request(engine);
1045                 if (request) {
1046                         struct i915_address_space *vm;
1047
1048                         vm = request->ctx && request->ctx->ppgtt ?
1049                                 &request->ctx->ppgtt->base :
1050                                 &ggtt->base;
1051
1052                         /* We need to copy these to an anonymous buffer
1053                          * as the simplest method to avoid being overwritten
1054                          * by userspace.
1055                          */
1056                         error->ring[i].batchbuffer =
1057                                 i915_error_object_create(dev_priv,
1058                                                          request->batch_obj,
1059                                                          vm);
1060
1061                         if (HAS_BROKEN_CS_TLB(dev_priv))
1062                                 error->ring[i].wa_batchbuffer =
1063                                         i915_error_ggtt_object_create(dev_priv,
1064                                                              engine->scratch.obj);
1065
1066                         if (request->pid) {
1067 #if 0
1068                                 struct task_struct *task;
1069
1070                                 rcu_read_lock();
1071                                 task = pid_task(request->pid, PIDTYPE_PID);
1072                                 if (task) {
1073                                         strcpy(error->ring[i].comm, task->comm);
1074                                         error->ring[i].pid = task->pid;
1075                                 }
1076                                 rcu_read_unlock();
1077 #endif
1078                         }
1079                 }
1080
1081                 if (i915.enable_execlists) {
1082                         /* TODO: This is only a small fix to keep basic error
1083                          * capture working, but we need to add more information
1084                          * for it to be useful (e.g. dump the context being
1085                          * executed).
1086                          */
1087                         if (request)
1088                                 rbuf = request->ctx->engine[engine->id].ringbuf;
1089                         else
1090                                 rbuf = dev_priv->kernel_context->engine[engine->id].ringbuf;
1091                 } else
1092                         rbuf = engine->buffer;
1093
1094                 error->ring[i].cpu_ring_head = rbuf->head;
1095                 error->ring[i].cpu_ring_tail = rbuf->tail;
1096
1097                 error->ring[i].ringbuffer =
1098                         i915_error_ggtt_object_create(dev_priv, rbuf->obj);
1099
1100                 error->ring[i].hws_page =
1101                         i915_error_ggtt_object_create(dev_priv,
1102                                                       engine->status_page.obj);
1103
1104                 if (engine->wa_ctx.obj) {
1105                         error->ring[i].wa_ctx =
1106                                 i915_error_ggtt_object_create(dev_priv,
1107                                                               engine->wa_ctx.obj);
1108                 }
1109
1110                 i915_gem_record_active_context(engine, error, &error->ring[i]);
1111
1112                 count = 0;
1113                 list_for_each_entry(request, &engine->request_list, list)
1114                         count++;
1115
1116                 error->ring[i].num_requests = count;
1117                 error->ring[i].requests =
1118                         kcalloc(count, sizeof(*error->ring[i].requests),
1119                                 GFP_ATOMIC);
1120                 if (error->ring[i].requests == NULL) {
1121                         error->ring[i].num_requests = 0;
1122                         continue;
1123                 }
1124
1125                 count = 0;
1126                 list_for_each_entry(request, &engine->request_list, list) {
1127                         struct drm_i915_error_request *erq;
1128
1129                         if (count >= error->ring[i].num_requests) {
1130                                 /*
1131                                  * If the ring request list was changed in
1132                                  * between the point where the error request
1133                                  * list was created and dimensioned and this
1134                                  * point then just exit early to avoid crashes.
1135                                  *
1136                                  * We don't need to communicate that the
1137                                  * request list changed state during error
1138                                  * state capture and that the error state is
1139                                  * slightly incorrect as a consequence since we
1140                                  * are typically only interested in the request
1141                                  * list state at the point of error state
1142                                  * capture, not in any changes happening during
1143                                  * the capture.
1144                                  */
1145                                 break;
1146                         }
1147
1148                         erq = &error->ring[i].requests[count++];
1149                         erq->seqno = request->seqno;
1150                         erq->jiffies = request->emitted_jiffies;
1151                         erq->tail = request->postfix;
1152                 }
1153         }
1154 }
1155
1156 /* FIXME: Since pin count/bound list is global, we duplicate what we capture per
1157  * VM.
1158  */
1159 static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
1160                                 struct drm_i915_error_state *error,
1161                                 struct i915_address_space *vm,
1162                                 const int ndx)
1163 {
1164         struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL;
1165         struct drm_i915_gem_object *obj;
1166         struct i915_vma *vma;
1167         int i;
1168
1169         i = 0;
1170         list_for_each_entry(vma, &vm->active_list, vm_link)
1171                 i++;
1172         error->active_bo_count[ndx] = i;
1173
1174         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1175                 list_for_each_entry(vma, &obj->vma_list, obj_link)
1176                         if (vma->vm == vm && vma->pin_count > 0)
1177                                 i++;
1178         }
1179         error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
1180
1181         if (i) {
1182                 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC);
1183                 if (active_bo)
1184                         pinned_bo = active_bo + error->active_bo_count[ndx];
1185         }
1186
1187         if (active_bo)
1188                 error->active_bo_count[ndx] =
1189                         capture_active_bo(active_bo,
1190                                           error->active_bo_count[ndx],
1191                                           &vm->active_list);
1192
1193         if (pinned_bo)
1194                 error->pinned_bo_count[ndx] =
1195                         capture_pinned_bo(pinned_bo,
1196                                           error->pinned_bo_count[ndx],
1197                                           &dev_priv->mm.bound_list, vm);
1198         error->active_bo[ndx] = active_bo;
1199         error->pinned_bo[ndx] = pinned_bo;
1200 }
1201
1202 static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
1203                                      struct drm_i915_error_state *error)
1204 {
1205         struct i915_address_space *vm;
1206         int cnt = 0, i = 0;
1207
1208         list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1209                 cnt++;
1210
1211         error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
1212         error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
1213         error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
1214                                          GFP_ATOMIC);
1215         error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
1216                                          GFP_ATOMIC);
1217
1218         if (error->active_bo == NULL ||
1219             error->pinned_bo == NULL ||
1220             error->active_bo_count == NULL ||
1221             error->pinned_bo_count == NULL) {
1222                 kfree(error->active_bo);
1223                 kfree(error->active_bo_count);
1224                 kfree(error->pinned_bo);
1225                 kfree(error->pinned_bo_count);
1226
1227                 error->active_bo = NULL;
1228                 error->active_bo_count = NULL;
1229                 error->pinned_bo = NULL;
1230                 error->pinned_bo_count = NULL;
1231         } else {
1232                 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1233                         i915_gem_capture_vm(dev_priv, error, vm, i++);
1234
1235                 error->vm_count = cnt;
1236         }
1237 }
1238
1239 /* Capture all registers which don't fit into another category. */
1240 static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
1241                                    struct drm_i915_error_state *error)
1242 {
1243         struct drm_device *dev = dev_priv->dev;
1244         int i;
1245
1246         /* General organization
1247          * 1. Registers specific to a single generation
1248          * 2. Registers which belong to multiple generations
1249          * 3. Feature specific registers.
1250          * 4. Everything else
1251          * Please try to follow the order.
1252          */
1253
1254         /* 1: Registers specific to a single generation */
1255         if (IS_VALLEYVIEW(dev)) {
1256                 error->gtier[0] = I915_READ(GTIER);
1257                 error->ier = I915_READ(VLV_IER);
1258                 error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
1259         }
1260
1261         if (IS_GEN7(dev))
1262                 error->err_int = I915_READ(GEN7_ERR_INT);
1263
1264         if (INTEL_INFO(dev)->gen >= 8) {
1265                 error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
1266                 error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
1267         }
1268
1269         if (IS_GEN6(dev)) {
1270                 error->forcewake = I915_READ_FW(FORCEWAKE);
1271                 error->gab_ctl = I915_READ(GAB_CTL);
1272                 error->gfx_mode = I915_READ(GFX_MODE);
1273         }
1274
1275         /* 2: Registers which belong to multiple generations */
1276         if (INTEL_INFO(dev)->gen >= 7)
1277                 error->forcewake = I915_READ_FW(FORCEWAKE_MT);
1278
1279         if (INTEL_INFO(dev)->gen >= 6) {
1280                 error->derrmr = I915_READ(DERRMR);
1281                 error->error = I915_READ(ERROR_GEN6);
1282                 error->done_reg = I915_READ(DONE_REG);
1283         }
1284
1285         /* 3: Feature specific registers */
1286         if (IS_GEN6(dev) || IS_GEN7(dev)) {
1287                 error->gam_ecochk = I915_READ(GAM_ECOCHK);
1288                 error->gac_eco = I915_READ(GAC_ECO_BITS);
1289         }
1290
1291         /* 4: Everything else */
1292         if (HAS_HW_CONTEXTS(dev))
1293                 error->ccid = I915_READ(CCID);
1294
1295         if (INTEL_INFO(dev)->gen >= 8) {
1296                 error->ier = I915_READ(GEN8_DE_MISC_IER);
1297                 for (i = 0; i < 4; i++)
1298                         error->gtier[i] = I915_READ(GEN8_GT_IER(i));
1299         } else if (HAS_PCH_SPLIT(dev)) {
1300                 error->ier = I915_READ(DEIER);
1301                 error->gtier[0] = I915_READ(GTIER);
1302         } else if (IS_GEN2(dev)) {
1303                 error->ier = I915_READ16(IER);
1304         } else if (!IS_VALLEYVIEW(dev)) {
1305                 error->ier = I915_READ(IER);
1306         }
1307         error->eir = I915_READ(EIR);
1308         error->pgtbl_er = I915_READ(PGTBL_ER);
1309
1310         i915_get_extra_instdone(dev, error->extra_instdone);
1311 }
1312
1313 static void i915_error_capture_msg(struct drm_device *dev,
1314                                    struct drm_i915_error_state *error,
1315                                    u32 engine_mask,
1316                                    const char *error_msg)
1317 {
1318         struct drm_i915_private *dev_priv = dev->dev_private;
1319         u32 ecode;
1320         int ring_id = -1, len;
1321
1322         ecode = i915_error_generate_code(dev_priv, error, &ring_id);
1323
1324         len = scnprintf(error->error_msg, sizeof(error->error_msg),
1325                         "GPU HANG: ecode %d:%d:0x%08x",
1326                         INTEL_INFO(dev)->gen, ring_id, ecode);
1327
1328         if (ring_id != -1 && error->ring[ring_id].pid != -1)
1329                 len += scnprintf(error->error_msg + len,
1330                                  sizeof(error->error_msg) - len,
1331                                  ", in %s [%d]",
1332                                  error->ring[ring_id].comm,
1333                                  error->ring[ring_id].pid);
1334
1335         scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
1336                   ", reason: %s, action: %s",
1337                   error_msg,
1338                   engine_mask ? "reset" : "continue");
1339 }
1340
1341 static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
1342                                    struct drm_i915_error_state *error)
1343 {
1344         error->iommu = -1;
1345 #ifdef CONFIG_INTEL_IOMMU
1346         error->iommu = intel_iommu_gfx_mapped;
1347 #endif
1348         error->reset_count = i915_reset_count(&dev_priv->gpu_error);
1349         error->suspend_count = dev_priv->suspend_count;
1350 }
1351
1352 /**
1353  * i915_capture_error_state - capture an error record for later analysis
1354  * @dev: drm device
1355  *
1356  * Should be called when an error is detected (either a hang or an error
1357  * interrupt) to capture error state from the time of the error.  Fills
1358  * out a structure which becomes available in debugfs for user level tools
1359  * to pick up.
1360  */
1361 void i915_capture_error_state(struct drm_device *dev, u32 engine_mask,
1362                               const char *error_msg)
1363 {
1364         static bool warned;
1365         struct drm_i915_private *dev_priv = dev->dev_private;
1366         struct drm_i915_error_state *error;
1367         unsigned long flags;
1368
1369         /* Account for pipe specific data like PIPE*STAT */
1370         error = kzalloc(sizeof(*error), GFP_ATOMIC);
1371         if (!error) {
1372                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1373                 return;
1374         }
1375
1376         kref_init(&error->ref);
1377
1378         i915_capture_gen_state(dev_priv, error);
1379         i915_capture_reg_state(dev_priv, error);
1380         i915_gem_capture_buffers(dev_priv, error);
1381         i915_gem_record_fences(dev, error);
1382         i915_gem_record_rings(dev, error);
1383
1384         do_gettimeofday(&error->time);
1385
1386         error->overlay = intel_overlay_capture_error_state(dev);
1387         error->display = intel_display_capture_error_state(dev);
1388
1389         i915_error_capture_msg(dev, error, engine_mask, error_msg);
1390         DRM_INFO("%s\n", error->error_msg);
1391
1392         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1393         if (dev_priv->gpu_error.first_error == NULL) {
1394                 dev_priv->gpu_error.first_error = error;
1395                 error = NULL;
1396         }
1397         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1398
1399         if (error) {
1400                 i915_error_state_free(&error->ref);
1401                 return;
1402         }
1403
1404         if (!warned) {
1405                 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1406                 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1407                 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1408                 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1409                 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index);
1410                 warned = true;
1411         }
1412 }
1413
1414 void i915_error_state_get(struct drm_device *dev,
1415                           struct i915_error_state_file_priv *error_priv)
1416 {
1417         struct drm_i915_private *dev_priv = dev->dev_private;
1418
1419         spin_lock_irq(&dev_priv->gpu_error.lock);
1420         error_priv->error = dev_priv->gpu_error.first_error;
1421         if (error_priv->error)
1422                 kref_get(&error_priv->error->ref);
1423         spin_unlock_irq(&dev_priv->gpu_error.lock);
1424
1425 }
1426
1427 void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
1428 {
1429         if (error_priv->error)
1430                 kref_put(&error_priv->error->ref, i915_error_state_free);
1431 }
1432
1433 void i915_destroy_error_state(struct drm_device *dev)
1434 {
1435         struct drm_i915_private *dev_priv = dev->dev_private;
1436         struct drm_i915_error_state *error;
1437
1438         spin_lock_irq(&dev_priv->gpu_error.lock);
1439         error = dev_priv->gpu_error.first_error;
1440         dev_priv->gpu_error.first_error = NULL;
1441         spin_unlock_irq(&dev_priv->gpu_error.lock);
1442
1443         if (error)
1444                 kref_put(&error->ref, i915_error_state_free);
1445 }
1446
1447 const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
1448 {
1449         switch (type) {
1450         case I915_CACHE_NONE: return " uncached";
1451         case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
1452         case I915_CACHE_L3_LLC: return " L3+LLC";
1453         case I915_CACHE_WT: return " WT";
1454         default: return "";
1455         }
1456 }
1457
1458 /* NB: please notice the memset */
1459 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
1460 {
1461         struct drm_i915_private *dev_priv = dev->dev_private;
1462         memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1463
1464         if (IS_GEN2(dev) || IS_GEN3(dev))
1465                 instdone[0] = I915_READ(GEN2_INSTDONE);
1466         else if (IS_GEN4(dev) || IS_GEN5(dev) || IS_GEN6(dev)) {
1467                 instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
1468                 instdone[1] = I915_READ(GEN4_INSTDONE1);
1469         } else if (INTEL_INFO(dev)->gen >= 7) {
1470                 instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
1471                 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1472                 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1473                 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1474         }
1475 }