sys/dev/drm/radeon/radeon_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  *
  32  * $FreeBSD: head/sys/dev/drm2/radeon/radeon_ttm.c 254885 2013-08-25 19:37:15Z dumbbell $
  33  */
  34 #include <ttm/ttm_bo_api.h>
  35 #include <ttm/ttm_bo_driver.h>
  36 #include <ttm/ttm_placement.h>
  37 #include <ttm/ttm_module.h>
  38 #include <ttm/ttm_page_alloc.h>
  39 #include <drm/drmP.h>
  40 #include <drm/radeon_drm.h>
  41 #include <linux/seq_file.h>
  42 #include <linux/slab.h>
  43 #include <linux/swap.h>
  44 #include <linux/pagemap.h>
  45 #include "radeon_reg.h"
  46 #include "radeon.h"
  47
  48 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  49
  50 static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
  51 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev);
  52
  53 static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
  54 {
  55         struct radeon_mman *mman;
  56         struct radeon_device *rdev;
  57
  58         mman = container_of(bdev, struct radeon_mman, bdev);
  59         rdev = container_of(mman, struct radeon_device, mman);
  60         return rdev;
  61 }
  62
  63
  64 /*
  65  * Global memory.
  66  */
  67 static int radeon_ttm_mem_global_init(struct drm_global_reference *ref)
  68 {
  69         return ttm_mem_global_init(ref->object);
  70 }
  71
  72 static void radeon_ttm_mem_global_release(struct drm_global_reference *ref)
  73 {
  74         ttm_mem_global_release(ref->object);
  75 }
  76
  77 static int radeon_ttm_global_init(struct radeon_device *rdev)
  78 {
  79         struct drm_global_reference *global_ref;
  80         int r;
  81
  82         rdev->mman.mem_global_referenced = false;
  83         global_ref = &rdev->mman.mem_global_ref;
  84         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  85         global_ref->size = sizeof(struct ttm_mem_global);
  86         global_ref->init = &radeon_ttm_mem_global_init;
  87         global_ref->release = &radeon_ttm_mem_global_release;
  88         r = drm_global_item_ref(global_ref);
  89         if (r != 0) {
  90                 DRM_ERROR("Failed setting up TTM memory accounting "
  91                           "subsystem.\n");
  92                 return r;
  93         }
  94
  95         rdev->mman.bo_global_ref.mem_glob =
  96                 rdev->mman.mem_global_ref.object;
  97         global_ref = &rdev->mman.bo_global_ref.ref;
  98         global_ref->global_type = DRM_GLOBAL_TTM_BO;
  99         global_ref->size = sizeof(struct ttm_bo_global);
 100         global_ref->init = &ttm_bo_global_init;
 101         global_ref->release = &ttm_bo_global_release;
 102         r = drm_global_item_ref(global_ref);
 103         if (r != 0) {
 104                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
 105                 drm_global_item_unref(&rdev->mman.mem_global_ref);
 106                 return r;
 107         }
 108
 109         rdev->mman.mem_global_referenced = true;
 110         return 0;
 111 }
 112
 113 static void radeon_ttm_global_fini(struct radeon_device *rdev)
 114 {
 115         if (rdev->mman.mem_global_referenced) {
 116                 drm_global_item_unref(&rdev->mman.bo_global_ref.ref);
 117                 drm_global_item_unref(&rdev->mman.mem_global_ref);
 118                 rdev->mman.mem_global_referenced = false;
 119         }
 120 }
 121
 122 static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 123 {
 124         return 0;
 125 }
 126
 127 static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 128                                 struct ttm_mem_type_manager *man)
 129 {
 130         struct radeon_device *rdev;
 131
 132         rdev = radeon_get_rdev(bdev);
 133
 134         switch (type) {
 135         case TTM_PL_SYSTEM:
 136                 /* System memory */
 137                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 138                 man->available_caching = TTM_PL_MASK_CACHING;
 139                 man->default_caching = TTM_PL_FLAG_CACHED;
 140                 break;
 141         case TTM_PL_TT:
 142                 man->func = &ttm_bo_manager_func;
 143                 man->gpu_offset = rdev->mc.gtt_start;
 144                 man->available_caching = TTM_PL_MASK_CACHING;
 145                 man->default_caching = TTM_PL_FLAG_CACHED;
 146                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 147 #if IS_ENABLED(CONFIG_AGP)
 148                 if (rdev->flags & RADEON_IS_AGP) {
 149                         if (!rdev->ddev->agp) {
 150                                 DRM_ERROR("AGP is not enabled for memory type %u\n",
 151                                           (unsigned)type);
 152                                 return -EINVAL;
 153                         }
 154                         if (!rdev->ddev->agp->cant_use_aperture)
 155                                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 156                         man->available_caching = TTM_PL_FLAG_UNCACHED |
 157                                                  TTM_PL_FLAG_WC;
 158                         man->default_caching = TTM_PL_FLAG_WC;
 159                 }
 160 #endif
 161                 break;
 162         case TTM_PL_VRAM:
 163                 /* "On-card" video ram */
 164                 man->func = &ttm_bo_manager_func;
 165                 man->gpu_offset = rdev->mc.vram_start;
 166                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 167                              TTM_MEMTYPE_FLAG_MAPPABLE;
 168                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 169                 man->default_caching = TTM_PL_FLAG_WC;
 170                 break;
 171         default:
 172                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 173                 return -EINVAL;
 174         }
 175         return 0;
 176 }
 177
 178 static void radeon_evict_flags(struct ttm_buffer_object *bo,
 179                                 struct ttm_placement *placement)
 180 {
 181         static struct ttm_place placements = {
 182                 .fpfn = 0,
 183                 .lpfn = 0,
 184                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 185         };
 186
 187         struct radeon_bo *rbo;
 188
 189         if (!radeon_ttm_bo_is_radeon_bo(bo)) {
 190                 placement->placement = &placements;
 191                 placement->busy_placement = &placements;
 192                 placement->num_placement = 1;
 193                 placement->num_busy_placement = 1;
 194                 return;
 195         }
 196         rbo = container_of(bo, struct radeon_bo, tbo);
 197         switch (bo->mem.mem_type) {
 198         case TTM_PL_VRAM:
 199                 if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false)
 200                         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
 201                 else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size &&
 202                          bo->mem.start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) {
 203                         unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 204                         int i;
 205
 206                         /* Try evicting to the CPU inaccessible part of VRAM
 207                          * first, but only set GTT as busy placement, so this
 208                          * BO will be evicted to GTT rather than causing other
 209                          * BOs to be evicted from VRAM
 210                          */
 211                         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM |
 212                                                          RADEON_GEM_DOMAIN_GTT);
 213                         rbo->placement.num_busy_placement = 0;
 214                         for (i = 0; i < rbo->placement.num_placement; i++) {
 215                                 if (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) {
 216                                         if (rbo->placements[i].fpfn < fpfn)
 217                                                 rbo->placements[i].fpfn = fpfn;
 218                                 } else {
 219                                         rbo->placement.busy_placement =
 220                                                 &rbo->placements[i];
 221                                         rbo->placement.num_busy_placement = 1;
 222                                 }
 223                         }
 224                 } else
 225                         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
 226                 break;
 227         case TTM_PL_TT:
 228         default:
 229                 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
 230         }
 231         *placement = rbo->placement;
 232 }
 233
 234 static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 235 {
 236 #if 0
 237         struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
 238 #endif
 239
 240         if (radeon_ttm_tt_has_userptr(bo->ttm))
 241                 return -EPERM;
 242
 243         return 0;
 244 }
 245
 246 static void radeon_move_null(struct ttm_buffer_object *bo,
 247                              struct ttm_mem_reg *new_mem)
 248 {
 249         struct ttm_mem_reg *old_mem = &bo->mem;
 250
 251         BUG_ON(old_mem->mm_node != NULL);
 252         *old_mem = *new_mem;
 253         new_mem->mm_node = NULL;
 254 }
 255
 256 static int radeon_move_blit(struct ttm_buffer_object *bo,
 257                         bool evict, bool no_wait_gpu,
 258                         struct ttm_mem_reg *new_mem,
 259                         struct ttm_mem_reg *old_mem)
 260 {
 261         struct radeon_device *rdev;
 262         uint64_t old_start, new_start;
 263         struct radeon_fence *fence;
 264         unsigned num_pages;
 265         int r, ridx;
 266
 267         rdev = radeon_get_rdev(bo->bdev);
 268         ridx = radeon_copy_ring_index(rdev);
 269         old_start = (u64)old_mem->start << PAGE_SHIFT;
 270         new_start = (u64)new_mem->start << PAGE_SHIFT;
 271
 272         switch (old_mem->mem_type) {
 273         case TTM_PL_VRAM:
 274                 old_start += rdev->mc.vram_start;
 275                 break;
 276         case TTM_PL_TT:
 277                 old_start += rdev->mc.gtt_start;
 278                 break;
 279         default:
 280                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
 281                 return -EINVAL;
 282         }
 283         switch (new_mem->mem_type) {
 284         case TTM_PL_VRAM:
 285                 new_start += rdev->mc.vram_start;
 286                 break;
 287         case TTM_PL_TT:
 288                 new_start += rdev->mc.gtt_start;
 289                 break;
 290         default:
 291                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
 292                 return -EINVAL;
 293         }
 294         if (!rdev->ring[ridx].ready) {
 295                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 296                 return -EINVAL;
 297         }
 298
 299         BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
 300
 301         num_pages = new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
 302         fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->resv);
 303         if (IS_ERR(fence))
 304                 return PTR_ERR(fence);
 305
 306         r = ttm_bo_move_accel_cleanup(bo, &fence->base,
 307                                       evict, no_wait_gpu, new_mem);
 308         radeon_fence_unref(&fence);
 309         return r;
 310 }
 311
 312 static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
 313                                 bool evict, bool interruptible,
 314                                 bool no_wait_gpu,
 315                                 struct ttm_mem_reg *new_mem)
 316 {
 317         struct radeon_device *rdev;
 318         struct ttm_mem_reg *old_mem = &bo->mem;
 319         struct ttm_mem_reg tmp_mem;
 320         struct ttm_place placements;
 321         struct ttm_placement placement;
 322         int r;
 323
 324         rdev = radeon_get_rdev(bo->bdev);
 325         tmp_mem = *new_mem;
 326         tmp_mem.mm_node = NULL;
 327         placement.num_placement = 1;
 328         placement.placement = &placements;
 329         placement.num_busy_placement = 1;
 330         placement.busy_placement = &placements;
 331         placements.fpfn = 0;
 332         placements.lpfn = 0;
 333         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 334         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 335                              interruptible, no_wait_gpu);
 336         if (unlikely(r)) {
 337                 return r;
 338         }
 339
 340         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 341         if (unlikely(r)) {
 342                 goto out_cleanup;
 343         }
 344
 345         r = ttm_tt_bind(bo->ttm, &tmp_mem);
 346         if (unlikely(r)) {
 347                 goto out_cleanup;
 348         }
 349         r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
 350         if (unlikely(r)) {
 351                 goto out_cleanup;
 352         }
 353         r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
 354 out_cleanup:
 355         ttm_bo_mem_put(bo, &tmp_mem);
 356         return r;
 357 }
 358
 359 static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
 360                                 bool evict, bool interruptible,
 361                                 bool no_wait_gpu,
 362                                 struct ttm_mem_reg *new_mem)
 363 {
 364         struct radeon_device *rdev;
 365         struct ttm_mem_reg *old_mem = &bo->mem;
 366         struct ttm_mem_reg tmp_mem;
 367         struct ttm_placement placement;
 368         struct ttm_place placements;
 369         int r;
 370
 371         rdev = radeon_get_rdev(bo->bdev);
 372         tmp_mem = *new_mem;
 373         tmp_mem.mm_node = NULL;
 374         placement.num_placement = 1;
 375         placement.placement = &placements;
 376         placement.num_busy_placement = 1;
 377         placement.busy_placement = &placements;
 378         placements.fpfn = 0;
 379         placements.lpfn = 0;
 380         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 381         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 382                              interruptible, no_wait_gpu);
 383         if (unlikely(r)) {
 384                 return r;
 385         }
 386         r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
 387         if (unlikely(r)) {
 388                 goto out_cleanup;
 389         }
 390         r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
 391         if (unlikely(r)) {
 392                 goto out_cleanup;
 393         }
 394 out_cleanup:
 395         ttm_bo_mem_put(bo, &tmp_mem);
 396         return r;
 397 }
 398
 399 static int radeon_bo_move(struct ttm_buffer_object *bo,
 400                         bool evict, bool interruptible,
 401                         bool no_wait_gpu,
 402                         struct ttm_mem_reg *new_mem)
 403 {
 404         struct radeon_device *rdev;
 405         struct radeon_bo *rbo;
 406         struct ttm_mem_reg *old_mem = &bo->mem;
 407         int r;
 408
 409         /* Can't move a pinned BO */
 410         rbo = container_of(bo, struct radeon_bo, tbo);
 411         if (WARN_ON_ONCE(rbo->pin_count > 0))
 412                 return -EINVAL;
 413
 414         rdev = radeon_get_rdev(bo->bdev);
 415         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 416                 radeon_move_null(bo, new_mem);
 417                 return 0;
 418         }
 419         if ((old_mem->mem_type == TTM_PL_TT &&
 420              new_mem->mem_type == TTM_PL_SYSTEM) ||
 421             (old_mem->mem_type == TTM_PL_SYSTEM &&
 422              new_mem->mem_type == TTM_PL_TT)) {
 423                 /* bind is enough */
 424                 radeon_move_null(bo, new_mem);
 425                 return 0;
 426         }
 427         if (!rdev->ring[radeon_copy_ring_index(rdev)].ready ||
 428             rdev->asic->copy.copy == NULL) {
 429                 /* use memcpy */
 430                 goto memcpy;
 431         }
 432
 433         if (old_mem->mem_type == TTM_PL_VRAM &&
 434             new_mem->mem_type == TTM_PL_SYSTEM) {
 435                 r = radeon_move_vram_ram(bo, evict, interruptible,
 436                                         no_wait_gpu, new_mem);
 437         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 438                    new_mem->mem_type == TTM_PL_VRAM) {
 439                 r = radeon_move_ram_vram(bo, evict, interruptible,
 440                                             no_wait_gpu, new_mem);
 441         } else {
 442                 r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
 443         }
 444
 445         if (r) {
 446 memcpy:
 447                 r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
 448                 if (r) {
 449                         return r;
 450                 }
 451         }
 452
 453         /* update statistics */
 454         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved);
 455         return 0;
 456 }
 457
 458 static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 459 {
 460         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 461         struct radeon_device *rdev = radeon_get_rdev(bdev);
 462
 463         mem->bus.addr = NULL;
 464         mem->bus.offset = 0;
 465         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 466         mem->bus.base = 0;
 467         mem->bus.is_iomem = false;
 468         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 469                 return -EINVAL;
 470         switch (mem->mem_type) {
 471         case TTM_PL_SYSTEM:
 472                 /* system memory */
 473                 return 0;
 474         case TTM_PL_TT:
 475 #if IS_ENABLED(CONFIG_AGP)
 476                 if (rdev->flags & RADEON_IS_AGP) {
 477                         /* RADEON_IS_AGP is set only if AGP is active */
 478                         mem->bus.offset = mem->start << PAGE_SHIFT;
 479                         mem->bus.base = rdev->mc.agp_base;
 480                         mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture;
 481                 }
 482 #endif
 483                 break;
 484         case TTM_PL_VRAM:
 485                 mem->bus.offset = mem->start << PAGE_SHIFT;
 486                 /* check if it's visible */
 487                 if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size)
 488                         return -EINVAL;
 489                 mem->bus.base = rdev->mc.aper_base;
 490                 mem->bus.is_iomem = true;
 491 #ifdef __alpha__
 492                 /*
 493                  * Alpha: use bus.addr to hold the ioremap() return,
 494                  * so we can modify bus.base below.
 495                  */
 496                 if (mem->placement & TTM_PL_FLAG_WC)
 497                         mem->bus.addr =
 498                                 ioremap_wc(mem->bus.base + mem->bus.offset,
 499                                            mem->bus.size);
 500                 else
 501                         mem->bus.addr =
 502                                 ioremap_nocache(mem->bus.base + mem->bus.offset,
 503                                                 mem->bus.size);
 504
 505                 /*
 506                  * Alpha: Use just the bus offset plus
 507                  * the hose/domain memory base for bus.base.
 508                  * It then can be used to build PTEs for VRAM
 509                  * access, as done in ttm_bo_vm_fault().
 510                  */
 511                 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
 512                         rdev->ddev->hose->dense_mem_base;
 513 #endif
 514                 break;
 515         default:
 516                 return -EINVAL;
 517         }
 518         return 0;
 519 }
 520
 521 static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 522 {
 523 }
 524
 525 /*
 526  * TTM backend functions.
 527  */
 528 struct radeon_ttm_tt {
 529         struct ttm_dma_tt               ttm;
 530         struct radeon_device            *rdev;
 531         u64                             offset;
 532
 533         uint64_t                        userptr;
 534         struct mm_struct                *usermm;
 535         uint32_t                        userflags;
 536 };
 537
 538 #if 0
 539 /* prepare the sg table with the user pages */
 540 static int radeon_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 541 {
 542         struct radeon_device *rdev = radeon_get_rdev(ttm->bdev);
 543         struct radeon_ttm_tt *gtt = (void *)ttm;
 544         unsigned pinned = 0, nents;
 545         int r;
 546
 547         int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
 548         enum dma_data_direction direction = write ?
 549                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 550
 551         if (current->mm != gtt->usermm)
 552                 return -EPERM;
 553
 554         if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) {
 555                 /* check that we only pin down anonymous memory
 556                    to prevent problems with writeback */
 557                 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
 558                 struct vm_area_struct *vma;
 559                 vma = find_vma(gtt->usermm, gtt->userptr);
 560                 if (!vma || vma->vm_file || vma->vm_end < end)
 561                         return -EPERM;
 562         }
 563
 564         do {
 565                 unsigned num_pages = ttm->num_pages - pinned;
 566                 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
 567                 struct page **pages = ttm->pages + pinned;
 568
 569                 r = get_user_pages(userptr, num_pages, write, 0, pages, NULL);
 570                 if (r < 0)
 571                         goto release_pages;
 572
 573                 pinned += r;
 574
 575         } while (pinned < ttm->num_pages);
 576
 577         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 578                                       ttm->num_pages << PAGE_SHIFT,
 579                                       GFP_KERNEL);
 580         if (r)
 581                 goto release_sg;
 582
 583         r = -ENOMEM;
 584         nents = dma_map_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 585         if (nents != ttm->sg->nents)
 586                 goto release_sg;
 587
 588         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 589                                          gtt->ttm.dma_address, ttm->num_pages);
 590
 591         return 0;
 592
 593 release_sg:
 594         kfree(ttm->sg);
 595
 596 release_pages:
 597         release_pages(ttm->pages, pinned, 0);
 598         return r;
 599 }
 600
 601 static void radeon_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 602 {
 603         struct radeon_device *rdev = radeon_get_rdev(ttm->bdev);
 604         struct radeon_ttm_tt *gtt = (void *)ttm;
 605         struct sg_page_iter sg_iter;
 606
 607         int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
 608         enum dma_data_direction direction = write ?
 609                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 610
 611         /* double check that we don't free the table twice */
 612         if (!ttm->sg->sgl)
 613                 return;
 614
 615         /* free the sg table and pages again */
 616         dma_unmap_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 617
 618         for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
 619                 struct page *page = sg_page_iter_page(&sg_iter);
 620                 if (!(gtt->userflags & RADEON_GEM_USERPTR_READONLY))
 621                         set_page_dirty(page);
 622
 623                 mark_page_accessed(page);
 624                 put_page(page);
 625         }
 626
 627         sg_free_table(ttm->sg);
 628 }
 629 #endif
 630
 631 static int radeon_ttm_backend_bind(struct ttm_tt *ttm,
 632                                    struct ttm_mem_reg *bo_mem)
 633 {
 634         struct radeon_ttm_tt *gtt = (void*)ttm;
 635         uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ |
 636                 RADEON_GART_PAGE_WRITE;
 637         int r;
 638
 639 #if 0
 640         if (gtt->userptr) {
 641                 radeon_ttm_tt_pin_userptr(ttm);
 642                 flags &= ~RADEON_GART_PAGE_WRITE;
 643         }
 644 #endif
 645
 646         gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
 647         if (!ttm->num_pages) {
 648                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
 649                      ttm->num_pages, bo_mem, ttm);
 650         }
 651         if (ttm->caching_state == tt_cached)
 652                 flags |= RADEON_GART_PAGE_SNOOP;
 653         r = radeon_gart_bind(gtt->rdev, gtt->offset, ttm->num_pages,
 654                              ttm->pages, gtt->ttm.dma_address, flags);
 655         if (r) {
 656                 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
 657                           ttm->num_pages, (unsigned)gtt->offset);
 658                 return r;
 659         }
 660         return 0;
 661 }
 662
 663 static int radeon_ttm_backend_unbind(struct ttm_tt *ttm)
 664 {
 665         struct radeon_ttm_tt *gtt = (void *)ttm;
 666
 667         radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages);
 668 #if 0
 669         if (gtt->userptr)
 670                 radeon_ttm_tt_unpin_userptr(ttm);
 671 #endif
 672
 673         return 0;
 674 }
 675
 676 static void radeon_ttm_backend_destroy(struct ttm_tt *ttm)
 677 {
 678         struct radeon_ttm_tt *gtt = (void *)ttm;
 679
 680         ttm_dma_tt_fini(&gtt->ttm);
 681         kfree(gtt);
 682 }
 683
 684 static struct ttm_backend_func radeon_backend_func = {
 685         .bind = &radeon_ttm_backend_bind,
 686         .unbind = &radeon_ttm_backend_unbind,
 687         .destroy = &radeon_ttm_backend_destroy,
 688 };
 689
 690 static struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev,
 691                                     unsigned long size, uint32_t page_flags,
 692                                     struct page *dummy_read_page)
 693 {
 694         struct radeon_device *rdev;
 695         struct radeon_ttm_tt *gtt;
 696
 697         rdev = radeon_get_rdev(bdev);
 698 #if IS_ENABLED(CONFIG_AGP)
 699         if (rdev->flags & RADEON_IS_AGP) {
 700                 return ttm_agp_tt_create(bdev, rdev->ddev->agp->agpdev,
 701                                          size, page_flags, dummy_read_page);
 702         }
 703 #endif
 704
 705         gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL);
 706         if (gtt == NULL) {
 707                 return NULL;
 708         }
 709         gtt->ttm.ttm.func = &radeon_backend_func;
 710         gtt->rdev = rdev;
 711         if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
 712                 kfree(gtt);
 713                 return NULL;
 714         }
 715         return &gtt->ttm.ttm;
 716 }
 717
 718 static struct radeon_ttm_tt *radeon_ttm_tt_to_gtt(struct ttm_tt *ttm)
 719 {
 720         if (!ttm || ttm->func != &radeon_backend_func)
 721                 return NULL;
 722         return (struct radeon_ttm_tt *)ttm;
 723 }
 724
 725 static int radeon_ttm_tt_populate(struct ttm_tt *ttm)
 726 {
 727         struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
 728         struct radeon_device *rdev;
 729         unsigned i;
 730         int r;
 731 #ifdef DUMBBELL_WIP
 732         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 733 #endif /* DUMBBELL_WIP */
 734
 735         if (ttm->state != tt_unpopulated)
 736                 return 0;
 737
 738 #if 0
 739         if (gtt && gtt->userptr) {
 740                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
 741                 if (!ttm->sg)
 742                         return -ENOMEM;
 743
 744                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
 745                 ttm->state = tt_unbound;
 746                 return 0;
 747         }
 748 #endif
 749
 750 #ifdef DUMBBELL_WIP
 751         /*
 752          * Maybe unneeded on FreeBSD.
 753          *   -- dumbbell@
 754          */
 755         if (slave && ttm->sg) {
 756                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 757                                                  gtt->ttm.dma_address, ttm->num_pages);
 758                 ttm->state = tt_unbound;
 759                 return 0;
 760         }
 761 #endif /* DUMBBELL_WIP */
 762
 763         rdev = radeon_get_rdev(ttm->bdev);
 764 #if IS_ENABLED(CONFIG_AGP)
 765         if (rdev->flags & RADEON_IS_AGP) {
 766                 return ttm_agp_tt_populate(ttm);
 767         }
 768 #endif
 769
 770 #ifdef CONFIG_SWIOTLB
 771         if (swiotlb_nr_tbl()) {
 772                 return ttm_dma_populate(&gtt->ttm, rdev->dev);
 773         }
 774 #endif
 775
 776         r = ttm_pool_populate(ttm);
 777         if (r) {
 778                 return r;
 779         }
 780
 781         for (i = 0; i < ttm->num_pages; i++) {
 782                 gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i],
 783                                                        0, PAGE_SIZE,
 784                                                        PCI_DMA_BIDIRECTIONAL);
 785 #ifdef DUMBBELL_WIP
 786                 if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) {
 787                         while (i--) {
 788                                 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
 789                                                PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 790                                 gtt->ttm.dma_address[i] = 0;
 791                         }
 792                         ttm_pool_unpopulate(ttm);
 793                         return -EFAULT;
 794                 }
 795 #endif /* DUMBBELL_WIP */
 796         }
 797         return 0;
 798 }
 799
 800 static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm)
 801 {
 802         struct radeon_device *rdev;
 803         struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
 804         unsigned i;
 805         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 806
 807 #if 0
 808         if (gtt && gtt->userptr) {
 809                 kfree(ttm->sg);
 810                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
 811                 return;
 812         }
 813 #endif
 814
 815         if (slave)
 816                 return;
 817
 818         rdev = radeon_get_rdev(ttm->bdev);
 819 #if IS_ENABLED(CONFIG_AGP)
 820         if (rdev->flags & RADEON_IS_AGP) {
 821                 ttm_agp_tt_unpopulate(ttm);
 822                 return;
 823         }
 824 #endif
 825
 826 #ifdef CONFIG_SWIOTLB
 827         if (swiotlb_nr_tbl()) {
 828                 ttm_dma_unpopulate(&gtt->ttm, rdev->dev);
 829                 return;
 830         }
 831 #endif
 832
 833         for (i = 0; i < ttm->num_pages; i++) {
 834                 if (gtt->ttm.dma_address[i]) {
 835                         gtt->ttm.dma_address[i] = 0;
 836 #ifdef DUMBBELL_WIP
 837                         pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
 838                                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 839 #endif /* DUMBBELL_WIP */
 840                 }
 841         }
 842
 843         ttm_pool_unpopulate(ttm);
 844 }
 845
 846 bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm)
 847 {
 848 #if 0
 849         struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
 850
 851         if (gtt == NULL)
 852 #endif
 853                 return false;
 854
 855 #if 0
 856         return !!gtt->userptr;
 857 #endif
 858 }
 859
 860 bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm)
 861 {
 862         struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
 863
 864         if (gtt == NULL)
 865                 return false;
 866
 867         return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
 868 }
 869
 870 static struct ttm_bo_driver radeon_bo_driver = {
 871         .ttm_tt_create = &radeon_ttm_tt_create,
 872         .ttm_tt_populate = &radeon_ttm_tt_populate,
 873         .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate,
 874         .invalidate_caches = &radeon_invalidate_caches,
 875         .init_mem_type = &radeon_init_mem_type,
 876         .evict_flags = &radeon_evict_flags,
 877         .move = &radeon_bo_move,
 878         .verify_access = &radeon_verify_access,
 879         .move_notify = &radeon_bo_move_notify,
 880         .fault_reserve_notify = &radeon_bo_fault_reserve_notify,
 881         .io_mem_reserve = &radeon_ttm_io_mem_reserve,
 882         .io_mem_free = &radeon_ttm_io_mem_free,
 883         .lru_tail = &ttm_bo_default_lru_tail,
 884         .swap_lru_tail = &ttm_bo_default_swap_lru_tail,
 885 };
 886
 887 int radeon_ttm_init(struct radeon_device *rdev)
 888 {
 889         int r;
 890
 891         r = radeon_ttm_global_init(rdev);
 892         if (r) {
 893                 return r;
 894         }
 895         /* No others user of address space so set it to 0 */
 896         r = ttm_bo_device_init(&rdev->mman.bdev,
 897                                rdev->mman.bo_global_ref.ref.object,
 898                                &radeon_bo_driver,
 899 #ifdef __DragonFly__
 900                                NULL,
 901 #else
 902                                rdev->ddev->anon_inode->i_mapping,
 903 #endif
 904                                DRM_FILE_PAGE_OFFSET,
 905                                rdev->need_dma32);
 906         if (r) {
 907                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
 908                 return r;
 909         }
 910         rdev->mman.initialized = true;
 911         rdev->ddev->drm_ttm_bdev = &rdev->mman.bdev;
 912         r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
 913                                 rdev->mc.real_vram_size >> PAGE_SHIFT);
 914         if (r) {
 915                 DRM_ERROR("Failed initializing VRAM heap.\n");
 916                 return r;
 917         }
 918         /* Change the size here instead of the init above so only lpfn is affected */
 919         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
 920
 921         r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true,
 922                              RADEON_GEM_DOMAIN_VRAM, 0, NULL,
 923                              NULL, &rdev->stollen_vga_memory);
 924         if (r) {
 925                 return r;
 926         }
 927         r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
 928         if (r)
 929                 return r;
 930         r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
 931         radeon_bo_unreserve(rdev->stollen_vga_memory);
 932         if (r) {
 933                 radeon_bo_unref(&rdev->stollen_vga_memory);
 934                 return r;
 935         }
 936         DRM_INFO("radeon: %uM of VRAM memory ready\n",
 937                  (unsigned) (rdev->mc.real_vram_size / (1024 * 1024)));
 938         r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
 939                                 rdev->mc.gtt_size >> PAGE_SHIFT);
 940         if (r) {
 941                 DRM_ERROR("Failed initializing GTT heap.\n");
 942                 return r;
 943         }
 944         DRM_INFO("radeon: %uM of GTT memory ready.\n",
 945                  (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
 946
 947         r = radeon_ttm_debugfs_init(rdev);
 948         if (r) {
 949                 DRM_ERROR("Failed to init debugfs\n");
 950                 return r;
 951         }
 952         return 0;
 953 }
 954
 955 void radeon_ttm_fini(struct radeon_device *rdev)
 956 {
 957         int r;
 958
 959         if (!rdev->mman.initialized)
 960                 return;
 961         radeon_ttm_debugfs_fini(rdev);
 962         if (rdev->stollen_vga_memory) {
 963                 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
 964                 if (r == 0) {
 965                         radeon_bo_unpin(rdev->stollen_vga_memory);
 966                         radeon_bo_unreserve(rdev->stollen_vga_memory);
 967                 }
 968                 radeon_bo_unref(&rdev->stollen_vga_memory);
 969         }
 970         ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM);
 971         ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT);
 972         ttm_bo_device_release(&rdev->mman.bdev);
 973         radeon_gart_fini(rdev);
 974         radeon_ttm_global_fini(rdev);
 975         rdev->mman.initialized = false;
 976         DRM_INFO("radeon: ttm finalized\n");
 977 }
 978
 979 /* this should only be called at bootup or when userspace
 980  * isn't running */
 981 void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
 982 {
 983         struct ttm_mem_type_manager *man;
 984
 985         if (!rdev->mman.initialized)
 986                 return;
 987
 988         man = &rdev->mman.bdev.man[TTM_PL_VRAM];
 989         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
 990         man->size = size >> PAGE_SHIFT;
 991 }
 992
 993 #ifdef DUMBBELL_WIP
 994 static struct vm_operations_struct radeon_ttm_vm_ops;
 995 static const struct vm_operations_struct *ttm_vm_ops = NULL;
 996
 997 static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
 998 {
 999         struct ttm_buffer_object *bo;
1000         struct radeon_device *rdev;
1001         int r;
1002
1003         bo = (struct ttm_buffer_object *)vma->vm_private_data;
1004         if (bo == NULL) {
1005                 return VM_FAULT_NOPAGE;
1006         }
1007         rdev = radeon_get_rdev(bo->bdev);
1008         down_read(&rdev->pm.mclk_lock);
1009         r = ttm_vm_ops->fault(vma, vmf);
1010         up_read(&rdev->pm.mclk_lock);
1011         return r;
1012 }
1013
1014 int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
1015 {
1016         struct drm_file *file_priv;
1017         struct radeon_device *rdev;
1018         int r;
1019
1020         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) {
1021                 return -EINVAL;
1022         }
1023
1024         file_priv = filp->private_data;
1025         rdev = file_priv->minor->dev->dev_private;
1026         if (rdev == NULL) {
1027                 return -EINVAL;
1028         }
1029         r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
1030         if (unlikely(r != 0)) {
1031                 return r;
1032         }
1033         if (unlikely(ttm_vm_ops == NULL)) {
1034                 ttm_vm_ops = vma->vm_ops;
1035                 radeon_ttm_vm_ops = *ttm_vm_ops;
1036                 radeon_ttm_vm_ops.fault = &radeon_ttm_fault;
1037         }
1038         vma->vm_ops = &radeon_ttm_vm_ops;
1039         return 0;
1040 }
1041 #endif /* DUMBBELL_WIP */
1042
1043 #if defined(CONFIG_DEBUG_FS)
1044
1045 static int radeon_mm_dump_table(struct seq_file *m, void *data)
1046 {
1047         struct drm_info_node *node = (struct drm_info_node *)m->private;
1048         unsigned ttm_pl = *(int *)node->info_ent->data;
1049         struct drm_device *dev = node->minor->dev;
1050         struct radeon_device *rdev = dev->dev_private;
1051         struct drm_mm *mm = (struct drm_mm *)rdev->mman.bdev.man[ttm_pl].priv;
1052         int ret;
1053         struct ttm_bo_global *glob = rdev->mman.bdev.glob;
1054
1055         spin_lock(&glob->lru_lock);
1056         ret = drm_mm_dump_table(m, mm);
1057         spin_unlock(&glob->lru_lock);
1058         return ret;
1059 }
1060
1061 static int ttm_pl_vram = TTM_PL_VRAM;
1062 static int ttm_pl_tt = TTM_PL_TT;
1063
1064 static struct drm_info_list radeon_ttm_debugfs_list[] = {
1065         {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram},
1066         {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt},
1067         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1068 #ifdef CONFIG_SWIOTLB
1069         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1070 #endif
1071 };
1072
1073 static int radeon_ttm_vram_open(struct inode *inode, struct file *filep)
1074 {
1075         struct radeon_device *rdev = inode->i_private;
1076         i_size_write(inode, rdev->mc.mc_vram_size);
1077         filep->private_data = inode->i_private;
1078         return 0;
1079 }
1080
1081 static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf,
1082                                     size_t size, loff_t *pos)
1083 {
1084         struct radeon_device *rdev = f->private_data;
1085         ssize_t result = 0;
1086         int r;
1087
1088         if (size & 0x3 || *pos & 0x3)
1089                 return -EINVAL;
1090
1091         while (size) {
1092                 unsigned long flags;
1093                 uint32_t value;
1094
1095                 if (*pos >= rdev->mc.mc_vram_size)
1096                         return result;
1097
1098                 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
1099                 WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000);
1100                 if (rdev->family >= CHIP_CEDAR)
1101                         WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31);
1102                 value = RREG32(RADEON_MM_DATA);
1103                 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
1104
1105                 r = put_user(value, (uint32_t *)buf);
1106                 if (r)
1107                         return r;
1108
1109                 result += 4;
1110                 buf += 4;
1111                 *pos += 4;
1112                 size -= 4;
1113         }
1114
1115         return result;
1116 }
1117
1118 static const struct file_operations radeon_ttm_vram_fops = {
1119         .owner = THIS_MODULE,
1120         .open = radeon_ttm_vram_open,
1121         .read = radeon_ttm_vram_read,
1122         .llseek = default_llseek
1123 };
1124
1125 static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep)
1126 {
1127         struct radeon_device *rdev = inode->i_private;
1128         i_size_write(inode, rdev->mc.gtt_size);
1129         filep->private_data = inode->i_private;
1130         return 0;
1131 }
1132
1133 static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf,
1134                                    size_t size, loff_t *pos)
1135 {
1136         struct radeon_device *rdev = f->private_data;
1137         ssize_t result = 0;
1138         int r;
1139
1140         while (size) {
1141                 loff_t p = *pos / PAGE_SIZE;
1142                 unsigned off = *pos & ~LINUX_PAGE_MASK;
1143                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1144                 struct page *page;
1145                 void *ptr;
1146
1147                 if (p >= rdev->gart.num_cpu_pages)
1148                         return result;
1149
1150                 page = rdev->gart.pages[p];
1151                 if (page) {
1152                         ptr = kmap(page);
1153                         ptr += off;
1154
1155                         r = copy_to_user(buf, ptr, cur_size);
1156                         kunmap(rdev->gart.pages[p]);
1157                 } else
1158                         r = clear_user(buf, cur_size);
1159
1160                 if (r)
1161                         return -EFAULT;
1162
1163                 result += cur_size;
1164                 buf += cur_size;
1165                 *pos += cur_size;
1166                 size -= cur_size;
1167         }
1168
1169         return result;
1170 }
1171
1172 static const struct file_operations radeon_ttm_gtt_fops = {
1173         .owner = THIS_MODULE,
1174         .open = radeon_ttm_gtt_open,
1175         .read = radeon_ttm_gtt_read,
1176         .llseek = default_llseek
1177 };
1178
1179 #endif
1180
1181 static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
1182 {
1183 #if defined(CONFIG_DEBUG_FS)
1184         unsigned count;
1185
1186         struct drm_minor *minor = rdev->ddev->primary;
1187         struct dentry *ent, *root = minor->debugfs_root;
1188
1189         ent = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, root,
1190                                   rdev, &radeon_ttm_vram_fops);
1191         if (IS_ERR(ent))
1192                 return PTR_ERR(ent);
1193         rdev->mman.vram = ent;
1194
1195         ent = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, root,
1196                                   rdev, &radeon_ttm_gtt_fops);
1197         if (IS_ERR(ent))
1198                 return PTR_ERR(ent);
1199         rdev->mman.gtt = ent;
1200
1201         count = ARRAY_SIZE(radeon_ttm_debugfs_list);
1202
1203 #ifdef CONFIG_SWIOTLB
1204         if (!swiotlb_nr_tbl())
1205                 --count;
1206 #endif
1207
1208         return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count);
1209 #else
1210
1211         return 0;
1212 #endif
1213 }
1214
1215 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev)
1216 {
1217 #if defined(CONFIG_DEBUG_FS)
1218
1219         debugfs_remove(rdev->mman.vram);
1220         rdev->mman.vram = NULL;
1221
1222         debugfs_remove(rdev->mman.gtt);
1223         rdev->mman.gtt = NULL;
1224 #endif
1225 }