1 /******************************************************************************
3 Copyright (c) 2001-2009, Intel Corporation
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7 modification, are permitted provided that the following conditions are met:
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32 ******************************************************************************/
36 * 82571EB Gigabit Ethernet Controller
37 * 82571EB Gigabit Ethernet Controller (Copper)
38 * 82571EB Gigabit Ethernet Controller (Fiber)
39 * 82571EB Dual Port Gigabit Mezzanine Adapter
40 * 82571EB Quad Port Gigabit Mezzanine Adapter
41 * 82571PT Gigabit PT Quad Port Server ExpressModule
42 * 82572EI Gigabit Ethernet Controller (Copper)
43 * 82572EI Gigabit Ethernet Controller (Fiber)
44 * 82572EI Gigabit Ethernet Controller
45 * 82573V Gigabit Ethernet Controller (Copper)
46 * 82573E Gigabit Ethernet Controller (Copper)
47 * 82573L Gigabit Ethernet Controller
48 * 82574L Gigabit Network Connection
49 * 82583V Gigabit Network Connection
52 #include "e1000_api.h"
54 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw);
55 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw);
56 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw);
57 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw);
58 static void e1000_release_nvm_82571(struct e1000_hw *hw);
59 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
60 u16 words, u16 *data);
61 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
62 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
63 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw);
64 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
66 static s32 e1000_reset_hw_82571(struct e1000_hw *hw);
67 static s32 e1000_init_hw_82571(struct e1000_hw *hw);
68 static void e1000_clear_vfta_82571(struct e1000_hw *hw);
69 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
70 static s32 e1000_led_on_82574(struct e1000_hw *hw);
71 static s32 e1000_setup_link_82571(struct e1000_hw *hw);
72 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
73 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
74 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
75 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
76 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
77 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw);
78 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
79 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
80 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
81 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw);
82 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
83 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
84 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
85 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
86 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
87 u16 words, u16 *data);
88 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw);
89 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
92 * e1000_init_phy_params_82571 - Init PHY func ptrs.
93 * @hw: pointer to the HW structure
95 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
97 struct e1000_phy_info *phy = &hw->phy;
98 s32 ret_val = E1000_SUCCESS;
100 DEBUGFUNC("e1000_init_phy_params_82571");
102 if (hw->phy.media_type != e1000_media_type_copper) {
103 phy->type = e1000_phy_none;
108 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
109 phy->reset_delay_us = 100;
111 phy->ops.check_reset_block = e1000_check_reset_block_generic;
112 phy->ops.reset = e1000_phy_hw_reset_generic;
113 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571;
114 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
115 phy->ops.power_up = e1000_power_up_phy_copper;
116 phy->ops.power_down = e1000_power_down_phy_copper_82571;
118 switch (hw->mac.type) {
121 phy->type = e1000_phy_igp_2;
122 phy->ops.get_cfg_done = e1000_get_cfg_done_82571;
123 phy->ops.get_info = e1000_get_phy_info_igp;
124 phy->ops.check_polarity = e1000_check_polarity_igp;
125 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
126 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
127 phy->ops.read_reg = e1000_read_phy_reg_igp;
128 phy->ops.write_reg = e1000_write_phy_reg_igp;
129 phy->ops.acquire = e1000_get_hw_semaphore_82571;
130 phy->ops.release = e1000_put_hw_semaphore_82571;
132 /* This uses above function pointers */
133 ret_val = e1000_get_phy_id_82571(hw);
136 if (phy->id != IGP01E1000_I_PHY_ID) {
137 ret_val = -E1000_ERR_PHY;
138 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
143 phy->type = e1000_phy_m88;
144 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
145 phy->ops.get_info = e1000_get_phy_info_m88;
146 phy->ops.check_polarity = e1000_check_polarity_m88;
147 phy->ops.commit = e1000_phy_sw_reset_generic;
148 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
149 phy->ops.get_cable_length = e1000_get_cable_length_m88;
150 phy->ops.read_reg = e1000_read_phy_reg_m88;
151 phy->ops.write_reg = e1000_write_phy_reg_m88;
152 phy->ops.acquire = e1000_get_hw_semaphore_82571;
153 phy->ops.release = e1000_put_hw_semaphore_82571;
155 /* This uses above function pointers */
156 ret_val = e1000_get_phy_id_82571(hw);
159 if (phy->id != M88E1111_I_PHY_ID) {
160 ret_val = -E1000_ERR_PHY;
161 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
167 phy->type = e1000_phy_bm;
168 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
169 phy->ops.get_info = e1000_get_phy_info_m88;
170 phy->ops.check_polarity = e1000_check_polarity_m88;
171 phy->ops.commit = e1000_phy_sw_reset_generic;
172 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
173 phy->ops.get_cable_length = e1000_get_cable_length_m88;
174 phy->ops.read_reg = e1000_read_phy_reg_bm2;
175 phy->ops.write_reg = e1000_write_phy_reg_bm2;
176 phy->ops.acquire = e1000_get_hw_semaphore_82574;
177 phy->ops.release = e1000_put_hw_semaphore_82574;
179 /* This uses above function pointers */
180 ret_val = e1000_get_phy_id_82571(hw);
182 if (phy->id != BME1000_E_PHY_ID_R2) {
183 ret_val = -E1000_ERR_PHY;
184 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
189 ret_val = -E1000_ERR_PHY;
199 * e1000_init_nvm_params_82571 - Init NVM func ptrs.
200 * @hw: pointer to the HW structure
202 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
204 struct e1000_nvm_info *nvm = &hw->nvm;
205 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
208 DEBUGFUNC("e1000_init_nvm_params_82571");
210 nvm->opcode_bits = 8;
212 switch (nvm->override) {
213 case e1000_nvm_override_spi_large:
215 nvm->address_bits = 16;
217 case e1000_nvm_override_spi_small:
219 nvm->address_bits = 8;
222 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
223 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
227 switch (hw->mac.type) {
231 if (((eecd >> 15) & 0x3) == 0x3) {
232 nvm->type = e1000_nvm_flash_hw;
233 nvm->word_size = 2048;
235 * Autonomous Flash update bit must be cleared due
236 * to Flash update issue.
238 eecd &= ~E1000_EECD_AUPDEN;
239 E1000_WRITE_REG(hw, E1000_EECD, eecd);
244 nvm->type = e1000_nvm_eeprom_spi;
245 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
246 E1000_EECD_SIZE_EX_SHIFT);
248 * Added to a constant, "size" becomes the left-shift value
249 * for setting word_size.
251 size += NVM_WORD_SIZE_BASE_SHIFT;
253 /* EEPROM access above 16k is unsupported */
256 nvm->word_size = 1 << size;
260 /* Function Pointers */
261 switch (hw->mac.type) {
264 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
265 nvm->ops.release = e1000_put_hw_semaphore_82574;
268 nvm->ops.acquire = e1000_acquire_nvm_82571;
269 nvm->ops.release = e1000_release_nvm_82571;
272 nvm->ops.read = e1000_read_nvm_eerd;
273 nvm->ops.update = e1000_update_nvm_checksum_82571;
274 nvm->ops.validate = e1000_validate_nvm_checksum_82571;
275 nvm->ops.valid_led_default = e1000_valid_led_default_82571;
276 nvm->ops.write = e1000_write_nvm_82571;
278 return E1000_SUCCESS;
282 * e1000_init_mac_params_82571 - Init MAC func ptrs.
283 * @hw: pointer to the HW structure
285 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
287 struct e1000_mac_info *mac = &hw->mac;
290 bool force_clear_smbi = FALSE;
292 DEBUGFUNC("e1000_init_mac_params_82571");
294 /* Set media type and media-dependent function pointers */
295 switch (hw->device_id) {
296 case E1000_DEV_ID_82571EB_FIBER:
297 case E1000_DEV_ID_82572EI_FIBER:
298 case E1000_DEV_ID_82571EB_QUAD_FIBER:
299 hw->phy.media_type = e1000_media_type_fiber;
300 mac->ops.setup_physical_interface =
301 e1000_setup_fiber_serdes_link_82571;
302 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
303 mac->ops.get_link_up_info =
304 e1000_get_speed_and_duplex_fiber_serdes_generic;
306 case E1000_DEV_ID_82571EB_SERDES:
307 case E1000_DEV_ID_82571EB_SERDES_DUAL:
308 case E1000_DEV_ID_82571EB_SERDES_QUAD:
309 case E1000_DEV_ID_82572EI_SERDES:
310 hw->phy.media_type = e1000_media_type_internal_serdes;
311 mac->ops.setup_physical_interface =
312 e1000_setup_fiber_serdes_link_82571;
313 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
314 mac->ops.get_link_up_info =
315 e1000_get_speed_and_duplex_fiber_serdes_generic;
318 hw->phy.media_type = e1000_media_type_copper;
319 mac->ops.setup_physical_interface =
320 e1000_setup_copper_link_82571;
321 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
322 mac->ops.get_link_up_info =
323 e1000_get_speed_and_duplex_copper_generic;
327 /* Set mta register count */
328 mac->mta_reg_count = 128;
329 /* Set rar entry count */
330 mac->rar_entry_count = E1000_RAR_ENTRIES;
331 /* Set if part includes ASF firmware */
332 mac->asf_firmware_present = TRUE;
333 /* Adaptive IFS supported */
334 mac->adaptive_ifs = TRUE;
336 /* Function pointers */
338 /* bus type/speed/width */
339 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
341 mac->ops.reset_hw = e1000_reset_hw_82571;
342 /* hw initialization */
343 mac->ops.init_hw = e1000_init_hw_82571;
345 mac->ops.setup_link = e1000_setup_link_82571;
346 /* multicast address update */
347 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
349 mac->ops.write_vfta = e1000_write_vfta_generic;
351 mac->ops.clear_vfta = e1000_clear_vfta_82571;
352 /* read mac address */
353 mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
355 mac->ops.id_led_init = e1000_id_led_init_generic;
357 mac->ops.blink_led = e1000_blink_led_generic;
359 mac->ops.setup_led = e1000_setup_led_generic;
361 mac->ops.cleanup_led = e1000_cleanup_led_generic;
363 mac->ops.led_off = e1000_led_off_generic;
364 /* clear hardware counters */
365 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
367 /* MAC-specific function pointers */
368 switch (hw->mac.type) {
370 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
371 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
372 mac->ops.led_on = e1000_led_on_generic;
375 mac->has_fwsm = TRUE;
377 * ARC supported; valid only if manageability features are
380 mac->arc_subsystem_valid =
381 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
386 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
387 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
388 mac->ops.led_on = e1000_led_on_82574;
391 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
392 mac->ops.led_on = e1000_led_on_generic;
395 mac->has_fwsm = TRUE;
400 * Ensure that the inter-port SWSM.SMBI lock bit is clear before
401 * first NVM or PHY acess. This should be done for single-port
402 * devices, and for one port only on dual-port devices so that
403 * for those devices we can still use the SMBI lock to synchronize
404 * inter-port accesses to the PHY & NVM.
406 switch (hw->mac.type) {
409 swsm2 = E1000_READ_REG(hw, E1000_SWSM2);
411 if (!(swsm2 & E1000_SWSM2_LOCK)) {
412 /* Only do this for the first interface on this card */
413 E1000_WRITE_REG(hw, E1000_SWSM2,
414 swsm2 | E1000_SWSM2_LOCK);
415 force_clear_smbi = TRUE;
417 force_clear_smbi = FALSE;
420 force_clear_smbi = TRUE;
424 if (force_clear_smbi) {
425 /* Make sure SWSM.SMBI is clear */
426 swsm = E1000_READ_REG(hw, E1000_SWSM);
427 if (swsm & E1000_SWSM_SMBI) {
428 /* This bit should not be set on a first interface, and
429 * indicates that the bootagent or EFI code has
430 * improperly left this bit enabled
432 DEBUGOUT("Please update your 82571 Bootagent\n");
434 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI);
438 * Initialze device specific counter of SMBI acquisition
441 hw->dev_spec._82571.smb_counter = 0;
443 return E1000_SUCCESS;
447 * e1000_init_function_pointers_82571 - Init func ptrs.
448 * @hw: pointer to the HW structure
450 * Called to initialize all function pointers and parameters.
452 void e1000_init_function_pointers_82571(struct e1000_hw *hw)
454 DEBUGFUNC("e1000_init_function_pointers_82571");
456 hw->mac.ops.init_params = e1000_init_mac_params_82571;
457 hw->nvm.ops.init_params = e1000_init_nvm_params_82571;
458 hw->phy.ops.init_params = e1000_init_phy_params_82571;
462 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
463 * @hw: pointer to the HW structure
465 * Reads the PHY registers and stores the PHY ID and possibly the PHY
466 * revision in the hardware structure.
468 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
470 struct e1000_phy_info *phy = &hw->phy;
471 s32 ret_val = E1000_SUCCESS;
474 DEBUGFUNC("e1000_get_phy_id_82571");
476 switch (hw->mac.type) {
480 * The 82571 firmware may still be configuring the PHY.
481 * In this case, we cannot access the PHY until the
482 * configuration is done. So we explicitly set the
485 phy->id = IGP01E1000_I_PHY_ID;
488 ret_val = e1000_get_phy_id(hw);
492 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
496 phy->id = (u32)(phy_id << 16);
498 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
502 phy->id |= (u32)(phy_id);
503 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
506 ret_val = -E1000_ERR_PHY;
514 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
515 * @hw: pointer to the HW structure
517 * Acquire the HW semaphore to access the PHY or NVM
519 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
522 s32 ret_val = E1000_SUCCESS;
523 s32 sw_timeout = hw->nvm.word_size + 1;
524 s32 fw_timeout = hw->nvm.word_size + 1;
527 DEBUGFUNC("e1000_get_hw_semaphore_82571");
530 * If we have timedout 3 times on trying to acquire
531 * the inter-port SMBI semaphore, there is old code
532 * operating on the other port, and it is not
533 * releasing SMBI. Modify the number of times that
534 * we try for the semaphore to interwork with this
537 if (hw->dev_spec._82571.smb_counter > 2)
540 /* Get the SW semaphore */
541 while (i < sw_timeout) {
542 swsm = E1000_READ_REG(hw, E1000_SWSM);
543 if (!(swsm & E1000_SWSM_SMBI))
550 if (i == sw_timeout) {
551 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
552 hw->dev_spec._82571.smb_counter++;
554 /* Get the FW semaphore. */
555 for (i = 0; i < fw_timeout; i++) {
556 swsm = E1000_READ_REG(hw, E1000_SWSM);
557 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
559 /* Semaphore acquired if bit latched */
560 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
566 if (i == fw_timeout) {
567 /* Release semaphores */
568 e1000_put_hw_semaphore_82571(hw);
569 DEBUGOUT("Driver can't access the NVM\n");
570 ret_val = -E1000_ERR_NVM;
579 * e1000_put_hw_semaphore_82571 - Release hardware semaphore
580 * @hw: pointer to the HW structure
582 * Release hardware semaphore used to access the PHY or NVM
584 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
588 DEBUGFUNC("e1000_put_hw_semaphore_generic");
590 swsm = E1000_READ_REG(hw, E1000_SWSM);
592 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
594 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
598 * e1000_get_hw_semaphore_82573 - Acquire hardware semaphore
599 * @hw: pointer to the HW structure
601 * Acquire the HW semaphore during reset.
604 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
607 s32 ret_val = E1000_SUCCESS;
610 DEBUGFUNC("e1000_get_hw_semaphore_82573");
612 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
613 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
615 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
616 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
618 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
621 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
625 } while (i < MDIO_OWNERSHIP_TIMEOUT);
627 if (i == MDIO_OWNERSHIP_TIMEOUT) {
628 /* Release semaphores */
629 e1000_put_hw_semaphore_82573(hw);
630 DEBUGOUT("Driver can't access the PHY\n");
631 ret_val = -E1000_ERR_PHY;
640 * e1000_put_hw_semaphore_82573 - Release hardware semaphore
641 * @hw: pointer to the HW structure
643 * Release hardware semaphore used during reset.
646 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
650 DEBUGFUNC("e1000_put_hw_semaphore_82573");
652 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
653 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
654 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
658 * e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
659 * @hw: pointer to the HW structure
661 * Acquire the HW semaphore to access the PHY or NVM.
664 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
668 DEBUGFUNC("e1000_get_hw_semaphore_82574");
670 ret_val = e1000_get_hw_semaphore_82573(hw);
675 * e1000_put_hw_semaphore_82574 - Release hardware semaphore
676 * @hw: pointer to the HW structure
678 * Release hardware semaphore used to access the PHY or NVM
681 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
683 DEBUGFUNC("e1000_put_hw_semaphore_82574");
685 e1000_put_hw_semaphore_82573(hw);
689 * e1000_acquire_nvm_82571 - Request for access to the EEPROM
690 * @hw: pointer to the HW structure
692 * To gain access to the EEPROM, first we must obtain a hardware semaphore.
693 * Then for non-82573 hardware, set the EEPROM access request bit and wait
694 * for EEPROM access grant bit. If the access grant bit is not set, release
695 * hardware semaphore.
697 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
701 DEBUGFUNC("e1000_acquire_nvm_82571");
703 ret_val = e1000_get_hw_semaphore_82571(hw);
707 switch (hw->mac.type) {
711 ret_val = e1000_acquire_nvm_generic(hw);
716 e1000_put_hw_semaphore_82571(hw);
723 * e1000_release_nvm_82571 - Release exclusive access to EEPROM
724 * @hw: pointer to the HW structure
726 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
728 static void e1000_release_nvm_82571(struct e1000_hw *hw)
730 DEBUGFUNC("e1000_release_nvm_82571");
732 e1000_release_nvm_generic(hw);
733 e1000_put_hw_semaphore_82571(hw);
737 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
738 * @hw: pointer to the HW structure
739 * @offset: offset within the EEPROM to be written to
740 * @words: number of words to write
741 * @data: 16 bit word(s) to be written to the EEPROM
743 * For non-82573 silicon, write data to EEPROM at offset using SPI interface.
745 * If e1000_update_nvm_checksum is not called after this function, the
746 * EEPROM will most likely contain an invalid checksum.
748 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
751 s32 ret_val = E1000_SUCCESS;
753 DEBUGFUNC("e1000_write_nvm_82571");
755 switch (hw->mac.type) {
759 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
763 ret_val = e1000_write_nvm_spi(hw, offset, words, data);
766 ret_val = -E1000_ERR_NVM;
774 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum
775 * @hw: pointer to the HW structure
777 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
778 * up to the checksum. Then calculates the EEPROM checksum and writes the
779 * value to the EEPROM.
781 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
787 DEBUGFUNC("e1000_update_nvm_checksum_82571");
789 ret_val = e1000_update_nvm_checksum_generic(hw);
794 * If our nvm is an EEPROM, then we're done
795 * otherwise, commit the checksum to the flash NVM.
797 if (hw->nvm.type != e1000_nvm_flash_hw)
800 /* Check for pending operations. */
801 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
803 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0)
807 if (i == E1000_FLASH_UPDATES) {
808 ret_val = -E1000_ERR_NVM;
812 /* Reset the firmware if using STM opcode. */
813 if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) {
815 * The enabling of and the actual reset must be done
816 * in two write cycles.
818 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE);
819 E1000_WRITE_FLUSH(hw);
820 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET);
823 /* Commit the write to flash */
824 eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD;
825 E1000_WRITE_REG(hw, E1000_EECD, eecd);
827 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
829 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0)
833 if (i == E1000_FLASH_UPDATES) {
834 ret_val = -E1000_ERR_NVM;
843 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
844 * @hw: pointer to the HW structure
846 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
847 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
849 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
851 DEBUGFUNC("e1000_validate_nvm_checksum_82571");
853 if (hw->nvm.type == e1000_nvm_flash_hw)
854 e1000_fix_nvm_checksum_82571(hw);
856 return e1000_validate_nvm_checksum_generic(hw);
860 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
861 * @hw: pointer to the HW structure
862 * @offset: offset within the EEPROM to be written to
863 * @words: number of words to write
864 * @data: 16 bit word(s) to be written to the EEPROM
866 * After checking for invalid values, poll the EEPROM to ensure the previous
867 * command has completed before trying to write the next word. After write
868 * poll for completion.
870 * If e1000_update_nvm_checksum is not called after this function, the
871 * EEPROM will most likely contain an invalid checksum.
873 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
874 u16 words, u16 *data)
876 struct e1000_nvm_info *nvm = &hw->nvm;
880 DEBUGFUNC("e1000_write_nvm_eewr_82571");
883 * A check for invalid values: offset too large, too many words,
884 * and not enough words.
886 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
888 DEBUGOUT("nvm parameter(s) out of bounds\n");
889 ret_val = -E1000_ERR_NVM;
893 for (i = 0; i < words; i++) {
894 eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
895 ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
896 E1000_NVM_RW_REG_START;
898 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
902 E1000_WRITE_REG(hw, E1000_EEWR, eewr);
904 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
914 * e1000_get_cfg_done_82571 - Poll for configuration done
915 * @hw: pointer to the HW structure
917 * Reads the management control register for the config done bit to be set.
919 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
921 s32 timeout = PHY_CFG_TIMEOUT;
922 s32 ret_val = E1000_SUCCESS;
924 DEBUGFUNC("e1000_get_cfg_done_82571");
927 if (E1000_READ_REG(hw, E1000_EEMNGCTL) &
928 E1000_NVM_CFG_DONE_PORT_0)
934 DEBUGOUT("MNG configuration cycle has not completed.\n");
935 ret_val = -E1000_ERR_RESET;
944 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
945 * @hw: pointer to the HW structure
946 * @active: TRUE to enable LPLU, FALSE to disable
948 * Sets the LPLU D0 state according to the active flag. When activating LPLU
949 * this function also disables smart speed and vice versa. LPLU will not be
950 * activated unless the device autonegotiation advertisement meets standards
951 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function
952 * pointer entry point only called by PHY setup routines.
954 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
956 struct e1000_phy_info *phy = &hw->phy;
957 s32 ret_val = E1000_SUCCESS;
960 DEBUGFUNC("e1000_set_d0_lplu_state_82571");
962 if (!(phy->ops.read_reg))
965 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
970 data |= IGP02E1000_PM_D0_LPLU;
971 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
976 /* When LPLU is enabled, we should disable SmartSpeed */
977 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
979 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
980 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
985 data &= ~IGP02E1000_PM_D0_LPLU;
986 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
989 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
990 * during Dx states where the power conservation is most
991 * important. During driver activity we should enable
992 * SmartSpeed, so performance is maintained.
994 if (phy->smart_speed == e1000_smart_speed_on) {
995 ret_val = phy->ops.read_reg(hw,
996 IGP01E1000_PHY_PORT_CONFIG,
1001 data |= IGP01E1000_PSCFR_SMART_SPEED;
1002 ret_val = phy->ops.write_reg(hw,
1003 IGP01E1000_PHY_PORT_CONFIG,
1007 } else if (phy->smart_speed == e1000_smart_speed_off) {
1008 ret_val = phy->ops.read_reg(hw,
1009 IGP01E1000_PHY_PORT_CONFIG,
1014 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1015 ret_val = phy->ops.write_reg(hw,
1016 IGP01E1000_PHY_PORT_CONFIG,
1028 * e1000_reset_hw_82571 - Reset hardware
1029 * @hw: pointer to the HW structure
1031 * This resets the hardware into a known state.
1033 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
1035 u32 ctrl, ctrl_ext, icr;
1038 DEBUGFUNC("e1000_reset_hw_82571");
1041 * Prevent the PCI-E bus from sticking if there is no TLP connection
1042 * on the last TLP read/write transaction when MAC is reset.
1044 ret_val = e1000_disable_pcie_master_generic(hw);
1046 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1048 DEBUGOUT("Masking off all interrupts\n");
1049 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1051 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1052 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1053 E1000_WRITE_FLUSH(hw);
1058 * Must acquire the MDIO ownership before MAC reset.
1059 * Ownership defaults to firmware after a reset.
1061 switch (hw->mac.type) {
1063 ret_val = e1000_get_hw_semaphore_82573(hw);
1067 ret_val = e1000_get_hw_semaphore_82574(hw);
1073 DEBUGOUT("Cannot acquire MDIO ownership\n");
1075 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1077 DEBUGOUT("Issuing a global reset to MAC\n");
1078 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1080 /* Must release MDIO ownership and mutex after MAC reset. */
1081 switch (hw->mac.type) {
1084 e1000_put_hw_semaphore_82574(hw);
1090 if (hw->nvm.type == e1000_nvm_flash_hw) {
1092 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1093 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1094 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1095 E1000_WRITE_FLUSH(hw);
1098 ret_val = e1000_get_auto_rd_done_generic(hw);
1100 /* We don't want to continue accessing MAC registers. */
1104 * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1105 * Need to wait for Phy configuration completion before accessing
1109 switch (hw->mac.type) {
1119 /* Clear any pending interrupt events. */
1120 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1121 icr = E1000_READ_REG(hw, E1000_ICR);
1123 if (hw->mac.type == e1000_82571) {
1124 /* Install any alternate MAC address into RAR0 */
1125 ret_val = e1000_check_alt_mac_addr_generic(hw);
1129 e1000_set_laa_state_82571(hw, TRUE);
1132 /* Reinitialize the 82571 serdes link state machine */
1133 if (hw->phy.media_type == e1000_media_type_internal_serdes)
1134 hw->mac.serdes_link_state = e1000_serdes_link_down;
1141 * e1000_init_hw_82571 - Initialize hardware
1142 * @hw: pointer to the HW structure
1144 * This inits the hardware readying it for operation.
1146 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1148 struct e1000_mac_info *mac = &hw->mac;
1151 u16 i, rar_count = mac->rar_entry_count;
1153 DEBUGFUNC("e1000_init_hw_82571");
1155 e1000_initialize_hw_bits_82571(hw);
1157 /* Initialize identification LED */
1158 ret_val = mac->ops.id_led_init(hw);
1160 DEBUGOUT("Error initializing identification LED\n");
1161 /* This is not fatal and we should not stop init due to this */
1163 /* Disabling VLAN filtering */
1164 DEBUGOUT("Initializing the IEEE VLAN\n");
1165 mac->ops.clear_vfta(hw);
1167 /* Setup the receive address. */
1169 * If, however, a locally administered address was assigned to the
1170 * 82571, we must reserve a RAR for it to work around an issue where
1171 * resetting one port will reload the MAC on the other port.
1173 if (e1000_get_laa_state_82571(hw))
1175 e1000_init_rx_addrs_generic(hw, rar_count);
1177 /* Zero out the Multicast HASH table */
1178 DEBUGOUT("Zeroing the MTA\n");
1179 for (i = 0; i < mac->mta_reg_count; i++)
1180 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1182 /* Setup link and flow control */
1183 ret_val = mac->ops.setup_link(hw);
1185 /* Set the transmit descriptor write-back policy */
1186 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
1187 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1188 E1000_TXDCTL_FULL_TX_DESC_WB |
1189 E1000_TXDCTL_COUNT_DESC;
1190 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
1192 /* ...for both queues. */
1193 switch (mac->type) {
1195 e1000_enable_tx_pkt_filtering_generic(hw);
1199 reg_data = E1000_READ_REG(hw, E1000_GCR);
1200 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1201 E1000_WRITE_REG(hw, E1000_GCR, reg_data);
1204 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
1205 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1206 E1000_TXDCTL_FULL_TX_DESC_WB |
1207 E1000_TXDCTL_COUNT_DESC;
1208 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
1213 * Clear all of the statistics registers (clear on read). It is
1214 * important that we do this after we have tried to establish link
1215 * because the symbol error count will increment wildly if there
1218 e1000_clear_hw_cntrs_82571(hw);
1224 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1225 * @hw: pointer to the HW structure
1227 * Initializes required hardware-dependent bits needed for normal operation.
1229 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1233 DEBUGFUNC("e1000_initialize_hw_bits_82571");
1235 /* Transmit Descriptor Control 0 */
1236 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1238 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1240 /* Transmit Descriptor Control 1 */
1241 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1243 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1245 /* Transmit Arbitration Control 0 */
1246 reg = E1000_READ_REG(hw, E1000_TARC(0));
1247 reg &= ~(0xF << 27); /* 30:27 */
1248 switch (hw->mac.type) {
1251 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1256 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1258 /* Transmit Arbitration Control 1 */
1259 reg = E1000_READ_REG(hw, E1000_TARC(1));
1260 switch (hw->mac.type) {
1263 reg &= ~((1 << 29) | (1 << 30));
1264 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1265 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1269 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1275 /* Device Control */
1276 switch (hw->mac.type) {
1280 reg = E1000_READ_REG(hw, E1000_CTRL);
1282 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1288 /* Extended Device Control */
1289 switch (hw->mac.type) {
1293 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1296 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1302 if (hw->mac.type == e1000_82571) {
1303 reg = E1000_READ_REG(hw, E1000_PBA_ECC);
1304 reg |= E1000_PBA_ECC_CORR_EN;
1305 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg);
1309 * Workaround for hardware errata.
1310 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1312 if ((hw->mac.type == e1000_82571) ||
1313 (hw->mac.type == e1000_82572)) {
1314 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1315 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1316 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1319 /* PCI-Ex Control Registers */
1320 switch (hw->mac.type) {
1323 reg = E1000_READ_REG(hw, E1000_GCR);
1325 E1000_WRITE_REG(hw, E1000_GCR, reg);
1328 * Workaround for hardware errata.
1329 * apply workaround for hardware errata documented in errata
1330 * docs Fixes issue where some error prone or unreliable PCIe
1331 * completions are occurring, particularly with ASPM enabled.
1332 * Without fix, issue can cause tx timeouts.
1334 reg = E1000_READ_REG(hw, E1000_GCR2);
1336 E1000_WRITE_REG(hw, E1000_GCR2, reg);
1346 * e1000_clear_vfta_82571 - Clear VLAN filter table
1347 * @hw: pointer to the HW structure
1349 * Clears the register array which contains the VLAN filter table by
1350 * setting all the values to 0.
1352 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1356 u32 vfta_offset = 0;
1357 u32 vfta_bit_in_reg = 0;
1359 DEBUGFUNC("e1000_clear_vfta_82571");
1361 switch (hw->mac.type) {
1365 if (hw->mng_cookie.vlan_id != 0) {
1367 * The VFTA is a 4096b bit-field, each identifying
1368 * a single VLAN ID. The following operations
1369 * determine which 32b entry (i.e. offset) into the
1370 * array we want to set the VLAN ID (i.e. bit) of
1371 * the manageability unit.
1373 vfta_offset = (hw->mng_cookie.vlan_id >>
1374 E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK;
1375 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
1376 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1382 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1384 * If the offset we want to clear is the same offset of the
1385 * manageability VLAN ID, then clear all bits except that of
1386 * the manageability unit.
1388 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1389 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1390 E1000_WRITE_FLUSH(hw);
1395 * e1000_check_mng_mode_82574 - Check manageability is enabled
1396 * @hw: pointer to the HW structure
1398 * Reads the NVM Initialization Control Word 2 and returns TRUE
1399 * (>0) if any manageability is enabled, else FALSE (0).
1401 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1405 DEBUGFUNC("e1000_check_mng_mode_82574");
1407 hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1408 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1412 * e1000_led_on_82574 - Turn LED on
1413 * @hw: pointer to the HW structure
1417 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1422 DEBUGFUNC("e1000_led_on_82574");
1424 ctrl = hw->mac.ledctl_mode2;
1425 if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) {
1427 * If no link, then turn LED on by setting the invert bit
1428 * for each LED that's "on" (0x0E) in ledctl_mode2.
1430 for (i = 0; i < 4; i++)
1431 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1432 E1000_LEDCTL_MODE_LED_ON)
1433 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1435 E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl);
1437 return E1000_SUCCESS;
1441 * e1000_check_phy_82574 - check 82574 phy hung state
1442 * @hw: pointer to the HW structure
1444 * Returns whether phy is hung or not
1446 bool e1000_check_phy_82574(struct e1000_hw *hw)
1448 u16 status_1kbt = 0;
1449 u16 receive_errors = 0;
1450 bool phy_hung = FALSE;
1451 s32 ret_val = E1000_SUCCESS;
1453 DEBUGFUNC("e1000_check_phy_82574");
1456 * Read PHY Receive Error counter first, if its is max - all F's then
1457 * read the Base1000T status register If both are max then PHY is hung.
1459 ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,
1463 if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1464 ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,
1468 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1469 E1000_IDLE_ERROR_COUNT_MASK)
1478 * e1000_setup_link_82571 - Setup flow control and link settings
1479 * @hw: pointer to the HW structure
1481 * Determines which flow control settings to use, then configures flow
1482 * control. Calls the appropriate media-specific link configuration
1483 * function. Assuming the adapter has a valid link partner, a valid link
1484 * should be established. Assumes the hardware has previously been reset
1485 * and the transmitter and receiver are not enabled.
1487 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1489 DEBUGFUNC("e1000_setup_link_82571");
1492 * 82573 does not have a word in the NVM to determine
1493 * the default flow control setting, so we explicitly
1496 switch (hw->mac.type) {
1500 if (hw->fc.requested_mode == e1000_fc_default)
1501 hw->fc.requested_mode = e1000_fc_full;
1506 return e1000_setup_link_generic(hw);
1510 * e1000_setup_copper_link_82571 - Configure copper link settings
1511 * @hw: pointer to the HW structure
1513 * Configures the link for auto-neg or forced speed and duplex. Then we check
1514 * for link, once link is established calls to configure collision distance
1515 * and flow control are called.
1517 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1522 DEBUGFUNC("e1000_setup_copper_link_82571");
1524 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1525 ctrl |= E1000_CTRL_SLU;
1526 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1527 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1529 switch (hw->phy.type) {
1532 ret_val = e1000_copper_link_setup_m88(hw);
1534 case e1000_phy_igp_2:
1535 ret_val = e1000_copper_link_setup_igp(hw);
1538 ret_val = -E1000_ERR_PHY;
1545 ret_val = e1000_setup_copper_link_generic(hw);
1552 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1553 * @hw: pointer to the HW structure
1555 * Configures collision distance and flow control for fiber and serdes links.
1556 * Upon successful setup, poll for link.
1558 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1560 DEBUGFUNC("e1000_setup_fiber_serdes_link_82571");
1562 switch (hw->mac.type) {
1566 * If SerDes loopback mode is entered, there is no form
1567 * of reset to take the adapter out of that mode. So we
1568 * have to explicitly take the adapter out of loopback
1569 * mode. This prevents drivers from twiddling their thumbs
1570 * if another tool failed to take it out of loopback mode.
1572 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1578 return e1000_setup_fiber_serdes_link_generic(hw);
1582 * e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1583 * @hw: pointer to the HW structure
1585 * Reports the link state as up or down.
1587 * If autonegotiation is supported by the link partner, the link state is
1588 * determined by the result of autonegotiation. This is the most likely case.
1589 * If autonegotiation is not supported by the link partner, and the link
1590 * has a valid signal, force the link up.
1592 * The link state is represented internally here by 4 states:
1595 * 2) autoneg_progress
1596 * 3) autoneg_complete (the link sucessfully autonegotiated)
1597 * 4) forced_up (the link has been forced up, it did not autonegotiate)
1600 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1602 struct e1000_mac_info *mac = &hw->mac;
1608 s32 ret_val = E1000_SUCCESS;
1610 DEBUGFUNC("e1000_check_for_serdes_link_82571");
1612 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1613 status = E1000_READ_REG(hw, E1000_STATUS);
1614 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1616 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1618 /* Receiver is synchronized with no invalid bits. */
1619 switch (mac->serdes_link_state) {
1620 case e1000_serdes_link_autoneg_complete:
1621 if (!(status & E1000_STATUS_LU)) {
1623 * We have lost link, retry autoneg before
1624 * reporting link failure
1626 mac->serdes_link_state =
1627 e1000_serdes_link_autoneg_progress;
1628 mac->serdes_has_link = FALSE;
1629 DEBUGOUT("AN_UP -> AN_PROG\n");
1631 mac->serdes_has_link = TRUE;
1635 case e1000_serdes_link_forced_up:
1637 * If we are receiving /C/ ordered sets, re-enable
1638 * auto-negotiation in the TXCW register and disable
1639 * forced link in the Device Control register in an
1640 * attempt to auto-negotiate with our link partner.
1641 * If the partner code word is null, stop forcing
1642 * and restart auto negotiation.
1644 if ((rxcw & E1000_RXCW_C) || !(rxcw & E1000_RXCW_CW)) {
1645 /* Enable autoneg, and unforce link up */
1646 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1647 E1000_WRITE_REG(hw, E1000_CTRL,
1648 (ctrl & ~E1000_CTRL_SLU));
1649 mac->serdes_link_state =
1650 e1000_serdes_link_autoneg_progress;
1651 mac->serdes_has_link = FALSE;
1652 DEBUGOUT("FORCED_UP -> AN_PROG\n");
1654 mac->serdes_has_link = TRUE;
1658 case e1000_serdes_link_autoneg_progress:
1659 if (rxcw & E1000_RXCW_C) {
1661 * We received /C/ ordered sets, meaning the
1662 * link partner has autonegotiated, and we can
1663 * trust the Link Up (LU) status bit.
1665 if (status & E1000_STATUS_LU) {
1666 mac->serdes_link_state =
1667 e1000_serdes_link_autoneg_complete;
1668 DEBUGOUT("AN_PROG -> AN_UP\n");
1669 mac->serdes_has_link = TRUE;
1671 /* Autoneg completed, but failed. */
1672 mac->serdes_link_state =
1673 e1000_serdes_link_down;
1674 DEBUGOUT("AN_PROG -> DOWN\n");
1678 * The link partner did not autoneg.
1679 * Force link up and full duplex, and change
1682 E1000_WRITE_REG(hw, E1000_TXCW,
1683 (mac->txcw & ~E1000_TXCW_ANE));
1684 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1685 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1687 /* Configure Flow Control after link up. */
1689 e1000_config_fc_after_link_up_generic(hw);
1691 DEBUGOUT("Error config flow control\n");
1694 mac->serdes_link_state =
1695 e1000_serdes_link_forced_up;
1696 mac->serdes_has_link = TRUE;
1697 DEBUGOUT("AN_PROG -> FORCED_UP\n");
1701 case e1000_serdes_link_down:
1704 * The link was down but the receiver has now gained
1705 * valid sync, so lets see if we can bring the link
1708 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1709 E1000_WRITE_REG(hw, E1000_CTRL,
1710 (ctrl & ~E1000_CTRL_SLU));
1711 mac->serdes_link_state =
1712 e1000_serdes_link_autoneg_progress;
1713 mac->serdes_has_link = FALSE;
1714 DEBUGOUT("DOWN -> AN_PROG\n");
1718 if (!(rxcw & E1000_RXCW_SYNCH)) {
1719 mac->serdes_has_link = FALSE;
1720 mac->serdes_link_state = e1000_serdes_link_down;
1721 DEBUGOUT("ANYSTATE -> DOWN\n");
1724 * Check several times, if Sync and Config
1725 * both are consistently 1 then simply ignore
1726 * the Invalid bit and restart Autoneg
1728 for (i = 0; i < AN_RETRY_COUNT; i++) {
1730 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1731 if ((rxcw & E1000_RXCW_IV) &&
1732 !((rxcw & E1000_RXCW_SYNCH) &&
1733 (rxcw & E1000_RXCW_C))) {
1734 mac->serdes_has_link = FALSE;
1735 mac->serdes_link_state =
1736 e1000_serdes_link_down;
1737 DEBUGOUT("ANYSTATE -> DOWN\n");
1742 if (i == AN_RETRY_COUNT) {
1743 txcw = E1000_READ_REG(hw, E1000_TXCW);
1744 txcw |= E1000_TXCW_ANE;
1745 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1746 mac->serdes_link_state =
1747 e1000_serdes_link_autoneg_progress;
1748 mac->serdes_has_link = FALSE;
1749 DEBUGOUT("ANYSTATE -> AN_PROG\n");
1758 * e1000_valid_led_default_82571 - Verify a valid default LED config
1759 * @hw: pointer to the HW structure
1760 * @data: pointer to the NVM (EEPROM)
1762 * Read the EEPROM for the current default LED configuration. If the
1763 * LED configuration is not valid, set to a valid LED configuration.
1765 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1769 DEBUGFUNC("e1000_valid_led_default_82571");
1771 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1773 DEBUGOUT("NVM Read Error\n");
1777 switch (hw->mac.type) {
1781 if (*data == ID_LED_RESERVED_F746)
1782 *data = ID_LED_DEFAULT_82573;
1785 if (*data == ID_LED_RESERVED_0000 ||
1786 *data == ID_LED_RESERVED_FFFF)
1787 *data = ID_LED_DEFAULT;
1796 * e1000_get_laa_state_82571 - Get locally administered address state
1797 * @hw: pointer to the HW structure
1799 * Retrieve and return the current locally administered address state.
1801 bool e1000_get_laa_state_82571(struct e1000_hw *hw)
1803 DEBUGFUNC("e1000_get_laa_state_82571");
1805 if (hw->mac.type != e1000_82571)
1808 return hw->dev_spec._82571.laa_is_present;
1812 * e1000_set_laa_state_82571 - Set locally administered address state
1813 * @hw: pointer to the HW structure
1814 * @state: enable/disable locally administered address
1816 * Enable/Disable the current locally administered address state.
1818 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state)
1820 DEBUGFUNC("e1000_set_laa_state_82571");
1822 if (hw->mac.type != e1000_82571)
1825 hw->dev_spec._82571.laa_is_present = state;
1827 /* If workaround is activated... */
1830 * Hold a copy of the LAA in RAR[14] This is done so that
1831 * between the time RAR[0] gets clobbered and the time it
1832 * gets fixed, the actual LAA is in one of the RARs and no
1833 * incoming packets directed to this port are dropped.
1834 * Eventually the LAA will be in RAR[0] and RAR[14].
1836 e1000_rar_set_generic(hw, hw->mac.addr,
1837 hw->mac.rar_entry_count - 1);
1842 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1843 * @hw: pointer to the HW structure
1845 * Verifies that the EEPROM has completed the update. After updating the
1846 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If
1847 * the checksum fix is not implemented, we need to set the bit and update
1848 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,
1849 * we need to return bad checksum.
1851 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1853 struct e1000_nvm_info *nvm = &hw->nvm;
1854 s32 ret_val = E1000_SUCCESS;
1857 DEBUGFUNC("e1000_fix_nvm_checksum_82571");
1859 if (nvm->type != e1000_nvm_flash_hw)
1863 * Check bit 4 of word 10h. If it is 0, firmware is done updating
1864 * 10h-12h. Checksum may need to be fixed.
1866 ret_val = nvm->ops.read(hw, 0x10, 1, &data);
1870 if (!(data & 0x10)) {
1872 * Read 0x23 and check bit 15. This bit is a 1
1873 * when the checksum has already been fixed. If
1874 * the checksum is still wrong and this bit is a
1875 * 1, we need to return bad checksum. Otherwise,
1876 * we need to set this bit to a 1 and update the
1879 ret_val = nvm->ops.read(hw, 0x23, 1, &data);
1883 if (!(data & 0x8000)) {
1885 ret_val = nvm->ops.write(hw, 0x23, 1, &data);
1888 ret_val = nvm->ops.update(hw);
1898 * e1000_read_mac_addr_82571 - Read device MAC address
1899 * @hw: pointer to the HW structure
1901 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1903 s32 ret_val = E1000_SUCCESS;
1905 DEBUGFUNC("e1000_read_mac_addr_82571");
1907 if (hw->mac.type == e1000_82571) {
1909 * If there's an alternate MAC address place it in RAR0
1910 * so that it will override the Si installed default perm
1913 ret_val = e1000_check_alt_mac_addr_generic(hw);
1918 ret_val = e1000_read_mac_addr_generic(hw);
1925 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1926 * @hw: pointer to the HW structure
1928 * In the case of a PHY power down to save power, or to turn off link during a
1929 * driver unload, or wake on lan is not enabled, remove the link.
1931 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1933 struct e1000_phy_info *phy = &hw->phy;
1934 struct e1000_mac_info *mac = &hw->mac;
1936 if (!(phy->ops.check_reset_block))
1939 /* If the management interface is not enabled, then power down */
1940 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1941 e1000_power_down_phy_copper(hw);
1947 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1948 * @hw: pointer to the HW structure
1950 * Clears the hardware counters by reading the counter registers.
1952 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1954 DEBUGFUNC("e1000_clear_hw_cntrs_82571");
1956 e1000_clear_hw_cntrs_base_generic(hw);
1958 E1000_READ_REG(hw, E1000_PRC64);
1959 E1000_READ_REG(hw, E1000_PRC127);
1960 E1000_READ_REG(hw, E1000_PRC255);
1961 E1000_READ_REG(hw, E1000_PRC511);
1962 E1000_READ_REG(hw, E1000_PRC1023);
1963 E1000_READ_REG(hw, E1000_PRC1522);
1964 E1000_READ_REG(hw, E1000_PTC64);
1965 E1000_READ_REG(hw, E1000_PTC127);
1966 E1000_READ_REG(hw, E1000_PTC255);
1967 E1000_READ_REG(hw, E1000_PTC511);
1968 E1000_READ_REG(hw, E1000_PTC1023);
1969 E1000_READ_REG(hw, E1000_PTC1522);
1971 E1000_READ_REG(hw, E1000_ALGNERRC);
1972 E1000_READ_REG(hw, E1000_RXERRC);
1973 E1000_READ_REG(hw, E1000_TNCRS);
1974 E1000_READ_REG(hw, E1000_CEXTERR);
1975 E1000_READ_REG(hw, E1000_TSCTC);
1976 E1000_READ_REG(hw, E1000_TSCTFC);
1978 E1000_READ_REG(hw, E1000_MGTPRC);
1979 E1000_READ_REG(hw, E1000_MGTPDC);
1980 E1000_READ_REG(hw, E1000_MGTPTC);
1982 E1000_READ_REG(hw, E1000_IAC);
1983 E1000_READ_REG(hw, E1000_ICRXOC);
1985 E1000_READ_REG(hw, E1000_ICRXPTC);
1986 E1000_READ_REG(hw, E1000_ICRXATC);
1987 E1000_READ_REG(hw, E1000_ICTXPTC);
1988 E1000_READ_REG(hw, E1000_ICTXATC);
1989 E1000_READ_REG(hw, E1000_ICTXQEC);
1990 E1000_READ_REG(hw, E1000_ICTXQMTC);
1991 E1000_READ_REG(hw, E1000_ICRXDMTC);