2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
26 * Copyright (c) 2011 The FreeBSD Foundation
27 * All rights reserved.
29 * This software was developed by Konstantin Belousov under sponsorship from
30 * the FreeBSD Foundation.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
35 * 1. Redistributions of source code must retain the above copyright
36 * notice, this list of conditions and the following disclaimer.
37 * 2. Redistributions in binary form must reproduce the above copyright
38 * notice, this list of conditions and the following disclaimer in the
39 * documentation and/or other materials provided with the distribution.
41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
53 * $FreeBSD: head/sys/dev/drm2/i915/i915_gem.c 253497 2013-07-20 13:52:40Z kib $
56 #include <sys/resourcevar.h>
57 #include <sys/sfbuf.h>
60 #include <drm/i915_drm.h>
62 #include "intel_drv.h"
63 #include "intel_ringbuffer.h"
64 #include <linux/completion.h>
65 #include <linux/jiffies.h>
66 #include <linux/time.h>
68 static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
69 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
70 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
71 static int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
72 unsigned alignment, bool map_and_fenceable);
73 static int i915_gem_phys_pwrite(struct drm_device *dev,
74 struct drm_i915_gem_object *obj, uint64_t data_ptr, uint64_t offset,
75 uint64_t size, struct drm_file *file_priv);
76 static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj);
78 static void i915_gem_write_fence(struct drm_device *dev, int reg,
79 struct drm_i915_gem_object *obj);
80 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
81 struct drm_i915_fence_reg *fence,
84 static uint32_t i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size,
86 static uint32_t i915_gem_get_gtt_alignment(struct drm_device *dev,
87 uint32_t size, int tiling_mode);
88 static int i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
90 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj);
91 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
93 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
96 i915_gem_release_mmap(obj);
98 /* As we do not have an associated fence register, we will force
99 * a tiling change if we ever need to acquire one.
101 obj->tiling_changed = false;
102 obj->fence_reg = I915_FENCE_REG_NONE;
105 static int i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj);
106 static bool i915_gem_object_is_inactive(struct drm_i915_gem_object *obj);
107 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj);
108 static vm_page_t i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex);
109 static void i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
110 uint32_t flush_domains);
111 static void i915_gem_reset_fences(struct drm_device *dev);
112 static void i915_gem_lowmem(void *arg);
114 static int i915_gem_obj_io(struct drm_device *dev, uint32_t handle, uint64_t data_ptr,
115 uint64_t size, uint64_t offset, enum uio_rw rw, struct drm_file *file);
117 MALLOC_DEFINE(DRM_I915_GEM, "i915gem", "Allocations from i915 gem");
118 long i915_gem_wired_pages_cnt;
120 /* some bookkeeping */
121 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
125 dev_priv->mm.object_count++;
126 dev_priv->mm.object_memory += size;
129 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
133 dev_priv->mm.object_count--;
134 dev_priv->mm.object_memory -= size;
138 i915_gem_wait_for_error(struct drm_device *dev)
140 struct drm_i915_private *dev_priv = dev->dev_private;
141 struct completion *x = &dev_priv->error_completion;
144 if (!atomic_read(&dev_priv->mm.wedged))
148 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
149 * userspace. If it takes that long something really bad is going on and
150 * we should simply try to bail out and fail as gracefully as possible.
152 ret = wait_for_completion_interruptible_timeout(x, 10*hz);
154 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
156 } else if (ret < 0) {
160 if (atomic_read(&dev_priv->mm.wedged)) {
161 /* GPU is hung, bump the completion count to account for
162 * the token we just consumed so that we never hit zero and
163 * end up waiting upon a subsequent completion event that
166 spin_lock(&x->wait.lock);
168 spin_unlock(&x->wait.lock);
173 int i915_mutex_lock_interruptible(struct drm_device *dev)
177 ret = i915_gem_wait_for_error(dev);
181 ret = lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL);
185 WARN_ON(i915_verify_lists(dev));
190 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
192 return (obj->gtt_space && !obj->active && obj->pin_count == 0);
196 i915_gem_init_ioctl(struct drm_device *dev, void *data,
197 struct drm_file *file)
199 struct drm_i915_gem_init *args;
200 drm_i915_private_t *dev_priv;
202 dev_priv = dev->dev_private;
205 if (args->gtt_start >= args->gtt_end ||
206 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
210 * XXXKIB. The second-time initialization should be guarded
213 lockmgr(&dev->dev_lock, LK_EXCLUSIVE|LK_RETRY|LK_CANRECURSE);
214 i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end);
215 lockmgr(&dev->dev_lock, LK_RELEASE);
221 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
222 struct drm_file *file)
224 struct drm_i915_private *dev_priv;
225 struct drm_i915_gem_get_aperture *args;
226 struct drm_i915_gem_object *obj;
229 dev_priv = dev->dev_private;
234 list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
235 pinned += obj->gtt_space->size;
238 args->aper_size = dev_priv->mm.gtt_total;
239 args->aper_available_size = args->aper_size - pinned;
245 i915_gem_create(struct drm_file *file, struct drm_device *dev, uint64_t size,
248 struct drm_i915_gem_object *obj;
252 size = roundup(size, PAGE_SIZE);
256 obj = i915_gem_alloc_object(dev, size);
261 ret = drm_gem_handle_create(file, &obj->base, &handle);
263 drm_gem_object_release(&obj->base);
264 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
265 drm_free(obj, DRM_I915_GEM);
269 /* drop reference from allocate - handle holds it now */
270 drm_gem_object_unreference(&obj->base);
276 i915_gem_dumb_create(struct drm_file *file,
277 struct drm_device *dev,
278 struct drm_mode_create_dumb *args)
281 /* have to work out size/pitch and return them */
282 args->pitch = roundup2(args->width * ((args->bpp + 7) / 8), 64);
283 args->size = args->pitch * args->height;
284 return (i915_gem_create(file, dev, args->size, &args->handle));
287 int i915_gem_dumb_destroy(struct drm_file *file,
288 struct drm_device *dev,
292 return (drm_gem_handle_delete(file, handle));
296 * Creates a new mm object and returns a handle to it.
299 i915_gem_create_ioctl(struct drm_device *dev, void *data,
300 struct drm_file *file)
302 struct drm_i915_gem_create *args = data;
304 return (i915_gem_create(file, dev, args->size, &args->handle));
307 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
309 drm_i915_private_t *dev_priv;
311 dev_priv = obj->base.dev->dev_private;
312 return (dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
313 obj->tiling_mode != I915_TILING_NONE);
317 * Reads data from the object referenced by handle.
319 * On error, the contents of *data are undefined.
322 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
323 struct drm_file *file)
325 struct drm_i915_gem_pread *args;
328 return (i915_gem_obj_io(dev, args->handle, args->data_ptr, args->size,
329 args->offset, UIO_READ, file));
333 * Writes data to the object referenced by handle.
335 * On error, the contents of the buffer that were to be modified are undefined.
338 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
339 struct drm_file *file)
341 struct drm_i915_gem_pwrite *args;
344 return (i915_gem_obj_io(dev, args->handle, args->data_ptr, args->size,
345 args->offset, UIO_WRITE, file));
349 i915_gem_check_wedge(struct drm_i915_private *dev_priv,
352 if (atomic_read(&dev_priv->mm.wedged)) {
353 struct completion *x = &dev_priv->error_completion;
354 bool recovery_complete;
356 /* Give the error handler a chance to run. */
357 spin_lock(&x->wait.lock);
358 recovery_complete = x->done > 0;
359 spin_unlock(&x->wait.lock);
361 /* Non-interruptible callers can't handle -EAGAIN, hence return
362 * -EIO unconditionally for these. */
366 /* Recovery complete, but still wedged means reset failure. */
367 if (recovery_complete)
377 * Compare seqno against outstanding lazy request. Emit a request if they are
381 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
385 DRM_LOCK_ASSERT(ring->dev);
388 if (seqno == ring->outstanding_lazy_request)
389 ret = i915_add_request(ring, NULL, NULL);
395 * __wait_seqno - wait until execution of seqno has finished
396 * @ring: the ring expected to report seqno
398 * @interruptible: do an interruptible wait (normally yes)
399 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
401 * Returns 0 if the seqno was found within the alloted time. Else returns the
402 * errno with remaining time filled in timeout argument.
404 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
405 bool interruptible, struct timespec *timeout)
407 drm_i915_private_t *dev_priv = ring->dev->dev_private;
408 struct timespec before, now, wait_time={1,0};
409 unsigned long timeout_jiffies;
411 bool wait_forever = true;
414 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
417 if (timeout != NULL) {
418 wait_time = *timeout;
419 wait_forever = false;
422 timeout_jiffies = timespec_to_jiffies(&wait_time);
424 if (WARN_ON(!ring->irq_get(ring)))
427 /* Record current time in case interrupted by signal, or wedged * */
428 getrawmonotonic(&before);
431 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
432 atomic_read(&dev_priv->mm.wedged))
435 end = wait_event_interruptible_timeout(ring->irq_queue,
439 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
442 ret = i915_gem_check_wedge(dev_priv, interruptible);
445 } while (end == 0 && wait_forever);
447 getrawmonotonic(&now);
453 struct timespec sleep_time = timespec_sub(now, before);
454 *timeout = timespec_sub(*timeout, sleep_time);
459 case -EAGAIN: /* Wedged */
460 case -ERESTARTSYS: /* Signal */
462 case 0: /* Timeout */
464 set_normalized_timespec(timeout, 0, 0);
465 return -ETIMEDOUT; /* -ETIME on Linux */
466 default: /* Completed */
467 WARN_ON(end < 0); /* We're not aware of other errors */
473 * Waits for a sequence number to be signaled, and cleans up the
474 * request and object lists appropriately for that event.
477 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
479 drm_i915_private_t *dev_priv = ring->dev->dev_private;
484 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
488 ret = i915_gem_check_olr(ring, seqno);
492 ret = __wait_seqno(ring, seqno, dev_priv->mm.interruptible, NULL);
498 * Ensures that all rendering to the object has completed and the object is
499 * safe to unbind from the GTT or access from the CPU.
501 static __must_check int
502 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
508 /* This function only exists to support waiting for existing rendering,
509 * not for emitting required flushes.
511 BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0);
513 /* If there is rendering queued on the buffer being evicted, wait for
517 seqno = obj->last_write_seqno;
519 seqno = obj->last_read_seqno;
523 ret = i915_wait_seqno(obj->ring, seqno);
527 /* Manually manage the write flush as we may have not yet retired
530 if (obj->last_write_seqno &&
531 i915_seqno_passed(seqno, obj->last_write_seqno)) {
532 obj->last_write_seqno = 0;
533 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
536 i915_gem_retire_requests_ring(obj->ring);
541 * Ensures that an object will eventually get non-busy by flushing any required
542 * write domains, emitting any outstanding lazy request and retiring and
543 * completed requests.
546 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
551 ret = i915_gem_object_flush_gpu_write_domain(obj);
555 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
559 i915_gem_retire_requests_ring(obj->ring);
566 * Called when user space prepares to use an object with the CPU, either
567 * through the mmap ioctl's mapping or a GTT mapping.
570 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
571 struct drm_file *file)
573 struct drm_i915_gem_set_domain *args;
574 struct drm_i915_gem_object *obj;
575 uint32_t read_domains;
576 uint32_t write_domain;
580 read_domains = args->read_domains;
581 write_domain = args->write_domain;
583 if ((write_domain & I915_GEM_GPU_DOMAINS) != 0 ||
584 (read_domains & I915_GEM_GPU_DOMAINS) != 0 ||
585 (write_domain != 0 && read_domains != write_domain))
588 ret = i915_mutex_lock_interruptible(dev);
592 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
593 if (&obj->base == NULL) {
598 if ((read_domains & I915_GEM_DOMAIN_GTT) != 0) {
599 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
603 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
605 drm_gem_object_unreference(&obj->base);
612 * Called when user space has done writes to this buffer
615 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
616 struct drm_file *file)
618 struct drm_i915_gem_sw_finish *args = data;
619 struct drm_i915_gem_object *obj;
622 ret = i915_mutex_lock_interruptible(dev);
625 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
626 if (&obj->base == NULL) {
630 if (obj->pin_count != 0)
631 i915_gem_object_flush_cpu_write_domain(obj);
632 drm_gem_object_unreference(&obj->base);
639 * Maps the contents of an object, returning the address it is mapped
642 * While the mapping holds a reference on the contents of the object, it doesn't
643 * imply a ref on the object itself.
646 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
647 struct drm_file *file)
649 struct drm_i915_gem_mmap *args;
650 struct drm_gem_object *obj;
659 obj = drm_gem_object_lookup(dev, file, args->handle);
666 map = &p->p_vmspace->vm_map;
667 size = round_page(args->size);
669 if (map->size + size > p->p_rlimit[RLIMIT_VMEM].rlim_cur) {
677 vm_object_hold(obj->vm_obj);
678 vm_object_reference_locked(obj->vm_obj);
679 vm_object_drop(obj->vm_obj);
681 rv = vm_map_find(map, obj->vm_obj, args->offset, &addr, args->size,
682 PAGE_SIZE, /* align */
684 VM_MAPTYPE_NORMAL, /* maptype */
685 VM_PROT_READ | VM_PROT_WRITE, /* prot */
686 VM_PROT_READ | VM_PROT_WRITE, /* max */
687 MAP_SHARED /* cow */);
688 if (rv != KERN_SUCCESS) {
689 vm_object_deallocate(obj->vm_obj);
690 error = -vm_mmap_to_errno(rv);
692 args->addr_ptr = (uint64_t)addr;
696 drm_gem_object_unreference(obj);
701 * i915_gem_release_mmap - remove physical page mappings
702 * @obj: obj in question
704 * Preserve the reservation of the mmapping with the DRM core code, but
705 * relinquish ownership of the pages back to the system.
707 * It is vital that we remove the page mapping if we have mapped a tiled
708 * object through the GTT and then lose the fence register due to
709 * resource pressure. Similarly if the object has been moved out of the
710 * aperture, than pages mapped into userspace must be revoked. Removing the
711 * mapping will then trigger a page fault on the next user access, allowing
712 * fixup by i915_gem_fault().
715 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
721 if (!obj->fault_mappable)
724 devobj = cdev_pager_lookup(obj);
725 if (devobj != NULL) {
726 page_count = OFF_TO_IDX(obj->base.size);
728 VM_OBJECT_LOCK(devobj);
729 for (i = 0; i < page_count; i++) {
730 m = vm_page_lookup_busy_wait(devobj, i, TRUE, "915unm");
733 cdev_pager_free_page(devobj, m);
735 VM_OBJECT_UNLOCK(devobj);
736 vm_object_deallocate(devobj);
739 obj->fault_mappable = false;
743 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
747 if (INTEL_INFO(dev)->gen >= 4 ||
748 tiling_mode == I915_TILING_NONE)
751 /* Previous chips need a power-of-two fence region when tiling */
752 if (INTEL_INFO(dev)->gen == 3)
753 gtt_size = 1024*1024;
757 while (gtt_size < size)
764 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
765 * @obj: object to check
767 * Return the required GTT alignment for an object, taking into account
768 * potential fence register mapping.
771 i915_gem_get_gtt_alignment(struct drm_device *dev,
777 * Minimum alignment is 4k (GTT page size), but might be greater
778 * if a fence register is needed for the object.
780 if (INTEL_INFO(dev)->gen >= 4 ||
781 tiling_mode == I915_TILING_NONE)
785 * Previous chips need to be aligned to the size of the smallest
786 * fence register that can contain the object.
788 return (i915_gem_get_gtt_size(dev, size, tiling_mode));
792 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
795 * @size: size of the object
796 * @tiling_mode: tiling mode of the object
798 * Return the required GTT alignment for an object, only taking into account
799 * unfenced tiled surface requirements.
802 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
807 if (tiling_mode == I915_TILING_NONE)
811 * Minimum alignment is 4k (GTT page size) for sane hw.
813 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev))
817 * Previous hardware however needs to be aligned to a power-of-two
818 * tile height. The simplest method for determining this is to reuse
819 * the power-of-tile object size.
821 return (i915_gem_get_gtt_size(dev, size, tiling_mode));
825 i915_gem_mmap_gtt(struct drm_file *file,
826 struct drm_device *dev,
830 struct drm_i915_private *dev_priv;
831 struct drm_i915_gem_object *obj;
834 dev_priv = dev->dev_private;
836 ret = i915_mutex_lock_interruptible(dev);
840 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
841 if (&obj->base == NULL) {
846 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
851 if (obj->madv != I915_MADV_WILLNEED) {
852 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
857 ret = drm_gem_create_mmap_offset(&obj->base);
861 *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) |
864 drm_gem_object_unreference(&obj->base);
871 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
873 * @data: GTT mapping ioctl data
874 * @file: GEM object info
876 * Simply returns the fake offset to userspace so it can mmap it.
877 * The mmap call will end up in drm_gem_mmap(), which will set things
878 * up so we can get faults in the handler above.
880 * The fault handler will take care of binding the object into the GTT
881 * (since it may have been evicted to make room for something), allocating
882 * a fence register, and mapping the appropriate aperture address into
886 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
887 struct drm_file *file)
889 struct drm_i915_private *dev_priv;
890 struct drm_i915_gem_mmap_gtt *args = data;
892 dev_priv = dev->dev_private;
894 return (i915_gem_mmap_gtt(file, dev, args->handle, &args->offset));
897 /* Immediately discard the backing storage */
899 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
903 vm_obj = obj->base.vm_obj;
904 VM_OBJECT_LOCK(vm_obj);
905 vm_object_page_remove(vm_obj, 0, 0, false);
906 VM_OBJECT_UNLOCK(vm_obj);
907 obj->madv = __I915_MADV_PURGED;
911 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
913 return obj->madv == I915_MADV_DONTNEED;
916 static inline void vm_page_reference(vm_page_t m)
918 vm_page_flag_set(m, PG_REFERENCED);
922 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
927 BUG_ON(obj->madv == __I915_MADV_PURGED);
929 if (obj->tiling_mode != I915_TILING_NONE)
930 i915_gem_object_save_bit_17_swizzle(obj);
931 if (obj->madv == I915_MADV_DONTNEED)
933 page_count = obj->base.size / PAGE_SIZE;
934 VM_OBJECT_LOCK(obj->base.vm_obj);
935 #if GEM_PARANOID_CHECK_GTT
936 i915_gem_assert_pages_not_mapped(obj->base.dev, obj->pages, page_count);
938 for (i = 0; i < page_count; i++) {
942 if (obj->madv == I915_MADV_WILLNEED)
943 vm_page_reference(m);
944 vm_page_busy_wait(obj->pages[i], FALSE, "i915gem");
945 vm_page_unwire(obj->pages[i], 1);
946 vm_page_wakeup(obj->pages[i]);
947 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
949 VM_OBJECT_UNLOCK(obj->base.vm_obj);
951 drm_free(obj->pages, DRM_I915_GEM);
956 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
959 struct drm_device *dev;
962 int page_count, i, j;
965 KASSERT(obj->pages == NULL, ("Obj already has pages"));
966 page_count = obj->base.size / PAGE_SIZE;
967 obj->pages = kmalloc(page_count * sizeof(vm_page_t), DRM_I915_GEM,
969 vm_obj = obj->base.vm_obj;
970 VM_OBJECT_LOCK(vm_obj);
971 for (i = 0; i < page_count; i++) {
972 if ((obj->pages[i] = i915_gem_wire_page(vm_obj, i)) == NULL)
975 VM_OBJECT_UNLOCK(vm_obj);
976 if (i915_gem_object_needs_bit17_swizzle(obj))
977 i915_gem_object_do_bit_17_swizzle(obj);
981 for (j = 0; j < i; j++) {
983 vm_page_busy_wait(m, FALSE, "i915gem");
984 vm_page_unwire(m, 0);
986 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
988 VM_OBJECT_UNLOCK(vm_obj);
989 drm_free(obj->pages, DRM_I915_GEM);
995 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
996 struct intel_ring_buffer *ring,
999 struct drm_device *dev = obj->base.dev;
1000 struct drm_i915_private *dev_priv = dev->dev_private;
1002 BUG_ON(ring == NULL);
1005 /* Add a reference if we're newly entering the active list. */
1007 drm_gem_object_reference(&obj->base);
1011 /* Move from whatever list we were on to the tail of execution. */
1012 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1013 list_move_tail(&obj->ring_list, &ring->active_list);
1015 obj->last_read_seqno = seqno;
1017 if (obj->fenced_gpu_access) {
1018 obj->last_fenced_seqno = seqno;
1020 /* Bump MRU to take account of the delayed flush */
1021 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1022 struct drm_i915_fence_reg *reg;
1024 reg = &dev_priv->fence_regs[obj->fence_reg];
1025 list_move_tail(®->lru_list,
1026 &dev_priv->mm.fence_list);
1032 i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
1034 list_del_init(&obj->ring_list);
1035 obj->last_read_seqno = 0;
1036 obj->last_write_seqno = 0;
1037 obj->last_fenced_seqno = 0;
1041 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1043 struct drm_device *dev = obj->base.dev;
1044 struct drm_i915_private *dev_priv = dev->dev_private;
1046 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1048 BUG_ON(!list_empty(&obj->gpu_write_list));
1049 BUG_ON(!obj->active);
1052 i915_gem_object_move_off_active(obj);
1053 obj->fenced_gpu_access = false;
1056 drm_gem_object_unreference(&obj->base);
1058 WARN_ON(i915_verify_lists(dev));
1062 i915_gem_get_seqno(struct drm_device *dev)
1064 drm_i915_private_t *dev_priv = dev->dev_private;
1065 u32 seqno = dev_priv->next_seqno;
1067 /* reserve 0 for non-seqno */
1068 if (++dev_priv->next_seqno == 0)
1069 dev_priv->next_seqno = 1;
1075 i915_add_request(struct intel_ring_buffer *ring,
1076 struct drm_file *file,
1077 struct drm_i915_gem_request *request)
1079 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1081 u32 request_ring_position;
1086 * Emit any outstanding flushes - execbuf can fail to emit the flush
1087 * after having emitted the batchbuffer command. Hence we need to fix
1088 * things up similar to emitting the lazy request. The difference here
1089 * is that the flush _must_ happen before the next request, no matter
1092 if (ring->gpu_caches_dirty) {
1093 ret = i915_gem_flush_ring(ring, 0, I915_GEM_GPU_DOMAINS);
1097 ring->gpu_caches_dirty = false;
1100 if (request == NULL) {
1101 request = kmalloc(sizeof(*request), DRM_I915_GEM,
1103 if (request == NULL)
1107 seqno = i915_gem_next_request_seqno(ring);
1109 /* Record the position of the start of the request so that
1110 * should we detect the updated seqno part-way through the
1111 * GPU processing the request, we never over-estimate the
1112 * position of the head.
1114 request_ring_position = intel_ring_get_tail(ring);
1116 ret = ring->add_request(ring, &seqno);
1118 kfree(request, DRM_I915_GEM);
1122 request->seqno = seqno;
1123 request->ring = ring;
1124 request->tail = request_ring_position;
1125 request->emitted_jiffies = jiffies;
1126 was_empty = list_empty(&ring->request_list);
1127 list_add_tail(&request->list, &ring->request_list);
1128 request->file_priv = NULL;
1131 struct drm_i915_file_private *file_priv = file->driver_priv;
1133 spin_lock(&file_priv->mm.lock);
1134 request->file_priv = file_priv;
1135 list_add_tail(&request->client_list,
1136 &file_priv->mm.request_list);
1137 spin_unlock(&file_priv->mm.lock);
1140 ring->outstanding_lazy_request = 0;
1142 if (!dev_priv->mm.suspended) {
1143 if (i915_enable_hangcheck) {
1144 mod_timer(&dev_priv->hangcheck_timer,
1145 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
1148 queue_delayed_work(dev_priv->wq,
1149 &dev_priv->mm.retire_work,
1150 round_jiffies_up_relative(hz));
1151 intel_mark_busy(dev_priv->dev);
1155 WARN_ON(!list_empty(&ring->gpu_write_list));
1161 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1163 struct drm_i915_file_private *file_priv = request->file_priv;
1168 DRM_LOCK_ASSERT(request->ring->dev);
1170 spin_lock(&file_priv->mm.lock);
1171 if (request->file_priv != NULL) {
1172 list_del(&request->client_list);
1173 request->file_priv = NULL;
1175 spin_unlock(&file_priv->mm.lock);
1179 i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1180 struct intel_ring_buffer *ring)
1183 if (ring->dev != NULL)
1184 DRM_LOCK_ASSERT(ring->dev);
1186 while (!list_empty(&ring->request_list)) {
1187 struct drm_i915_gem_request *request;
1189 request = list_first_entry(&ring->request_list,
1190 struct drm_i915_gem_request, list);
1192 list_del(&request->list);
1193 i915_gem_request_remove_from_client(request);
1194 drm_free(request, DRM_I915_GEM);
1197 while (!list_empty(&ring->active_list)) {
1198 struct drm_i915_gem_object *obj;
1200 obj = list_first_entry(&ring->active_list,
1201 struct drm_i915_gem_object, ring_list);
1203 obj->base.write_domain = 0;
1204 list_del_init(&obj->gpu_write_list);
1205 i915_gem_object_move_to_inactive(obj);
1209 static void i915_gem_reset_fences(struct drm_device *dev)
1211 struct drm_i915_private *dev_priv = dev->dev_private;
1214 for (i = 0; i < dev_priv->num_fence_regs; i++) {
1215 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1217 i915_gem_write_fence(dev, i, NULL);
1220 i915_gem_object_fence_lost(reg->obj);
1224 INIT_LIST_HEAD(®->lru_list);
1227 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
1230 void i915_gem_reset(struct drm_device *dev)
1232 struct drm_i915_private *dev_priv = dev->dev_private;
1233 struct drm_i915_gem_object *obj;
1236 for (i = 0; i < I915_NUM_RINGS; i++)
1237 i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]);
1239 /* Remove anything from the flushing lists. The GPU cache is likely
1240 * to be lost on reset along with the data, so simply move the
1241 * lost bo to the inactive list.
1243 while (!list_empty(&dev_priv->mm.flushing_list)) {
1244 obj = list_first_entry(&dev_priv->mm.flushing_list,
1245 struct drm_i915_gem_object,
1248 obj->base.write_domain = 0;
1249 list_del_init(&obj->gpu_write_list);
1250 i915_gem_object_move_to_inactive(obj);
1253 /* Move everything out of the GPU domains to ensure we do any
1254 * necessary invalidation upon reuse.
1256 list_for_each_entry(obj, &dev_priv->mm.inactive_list, mm_list) {
1257 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1260 /* The fence registers are invalidated so clear them out */
1261 i915_gem_reset_fences(dev);
1265 i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
1267 struct drm_device *dev = obj->base.dev;
1268 drm_i915_private_t *dev_priv = dev->dev_private;
1270 KASSERT(obj->active, ("Object not active"));
1271 list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
1273 i915_gem_object_move_off_active(obj);
1277 * This function clears the request list as sequence numbers are passed.
1280 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
1285 if (list_empty(&ring->request_list))
1288 WARN_ON(i915_verify_lists(ring->dev));
1290 seqno = ring->get_seqno(ring, true);
1292 for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
1293 if (seqno >= ring->sync_seqno[i])
1294 ring->sync_seqno[i] = 0;
1296 while (!list_empty(&ring->request_list)) {
1297 struct drm_i915_gem_request *request;
1299 request = list_first_entry(&ring->request_list,
1300 struct drm_i915_gem_request,
1303 if (!i915_seqno_passed(seqno, request->seqno))
1306 /* We know the GPU must have read the request to have
1307 * sent us the seqno + interrupt, so use the position
1308 * of tail of the request to update the last known position
1311 ring->last_retired_head = request->tail;
1313 list_del(&request->list);
1314 i915_gem_request_remove_from_client(request);
1315 kfree(request, DRM_I915_GEM);
1318 /* Move any buffers on the active list that are no longer referenced
1319 * by the ringbuffer to the flushing/inactive lists as appropriate.
1321 while (!list_empty(&ring->active_list)) {
1322 struct drm_i915_gem_object *obj;
1324 obj = list_first_entry(&ring->active_list,
1325 struct drm_i915_gem_object,
1328 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
1331 if (obj->base.write_domain != 0)
1332 i915_gem_object_move_to_flushing(obj);
1334 i915_gem_object_move_to_inactive(obj);
1337 if (unlikely(ring->trace_irq_seqno &&
1338 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1339 ring->irq_put(ring);
1340 ring->trace_irq_seqno = 0;
1346 i915_gem_retire_requests(struct drm_device *dev)
1348 drm_i915_private_t *dev_priv = dev->dev_private;
1349 struct drm_i915_gem_object *obj, *next;
1352 if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1353 list_for_each_entry_safe(obj, next,
1354 &dev_priv->mm.deferred_free_list, mm_list)
1355 i915_gem_free_object_tail(obj);
1358 for (i = 0; i < I915_NUM_RINGS; i++)
1359 i915_gem_retire_requests_ring(&dev_priv->ring[i]);
1363 i915_gem_retire_work_handler(struct work_struct *work)
1365 drm_i915_private_t *dev_priv;
1366 struct drm_device *dev;
1367 struct intel_ring_buffer *ring;
1371 dev_priv = container_of(work, drm_i915_private_t,
1372 mm.retire_work.work);
1373 dev = dev_priv->dev;
1375 /* Come back later if the device is busy... */
1376 if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_NOWAIT)) {
1377 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
1378 round_jiffies_up_relative(hz));
1382 i915_gem_retire_requests(dev);
1384 /* Send a periodic flush down the ring so we don't hold onto GEM
1385 * objects indefinitely.
1388 for_each_ring(ring, dev_priv, i) {
1389 if (ring->gpu_caches_dirty)
1390 i915_add_request(ring, NULL, NULL);
1392 idle &= list_empty(&ring->request_list);
1395 if (!dev_priv->mm.suspended && !idle)
1396 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
1397 round_jiffies_up_relative(hz));
1399 intel_mark_idle(dev);
1405 * i915_gem_object_sync - sync an object to a ring.
1407 * @obj: object which may be in use on another ring.
1408 * @to: ring we wish to use the object on. May be NULL.
1410 * This code is meant to abstract object synchronization with the GPU.
1411 * Calling with NULL implies synchronizing the object with the CPU
1412 * rather than a particular GPU ring.
1414 * Returns 0 if successful, else propagates up the lower layer error.
1417 i915_gem_object_sync(struct drm_i915_gem_object *obj,
1418 struct intel_ring_buffer *to)
1420 struct intel_ring_buffer *from = obj->ring;
1424 if (from == NULL || to == from)
1427 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
1428 return i915_gem_object_wait_rendering(obj, false);
1430 idx = intel_ring_sync_index(from, to);
1432 seqno = obj->last_read_seqno;
1433 if (seqno <= from->sync_seqno[idx])
1436 ret = i915_gem_check_olr(obj->ring, seqno);
1440 ret = to->sync_to(to, from, seqno);
1442 from->sync_seqno[idx] = seqno;
1447 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
1449 u32 old_write_domain, old_read_domains;
1451 /* Act a barrier for all accesses through the GTT */
1454 /* Force a pagefault for domain tracking on next user access */
1455 i915_gem_release_mmap(obj);
1457 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
1460 old_read_domains = obj->base.read_domains;
1461 old_write_domain = obj->base.write_domain;
1463 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
1464 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
1469 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
1471 drm_i915_private_t *dev_priv;
1474 dev_priv = obj->base.dev->dev_private;
1476 if (obj->gtt_space == NULL)
1478 if (obj->pin_count != 0) {
1479 DRM_ERROR("Attempting to unbind pinned buffer\n");
1483 ret = i915_gem_object_finish_gpu(obj);
1484 if (ret == -ERESTART || ret == -EINTR)
1487 i915_gem_object_finish_gtt(obj);
1490 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1491 if (ret == -ERESTART || ret == -EINTR)
1494 i915_gem_clflush_object(obj);
1495 obj->base.read_domains = obj->base.write_domain =
1496 I915_GEM_DOMAIN_CPU;
1499 ret = i915_gem_object_put_fence(obj);
1500 if (ret == -ERESTART)
1503 i915_gem_gtt_unbind_object(obj);
1504 if (obj->has_aliasing_ppgtt_mapping) {
1505 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
1506 obj->has_aliasing_ppgtt_mapping = 0;
1508 i915_gem_object_put_pages_gtt(obj);
1510 list_del_init(&obj->gtt_list);
1511 list_del_init(&obj->mm_list);
1512 obj->map_and_fenceable = true;
1514 drm_mm_put_block(obj->gtt_space);
1515 obj->gtt_space = NULL;
1516 obj->gtt_offset = 0;
1518 if (i915_gem_object_is_purgeable(obj))
1519 i915_gem_object_truncate(obj);
1524 int i915_gpu_idle(struct drm_device *dev)
1526 drm_i915_private_t *dev_priv = dev->dev_private;
1527 struct intel_ring_buffer *ring;
1530 /* Flush everything onto the inactive list. */
1531 for_each_ring(ring, dev_priv, i) {
1532 ret = intel_ring_idle(ring);
1540 static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
1541 struct drm_i915_gem_object *obj)
1543 drm_i915_private_t *dev_priv = dev->dev_private;
1547 u32 size = obj->gtt_space->size;
1549 val = (uint64_t)((obj->gtt_offset + size - 4096) &
1551 val |= obj->gtt_offset & 0xfffff000;
1552 val |= (uint64_t)((obj->stride / 128) - 1) <<
1553 SANDYBRIDGE_FENCE_PITCH_SHIFT;
1555 if (obj->tiling_mode == I915_TILING_Y)
1556 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
1557 val |= I965_FENCE_REG_VALID;
1561 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
1562 POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
1565 static void i965_write_fence_reg(struct drm_device *dev, int reg,
1566 struct drm_i915_gem_object *obj)
1568 drm_i915_private_t *dev_priv = dev->dev_private;
1572 u32 size = obj->gtt_space->size;
1574 val = (uint64_t)((obj->gtt_offset + size - 4096) &
1576 val |= obj->gtt_offset & 0xfffff000;
1577 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
1578 if (obj->tiling_mode == I915_TILING_Y)
1579 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
1580 val |= I965_FENCE_REG_VALID;
1584 I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
1585 POSTING_READ(FENCE_REG_965_0 + reg * 8);
1588 static void i915_write_fence_reg(struct drm_device *dev, int reg,
1589 struct drm_i915_gem_object *obj)
1591 drm_i915_private_t *dev_priv = dev->dev_private;
1595 u32 size = obj->gtt_space->size;
1599 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
1600 (size & -size) != size ||
1601 (obj->gtt_offset & (size - 1)),
1602 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
1603 obj->gtt_offset, obj->map_and_fenceable, size);
1605 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
1610 /* Note: pitch better be a power of two tile widths */
1611 pitch_val = obj->stride / tile_width;
1612 pitch_val = ffs(pitch_val) - 1;
1614 val = obj->gtt_offset;
1615 if (obj->tiling_mode == I915_TILING_Y)
1616 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
1617 val |= I915_FENCE_SIZE_BITS(size);
1618 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
1619 val |= I830_FENCE_REG_VALID;
1624 reg = FENCE_REG_830_0 + reg * 4;
1626 reg = FENCE_REG_945_8 + (reg - 8) * 4;
1628 I915_WRITE(reg, val);
1632 static void i830_write_fence_reg(struct drm_device *dev, int reg,
1633 struct drm_i915_gem_object *obj)
1635 drm_i915_private_t *dev_priv = dev->dev_private;
1639 u32 size = obj->gtt_space->size;
1642 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
1643 (size & -size) != size ||
1644 (obj->gtt_offset & (size - 1)),
1645 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
1646 obj->gtt_offset, size);
1648 pitch_val = obj->stride / 128;
1649 pitch_val = ffs(pitch_val) - 1;
1651 val = obj->gtt_offset;
1652 if (obj->tiling_mode == I915_TILING_Y)
1653 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
1654 val |= I830_FENCE_SIZE_BITS(size);
1655 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
1656 val |= I830_FENCE_REG_VALID;
1660 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
1661 POSTING_READ(FENCE_REG_830_0 + reg * 4);
1664 static void i915_gem_write_fence(struct drm_device *dev, int reg,
1665 struct drm_i915_gem_object *obj)
1667 switch (INTEL_INFO(dev)->gen) {
1669 case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
1671 case 4: i965_write_fence_reg(dev, reg, obj); break;
1672 case 3: i915_write_fence_reg(dev, reg, obj); break;
1673 case 2: i830_write_fence_reg(dev, reg, obj); break;
1678 static inline int fence_number(struct drm_i915_private *dev_priv,
1679 struct drm_i915_fence_reg *fence)
1681 return fence - dev_priv->fence_regs;
1684 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
1685 struct drm_i915_fence_reg *fence,
1688 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1689 int reg = fence_number(dev_priv, fence);
1691 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
1694 obj->fence_reg = reg;
1696 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
1698 obj->fence_reg = I915_FENCE_REG_NONE;
1700 list_del_init(&fence->lru_list);
1705 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
1709 if (obj->fenced_gpu_access) {
1710 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
1711 ret = i915_gem_flush_ring(obj->ring,
1712 0, obj->base.write_domain);
1717 obj->fenced_gpu_access = false;
1720 if (obj->last_fenced_seqno) {
1721 ret = i915_wait_seqno(obj->ring,
1722 obj->last_fenced_seqno);
1726 obj->last_fenced_seqno = 0;
1729 /* Ensure that all CPU reads are completed before installing a fence
1730 * and all writes before removing the fence.
1732 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
1739 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
1741 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1744 ret = i915_gem_object_flush_fence(obj);
1748 if (obj->fence_reg == I915_FENCE_REG_NONE)
1751 i915_gem_object_update_fence(obj,
1752 &dev_priv->fence_regs[obj->fence_reg],
1754 i915_gem_object_fence_lost(obj);
1759 static struct drm_i915_fence_reg *
1760 i915_find_fence_reg(struct drm_device *dev)
1762 struct drm_i915_private *dev_priv = dev->dev_private;
1763 struct drm_i915_fence_reg *reg, *avail;
1766 /* First try to find a free reg */
1768 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
1769 reg = &dev_priv->fence_regs[i];
1773 if (!reg->pin_count)
1780 /* None available, try to steal one or wait for a user to finish */
1781 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
1792 * i915_gem_object_get_fence - set up fencing for an object
1793 * @obj: object to map through a fence reg
1795 * When mapping objects through the GTT, userspace wants to be able to write
1796 * to them without having to worry about swizzling if the object is tiled.
1797 * This function walks the fence regs looking for a free one for @obj,
1798 * stealing one if it can't find any.
1800 * It then sets up the reg based on the object's properties: address, pitch
1801 * and tiling format.
1803 * For an untiled surface, this removes any existing fence.
1806 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
1808 struct drm_device *dev = obj->base.dev;
1809 struct drm_i915_private *dev_priv = dev->dev_private;
1810 bool enable = obj->tiling_mode != I915_TILING_NONE;
1811 struct drm_i915_fence_reg *reg;
1814 /* Have we updated the tiling parameters upon the object and so
1815 * will need to serialise the write to the associated fence register?
1817 if (obj->tiling_changed) {
1818 ret = i915_gem_object_flush_fence(obj);
1823 /* Just update our place in the LRU if our fence is getting reused. */
1824 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1825 reg = &dev_priv->fence_regs[obj->fence_reg];
1826 if (!obj->tiling_changed) {
1827 list_move_tail(®->lru_list,
1828 &dev_priv->mm.fence_list);
1831 } else if (enable) {
1832 reg = i915_find_fence_reg(dev);
1837 struct drm_i915_gem_object *old = reg->obj;
1839 ret = i915_gem_object_flush_fence(old);
1843 i915_gem_object_fence_lost(old);
1848 i915_gem_object_update_fence(obj, reg, enable);
1849 obj->tiling_changed = false;
1855 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
1856 unsigned alignment, bool map_and_fenceable)
1858 struct drm_device *dev;
1859 struct drm_i915_private *dev_priv;
1860 struct drm_mm_node *free_space;
1861 uint32_t size, fence_size, fence_alignment, unfenced_alignment;
1862 bool mappable, fenceable;
1865 dev = obj->base.dev;
1866 dev_priv = dev->dev_private;
1868 if (obj->madv != I915_MADV_WILLNEED) {
1869 DRM_ERROR("Attempting to bind a purgeable object\n");
1873 fence_size = i915_gem_get_gtt_size(dev, obj->base.size,
1875 fence_alignment = i915_gem_get_gtt_alignment(dev, obj->base.size,
1877 unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(dev,
1878 obj->base.size, obj->tiling_mode);
1880 alignment = map_and_fenceable ? fence_alignment :
1882 if (map_and_fenceable && (alignment & (fence_alignment - 1)) != 0) {
1883 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
1887 size = map_and_fenceable ? fence_size : obj->base.size;
1889 /* If the object is bigger than the entire aperture, reject it early
1890 * before evicting everything in a vain attempt to find space.
1892 if (obj->base.size > (map_and_fenceable ?
1893 dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
1895 "Attempting to bind an object larger than the aperture\n");
1900 if (map_and_fenceable)
1901 free_space = drm_mm_search_free_in_range(
1902 &dev_priv->mm.gtt_space, size, alignment, 0,
1903 dev_priv->mm.gtt_mappable_end, 0);
1905 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
1906 size, alignment, 0);
1907 if (free_space != NULL) {
1909 if (map_and_fenceable)
1910 obj->gtt_space = drm_mm_get_block_range_generic(
1911 free_space, size, alignment, color, 0,
1912 dev_priv->mm.gtt_mappable_end, 1);
1914 obj->gtt_space = drm_mm_get_block_generic(free_space,
1915 size, alignment, color, 1);
1917 if (obj->gtt_space == NULL) {
1918 ret = i915_gem_evict_something(dev, size, alignment,
1926 * NOTE: i915_gem_object_get_pages_gtt() cannot
1927 * return ENOMEM, since we used VM_ALLOC_RETRY.
1929 ret = i915_gem_object_get_pages_gtt(obj, 0);
1931 drm_mm_put_block(obj->gtt_space);
1932 obj->gtt_space = NULL;
1936 i915_gem_gtt_bind_object(obj, obj->cache_level);
1938 i915_gem_object_put_pages_gtt(obj);
1939 drm_mm_put_block(obj->gtt_space);
1940 obj->gtt_space = NULL;
1941 if (i915_gem_evict_everything(dev))
1946 list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
1947 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1949 obj->gtt_offset = obj->gtt_space->start;
1952 obj->gtt_space->size == fence_size &&
1953 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
1956 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
1957 obj->map_and_fenceable = mappable && fenceable;
1963 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
1966 /* If we don't have a page list set up, then we're not pinned
1967 * to GPU, and we can ignore the cache flush because it'll happen
1968 * again at bind time.
1970 if (obj->pages == NULL)
1973 /* If the GPU is snooping the contents of the CPU cache,
1974 * we do not need to manually clear the CPU cache lines. However,
1975 * the caches are only snooped when the render cache is
1976 * flushed/invalidated. As we always have to emit invalidations
1977 * and flushes when moving into and out of the RENDER domain, correct
1978 * snooping behaviour occurs naturally as the result of our domain
1981 if (obj->cache_level != I915_CACHE_NONE)
1984 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
1987 /** Flushes the GTT write domain for the object if it's dirty. */
1989 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
1991 uint32_t old_write_domain;
1993 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
1996 /* No actual flushing is required for the GTT write domain. Writes
1997 * to it immediately go to main memory as far as we know, so there's
1998 * no chipset flush. It also doesn't land in render cache.
2000 * However, we do have to enforce the order so that all writes through
2001 * the GTT land before any writes to the device, such as updates to
2006 old_write_domain = obj->base.write_domain;
2007 obj->base.write_domain = 0;
2010 /** Flushes the CPU write domain for the object if it's dirty. */
2012 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2014 uint32_t old_write_domain;
2016 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2019 i915_gem_clflush_object(obj);
2020 intel_gtt_chipset_flush();
2021 old_write_domain = obj->base.write_domain;
2022 obj->base.write_domain = 0;
2026 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
2029 if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
2031 return (i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain));
2035 * Moves a single object to the GTT read, and possibly write domain.
2037 * This function returns when the move is complete, including waiting on
2041 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2043 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2044 uint32_t old_write_domain, old_read_domains;
2047 /* Not valid to be called on unbound objects. */
2048 if (obj->gtt_space == NULL)
2051 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2054 ret = i915_gem_object_flush_gpu_write_domain(obj);
2058 ret = i915_gem_object_wait_rendering(obj, !write);
2062 i915_gem_object_flush_cpu_write_domain(obj);
2064 old_write_domain = obj->base.write_domain;
2065 old_read_domains = obj->base.read_domains;
2067 /* It should now be out of any other write domains, and we can update
2068 * the domain values for our changes.
2070 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2071 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2073 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
2074 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
2078 /* And bump the LRU for this access */
2079 if (i915_gem_object_is_inactive(obj))
2080 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2085 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2086 enum i915_cache_level cache_level)
2088 struct drm_device *dev = obj->base.dev;
2089 drm_i915_private_t *dev_priv = dev->dev_private;
2092 if (obj->cache_level == cache_level)
2095 if (obj->pin_count) {
2096 DRM_DEBUG("can not change the cache level of pinned objects\n");
2100 if (obj->gtt_space) {
2101 ret = i915_gem_object_finish_gpu(obj);
2105 i915_gem_object_finish_gtt(obj);
2107 /* Before SandyBridge, you could not use tiling or fence
2108 * registers with snooped memory, so relinquish any fences
2109 * currently pointing to our region in the aperture.
2111 if (INTEL_INFO(obj->base.dev)->gen < 6) {
2112 ret = i915_gem_object_put_fence(obj);
2117 if (obj->has_global_gtt_mapping)
2118 i915_gem_gtt_bind_object(obj, cache_level);
2119 if (obj->has_aliasing_ppgtt_mapping)
2120 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
2124 if (cache_level == I915_CACHE_NONE) {
2125 u32 old_read_domains, old_write_domain;
2127 /* If we're coming from LLC cached, then we haven't
2128 * actually been tracking whether the data is in the
2129 * CPU cache or not, since we only allow one bit set
2130 * in obj->write_domain and have been skipping the clflushes.
2131 * Just set it to the CPU cache for now.
2133 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
2134 ("obj %p in CPU write domain", obj));
2135 KASSERT((obj->base.read_domains & ~I915_GEM_DOMAIN_CPU) == 0,
2136 ("obj %p in CPU read domain", obj));
2138 old_read_domains = obj->base.read_domains;
2139 old_write_domain = obj->base.write_domain;
2141 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2142 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2146 obj->cache_level = cache_level;
2151 * Prepare buffer for display plane (scanout, cursors, etc).
2152 * Can be called from an uninterruptible phase (modesetting) and allows
2153 * any flushes to be pipelined (for pageflips).
2156 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2158 struct intel_ring_buffer *pipelined)
2160 u32 old_read_domains, old_write_domain;
2163 ret = i915_gem_object_flush_gpu_write_domain(obj);
2167 if (pipelined != obj->ring) {
2168 ret = i915_gem_object_sync(obj, pipelined);
2173 /* The display engine is not coherent with the LLC cache on gen6. As
2174 * a result, we make sure that the pinning that is about to occur is
2175 * done with uncached PTEs. This is lowest common denominator for all
2178 * However for gen6+, we could do better by using the GFDT bit instead
2179 * of uncaching, which would allow us to flush all the LLC-cached data
2180 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
2182 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
2186 /* As the user may map the buffer once pinned in the display plane
2187 * (e.g. libkms for the bootup splash), we have to ensure that we
2188 * always use map_and_fenceable for all scanout buffers.
2190 ret = i915_gem_object_pin(obj, alignment, true);
2194 i915_gem_object_flush_cpu_write_domain(obj);
2196 old_write_domain = obj->base.write_domain;
2197 old_read_domains = obj->base.read_domains;
2199 /* It should now be out of any other write domains, and we can update
2200 * the domain values for our changes.
2202 obj->base.write_domain = 0;
2203 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2209 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
2213 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
2216 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2217 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
2222 ret = i915_gem_object_wait_rendering(obj, false);
2226 /* Ensure that we invalidate the GPU's caches and TLBs. */
2227 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2232 * Moves a single object to the CPU read, and possibly write domain.
2234 * This function returns when the move is complete, including waiting on
2238 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
2240 uint32_t old_write_domain, old_read_domains;
2243 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
2246 ret = i915_gem_object_flush_gpu_write_domain(obj);
2250 ret = i915_gem_object_wait_rendering(obj, !write);
2254 i915_gem_object_flush_gtt_write_domain(obj);
2256 old_write_domain = obj->base.write_domain;
2257 old_read_domains = obj->base.read_domains;
2259 /* Flush the CPU cache if it's still invalid. */
2260 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2261 i915_gem_clflush_object(obj);
2263 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
2266 /* It should now be out of any other write domains, and we can update
2267 * the domain values for our changes.
2269 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2271 /* If we're writing through the CPU, then the GPU read domains will
2272 * need to be invalidated at next use.
2275 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2276 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2282 /* Throttle our rendering by waiting until the ring has completed our requests
2283 * emitted over 20 msec ago.
2285 * Note that if we were to use the current jiffies each time around the loop,
2286 * we wouldn't escape the function with any frames outstanding if the time to
2287 * render a frame was over 20ms.
2289 * This should get us reasonable parallelism between CPU and GPU but also
2290 * relatively low latency when blocking on a particular request to finish.
2293 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
2295 struct drm_i915_private *dev_priv = dev->dev_private;
2296 struct drm_i915_file_private *file_priv = file->driver_priv;
2297 unsigned long recent_enough = ticks - (20 * hz / 1000);
2298 struct drm_i915_gem_request *request;
2299 struct intel_ring_buffer *ring = NULL;
2303 if (atomic_read(&dev_priv->mm.wedged))
2306 spin_lock(&file_priv->mm.lock);
2307 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
2308 if (time_after_eq(request->emitted_jiffies, recent_enough))
2311 ring = request->ring;
2312 seqno = request->seqno;
2314 spin_unlock(&file_priv->mm.lock);
2319 ret = __wait_seqno(ring, seqno, true, NULL);
2322 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
2328 i915_gem_object_pin(struct drm_i915_gem_object *obj, uint32_t alignment,
2329 bool map_and_fenceable)
2331 struct drm_device *dev;
2332 struct drm_i915_private *dev_priv;
2335 dev = obj->base.dev;
2336 dev_priv = dev->dev_private;
2338 KASSERT(obj->pin_count != DRM_I915_GEM_OBJECT_MAX_PIN_COUNT,
2341 if (obj->gtt_space != NULL) {
2342 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
2343 (map_and_fenceable && !obj->map_and_fenceable)) {
2344 DRM_DEBUG("bo is already pinned with incorrect alignment:"
2345 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
2346 " obj->map_and_fenceable=%d\n",
2347 obj->gtt_offset, alignment,
2349 obj->map_and_fenceable);
2350 ret = i915_gem_object_unbind(obj);
2356 if (obj->gtt_space == NULL) {
2357 ret = i915_gem_object_bind_to_gtt(obj, alignment,
2363 if (obj->pin_count++ == 0 && !obj->active)
2364 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
2365 obj->pin_mappable |= map_and_fenceable;
2370 WARN_ON(i915_verify_lists(dev));
2376 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
2378 struct drm_device *dev;
2379 drm_i915_private_t *dev_priv;
2381 dev = obj->base.dev;
2382 dev_priv = dev->dev_private;
2387 WARN_ON(i915_verify_lists(dev));
2390 KASSERT(obj->pin_count != 0, ("zero pin count"));
2391 KASSERT(obj->gtt_space != NULL, ("No gtt mapping"));
2393 if (--obj->pin_count == 0) {
2395 list_move_tail(&obj->mm_list,
2396 &dev_priv->mm.inactive_list);
2397 obj->pin_mappable = false;
2402 WARN_ON(i915_verify_lists(dev));
2407 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2408 struct drm_file *file)
2410 struct drm_i915_gem_pin *args;
2411 struct drm_i915_gem_object *obj;
2412 struct drm_gem_object *gobj;
2417 ret = i915_mutex_lock_interruptible(dev);
2421 gobj = drm_gem_object_lookup(dev, file, args->handle);
2426 obj = to_intel_bo(gobj);
2428 if (obj->madv != I915_MADV_WILLNEED) {
2429 DRM_ERROR("Attempting to pin a purgeable buffer\n");
2434 if (obj->pin_filp != NULL && obj->pin_filp != file) {
2435 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
2441 obj->user_pin_count++;
2442 obj->pin_filp = file;
2443 if (obj->user_pin_count == 1) {
2444 ret = i915_gem_object_pin(obj, args->alignment, true);
2449 /* XXX - flush the CPU caches for pinned objects
2450 * as the X server doesn't manage domains yet
2452 i915_gem_object_flush_cpu_write_domain(obj);
2453 args->offset = obj->gtt_offset;
2455 drm_gem_object_unreference(&obj->base);
2462 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2463 struct drm_file *file)
2465 struct drm_i915_gem_pin *args;
2466 struct drm_i915_gem_object *obj;
2470 ret = i915_mutex_lock_interruptible(dev);
2474 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
2475 if (&obj->base == NULL) {
2480 if (obj->pin_filp != file) {
2481 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
2486 obj->user_pin_count--;
2487 if (obj->user_pin_count == 0) {
2488 obj->pin_filp = NULL;
2489 i915_gem_object_unpin(obj);
2493 drm_gem_object_unreference(&obj->base);
2500 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2501 struct drm_file *file)
2503 struct drm_i915_gem_busy *args = data;
2504 struct drm_i915_gem_object *obj;
2507 ret = i915_mutex_lock_interruptible(dev);
2511 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
2512 if (&obj->base == NULL) {
2517 /* Count all active objects as busy, even if they are currently not used
2518 * by the gpu. Users of this interface expect objects to eventually
2519 * become non-busy without any further actions, therefore emit any
2520 * necessary flushes here.
2522 ret = i915_gem_object_flush_active(obj);
2524 args->busy = obj->active;
2526 args->busy |= intel_ring_flag(obj->ring) << 17;
2529 drm_gem_object_unreference(&obj->base);
2536 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2537 struct drm_file *file_priv)
2540 return (i915_gem_ring_throttle(dev, file_priv));
2544 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2545 struct drm_file *file_priv)
2547 struct drm_i915_gem_madvise *args = data;
2548 struct drm_i915_gem_object *obj;
2551 switch (args->madv) {
2552 case I915_MADV_DONTNEED:
2553 case I915_MADV_WILLNEED:
2559 ret = i915_mutex_lock_interruptible(dev);
2563 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
2564 if (&obj->base == NULL) {
2569 if (obj->pin_count) {
2574 if (obj->madv != __I915_MADV_PURGED)
2575 obj->madv = args->madv;
2577 /* if the object is no longer attached, discard its backing storage */
2578 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
2579 i915_gem_object_truncate(obj);
2581 args->retained = obj->madv != __I915_MADV_PURGED;
2584 drm_gem_object_unreference(&obj->base);
2590 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2593 struct drm_i915_private *dev_priv;
2594 struct drm_i915_gem_object *obj;
2596 dev_priv = dev->dev_private;
2598 obj = kmalloc(sizeof(*obj), DRM_I915_GEM, M_WAITOK | M_ZERO);
2600 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
2601 drm_free(obj, DRM_I915_GEM);
2605 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2606 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2609 obj->cache_level = I915_CACHE_LLC;
2611 obj->cache_level = I915_CACHE_NONE;
2612 obj->base.driver_private = NULL;
2613 obj->fence_reg = I915_FENCE_REG_NONE;
2614 INIT_LIST_HEAD(&obj->mm_list);
2615 INIT_LIST_HEAD(&obj->gtt_list);
2616 INIT_LIST_HEAD(&obj->ring_list);
2617 INIT_LIST_HEAD(&obj->exec_list);
2618 INIT_LIST_HEAD(&obj->gpu_write_list);
2619 obj->madv = I915_MADV_WILLNEED;
2620 /* Avoid an unnecessary call to unbind on the first bind. */
2621 obj->map_and_fenceable = true;
2623 i915_gem_info_add_obj(dev_priv, size);
2628 int i915_gem_init_object(struct drm_gem_object *obj)
2631 kprintf("i915_gem_init_object called\n");
2636 i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
2638 struct drm_device *dev;
2639 drm_i915_private_t *dev_priv;
2642 dev = obj->base.dev;
2643 dev_priv = dev->dev_private;
2645 ret = i915_gem_object_unbind(obj);
2646 if (ret == -ERESTART) {
2647 list_move(&obj->mm_list, &dev_priv->mm.deferred_free_list);
2651 drm_gem_free_mmap_offset(&obj->base);
2652 drm_gem_object_release(&obj->base);
2653 i915_gem_info_remove_obj(dev_priv, obj->base.size);
2655 drm_free(obj->bit_17, DRM_I915_GEM);
2656 drm_free(obj, DRM_I915_GEM);
2660 i915_gem_free_object(struct drm_gem_object *gem_obj)
2662 struct drm_i915_gem_object *obj;
2663 struct drm_device *dev;
2665 obj = to_intel_bo(gem_obj);
2666 dev = obj->base.dev;
2668 while (obj->pin_count > 0)
2669 i915_gem_object_unpin(obj);
2671 if (obj->phys_obj != NULL)
2672 i915_gem_detach_phys_object(dev, obj);
2674 i915_gem_free_object_tail(obj);
2678 i915_gem_do_init(struct drm_device *dev, unsigned long start,
2679 unsigned long mappable_end, unsigned long end)
2681 drm_i915_private_t *dev_priv;
2682 unsigned long mappable;
2685 dev_priv = dev->dev_private;
2686 mappable = min(end, mappable_end) - start;
2688 drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
2690 dev_priv->mm.gtt_start = start;
2691 dev_priv->mm.gtt_mappable_end = mappable_end;
2692 dev_priv->mm.gtt_end = end;
2693 dev_priv->mm.gtt_total = end - start;
2694 dev_priv->mm.mappable_gtt_total = mappable;
2696 /* Take over this portion of the GTT */
2697 intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
2698 device_printf(dev->dev,
2699 "taking over the fictitious range 0x%lx-0x%lx\n",
2700 dev->agp->base + start, dev->agp->base + start + mappable);
2701 error = -vm_phys_fictitious_reg_range(dev->agp->base + start,
2702 dev->agp->base + start + mappable, VM_MEMATTR_WRITE_COMBINING);
2707 i915_gem_idle(struct drm_device *dev)
2709 drm_i915_private_t *dev_priv;
2712 dev_priv = dev->dev_private;
2713 if (dev_priv->mm.suspended)
2716 ret = i915_gpu_idle(dev);
2720 /* Under UMS, be paranoid and evict. */
2721 if (!drm_core_check_feature(dev, DRIVER_MODESET))
2722 i915_gem_evict_everything(dev);
2724 i915_gem_reset_fences(dev);
2726 /* Hack! Don't let anybody do execbuf while we don't control the chip.
2727 * We need to replace this with a semaphore, or something.
2728 * And not confound mm.suspended!
2730 dev_priv->mm.suspended = 1;
2731 del_timer_sync(&dev_priv->hangcheck_timer);
2733 i915_kernel_lost_context(dev);
2734 i915_gem_cleanup_ringbuffer(dev);
2736 /* Cancel the retire work handler, which should be idle now. */
2737 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2742 void i915_gem_l3_remap(struct drm_device *dev)
2744 drm_i915_private_t *dev_priv = dev->dev_private;
2748 if (!HAS_L3_GPU_CACHE(dev))
2751 if (!dev_priv->l3_parity.remap_info)
2754 misccpctl = I915_READ(GEN7_MISCCPCTL);
2755 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
2756 POSTING_READ(GEN7_MISCCPCTL);
2758 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
2759 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
2760 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
2761 DRM_DEBUG("0x%x was already programmed to %x\n",
2762 GEN7_L3LOG_BASE + i, remap);
2763 if (remap && !dev_priv->l3_parity.remap_info[i/4])
2764 DRM_DEBUG_DRIVER("Clearing remapped register\n");
2765 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
2768 /* Make sure all the writes land before disabling dop clock gating */
2769 POSTING_READ(GEN7_L3LOG_BASE);
2771 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
2775 i915_gem_init_swizzling(struct drm_device *dev)
2777 drm_i915_private_t *dev_priv;
2779 dev_priv = dev->dev_private;
2781 if (INTEL_INFO(dev)->gen < 5 ||
2782 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
2785 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
2786 DISP_TILE_SURFACE_SWIZZLING);
2791 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
2793 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
2795 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
2799 intel_enable_blt(struct drm_device *dev)
2806 /* The blitter was dysfunctional on early prototypes */
2807 revision = pci_read_config(dev->dev, PCIR_REVID, 1);
2808 if (IS_GEN6(dev) && revision < 8) {
2809 DRM_INFO("BLT not supported on this pre-production hardware;"
2810 " graphics performance will be degraded.\n");
2818 i915_gem_init_hw(struct drm_device *dev)
2820 drm_i915_private_t *dev_priv = dev->dev_private;
2823 if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
2824 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
2826 i915_gem_l3_remap(dev);
2828 i915_gem_init_swizzling(dev);
2830 ret = intel_init_render_ring_buffer(dev);
2835 ret = intel_init_bsd_ring_buffer(dev);
2837 goto cleanup_render_ring;
2840 if (intel_enable_blt(dev)) {
2841 ret = intel_init_blt_ring_buffer(dev);
2843 goto cleanup_bsd_ring;
2846 dev_priv->next_seqno = 1;
2849 * XXX: There was some w/a described somewhere suggesting loading
2850 * contexts before PPGTT.
2852 #if 0 /* XXX: HW context support */
2853 i915_gem_context_init(dev);
2855 i915_gem_init_ppgtt(dev);
2860 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
2861 cleanup_render_ring:
2862 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
2867 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
2869 drm_i915_private_t *dev_priv;
2872 dev_priv = dev->dev_private;
2873 for (i = 0; i < I915_NUM_RINGS; i++)
2874 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
2878 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2879 struct drm_file *file_priv)
2881 drm_i915_private_t *dev_priv = dev->dev_private;
2884 if (drm_core_check_feature(dev, DRIVER_MODESET))
2887 if (atomic_read(&dev_priv->mm.wedged)) {
2888 DRM_ERROR("Reenabling wedged hardware, good luck\n");
2889 atomic_set(&dev_priv->mm.wedged, 0);
2893 dev_priv->mm.suspended = 0;
2895 ret = i915_gem_init_hw(dev);
2901 KASSERT(list_empty(&dev_priv->mm.active_list), ("active list"));
2904 ret = drm_irq_install(dev);
2906 goto cleanup_ringbuffer;
2912 i915_gem_cleanup_ringbuffer(dev);
2913 dev_priv->mm.suspended = 1;
2920 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2921 struct drm_file *file_priv)
2924 if (drm_core_check_feature(dev, DRIVER_MODESET))
2927 drm_irq_uninstall(dev);
2928 return (i915_gem_idle(dev));
2932 i915_gem_lastclose(struct drm_device *dev)
2936 if (drm_core_check_feature(dev, DRIVER_MODESET))
2939 ret = i915_gem_idle(dev);
2941 DRM_ERROR("failed to idle hardware: %d\n", ret);
2945 init_ring_lists(struct intel_ring_buffer *ring)
2948 INIT_LIST_HEAD(&ring->active_list);
2949 INIT_LIST_HEAD(&ring->request_list);
2950 INIT_LIST_HEAD(&ring->gpu_write_list);
2954 i915_gem_load(struct drm_device *dev)
2957 drm_i915_private_t *dev_priv = dev->dev_private;
2959 INIT_LIST_HEAD(&dev_priv->mm.active_list);
2960 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
2961 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
2962 INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
2963 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
2964 INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
2965 INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
2966 for (i = 0; i < I915_NUM_RINGS; i++)
2967 init_ring_lists(&dev_priv->ring[i]);
2968 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
2969 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
2970 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
2971 i915_gem_retire_work_handler);
2972 init_completion(&dev_priv->error_completion);
2974 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
2976 I915_WRITE(MI_ARB_STATE,
2977 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
2980 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
2982 /* Old X drivers will take 0-2 for front, back, depth buffers */
2983 if (!drm_core_check_feature(dev, DRIVER_MODESET))
2984 dev_priv->fence_reg_start = 3;
2986 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
2987 dev_priv->num_fence_regs = 16;
2989 dev_priv->num_fence_regs = 8;
2991 /* Initialize fence registers to zero */
2992 i915_gem_reset_fences(dev);
2994 i915_gem_detect_bit_6_swizzle(dev);
2995 init_waitqueue_head(&dev_priv->pending_flip_queue);
2997 dev_priv->mm.interruptible = true;
3000 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
3001 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
3002 register_shrinker(&dev_priv->mm.inactive_shrinker);
3004 dev_priv->mm.i915_lowmem = EVENTHANDLER_REGISTER(vm_lowmem,
3005 i915_gem_lowmem, dev, EVENTHANDLER_PRI_ANY);
3010 i915_gem_init_phys_object(struct drm_device *dev, int id, int size, int align)
3012 drm_i915_private_t *dev_priv;
3013 struct drm_i915_gem_phys_object *phys_obj;
3016 dev_priv = dev->dev_private;
3017 if (dev_priv->mm.phys_objs[id - 1] != NULL || size == 0)
3020 phys_obj = kmalloc(sizeof(struct drm_i915_gem_phys_object), DRM_I915_GEM,
3025 phys_obj->handle = drm_pci_alloc(dev, size, align, ~0);
3026 if (phys_obj->handle == NULL) {
3030 pmap_change_attr((vm_offset_t)phys_obj->handle->vaddr,
3031 size / PAGE_SIZE, PAT_WRITE_COMBINING);
3033 dev_priv->mm.phys_objs[id - 1] = phys_obj;
3038 drm_free(phys_obj, DRM_I915_GEM);
3043 i915_gem_free_phys_object(struct drm_device *dev, int id)
3045 drm_i915_private_t *dev_priv;
3046 struct drm_i915_gem_phys_object *phys_obj;
3048 dev_priv = dev->dev_private;
3049 if (dev_priv->mm.phys_objs[id - 1] == NULL)
3052 phys_obj = dev_priv->mm.phys_objs[id - 1];
3053 if (phys_obj->cur_obj != NULL)
3054 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3056 drm_pci_free(dev, phys_obj->handle);
3057 drm_free(phys_obj, DRM_I915_GEM);
3058 dev_priv->mm.phys_objs[id - 1] = NULL;
3062 i915_gem_free_all_phys_object(struct drm_device *dev)
3066 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3067 i915_gem_free_phys_object(dev, i);
3071 i915_gem_detach_phys_object(struct drm_device *dev,
3072 struct drm_i915_gem_object *obj)
3079 if (obj->phys_obj == NULL)
3081 vaddr = obj->phys_obj->handle->vaddr;
3083 page_count = obj->base.size / PAGE_SIZE;
3084 VM_OBJECT_LOCK(obj->base.vm_obj);
3085 for (i = 0; i < page_count; i++) {
3086 m = i915_gem_wire_page(obj->base.vm_obj, i);
3090 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3091 sf = sf_buf_alloc(m);
3093 dst = (char *)sf_buf_kva(sf);
3094 memcpy(dst, vaddr + IDX_TO_OFF(i), PAGE_SIZE);
3097 drm_clflush_pages(&m, 1);
3099 VM_OBJECT_LOCK(obj->base.vm_obj);
3100 vm_page_reference(m);
3102 vm_page_busy_wait(m, FALSE, "i915gem");
3103 vm_page_unwire(m, 0);
3105 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3107 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3108 intel_gtt_chipset_flush();
3110 obj->phys_obj->cur_obj = NULL;
3111 obj->phys_obj = NULL;
3115 i915_gem_attach_phys_object(struct drm_device *dev,
3116 struct drm_i915_gem_object *obj,
3120 drm_i915_private_t *dev_priv;
3124 int i, page_count, ret;
3126 if (id > I915_MAX_PHYS_OBJECT)
3129 if (obj->phys_obj != NULL) {
3130 if (obj->phys_obj->id == id)
3132 i915_gem_detach_phys_object(dev, obj);
3135 dev_priv = dev->dev_private;
3136 if (dev_priv->mm.phys_objs[id - 1] == NULL) {
3137 ret = i915_gem_init_phys_object(dev, id, obj->base.size, align);
3139 DRM_ERROR("failed to init phys object %d size: %zu\n",
3140 id, obj->base.size);
3145 /* bind to the object */
3146 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
3147 obj->phys_obj->cur_obj = obj;
3149 page_count = obj->base.size / PAGE_SIZE;
3151 VM_OBJECT_LOCK(obj->base.vm_obj);
3153 for (i = 0; i < page_count; i++) {
3154 m = i915_gem_wire_page(obj->base.vm_obj, i);
3159 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3160 sf = sf_buf_alloc(m);
3161 src = (char *)sf_buf_kva(sf);
3162 dst = (char *)obj->phys_obj->handle->vaddr + IDX_TO_OFF(i);
3163 memcpy(dst, src, PAGE_SIZE);
3166 VM_OBJECT_LOCK(obj->base.vm_obj);
3168 vm_page_reference(m);
3169 vm_page_busy_wait(m, FALSE, "i915gem");
3170 vm_page_unwire(m, 0);
3172 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3174 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3180 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_i915_gem_object *obj,
3181 uint64_t data_ptr, uint64_t offset, uint64_t size,
3182 struct drm_file *file_priv)
3184 char *user_data, *vaddr;
3187 vaddr = (char *)obj->phys_obj->handle->vaddr + offset;
3188 user_data = (char *)(uintptr_t)data_ptr;
3190 if (copyin_nofault(user_data, vaddr, size) != 0) {
3191 /* The physical object once assigned is fixed for the lifetime
3192 * of the obj, so we can safely drop the lock and continue
3196 ret = -copyin(user_data, vaddr, size);
3202 intel_gtt_chipset_flush();
3207 i915_gem_release(struct drm_device *dev, struct drm_file *file)
3209 struct drm_i915_file_private *file_priv;
3210 struct drm_i915_gem_request *request;
3212 file_priv = file->driver_priv;
3214 /* Clean up our request list when the client is going away, so that
3215 * later retire_requests won't dereference our soon-to-be-gone
3218 spin_lock(&file_priv->mm.lock);
3219 while (!list_empty(&file_priv->mm.request_list)) {
3220 request = list_first_entry(&file_priv->mm.request_list,
3221 struct drm_i915_gem_request,
3223 list_del(&request->client_list);
3224 request->file_priv = NULL;
3226 spin_unlock(&file_priv->mm.lock);
3230 i915_gem_swap_io(struct drm_device *dev, struct drm_i915_gem_object *obj,
3231 uint64_t data_ptr, uint64_t size, uint64_t offset, enum uio_rw rw,
3232 struct drm_file *file)
3239 int cnt, do_bit17_swizzling, length, obj_po, ret, swizzled_po;
3241 if (obj->gtt_offset != 0 && rw == UIO_READ)
3242 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
3244 do_bit17_swizzling = 0;
3247 vm_obj = obj->base.vm_obj;
3250 VM_OBJECT_LOCK(vm_obj);
3251 vm_object_pip_add(vm_obj, 1);
3253 obj_pi = OFF_TO_IDX(offset);
3254 obj_po = offset & PAGE_MASK;
3256 m = i915_gem_wire_page(vm_obj, obj_pi);
3257 VM_OBJECT_UNLOCK(vm_obj);
3259 sf = sf_buf_alloc(m);
3260 mkva = sf_buf_kva(sf);
3261 length = min(size, PAGE_SIZE - obj_po);
3262 while (length > 0) {
3263 if (do_bit17_swizzling &&
3264 (VM_PAGE_TO_PHYS(m) & (1 << 17)) != 0) {
3265 cnt = roundup2(obj_po + 1, 64);
3266 cnt = min(cnt - obj_po, length);
3267 swizzled_po = obj_po ^ 64;
3270 swizzled_po = obj_po;
3273 ret = -copyout_nofault(
3274 (char *)mkva + swizzled_po,
3275 (void *)(uintptr_t)data_ptr, cnt);
3277 ret = -copyin_nofault(
3278 (void *)(uintptr_t)data_ptr,
3279 (char *)mkva + swizzled_po, cnt);
3289 VM_OBJECT_LOCK(vm_obj);
3290 if (rw == UIO_WRITE)
3292 vm_page_reference(m);
3293 vm_page_busy_wait(m, FALSE, "i915gem");
3294 vm_page_unwire(m, 1);
3296 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3301 vm_object_pip_wakeup(vm_obj);
3302 VM_OBJECT_UNLOCK(vm_obj);
3308 i915_gem_gtt_write(struct drm_device *dev, struct drm_i915_gem_object *obj,
3309 uint64_t data_ptr, uint64_t size, uint64_t offset, struct drm_file *file)
3315 * Pass the unaligned physical address and size to pmap_mapdev_attr()
3316 * so it can properly calculate whether an extra page needs to be
3317 * mapped or not to cover the requested range. The function will
3318 * add the page offset into the returned mkva for us.
3320 mkva = (vm_offset_t)pmap_mapdev_attr(dev->agp->base + obj->gtt_offset +
3321 offset, size, PAT_WRITE_COMBINING);
3322 ret = -copyin_nofault((void *)(uintptr_t)data_ptr, (char *)mkva, size);
3323 pmap_unmapdev(mkva, size);
3328 i915_gem_obj_io(struct drm_device *dev, uint32_t handle, uint64_t data_ptr,
3329 uint64_t size, uint64_t offset, enum uio_rw rw, struct drm_file *file)
3331 struct drm_i915_gem_object *obj;
3333 vm_offset_t start, end;
3338 start = trunc_page(data_ptr);
3339 end = round_page(data_ptr + size);
3340 npages = howmany(end - start, PAGE_SIZE);
3341 ma = kmalloc(npages * sizeof(vm_page_t), DRM_I915_GEM, M_WAITOK |
3343 npages = vm_fault_quick_hold_pages(&curproc->p_vmspace->vm_map,
3344 (vm_offset_t)data_ptr, size,
3345 (rw == UIO_READ ? VM_PROT_WRITE : 0 ) | VM_PROT_READ, ma, npages);
3351 ret = i915_mutex_lock_interruptible(dev);
3355 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
3356 if (&obj->base == NULL) {
3360 if (offset > obj->base.size || size > obj->base.size - offset) {
3365 if (rw == UIO_READ) {
3366 ret = i915_gem_swap_io(dev, obj, data_ptr, size, offset,
3369 if (obj->phys_obj) {
3370 ret = i915_gem_phys_pwrite(dev, obj, data_ptr, offset,
3372 } else if (obj->gtt_space &&
3373 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
3374 ret = i915_gem_object_pin(obj, 0, true);
3377 ret = i915_gem_object_set_to_gtt_domain(obj, true);
3380 ret = i915_gem_object_put_fence(obj);
3383 ret = i915_gem_gtt_write(dev, obj, data_ptr, size,
3386 i915_gem_object_unpin(obj);
3388 ret = i915_gem_object_set_to_cpu_domain(obj, true);
3391 ret = i915_gem_swap_io(dev, obj, data_ptr, size, offset,
3396 drm_gem_object_unreference(&obj->base);
3400 vm_page_unhold_pages(ma, npages);
3402 drm_free(ma, DRM_I915_GEM);
3407 i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot,
3408 vm_ooffset_t foff, struct ucred *cred, u_short *color)
3411 *color = 0; /* XXXKIB */
3418 i915_gem_pager_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot,
3421 struct drm_gem_object *gem_obj;
3422 struct drm_i915_gem_object *obj;
3423 struct drm_device *dev;
3424 drm_i915_private_t *dev_priv;
3429 gem_obj = vm_obj->handle;
3430 obj = to_intel_bo(gem_obj);
3431 dev = obj->base.dev;
3432 dev_priv = dev->dev_private;
3434 write = (prot & VM_PROT_WRITE) != 0;
3438 vm_object_pip_add(vm_obj, 1);
3441 * Remove the placeholder page inserted by vm_fault() from the
3442 * object before dropping the object lock. If
3443 * i915_gem_release_mmap() is active in parallel on this gem
3444 * object, then it owns the drm device sx and might find the
3445 * placeholder already. Then, since the page is busy,
3446 * i915_gem_release_mmap() sleeps waiting for the busy state
3447 * of the page cleared. We will be not able to acquire drm
3448 * device lock until i915_gem_release_mmap() is able to make a
3451 if (*mres != NULL) {
3453 vm_page_remove(oldm);
3458 VM_OBJECT_UNLOCK(vm_obj);
3464 ret = i915_mutex_lock_interruptible(dev);
3473 * Since the object lock was dropped, other thread might have
3474 * faulted on the same GTT address and instantiated the
3475 * mapping for the page. Recheck.
3477 VM_OBJECT_LOCK(vm_obj);
3478 m = vm_page_lookup(vm_obj, OFF_TO_IDX(offset));
3480 if ((m->flags & PG_BUSY) != 0) {
3483 vm_page_sleep(m, "915pee");
3489 VM_OBJECT_UNLOCK(vm_obj);
3491 /* Now bind it into the GTT if needed */
3492 if (!obj->map_and_fenceable) {
3493 ret = i915_gem_object_unbind(obj);
3499 if (!obj->gtt_space) {
3500 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
3506 ret = i915_gem_object_set_to_gtt_domain(obj, write);
3513 if (obj->tiling_mode == I915_TILING_NONE)
3514 ret = i915_gem_object_put_fence(obj);
3516 ret = i915_gem_object_get_fence(obj);
3522 if (i915_gem_object_is_inactive(obj))
3523 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3525 obj->fault_mappable = true;
3526 VM_OBJECT_LOCK(vm_obj);
3527 m = vm_phys_fictitious_to_vm_page(dev->agp->base + obj->gtt_offset +
3534 KASSERT((m->flags & PG_FICTITIOUS) != 0,
3535 ("not fictitious %p", m));
3536 KASSERT(m->wire_count == 1, ("wire_count not 1 %p", m));
3538 if ((m->flags & PG_BUSY) != 0) {
3541 vm_page_sleep(m, "915pbs");
3545 m->valid = VM_PAGE_BITS_ALL;
3546 vm_page_insert(m, vm_obj, OFF_TO_IDX(offset));
3549 vm_page_busy_try(m, false);
3555 vm_object_pip_wakeup(vm_obj);
3556 return (VM_PAGER_OK);
3561 KASSERT(ret != 0, ("i915_gem_pager_fault: wrong return"));
3562 if (ret == -EAGAIN || ret == -EIO || ret == -EINTR) {
3563 goto unlocked_vmobj;
3565 VM_OBJECT_LOCK(vm_obj);
3566 vm_object_pip_wakeup(vm_obj);
3567 return (VM_PAGER_ERROR);
3571 i915_gem_pager_dtor(void *handle)
3573 struct drm_gem_object *obj;
3574 struct drm_device *dev;
3580 drm_gem_free_mmap_offset(obj);
3581 i915_gem_release_mmap(to_intel_bo(obj));
3582 drm_gem_object_unreference(obj);
3586 struct cdev_pager_ops i915_gem_pager_ops = {
3587 .cdev_pg_fault = i915_gem_pager_fault,
3588 .cdev_pg_ctor = i915_gem_pager_ctor,
3589 .cdev_pg_dtor = i915_gem_pager_dtor
3592 #define GEM_PARANOID_CHECK_GTT 0
3593 #if GEM_PARANOID_CHECK_GTT
3595 i915_gem_assert_pages_not_mapped(struct drm_device *dev, vm_page_t *ma,
3598 struct drm_i915_private *dev_priv;
3600 unsigned long start, end;
3604 dev_priv = dev->dev_private;
3605 start = OFF_TO_IDX(dev_priv->mm.gtt_start);
3606 end = OFF_TO_IDX(dev_priv->mm.gtt_end);
3607 for (i = start; i < end; i++) {
3608 pa = intel_gtt_read_pte_paddr(i);
3609 for (j = 0; j < page_count; j++) {
3610 if (pa == VM_PAGE_TO_PHYS(ma[j])) {
3611 panic("Page %p in GTT pte index %d pte %x",
3612 ma[i], i, intel_gtt_read_pte(i));
3620 i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
3621 uint32_t flush_domains)
3623 struct drm_i915_gem_object *obj, *next;
3624 uint32_t old_write_domain;
3626 list_for_each_entry_safe(obj, next, &ring->gpu_write_list,
3628 if (obj->base.write_domain & flush_domains) {
3629 old_write_domain = obj->base.write_domain;
3630 obj->base.write_domain = 0;
3631 list_del_init(&obj->gpu_write_list);
3632 i915_gem_object_move_to_active(obj, ring,
3633 i915_gem_next_request_seqno(ring));
3638 #define VM_OBJECT_LOCK_ASSERT_OWNED(object)
3641 i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex)
3646 VM_OBJECT_LOCK_ASSERT_OWNED(object);
3647 m = vm_page_grab(object, pindex, VM_ALLOC_NORMAL | VM_ALLOC_RETRY);
3648 if (m->valid != VM_PAGE_BITS_ALL) {
3649 if (vm_pager_has_page(object, pindex)) {
3650 rv = vm_pager_get_page(object, &m, 1);
3651 m = vm_page_lookup(object, pindex);
3654 if (rv != VM_PAGER_OK) {
3659 pmap_zero_page(VM_PAGE_TO_PHYS(m));
3660 m->valid = VM_PAGE_BITS_ALL;
3666 atomic_add_long(&i915_gem_wired_pages_cnt, 1);
3671 i915_gem_flush_ring(struct intel_ring_buffer *ring, uint32_t invalidate_domains,
3672 uint32_t flush_domains)
3676 if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
3679 ret = ring->flush(ring, invalidate_domains, flush_domains);
3683 if (flush_domains & I915_GEM_GPU_DOMAINS)
3684 i915_gem_process_flushing_list(ring, flush_domains);
3689 i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
3691 if (ring->outstanding_lazy_request == 0)
3692 ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev);
3694 return ring->outstanding_lazy_request;
3698 i915_gpu_is_active(struct drm_device *dev)
3700 drm_i915_private_t *dev_priv;
3702 dev_priv = dev->dev_private;
3703 return (!list_empty(&dev_priv->mm.flushing_list) ||
3704 !list_empty(&dev_priv->mm.active_list));
3708 i915_gem_lowmem(void *arg)
3710 struct drm_device *dev;
3711 struct drm_i915_private *dev_priv;
3712 struct drm_i915_gem_object *obj, *next;
3713 int cnt, cnt_fail, cnt_total;
3716 dev_priv = dev->dev_private;
3718 if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_NOWAIT))
3722 /* first scan for clean buffers */
3723 i915_gem_retire_requests(dev);
3725 cnt_total = cnt_fail = cnt = 0;
3727 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
3729 if (i915_gem_object_is_purgeable(obj)) {
3730 if (i915_gem_object_unbind(obj) != 0)
3736 /* second pass, evict/count anything still on the inactive list */
3737 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
3739 if (i915_gem_object_unbind(obj) == 0)
3745 if (cnt_fail > cnt_total / 100 && i915_gpu_is_active(dev)) {
3747 * We are desperate for pages, so as a last resort, wait
3748 * for the GPU to finish and discard whatever we can.
3749 * This has a dramatic impact to reduce the number of
3750 * OOM-killer events whilst running the GPU aggressively.
3752 if (i915_gpu_idle(dev) == 0)
3759 i915_gem_unload(struct drm_device *dev)
3761 struct drm_i915_private *dev_priv;
3763 dev_priv = dev->dev_private;
3764 EVENTHANDLER_DEREGISTER(vm_lowmem, dev_priv->mm.i915_lowmem);