2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
26 * $DragonFly: src/sys/platform/pc32/apic/mpapic.c,v 1.22 2008/04/20 13:44:26 swildner Exp $
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/kernel.h>
32 #include <machine/globaldata.h>
33 #include <machine/smp.h>
34 #include <machine/md_var.h>
35 #include <machine_base/apic/mpapic.h>
36 #include <machine/segments.h>
37 #include <sys/thread2.h>
39 #include <machine_base/isa/intr_machdep.h> /* Xspuriousint() */
43 /* EISA Edge/Level trigger control registers */
44 #define ELCR0 0x4d0 /* eisa irq 0-7 */
45 #define ELCR1 0x4d1 /* eisa irq 8-15 */
47 volatile lapic_t *lapic;
49 static void lapic_timer_calibrate(void);
50 static void lapic_timer_set_divisor(int);
51 static void lapic_timer_fixup_handler(void *);
52 static void lapic_timer_restart_handler(void *);
54 void lapic_timer_process(void);
55 void lapic_timer_process_frame(struct intrframe *);
57 static int lapic_timer_enable = 1;
58 TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
60 static void lapic_timer_intr_reload(struct cputimer_intr *, sysclock_t);
61 static void lapic_timer_intr_enable(struct cputimer_intr *);
62 static void lapic_timer_intr_restart(struct cputimer_intr *);
63 static void lapic_timer_intr_pmfixup(struct cputimer_intr *);
65 static struct cputimer_intr lapic_cputimer_intr = {
67 .reload = lapic_timer_intr_reload,
68 .enable = lapic_timer_intr_enable,
69 .config = cputimer_intr_default_config,
70 .restart = lapic_timer_intr_restart,
71 .pmfixup = lapic_timer_intr_pmfixup,
72 .initclock = cputimer_intr_default_initclock,
73 .next = SLIST_ENTRY_INITIALIZER,
75 .type = CPUTIMER_INTR_LAPIC,
76 .prio = CPUTIMER_INTR_PRIO_LAPIC,
77 .caps = CPUTIMER_INTR_CAP_NONE
81 * pointers to pmapped apic hardware.
84 volatile ioapic_t **ioapic;
86 static int lapic_timer_divisor_idx = -1;
87 static const uint32_t lapic_timer_divisors[] = {
88 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
89 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
91 #define APIC_TIMER_NDIVISORS \
92 (int)(sizeof(lapic_timer_divisors) / sizeof(lapic_timer_divisors[0]))
103 * Enable APIC, configure interrupts.
106 apic_initialize(boolean_t bsp)
112 * setup LVT1 as ExtINT on the BSP. This is theoretically an
113 * aggregate interrupt input from the 8259. The INTA cycle
114 * will be routed to the external controller (the 8259) which
115 * is expected to supply the vector.
117 * Must be setup edge triggered, active high.
119 * Disable LVT1 on the APs. It doesn't matter what delivery
120 * mode we use because we leave it masked.
122 temp = lapic->lvt_lint0;
123 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
124 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
125 if (mycpu->gd_cpuid == 0)
126 temp |= APIC_LVT_DM_EXTINT;
128 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
129 lapic->lvt_lint0 = temp;
132 * setup LVT2 as NMI, masked till later. Edge trigger, active high.
134 temp = lapic->lvt_lint1;
135 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
136 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
137 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
138 lapic->lvt_lint1 = temp;
141 * Mask the apic error interrupt, apic performance counter
144 lapic->lvt_error = lapic->lvt_error | APIC_LVT_MASKED;
145 lapic->lvt_pcint = lapic->lvt_pcint | APIC_LVT_MASKED;
147 /* Set apic timer vector and mask the apic timer interrupt. */
148 timer = lapic->lvt_timer;
149 timer &= ~APIC_LVTT_VECTOR;
150 timer |= XTIMER_OFFSET;
151 timer |= APIC_LVTT_MASKED;
152 lapic->lvt_timer = timer;
155 * Set the Task Priority Register as needed. At the moment allow
156 * interrupts on all cpus (the APs will remain CLId until they are
157 * ready to deal). We could disable all but IPIs by setting
158 * temp |= TPR_IPI_ONLY for cpu != 0.
161 temp &= ~APIC_TPR_PRIO; /* clear priority field */
164 * If we are NOT running the IO APICs, the LAPIC will only be used
165 * for IPIs. Set the TPR to prevent any unintentional interrupts.
167 temp |= TPR_IPI_ONLY;
173 * enable the local APIC
176 temp |= APIC_SVR_ENABLE; /* enable the APIC */
177 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
180 * Set the spurious interrupt vector. The low 4 bits of the vector
183 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
184 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
185 temp &= ~APIC_SVR_VECTOR;
186 temp |= XSPURIOUSINT_OFFSET;
191 * Pump out a few EOIs to clean out interrupts that got through
192 * before we were able to set the TPR.
199 lapic_timer_calibrate();
200 if (lapic_timer_enable) {
201 cputimer_intr_register(&lapic_cputimer_intr);
202 cputimer_intr_select(&lapic_cputimer_intr, 0);
205 lapic_timer_set_divisor(lapic_timer_divisor_idx);
209 apic_dump("apic_initialize()");
214 lapic_timer_set_divisor(int divisor_idx)
216 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
217 lapic->dcr_timer = lapic_timer_divisors[divisor_idx];
221 lapic_timer_oneshot(u_int count)
225 value = lapic->lvt_timer;
226 value &= ~APIC_LVTT_PERIODIC;
227 lapic->lvt_timer = value;
228 lapic->icr_timer = count;
232 lapic_timer_oneshot_quick(u_int count)
234 lapic->icr_timer = count;
238 lapic_timer_calibrate(void)
242 /* Try to calibrate the local APIC timer. */
243 for (lapic_timer_divisor_idx = 0;
244 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
245 lapic_timer_divisor_idx++) {
246 lapic_timer_set_divisor(lapic_timer_divisor_idx);
247 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
249 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
250 if (value != APIC_TIMER_MAX_COUNT)
253 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
254 panic("lapic: no proper timer divisor?!\n");
255 lapic_cputimer_intr.freq = value / 2;
257 kprintf("lapic: divisor index %d, frequency %u Hz\n",
258 lapic_timer_divisor_idx, lapic_cputimer_intr.freq);
262 lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
266 gd->gd_timer_running = 0;
268 count = sys_cputimer->count();
269 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
270 systimer_intr(&count, 0, frame);
274 lapic_timer_process(void)
276 lapic_timer_process_oncpu(mycpu, NULL);
280 lapic_timer_process_frame(struct intrframe *frame)
282 lapic_timer_process_oncpu(mycpu, frame);
286 lapic_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
288 struct globaldata *gd = mycpu;
290 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
294 if (gd->gd_timer_running) {
295 if (reload < lapic->ccr_timer)
296 lapic_timer_oneshot_quick(reload);
298 gd->gd_timer_running = 1;
299 lapic_timer_oneshot_quick(reload);
304 lapic_timer_intr_enable(struct cputimer_intr *cti __unused)
308 timer = lapic->lvt_timer;
309 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
310 lapic->lvt_timer = timer;
312 lapic_timer_fixup_handler(NULL);
316 lapic_timer_fixup_handler(void *arg)
323 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
325 * Detect the presence of C1E capability mostly on latest
326 * dual-cores (or future) k8 family. This feature renders
327 * the local APIC timer dead, so we disable it by reading
328 * the Interrupt Pending Message register and clearing both
329 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
332 * "BIOS and Kernel Developer's Guide for AMD NPT
333 * Family 0Fh Processors"
334 * #32559 revision 3.00
336 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
337 (cpu_id & 0x0fff0000) >= 0x00040000) {
340 msr = rdmsr(0xc0010055);
341 if (msr & 0x18000000) {
342 struct globaldata *gd = mycpu;
344 kprintf("cpu%d: AMD C1E detected\n",
346 wrmsr(0xc0010055, msr & ~0x18000000ULL);
349 * We are kinda stalled;
352 gd->gd_timer_running = 1;
353 lapic_timer_oneshot_quick(2);
363 lapic_timer_restart_handler(void *dummy __unused)
367 lapic_timer_fixup_handler(&started);
369 struct globaldata *gd = mycpu;
371 gd->gd_timer_running = 1;
372 lapic_timer_oneshot_quick(2);
377 * This function is called only by ACPI-CA code currently:
378 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
379 * module controls PM. So once ACPI-CA is attached, we try
380 * to apply the fixup to prevent LAPIC timer from hanging.
383 lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused)
385 lwkt_send_ipiq_mask(smp_active_mask,
386 lapic_timer_fixup_handler, NULL);
390 lapic_timer_intr_restart(struct cputimer_intr *cti __unused)
392 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL);
397 * dump contents of local APIC registers
402 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
403 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
404 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
414 #define IOAPIC_ISA_INTS 16
415 #define REDIRCNT_IOAPIC(A) \
416 ((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1)
418 static int trigger (int apic, int pin, u_int32_t * flags);
419 static void polarity (int apic, int pin, u_int32_t * flags, int level);
421 #define DEFAULT_FLAGS \
427 #define DEFAULT_ISA_FLAGS \
436 io_apic_set_id(int apic, int id)
440 ux = io_apic_read(apic, IOAPIC_ID); /* get current contents */
441 if (((ux & APIC_ID_MASK) >> 24) != id) {
442 kprintf("Changing APIC ID for IO APIC #%d"
443 " from %d to %d on chip\n",
444 apic, ((ux & APIC_ID_MASK) >> 24), id);
445 ux &= ~APIC_ID_MASK; /* clear the ID field */
447 io_apic_write(apic, IOAPIC_ID, ux); /* write new value */
448 ux = io_apic_read(apic, IOAPIC_ID); /* re-read && test */
449 if (((ux & APIC_ID_MASK) >> 24) != id)
450 panic("can't control IO APIC #%d ID, reg: 0x%08x",
457 io_apic_get_id(int apic)
459 return (io_apic_read(apic, IOAPIC_ID) & APIC_ID_MASK) >> 24;
468 extern int apic_pin_trigger; /* 'opaque' */
471 io_apic_setup_intpin(int apic, int pin)
473 int bus, bustype, irq;
474 u_char select; /* the select register is 8 bits */
475 u_int32_t flags; /* the window register is 32 bits */
476 u_int32_t target; /* the window register is 32 bits */
477 u_int32_t vector; /* the window register is 32 bits */
482 select = pin * 2 + IOAPIC_REDTBL0; /* register */
485 * Always clear an IO APIC pin before [re]programming it. This is
486 * particularly important if the pin is set up for a level interrupt
487 * as the IOART_REM_IRR bit might be set. When we reprogram the
488 * vector any EOI from pending ints on this pin could be lost and
489 * IRR might never get reset.
491 * To fix this problem, clear the vector and make sure it is
492 * programmed as an edge interrupt. This should theoretically
493 * clear IRR so we can later, safely program it as a level
498 flags = io_apic_read(apic, select) & IOART_RESV;
499 flags |= IOART_INTMSET | IOART_TRGREDG | IOART_INTAHI;
500 flags |= IOART_DESTPHY | IOART_DELFIXED;
502 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
503 target |= 0; /* fixed mode cpu mask of 0 - don't deliver anywhere */
507 io_apic_write(apic, select, flags | vector);
508 io_apic_write(apic, select + 1, target);
513 * We only deal with vectored interrupts here. ? documentation is
514 * lacking, I'm guessing an interrupt type of 0 is the 'INT' type,
517 * This test also catches unconfigured pins.
519 if (apic_int_type(apic, pin) != 0)
523 * Leave the pin unprogrammed if it does not correspond to
526 irq = apic_irq(apic, pin);
530 /* determine the bus type for this pin */
531 bus = apic_src_bus_id(apic, pin);
534 bustype = apic_bus_type(bus);
536 if ((bustype == ISA) &&
537 (pin < IOAPIC_ISA_INTS) &&
539 (apic_polarity(apic, pin) == 0x1) &&
540 (apic_trigger(apic, pin) == 0x3)) {
542 * A broken BIOS might describe some ISA
543 * interrupts as active-high level-triggered.
544 * Use default ISA flags for those interrupts.
546 flags = DEFAULT_ISA_FLAGS;
549 * Program polarity and trigger mode according to
552 flags = DEFAULT_FLAGS;
553 level = trigger(apic, pin, &flags);
555 apic_pin_trigger |= (1 << irq);
556 polarity(apic, pin, &flags, level);
560 ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", irq);
561 kgetenv_int(envpath, &cpuid);
563 /* ncpus may not be available yet */
568 kprintf("IOAPIC #%d intpin %d -> irq %d (CPU%d)\n",
569 apic, pin, irq, cpuid);
573 * Program the appropriate registers. This routing may be
574 * overridden when an interrupt handler for a device is
575 * actually added (see register_int(), which calls through
576 * the MACHINTR ABI to set up an interrupt handler/vector).
578 * The order in which we must program the two registers for
579 * safety is unclear! XXX
583 vector = IDT_OFFSET + irq; /* IDT vec */
584 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
585 /* Deliver all interrupts to CPU0 (BSP) */
586 target |= (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
588 flags |= io_apic_read(apic, select) & IOART_RESV;
589 io_apic_write(apic, select, flags | vector);
590 io_apic_write(apic, select + 1, target);
596 io_apic_setup(int apic)
602 apic_pin_trigger = 0; /* default to edge-triggered */
604 maxpin = REDIRCNT_IOAPIC(apic); /* pins in APIC */
605 kprintf("Programming %d pins in IOAPIC #%d\n", maxpin, apic);
607 for (pin = 0; pin < maxpin; ++pin) {
608 io_apic_setup_intpin(apic, pin);
611 if (apic_int_type(apic, pin) >= 0) {
612 kprintf("Warning: IOAPIC #%d pin %d does not exist,"
613 " cannot program!\n", apic, pin);
618 /* return GOOD status */
621 #undef DEFAULT_ISA_FLAGS
625 #define DEFAULT_EXTINT_FLAGS \
634 * XXX this function is only used by 8254 setup
635 * Setup the source of External INTerrupts.
638 ext_int_setup(int apic, int intr)
640 u_char select; /* the select register is 8 bits */
641 u_int32_t flags; /* the window register is 32 bits */
642 u_int32_t target; /* the window register is 32 bits */
643 u_int32_t vector; /* the window register is 32 bits */
647 if (apic_int_type(apic, intr) != 3)
651 ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", intr);
652 kgetenv_int(envpath, &cpuid);
654 /* ncpus may not be available yet */
658 /* Deliver interrupts to CPU0 (BSP) */
659 target = (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
661 select = IOAPIC_REDTBL0 + (2 * intr);
662 vector = IDT_OFFSET + intr;
663 flags = DEFAULT_EXTINT_FLAGS;
665 io_apic_write(apic, select, flags | vector);
666 io_apic_write(apic, select + 1, target);
670 #undef DEFAULT_EXTINT_FLAGS
674 * Set the trigger level for an IO APIC pin.
677 trigger(int apic, int pin, u_int32_t * flags)
682 static int intcontrol = -1;
684 switch (apic_trigger(apic, pin)) {
690 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG */
694 *flags |= IOART_TRGRLVL;
702 if ((id = apic_src_bus_id(apic, pin)) == -1)
705 switch (apic_bus_type(id)) {
707 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG; */
711 eirq = apic_src_bus_irq(apic, pin);
713 if (eirq < 0 || eirq > 15) {
714 kprintf("EISA IRQ %d?!?!\n", eirq);
718 if (intcontrol == -1) {
719 intcontrol = inb(ELCR1) << 8;
720 intcontrol |= inb(ELCR0);
721 kprintf("EISA INTCONTROL = %08x\n", intcontrol);
724 /* Use ELCR settings to determine level or edge mode */
725 level = (intcontrol >> eirq) & 1;
728 * Note that on older Neptune chipset based systems, any
729 * pci interrupts often show up here and in the ELCR as well
730 * as level sensitive interrupts attributed to the EISA bus.
734 *flags |= IOART_TRGRLVL;
736 *flags &= ~IOART_TRGRLVL;
741 *flags |= IOART_TRGRLVL;
750 panic("bad APIC IO INT flags");
755 * Set the polarity value for an IO APIC pin.
758 polarity(int apic, int pin, u_int32_t * flags, int level)
762 switch (apic_polarity(apic, pin)) {
768 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
772 *flags |= IOART_INTALO;
780 if ((id = apic_src_bus_id(apic, pin)) == -1)
783 switch (apic_bus_type(id)) {
785 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
789 /* polarity converter always gives active high */
790 *flags &= ~IOART_INTALO;
794 *flags |= IOART_INTALO;
803 panic("bad APIC IO INT flags");
808 * Print contents of apic_imen.
810 extern u_int apic_imen; /* keep apic_imen 'opaque' */
816 kprintf("SMP: enabled INTs: ");
817 for (x = 0; x < 24; ++x)
818 if ((apic_imen & (1 << x)) == 0)
820 kprintf("apic_imen: 0x%08x\n", apic_imen);
825 * Inter Processor Interrupt functions.
831 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
833 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
834 * vector is any valid SYSTEM INT vector
835 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
837 * A backlog of requests can create a deadlock between cpus. To avoid this
838 * we have to be able to accept IPIs at the same time we are trying to send
839 * them. The critical section prevents us from attempting to send additional
840 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
841 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
842 * to occur but fortunately it does not happen too often.
845 apic_ipi(int dest_type, int vector, int delivery_mode)
850 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
851 unsigned long rflags = read_rflags();
853 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
856 write_rflags(rflags);
859 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
860 delivery_mode | vector;
861 lapic->icr_lo = icr_lo;
867 single_apic_ipi(int cpu, int vector, int delivery_mode)
873 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
874 unsigned long rflags = read_rflags();
876 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
879 write_rflags(rflags);
881 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
882 icr_hi |= (CPU_TO_ID(cpu) << 24);
883 lapic->icr_hi = icr_hi;
886 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK)
887 | APIC_DEST_DESTFLD | delivery_mode | vector;
890 lapic->icr_lo = icr_lo;
897 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
899 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
900 * to the target, and the scheduler does not 'poll' for IPI messages.
903 single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
909 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
913 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
914 icr_hi |= (CPU_TO_ID(cpu) << 24);
915 lapic->icr_hi = icr_hi;
918 icr_lo = (lapic->icr_lo & APIC_RESV2_MASK)
919 | APIC_DEST_DESTFLD | delivery_mode | vector;
922 lapic->icr_lo = icr_lo;
930 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
932 * target is a bitmask of destination cpus. Vector is any
933 * valid system INT vector. Delivery mode may be either
934 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
937 selected_apic_ipi(u_int target, int vector, int delivery_mode)
941 int n = bsfl(target);
943 single_apic_ipi(n, vector, delivery_mode);
949 * Timer code, in development...
950 * - suggested by rgrimes@gndrsh.aac.dev.com
953 get_apic_timer_frequency(void)
955 return(lapic_cputimer_intr.freq);
959 * Load a 'downcount time' in uSeconds.
962 set_apic_timer(int us)
967 * When we reach here, lapic timer's frequency
968 * must have been calculated as well as the
969 * divisor (lapic->dcr_timer is setup during the
970 * divisor calculation).
972 KKASSERT(lapic_cputimer_intr.freq != 0 &&
973 lapic_timer_divisor_idx >= 0);
975 count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000;
976 lapic_timer_oneshot(count);
981 * Read remaining time in timer.
984 read_apic_timer(void)
987 /** XXX FIXME: we need to return the actual remaining time,
988 * for now we just return the remaining count.
991 return lapic->ccr_timer;
997 * Spin-style delay, set delay time in uS, spin till it drains.
1002 set_apic_timer(count);
1003 while (read_apic_timer())