1 /******************************************************************************
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7 modification, are permitted provided that the following conditions are met:
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32 ******************************************************************************/
36 * 82575EB Gigabit Network Connection
37 * 82575EB Gigabit Backplane Connection
38 * 82575GB Gigabit Network Connection
39 * 82576 Gigabit Network Connection
42 #include "e1000_api.h"
44 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
45 static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw);
46 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
47 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw);
48 static void e1000_release_phy_82575(struct e1000_hw *hw);
49 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
50 static void e1000_release_nvm_82575(struct e1000_hw *hw);
51 static s32 e1000_check_for_link_82575(struct e1000_hw *hw);
52 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
53 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
55 static s32 e1000_init_hw_82575(struct e1000_hw *hw);
56 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
57 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
59 static s32 e1000_reset_hw_82575(struct e1000_hw *hw);
60 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
62 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
63 static s32 e1000_setup_fiber_serdes_link_82575(struct e1000_hw *hw);
64 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
65 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
66 u32 offset, u16 data);
67 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
68 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
69 static s32 e1000_configure_pcs_link_82575(struct e1000_hw *hw);
70 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
71 u16 *speed, u16 *duplex);
72 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
73 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
74 static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
75 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
76 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
77 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
79 static void e1000_init_rx_addrs_82575(struct e1000_hw *hw, u16 rar_count);
80 static void e1000_update_mc_addr_list_82575(struct e1000_hw *hw,
81 u8 *mc_addr_list, u32 mc_addr_count,
82 u32 rar_used_count, u32 rar_count);
83 void e1000_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw);
86 * e1000_init_phy_params_82575 - Init PHY func ptrs.
87 * @hw: pointer to the HW structure
89 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
91 struct e1000_phy_info *phy = &hw->phy;
92 s32 ret_val = E1000_SUCCESS;
94 DEBUGFUNC("e1000_init_phy_params_82575");
96 if (hw->phy.media_type != e1000_media_type_copper) {
97 phy->type = e1000_phy_none;
100 phy->ops.power_up = e1000_power_up_phy_copper;
101 phy->ops.power_down = e1000_power_down_phy_copper_82575;
104 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
105 phy->reset_delay_us = 100;
107 phy->ops.acquire = e1000_acquire_phy_82575;
108 phy->ops.check_reset_block = e1000_check_reset_block_generic;
109 phy->ops.commit = e1000_phy_sw_reset_generic;
110 phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
111 phy->ops.release = e1000_release_phy_82575;
113 if (e1000_sgmii_active_82575(hw)) {
114 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
115 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
116 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
118 phy->ops.reset = e1000_phy_hw_reset_generic;
119 phy->ops.read_reg = e1000_read_phy_reg_igp;
120 phy->ops.write_reg = e1000_write_phy_reg_igp;
123 /* Set phy->phy_addr and phy->id. */
124 ret_val = e1000_get_phy_id_82575(hw);
126 /* Verify phy id and set remaining function pointers */
128 case M88E1111_I_PHY_ID:
129 phy->type = e1000_phy_m88;
130 phy->ops.check_polarity = e1000_check_polarity_m88;
131 phy->ops.get_info = e1000_get_phy_info_m88;
132 phy->ops.get_cable_length = e1000_get_cable_length_m88;
133 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
135 case IGP03E1000_E_PHY_ID:
136 case IGP04E1000_E_PHY_ID:
137 phy->type = e1000_phy_igp_3;
138 phy->ops.check_polarity = e1000_check_polarity_igp;
139 phy->ops.get_info = e1000_get_phy_info_igp;
140 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
141 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
142 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
143 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
146 ret_val = -E1000_ERR_PHY;
155 * e1000_init_nvm_params_82575 - Init NVM func ptrs.
156 * @hw: pointer to the HW structure
158 static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
160 struct e1000_nvm_info *nvm = &hw->nvm;
161 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
164 DEBUGFUNC("e1000_init_nvm_params_82575");
166 nvm->opcode_bits = 8;
168 switch (nvm->override) {
169 case e1000_nvm_override_spi_large:
171 nvm->address_bits = 16;
173 case e1000_nvm_override_spi_small:
175 nvm->address_bits = 8;
178 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
179 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
183 nvm->type = e1000_nvm_eeprom_spi;
185 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
186 E1000_EECD_SIZE_EX_SHIFT);
189 * Added to a constant, "size" becomes the left-shift value
190 * for setting word_size.
192 size += NVM_WORD_SIZE_BASE_SHIFT;
194 /* EEPROM access above 16k is unsupported */
197 nvm->word_size = 1 << size;
199 /* Function Pointers */
200 nvm->ops.acquire = e1000_acquire_nvm_82575;
201 nvm->ops.read = e1000_read_nvm_eerd;
202 nvm->ops.release = e1000_release_nvm_82575;
203 nvm->ops.update = e1000_update_nvm_checksum_generic;
204 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
205 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
206 nvm->ops.write = e1000_write_nvm_spi;
208 return E1000_SUCCESS;
212 * e1000_init_mac_params_82575 - Init MAC func ptrs.
213 * @hw: pointer to the HW structure
215 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
217 struct e1000_mac_info *mac = &hw->mac;
218 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
221 DEBUGFUNC("e1000_init_mac_params_82575");
225 * The 82575 uses bits 22:23 for link mode. The mode can be changed
226 * based on the EEPROM. We cannot rely upon device ID. There
227 * is no distinguishable difference between fiber and internal
228 * SerDes mode on the 82575. There can be an external PHY attached
229 * on the SGMII interface. For this, we'll set sgmii_active to TRUE.
231 hw->phy.media_type = e1000_media_type_copper;
232 dev_spec->sgmii_active = FALSE;
234 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
235 if ((ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) ==
236 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES) {
237 hw->phy.media_type = e1000_media_type_internal_serdes;
238 ctrl_ext |= E1000_CTRL_I2C_ENA;
239 } else if (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII) {
240 dev_spec->sgmii_active = TRUE;
241 ctrl_ext |= E1000_CTRL_I2C_ENA;
243 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
245 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
247 /* Set mta register count */
248 mac->mta_reg_count = 128;
249 /* Set rar entry count */
250 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
251 if (mac->type == e1000_82576)
252 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
253 /* Set if part includes ASF firmware */
254 mac->asf_firmware_present = TRUE;
255 /* Set if manageability features are enabled. */
256 mac->arc_subsystem_valid =
257 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
260 /* Function pointers */
262 /* bus type/speed/width */
263 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
265 mac->ops.reset_hw = e1000_reset_hw_82575;
266 /* hw initialization */
267 mac->ops.init_hw = e1000_init_hw_82575;
269 mac->ops.setup_link = e1000_setup_link_generic;
270 /* physical interface link setup */
271 mac->ops.setup_physical_interface =
272 (hw->phy.media_type == e1000_media_type_copper)
273 ? e1000_setup_copper_link_82575
274 : e1000_setup_fiber_serdes_link_82575;
275 /* physical interface shutdown */
276 mac->ops.shutdown_serdes = e1000_shutdown_fiber_serdes_link_82575;
278 mac->ops.check_for_link = e1000_check_for_link_82575;
279 /* receive address register setting */
280 mac->ops.rar_set = e1000_rar_set_generic;
281 /* read mac address */
282 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
283 /* multicast address update */
284 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_82575;
286 mac->ops.write_vfta = e1000_write_vfta_generic;
288 mac->ops.clear_vfta = e1000_clear_vfta_generic;
290 mac->ops.mta_set = e1000_mta_set_generic;
292 mac->ops.blink_led = e1000_blink_led_generic;
294 mac->ops.setup_led = e1000_setup_led_generic;
296 mac->ops.cleanup_led = e1000_cleanup_led_generic;
297 /* turn on/off LED */
298 mac->ops.led_on = e1000_led_on_generic;
299 mac->ops.led_off = e1000_led_off_generic;
300 /* clear hardware counters */
301 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
303 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
305 return E1000_SUCCESS;
309 * e1000_init_function_pointers_82575 - Init func ptrs.
310 * @hw: pointer to the HW structure
312 * Called to initialize all function pointers and parameters.
314 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
316 DEBUGFUNC("e1000_init_function_pointers_82575");
318 hw->mac.ops.init_params = e1000_init_mac_params_82575;
319 hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
320 hw->phy.ops.init_params = e1000_init_phy_params_82575;
324 * e1000_acquire_phy_82575 - Acquire rights to access PHY
325 * @hw: pointer to the HW structure
327 * Acquire access rights to the correct PHY.
329 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
333 DEBUGFUNC("e1000_acquire_phy_82575");
335 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
337 return e1000_acquire_swfw_sync_82575(hw, mask);
341 * e1000_release_phy_82575 - Release rights to access PHY
342 * @hw: pointer to the HW structure
344 * A wrapper to release access rights to the correct PHY.
346 static void e1000_release_phy_82575(struct e1000_hw *hw)
350 DEBUGFUNC("e1000_release_phy_82575");
352 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
353 e1000_release_swfw_sync_82575(hw, mask);
357 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
358 * @hw: pointer to the HW structure
359 * @offset: register offset to be read
360 * @data: pointer to the read data
362 * Reads the PHY register at offset using the serial gigabit media independent
363 * interface and stores the retrieved information in data.
365 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
368 struct e1000_phy_info *phy = &hw->phy;
371 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
373 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
374 DEBUGOUT1("PHY Address %u is out of range\n", offset);
375 return -E1000_ERR_PARAM;
379 * Set up Op-code, Phy Address, and register address in the I2CCMD
380 * register. The MAC will take care of interfacing with the
381 * PHY to retrieve the desired data.
383 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
384 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
385 (E1000_I2CCMD_OPCODE_READ));
387 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
389 /* Poll the ready bit to see if the I2C read completed */
390 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
392 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
393 if (i2ccmd & E1000_I2CCMD_READY)
396 if (!(i2ccmd & E1000_I2CCMD_READY)) {
397 DEBUGOUT("I2CCMD Read did not complete\n");
398 return -E1000_ERR_PHY;
400 if (i2ccmd & E1000_I2CCMD_ERROR) {
401 DEBUGOUT("I2CCMD Error bit set\n");
402 return -E1000_ERR_PHY;
405 /* Need to byte-swap the 16-bit value. */
406 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
408 return E1000_SUCCESS;
412 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
413 * @hw: pointer to the HW structure
414 * @offset: register offset to write to
415 * @data: data to write at register offset
417 * Writes the data to PHY register at the offset using the serial gigabit
418 * media independent interface.
420 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
423 struct e1000_phy_info *phy = &hw->phy;
425 u16 phy_data_swapped;
427 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
429 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
430 DEBUGOUT1("PHY Address %d is out of range\n", offset);
431 return -E1000_ERR_PARAM;
434 /* Swap the data bytes for the I2C interface */
435 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
438 * Set up Op-code, Phy Address, and register address in the I2CCMD
439 * register. The MAC will take care of interfacing with the
440 * PHY to retrieve the desired data.
442 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
443 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
444 E1000_I2CCMD_OPCODE_WRITE |
447 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
449 /* Poll the ready bit to see if the I2C read completed */
450 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
452 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
453 if (i2ccmd & E1000_I2CCMD_READY)
456 if (!(i2ccmd & E1000_I2CCMD_READY)) {
457 DEBUGOUT("I2CCMD Write did not complete\n");
458 return -E1000_ERR_PHY;
460 if (i2ccmd & E1000_I2CCMD_ERROR) {
461 DEBUGOUT("I2CCMD Error bit set\n");
462 return -E1000_ERR_PHY;
465 return E1000_SUCCESS;
469 * e1000_get_phy_id_82575 - Retrieve PHY addr and id
470 * @hw: pointer to the HW structure
472 * Retrieves the PHY address and ID for both PHY's which do and do not use
475 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
477 struct e1000_phy_info *phy = &hw->phy;
478 s32 ret_val = E1000_SUCCESS;
481 DEBUGFUNC("e1000_get_phy_id_82575");
484 * For SGMII PHYs, we try the list of possible addresses until
485 * we find one that works. For non-SGMII PHYs
486 * (e.g. integrated copper PHYs), an address of 1 should
487 * work. The result of this function should mean phy->phy_addr
488 * and phy->id are set correctly.
490 if (!(e1000_sgmii_active_82575(hw))) {
492 ret_val = e1000_get_phy_id(hw);
497 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
498 * Therefore, we need to test 1-7
500 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
501 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
502 if (ret_val == E1000_SUCCESS) {
503 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
507 * At the time of this writing, The M88 part is
508 * the only supported SGMII PHY product.
510 if (phy_id == M88_VENDOR)
513 DEBUGOUT1("PHY address %u was unreadable\n",
518 /* A valid PHY type couldn't be found. */
519 if (phy->addr == 8) {
521 ret_val = -E1000_ERR_PHY;
525 ret_val = e1000_get_phy_id(hw);
532 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
533 * @hw: pointer to the HW structure
535 * Resets the PHY using the serial gigabit media independent interface.
537 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
539 s32 ret_val = E1000_SUCCESS;
541 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
544 * This isn't a TRUE "hard" reset, but is the only reset
545 * available to us at this time.
548 DEBUGOUT("Soft resetting SGMII attached PHY...\n");
550 if (!(hw->phy.ops.write_reg))
554 * SFP documentation requires the following to configure the SPF module
555 * to work on SGMII. No further documentation is given.
557 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
561 ret_val = hw->phy.ops.commit(hw);
568 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
569 * @hw: pointer to the HW structure
570 * @active: TRUE to enable LPLU, FALSE to disable
572 * Sets the LPLU D0 state according to the active flag. When
573 * activating LPLU this function also disables smart speed
574 * and vice versa. LPLU will not be activated unless the
575 * device autonegotiation advertisement meets standards of
576 * either 10 or 10/100 or 10/100/1000 at all duplexes.
577 * This is a function pointer entry point only called by
578 * PHY setup routines.
580 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
582 struct e1000_phy_info *phy = &hw->phy;
583 s32 ret_val = E1000_SUCCESS;
586 DEBUGFUNC("e1000_set_d0_lplu_state_82575");
588 if (!(hw->phy.ops.read_reg))
591 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
596 data |= IGP02E1000_PM_D0_LPLU;
597 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
602 /* When LPLU is enabled, we should disable SmartSpeed */
603 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
605 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
606 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
611 data &= ~IGP02E1000_PM_D0_LPLU;
612 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
615 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
616 * during Dx states where the power conservation is most
617 * important. During driver activity we should enable
618 * SmartSpeed, so performance is maintained.
620 if (phy->smart_speed == e1000_smart_speed_on) {
621 ret_val = phy->ops.read_reg(hw,
622 IGP01E1000_PHY_PORT_CONFIG,
627 data |= IGP01E1000_PSCFR_SMART_SPEED;
628 ret_val = phy->ops.write_reg(hw,
629 IGP01E1000_PHY_PORT_CONFIG,
633 } else if (phy->smart_speed == e1000_smart_speed_off) {
634 ret_val = phy->ops.read_reg(hw,
635 IGP01E1000_PHY_PORT_CONFIG,
640 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
641 ret_val = phy->ops.write_reg(hw,
642 IGP01E1000_PHY_PORT_CONFIG,
654 * e1000_acquire_nvm_82575 - Request for access to EEPROM
655 * @hw: pointer to the HW structure
657 * Acquire the necessary semaphores for exclusive access to the EEPROM.
658 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
659 * Return successful if access grant bit set, else clear the request for
660 * EEPROM access and return -E1000_ERR_NVM (-1).
662 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
666 DEBUGFUNC("e1000_acquire_nvm_82575");
668 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
672 ret_val = e1000_acquire_nvm_generic(hw);
675 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
682 * e1000_release_nvm_82575 - Release exclusive access to EEPROM
683 * @hw: pointer to the HW structure
685 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
686 * then release the semaphores acquired.
688 static void e1000_release_nvm_82575(struct e1000_hw *hw)
690 DEBUGFUNC("e1000_release_nvm_82575");
692 e1000_release_nvm_generic(hw);
693 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
697 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
698 * @hw: pointer to the HW structure
699 * @mask: specifies which semaphore to acquire
701 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
702 * will also specify which port we're acquiring the lock for.
704 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
708 u32 fwmask = mask << 16;
709 s32 ret_val = E1000_SUCCESS;
710 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
712 DEBUGFUNC("e1000_acquire_swfw_sync_82575");
714 while (i < timeout) {
715 if (e1000_get_hw_semaphore_generic(hw)) {
716 ret_val = -E1000_ERR_SWFW_SYNC;
720 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
721 if (!(swfw_sync & (fwmask | swmask)))
725 * Firmware currently using resource (fwmask)
726 * or other software thread using resource (swmask)
728 e1000_put_hw_semaphore_generic(hw);
734 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
735 ret_val = -E1000_ERR_SWFW_SYNC;
740 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
742 e1000_put_hw_semaphore_generic(hw);
749 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore
750 * @hw: pointer to the HW structure
751 * @mask: specifies which semaphore to acquire
753 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
754 * will also specify which port we're releasing the lock for.
756 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
760 DEBUGFUNC("e1000_release_swfw_sync_82575");
762 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS);
765 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
767 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
769 e1000_put_hw_semaphore_generic(hw);
773 * e1000_get_cfg_done_82575 - Read config done bit
774 * @hw: pointer to the HW structure
776 * Read the management control register for the config done bit for
777 * completion status. NOTE: silicon which is EEPROM-less will fail trying
778 * to read the config done bit, so an error is *ONLY* logged and returns
779 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
780 * would not be able to be reset or change link.
782 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
784 s32 timeout = PHY_CFG_TIMEOUT;
785 s32 ret_val = E1000_SUCCESS;
786 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
788 DEBUGFUNC("e1000_get_cfg_done_82575");
790 if (hw->bus.func == 1)
791 mask = E1000_NVM_CFG_DONE_PORT_1;
794 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
800 DEBUGOUT("MNG configuration cycle has not completed.\n");
803 /* If EEPROM is not marked present, init the PHY manually */
804 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) &&
805 (hw->phy.type == e1000_phy_igp_3)) {
806 e1000_phy_init_script_igp3(hw);
813 * e1000_get_link_up_info_82575 - Get link speed/duplex info
814 * @hw: pointer to the HW structure
815 * @speed: stores the current speed
816 * @duplex: stores the current duplex
818 * This is a wrapper function, if using the serial gigabit media independent
819 * interface, use PCS to retrieve the link speed and duplex information.
820 * Otherwise, use the generic function to get the link speed and duplex info.
822 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
827 DEBUGFUNC("e1000_get_link_up_info_82575");
829 if (hw->phy.media_type != e1000_media_type_copper ||
830 e1000_sgmii_active_82575(hw)) {
831 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
834 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
842 * e1000_check_for_link_82575 - Check for link
843 * @hw: pointer to the HW structure
845 * If sgmii is enabled, then use the pcs register to determine link, otherwise
846 * use the generic interface for determining link.
848 static s32 e1000_check_for_link_82575(struct e1000_hw *hw)
853 DEBUGFUNC("e1000_check_for_link_82575");
855 /* SGMII link check is done through the PCS register. */
856 if ((hw->phy.media_type != e1000_media_type_copper) ||
857 (e1000_sgmii_active_82575(hw)))
858 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
861 ret_val = e1000_check_for_copper_link_generic(hw);
867 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
868 * @hw: pointer to the HW structure
869 * @speed: stores the current speed
870 * @duplex: stores the current duplex
872 * Using the physical coding sub-layer (PCS), retrieve the current speed and
873 * duplex, then store the values in the pointers provided.
875 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
876 u16 *speed, u16 *duplex)
878 struct e1000_mac_info *mac = &hw->mac;
881 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
883 /* Set up defaults for the return values of this function */
884 mac->serdes_has_link = FALSE;
889 * Read the PCS Status register for link state. For non-copper mode,
890 * the status register is not accurate. The PCS status register is
893 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
896 * The link up bit determines when link is up on autoneg. The sync ok
897 * gets set once both sides sync up and agree upon link. Stable link
898 * can be determined by checking for both link up and link sync ok
900 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
901 mac->serdes_has_link = TRUE;
903 /* Detect and store PCS speed */
904 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
906 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
912 /* Detect and store PCS duplex */
913 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
914 *duplex = FULL_DUPLEX;
916 *duplex = HALF_DUPLEX;
920 return E1000_SUCCESS;
924 * e1000_init_rx_addrs_82575 - Initialize receive address's
925 * @hw: pointer to the HW structure
926 * @rar_count: receive address registers
928 * Setups the receive address registers by setting the base receive address
929 * register to the devices MAC address and clearing all the other receive
930 * address registers to 0.
932 static void e1000_init_rx_addrs_82575(struct e1000_hw *hw, u16 rar_count)
935 u8 addr[6] = {0,0,0,0,0,0};
937 * This function is essentially the same as that of
938 * e1000_init_rx_addrs_generic. However it also takes care
939 * of the special case where the register offset of the
940 * second set of RARs begins elsewhere. This is implicitly taken care by
941 * function e1000_rar_set_generic.
944 DEBUGFUNC("e1000_init_rx_addrs_82575");
946 /* Setup the receive address */
947 DEBUGOUT("Programming MAC Address into RAR[0]\n");
948 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
950 /* Zero out the other (rar_entry_count - 1) receive addresses */
951 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
952 for (i = 1; i < rar_count; i++) {
953 hw->mac.ops.rar_set(hw, addr, i);
958 * e1000_update_mc_addr_list_82575 - Update Multicast addresses
959 * @hw: pointer to the HW structure
960 * @mc_addr_list: array of multicast addresses to program
961 * @mc_addr_count: number of multicast addresses to program
962 * @rar_used_count: the first RAR register free to program
963 * @rar_count: total number of supported Receive Address Registers
965 * Updates the Receive Address Registers and Multicast Table Array.
966 * The caller must have a packed mc_addr_list of multicast addresses.
967 * The parameter rar_count will usually be hw->mac.rar_entry_count
968 * unless there are workarounds that change this.
970 static void e1000_update_mc_addr_list_82575(struct e1000_hw *hw,
971 u8 *mc_addr_list, u32 mc_addr_count,
972 u32 rar_used_count, u32 rar_count)
976 u8 addr[6] = {0,0,0,0,0,0};
978 * This function is essentially the same as that of
979 * e1000_update_mc_addr_list_generic. However it also takes care
980 * of the special case where the register offset of the
981 * second set of RARs begins elsewhere. This is implicitly taken care by
982 * function e1000_rar_set_generic.
985 DEBUGFUNC("e1000_update_mc_addr_list_82575");
988 * Load the first set of multicast addresses into the exact
989 * filters (RAR). If there are not enough to fill the RAR
990 * array, clear the filters.
992 for (i = rar_used_count; i < rar_count; i++) {
994 e1000_rar_set_generic(hw, mc_addr_list, i);
996 mc_addr_list += ETH_ADDR_LEN;
998 e1000_rar_set_generic(hw, addr, i);
1002 /* Clear the old settings from the MTA */
1003 DEBUGOUT("Clearing MTA\n");
1004 for (i = 0; i < hw->mac.mta_reg_count; i++) {
1005 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1006 E1000_WRITE_FLUSH(hw);
1009 /* Load any remaining multicast addresses into the hash table. */
1010 for (; mc_addr_count > 0; mc_addr_count--) {
1011 hash_value = e1000_hash_mc_addr(hw, mc_addr_list);
1012 DEBUGOUT1("Hash value = 0x%03X\n", hash_value);
1013 hw->mac.ops.mta_set(hw, hash_value);
1014 mc_addr_list += ETH_ADDR_LEN;
1019 * e1000_shutdown_fiber_serdes_link_82575 - Remove link during power down
1020 * @hw: pointer to the HW structure
1022 * In the case of fiber serdes shut down optics and PCS on driver unload
1023 * when management pass thru is not enabled.
1025 void e1000_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw)
1028 u16 eeprom_data = 0;
1030 if (hw->mac.type != e1000_82576 ||
1031 (hw->phy.media_type != e1000_media_type_fiber &&
1032 hw->phy.media_type != e1000_media_type_internal_serdes))
1035 if (hw->bus.func == 0)
1036 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
1039 * If APM is not enabled in the EEPROM and management interface is
1040 * not enabled, then power down.
1042 if (!(eeprom_data & E1000_NVM_APME_82575) &&
1043 !e1000_enable_mng_pass_thru(hw)) {
1044 /* Disable PCS to turn off link */
1045 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1046 reg &= ~E1000_PCS_CFG_PCS_EN;
1047 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1049 /* shutdown the laser */
1050 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1051 reg |= E1000_CTRL_EXT_SDP7_DATA;
1052 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1054 /* flush the write to verfiy completion */
1055 E1000_WRITE_FLUSH(hw);
1063 * e1000_reset_hw_82575 - Reset hardware
1064 * @hw: pointer to the HW structure
1066 * This resets the hardware into a known state.
1068 static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1073 DEBUGFUNC("e1000_reset_hw_82575");
1076 * Prevent the PCI-E bus from sticking if there is no TLP connection
1077 * on the last TLP read/write transaction when MAC is reset.
1079 ret_val = e1000_disable_pcie_master_generic(hw);
1081 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1084 DEBUGOUT("Masking off all interrupts\n");
1085 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1087 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1088 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1089 E1000_WRITE_FLUSH(hw);
1093 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1095 DEBUGOUT("Issuing a global reset to MAC\n");
1096 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1098 ret_val = e1000_get_auto_rd_done_generic(hw);
1101 * When auto config read does not complete, do not
1102 * return with an error. This can happen in situations
1103 * where there is no eeprom and prevents getting link.
1105 DEBUGOUT("Auto Read Done did not complete\n");
1108 /* If EEPROM is not present, run manual init scripts */
1109 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0)
1110 e1000_reset_init_script_82575(hw);
1112 /* Clear any pending interrupt events. */
1113 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1114 icr = E1000_READ_REG(hw, E1000_ICR);
1116 e1000_check_alt_mac_addr_generic(hw);
1122 * e1000_init_hw_82575 - Initialize hardware
1123 * @hw: pointer to the HW structure
1125 * This inits the hardware readying it for operation.
1127 static s32 e1000_init_hw_82575(struct e1000_hw *hw)
1129 struct e1000_mac_info *mac = &hw->mac;
1131 u16 i, rar_count = mac->rar_entry_count;
1133 DEBUGFUNC("e1000_init_hw_82575");
1135 /* Initialize identification LED */
1136 ret_val = e1000_id_led_init_generic(hw);
1138 DEBUGOUT("Error initializing identification LED\n");
1139 /* This is not fatal and we should not stop init due to this */
1142 /* Disabling VLAN filtering */
1143 DEBUGOUT("Initializing the IEEE VLAN\n");
1144 mac->ops.clear_vfta(hw);
1146 /* Setup the receive address */
1147 e1000_init_rx_addrs_82575(hw, rar_count);
1148 /* Zero out the Multicast HASH table */
1149 DEBUGOUT("Zeroing the MTA\n");
1150 for (i = 0; i < mac->mta_reg_count; i++)
1151 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1153 /* Setup link and flow control */
1154 ret_val = mac->ops.setup_link(hw);
1157 * Clear all of the statistics registers (clear on read). It is
1158 * important that we do this after we have tried to establish link
1159 * because the symbol error count will increment wildly if there
1162 e1000_clear_hw_cntrs_82575(hw);
1168 * e1000_setup_copper_link_82575 - Configure copper link settings
1169 * @hw: pointer to the HW structure
1171 * Configures the link for auto-neg or forced speed and duplex. Then we check
1172 * for link, once link is established calls to configure collision distance
1173 * and flow control are called.
1175 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1181 DEBUGFUNC("e1000_setup_copper_link_82575");
1183 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1184 ctrl |= E1000_CTRL_SLU;
1185 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1186 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1188 switch (hw->phy.type) {
1190 ret_val = e1000_copper_link_setup_m88(hw);
1192 case e1000_phy_igp_3:
1193 ret_val = e1000_copper_link_setup_igp(hw);
1194 /* Setup activity LED */
1195 led_ctrl = E1000_READ_REG(hw, E1000_LEDCTL);
1196 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1197 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1198 E1000_WRITE_REG(hw, E1000_LEDCTL, led_ctrl);
1201 ret_val = -E1000_ERR_PHY;
1208 if (hw->mac.autoneg) {
1210 * Setup autoneg and flow control advertisement
1211 * and perform autonegotiation.
1213 ret_val = e1000_copper_link_autoneg(hw);
1218 * PHY will be set to 10H, 10F, 100H or 100F
1219 * depending on user settings.
1221 DEBUGOUT("Forcing Speed and Duplex\n");
1222 ret_val = hw->phy.ops.force_speed_duplex(hw);
1224 DEBUGOUT("Error Forcing Speed and Duplex\n");
1229 ret_val = e1000_configure_pcs_link_82575(hw);
1234 * Check link status. Wait up to 100 microseconds for link to become
1237 ret_val = e1000_phy_has_link_generic(hw,
1238 COPPER_LINK_UP_LIMIT,
1245 DEBUGOUT("Valid link established!!!\n");
1246 /* Config the MAC and PHY after link is up */
1247 e1000_config_collision_dist_generic(hw);
1248 ret_val = e1000_config_fc_after_link_up_generic(hw);
1250 DEBUGOUT("Unable to establish link!!!\n");
1258 * e1000_setup_fiber_serdes_link_82575 - Setup link for fiber/serdes
1259 * @hw: pointer to the HW structure
1261 * Configures speed and duplex for fiber and serdes links.
1263 static s32 e1000_setup_fiber_serdes_link_82575(struct e1000_hw *hw)
1267 DEBUGFUNC("e1000_setup_fiber_serdes_link_82575");
1270 * On the 82575, SerDes loopback mode persists until it is
1271 * explicitly turned off or a power cycle is performed. A read to
1272 * the register does not indicate its status. Therefore, we ensure
1273 * loopback mode is disabled during initialization.
1275 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1277 /* Force link up, set 1gb, set both sw defined pins */
1278 reg = E1000_READ_REG(hw, E1000_CTRL);
1279 reg |= E1000_CTRL_SLU |
1280 E1000_CTRL_SPD_1000 |
1282 E1000_CTRL_SWDPIN0 |
1284 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1286 /* Power on phy for 82576 fiber adapters */
1287 if (hw->mac.type == e1000_82576) {
1288 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1289 reg &= ~E1000_CTRL_EXT_SDP7_DATA;
1290 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1293 /* Set switch control to serdes energy detect */
1294 reg = E1000_READ_REG(hw, E1000_CONNSW);
1295 reg |= E1000_CONNSW_ENRGSRC;
1296 E1000_WRITE_REG(hw, E1000_CONNSW, reg);
1299 * New SerDes mode allows for forcing speed or autonegotiating speed
1300 * at 1gb. Autoneg should be default set by most drivers. This is the
1301 * mode that will be compatible with older link partners and switches.
1302 * However, both are supported by the hardware and some drivers/tools.
1304 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1306 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1307 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1309 if (hw->mac.autoneg) {
1310 /* Set PCS register for autoneg */
1311 reg |= E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1312 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1313 E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1314 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1315 DEBUGOUT1("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg);
1317 /* Set PCS register for forced speed */
1318 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1319 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1320 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1321 E1000_PCS_LCTL_FSD | /* Force Speed */
1322 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1323 DEBUGOUT1("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg);
1326 if (hw->mac.type == e1000_82576) {
1327 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1328 e1000_force_mac_fc_generic(hw);
1331 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1333 return E1000_SUCCESS;
1337 * e1000_valid_led_default_82575 - Verify a valid default LED config
1338 * @hw: pointer to the HW structure
1339 * @data: pointer to the NVM (EEPROM)
1341 * Read the EEPROM for the current default LED configuration. If the
1342 * LED configuration is not valid, set to a valid LED configuration.
1344 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1348 DEBUGFUNC("e1000_valid_led_default_82575");
1350 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1352 DEBUGOUT("NVM Read Error\n");
1356 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1357 switch(hw->phy.media_type) {
1358 case e1000_media_type_fiber:
1359 case e1000_media_type_internal_serdes:
1360 *data = ID_LED_DEFAULT_82575_SERDES;
1362 case e1000_media_type_copper:
1364 *data = ID_LED_DEFAULT;
1373 * e1000_configure_pcs_link_82575 - Configure PCS link
1374 * @hw: pointer to the HW structure
1376 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1377 * only used on copper connections where the serialized gigabit media
1378 * independent interface (sgmii) is being used. Configures the link
1379 * for auto-negotiation or forces speed/duplex.
1381 static s32 e1000_configure_pcs_link_82575(struct e1000_hw *hw)
1383 struct e1000_mac_info *mac = &hw->mac;
1386 DEBUGFUNC("e1000_configure_pcs_link_82575");
1388 if (hw->phy.media_type != e1000_media_type_copper ||
1389 !(e1000_sgmii_active_82575(hw)))
1392 /* For SGMII, we need to issue a PCS autoneg restart */
1393 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1395 /* AN time out should be disabled for SGMII mode */
1396 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1399 /* Make sure forced speed and force link are not set */
1400 reg &= ~(E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1403 * The PHY should be setup prior to calling this function.
1404 * All we need to do is restart autoneg and enable autoneg.
1406 reg |= E1000_PCS_LCTL_AN_RESTART | E1000_PCS_LCTL_AN_ENABLE;
1408 /* Set PCS register for forced speed */
1410 /* Turn off bits for full duplex, speed, and autoneg */
1411 reg &= ~(E1000_PCS_LCTL_FSV_1000 |
1412 E1000_PCS_LCTL_FSV_100 |
1413 E1000_PCS_LCTL_FDV_FULL |
1414 E1000_PCS_LCTL_AN_ENABLE);
1416 /* Check for duplex first */
1417 if (mac->forced_speed_duplex & E1000_ALL_FULL_DUPLEX)
1418 reg |= E1000_PCS_LCTL_FDV_FULL;
1421 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED)
1422 reg |= E1000_PCS_LCTL_FSV_100;
1424 /* Force speed and force link */
1425 reg |= E1000_PCS_LCTL_FSD |
1426 E1000_PCS_LCTL_FORCE_LINK |
1427 E1000_PCS_LCTL_FLV_LINK_UP;
1429 DEBUGOUT1("Wrote 0x%08X to PCS_LCTL to configure forced link\n",
1432 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1435 return E1000_SUCCESS;
1439 * e1000_sgmii_active_82575 - Return sgmii state
1440 * @hw: pointer to the HW structure
1442 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1443 * which can be enabled for use in the embedded applications. Simply
1444 * return the current state of the sgmii interface.
1446 static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1448 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1450 DEBUGFUNC("e1000_sgmii_active_82575");
1452 if (hw->mac.type != e1000_82575 && hw->mac.type != e1000_82576)
1455 return dev_spec->sgmii_active;
1459 * e1000_reset_init_script_82575 - Inits HW defaults after reset
1460 * @hw: pointer to the HW structure
1462 * Inits recommended HW defaults after a reset when there is no EEPROM
1463 * detected. This is only for the 82575.
1465 static s32 e1000_reset_init_script_82575(struct e1000_hw* hw)
1467 DEBUGFUNC("e1000_reset_init_script_82575");
1469 if (hw->mac.type == e1000_82575) {
1470 DEBUGOUT("Running reset init script for 82575\n");
1471 /* SerDes configuration via SERDESCTRL */
1472 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1473 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1474 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1475 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1477 /* CCM configuration via CCMCTL register */
1478 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1479 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1481 /* PCIe lanes configuration */
1482 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1483 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1484 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1485 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1487 /* PCIe PLL Configuration */
1488 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1489 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1490 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1493 return E1000_SUCCESS;
1497 * e1000_read_mac_addr_82575 - Read device MAC address
1498 * @hw: pointer to the HW structure
1500 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1502 s32 ret_val = E1000_SUCCESS;
1504 DEBUGFUNC("e1000_read_mac_addr_82575");
1505 if (e1000_check_alt_mac_addr_generic(hw))
1506 ret_val = e1000_read_mac_addr_generic(hw);
1512 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
1513 * @hw: pointer to the HW structure
1515 * In the case of a PHY power down to save power, or to turn off link during a
1516 * driver unload, or wake on lan is not enabled, remove the link.
1518 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
1520 struct e1000_phy_info *phy = &hw->phy;
1521 struct e1000_mac_info *mac = &hw->mac;
1523 if (!(phy->ops.check_reset_block))
1526 /* If the management interface is not enabled, then power down */
1527 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1528 e1000_power_down_phy_copper(hw);
1534 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
1535 * @hw: pointer to the HW structure
1537 * Clears the hardware counters by reading the counter registers.
1539 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
1541 DEBUGFUNC("e1000_clear_hw_cntrs_82575");
1543 e1000_clear_hw_cntrs_base_generic(hw);
1545 E1000_READ_REG(hw, E1000_PRC64);
1546 E1000_READ_REG(hw, E1000_PRC127);
1547 E1000_READ_REG(hw, E1000_PRC255);
1548 E1000_READ_REG(hw, E1000_PRC511);
1549 E1000_READ_REG(hw, E1000_PRC1023);
1550 E1000_READ_REG(hw, E1000_PRC1522);
1551 E1000_READ_REG(hw, E1000_PTC64);
1552 E1000_READ_REG(hw, E1000_PTC127);
1553 E1000_READ_REG(hw, E1000_PTC255);
1554 E1000_READ_REG(hw, E1000_PTC511);
1555 E1000_READ_REG(hw, E1000_PTC1023);
1556 E1000_READ_REG(hw, E1000_PTC1522);
1558 E1000_READ_REG(hw, E1000_ALGNERRC);
1559 E1000_READ_REG(hw, E1000_RXERRC);
1560 E1000_READ_REG(hw, E1000_TNCRS);
1561 E1000_READ_REG(hw, E1000_CEXTERR);
1562 E1000_READ_REG(hw, E1000_TSCTC);
1563 E1000_READ_REG(hw, E1000_TSCTFC);
1565 E1000_READ_REG(hw, E1000_MGTPRC);
1566 E1000_READ_REG(hw, E1000_MGTPDC);
1567 E1000_READ_REG(hw, E1000_MGTPTC);
1569 E1000_READ_REG(hw, E1000_IAC);
1570 E1000_READ_REG(hw, E1000_ICRXOC);
1572 E1000_READ_REG(hw, E1000_ICRXPTC);
1573 E1000_READ_REG(hw, E1000_ICRXATC);
1574 E1000_READ_REG(hw, E1000_ICTXPTC);
1575 E1000_READ_REG(hw, E1000_ICTXATC);
1576 E1000_READ_REG(hw, E1000_ICTXQEC);
1577 E1000_READ_REG(hw, E1000_ICTXQMTC);
1578 E1000_READ_REG(hw, E1000_ICRXDMTC);
1580 E1000_READ_REG(hw, E1000_CBTMPC);
1581 E1000_READ_REG(hw, E1000_HTDPMC);
1582 E1000_READ_REG(hw, E1000_CBRMPC);
1583 E1000_READ_REG(hw, E1000_RPTHC);
1584 E1000_READ_REG(hw, E1000_HGPTC);
1585 E1000_READ_REG(hw, E1000_HTCBDPC);
1586 E1000_READ_REG(hw, E1000_HGORCL);
1587 E1000_READ_REG(hw, E1000_HGORCH);
1588 E1000_READ_REG(hw, E1000_HGOTCL);
1589 E1000_READ_REG(hw, E1000_HGOTCH);
1590 E1000_READ_REG(hw, E1000_LENERRS);
1592 /* This register should not be read in copper configurations */
1593 if (hw->phy.media_type == e1000_media_type_internal_serdes)
1594 E1000_READ_REG(hw, E1000_SCVPC);
1597 * e1000_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1598 * @hw: pointer to the HW structure
1600 * After rx enable if managability is enabled then there is likely some
1601 * bad data at the start of the fifo and possibly in the DMA fifo. This
1602 * function clears the fifos and flushes any packets that came in as rx was
1605 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
1607 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1610 DEBUGFUNC("e1000_rx_fifo_workaround_82575");
1611 if (hw->mac.type != e1000_82575 ||
1612 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1615 /* Disable all RX queues */
1616 for (i = 0; i < 4; i++) {
1617 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
1618 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
1619 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1621 /* Poll all queues to verify they have shut down */
1622 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1625 for (i = 0; i < 4; i++)
1626 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
1627 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1632 DEBUGOUT("Queue disable timed out after 10ms\n");
1634 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1635 * incoming packets are rejected. Set enable and wait 2ms so that
1636 * any packet that was coming in as RCTL.EN was set is flushed
1638 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
1639 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1641 rlpml = E1000_READ_REG(hw, E1000_RLPML);
1642 E1000_WRITE_REG(hw, E1000_RLPML, 0);
1644 rctl = E1000_READ_REG(hw, E1000_RCTL);
1645 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1646 temp_rctl |= E1000_RCTL_LPE;
1648 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
1649 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1650 E1000_WRITE_FLUSH(hw);
1653 /* Enable RX queues that were previously enabled and restore our
1656 for (i = 0; i < 4; i++)
1657 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
1658 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1659 E1000_WRITE_FLUSH(hw);
1661 E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
1662 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
1664 /* Flush receive errors generated by workaround */
1665 E1000_READ_REG(hw, E1000_ROC);
1666 E1000_READ_REG(hw, E1000_RNBC);
1667 E1000_READ_REG(hw, E1000_MPC);