1 /* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
37 /* Define the specific costs for a given cpu */
39 struct processor_costs {
40 const int add; /* cost of an add instruction */
41 const int lea; /* cost of a lea instruction */
42 const int shift_var; /* variable shift costs */
43 const int shift_const; /* constant shift costs */
44 const int mult_init[5]; /* cost of starting a multiply
45 in QImode, HImode, SImode, DImode, TImode*/
46 const int mult_bit; /* cost of multiply per each bit set */
47 const int divide[5]; /* cost of a divide/mod
48 in QImode, HImode, SImode, DImode, TImode*/
49 int movsx; /* The cost of movsx operation. */
50 int movzx; /* The cost of movzx operation. */
51 const int large_insn; /* insns larger than this cost more */
52 const int move_ratio; /* The threshold of number of scalar
53 memory-to-memory move insns. */
54 const int movzbl_load; /* cost of loading using movzbl */
55 const int int_load[3]; /* cost of loading integer registers
56 in QImode, HImode and SImode relative
57 to reg-reg move (2). */
58 const int int_store[3]; /* cost of storing integer register
59 in QImode, HImode and SImode */
60 const int fp_move; /* cost of reg,reg fld/fst */
61 const int fp_load[3]; /* cost of loading FP register
62 in SFmode, DFmode and XFmode */
63 const int fp_store[3]; /* cost of storing FP register
64 in SFmode, DFmode and XFmode */
65 const int mmx_move; /* cost of moving MMX register. */
66 const int mmx_load[2]; /* cost of loading MMX register
67 in SImode and DImode */
68 const int mmx_store[2]; /* cost of storing MMX register
69 in SImode and DImode */
70 const int sse_move; /* cost of moving SSE register. */
71 const int sse_load[3]; /* cost of loading SSE register
72 in SImode, DImode and TImode*/
73 const int sse_store[3]; /* cost of storing SSE register
74 in SImode, DImode and TImode*/
75 const int mmxsse_to_integer; /* cost of moving mmxsse register to
76 integer and vice versa. */
77 const int prefetch_block; /* bytes moved to cache for prefetch. */
78 const int simultaneous_prefetches; /* number of parallel prefetch
80 const int branch_cost; /* Default value for BRANCH_COST. */
81 const int fadd; /* cost of FADD and FSUB instructions. */
82 const int fmul; /* cost of FMUL instruction. */
83 const int fdiv; /* cost of FDIV instruction. */
84 const int fabs; /* cost of FABS instruction. */
85 const int fchs; /* cost of FCHS instruction. */
86 const int fsqrt; /* cost of FSQRT instruction. */
89 extern const struct processor_costs *ix86_cost;
91 /* Run-time compilation parameters selecting different hardware subsets. */
93 extern int target_flags;
95 /* Macros used in the machine description to test the flags. */
97 /* configure can arrange to make this 2, to force a 486. */
99 #ifndef TARGET_CPU_DEFAULT
100 #ifdef TARGET_64BIT_DEFAULT
101 #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_k8
103 #define TARGET_CPU_DEFAULT 0
107 /* Masks for the -m switches */
108 #define MASK_80387 0x00000001 /* Hardware floating point */
109 #define MASK_RTD 0x00000002 /* Use ret that pops args */
110 #define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */
111 #define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */
112 #define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */
113 #define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */
114 #define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */
115 #define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */
116 #define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */
117 #define MASK_NO_ALIGN_STROPS 0x00000200 /* Enable aligning of string ops. */
118 #define MASK_INLINE_ALL_STROPS 0x00000400 /* Inline stringops in all cases */
119 #define MASK_NO_PUSH_ARGS 0x00000800 /* Use push instructions */
120 #define MASK_ACCUMULATE_OUTGOING_ARGS 0x00001000/* Accumulate outgoing args */
121 #define MASK_MMX 0x00002000 /* Support MMX regs/builtins */
122 #define MASK_SSE 0x00004000 /* Support SSE regs/builtins */
123 #define MASK_SSE2 0x00008000 /* Support SSE2 regs/builtins */
124 #define MASK_SSE3 0x00010000 /* Support SSE3 regs/builtins */
125 #define MASK_3DNOW 0x00020000 /* Support 3Dnow builtins */
126 #define MASK_3DNOW_A 0x00040000 /* Support Athlon 3Dnow builtins */
127 #define MASK_128BIT_LONG_DOUBLE 0x00080000 /* long double size is 128bit */
128 #define MASK_64BIT 0x00100000 /* Produce 64bit code */
129 #define MASK_MS_BITFIELD_LAYOUT 0x00200000 /* Use native (MS) bitfield layout */
130 #define MASK_TLS_DIRECT_SEG_REFS 0x00400000 /* Avoid adding %gs:0 */
132 /* Unused: 0x03e0000 */
134 /* ... overlap with subtarget options starts by 0x04000000. */
135 #define MASK_NO_RED_ZONE 0x04000000 /* Do not use red zone */
137 /* Use the floating point instructions */
138 #define TARGET_80387 (target_flags & MASK_80387)
140 /* Compile using ret insn that pops args.
141 This will not work unless you use prototypes at least
142 for all functions that can take varying numbers of args. */
143 #define TARGET_RTD (target_flags & MASK_RTD)
145 /* Align doubles to a two word boundary. This breaks compatibility with
146 the published ABI's for structures containing doubles, but produces
147 faster code on the pentium. */
148 #define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE)
150 /* Use push instructions to save outgoing args. */
151 #define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS))
153 /* Accumulate stack adjustments to prologue/epilogue. */
154 #define TARGET_ACCUMULATE_OUTGOING_ARGS \
155 (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS)
157 /* Put uninitialized locals into bss, not data.
158 Meaningful only on svr3. */
159 #define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB)
161 /* Use IEEE floating point comparisons. These handle correctly the cases
162 where the result of a comparison is unordered. Normally SIGFPE is
163 generated in such cases, in which case this isn't needed. */
164 #define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP)
166 /* Functions that return a floating point value may return that value
167 in the 387 FPU or in 386 integer registers. If set, this flag causes
168 the 387 to be used, which is compatible with most calling conventions. */
169 #define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS)
171 /* Long double is 128bit instead of 96bit, even when only 80bits are used.
172 This mode wastes cache, but avoid misaligned data accesses and simplifies
173 address calculations. */
174 #define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE)
176 /* Disable generation of FP sin, cos and sqrt operations for 387.
177 This is because FreeBSD lacks these in the math-emulator-code */
178 #define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387)
180 /* Generate 387 floating point intrinsics for the current target. */
181 #define TARGET_USE_FANCY_MATH_387 (! TARGET_NO_FANCY_MATH_387)
183 /* Don't create frame pointers for leaf functions */
184 #define TARGET_OMIT_LEAF_FRAME_POINTER \
185 (target_flags & MASK_OMIT_LEAF_FRAME_POINTER)
187 /* Debug GO_IF_LEGITIMATE_ADDRESS */
188 #define TARGET_DEBUG_ADDR (ix86_debug_addr_string != 0)
190 /* Debug FUNCTION_ARG macros */
191 #define TARGET_DEBUG_ARG (ix86_debug_arg_string != 0)
193 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
194 compile-time constant. */
197 #define TARGET_64BIT 1
199 #define TARGET_64BIT 0
202 #ifdef TARGET_BI_ARCH
203 #define TARGET_64BIT (target_flags & MASK_64BIT)
205 #if TARGET_64BIT_DEFAULT
206 #define TARGET_64BIT 1
208 #define TARGET_64BIT 0
213 #define HAS_LONG_COND_BRANCH 1
214 #define HAS_LONG_UNCOND_BRANCH 1
216 /* Avoid adding %gs:0 in TLS references; use %gs:address directly. */
217 #define TARGET_TLS_DIRECT_SEG_REFS (target_flags & MASK_TLS_DIRECT_SEG_REFS)
219 #define TARGET_386 (ix86_tune == PROCESSOR_I386)
220 #define TARGET_486 (ix86_tune == PROCESSOR_I486)
221 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
222 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
223 #define TARGET_K6 (ix86_tune == PROCESSOR_K6)
224 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
225 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
226 #define TARGET_K8 (ix86_tune == PROCESSOR_K8)
227 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
228 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
230 #define TUNEMASK (1 << ix86_tune)
231 extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
232 extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
233 extern const int x86_branch_hints, x86_unroll_strlen;
234 extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
235 extern const int x86_use_loop, x86_use_fiop, x86_use_mov0;
236 extern const int x86_use_cltd, x86_read_modify_write;
237 extern const int x86_read_modify, x86_split_long_moves;
238 extern const int x86_promote_QImode, x86_single_stringop, x86_fast_prefix;
239 extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs;
240 extern const int x86_promote_hi_regs, x86_integer_DFmode_moves;
241 extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8;
242 extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
243 extern const int x86_accumulate_outgoing_args, x86_prologue_using_move;
244 extern const int x86_epilogue_using_move, x86_decompose_lea;
245 extern const int x86_arch_always_fancy_math_387, x86_shift1;
246 extern const int x86_sse_partial_reg_dependency, x86_sse_split_regs;
247 extern const int x86_sse_typeless_stores, x86_sse_load0_by_pxor;
248 extern const int x86_use_ffreep;
249 extern const int x86_inter_unit_moves, x86_schedule;
250 extern const int x86_use_bt;
251 extern int x86_prefetch_sse;
253 #define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK)
254 #define TARGET_PUSH_MEMORY (x86_push_memory & TUNEMASK)
255 #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & TUNEMASK)
256 #define TARGET_USE_BIT_TEST (x86_use_bit_test & TUNEMASK)
257 #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & TUNEMASK)
258 /* For sane SSE instruction set generation we need fcomi instruction. It is
259 safe to enable all CMOVE instructions. */
260 #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
261 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & TUNEMASK)
262 #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & TUNEMASK)
263 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & TUNEMASK)
264 #define TARGET_USE_SAHF ((x86_use_sahf & TUNEMASK) && !TARGET_64BIT)
265 #define TARGET_MOVX (x86_movx & TUNEMASK)
266 #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & TUNEMASK)
267 #define TARGET_USE_LOOP (x86_use_loop & TUNEMASK)
268 #define TARGET_USE_FIOP (x86_use_fiop & TUNEMASK)
269 #define TARGET_USE_MOV0 (x86_use_mov0 & TUNEMASK)
270 #define TARGET_USE_CLTD (x86_use_cltd & TUNEMASK)
271 #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & TUNEMASK)
272 #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & TUNEMASK)
273 #define TARGET_READ_MODIFY (x86_read_modify & TUNEMASK)
274 #define TARGET_PROMOTE_QImode (x86_promote_QImode & TUNEMASK)
275 #define TARGET_FAST_PREFIX (x86_fast_prefix & TUNEMASK)
276 #define TARGET_SINGLE_STRINGOP (x86_single_stringop & TUNEMASK)
277 #define TARGET_QIMODE_MATH (x86_qimode_math & TUNEMASK)
278 #define TARGET_HIMODE_MATH (x86_himode_math & TUNEMASK)
279 #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & TUNEMASK)
280 #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & TUNEMASK)
281 #define TARGET_ADD_ESP_4 (x86_add_esp_4 & TUNEMASK)
282 #define TARGET_ADD_ESP_8 (x86_add_esp_8 & TUNEMASK)
283 #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & TUNEMASK)
284 #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & TUNEMASK)
285 #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & TUNEMASK)
286 #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & TUNEMASK)
287 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
288 (x86_sse_partial_reg_dependency & TUNEMASK)
289 #define TARGET_SSE_SPLIT_REGS (x86_sse_split_regs & TUNEMASK)
290 #define TARGET_SSE_TYPELESS_STORES (x86_sse_typeless_stores & TUNEMASK)
291 #define TARGET_SSE_LOAD0_BY_PXOR (x86_sse_load0_by_pxor & TUNEMASK)
292 #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & TUNEMASK)
293 #define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & TUNEMASK)
294 #define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & TUNEMASK)
295 #define TARGET_DECOMPOSE_LEA (x86_decompose_lea & TUNEMASK)
296 #define TARGET_PREFETCH_SSE (x86_prefetch_sse)
297 #define TARGET_SHIFT1 (x86_shift1 & TUNEMASK)
298 #define TARGET_USE_FFREEP (x86_use_ffreep & TUNEMASK)
299 #define TARGET_REP_MOVL_OPTIMAL (x86_rep_movl_optimal & TUNEMASK)
300 #define TARGET_INTER_UNIT_MOVES (x86_inter_unit_moves & TUNEMASK)
301 #define TARGET_FOUR_JUMP_LIMIT (x86_four_jump_limit & TUNEMASK)
302 #define TARGET_SCHEDULE (x86_schedule & TUNEMASK)
303 #define TARGET_USE_BT (x86_use_bt & TUNEMASK)
305 #define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE)
307 #define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS))
308 #define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS)
310 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
312 #define TARGET_SSE ((target_flags & MASK_SSE) != 0)
313 #define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
314 #define TARGET_SSE3 ((target_flags & MASK_SSE3) != 0)
315 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
316 #define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
317 && (ix86_fpmath & FPMATH_387))
318 #define TARGET_MMX ((target_flags & MASK_MMX) != 0)
319 #define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0)
320 #define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0)
322 #define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE))
324 #define TARGET_USE_MS_BITFIELD_LAYOUT (target_flags & MASK_MS_BITFIELD_LAYOUT)
326 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
327 #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
329 /* WARNING: Do not mark empty strings for translation, as calling
330 gettext on an empty string does NOT return an empty
334 #define TARGET_SWITCHES \
335 { { "80387", MASK_80387, N_("Use hardware fp") }, \
336 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \
337 { "hard-float", MASK_80387, N_("Use hardware fp") }, \
338 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \
339 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \
340 { "386", 0, "" /*Deprecated.*/}, \
341 { "486", 0, "" /*Deprecated.*/}, \
342 { "pentium", 0, "" /*Deprecated.*/}, \
343 { "pentiumpro", 0, "" /*Deprecated.*/}, \
344 { "intel-syntax", 0, "" /*Deprecated.*/}, \
345 { "no-intel-syntax", 0, "" /*Deprecated.*/}, \
347 N_("Alternate calling convention") }, \
348 { "no-rtd", -MASK_RTD, \
349 N_("Use normal calling convention") }, \
350 { "align-double", MASK_ALIGN_DOUBLE, \
351 N_("Align some doubles on dword boundary") }, \
352 { "no-align-double", -MASK_ALIGN_DOUBLE, \
353 N_("Align doubles on word boundary") }, \
354 { "svr3-shlib", MASK_SVR3_SHLIB, \
355 N_("Uninitialized locals in .bss") }, \
356 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \
357 N_("Uninitialized locals in .data") }, \
358 { "ieee-fp", MASK_IEEE_FP, \
359 N_("Use IEEE math for fp comparisons") }, \
360 { "no-ieee-fp", -MASK_IEEE_FP, \
361 N_("Do not use IEEE math for fp comparisons") }, \
362 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \
363 N_("Return values of functions in FPU registers") }, \
364 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \
365 N_("Do not return values of functions in FPU registers")}, \
366 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \
367 N_("Do not generate sin, cos, sqrt for FPU") }, \
368 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \
369 N_("Generate sin, cos, sqrt for FPU")}, \
370 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \
371 N_("Omit the frame pointer in leaf functions") }, \
372 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \
373 { "stack-arg-probe", MASK_STACK_PROBE, \
374 N_("Enable stack probing") }, \
375 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \
376 { "windows", 0, 0 /* undocumented */ }, \
377 { "dll", 0, 0 /* undocumented */ }, \
378 { "align-stringops", -MASK_NO_ALIGN_STROPS, \
379 N_("Align destination of the string operations") }, \
380 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \
381 N_("Do not align destination of the string operations") }, \
382 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \
383 N_("Inline all known string operations") }, \
384 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \
385 N_("Do not inline all known string operations") }, \
386 { "push-args", -MASK_NO_PUSH_ARGS, \
387 N_("Use push instructions to save outgoing arguments") }, \
388 { "no-push-args", MASK_NO_PUSH_ARGS, \
389 N_("Do not use push instructions to save outgoing arguments") }, \
390 { "accumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS, \
391 N_("Use push instructions to save outgoing arguments") }, \
392 { "no-accumulate-outgoing-args",-MASK_ACCUMULATE_OUTGOING_ARGS, \
393 N_("Do not use push instructions to save outgoing arguments") }, \
395 N_("Support MMX built-in functions") }, \
396 { "no-mmx", -(MASK_MMX|MASK_3DNOW|MASK_3DNOW_A), \
397 N_("Do not support MMX built-in functions") }, \
398 { "3dnow", MASK_3DNOW, \
399 N_("Support 3DNow! built-in functions") }, \
400 { "no-3dnow", -(MASK_3DNOW|MASK_3DNOW_A), \
401 N_("Do not support 3DNow! built-in functions") }, \
403 N_("Support MMX and SSE built-in functions and code generation") }, \
404 { "no-sse", -(MASK_SSE|MASK_SSE2|MASK_SSE3), \
405 N_("Do not support MMX and SSE built-in functions and code generation") },\
406 { "sse2", MASK_SSE2, \
407 N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \
408 { "no-sse2", -(MASK_SSE2|MASK_SSE3), \
409 N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \
410 { "sse3", MASK_SSE3, \
411 N_("Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation") },\
412 { "no-sse3", -MASK_SSE3, \
413 N_("Do not support MMX, SSE, SSE2 and SSE3 built-in functions and code generation") },\
414 { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \
415 N_("sizeof(long double) is 16") }, \
416 { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \
417 N_("sizeof(long double) is 12") }, \
418 { "64", MASK_64BIT, \
419 N_("Generate 64bit x86-64 code") }, \
420 { "32", -MASK_64BIT, \
421 N_("Generate 32bit i386 code") }, \
422 { "ms-bitfields", MASK_MS_BITFIELD_LAYOUT, \
423 N_("Use native (MS) bitfield layout") }, \
424 { "no-ms-bitfields", -MASK_MS_BITFIELD_LAYOUT, \
425 N_("Use gcc default bitfield layout") }, \
426 { "red-zone", -MASK_NO_RED_ZONE, \
427 N_("Use red-zone in the x86-64 code") }, \
428 { "no-red-zone", MASK_NO_RED_ZONE, \
429 N_("Do not use red-zone in the x86-64 code") }, \
430 { "tls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS, \
431 N_("Use direct references against %gs when accessing tls data") }, \
432 { "no-tls-direct-seg-refs", -MASK_TLS_DIRECT_SEG_REFS, \
433 N_("Do not use direct references against %gs when accessing tls data") }, \
436 TARGET_DEFAULT | TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_DEFAULT \
437 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT, 0 }}
439 #ifndef TARGET_64BIT_DEFAULT
440 #define TARGET_64BIT_DEFAULT 0
442 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
443 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
446 /* Once GDB has been enhanced to deal with functions without frame
447 pointers, we can change this to allow for elimination of
448 the frame pointer in leaf functions. */
449 #define TARGET_DEFAULT 0
451 /* This is not really a target flag, but is done this way so that
452 it's analogous to similar code for Mach-O on PowerPC. darwin.h
453 redefines this to 1. */
454 #define TARGET_MACHO 0
456 /* Subtargets may reset this to 1 in order to enable 96-bit long double
457 with the rounding mode forced to 53 bits. */
458 #define TARGET_96_ROUND_53_LONG_DOUBLE 0
460 /* This macro is similar to `TARGET_SWITCHES' but defines names of
461 command options that have values. Its definition is an
462 initializer with a subgrouping for each command option.
464 Each subgrouping contains a string constant, that defines the
465 fixed part of the option name, and the address of a variable. The
466 variable, type `char *', is set to the variable part of the given
467 option if the fixed part matches. The actual option name is made
468 by appending `-m' to the specified name. */
469 #define TARGET_OPTIONS \
470 { { "tune=", &ix86_tune_string, \
471 N_("Schedule code for given CPU"), 0}, \
472 { "fpmath=", &ix86_fpmath_string, \
473 N_("Generate floating point mathematics using given instruction set"), 0},\
474 { "arch=", &ix86_arch_string, \
475 N_("Generate code for given CPU"), 0}, \
476 { "regparm=", &ix86_regparm_string, \
477 N_("Number of registers used to pass integer arguments"), 0},\
478 { "align-loops=", &ix86_align_loops_string, \
479 N_("Loop code aligned to this power of 2"), 0}, \
480 { "align-jumps=", &ix86_align_jumps_string, \
481 N_("Jump targets are aligned to this power of 2"), 0}, \
482 { "align-functions=", &ix86_align_funcs_string, \
483 N_("Function starts are aligned to this power of 2"), 0}, \
484 { "preferred-stack-boundary=", \
485 &ix86_preferred_stack_boundary_string, \
486 N_("Attempt to keep stack aligned to this power of 2"), 0}, \
487 { "branch-cost=", &ix86_branch_cost_string, \
488 N_("Branches are this expensive (1-5, arbitrary units)"), 0},\
489 { "cmodel=", &ix86_cmodel_string, \
490 N_("Use given x86-64 code model"), 0}, \
491 { "debug-arg", &ix86_debug_arg_string, \
492 "" /* Undocumented. */, 0}, \
493 { "debug-addr", &ix86_debug_addr_string, \
494 "" /* Undocumented. */, 0}, \
495 { "asm=", &ix86_asm_string, \
496 N_("Use given assembler dialect"), 0}, \
497 { "tls-dialect=", &ix86_tls_dialect_string, \
498 N_("Use given thread-local storage dialect"), 0}, \
502 /* Sometimes certain combinations of command options do not make
503 sense on a particular target machine. You can define a macro
504 `OVERRIDE_OPTIONS' to take account of this. This macro, if
505 defined, is executed once just after all the command options have
508 Don't use this macro to turn on various extra optimizations for
509 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
511 #define OVERRIDE_OPTIONS override_options ()
513 /* These are meant to be redefined in the host dependent files */
514 #define SUBTARGET_SWITCHES
515 #define SUBTARGET_OPTIONS
517 /* Define this to change the optimizations performed by default. */
518 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
519 optimization_options ((LEVEL), (SIZE))
521 /* Support for configure-time defaults of some command line options. */
522 #define OPTION_DEFAULT_SPECS \
523 {"arch", "%{!march=*:-march=%(VALUE)}"}, \
524 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
525 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }
527 /* Specs for the compiler proper */
530 #define CC1_CPU_SPEC "\
533 %n`-m386' is deprecated. Use `-march=i386' or `-mtune=i386' instead.\n} \
535 %n`-m486' is deprecated. Use `-march=i486' or `-mtune=i486' instead.\n} \
536 %{mpentium:-mtune=pentium \
537 %n`-mpentium' is deprecated. Use `-march=pentium' or `-mtune=pentium' instead.\n} \
538 %{mpentiumpro:-mtune=pentiumpro \
539 %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mtune=pentiumpro' instead.\n} \
541 %n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n}} \
543 %{mintel-syntax:-masm=intel \
544 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
545 %{mno-intel-syntax:-masm=att \
546 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
549 /* Target CPU builtins. */
550 #define TARGET_CPU_CPP_BUILTINS() \
553 size_t arch_len = strlen (ix86_arch_string); \
554 size_t tune_len = strlen (ix86_tune_string); \
555 int last_arch_char = ix86_arch_string[arch_len - 1]; \
556 int last_tune_char = ix86_tune_string[tune_len - 1]; \
560 builtin_assert ("cpu=x86_64"); \
561 builtin_assert ("machine=x86_64"); \
562 builtin_define ("__amd64"); \
563 builtin_define ("__amd64__"); \
564 builtin_define ("__x86_64"); \
565 builtin_define ("__x86_64__"); \
569 builtin_assert ("cpu=i386"); \
570 builtin_assert ("machine=i386"); \
571 builtin_define_std ("i386"); \
574 /* Built-ins based on -mtune= (or -march= if no \
577 builtin_define ("__tune_i386__"); \
578 else if (TARGET_486) \
579 builtin_define ("__tune_i486__"); \
580 else if (TARGET_PENTIUM) \
582 builtin_define ("__tune_i586__"); \
583 builtin_define ("__tune_pentium__"); \
584 if (last_tune_char == 'x') \
585 builtin_define ("__tune_pentium_mmx__"); \
587 else if (TARGET_PENTIUMPRO) \
589 builtin_define ("__tune_i686__"); \
590 builtin_define ("__tune_pentiumpro__"); \
591 switch (last_tune_char) \
594 builtin_define ("__tune_pentium3__"); \
597 builtin_define ("__tune_pentium2__"); \
601 else if (TARGET_K6) \
603 builtin_define ("__tune_k6__"); \
604 if (last_tune_char == '2') \
605 builtin_define ("__tune_k6_2__"); \
606 else if (last_tune_char == '3') \
607 builtin_define ("__tune_k6_3__"); \
609 else if (TARGET_ATHLON) \
611 builtin_define ("__tune_athlon__"); \
612 /* Only plain "athlon" lacks SSE. */ \
613 if (last_tune_char != 'n') \
614 builtin_define ("__tune_athlon_sse__"); \
616 else if (TARGET_K8) \
617 builtin_define ("__tune_k8__"); \
618 else if (TARGET_PENTIUM4) \
619 builtin_define ("__tune_pentium4__"); \
620 else if (TARGET_NOCONA) \
621 builtin_define ("__tune_nocona__"); \
624 builtin_define ("__MMX__"); \
626 builtin_define ("__3dNOW__"); \
627 if (TARGET_3DNOW_A) \
628 builtin_define ("__3dNOW_A__"); \
630 builtin_define ("__SSE__"); \
632 builtin_define ("__SSE2__"); \
634 builtin_define ("__SSE3__"); \
635 if (TARGET_SSE_MATH && TARGET_SSE) \
636 builtin_define ("__SSE_MATH__"); \
637 if (TARGET_SSE_MATH && TARGET_SSE2) \
638 builtin_define ("__SSE2_MATH__"); \
640 /* Built-ins based on -march=. */ \
641 if (ix86_arch == PROCESSOR_I486) \
643 builtin_define ("__i486"); \
644 builtin_define ("__i486__"); \
646 else if (ix86_arch == PROCESSOR_PENTIUM) \
648 builtin_define ("__i586"); \
649 builtin_define ("__i586__"); \
650 builtin_define ("__pentium"); \
651 builtin_define ("__pentium__"); \
652 if (last_arch_char == 'x') \
653 builtin_define ("__pentium_mmx__"); \
655 else if (ix86_arch == PROCESSOR_PENTIUMPRO) \
657 builtin_define ("__i686"); \
658 builtin_define ("__i686__"); \
659 builtin_define ("__pentiumpro"); \
660 builtin_define ("__pentiumpro__"); \
662 else if (ix86_arch == PROCESSOR_K6) \
665 builtin_define ("__k6"); \
666 builtin_define ("__k6__"); \
667 if (last_arch_char == '2') \
668 builtin_define ("__k6_2__"); \
669 else if (last_arch_char == '3') \
670 builtin_define ("__k6_3__"); \
672 else if (ix86_arch == PROCESSOR_ATHLON) \
674 builtin_define ("__athlon"); \
675 builtin_define ("__athlon__"); \
676 /* Only plain "athlon" lacks SSE. */ \
677 if (last_arch_char != 'n') \
678 builtin_define ("__athlon_sse__"); \
680 else if (ix86_arch == PROCESSOR_K8) \
682 builtin_define ("__k8"); \
683 builtin_define ("__k8__"); \
685 else if (ix86_arch == PROCESSOR_PENTIUM4) \
687 builtin_define ("__pentium4"); \
688 builtin_define ("__pentium4__"); \
690 else if (ix86_arch == PROCESSOR_NOCONA) \
692 builtin_define ("__nocona"); \
693 builtin_define ("__nocona__"); \
698 #define TARGET_CPU_DEFAULT_i386 0
699 #define TARGET_CPU_DEFAULT_i486 1
700 #define TARGET_CPU_DEFAULT_pentium 2
701 #define TARGET_CPU_DEFAULT_pentium_mmx 3
702 #define TARGET_CPU_DEFAULT_pentiumpro 4
703 #define TARGET_CPU_DEFAULT_pentium2 5
704 #define TARGET_CPU_DEFAULT_pentium3 6
705 #define TARGET_CPU_DEFAULT_pentium4 7
706 #define TARGET_CPU_DEFAULT_k6 8
707 #define TARGET_CPU_DEFAULT_k6_2 9
708 #define TARGET_CPU_DEFAULT_k6_3 10
709 #define TARGET_CPU_DEFAULT_athlon 11
710 #define TARGET_CPU_DEFAULT_athlon_sse 12
711 #define TARGET_CPU_DEFAULT_k8 13
712 #define TARGET_CPU_DEFAULT_pentium_m 14
713 #define TARGET_CPU_DEFAULT_prescott 15
714 #define TARGET_CPU_DEFAULT_nocona 16
716 #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
717 "pentiumpro", "pentium2", "pentium3", \
718 "pentium4", "k6", "k6-2", "k6-3",\
719 "athlon", "athlon-4", "k8", \
720 "pentium-m", "prescott", "nocona"}
723 #define CC1_SPEC "%(cc1_cpu) "
726 /* This macro defines names of additional specifications to put in the
727 specs that can be used in various specifications like CC1_SPEC. Its
728 definition is an initializer with a subgrouping for each command option.
730 Each subgrouping contains a string constant, that defines the
731 specification name, and a string constant that used by the GCC driver
734 Do not define this macro if it does not need to do anything. */
736 #ifndef SUBTARGET_EXTRA_SPECS
737 #define SUBTARGET_EXTRA_SPECS
740 #define EXTRA_SPECS \
741 { "cc1_cpu", CC1_CPU_SPEC }, \
742 SUBTARGET_EXTRA_SPECS
744 /* target machine storage layout */
746 #define LONG_DOUBLE_TYPE_SIZE 80
748 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the
749 FPU, assume that the fpcw is set to extended precision; when using
750 only SSE, rounding is correct; when using both SSE and the FPU,
751 the rounding precision is indeterminate, since either may be chosen
752 apparently at random. */
753 #define TARGET_FLT_EVAL_METHOD \
754 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)
756 #define SHORT_TYPE_SIZE 16
757 #define INT_TYPE_SIZE 32
758 #define FLOAT_TYPE_SIZE 32
759 #define LONG_TYPE_SIZE BITS_PER_WORD
760 #define DOUBLE_TYPE_SIZE 64
761 #define LONG_LONG_TYPE_SIZE 64
763 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
764 #define MAX_BITS_PER_WORD 64
766 #define MAX_BITS_PER_WORD 32
769 /* Define this if most significant byte of a word is the lowest numbered. */
770 /* That is true on the 80386. */
772 #define BITS_BIG_ENDIAN 0
774 /* Define this if most significant byte of a word is the lowest numbered. */
775 /* That is not true on the 80386. */
776 #define BYTES_BIG_ENDIAN 0
778 /* Define this if most significant word of a multiword number is the lowest
780 /* Not true for 80386 */
781 #define WORDS_BIG_ENDIAN 0
783 /* Width of a word, in units (bytes). */
784 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
786 #define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
788 #define MIN_UNITS_PER_WORD 4
791 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
792 #define PARM_BOUNDARY BITS_PER_WORD
794 /* Boundary (in *bits*) on which stack pointer should be aligned. */
795 #define STACK_BOUNDARY BITS_PER_WORD
797 /* Boundary (in *bits*) on which the stack pointer prefers to be
798 aligned; the compiler cannot rely on having this alignment. */
799 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
801 /* As of July 2001, many runtimes to not align the stack properly when
802 entering main. This causes expand_main_function to forcibly align
803 the stack, which results in aligned frames for functions called from
804 main, though it does nothing for the alignment of main itself. */
805 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
806 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
808 /* Minimum allocation boundary for the code of a function. */
809 #define FUNCTION_BOUNDARY 8
811 /* C++ stores the virtual bit in the lowest bit of function pointers. */
812 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
814 /* Alignment of field after `int : 0' in a structure. */
816 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
818 /* Minimum size in bits of the largest boundary to which any
819 and all fundamental data types supported by the hardware
820 might need to be aligned. No data type wants to be aligned
823 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
824 and Pentium Pro XFmode values at 128 bit boundaries. */
826 #define BIGGEST_ALIGNMENT 128
828 /* Decide whether a variable of mode MODE should be 128 bit aligned. */
829 #define ALIGN_MODE_128(MODE) \
830 ((MODE) == XFmode || (MODE) == TFmode || SSE_REG_MODE_P (MODE))
832 /* The published ABIs say that doubles should be aligned on word
833 boundaries, so lower the alignment for structure fields unless
834 -malign-double is set. */
836 /* ??? Blah -- this macro is used directly by libobjc. Since it
837 supports no vector modes, cut out the complexity and fall back
838 on BIGGEST_FIELD_ALIGNMENT. */
839 #ifdef IN_TARGET_LIBS
841 #define BIGGEST_FIELD_ALIGNMENT 128
843 #define BIGGEST_FIELD_ALIGNMENT 32
846 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
847 x86_field_alignment (FIELD, COMPUTED)
850 /* If defined, a C expression to compute the alignment given to a
851 constant that is being placed in memory. EXP is the constant
852 and ALIGN is the alignment that the object would ordinarily have.
853 The value of this macro is used instead of that alignment to align
856 If this macro is not defined, then ALIGN is used.
858 The typical use of this macro is to increase alignment for string
859 constants to be word aligned so that `strcpy' calls that copy
860 constants can be done inline. */
862 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
864 /* If defined, a C expression to compute the alignment for a static
865 variable. TYPE is the data type, and ALIGN is the alignment that
866 the object would ordinarily have. The value of this macro is used
867 instead of that alignment to align the object.
869 If this macro is not defined, then ALIGN is used.
871 One use of this macro is to increase alignment of medium-size
872 data to make it all fit in fewer cache lines. Another is to
873 cause character arrays to be word-aligned so that `strcpy' calls
874 that copy constants to character arrays can be done inline. */
876 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
878 /* If defined, a C expression to compute the alignment for a local
879 variable. TYPE is the data type, and ALIGN is the alignment that
880 the object would ordinarily have. The value of this macro is used
881 instead of that alignment to align the object.
883 If this macro is not defined, then ALIGN is used.
885 One use of this macro is to increase alignment of medium-size
886 data to make it all fit in fewer cache lines. */
888 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN))
890 /* If defined, a C expression that gives the alignment boundary, in
891 bits, of an argument with the specified mode and type. If it is
892 not defined, `PARM_BOUNDARY' is used for all arguments. */
894 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
895 ix86_function_arg_boundary ((MODE), (TYPE))
897 /* Set this nonzero if move instructions will actually fail to work
898 when given unaligned data. */
899 #define STRICT_ALIGNMENT 0
901 /* If bit field type is int, don't let it cross an int,
902 and give entire struct the alignment of an int. */
903 /* Required on the 386 since it doesn't have bit-field insns. */
904 #define PCC_BITFIELD_TYPE_MATTERS 1
906 /* Standard register usage. */
908 /* This processor has special stack-like registers. See reg-stack.c
912 #define IS_STACK_MODE(MODE) \
913 ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode) \
915 /* Number of actual hardware registers.
916 The hardware registers are assigned numbers for the compiler
917 from 0 to just below FIRST_PSEUDO_REGISTER.
918 All registers that the compiler knows about must be given numbers,
919 even those that are not normally considered general registers.
921 In the 80386 we give the 8 general purpose registers the numbers 0-7.
922 We number the floating point registers 8-15.
923 Note that registers 0-7 can be accessed as a short or int,
924 while only 0-3 may be used with byte `mov' instructions.
926 Reg 16 does not correspond to any hardware register, but instead
927 appears in the RTL as an argument pointer prior to reload, and is
928 eliminated during reloading in favor of either the stack or frame
931 #define FIRST_PSEUDO_REGISTER 53
933 /* Number of hardware registers that go into the DWARF-2 unwind info.
934 If not defined, equals FIRST_PSEUDO_REGISTER. */
936 #define DWARF_FRAME_REGISTERS 17
938 /* 1 for registers that have pervasive standard uses
939 and are not available for the register allocator.
940 On the 80386, the stack pointer is such, as is the arg pointer.
942 The value is zero if the register is not fixed on either 32 or
943 64 bit targets, one if the register if fixed on both 32 and 64
944 bit targets, two if it is only fixed on 32bit targets and three
945 if its only fixed on 64bit targets.
946 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
948 #define FIXED_REGISTERS \
949 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
950 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
951 /*arg,flags,fpsr,dir,frame*/ \
953 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
954 0, 0, 0, 0, 0, 0, 0, 0, \
955 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
956 0, 0, 0, 0, 0, 0, 0, 0, \
957 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
958 2, 2, 2, 2, 2, 2, 2, 2, \
959 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
960 2, 2, 2, 2, 2, 2, 2, 2}
963 /* 1 for registers not available across function calls.
964 These must include the FIXED_REGISTERS and also any
965 registers that can be used without being saved.
966 The latter must include the registers where values are returned
967 and the register where structure-value addresses are passed.
968 Aside from that, you can include as many other registers as you like.
970 The value is zero if the register is not call used on either 32 or
971 64 bit targets, one if the register if call used on both 32 and 64
972 bit targets, two if it is only call used on 32bit targets and three
973 if its only call used on 64bit targets.
974 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
976 #define CALL_USED_REGISTERS \
977 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
978 { 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
979 /*arg,flags,fpsr,dir,frame*/ \
981 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
982 1, 1, 1, 1, 1, 1, 1, 1, \
983 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
984 1, 1, 1, 1, 1, 1, 1, 1, \
985 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
986 1, 1, 1, 1, 2, 2, 2, 2, \
987 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
988 1, 1, 1, 1, 1, 1, 1, 1} \
990 /* Order in which to allocate registers. Each register must be
991 listed once, even those in FIXED_REGISTERS. List frame pointer
992 late and fixed registers last. Note that, in general, we prefer
993 registers listed in CALL_USED_REGISTERS, keeping the others
994 available for storage of persistent values.
996 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
997 so this is just empty initializer for array. */
999 #define REG_ALLOC_ORDER \
1000 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
1001 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
1002 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1003 48, 49, 50, 51, 52 }
1005 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1006 to be rearranged based on a particular function. When using sse math,
1007 we want to allocate SSE before x87 registers and vice vera. */
1009 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
1012 /* Macro to conditionally modify fixed_regs/call_used_regs. */
1013 #define CONDITIONAL_REGISTER_USAGE \
1016 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
1018 if (fixed_regs[i] > 1) \
1019 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \
1020 if (call_used_regs[i] > 1) \
1021 call_used_regs[i] = (call_used_regs[i] \
1022 == (TARGET_64BIT ? 3 : 2)); \
1024 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
1026 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
1027 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
1032 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
1033 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
1034 fixed_regs[i] = call_used_regs[i] = 1; \
1039 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
1040 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
1041 fixed_regs[i] = call_used_regs[i] = 1; \
1043 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
1047 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
1048 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
1049 if (TEST_HARD_REG_BIT (x, i)) \
1050 fixed_regs[i] = call_used_regs[i] = 1; \
1054 /* Return number of consecutive hard regs needed starting at reg REGNO
1055 to hold something of mode MODE.
1056 This is ordinarily the length in words of a value of mode MODE
1057 but can be less for certain modes in special long registers.
1059 Actually there are no two word move instructions for consecutive
1060 registers. And only registers 0-3 may have mov byte instructions
1064 #define HARD_REGNO_NREGS(REGNO, MODE) \
1065 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
1066 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1067 : ((MODE) == XFmode \
1068 ? (TARGET_64BIT ? 2 : 3) \
1069 : (MODE) == XCmode \
1070 ? (TARGET_64BIT ? 4 : 6) \
1071 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
1073 #define VALID_SSE2_REG_MODE(MODE) \
1074 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
1075 || (MODE) == V2DImode || (MODE) == DFmode)
1077 #define VALID_SSE_REG_MODE(MODE) \
1078 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1079 || (MODE) == SFmode || (MODE) == TFmode)
1081 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
1082 ((MODE) == V2SFmode || (MODE) == SFmode)
1084 #define VALID_MMX_REG_MODE(MODE) \
1085 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
1086 || (MODE) == V2SImode || (MODE) == SImode)
1088 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
1089 place emms and femms instructions. */
1090 #define UNITS_PER_SIMD_WORD (TARGET_SSE ? 16 : 0)
1092 #define VALID_FP_MODE_P(MODE) \
1093 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
1094 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \
1096 #define VALID_INT_MODE_P(MODE) \
1097 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
1098 || (MODE) == DImode \
1099 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
1100 || (MODE) == CDImode \
1101 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \
1102 || (MODE) == TFmode || (MODE) == TCmode)))
1104 /* Return true for modes passed in SSE registers. */
1105 #define SSE_REG_MODE_P(MODE) \
1106 ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \
1107 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \
1108 || (MODE) == V4SFmode || (MODE) == V4SImode)
1110 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1112 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1113 ix86_hard_regno_mode_ok ((REGNO), (MODE))
1115 /* Value is 1 if it is a good idea to tie two pseudo registers
1116 when one has mode MODE1 and one has mode MODE2.
1117 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1118 for any hard reg, then this must be 0 for correct output. */
1120 #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2)
1122 /* It is possible to write patterns to move flags; but until someone
1124 #define AVOID_CCMODE_COPIES
1126 /* Specify the modes required to caller save a given hard regno.
1127 We do this on i386 to prevent flags from being saved at all.
1129 Kill any attempts to combine saving of modes. */
1131 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1132 (CC_REGNO_P (REGNO) ? VOIDmode \
1133 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1134 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false)\
1135 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1136 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
1138 /* Specify the registers used for certain standard purposes.
1139 The values of these macros are register numbers. */
1141 /* on the 386 the pc register is %eip, and is not usable as a general
1142 register. The ordinary mov instructions won't work */
1143 /* #define PC_REGNUM */
1145 /* Register to use for pushing function arguments. */
1146 #define STACK_POINTER_REGNUM 7
1148 /* Base register for access to local variables of the function. */
1149 #define HARD_FRAME_POINTER_REGNUM 6
1151 /* Base register for access to local variables of the function. */
1152 #define FRAME_POINTER_REGNUM 20
1154 /* First floating point reg */
1155 #define FIRST_FLOAT_REG 8
1157 /* First & last stack-like regs */
1158 #define FIRST_STACK_REG FIRST_FLOAT_REG
1159 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1161 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1162 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1164 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1165 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1167 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1168 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1170 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1171 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1173 /* Value should be nonzero if functions must have frame pointers.
1174 Zero means the frame pointer need not be set up (and parms
1175 may be accessed via the stack pointer) in functions that seem suitable.
1176 This is computed in `reload', in reload1.c. */
1177 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1179 /* Override this in other tm.h files to cope with various OS losage
1180 requiring a frame pointer. */
1181 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1182 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1185 /* Make sure we can access arbitrary call frames. */
1186 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1188 /* Base register for access to arguments of the function. */
1189 #define ARG_POINTER_REGNUM 16
1191 /* Register in which static-chain is passed to a function.
1192 We do use ECX as static chain register for 32 bit ABI. On the
1193 64bit ABI, ECX is an argument register, so we use R10 instead. */
1194 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1196 /* Register to hold the addressing base for position independent
1197 code access to data items. We don't use PIC pointer for 64bit
1198 mode. Define the regnum to dummy value to prevent gcc from
1199 pessimizing code dealing with EBX.
1201 To avoid clobbering a call-saved register unnecessarily, we renumber
1202 the pic register when possible. The change is visible after the
1203 prologue has been emitted. */
1205 #define REAL_PIC_OFFSET_TABLE_REGNUM 3
1207 #define PIC_OFFSET_TABLE_REGNUM \
1208 (TARGET_64BIT || !flag_pic ? INVALID_REGNUM \
1209 : reload_completed ? REGNO (pic_offset_table_rtx) \
1210 : REAL_PIC_OFFSET_TABLE_REGNUM)
1212 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1214 /* A C expression which can inhibit the returning of certain function
1215 values in registers, based on the type of value. A nonzero value
1216 says to return the function value in memory, just as large
1217 structures are always returned. Here TYPE will be a C expression
1218 of type `tree', representing the data type of the value.
1220 Note that values of mode `BLKmode' must be explicitly handled by
1221 this macro. Also, the option `-fpcc-struct-return' takes effect
1222 regardless of this macro. On most systems, it is possible to
1223 leave the macro undefined; this causes a default definition to be
1224 used, whose value is the constant 1 for `BLKmode' values, and 0
1227 Do not use this macro to indicate that structures and unions
1228 should always be returned in memory. You should instead use
1229 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1231 #define RETURN_IN_MEMORY(TYPE) \
1232 ix86_return_in_memory (TYPE)
1234 /* This is overridden by <cygwin.h>. */
1235 #define MS_AGGREGATE_RETURN 0
1237 /* This is overridden by <netware.h>. */
1238 #define KEEP_AGGREGATE_RETURN_POINTER 0
1240 /* Define the classes of registers for register constraints in the
1241 machine description. Also define ranges of constants.
1243 One of the classes must always be named ALL_REGS and include all hard regs.
1244 If there is more than one class, another class must be named NO_REGS
1245 and contain no registers.
1247 The name GENERAL_REGS must be the name of a class (or an alias for
1248 another name such as ALL_REGS). This is the class of registers
1249 that is allowed by "g" or "r" in a register constraint.
1250 Also, registers outside this class are allocated only when
1251 instructions express preferences for them.
1253 The classes must be numbered in nondecreasing order; that is,
1254 a larger-numbered class must never be contained completely
1255 in a smaller-numbered class.
1257 For any two classes, it is very desirable that there be another
1258 class that represents their union.
1260 It might seem that class BREG is unnecessary, since no useful 386
1261 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1262 and the "b" register constraint is useful in asms for syscalls.
1264 The flags and fpsr registers are in no class. */
1269 AREG, DREG, CREG, BREG, SIREG, DIREG,
1270 AD_REGS, /* %eax/%edx for DImode */
1271 Q_REGS, /* %eax %ebx %ecx %edx */
1272 NON_Q_REGS, /* %esi %edi %ebp %esp */
1273 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1274 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1275 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1276 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1286 ALL_REGS, LIM_REG_CLASSES
1289 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1291 #define INTEGER_CLASS_P(CLASS) \
1292 reg_class_subset_p ((CLASS), GENERAL_REGS)
1293 #define FLOAT_CLASS_P(CLASS) \
1294 reg_class_subset_p ((CLASS), FLOAT_REGS)
1295 #define SSE_CLASS_P(CLASS) \
1296 ((CLASS) == SSE_REGS)
1297 #define MMX_CLASS_P(CLASS) \
1298 ((CLASS) == MMX_REGS)
1299 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1300 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1301 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1302 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1303 #define MAYBE_SSE_CLASS_P(CLASS) \
1304 reg_classes_intersect_p (SSE_REGS, (CLASS))
1305 #define MAYBE_MMX_CLASS_P(CLASS) \
1306 reg_classes_intersect_p (MMX_REGS, (CLASS))
1308 #define Q_CLASS_P(CLASS) \
1309 reg_class_subset_p ((CLASS), Q_REGS)
1311 /* Give names of register classes as strings for dump file. */
1313 #define REG_CLASS_NAMES \
1315 "AREG", "DREG", "CREG", "BREG", \
1318 "Q_REGS", "NON_Q_REGS", \
1322 "FP_TOP_REG", "FP_SECOND_REG", \
1326 "FP_TOP_SSE_REGS", \
1327 "FP_SECOND_SSE_REGS", \
1331 "FLOAT_INT_SSE_REGS", \
1334 /* Define which registers fit in which classes.
1335 This is an initializer for a vector of HARD_REG_SET
1336 of length N_REG_CLASSES. */
1338 #define REG_CLASS_CONTENTS \
1340 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1341 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1342 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1343 { 0x03, 0x0 }, /* AD_REGS */ \
1344 { 0x0f, 0x0 }, /* Q_REGS */ \
1345 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1346 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1347 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1348 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1349 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1350 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1351 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1352 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1353 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1354 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1355 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1356 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1357 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1358 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1359 { 0xffffffff,0x1fffff } \
1362 /* The same information, inverted:
1363 Return the class number of the smallest class containing
1364 reg number REGNO. This could be a conditional expression
1365 or could index an array. */
1367 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1369 /* When defined, the compiler allows registers explicitly used in the
1370 rtl to be used as spill registers but prevents the compiler from
1371 extending the lifetime of these registers. */
1373 #define SMALL_REGISTER_CLASSES 1
1375 #define QI_REG_P(X) \
1376 (REG_P (X) && REGNO (X) < 4)
1378 #define GENERAL_REGNO_P(N) \
1379 ((N) < 8 || REX_INT_REGNO_P (N))
1381 #define GENERAL_REG_P(X) \
1382 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1384 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1386 #define NON_QI_REG_P(X) \
1387 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
1389 #define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG)
1390 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1392 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1393 #define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG)
1394 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1395 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1397 #define SSE_REGNO_P(N) \
1398 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \
1399 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG))
1401 #define REX_SSE_REGNO_P(N) \
1402 ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG)
1404 #define SSE_REGNO(N) \
1405 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1406 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1408 #define SSE_FLOAT_MODE_P(MODE) \
1409 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1411 #define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG)
1412 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1414 #define STACK_REG_P(XOP) \
1416 REGNO (XOP) >= FIRST_STACK_REG && \
1417 REGNO (XOP) <= LAST_STACK_REG)
1419 #define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP))
1421 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1423 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1424 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1426 /* The class value for index registers, and the one for base regs. */
1428 #define INDEX_REG_CLASS INDEX_REGS
1429 #define BASE_REG_CLASS GENERAL_REGS
1436 /* Get reg_class from a letter such as appears in the machine description. */
1438 #define REG_CLASS_FROM_LETTER(C) \
1439 ((C) == 'r' ? GENERAL_REGS : \
1440 (C) == 'R' ? LEGACY_REGS : \
1441 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \
1442 (C) == 'Q' ? Q_REGS : \
1443 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1446 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1449 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1452 (C) == 'a' ? AREG : \
1453 (C) == 'b' ? BREG : \
1454 (C) == 'c' ? CREG : \
1455 (C) == 'd' ? DREG : \
1456 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \
1457 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \
1458 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \
1459 (C) == 'A' ? AD_REGS : \
1460 (C) == 'D' ? DIREG : \
1461 (C) == 'S' ? SIREG : \
1462 (C) == 'l' ? INDEX_REGS : \
1465 /* The letters I, J, K, L and M in a register constraint string
1466 can be used to stand for particular ranges of immediate operands.
1467 This macro defines what the ranges are.
1468 C is the letter, and VALUE is a constant value.
1469 Return 1 if VALUE is in the range specified by C.
1471 I is for non-DImode shifts.
1472 J is for DImode shifts.
1473 K is for signed imm8 operands.
1474 L is for andsi as zero-extending move.
1475 M is for shifts that can be executed by the "lea" opcode.
1476 N is for immediate operands for out/in instructions (0-255)
1479 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1480 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \
1481 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \
1482 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \
1483 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \
1484 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \
1485 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \
1488 /* Similar, but for floating constants, and defining letters G and H.
1489 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if
1490 TARGET_387 isn't set, because the stack register converter may need to
1491 load 0.0 into the function value register. */
1493 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1494 ((C) == 'G' ? standard_80387_constant_p (VALUE) \
1497 /* A C expression that defines the optional machine-dependent
1498 constraint letters that can be used to segregate specific types of
1499 operands, usually memory references, for the target machine. Any
1500 letter that is not elsewhere defined and not matched by
1501 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not
1504 If it is required for a particular target machine, it should
1505 return 1 if VALUE corresponds to the operand type represented by
1506 the constraint letter C. If C is not defined as an extra
1507 constraint, the value returned should be 0 regardless of VALUE. */
1509 #define EXTRA_CONSTRAINT(VALUE, D) \
1510 ((D) == 'e' ? x86_64_immediate_operand (VALUE, VOIDmode) \
1511 : (D) == 'Z' ? x86_64_zext_immediate_operand (VALUE, VOIDmode) \
1512 : (D) == 'C' ? standard_sse_constant_p (VALUE) \
1515 /* Place additional restrictions on the register class to use when it
1516 is necessary to be able to hold a value of mode MODE in a reload
1517 register for which class CLASS would ordinarily be used. */
1519 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1520 ((MODE) == QImode && !TARGET_64BIT \
1521 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1522 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1525 /* Given an rtx X being reloaded into a reg required to be
1526 in class CLASS, return the class of reg to actually use.
1527 In general this is just CLASS; but on some machines
1528 in some cases it is preferable to use a more restrictive class.
1529 On the 80386 series, we prevent floating constants from being
1530 reloaded into floating registers (since no move-insn can do that)
1531 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1533 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1534 QImode must go into class Q_REGS.
1535 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1536 movdf to do mem-to-mem moves through integer regs. */
1538 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1539 ix86_preferred_reload_class ((X), (CLASS))
1541 /* If we are copying between general and FP registers, we need a memory
1542 location. The same is true for SSE and MMX registers. */
1543 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1544 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1546 /* QImode spills from non-QI registers need a scratch. This does not
1547 happen often -- the only example so far requires an uninitialized
1550 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
1551 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \
1552 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \
1555 /* Return the maximum number of consecutive registers
1556 needed to represent mode MODE in a register of class CLASS. */
1557 /* On the 80386, this is the size of MODE in words,
1558 except in the FP regs, where a single reg is always enough. */
1559 #define CLASS_MAX_NREGS(CLASS, MODE) \
1560 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1561 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1562 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \
1563 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1565 /* A C expression whose value is nonzero if pseudos that have been
1566 assigned to registers of class CLASS would likely be spilled
1567 because registers of CLASS are needed for spill registers.
1569 The default value of this macro returns 1 if CLASS has exactly one
1570 register and zero otherwise. On most machines, this default
1571 should be used. Only define this macro to some other expression
1572 if pseudo allocated by `local-alloc.c' end up in memory because
1573 their hard registers were needed for spill registers. If this
1574 macro returns nonzero for those classes, those pseudos will only
1575 be allocated by `global.c', which knows how to reallocate the
1576 pseudo to another register. If there would not be another
1577 register available for reallocation, you should not change the
1578 definition of this macro since the only effect of such a
1579 definition would be to slow down register allocation. */
1581 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1582 (((CLASS) == AREG) \
1583 || ((CLASS) == DREG) \
1584 || ((CLASS) == CREG) \
1585 || ((CLASS) == BREG) \
1586 || ((CLASS) == AD_REGS) \
1587 || ((CLASS) == SIREG) \
1588 || ((CLASS) == DIREG) \
1589 || ((CLASS) == FP_TOP_REG) \
1590 || ((CLASS) == FP_SECOND_REG))
1592 /* Return a class of registers that cannot change FROM mode to TO mode.
1594 x87 registers can't do subreg as all values are reformated to extended
1595 precision. XMM registers does not support with nonzero offsets equal
1596 to 4, 8 and 12 otherwise valid for integer registers. Since we can't
1597 determine these, prohibit all nonparadoxical subregs changing size. */
1599 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1600 (GET_MODE_SIZE (TO) < GET_MODE_SIZE (FROM) \
1601 ? reg_classes_intersect_p (FLOAT_SSE_REGS, (CLASS)) \
1602 || MAYBE_MMX_CLASS_P (CLASS) \
1603 : GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1604 ? reg_classes_intersect_p (FLOAT_REGS, (CLASS)) : 0)
1606 /* Stack layout; function entry, exit and calling. */
1608 /* Define this if pushing a word on the stack
1609 makes the stack pointer a smaller address. */
1610 #define STACK_GROWS_DOWNWARD
1612 /* Define this if the nominal address of the stack frame
1613 is at the high-address end of the local variables;
1614 that is, each additional local variable allocated
1615 goes at a more negative offset in the frame. */
1616 #define FRAME_GROWS_DOWNWARD
1618 /* Offset within stack frame to start allocating local variables at.
1619 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1620 first local allocated. Otherwise, it is the offset to the BEGINNING
1621 of the first local allocated. */
1622 #define STARTING_FRAME_OFFSET 0
1624 /* If we generate an insn to push BYTES bytes,
1625 this says how many the stack pointer really advances by.
1626 On 386 pushw decrements by exactly 2 no matter what the position was.
1627 On the 386 there is no pushb; we use pushw instead, and this
1628 has the effect of rounding up to 2.
1630 For 64bit ABI we round up to 8 bytes.
1633 #define PUSH_ROUNDING(BYTES) \
1635 ? (((BYTES) + 7) & (-8)) \
1636 : (((BYTES) + 1) & (-2)))
1638 /* If defined, the maximum amount of space required for outgoing arguments will
1639 be computed and placed into the variable
1640 `current_function_outgoing_args_size'. No space will be pushed onto the
1641 stack for each call; instead, the function prologue should increase the stack
1642 frame size by this amount. */
1644 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1646 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1647 instructions to pass outgoing arguments. */
1649 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1651 /* We want the stack and args grow in opposite directions, even if
1653 #define PUSH_ARGS_REVERSED 1
1655 /* Offset of first parameter from the argument pointer register value. */
1656 #define FIRST_PARM_OFFSET(FNDECL) 0
1658 /* Define this macro if functions should assume that stack space has been
1659 allocated for arguments even when their values are passed in registers.
1661 The value of this macro is the size, in bytes, of the area reserved for
1662 arguments passed in registers for the function represented by FNDECL.
1664 This space can be allocated by the caller, or be a part of the
1665 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1667 #define REG_PARM_STACK_SPACE(FNDECL) 0
1669 /* Value is the number of bytes of arguments automatically
1670 popped when returning from a subroutine call.
1671 FUNDECL is the declaration node of the function (as a tree),
1672 FUNTYPE is the data type of the function (as a tree),
1673 or for a library call it is an identifier node for the subroutine name.
1674 SIZE is the number of bytes of arguments passed on the stack.
1676 On the 80386, the RTD insn may be used to pop them if the number
1677 of args is fixed, but if the number is variable then the caller
1678 must pop them all. RTD can't be used for library calls now
1679 because the library is compiled with the Unix compiler.
1680 Use of RTD is a selectable option, since it is incompatible with
1681 standard Unix calling sequences. If the option is not selected,
1682 the caller must always pop the args.
1684 The attribute stdcall is equivalent to RTD on a per module basis. */
1686 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1687 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1689 /* Define how to find the value returned by a function.
1690 VALTYPE is the data type of the value (as a tree).
1691 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1692 otherwise, FUNC is 0. */
1693 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1694 ix86_function_value (VALTYPE)
1696 #define FUNCTION_VALUE_REGNO_P(N) \
1697 ix86_function_value_regno_p (N)
1699 /* Define how to find the value returned by a library function
1700 assuming the value has mode MODE. */
1702 #define LIBCALL_VALUE(MODE) \
1703 ix86_libcall_value (MODE)
1705 /* Define the size of the result block used for communication between
1706 untyped_call and untyped_return. The block contains a DImode value
1707 followed by the block used by fnsave and frstor. */
1709 #define APPLY_RESULT_SIZE (8+108)
1711 /* 1 if N is a possible register number for function argument passing. */
1712 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1714 /* Define a data type for recording info about an argument list
1715 during the scan of that argument list. This data type should
1716 hold all necessary information about the function itself
1717 and about the args processed so far, enough to enable macros
1718 such as FUNCTION_ARG to determine where the next arg should go. */
1720 typedef struct ix86_args {
1721 int words; /* # words passed so far */
1722 int nregs; /* # registers available for passing */
1723 int regno; /* next available register number */
1724 int fastcall; /* fastcall calling convention is used */
1725 int sse_words; /* # sse words passed so far */
1726 int sse_nregs; /* # sse registers available for passing */
1727 int warn_sse; /* True when we want to warn about SSE ABI. */
1728 int warn_mmx; /* True when we want to warn about MMX ABI. */
1729 int sse_regno; /* next available sse register number */
1730 int mmx_words; /* # mmx words passed so far */
1731 int mmx_nregs; /* # mmx registers available for passing */
1732 int mmx_regno; /* next available mmx register number */
1733 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1736 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1737 for a call to a function whose data type is FNTYPE.
1738 For a library call, FNTYPE is 0. */
1740 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1741 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1743 /* Update the data in CUM to advance over an argument
1744 of mode MODE and data type TYPE.
1745 (TYPE is null for libcalls where that information may not be available.) */
1747 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1748 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1750 /* Define where to put the arguments to a function.
1751 Value is zero to push the argument on the stack,
1752 or a hard register in which to store the argument.
1754 MODE is the argument's machine mode.
1755 TYPE is the data type of the argument (as a tree).
1756 This is null for libcalls where that information may
1758 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1759 the preceding args and about the function being called.
1760 NAMED is nonzero if this argument is a named parameter
1761 (otherwise it is an extra parameter matching an ellipsis). */
1763 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1764 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1766 /* Implement `va_start' for varargs and stdarg. */
1767 #define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \
1768 ix86_va_start (VALIST, NEXTARG)
1770 #define TARGET_ASM_FILE_END ix86_file_end
1771 #define NEED_INDICATE_EXEC_STACK 0
1773 /* Output assembler code to FILE to increment profiler label # LABELNO
1774 for profiling a function entry. */
1776 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO)
1778 #define MCOUNT_NAME "_mcount"
1780 #define PROFILE_COUNT_REGISTER "edx"
1782 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1783 the stack pointer does not matter. The value is tested only in
1784 functions that have frame pointers.
1785 No definition is equivalent to always zero. */
1786 /* Note on the 386 it might be more efficient not to define this since
1787 we have to restore it ourselves from the frame pointer, in order to
1790 #define EXIT_IGNORE_STACK 1
1792 /* Output assembler code for a block containing the constant parts
1793 of a trampoline, leaving space for the variable parts. */
1795 /* On the 386, the trampoline contains two instructions:
1798 The trampoline is generated entirely at runtime. The operand of JMP
1799 is the address of FUNCTION relative to the instruction following the
1800 JMP (which is 5 bytes long). */
1802 /* Length in units of the trampoline for entering a nested function. */
1804 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1806 /* Emit RTL insns to initialize the variable parts of a trampoline.
1807 FNADDR is an RTX for the address of the function's pure code.
1808 CXT is an RTX for the static chain value for the function. */
1810 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1811 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1813 /* Definitions for register eliminations.
1815 This is an array of structures. Each structure initializes one pair
1816 of eliminable registers. The "from" register number is given first,
1817 followed by "to". Eliminations of the same "from" register are listed
1818 in order of preference.
1820 There are two registers that can always be eliminated on the i386.
1821 The frame pointer and the arg pointer can be replaced by either the
1822 hard frame pointer or to the stack pointer, depending upon the
1823 circumstances. The hard frame pointer is not used before reload and
1824 so it is not eligible for elimination. */
1826 #define ELIMINABLE_REGS \
1827 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1828 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1829 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1830 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1832 /* Given FROM and TO register numbers, say whether this elimination is
1833 allowed. Frame pointer elimination is automatically handled.
1835 All other eliminations are valid. */
1837 #define CAN_ELIMINATE(FROM, TO) \
1838 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1840 /* Define the offset between two registers, one to be eliminated, and the other
1841 its replacement, at the start of a routine. */
1843 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1844 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1846 /* Addressing modes, and classification of registers for them. */
1848 /* Macros to check register numbers against specific register classes. */
1850 /* These assume that REGNO is a hard or pseudo reg number.
1851 They give nonzero only if REGNO is a hard reg of the suitable class
1852 or a pseudo reg currently allocated to a suitable hard reg.
1853 Since they use reg_renumber, they are safe only once reg_renumber
1854 has been allocated, which happens in local-alloc.c. */
1856 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1857 ((REGNO) < STACK_POINTER_REGNUM \
1858 || (REGNO >= FIRST_REX_INT_REG \
1859 && (REGNO) <= LAST_REX_INT_REG) \
1860 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1861 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1862 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM)
1864 #define REGNO_OK_FOR_BASE_P(REGNO) \
1865 ((REGNO) <= STACK_POINTER_REGNUM \
1866 || (REGNO) == ARG_POINTER_REGNUM \
1867 || (REGNO) == FRAME_POINTER_REGNUM \
1868 || (REGNO >= FIRST_REX_INT_REG \
1869 && (REGNO) <= LAST_REX_INT_REG) \
1870 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1871 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1872 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM)
1874 #define REGNO_OK_FOR_SIREG_P(REGNO) \
1875 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4)
1876 #define REGNO_OK_FOR_DIREG_P(REGNO) \
1877 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5)
1879 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1880 and check its validity for a certain class.
1881 We have two alternate definitions for each of them.
1882 The usual definition accepts all pseudo regs; the other rejects
1883 them unless they have been allocated suitable hard regs.
1884 The symbol REG_OK_STRICT causes the latter definition to be used.
1886 Most source files want to accept pseudo regs in the hope that
1887 they will get allocated to the class that the insn wants them to be in.
1888 Source files for reload pass need to be strict.
1889 After reload, it makes no difference, since pseudo regs have
1890 been eliminated by then. */
1893 /* Non strict versions, pseudos are ok. */
1894 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1895 (REGNO (X) < STACK_POINTER_REGNUM \
1896 || (REGNO (X) >= FIRST_REX_INT_REG \
1897 && REGNO (X) <= LAST_REX_INT_REG) \
1898 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1900 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1901 (REGNO (X) <= STACK_POINTER_REGNUM \
1902 || REGNO (X) == ARG_POINTER_REGNUM \
1903 || REGNO (X) == FRAME_POINTER_REGNUM \
1904 || (REGNO (X) >= FIRST_REX_INT_REG \
1905 && REGNO (X) <= LAST_REX_INT_REG) \
1906 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1908 /* Strict versions, hard registers only */
1909 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1910 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1912 #ifndef REG_OK_STRICT
1913 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1914 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1917 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1918 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1921 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1922 that is a valid memory address for an instruction.
1923 The MODE argument is the machine mode for the MEM expression
1924 that wants to use this address.
1926 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1927 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1929 See legitimize_pic_address in i386.c for details as to what
1930 constitutes a legitimate address when -fpic is used. */
1932 #define MAX_REGS_PER_ADDRESS 2
1934 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1936 /* Nonzero if the constant value X is a legitimate general operand.
1937 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1939 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1941 #ifdef REG_OK_STRICT
1942 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1944 if (legitimate_address_p ((MODE), (X), 1)) \
1949 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1951 if (legitimate_address_p ((MODE), (X), 0)) \
1957 /* If defined, a C expression to determine the base term of address X.
1958 This macro is used in only one place: `find_base_term' in alias.c.
1960 It is always safe for this macro to not be defined. It exists so
1961 that alias analysis can understand machine-dependent addresses.
1963 The typical use of this macro is to handle addresses containing
1964 a label_ref or symbol_ref within an UNSPEC. */
1966 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1968 /* Try machine-dependent ways of modifying an illegitimate address
1969 to be legitimate. If we find one, return the new, valid address.
1970 This macro is used in only one place: `memory_address' in explow.c.
1972 OLDX is the address as it was before break_out_memory_refs was called.
1973 In some cases it is useful to look at this to decide what needs to be done.
1975 MODE and WIN are passed so that this macro can use
1976 GO_IF_LEGITIMATE_ADDRESS.
1978 It is always safe for this macro to do nothing. It exists to recognize
1979 opportunities to optimize the output.
1981 For the 80386, we handle X+REG by loading X into a register R and
1982 using R+REG. R will go in a general reg and indexing will be used.
1983 However, if REG is a broken-out memory address or multiplication,
1984 nothing needs to be done because REG can certainly go in a general reg.
1986 When -fpic is used, special handling is needed for symbolic references.
1987 See comments by legitimize_pic_address in i386.c for details. */
1989 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1991 (X) = legitimize_address ((X), (OLDX), (MODE)); \
1992 if (memory_address_p ((MODE), (X))) \
1996 #define REWRITE_ADDRESS(X) rewrite_address (X)
1998 /* Nonzero if the constant value X is a legitimate general operand
1999 when generating PIC code. It is given that flag_pic is on and
2000 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
2002 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
2004 #define SYMBOLIC_CONST(X) \
2005 (GET_CODE (X) == SYMBOL_REF \
2006 || GET_CODE (X) == LABEL_REF \
2007 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
2009 /* Go to LABEL if ADDR (a legitimate address expression)
2010 has an effect that depends on the machine mode it is used for.
2011 On the 80386, only postdecrement and postincrement address depend thus
2012 (the amount of decrement or increment being the length of the operand). */
2013 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2015 if (GET_CODE (ADDR) == POST_INC \
2016 || GET_CODE (ADDR) == POST_DEC) \
2020 /* Max number of args passed in registers. If this is more than 3, we will
2021 have problems with ebx (register #4), since it is a caller save register and
2022 is also used as the pic register in ELF. So for now, don't allow more than
2023 3 registers to be passed in registers. */
2025 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
2027 #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : (TARGET_SSE ? 3 : 0))
2029 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0))
2032 /* Specify the machine mode that this machine uses
2033 for the index in the tablejump instruction. */
2034 #define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode)
2036 /* Define this as 1 if `char' should by default be signed; else as 0. */
2037 #define DEFAULT_SIGNED_CHAR 1
2039 /* Number of bytes moved into a data cache for a single prefetch operation. */
2040 #define PREFETCH_BLOCK ix86_cost->prefetch_block
2042 /* Number of prefetch operations that can be done in parallel. */
2043 #define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches
2045 /* Max number of bytes we can move from memory to memory
2046 in one reasonably fast instruction. */
2049 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
2050 move efficiently, as opposed to MOVE_MAX which is the maximum
2051 number of bytes we can move with a single instruction. */
2052 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
2054 /* If a memory-to-memory move would take MOVE_RATIO or more simple
2055 move-instruction pairs, we will do a movmem or libcall instead.
2056 Increasing the value will always make code faster, but eventually
2057 incurs high cost in increased code size.
2059 If you don't define this, a reasonable default is used. */
2061 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
2063 /* If a clear memory operation would take CLEAR_RATIO or more simple
2064 move-instruction sequences, we will do a clrmem or libcall instead. */
2066 #define CLEAR_RATIO (optimize_size ? 2 \
2067 : ix86_cost->move_ratio > 6 ? 6 : ix86_cost->move_ratio)
2069 /* Define if shifts truncate the shift count
2070 which implies one can omit a sign-extension or zero-extension
2071 of a shift count. */
2072 /* On i386, shifts do truncate the count. But bit opcodes don't. */
2074 /* #define SHIFT_COUNT_TRUNCATED */
2076 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2077 is done just by pretending it is already truncated. */
2078 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2080 /* A macro to update M and UNSIGNEDP when an object whose type is
2081 TYPE and which has the specified mode and signedness is to be
2082 stored in a register. This macro is only called when TYPE is a
2085 On i386 it is sometimes useful to promote HImode and QImode
2086 quantities to SImode. The choice depends on target type. */
2088 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2090 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
2091 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
2095 /* Specify the machine mode that pointers have.
2096 After generation of rtl, the compiler makes no further distinction
2097 between pointers and any other objects of this machine mode. */
2098 #define Pmode (TARGET_64BIT ? DImode : SImode)
2100 /* A function address in a call instruction
2101 is a byte address (for indexing purposes)
2102 so give the MEM rtx a byte's mode. */
2103 #define FUNCTION_MODE QImode
2105 /* A C expression for the cost of moving data from a register in class FROM to
2106 one in class TO. The classes are expressed using the enumeration values
2107 such as `GENERAL_REGS'. A value of 2 is the default; other values are
2108 interpreted relative to that.
2110 It is not required that the cost always equal 2 when FROM is the same as TO;
2111 on some machines it is expensive to move between registers if they are not
2112 general registers. */
2114 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2115 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
2117 /* A C expression for the cost of moving data of mode M between a
2118 register and memory. A value of 2 is the default; this cost is
2119 relative to those in `REGISTER_MOVE_COST'.
2121 If moving between registers and memory is more expensive than
2122 between two registers, you should define this macro to express the
2125 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
2126 ix86_memory_move_cost ((MODE), (CLASS), (IN))
2128 /* A C expression for the cost of a branch instruction. A value of 1
2129 is the default; other values are interpreted relative to that. */
2131 #define BRANCH_COST ix86_branch_cost
2133 /* Define this macro as a C expression which is nonzero if accessing
2134 less than a word of memory (i.e. a `char' or a `short') is no
2135 faster than accessing a word of memory, i.e., if such access
2136 require more than one instruction or if there is no difference in
2137 cost between byte and (aligned) word loads.
2139 When this macro is not defined, the compiler will access a field by
2140 finding the smallest containing object; when it is defined, a
2141 fullword load will be used if alignment permits. Unless bytes
2142 accesses are faster than word accesses, using word accesses is
2143 preferable since it may eliminate subsequent memory access if
2144 subsequent accesses occur to other fields in the same word of the
2145 structure, but to different bytes. */
2147 #define SLOW_BYTE_ACCESS 0
2149 /* Nonzero if access to memory by shorts is slow and undesirable. */
2150 #define SLOW_SHORT_ACCESS 0
2152 /* Define this macro to be the value 1 if unaligned accesses have a
2153 cost many times greater than aligned accesses, for example if they
2154 are emulated in a trap handler.
2156 When this macro is nonzero, the compiler will act as if
2157 `STRICT_ALIGNMENT' were nonzero when generating code for block
2158 moves. This can cause significantly more instructions to be
2159 produced. Therefore, do not set this macro nonzero if unaligned
2160 accesses only add a cycle or two to the time for a memory access.
2162 If the value of this macro is always zero, it need not be defined. */
2164 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
2166 /* Define this macro if it is as good or better to call a constant
2167 function address than to call an address kept in a register.
2169 Desirable on the 386 because a CALL with a constant address is
2170 faster than one with a register address. */
2172 #define NO_FUNCTION_CSE
2174 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2175 return the mode to be used for the comparison.
2177 For floating-point equality comparisons, CCFPEQmode should be used.
2178 VOIDmode should be used in all other cases.
2180 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2181 possible, to allow for more combinations. */
2183 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
2185 /* Return nonzero if MODE implies a floating point inequality can be
2188 #define REVERSIBLE_CC_MODE(MODE) 1
2190 /* A C expression whose value is reversed condition code of the CODE for
2191 comparison done in CC_MODE mode. */
2192 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
2195 /* Control the assembler format that we output, to the extent
2196 this does not vary between assemblers. */
2198 /* How to refer to registers in assembler output.
2199 This sequence is indexed by compiler's hard-register-number (see above). */
2201 /* In order to refer to the first 8 regs as 32 bit regs prefix an "e"
2202 For non floating point regs, the following are the HImode names.
2204 For float regs, the stack top is sometimes referred to as "%st(0)"
2205 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */
2207 #define HI_REGISTER_NAMES \
2208 {"ax","dx","cx","bx","si","di","bp","sp", \
2209 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
2210 "argp", "flags", "fpsr", "dirflag", "frame", \
2211 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2212 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \
2213 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2214 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2216 #define REGISTER_NAMES HI_REGISTER_NAMES
2218 /* Table of additional register names to use in user input. */
2220 #define ADDITIONAL_REGISTER_NAMES \
2221 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2222 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2223 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2224 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2225 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2226 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \
2227 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \
2228 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} }
2230 /* Note we are omitting these since currently I don't know how
2231 to get gcc to use these, since they want the same but different
2232 number as al, and ax.
2235 #define QI_REGISTER_NAMES \
2236 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2238 /* These parallel the array above, and can be used to access bits 8:15
2239 of regs 0 through 3. */
2241 #define QI_HIGH_REGISTER_NAMES \
2242 {"ah", "dh", "ch", "bh", }
2244 /* How to renumber registers for dbx and gdb. */
2246 #define DBX_REGISTER_NUMBER(N) \
2247 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
2249 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2250 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2251 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2253 /* Before the prologue, RA is at 0(%esp). */
2254 #define INCOMING_RETURN_ADDR_RTX \
2255 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2257 /* After the prologue, RA is at -4(AP) in the current frame. */
2258 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2260 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2261 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2263 /* PC is dbx register 8; let's use that column for RA. */
2264 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2266 /* Before the prologue, the top of the frame is at 4(%esp). */
2267 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2269 /* Describe how we implement __builtin_eh_return. */
2270 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2271 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2274 /* Select a format to encode pointers in exception handling data. CODE
2275 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2276 true if the symbol may be affected by dynamic relocations.
2278 ??? All x86 object file formats are capable of representing this.
2279 After all, the relocation needed is the same as for the call insn.
2280 Whether or not a particular assembler allows us to enter such, I
2281 guess we'll have to see. */
2282 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2284 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
2287 /* This is how to output an insn to push a register on the stack.
2288 It need not be very fast code. */
2290 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2293 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \
2294 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2296 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \
2299 /* This is how to output an insn to pop a register from the stack.
2300 It need not be very fast code. */
2302 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2305 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \
2306 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2308 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \
2311 /* This is how to output an element of a case-vector that is absolute. */
2313 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2314 ix86_output_addr_vec_elt ((FILE), (VALUE))
2316 /* This is how to output an element of a case-vector that is relative. */
2318 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2319 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2321 /* Under some conditions we need jump tables in the text section, because
2322 the assembler cannot handle label differences between sections. */
2324 #define JUMP_TABLES_IN_TEXT_SECTION \
2325 (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA)
2327 /* Emit a dtp-relative reference to a TLS variable. */
2330 #define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \
2331 i386_output_dwarf_dtprel (FILE, SIZE, X)
2334 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2335 and switch back. For x86 we do this only to save a few bytes that
2336 would otherwise be unused in the text section. */
2337 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2338 asm (SECTION_OP "\n\t" \
2339 "call " USER_LABEL_PREFIX #FUNC "\n" \
2340 TEXT_SECTION_ASM_OP);
2342 /* Print operand X (an rtx) in assembler syntax to file FILE.
2343 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2344 Effect of various CODE letters is described in i386.c near
2345 print_operand function. */
2347 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2348 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&')
2350 #define PRINT_OPERAND(FILE, X, CODE) \
2351 print_operand ((FILE), (X), (CODE))
2353 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2354 print_operand_address ((FILE), (ADDR))
2356 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2358 if (! output_addr_const_extra (FILE, (X))) \
2362 /* a letter which is not needed by the normal asm syntax, which
2363 we can use for operand syntax in the extended asm */
2365 #define ASM_OPERAND_LETTER '#'
2366 #define RET return ""
2367 #define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx))
2369 /* Which processor to schedule for. The cpu attribute defines a list that
2370 mirrors this list, so changes to i386.md must be made at the same time. */
2374 PROCESSOR_I386, /* 80386 */
2375 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
2377 PROCESSOR_PENTIUMPRO,
2386 extern enum processor_type ix86_tune;
2387 extern const char *ix86_tune_string;
2389 extern enum processor_type ix86_arch;
2390 extern const char *ix86_arch_string;
2398 extern enum fpmath_unit ix86_fpmath;
2399 extern const char *ix86_fpmath_string;
2407 extern enum tls_dialect ix86_tls_dialect;
2408 extern const char *ix86_tls_dialect_string;
2411 CM_32, /* The traditional 32-bit ABI. */
2412 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */
2413 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */
2414 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */
2415 CM_LARGE, /* No assumptions. */
2416 CM_SMALL_PIC /* Assumes code+data+got/plt fits in a 31 bit region. */
2419 extern enum cmodel ix86_cmodel;
2420 extern const char *ix86_cmodel_string;
2422 /* Size of the RED_ZONE area. */
2423 #define RED_ZONE_SIZE 128
2424 /* Reserved area of the red zone for temporaries. */
2425 #define RED_ZONE_RESERVE 8
2432 extern const char *ix86_asm_string;
2433 extern enum asm_dialect ix86_asm_dialect;
2435 extern int ix86_regparm;
2436 extern const char *ix86_regparm_string;
2438 extern unsigned int ix86_preferred_stack_boundary;
2439 extern const char *ix86_preferred_stack_boundary_string;
2441 extern int ix86_branch_cost;
2442 extern const char *ix86_branch_cost_string;
2444 extern const char *ix86_debug_arg_string;
2445 extern const char *ix86_debug_addr_string;
2447 /* Obsoleted by -f options. Remove before 3.2 ships. */
2448 extern const char *ix86_align_loops_string;
2449 extern const char *ix86_align_jumps_string;
2450 extern const char *ix86_align_funcs_string;
2452 /* Smallest class containing REGNO. */
2453 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
2455 extern rtx ix86_compare_op0; /* operand 0 for comparisons */
2456 extern rtx ix86_compare_op1; /* operand 1 for comparisons */
2458 /* To properly truncate FP values into integers, we need to set i387 control
2459 word. We can't emit proper mode switching code before reload, as spills
2460 generated by reload may truncate values incorrectly, but we still can avoid
2461 redundant computation of new control word by the mode switching pass.
2462 The fldcw instructions are still emitted redundantly, but this is probably
2463 not going to be noticeable problem, as most CPUs do have fast path for
2466 The machinery is to emit simple truncation instructions and split them
2467 before reload to instructions having USEs of two memory locations that
2468 are filled by this code to old and new control word.
2470 Post-reload pass may be later used to eliminate the redundant fildcw if
2474 /* Define this macro if the port needs extra instructions inserted
2475 for mode switching in an optimizing compilation. */
2477 #define OPTIMIZE_MODE_SWITCHING(ENTITY) ix86_optimize_mode_switching
2479 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2480 initializer for an array of integers. Each initializer element N
2481 refers to an entity that needs mode switching, and specifies the
2482 number of different modes that might need to be set for this
2483 entity. The position of the initializer in the initializer -
2484 starting counting at zero - determines the integer that is used to
2485 refer to the mode-switched entity in question. */
2487 #define NUM_MODES_FOR_MODE_SWITCHING { I387_CW_ANY }
2489 /* ENTITY is an integer specifying a mode-switched entity. If
2490 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
2491 return an integer value not larger than the corresponding element
2492 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
2493 must be switched into prior to the execution of INSN.
2495 The mode UNINITIALIZED is used to force re-load of possibly previously
2496 stored control word after function call. The mode ANY specify that
2497 function has no requirements on the control word and make no changes
2498 in the bits we are interested in. */
2500 #define MODE_NEEDED(ENTITY, I) \
2501 (GET_CODE (I) == CALL_INSN \
2502 || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \
2503 || GET_CODE (PATTERN (I)) == ASM_INPUT))\
2504 ? I387_CW_UNINITIALIZED \
2505 : recog_memoized (I) < 0 \
2507 : get_attr_i387_cw (I))
2509 /* This macro specifies the order in which modes for ENTITY are
2510 processed. 0 is the highest priority. */
2512 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
2514 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
2515 is the set of hard registers live at the point where the insn(s)
2516 are to be inserted. */
2518 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2519 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \
2520 ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \
2521 assign_386_stack_local (HImode, 2), \
2525 /* Avoid renaming of stack registers, as doing so in combination with
2526 scheduling just increases amount of live registers at time and in
2527 the turn amount of fxch instructions needed.
2529 ??? Maybe Pentium chips benefits from renaming, someone can try.... */
2531 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
2532 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG)
2535 #define DLL_IMPORT_EXPORT_PREFIX '#'
2537 #define FASTCALL_PREFIX '@'
2539 struct machine_function GTY(())
2541 struct stack_local_entry *stack_locals;
2542 const char *some_ld_name;
2543 int save_varrargs_registers;
2544 int accesses_prev_frame;
2545 int optimize_mode_switching;
2546 /* Set by ix86_compute_frame_layout and used by prologue/epilogue expander to
2547 determine the style used. */
2548 int use_fast_prologue_epilogue;
2549 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed
2551 int use_fast_prologue_epilogue_nregs;
2554 #define ix86_stack_locals (cfun->machine->stack_locals)
2555 #define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers)
2556 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2558 /* Control behavior of x86_file_start. */
2559 #define X86_FILE_START_VERSION_DIRECTIVE false
2560 #define X86_FILE_START_FLTUSED false
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