2 * Copyright (c) 2006-2007 Broadcom Corporation
3 * David Christensen <davidch@broadcom.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written consent.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGE.
30 * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
34 * The following controllers are supported by this driver:
42 * The following controllers are not supported by this driver:
48 * BCM5709S A0, A1, B0, B1, B2, C0
52 #include "opt_polling.h"
54 #include <sys/param.h>
56 #include <sys/endian.h>
57 #include <sys/kernel.h>
58 #include <sys/interrupt.h>
60 #include <sys/malloc.h>
61 #include <sys/queue.h>
63 #include <sys/random.h>
66 #include <sys/serialize.h>
67 #include <sys/socket.h>
68 #include <sys/sockio.h>
69 #include <sys/sysctl.h>
71 #include <netinet/ip.h>
72 #include <netinet/tcp.h>
75 #include <net/ethernet.h>
77 #include <net/if_arp.h>
78 #include <net/if_dl.h>
79 #include <net/if_media.h>
80 #include <net/if_types.h>
81 #include <net/ifq_var.h>
82 #include <net/vlan/if_vlan_var.h>
83 #include <net/vlan/if_vlan_ether.h>
85 #include <dev/netif/mii_layer/mii.h>
86 #include <dev/netif/mii_layer/miivar.h>
87 #include <dev/netif/mii_layer/brgphyreg.h>
89 #include <bus/pci/pcireg.h>
90 #include <bus/pci/pcivar.h>
92 #include "miibus_if.h"
94 #include <dev/netif/bce/if_bcereg.h>
95 #include <dev/netif/bce/if_bcefw.h>
97 /****************************************************************************/
98 /* BCE Debug Options */
99 /****************************************************************************/
102 static uint32_t bce_debug = BCE_WARN;
106 * 1 = 1 in 2,147,483,648
107 * 256 = 1 in 8,388,608
108 * 2048 = 1 in 1,048,576
109 * 65536 = 1 in 32,768
110 * 1048576 = 1 in 2,048
113 * 1073741824 = 1 in 2
115 * bce_debug_l2fhdr_status_check:
116 * How often the l2_fhdr frame error check will fail.
118 * bce_debug_unexpected_attention:
119 * How often the unexpected attention check will fail.
121 * bce_debug_mbuf_allocation_failure:
122 * How often to simulate an mbuf allocation failure.
124 * bce_debug_dma_map_addr_failure:
125 * How often to simulate a DMA mapping failure.
127 * bce_debug_bootcode_running_failure:
128 * How often to simulate a bootcode failure.
130 static int bce_debug_l2fhdr_status_check = 0;
131 static int bce_debug_unexpected_attention = 0;
132 static int bce_debug_mbuf_allocation_failure = 0;
133 static int bce_debug_dma_map_addr_failure = 0;
134 static int bce_debug_bootcode_running_failure = 0;
136 #endif /* BCE_DEBUG */
139 /****************************************************************************/
140 /* PCI Device ID Table */
142 /* Used by bce_probe() to identify the devices supported by this driver. */
143 /****************************************************************************/
144 #define BCE_DEVDESC_MAX 64
146 static struct bce_type bce_devs[] = {
147 /* BCM5706C Controllers and OEM boards. */
148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101,
149 "HP NC370T Multifunction Gigabit Server Adapter" },
150 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106,
151 "HP NC370i Multifunction Gigabit Server Adapter" },
152 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070,
153 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
154 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709,
155 "HP NC371i Multifunction Gigabit Server Adapter" },
156 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID,
157 "Broadcom NetXtreme II BCM5706 1000Base-T" },
159 /* BCM5706S controllers and OEM boards. */
160 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
161 "HP NC370F Multifunction Gigabit Server Adapter" },
162 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID,
163 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
165 /* BCM5708C controllers and OEM boards. */
166 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037,
167 "HP NC373T PCIe Multifunction Gig Server Adapter" },
168 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038,
169 "HP NC373i Multifunction Gigabit Server Adapter" },
170 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045,
171 "HP NC374m PCIe Multifunction Adapter" },
172 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID,
173 "Broadcom NetXtreme II BCM5708 1000Base-T" },
175 /* BCM5708S controllers and OEM boards. */
176 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706,
177 "HP NC373m Multifunction Gigabit Server Adapter" },
178 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b,
179 "HP NC373i Multifunction Gigabit Server Adapter" },
180 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d,
181 "HP NC373F PCIe Multifunc Giga Server Adapter" },
182 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID,
183 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
185 /* BCM5709C controllers and OEM boards. */
186 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055,
187 "HP NC382i DP Multifunction Gigabit Server Adapter" },
188 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059,
189 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
190 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID,
191 "Broadcom NetXtreme II BCM5709 1000Base-T" },
193 /* BCM5709S controllers and OEM boards. */
194 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d,
195 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
196 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056,
197 "HP NC382i DP Multifunction Gigabit Server Adapter" },
198 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID,
199 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
201 /* BCM5716 controllers and OEM boards. */
202 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID,
203 "Broadcom NetXtreme II BCM5716 1000Base-T" },
209 /****************************************************************************/
210 /* Supported Flash NVRAM device data. */
211 /****************************************************************************/
212 static const struct flash_spec flash_table[] =
214 #define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
215 #define NONBUFFERED_FLAGS (BCE_NV_WREN)
218 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
219 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
220 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
222 /* Expansion entry 0001 */
223 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
224 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
225 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
227 /* Saifun SA25F010 (non-buffered flash) */
228 /* strap, cfg1, & write1 need updates */
229 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
230 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
231 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
232 "Non-buffered flash (128kB)"},
233 /* Saifun SA25F020 (non-buffered flash) */
234 /* strap, cfg1, & write1 need updates */
235 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
236 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
237 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
238 "Non-buffered flash (256kB)"},
239 /* Expansion entry 0100 */
240 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
241 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
242 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
244 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
245 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
246 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
247 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
248 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
249 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
250 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
251 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
252 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
253 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
254 /* Saifun SA25F005 (non-buffered flash) */
255 /* strap, cfg1, & write1 need updates */
256 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
257 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
258 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
259 "Non-buffered flash (64kB)"},
261 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
262 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
263 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
265 /* Expansion entry 1001 */
266 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
267 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
268 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
270 /* Expansion entry 1010 */
271 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
272 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
273 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
275 /* ATMEL AT45DB011B (buffered flash) */
276 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
277 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
278 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
279 "Buffered flash (128kB)"},
280 /* Expansion entry 1100 */
281 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
282 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
283 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
285 /* Expansion entry 1101 */
286 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
287 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
288 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
290 /* Ateml Expansion entry 1110 */
291 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
292 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
293 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
294 "Entry 1110 (Atmel)"},
295 /* ATMEL AT45DB021B (buffered flash) */
296 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
297 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
298 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
299 "Buffered flash (256kB)"},
303 * The BCM5709 controllers transparently handle the
304 * differences between Atmel 264 byte pages and all
305 * flash devices which use 256 byte pages, so no
306 * logical-to-physical mapping is required in the
309 static struct flash_spec flash_5709 = {
310 .flags = BCE_NV_BUFFERED,
311 .page_bits = BCM5709_FLASH_PAGE_BITS,
312 .page_size = BCM5709_FLASH_PAGE_SIZE,
313 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
314 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2,
315 .name = "5709/5716 buffered flash (256kB)",
319 /****************************************************************************/
320 /* DragonFly device entry points. */
321 /****************************************************************************/
322 static int bce_probe(device_t);
323 static int bce_attach(device_t);
324 static int bce_detach(device_t);
325 static void bce_shutdown(device_t);
327 /****************************************************************************/
328 /* BCE Debug Data Structure Dump Routines */
329 /****************************************************************************/
331 static void bce_dump_mbuf(struct bce_softc *, struct mbuf *);
332 static void bce_dump_tx_mbuf_chain(struct bce_softc *, int, int);
333 static void bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
334 static void bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
335 static void bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
336 static void bce_dump_l2fhdr(struct bce_softc *, int,
337 struct l2_fhdr *) __unused;
338 static void bce_dump_tx_chain(struct bce_softc *, int, int);
339 static void bce_dump_rx_chain(struct bce_softc *, int, int);
340 static void bce_dump_status_block(struct bce_softc *);
341 static void bce_dump_driver_state(struct bce_softc *);
342 static void bce_dump_stats_block(struct bce_softc *) __unused;
343 static void bce_dump_hw_state(struct bce_softc *);
344 static void bce_dump_txp_state(struct bce_softc *);
345 static void bce_dump_rxp_state(struct bce_softc *) __unused;
346 static void bce_dump_tpat_state(struct bce_softc *) __unused;
347 static void bce_freeze_controller(struct bce_softc *) __unused;
348 static void bce_unfreeze_controller(struct bce_softc *) __unused;
349 static void bce_breakpoint(struct bce_softc *);
350 #endif /* BCE_DEBUG */
353 /****************************************************************************/
354 /* BCE Register/Memory Access Routines */
355 /****************************************************************************/
356 static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
357 static void bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
358 static void bce_shmem_wr(struct bce_softc *, uint32_t, uint32_t);
359 static uint32_t bce_shmem_rd(struct bce_softc *, u32);
360 static void bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
361 static int bce_miibus_read_reg(device_t, int, int);
362 static int bce_miibus_write_reg(device_t, int, int, int);
363 static void bce_miibus_statchg(device_t);
366 /****************************************************************************/
367 /* BCE NVRAM Access Routines */
368 /****************************************************************************/
369 static int bce_acquire_nvram_lock(struct bce_softc *);
370 static int bce_release_nvram_lock(struct bce_softc *);
371 static void bce_enable_nvram_access(struct bce_softc *);
372 static void bce_disable_nvram_access(struct bce_softc *);
373 static int bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
375 static int bce_init_nvram(struct bce_softc *);
376 static int bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
377 static int bce_nvram_test(struct bce_softc *);
379 /****************************************************************************/
380 /* BCE DMA Allocate/Free Routines */
381 /****************************************************************************/
382 static int bce_dma_alloc(struct bce_softc *);
383 static void bce_dma_free(struct bce_softc *);
384 static void bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
386 /****************************************************************************/
387 /* BCE Firmware Synchronization and Load */
388 /****************************************************************************/
389 static int bce_fw_sync(struct bce_softc *, uint32_t);
390 static void bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
392 static void bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
394 static void bce_start_cpu(struct bce_softc *, struct cpu_reg *);
395 static void bce_halt_cpu(struct bce_softc *, struct cpu_reg *);
396 static void bce_start_rxp_cpu(struct bce_softc *);
397 static void bce_init_rxp_cpu(struct bce_softc *);
398 static void bce_init_txp_cpu(struct bce_softc *);
399 static void bce_init_tpat_cpu(struct bce_softc *);
400 static void bce_init_cp_cpu(struct bce_softc *);
401 static void bce_init_com_cpu(struct bce_softc *);
402 static void bce_init_cpus(struct bce_softc *);
404 static void bce_stop(struct bce_softc *);
405 static int bce_reset(struct bce_softc *, uint32_t);
406 static int bce_chipinit(struct bce_softc *);
407 static int bce_blockinit(struct bce_softc *);
408 static int bce_newbuf_std(struct bce_softc *, uint16_t *, uint16_t *,
410 static void bce_setup_rxdesc_std(struct bce_softc *, uint16_t, uint32_t *);
411 static void bce_probe_pci_caps(struct bce_softc *);
412 static void bce_print_adapter_info(struct bce_softc *);
413 static void bce_get_media(struct bce_softc *);
415 static void bce_init_tx_context(struct bce_softc *);
416 static int bce_init_tx_chain(struct bce_softc *);
417 static void bce_init_rx_context(struct bce_softc *);
418 static int bce_init_rx_chain(struct bce_softc *);
419 static void bce_free_rx_chain(struct bce_softc *);
420 static void bce_free_tx_chain(struct bce_softc *);
422 static int bce_encap(struct bce_softc *, struct mbuf **);
423 static int bce_tso_setup(struct bce_softc *, struct mbuf **,
424 uint16_t *, uint16_t *);
425 static void bce_start(struct ifnet *);
426 static int bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
427 static void bce_watchdog(struct ifnet *);
428 static int bce_ifmedia_upd(struct ifnet *);
429 static void bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
430 static void bce_init(void *);
431 static void bce_mgmt_init(struct bce_softc *);
433 static int bce_init_ctx(struct bce_softc *);
434 static void bce_get_mac_addr(struct bce_softc *);
435 static void bce_set_mac_addr(struct bce_softc *);
436 static void bce_phy_intr(struct bce_softc *);
437 static void bce_rx_intr(struct bce_softc *, int, uint16_t);
438 static void bce_tx_intr(struct bce_softc *, uint16_t);
439 static void bce_disable_intr(struct bce_softc *);
440 static void bce_enable_intr(struct bce_softc *);
441 static void bce_reenable_intr(struct bce_softc *);
443 #ifdef DEVICE_POLLING
444 static void bce_poll(struct ifnet *, enum poll_cmd, int);
446 static void bce_intr(struct bce_softc *);
447 static void bce_intr_legacy(void *);
448 static void bce_intr_msi(void *);
449 static void bce_intr_msi_oneshot(void *);
450 static void bce_set_rx_mode(struct bce_softc *);
451 static void bce_stats_update(struct bce_softc *);
452 static void bce_tick(void *);
453 static void bce_tick_serialized(struct bce_softc *);
454 static void bce_pulse(void *);
455 static void bce_pulse_check_msi(struct bce_softc *);
456 static void bce_add_sysctls(struct bce_softc *);
458 static void bce_coal_change(struct bce_softc *);
459 static int bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
460 static int bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
461 static int bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
462 static int bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
463 static int bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
464 static int bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
465 static int bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
466 static int bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
467 static int bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
468 uint32_t *, uint32_t);
472 * Don't set bce_tx_ticks_int/bce_tx_ticks to 1023. Linux's bnx2
473 * takes 1023 as the TX ticks limit. However, using 1023 will
474 * cause 5708(B2) to generate extra interrupts (~2000/s) even when
475 * there is _no_ network activity on the NIC.
477 static uint32_t bce_tx_bds_int = 255; /* bcm: 20 */
478 static uint32_t bce_tx_bds = 255; /* bcm: 20 */
479 static uint32_t bce_tx_ticks_int = 1022; /* bcm: 80 */
480 static uint32_t bce_tx_ticks = 1022; /* bcm: 80 */
481 static uint32_t bce_rx_bds_int = 128; /* bcm: 6 */
482 static uint32_t bce_rx_bds = 128; /* bcm: 6 */
483 static uint32_t bce_rx_ticks_int = 150; /* bcm: 18 */
484 static uint32_t bce_rx_ticks = 150; /* bcm: 18 */
486 static int bce_msi_enable = 1;
488 static int bce_rx_pages = RX_PAGES_DEFAULT;
489 static int bce_tx_pages = TX_PAGES_DEFAULT;
491 TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
492 TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
493 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
494 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
495 TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
496 TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
497 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
498 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
499 TUNABLE_INT("hw.bce.msi.enable", &bce_msi_enable);
500 TUNABLE_INT("hw.bce.rx_pages", &bce_rx_pages);
501 TUNABLE_INT("hw.bce.tx_pages", &bce_tx_pages);
503 /****************************************************************************/
504 /* DragonFly device dispatch table. */
505 /****************************************************************************/
506 static device_method_t bce_methods[] = {
507 /* Device interface */
508 DEVMETHOD(device_probe, bce_probe),
509 DEVMETHOD(device_attach, bce_attach),
510 DEVMETHOD(device_detach, bce_detach),
511 DEVMETHOD(device_shutdown, bce_shutdown),
514 DEVMETHOD(bus_print_child, bus_generic_print_child),
515 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
518 DEVMETHOD(miibus_readreg, bce_miibus_read_reg),
519 DEVMETHOD(miibus_writereg, bce_miibus_write_reg),
520 DEVMETHOD(miibus_statchg, bce_miibus_statchg),
525 static driver_t bce_driver = {
528 sizeof(struct bce_softc)
531 static devclass_t bce_devclass;
534 DECLARE_DUMMY_MODULE(if_bce);
535 MODULE_DEPEND(bce, miibus, 1, 1, 1);
536 DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, NULL, NULL);
537 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
540 /****************************************************************************/
541 /* Device probe function. */
543 /* Compares the device to the driver's list of supported devices and */
544 /* reports back to the OS whether this is the right driver for the device. */
547 /* BUS_PROBE_DEFAULT on success, positive value on failure. */
548 /****************************************************************************/
550 bce_probe(device_t dev)
553 uint16_t vid, did, svid, sdid;
555 /* Get the data for the device to be probed. */
556 vid = pci_get_vendor(dev);
557 did = pci_get_device(dev);
558 svid = pci_get_subvendor(dev);
559 sdid = pci_get_subdevice(dev);
561 /* Look through the list of known devices for a match. */
562 for (t = bce_devs; t->bce_name != NULL; ++t) {
563 if (vid == t->bce_vid && did == t->bce_did &&
564 (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
565 (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
566 uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
569 descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
571 /* Print out the device identity. */
572 ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
574 ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
576 device_set_desc_copy(dev, descbuf);
577 kfree(descbuf, M_TEMP);
585 /****************************************************************************/
586 /* PCI Capabilities Probe Function. */
588 /* Walks the PCI capabiites list for the device to find what features are */
593 /****************************************************************************/
595 bce_print_adapter_info(struct bce_softc *sc)
597 device_printf(sc->bce_dev, "ASIC (0x%08X); ", sc->bce_chipid);
599 kprintf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
600 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
603 if (sc->bce_flags & BCE_PCIE_FLAG) {
604 kprintf("Bus (PCIe x%d, ", sc->link_width);
605 switch (sc->link_speed) {
607 kprintf("2.5Gbps); ");
613 kprintf("Unknown link speed); ");
617 kprintf("Bus (PCI%s, %s, %dMHz); ",
618 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
619 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
623 /* Firmware version and device features. */
624 kprintf("B/C (%s)", sc->bce_bc_ver);
626 if ((sc->bce_flags & BCE_MFW_ENABLE_FLAG) ||
627 (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
629 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
630 kprintf("MFW[%s]", sc->bce_mfw_ver);
631 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
639 /****************************************************************************/
640 /* PCI Capabilities Probe Function. */
642 /* Walks the PCI capabiites list for the device to find what features are */
647 /****************************************************************************/
649 bce_probe_pci_caps(struct bce_softc *sc)
651 device_t dev = sc->bce_dev;
654 if (pci_is_pcix(dev))
655 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
657 ptr = pci_get_pciecap_ptr(dev);
659 uint16_t link_status = pci_read_config(dev, ptr + 0x12, 2);
661 sc->link_speed = link_status & 0xf;
662 sc->link_width = (link_status >> 4) & 0x3f;
663 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
664 sc->bce_flags |= BCE_PCIE_FLAG;
669 /****************************************************************************/
670 /* Device attach function. */
672 /* Allocates device resources, performs secondary chip identification, */
673 /* resets and initializes the hardware, and initializes driver instance */
677 /* 0 on success, positive value on failure. */
678 /****************************************************************************/
680 bce_attach(device_t dev)
682 struct bce_softc *sc = device_get_softc(dev);
683 struct ifnet *ifp = &sc->arpcom.ac_if;
686 void (*irq_handle)(void *);
689 struct mii_probe_args mii_args;
690 uintptr_t mii_priv = 0;
693 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
695 pci_enable_busmaster(dev);
697 bce_probe_pci_caps(sc);
699 /* Allocate PCI memory resources. */
701 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
702 RF_ACTIVE | PCI_RF_DENSE);
703 if (sc->bce_res_mem == NULL) {
704 device_printf(dev, "PCI memory allocation failed\n");
707 sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
708 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
710 /* Allocate PCI IRQ resources. */
711 sc->bce_irq_type = pci_alloc_1intr(dev, bce_msi_enable,
712 &sc->bce_irq_rid, &irq_flags);
714 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
715 &sc->bce_irq_rid, irq_flags);
716 if (sc->bce_res_irq == NULL) {
717 device_printf(dev, "PCI map interrupt failed\n");
723 * Configure byte swap and enable indirect register access.
724 * Rely on CPU to do target byte swapping on big endian systems.
725 * Access to registers outside of PCI configurtion space are not
726 * valid until this is done.
728 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
729 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
730 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
732 /* Save ASIC revsion info. */
733 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID);
735 /* Weed out any non-production controller revisions. */
736 switch (BCE_CHIP_ID(sc)) {
737 case BCE_CHIP_ID_5706_A0:
738 case BCE_CHIP_ID_5706_A1:
739 case BCE_CHIP_ID_5708_A0:
740 case BCE_CHIP_ID_5708_B0:
741 case BCE_CHIP_ID_5709_A0:
742 case BCE_CHIP_ID_5709_B0:
743 case BCE_CHIP_ID_5709_B1:
745 /* 5709C B2 seems to work fine */
746 case BCE_CHIP_ID_5709_B2:
748 device_printf(dev, "Unsupported chip id 0x%08x!\n",
754 mii_priv |= BRGPHY_FLAG_WIRESPEED;
755 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
756 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax ||
757 BCE_CHIP_REV(sc) == BCE_CHIP_REV_Bx)
758 mii_priv |= BRGPHY_FLAG_NO_EARLYDAC;
760 mii_priv |= BRGPHY_FLAG_BER_BUG;
763 if (sc->bce_irq_type == PCI_INTR_TYPE_LEGACY) {
764 irq_handle = bce_intr_legacy;
765 } else if (sc->bce_irq_type == PCI_INTR_TYPE_MSI) {
766 irq_handle = bce_intr_msi;
767 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
768 irq_handle = bce_intr_msi_oneshot;
769 sc->bce_flags |= BCE_ONESHOT_MSI_FLAG;
772 panic("%s: unsupported intr type %d",
773 device_get_nameunit(dev), sc->bce_irq_type);
777 * Find the base address for shared memory access.
778 * Newer versions of bootcode use a signature and offset
779 * while older versions use a fixed address.
781 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
782 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) ==
783 BCE_SHM_HDR_SIGNATURE_SIG) {
784 /* Multi-port devices use different offsets in shared memory. */
785 sc->bce_shmem_base = REG_RD_IND(sc,
786 BCE_SHM_HDR_ADDR_0 + (pci_get_function(sc->bce_dev) << 2));
788 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
790 DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
792 /* Fetch the bootcode revision. */
793 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
794 for (i = 0, j = 0; i < 3; i++) {
798 num = (uint8_t)(val >> (24 - (i * 8)));
799 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
800 if (num >= k || !skip0 || k == 1) {
801 sc->bce_bc_ver[j++] = (num / k) + '0';
806 sc->bce_bc_ver[j++] = '.';
809 /* Check if any management firwmare is running. */
810 val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
811 if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
812 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
814 /* Allow time for firmware to enter the running state. */
815 for (i = 0; i < 30; i++) {
816 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
817 if (val & BCE_CONDITION_MFW_RUN_MASK)
823 /* Check the current bootcode state. */
824 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION) &
825 BCE_CONDITION_MFW_RUN_MASK;
826 if (val != BCE_CONDITION_MFW_RUN_UNKNOWN &&
827 val != BCE_CONDITION_MFW_RUN_NONE) {
828 uint32_t addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
830 for (i = 0, j = 0; j < 3; j++) {
831 val = bce_reg_rd_ind(sc, addr + j * 4);
833 memcpy(&sc->bce_mfw_ver[i], &val, 4);
838 /* Get PCI bus information (speed and type). */
839 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
840 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
843 sc->bce_flags |= BCE_PCIX_FLAG;
845 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
846 BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
848 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
849 sc->bus_speed_mhz = 133;
852 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
853 sc->bus_speed_mhz = 100;
856 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
857 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
858 sc->bus_speed_mhz = 66;
861 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
862 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
863 sc->bus_speed_mhz = 50;
866 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
867 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
868 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
869 sc->bus_speed_mhz = 33;
873 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
874 sc->bus_speed_mhz = 66;
876 sc->bus_speed_mhz = 33;
879 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
880 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
882 /* Reset the controller. */
883 rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
887 /* Initialize the controller. */
888 rc = bce_chipinit(sc);
890 device_printf(dev, "Controller initialization failed!\n");
894 /* Perform NVRAM test. */
895 rc = bce_nvram_test(sc);
897 device_printf(dev, "NVRAM test failed!\n");
901 /* Fetch the permanent Ethernet MAC address. */
902 bce_get_mac_addr(sc);
905 * Trip points control how many BDs
906 * should be ready before generating an
907 * interrupt while ticks control how long
908 * a BD can sit in the chain before
909 * generating an interrupt. Set the default
910 * values for the RX and TX rings.
914 /* Force more frequent interrupts. */
915 sc->bce_tx_quick_cons_trip_int = 1;
916 sc->bce_tx_quick_cons_trip = 1;
917 sc->bce_tx_ticks_int = 0;
918 sc->bce_tx_ticks = 0;
920 sc->bce_rx_quick_cons_trip_int = 1;
921 sc->bce_rx_quick_cons_trip = 1;
922 sc->bce_rx_ticks_int = 0;
923 sc->bce_rx_ticks = 0;
925 sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
926 sc->bce_tx_quick_cons_trip = bce_tx_bds;
927 sc->bce_tx_ticks_int = bce_tx_ticks_int;
928 sc->bce_tx_ticks = bce_tx_ticks;
930 sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
931 sc->bce_rx_quick_cons_trip = bce_rx_bds;
932 sc->bce_rx_ticks_int = bce_rx_ticks_int;
933 sc->bce_rx_ticks = bce_rx_ticks;
936 /* Update statistics once every second. */
937 sc->bce_stats_ticks = 1000000 & 0xffff00;
939 /* Find the media type for the adapter. */
942 /* Allocate DMA memory resources. */
943 rc = bce_dma_alloc(sc);
945 device_printf(dev, "DMA resource allocation failed!\n");
949 /* Initialize the ifnet interface. */
951 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
952 ifp->if_ioctl = bce_ioctl;
953 ifp->if_start = bce_start;
954 ifp->if_init = bce_init;
955 ifp->if_watchdog = bce_watchdog;
956 #ifdef DEVICE_POLLING
957 ifp->if_poll = bce_poll;
959 ifp->if_mtu = ETHERMTU;
960 ifp->if_hwassist = BCE_CSUM_FEATURES | CSUM_TSO;
961 ifp->if_capabilities = BCE_IF_CAPABILITIES;
962 ifp->if_capenable = ifp->if_capabilities;
963 ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD(sc));
964 ifq_set_ready(&ifp->if_snd);
966 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
967 ifp->if_baudrate = IF_Gbps(2.5);
969 ifp->if_baudrate = IF_Gbps(1);
971 /* Assume a standard 1500 byte MTU size for mbuf allocations. */
972 sc->mbuf_alloc_size = MCLBYTES;
977 mii_probe_args_init(&mii_args, bce_ifmedia_upd, bce_ifmedia_sts);
978 mii_args.mii_probemask = 1 << sc->bce_phy_addr;
979 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
980 mii_args.mii_priv = mii_priv;
982 rc = mii_probe(dev, &sc->bce_miibus, &mii_args);
984 device_printf(dev, "PHY probe failed!\n");
988 /* Attach to the Ethernet interface list. */
989 ether_ifattach(ifp, sc->eaddr, NULL);
991 callout_init_mp(&sc->bce_tick_callout);
992 callout_init_mp(&sc->bce_pulse_callout);
994 /* Hookup IRQ last. */
995 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_MPSAFE, irq_handle, sc,
996 &sc->bce_intrhand, ifp->if_serializer);
998 device_printf(dev, "Failed to setup IRQ!\n");
1003 ifp->if_cpuid = rman_get_cpuid(sc->bce_res_irq);
1004 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
1006 /* Print some important debugging info. */
1007 DBRUN(BCE_INFO, bce_dump_driver_state(sc));
1009 /* Add the supported sysctls to the kernel. */
1010 bce_add_sysctls(sc);
1013 * The chip reset earlier notified the bootcode that
1014 * a driver is present. We now need to start our pulse
1015 * routine so that the bootcode is reminded that we're
1020 /* Get the firmware running so IPMI still works */
1024 bce_print_adapter_info(sc);
1033 /****************************************************************************/
1034 /* Device detach function. */
1036 /* Stops the controller, resets the controller, and releases resources. */
1039 /* 0 on success, positive value on failure. */
1040 /****************************************************************************/
1042 bce_detach(device_t dev)
1044 struct bce_softc *sc = device_get_softc(dev);
1046 if (device_is_attached(dev)) {
1047 struct ifnet *ifp = &sc->arpcom.ac_if;
1050 /* Stop and reset the controller. */
1051 lwkt_serialize_enter(ifp->if_serializer);
1052 callout_stop(&sc->bce_pulse_callout);
1054 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1055 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1057 msg = BCE_DRV_MSG_CODE_UNLOAD;
1059 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
1060 lwkt_serialize_exit(ifp->if_serializer);
1062 ether_ifdetach(ifp);
1065 /* If we have a child device on the MII bus remove it too. */
1067 device_delete_child(dev, sc->bce_miibus);
1068 bus_generic_detach(dev);
1070 if (sc->bce_res_irq != NULL) {
1071 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid,
1075 if (sc->bce_irq_type == PCI_INTR_TYPE_MSI)
1076 pci_release_msi(dev);
1078 if (sc->bce_res_mem != NULL) {
1079 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
1085 if (sc->bce_sysctl_tree != NULL)
1086 sysctl_ctx_free(&sc->bce_sysctl_ctx);
1092 /****************************************************************************/
1093 /* Device shutdown function. */
1095 /* Stops and resets the controller. */
1099 /****************************************************************************/
1101 bce_shutdown(device_t dev)
1103 struct bce_softc *sc = device_get_softc(dev);
1104 struct ifnet *ifp = &sc->arpcom.ac_if;
1107 lwkt_serialize_enter(ifp->if_serializer);
1109 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1110 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1112 msg = BCE_DRV_MSG_CODE_UNLOAD;
1114 lwkt_serialize_exit(ifp->if_serializer);
1118 /****************************************************************************/
1119 /* Indirect register read. */
1121 /* Reads NetXtreme II registers using an index/data register pair in PCI */
1122 /* configuration space. Using this mechanism avoids issues with posted */
1123 /* reads but is much slower than memory-mapped I/O. */
1126 /* The value of the register. */
1127 /****************************************************************************/
1129 bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
1131 device_t dev = sc->bce_dev;
1133 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1137 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1138 DBPRINT(sc, BCE_EXCESSIVE,
1139 "%s(); offset = 0x%08X, val = 0x%08X\n",
1140 __func__, offset, val);
1144 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1149 /****************************************************************************/
1150 /* Indirect register write. */
1152 /* Writes NetXtreme II registers using an index/data register pair in PCI */
1153 /* configuration space. Using this mechanism avoids issues with posted */
1154 /* writes but is muchh slower than memory-mapped I/O. */
1158 /****************************************************************************/
1160 bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
1162 device_t dev = sc->bce_dev;
1164 DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
1165 __func__, offset, val);
1167 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1168 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1172 /****************************************************************************/
1173 /* Shared memory write. */
1175 /* Writes NetXtreme II shared memory region. */
1179 /****************************************************************************/
1181 bce_shmem_wr(struct bce_softc *sc, uint32_t offset, uint32_t val)
1183 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1187 /****************************************************************************/
1188 /* Shared memory read. */
1190 /* Reads NetXtreme II shared memory region. */
1193 /* The 32 bit value read. */
1194 /****************************************************************************/
1196 bce_shmem_rd(struct bce_softc *sc, uint32_t offset)
1198 return bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1202 /****************************************************************************/
1203 /* Context memory write. */
1205 /* The NetXtreme II controller uses context memory to track connection */
1206 /* information for L2 and higher network protocols. */
1210 /****************************************************************************/
1212 bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t ctx_offset,
1215 uint32_t idx, offset = ctx_offset + cid_addr;
1216 uint32_t val, retry_cnt = 5;
1218 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1219 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1220 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1221 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1223 for (idx = 0; idx < retry_cnt; idx++) {
1224 val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1225 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1230 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) {
1231 device_printf(sc->bce_dev,
1232 "Unable to write CTX memory: "
1233 "cid_addr = 0x%08X, offset = 0x%08X!\n",
1234 cid_addr, ctx_offset);
1237 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1238 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1243 /****************************************************************************/
1244 /* PHY register read. */
1246 /* Implements register reads on the MII bus. */
1249 /* The value of the register. */
1250 /****************************************************************************/
1252 bce_miibus_read_reg(device_t dev, int phy, int reg)
1254 struct bce_softc *sc = device_get_softc(dev);
1258 /* Make sure we are accessing the correct PHY address. */
1259 KASSERT(phy == sc->bce_phy_addr,
1260 ("invalid phyno %d, should be %d\n", phy, sc->bce_phy_addr));
1262 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1263 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1264 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1266 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1267 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1272 val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1273 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1274 BCE_EMAC_MDIO_COMM_START_BUSY;
1275 REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1277 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1280 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1281 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1284 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1285 val &= BCE_EMAC_MDIO_COMM_DATA;
1290 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1291 if_printf(&sc->arpcom.ac_if,
1292 "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1296 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1299 DBPRINT(sc, BCE_EXCESSIVE,
1300 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1301 __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff);
1303 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1304 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1305 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1307 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1308 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1312 return (val & 0xffff);
1316 /****************************************************************************/
1317 /* PHY register write. */
1319 /* Implements register writes on the MII bus. */
1322 /* The value of the register. */
1323 /****************************************************************************/
1325 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1327 struct bce_softc *sc = device_get_softc(dev);
1331 /* Make sure we are accessing the correct PHY address. */
1332 KASSERT(phy == sc->bce_phy_addr,
1333 ("invalid phyno %d, should be %d\n", phy, sc->bce_phy_addr));
1335 DBPRINT(sc, BCE_EXCESSIVE,
1336 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1337 __func__, phy, (uint16_t)(reg & 0xffff),
1338 (uint16_t)(val & 0xffff));
1340 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1341 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1342 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1344 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1345 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1350 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1351 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1352 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1353 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1355 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1358 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1359 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1365 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1366 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1368 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1369 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1370 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1372 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1373 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1381 /****************************************************************************/
1382 /* MII bus status change. */
1384 /* Called by the MII bus driver when the PHY establishes link to set the */
1385 /* MAC interface registers. */
1389 /****************************************************************************/
1391 bce_miibus_statchg(device_t dev)
1393 struct bce_softc *sc = device_get_softc(dev);
1394 struct mii_data *mii = device_get_softc(sc->bce_miibus);
1396 DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n",
1397 mii->mii_media_active);
1400 /* Decode the interface media flags. */
1401 if_printf(&sc->arpcom.ac_if, "Media: ( ");
1402 switch(IFM_TYPE(mii->mii_media_active)) {
1404 kprintf("Ethernet )");
1407 kprintf("Unknown )");
1411 kprintf(" Media Options: ( ");
1412 switch(IFM_SUBTYPE(mii->mii_media_active)) {
1414 kprintf("Autoselect )");
1417 kprintf("Manual )");
1423 kprintf("10Base-T )");
1426 kprintf("100Base-TX )");
1429 kprintf("1000Base-SX )");
1432 kprintf("1000Base-T )");
1439 kprintf(" Global Options: (");
1440 if (mii->mii_media_active & IFM_FDX)
1441 kprintf(" FullDuplex");
1442 if (mii->mii_media_active & IFM_HDX)
1443 kprintf(" HalfDuplex");
1444 if (mii->mii_media_active & IFM_LOOP)
1445 kprintf(" Loopback");
1446 if (mii->mii_media_active & IFM_FLAG0)
1448 if (mii->mii_media_active & IFM_FLAG1)
1450 if (mii->mii_media_active & IFM_FLAG2)
1455 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1458 * Set MII or GMII interface based on the speed negotiated
1461 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1462 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1463 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n");
1464 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1466 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n");
1467 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1471 * Set half or full duplex based on the duplicity negotiated
1474 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1475 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1476 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1478 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1479 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1484 /****************************************************************************/
1485 /* Acquire NVRAM lock. */
1487 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */
1488 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
1489 /* for use by the driver. */
1492 /* 0 on success, positive value on failure. */
1493 /****************************************************************************/
1495 bce_acquire_nvram_lock(struct bce_softc *sc)
1500 DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n");
1502 /* Request access to the flash interface. */
1503 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1504 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1505 val = REG_RD(sc, BCE_NVM_SW_ARB);
1506 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1512 if (j >= NVRAM_TIMEOUT_COUNT) {
1513 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1520 /****************************************************************************/
1521 /* Release NVRAM lock. */
1523 /* When the caller is finished accessing NVRAM the lock must be released. */
1524 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
1525 /* for use by the driver. */
1528 /* 0 on success, positive value on failure. */
1529 /****************************************************************************/
1531 bce_release_nvram_lock(struct bce_softc *sc)
1536 DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n");
1539 * Relinquish nvram interface.
1541 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1543 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1544 val = REG_RD(sc, BCE_NVM_SW_ARB);
1545 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1551 if (j >= NVRAM_TIMEOUT_COUNT) {
1552 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1559 /****************************************************************************/
1560 /* Enable NVRAM access. */
1562 /* Before accessing NVRAM for read or write operations the caller must */
1563 /* enabled NVRAM access. */
1567 /****************************************************************************/
1569 bce_enable_nvram_access(struct bce_softc *sc)
1573 DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n");
1575 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1576 /* Enable both bits, even on read. */
1577 REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1578 val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1582 /****************************************************************************/
1583 /* Disable NVRAM access. */
1585 /* When the caller is finished accessing NVRAM access must be disabled. */
1589 /****************************************************************************/
1591 bce_disable_nvram_access(struct bce_softc *sc)
1595 DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n");
1597 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1599 /* Disable both bits, even after read. */
1600 REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1601 val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1605 /****************************************************************************/
1606 /* Read a dword (32 bits) from NVRAM. */
1608 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */
1609 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */
1612 /* 0 on success and the 32 bit value read, positive value on failure. */
1613 /****************************************************************************/
1615 bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1621 /* Build the command word. */
1622 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1624 /* Calculate the offset for buffered flash. */
1625 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
1626 offset = ((offset / sc->bce_flash_info->page_size) <<
1627 sc->bce_flash_info->page_bits) +
1628 (offset % sc->bce_flash_info->page_size);
1632 * Clear the DONE bit separately, set the address to read,
1633 * and issue the read.
1635 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1636 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1637 REG_WR(sc, BCE_NVM_COMMAND, cmd);
1639 /* Wait for completion. */
1640 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1645 val = REG_RD(sc, BCE_NVM_COMMAND);
1646 if (val & BCE_NVM_COMMAND_DONE) {
1647 val = REG_RD(sc, BCE_NVM_READ);
1650 memcpy(ret_val, &val, 4);
1655 /* Check for errors. */
1656 if (i >= NVRAM_TIMEOUT_COUNT) {
1657 if_printf(&sc->arpcom.ac_if,
1658 "Timeout error reading NVRAM at offset 0x%08X!\n",
1666 /****************************************************************************/
1667 /* Initialize NVRAM access. */
1669 /* Identify the NVRAM device in use and prepare the NVRAM interface to */
1670 /* access that device. */
1673 /* 0 on success, positive value on failure. */
1674 /****************************************************************************/
1676 bce_init_nvram(struct bce_softc *sc)
1679 int j, entry_count, rc = 0;
1680 const struct flash_spec *flash;
1682 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
1684 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1685 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1686 sc->bce_flash_info = &flash_5709;
1687 goto bce_init_nvram_get_flash_size;
1690 /* Determine the selected interface. */
1691 val = REG_RD(sc, BCE_NVM_CFG1);
1693 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1696 * Flash reconfiguration is required to support additional
1697 * NVRAM devices not directly supported in hardware.
1698 * Check if the flash interface was reconfigured
1702 if (val & 0x40000000) {
1703 /* Flash interface reconfigured by bootcode. */
1705 DBPRINT(sc, BCE_INFO_LOAD,
1706 "%s(): Flash WAS reconfigured.\n", __func__);
1708 for (j = 0, flash = flash_table; j < entry_count;
1710 if ((val & FLASH_BACKUP_STRAP_MASK) ==
1711 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1712 sc->bce_flash_info = flash;
1717 /* Flash interface not yet reconfigured. */
1720 DBPRINT(sc, BCE_INFO_LOAD,
1721 "%s(): Flash was NOT reconfigured.\n", __func__);
1723 if (val & (1 << 23))
1724 mask = FLASH_BACKUP_STRAP_MASK;
1726 mask = FLASH_STRAP_MASK;
1728 /* Look for the matching NVRAM device configuration data. */
1729 for (j = 0, flash = flash_table; j < entry_count;
1731 /* Check if the device matches any of the known devices. */
1732 if ((val & mask) == (flash->strapping & mask)) {
1733 /* Found a device match. */
1734 sc->bce_flash_info = flash;
1736 /* Request access to the flash interface. */
1737 rc = bce_acquire_nvram_lock(sc);
1741 /* Reconfigure the flash interface. */
1742 bce_enable_nvram_access(sc);
1743 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1744 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1745 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1746 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1747 bce_disable_nvram_access(sc);
1748 bce_release_nvram_lock(sc);
1754 /* Check if a matching device was found. */
1755 if (j == entry_count) {
1756 sc->bce_flash_info = NULL;
1757 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
1761 bce_init_nvram_get_flash_size:
1762 /* Write the flash config data to the shared memory interface. */
1763 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2) &
1764 BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
1766 sc->bce_flash_size = val;
1768 sc->bce_flash_size = sc->bce_flash_info->total_size;
1770 DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n",
1771 __func__, sc->bce_flash_info->total_size);
1773 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
1779 /****************************************************************************/
1780 /* Read an arbitrary range of data from NVRAM. */
1782 /* Prepares the NVRAM interface for access and reads the requested data */
1783 /* into the supplied buffer. */
1786 /* 0 on success and the data read, positive value on failure. */
1787 /****************************************************************************/
1789 bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1792 uint32_t cmd_flags, offset32, len32, extra;
1798 /* Request access to the flash interface. */
1799 rc = bce_acquire_nvram_lock(sc);
1803 /* Enable access to flash interface */
1804 bce_enable_nvram_access(sc);
1812 /* XXX should we release nvram lock if read_dword() fails? */
1818 pre_len = 4 - (offset & 3);
1820 if (pre_len >= len32) {
1822 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1824 cmd_flags = BCE_NVM_COMMAND_FIRST;
1827 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1831 memcpy(ret_buf, buf + (offset & 3), pre_len);
1839 extra = 4 - (len32 & 3);
1840 len32 = (len32 + 4) & ~3;
1847 cmd_flags = BCE_NVM_COMMAND_LAST;
1849 cmd_flags = BCE_NVM_COMMAND_FIRST |
1850 BCE_NVM_COMMAND_LAST;
1852 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1854 memcpy(ret_buf, buf, 4 - extra);
1855 } else if (len32 > 0) {
1858 /* Read the first word. */
1862 cmd_flags = BCE_NVM_COMMAND_FIRST;
1864 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1866 /* Advance to the next dword. */
1871 while (len32 > 4 && rc == 0) {
1872 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1874 /* Advance to the next dword. */
1881 goto bce_nvram_read_locked_exit;
1883 cmd_flags = BCE_NVM_COMMAND_LAST;
1884 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1886 memcpy(ret_buf, buf, 4 - extra);
1889 bce_nvram_read_locked_exit:
1890 /* Disable access to flash interface and release the lock. */
1891 bce_disable_nvram_access(sc);
1892 bce_release_nvram_lock(sc);
1898 /****************************************************************************/
1899 /* Verifies that NVRAM is accessible and contains valid data. */
1901 /* Reads the configuration data from NVRAM and verifies that the CRC is */
1905 /* 0 on success, positive value on failure. */
1906 /****************************************************************************/
1908 bce_nvram_test(struct bce_softc *sc)
1910 uint32_t buf[BCE_NVRAM_SIZE / 4];
1911 uint32_t magic, csum;
1912 uint8_t *data = (uint8_t *)buf;
1916 * Check that the device NVRAM is valid by reading
1917 * the magic value at offset 0.
1919 rc = bce_nvram_read(sc, 0, data, 4);
1923 magic = be32toh(buf[0]);
1924 if (magic != BCE_NVRAM_MAGIC) {
1925 if_printf(&sc->arpcom.ac_if,
1926 "Invalid NVRAM magic value! Expected: 0x%08X, "
1927 "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1932 * Verify that the device NVRAM includes valid
1933 * configuration data.
1935 rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
1939 csum = ether_crc32_le(data, 0x100);
1940 if (csum != BCE_CRC32_RESIDUAL) {
1941 if_printf(&sc->arpcom.ac_if,
1942 "Invalid Manufacturing Information NVRAM CRC! "
1943 "Expected: 0x%08X, Found: 0x%08X\n",
1944 BCE_CRC32_RESIDUAL, csum);
1948 csum = ether_crc32_le(data + 0x100, 0x100);
1949 if (csum != BCE_CRC32_RESIDUAL) {
1950 if_printf(&sc->arpcom.ac_if,
1951 "Invalid Feature Configuration Information "
1952 "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
1953 BCE_CRC32_RESIDUAL, csum);
1960 /****************************************************************************/
1961 /* Identifies the current media type of the controller and sets the PHY */
1966 /****************************************************************************/
1968 bce_get_media(struct bce_softc *sc)
1972 sc->bce_phy_addr = 1;
1974 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1975 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1976 uint32_t val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
1977 uint32_t bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
1981 * The BCM5709S is software configurable
1982 * for Copper or SerDes operation.
1984 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
1986 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
1987 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1991 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) {
1992 strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
1995 (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
1998 if (pci_get_function(sc->bce_dev) == 0) {
2003 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2011 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2015 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
2016 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2019 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
2020 sc->bce_flags |= BCE_NO_WOL_FLAG;
2021 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
2022 sc->bce_phy_addr = 2;
2023 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
2024 if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
2025 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
2027 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
2028 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) {
2029 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
2034 /****************************************************************************/
2035 /* Free any DMA memory owned by the driver. */
2037 /* Scans through each data structre that requires DMA memory and frees */
2038 /* the memory if allocated. */
2042 /****************************************************************************/
2044 bce_dma_free(struct bce_softc *sc)
2048 /* Destroy the status block. */
2049 if (sc->status_tag != NULL) {
2050 if (sc->status_block != NULL) {
2051 bus_dmamap_unload(sc->status_tag, sc->status_map);
2052 bus_dmamem_free(sc->status_tag, sc->status_block,
2055 bus_dma_tag_destroy(sc->status_tag);
2058 /* Destroy the statistics block. */
2059 if (sc->stats_tag != NULL) {
2060 if (sc->stats_block != NULL) {
2061 bus_dmamap_unload(sc->stats_tag, sc->stats_map);
2062 bus_dmamem_free(sc->stats_tag, sc->stats_block,
2065 bus_dma_tag_destroy(sc->stats_tag);
2068 /* Destroy the CTX DMA stuffs. */
2069 if (sc->ctx_tag != NULL) {
2070 for (i = 0; i < sc->ctx_pages; i++) {
2071 if (sc->ctx_block[i] != NULL) {
2072 bus_dmamap_unload(sc->ctx_tag, sc->ctx_map[i]);
2073 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2077 bus_dma_tag_destroy(sc->ctx_tag);
2080 /* Destroy the TX buffer descriptor DMA stuffs. */
2081 if (sc->tx_bd_chain_tag != NULL) {
2082 for (i = 0; i < sc->tx_pages; i++) {
2083 if (sc->tx_bd_chain[i] != NULL) {
2084 bus_dmamap_unload(sc->tx_bd_chain_tag,
2085 sc->tx_bd_chain_map[i]);
2086 bus_dmamem_free(sc->tx_bd_chain_tag,
2088 sc->tx_bd_chain_map[i]);
2091 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
2094 /* Destroy the RX buffer descriptor DMA stuffs. */
2095 if (sc->rx_bd_chain_tag != NULL) {
2096 for (i = 0; i < sc->rx_pages; i++) {
2097 if (sc->rx_bd_chain[i] != NULL) {
2098 bus_dmamap_unload(sc->rx_bd_chain_tag,
2099 sc->rx_bd_chain_map[i]);
2100 bus_dmamem_free(sc->rx_bd_chain_tag,
2102 sc->rx_bd_chain_map[i]);
2105 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
2108 /* Destroy the TX mbuf DMA stuffs. */
2109 if (sc->tx_mbuf_tag != NULL) {
2110 for (i = 0; i < TOTAL_TX_BD(sc); i++) {
2111 /* Must have been unloaded in bce_stop() */
2112 KKASSERT(sc->tx_mbuf_ptr[i] == NULL);
2113 bus_dmamap_destroy(sc->tx_mbuf_tag,
2114 sc->tx_mbuf_map[i]);
2116 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2119 /* Destroy the RX mbuf DMA stuffs. */
2120 if (sc->rx_mbuf_tag != NULL) {
2121 for (i = 0; i < TOTAL_RX_BD(sc); i++) {
2122 /* Must have been unloaded in bce_stop() */
2123 KKASSERT(sc->rx_mbuf_ptr[i] == NULL);
2124 bus_dmamap_destroy(sc->rx_mbuf_tag,
2125 sc->rx_mbuf_map[i]);
2127 bus_dmamap_destroy(sc->rx_mbuf_tag, sc->rx_mbuf_tmpmap);
2128 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2131 /* Destroy the parent tag */
2132 if (sc->parent_tag != NULL)
2133 bus_dma_tag_destroy(sc->parent_tag);
2135 if (sc->tx_bd_chain_map != NULL)
2136 kfree(sc->tx_bd_chain_map, M_DEVBUF);
2137 if (sc->tx_bd_chain != NULL)
2138 kfree(sc->tx_bd_chain, M_DEVBUF);
2139 if (sc->tx_bd_chain_paddr != NULL)
2140 kfree(sc->tx_bd_chain_paddr, M_DEVBUF);
2142 if (sc->rx_bd_chain_map != NULL)
2143 kfree(sc->rx_bd_chain_map, M_DEVBUF);
2144 if (sc->rx_bd_chain != NULL)
2145 kfree(sc->rx_bd_chain, M_DEVBUF);
2146 if (sc->rx_bd_chain_paddr != NULL)
2147 kfree(sc->rx_bd_chain_paddr, M_DEVBUF);
2149 if (sc->tx_mbuf_map != NULL)
2150 kfree(sc->tx_mbuf_map, M_DEVBUF);
2151 if (sc->tx_mbuf_ptr != NULL)
2152 kfree(sc->tx_mbuf_ptr, M_DEVBUF);
2154 if (sc->rx_mbuf_map != NULL)
2155 kfree(sc->rx_mbuf_map, M_DEVBUF);
2156 if (sc->rx_mbuf_ptr != NULL)
2157 kfree(sc->rx_mbuf_ptr, M_DEVBUF);
2158 if (sc->rx_mbuf_paddr != NULL)
2159 kfree(sc->rx_mbuf_paddr, M_DEVBUF);
2163 /****************************************************************************/
2164 /* Get DMA memory from the OS. */
2166 /* Validates that the OS has provided DMA buffers in response to a */
2167 /* bus_dmamap_load() call and saves the physical address of those buffers. */
2168 /* When the callback is used the OS will return 0 for the mapping function */
2169 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */
2170 /* failures back to the caller. */
2174 /****************************************************************************/
2176 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2178 bus_addr_t *busaddr = arg;
2181 * Simulate a mapping failure.
2184 DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2185 kprintf("bce: %s(%d): Simulating DMA mapping error.\n",
2186 __FILE__, __LINE__);
2189 /* Check for an error and signal the caller that an error occurred. */
2193 KASSERT(nseg == 1, ("only one segment is allowed"));
2194 *busaddr = segs->ds_addr;
2198 /****************************************************************************/
2199 /* Allocate any DMA memory needed by the driver. */
2201 /* Allocates DMA memory needed for the various global structures needed by */
2204 /* Memory alignment requirements: */
2205 /* -----------------+----------+----------+----------+----------+ */
2206 /* Data Structure | 5706 | 5708 | 5709 | 5716 | */
2207 /* -----------------+----------+----------+----------+----------+ */
2208 /* Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */
2209 /* Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */
2210 /* RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */
2211 /* PG Buffers | none | none | none | none | */
2212 /* TX Buffers | none | none | none | none | */
2213 /* Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */
2214 /* Context Pages(1) | N/A | N/A | 4KiB | 4KiB | */
2215 /* -----------------+----------+----------+----------+----------+ */
2217 /* (1) Must align with CPU page size (BCM_PAGE_SZIE). */
2220 /* 0 for success, positive value for failure. */
2221 /****************************************************************************/
2223 bce_dma_alloc(struct bce_softc *sc)
2225 struct ifnet *ifp = &sc->arpcom.ac_if;
2226 int i, j, rc = 0, pages;
2227 bus_addr_t busaddr, max_busaddr;
2228 bus_size_t status_align, stats_align;
2230 pages = device_getenv_int(sc->bce_dev, "rx_pages", bce_rx_pages);
2231 if (pages <= 0 || pages > RX_PAGES_MAX || !powerof2(pages)) {
2232 device_printf(sc->bce_dev, "invalid # of RX pages\n");
2233 pages = RX_PAGES_DEFAULT;
2235 sc->rx_pages = pages;
2237 pages = device_getenv_int(sc->bce_dev, "tx_pages", bce_tx_pages);
2238 if (pages <= 0 || pages > TX_PAGES_MAX || !powerof2(pages)) {
2239 device_printf(sc->bce_dev, "invalid # of TX pages\n");
2240 pages = TX_PAGES_DEFAULT;
2242 sc->tx_pages = pages;
2244 sc->tx_bd_chain_map = kmalloc(sizeof(bus_dmamap_t) * sc->tx_pages,
2245 M_DEVBUF, M_WAITOK | M_ZERO);
2246 sc->tx_bd_chain = kmalloc(sizeof(struct tx_bd *) * sc->tx_pages,
2247 M_DEVBUF, M_WAITOK | M_ZERO);
2248 sc->tx_bd_chain_paddr = kmalloc(sizeof(bus_addr_t) * sc->tx_pages,
2249 M_DEVBUF, M_WAITOK | M_ZERO);
2251 sc->rx_bd_chain_map = kmalloc(sizeof(bus_dmamap_t) * sc->rx_pages,
2252 M_DEVBUF, M_WAITOK | M_ZERO);
2253 sc->rx_bd_chain = kmalloc(sizeof(struct rx_bd *) * sc->rx_pages,
2254 M_DEVBUF, M_WAITOK | M_ZERO);
2255 sc->rx_bd_chain_paddr = kmalloc(sizeof(bus_addr_t) * sc->rx_pages,
2256 M_DEVBUF, M_WAITOK | M_ZERO);
2258 sc->tx_mbuf_map = kmalloc(sizeof(bus_dmamap_t) * TOTAL_TX_BD(sc),
2259 M_DEVBUF, M_WAITOK | M_ZERO);
2260 sc->tx_mbuf_ptr = kmalloc(sizeof(struct mbuf *) * TOTAL_TX_BD(sc),
2261 M_DEVBUF, M_WAITOK | M_ZERO);
2263 sc->rx_mbuf_map = kmalloc(sizeof(bus_dmamap_t) * TOTAL_RX_BD(sc),
2264 M_DEVBUF, M_WAITOK | M_ZERO);
2265 sc->rx_mbuf_ptr = kmalloc(sizeof(struct mbuf *) * TOTAL_RX_BD(sc),
2266 M_DEVBUF, M_WAITOK | M_ZERO);
2267 sc->rx_mbuf_paddr = kmalloc(sizeof(bus_addr_t) * TOTAL_RX_BD(sc),
2268 M_DEVBUF, M_WAITOK | M_ZERO);
2271 * The embedded PCIe to PCI-X bridge (EPB)
2272 * in the 5708 cannot address memory above
2273 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
2275 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
2276 max_busaddr = BCE_BUS_SPACE_MAXADDR;
2278 max_busaddr = BUS_SPACE_MAXADDR;
2281 * BCM5709 and BCM5716 uses host memory as cache for context memory.
2283 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2284 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2285 sc->ctx_pages = BCE_CTX_BLK_SZ / BCM_PAGE_SIZE;
2286 if (sc->ctx_pages == 0)
2288 if (sc->ctx_pages > BCE_CTX_PAGES) {
2289 device_printf(sc->bce_dev, "excessive ctx pages %d\n",
2301 * Allocate the parent bus DMA tag appropriate for PCI.
2303 rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
2304 max_busaddr, BUS_SPACE_MAXADDR,
2306 BUS_SPACE_MAXSIZE_32BIT, 0,
2307 BUS_SPACE_MAXSIZE_32BIT,
2308 0, &sc->parent_tag);
2310 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2315 * Allocate status block.
2317 sc->status_block = bus_dmamem_coherent_any(sc->parent_tag,
2318 status_align, BCE_STATUS_BLK_SZ,
2319 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2320 &sc->status_tag, &sc->status_map,
2321 &sc->status_block_paddr);
2322 if (sc->status_block == NULL) {
2323 if_printf(ifp, "Could not allocate status block!\n");
2328 * Allocate statistics block.
2330 sc->stats_block = bus_dmamem_coherent_any(sc->parent_tag,
2331 stats_align, BCE_STATS_BLK_SZ,
2332 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2333 &sc->stats_tag, &sc->stats_map,
2334 &sc->stats_block_paddr);
2335 if (sc->stats_block == NULL) {
2336 if_printf(ifp, "Could not allocate statistics block!\n");
2341 * Allocate context block, if needed
2343 if (sc->ctx_pages != 0) {
2344 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2345 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2347 BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
2350 if_printf(ifp, "Could not allocate "
2351 "context block DMA tag!\n");
2355 for (i = 0; i < sc->ctx_pages; i++) {
2356 rc = bus_dmamem_alloc(sc->ctx_tag,
2357 (void **)&sc->ctx_block[i],
2358 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2362 if_printf(ifp, "Could not allocate %dth context "
2363 "DMA memory!\n", i);
2367 rc = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
2368 sc->ctx_block[i], BCM_PAGE_SIZE,
2369 bce_dma_map_addr, &busaddr,
2372 if (rc == EINPROGRESS) {
2373 panic("%s coherent memory loading "
2374 "is still in progress!", ifp->if_xname);
2376 if_printf(ifp, "Could not map %dth context "
2377 "DMA memory!\n", i);
2378 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2380 sc->ctx_block[i] = NULL;
2383 sc->ctx_paddr[i] = busaddr;
2388 * Create a DMA tag for the TX buffer descriptor chain,
2389 * allocate and clear the memory, and fetch the
2390 * physical address of the block.
2392 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2393 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2395 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2396 0, &sc->tx_bd_chain_tag);
2398 if_printf(ifp, "Could not allocate "
2399 "TX descriptor chain DMA tag!\n");
2403 for (i = 0; i < sc->tx_pages; i++) {
2404 rc = bus_dmamem_alloc(sc->tx_bd_chain_tag,
2405 (void **)&sc->tx_bd_chain[i],
2406 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2408 &sc->tx_bd_chain_map[i]);
2410 if_printf(ifp, "Could not allocate %dth TX descriptor "
2411 "chain DMA memory!\n", i);
2415 rc = bus_dmamap_load(sc->tx_bd_chain_tag,
2416 sc->tx_bd_chain_map[i],
2417 sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ,
2418 bce_dma_map_addr, &busaddr,
2421 if (rc == EINPROGRESS) {
2422 panic("%s coherent memory loading "
2423 "is still in progress!", ifp->if_xname);
2425 if_printf(ifp, "Could not map %dth TX descriptor "
2426 "chain DMA memory!\n", i);
2427 bus_dmamem_free(sc->tx_bd_chain_tag,
2429 sc->tx_bd_chain_map[i]);
2430 sc->tx_bd_chain[i] = NULL;
2434 sc->tx_bd_chain_paddr[i] = busaddr;
2435 /* DRC - Fix for 64 bit systems. */
2436 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n",
2437 i, (uint32_t)sc->tx_bd_chain_paddr[i]);
2440 /* Create a DMA tag for TX mbufs. */
2441 rc = bus_dma_tag_create(sc->parent_tag, 1, 0,
2442 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2444 IP_MAXPACKET + sizeof(struct ether_vlan_header),
2445 BCE_MAX_SEGMENTS, PAGE_SIZE,
2446 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2450 if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n");
2454 /* Create DMA maps for the TX mbufs clusters. */
2455 for (i = 0; i < TOTAL_TX_BD(sc); i++) {
2456 rc = bus_dmamap_create(sc->tx_mbuf_tag,
2457 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2458 &sc->tx_mbuf_map[i]);
2460 for (j = 0; j < i; ++j) {
2461 bus_dmamap_destroy(sc->tx_mbuf_tag,
2462 sc->tx_mbuf_map[i]);
2464 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2465 sc->tx_mbuf_tag = NULL;
2467 if_printf(ifp, "Unable to create "
2468 "%dth TX mbuf DMA map!\n", i);
2474 * Create a DMA tag for the RX buffer descriptor chain,
2475 * allocate and clear the memory, and fetch the physical
2476 * address of the blocks.
2478 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2479 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2481 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2482 0, &sc->rx_bd_chain_tag);
2484 if_printf(ifp, "Could not allocate "
2485 "RX descriptor chain DMA tag!\n");
2489 for (i = 0; i < sc->rx_pages; i++) {
2490 rc = bus_dmamem_alloc(sc->rx_bd_chain_tag,
2491 (void **)&sc->rx_bd_chain[i],
2492 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2494 &sc->rx_bd_chain_map[i]);
2496 if_printf(ifp, "Could not allocate %dth RX descriptor "
2497 "chain DMA memory!\n", i);
2501 rc = bus_dmamap_load(sc->rx_bd_chain_tag,
2502 sc->rx_bd_chain_map[i],
2503 sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ,
2504 bce_dma_map_addr, &busaddr,
2507 if (rc == EINPROGRESS) {
2508 panic("%s coherent memory loading "
2509 "is still in progress!", ifp->if_xname);
2511 if_printf(ifp, "Could not map %dth RX descriptor "
2512 "chain DMA memory!\n", i);
2513 bus_dmamem_free(sc->rx_bd_chain_tag,
2515 sc->rx_bd_chain_map[i]);
2516 sc->rx_bd_chain[i] = NULL;
2520 sc->rx_bd_chain_paddr[i] = busaddr;
2521 /* DRC - Fix for 64 bit systems. */
2522 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2523 i, (uint32_t)sc->rx_bd_chain_paddr[i]);
2526 /* Create a DMA tag for RX mbufs. */
2527 rc = bus_dma_tag_create(sc->parent_tag, BCE_DMA_RX_ALIGN, 0,
2528 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2530 MCLBYTES, 1, MCLBYTES,
2531 BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED |
2535 if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n");
2539 /* Create tmp DMA map for RX mbuf clusters. */
2540 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2541 &sc->rx_mbuf_tmpmap);
2543 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2544 sc->rx_mbuf_tag = NULL;
2546 if_printf(ifp, "Could not create RX mbuf tmp DMA map!\n");
2550 /* Create DMA maps for the RX mbuf clusters. */
2551 for (i = 0; i < TOTAL_RX_BD(sc); i++) {
2552 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2553 &sc->rx_mbuf_map[i]);
2555 for (j = 0; j < i; ++j) {
2556 bus_dmamap_destroy(sc->rx_mbuf_tag,
2557 sc->rx_mbuf_map[j]);
2559 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2560 sc->rx_mbuf_tag = NULL;
2562 if_printf(ifp, "Unable to create "
2563 "%dth RX mbuf DMA map!\n", i);
2571 /****************************************************************************/
2572 /* Firmware synchronization. */
2574 /* Before performing certain events such as a chip reset, synchronize with */
2575 /* the firmware first. */
2578 /* 0 for success, positive value for failure. */
2579 /****************************************************************************/
2581 bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2586 /* Don't waste any time if we've timed out before. */
2587 if (sc->bce_fw_timed_out)
2590 /* Increment the message sequence number. */
2591 sc->bce_fw_wr_seq++;
2592 msg_data |= sc->bce_fw_wr_seq;
2594 DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
2596 /* Send the message to the bootcode driver mailbox. */
2597 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2599 /* Wait for the bootcode to acknowledge the message. */
2600 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2601 /* Check for a response in the bootcode firmware mailbox. */
2602 val = bce_shmem_rd(sc, BCE_FW_MB);
2603 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2608 /* If we've timed out, tell the bootcode that we've stopped waiting. */
2609 if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2610 (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2611 if_printf(&sc->arpcom.ac_if,
2612 "Firmware synchronization timeout! "
2613 "msg_data = 0x%08X\n", msg_data);
2615 msg_data &= ~BCE_DRV_MSG_CODE;
2616 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2618 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2620 sc->bce_fw_timed_out = 1;
2627 /****************************************************************************/
2628 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */
2632 /****************************************************************************/
2634 bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2635 uint32_t rv2p_code_len, uint32_t rv2p_proc)
2640 for (i = 0; i < rv2p_code_len; i += 8) {
2641 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2643 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2646 if (rv2p_proc == RV2P_PROC1) {
2647 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2648 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2650 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2651 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2655 /* Reset the processor, un-stall is done later. */
2656 if (rv2p_proc == RV2P_PROC1)
2657 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2659 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2663 /****************************************************************************/
2664 /* Load RISC processor firmware. */
2666 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */
2667 /* associated with a particular processor. */
2671 /****************************************************************************/
2673 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2679 bce_halt_cpu(sc, cpu_reg);
2681 /* Load the Text area. */
2682 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2684 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2685 REG_WR_IND(sc, offset, fw->text[j]);
2688 /* Load the Data area. */
2689 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2691 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2692 REG_WR_IND(sc, offset, fw->data[j]);
2695 /* Load the SBSS area. */
2696 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2698 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2699 REG_WR_IND(sc, offset, fw->sbss[j]);
2702 /* Load the BSS area. */
2703 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2705 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2706 REG_WR_IND(sc, offset, fw->bss[j]);
2709 /* Load the Read-Only area. */
2710 offset = cpu_reg->spad_base +
2711 (fw->rodata_addr - cpu_reg->mips_view_base);
2713 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2714 REG_WR_IND(sc, offset, fw->rodata[j]);
2717 /* Clear the pre-fetch instruction and set the FW start address. */
2718 REG_WR_IND(sc, cpu_reg->inst, 0);
2719 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2723 /****************************************************************************/
2724 /* Starts the RISC processor. */
2726 /* Assumes the CPU starting address has already been set. */
2730 /****************************************************************************/
2732 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2736 /* Start the CPU. */
2737 val = REG_RD_IND(sc, cpu_reg->mode);
2738 val &= ~cpu_reg->mode_value_halt;
2739 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2740 REG_WR_IND(sc, cpu_reg->mode, val);
2744 /****************************************************************************/
2745 /* Halts the RISC processor. */
2749 /****************************************************************************/
2751 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2756 val = REG_RD_IND(sc, cpu_reg->mode);
2757 val |= cpu_reg->mode_value_halt;
2758 REG_WR_IND(sc, cpu_reg->mode, val);
2759 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2763 /****************************************************************************/
2764 /* Start the RX CPU. */
2768 /****************************************************************************/
2770 bce_start_rxp_cpu(struct bce_softc *sc)
2772 struct cpu_reg cpu_reg;
2774 cpu_reg.mode = BCE_RXP_CPU_MODE;
2775 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2776 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2777 cpu_reg.state = BCE_RXP_CPU_STATE;
2778 cpu_reg.state_value_clear = 0xffffff;
2779 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2780 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2781 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2782 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2783 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2784 cpu_reg.spad_base = BCE_RXP_SCRATCH;
2785 cpu_reg.mips_view_base = 0x8000000;
2787 bce_start_cpu(sc, &cpu_reg);
2791 /****************************************************************************/
2792 /* Initialize the RX CPU. */
2796 /****************************************************************************/
2798 bce_init_rxp_cpu(struct bce_softc *sc)
2800 struct cpu_reg cpu_reg;
2803 cpu_reg.mode = BCE_RXP_CPU_MODE;
2804 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2805 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2806 cpu_reg.state = BCE_RXP_CPU_STATE;
2807 cpu_reg.state_value_clear = 0xffffff;
2808 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2809 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2810 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2811 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2812 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2813 cpu_reg.spad_base = BCE_RXP_SCRATCH;
2814 cpu_reg.mips_view_base = 0x8000000;
2816 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2817 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2818 fw.ver_major = bce_RXP_b09FwReleaseMajor;
2819 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
2820 fw.ver_fix = bce_RXP_b09FwReleaseFix;
2821 fw.start_addr = bce_RXP_b09FwStartAddr;
2823 fw.text_addr = bce_RXP_b09FwTextAddr;
2824 fw.text_len = bce_RXP_b09FwTextLen;
2826 fw.text = bce_RXP_b09FwText;
2828 fw.data_addr = bce_RXP_b09FwDataAddr;
2829 fw.data_len = bce_RXP_b09FwDataLen;
2831 fw.data = bce_RXP_b09FwData;
2833 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
2834 fw.sbss_len = bce_RXP_b09FwSbssLen;
2836 fw.sbss = bce_RXP_b09FwSbss;
2838 fw.bss_addr = bce_RXP_b09FwBssAddr;
2839 fw.bss_len = bce_RXP_b09FwBssLen;
2841 fw.bss = bce_RXP_b09FwBss;
2843 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
2844 fw.rodata_len = bce_RXP_b09FwRodataLen;
2845 fw.rodata_index = 0;
2846 fw.rodata = bce_RXP_b09FwRodata;
2848 fw.ver_major = bce_RXP_b06FwReleaseMajor;
2849 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2850 fw.ver_fix = bce_RXP_b06FwReleaseFix;
2851 fw.start_addr = bce_RXP_b06FwStartAddr;
2853 fw.text_addr = bce_RXP_b06FwTextAddr;
2854 fw.text_len = bce_RXP_b06FwTextLen;
2856 fw.text = bce_RXP_b06FwText;
2858 fw.data_addr = bce_RXP_b06FwDataAddr;
2859 fw.data_len = bce_RXP_b06FwDataLen;
2861 fw.data = bce_RXP_b06FwData;
2863 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2864 fw.sbss_len = bce_RXP_b06FwSbssLen;
2866 fw.sbss = bce_RXP_b06FwSbss;
2868 fw.bss_addr = bce_RXP_b06FwBssAddr;
2869 fw.bss_len = bce_RXP_b06FwBssLen;
2871 fw.bss = bce_RXP_b06FwBss;
2873 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2874 fw.rodata_len = bce_RXP_b06FwRodataLen;
2875 fw.rodata_index = 0;
2876 fw.rodata = bce_RXP_b06FwRodata;
2879 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
2880 bce_load_cpu_fw(sc, &cpu_reg, &fw);
2881 /* Delay RXP start until initialization is complete. */
2885 /****************************************************************************/
2886 /* Initialize the TX CPU. */
2890 /****************************************************************************/
2892 bce_init_txp_cpu(struct bce_softc *sc)
2894 struct cpu_reg cpu_reg;
2897 cpu_reg.mode = BCE_TXP_CPU_MODE;
2898 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2899 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2900 cpu_reg.state = BCE_TXP_CPU_STATE;
2901 cpu_reg.state_value_clear = 0xffffff;
2902 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2903 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2904 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2905 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2906 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2907 cpu_reg.spad_base = BCE_TXP_SCRATCH;
2908 cpu_reg.mips_view_base = 0x8000000;
2910 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2911 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2912 fw.ver_major = bce_TXP_b09FwReleaseMajor;
2913 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
2914 fw.ver_fix = bce_TXP_b09FwReleaseFix;
2915 fw.start_addr = bce_TXP_b09FwStartAddr;
2917 fw.text_addr = bce_TXP_b09FwTextAddr;
2918 fw.text_len = bce_TXP_b09FwTextLen;
2920 fw.text = bce_TXP_b09FwText;
2922 fw.data_addr = bce_TXP_b09FwDataAddr;
2923 fw.data_len = bce_TXP_b09FwDataLen;
2925 fw.data = bce_TXP_b09FwData;
2927 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
2928 fw.sbss_len = bce_TXP_b09FwSbssLen;
2930 fw.sbss = bce_TXP_b09FwSbss;
2932 fw.bss_addr = bce_TXP_b09FwBssAddr;
2933 fw.bss_len = bce_TXP_b09FwBssLen;
2935 fw.bss = bce_TXP_b09FwBss;
2937 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
2938 fw.rodata_len = bce_TXP_b09FwRodataLen;
2939 fw.rodata_index = 0;
2940 fw.rodata = bce_TXP_b09FwRodata;
2942 fw.ver_major = bce_TXP_b06FwReleaseMajor;
2943 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2944 fw.ver_fix = bce_TXP_b06FwReleaseFix;
2945 fw.start_addr = bce_TXP_b06FwStartAddr;
2947 fw.text_addr = bce_TXP_b06FwTextAddr;
2948 fw.text_len = bce_TXP_b06FwTextLen;
2950 fw.text = bce_TXP_b06FwText;
2952 fw.data_addr = bce_TXP_b06FwDataAddr;
2953 fw.data_len = bce_TXP_b06FwDataLen;
2955 fw.data = bce_TXP_b06FwData;
2957 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2958 fw.sbss_len = bce_TXP_b06FwSbssLen;
2960 fw.sbss = bce_TXP_b06FwSbss;
2962 fw.bss_addr = bce_TXP_b06FwBssAddr;
2963 fw.bss_len = bce_TXP_b06FwBssLen;
2965 fw.bss = bce_TXP_b06FwBss;
2967 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2968 fw.rodata_len = bce_TXP_b06FwRodataLen;
2969 fw.rodata_index = 0;
2970 fw.rodata = bce_TXP_b06FwRodata;
2973 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
2974 bce_load_cpu_fw(sc, &cpu_reg, &fw);
2975 bce_start_cpu(sc, &cpu_reg);
2979 /****************************************************************************/
2980 /* Initialize the TPAT CPU. */
2984 /****************************************************************************/
2986 bce_init_tpat_cpu(struct bce_softc *sc)
2988 struct cpu_reg cpu_reg;
2991 cpu_reg.mode = BCE_TPAT_CPU_MODE;
2992 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2993 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2994 cpu_reg.state = BCE_TPAT_CPU_STATE;
2995 cpu_reg.state_value_clear = 0xffffff;
2996 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2997 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2998 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2999 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
3000 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
3001 cpu_reg.spad_base = BCE_TPAT_SCRATCH;
3002 cpu_reg.mips_view_base = 0x8000000;
3004 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3005 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3006 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
3007 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
3008 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
3009 fw.start_addr = bce_TPAT_b09FwStartAddr;
3011 fw.text_addr = bce_TPAT_b09FwTextAddr;
3012 fw.text_len = bce_TPAT_b09FwTextLen;
3014 fw.text = bce_TPAT_b09FwText;
3016 fw.data_addr = bce_TPAT_b09FwDataAddr;
3017 fw.data_len = bce_TPAT_b09FwDataLen;
3019 fw.data = bce_TPAT_b09FwData;
3021 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
3022 fw.sbss_len = bce_TPAT_b09FwSbssLen;
3024 fw.sbss = bce_TPAT_b09FwSbss;
3026 fw.bss_addr = bce_TPAT_b09FwBssAddr;
3027 fw.bss_len = bce_TPAT_b09FwBssLen;
3029 fw.bss = bce_TPAT_b09FwBss;
3031 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
3032 fw.rodata_len = bce_TPAT_b09FwRodataLen;
3033 fw.rodata_index = 0;
3034 fw.rodata = bce_TPAT_b09FwRodata;
3036 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
3037 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
3038 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
3039 fw.start_addr = bce_TPAT_b06FwStartAddr;
3041 fw.text_addr = bce_TPAT_b06FwTextAddr;
3042 fw.text_len = bce_TPAT_b06FwTextLen;
3044 fw.text = bce_TPAT_b06FwText;
3046 fw.data_addr = bce_TPAT_b06FwDataAddr;
3047 fw.data_len = bce_TPAT_b06FwDataLen;
3049 fw.data = bce_TPAT_b06FwData;
3051 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
3052 fw.sbss_len = bce_TPAT_b06FwSbssLen;
3054 fw.sbss = bce_TPAT_b06FwSbss;
3056 fw.bss_addr = bce_TPAT_b06FwBssAddr;
3057 fw.bss_len = bce_TPAT_b06FwBssLen;
3059 fw.bss = bce_TPAT_b06FwBss;
3061 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
3062 fw.rodata_len = bce_TPAT_b06FwRodataLen;
3063 fw.rodata_index = 0;
3064 fw.rodata = bce_TPAT_b06FwRodata;
3067 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
3068 bce_load_cpu_fw(sc, &cpu_reg, &fw);
3069 bce_start_cpu(sc, &cpu_reg);
3073 /****************************************************************************/
3074 /* Initialize the CP CPU. */
3078 /****************************************************************************/
3080 bce_init_cp_cpu(struct bce_softc *sc)
3082 struct cpu_reg cpu_reg;
3085 cpu_reg.mode = BCE_CP_CPU_MODE;
3086 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
3087 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
3088 cpu_reg.state = BCE_CP_CPU_STATE;
3089 cpu_reg.state_value_clear = 0xffffff;
3090 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
3091 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
3092 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
3093 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
3094 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
3095 cpu_reg.spad_base = BCE_CP_SCRATCH;
3096 cpu_reg.mips_view_base = 0x8000000;
3098 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3099 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3100 fw.ver_major = bce_CP_b09FwReleaseMajor;
3101 fw.ver_minor = bce_CP_b09FwReleaseMinor;
3102 fw.ver_fix = bce_CP_b09FwReleaseFix;
3103 fw.start_addr = bce_CP_b09FwStartAddr;
3105 fw.text_addr = bce_CP_b09FwTextAddr;
3106 fw.text_len = bce_CP_b09FwTextLen;
3108 fw.text = bce_CP_b09FwText;
3110 fw.data_addr = bce_CP_b09FwDataAddr;
3111 fw.data_len = bce_CP_b09FwDataLen;
3113 fw.data = bce_CP_b09FwData;
3115 fw.sbss_addr = bce_CP_b09FwSbssAddr;
3116 fw.sbss_len = bce_CP_b09FwSbssLen;
3118 fw.sbss = bce_CP_b09FwSbss;
3120 fw.bss_addr = bce_CP_b09FwBssAddr;
3121 fw.bss_len = bce_CP_b09FwBssLen;
3123 fw.bss = bce_CP_b09FwBss;
3125 fw.rodata_addr = bce_CP_b09FwRodataAddr;
3126 fw.rodata_len = bce_CP_b09FwRodataLen;
3127 fw.rodata_index = 0;
3128 fw.rodata = bce_CP_b09FwRodata;
3130 fw.ver_major = bce_CP_b06FwReleaseMajor;
3131 fw.ver_minor = bce_CP_b06FwReleaseMinor;
3132 fw.ver_fix = bce_CP_b06FwReleaseFix;
3133 fw.start_addr = bce_CP_b06FwStartAddr;
3135 fw.text_addr = bce_CP_b06FwTextAddr;
3136 fw.text_len = bce_CP_b06FwTextLen;
3138 fw.text = bce_CP_b06FwText;
3140 fw.data_addr = bce_CP_b06FwDataAddr;
3141 fw.data_len = bce_CP_b06FwDataLen;
3143 fw.data = bce_CP_b06FwData;
3145 fw.sbss_addr = bce_CP_b06FwSbssAddr;
3146 fw.sbss_len = bce_CP_b06FwSbssLen;
3148 fw.sbss = bce_CP_b06FwSbss;
3150 fw.bss_addr = bce_CP_b06FwBssAddr;
3151 fw.bss_len = bce_CP_b06FwBssLen;
3153 fw.bss = bce_CP_b06FwBss;
3155 fw.rodata_addr = bce_CP_b06FwRodataAddr;
3156 fw.rodata_len = bce_CP_b06FwRodataLen;
3157 fw.rodata_index = 0;
3158 fw.rodata = bce_CP_b06FwRodata;
3161 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
3162 bce_load_cpu_fw(sc, &cpu_reg, &fw);
3163 bce_start_cpu(sc, &cpu_reg);
3167 /****************************************************************************/
3168 /* Initialize the COM CPU. */
3172 /****************************************************************************/
3174 bce_init_com_cpu(struct bce_softc *sc)
3176 struct cpu_reg cpu_reg;
3179 cpu_reg.mode = BCE_COM_CPU_MODE;
3180 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
3181 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
3182 cpu_reg.state = BCE_COM_CPU_STATE;
3183 cpu_reg.state_value_clear = 0xffffff;
3184 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
3185 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
3186 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
3187 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
3188 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
3189 cpu_reg.spad_base = BCE_COM_SCRATCH;
3190 cpu_reg.mips_view_base = 0x8000000;
3192 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3193 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3194 fw.ver_major = bce_COM_b09FwReleaseMajor;
3195 fw.ver_minor = bce_COM_b09FwReleaseMinor;
3196 fw.ver_fix = bce_COM_b09FwReleaseFix;
3197 fw.start_addr = bce_COM_b09FwStartAddr;
3199 fw.text_addr = bce_COM_b09FwTextAddr;
3200 fw.text_len = bce_COM_b09FwTextLen;
3202 fw.text = bce_COM_b09FwText;
3204 fw.data_addr = bce_COM_b09FwDataAddr;
3205 fw.data_len = bce_COM_b09FwDataLen;
3207 fw.data = bce_COM_b09FwData;
3209 fw.sbss_addr = bce_COM_b09FwSbssAddr;
3210 fw.sbss_len = bce_COM_b09FwSbssLen;
3212 fw.sbss = bce_COM_b09FwSbss;
3214 fw.bss_addr = bce_COM_b09FwBssAddr;
3215 fw.bss_len = bce_COM_b09FwBssLen;
3217 fw.bss = bce_COM_b09FwBss;
3219 fw.rodata_addr = bce_COM_b09FwRodataAddr;
3220 fw.rodata_len = bce_COM_b09FwRodataLen;
3221 fw.rodata_index = 0;
3222 fw.rodata = bce_COM_b09FwRodata;
3224 fw.ver_major = bce_COM_b06FwReleaseMajor;
3225 fw.ver_minor = bce_COM_b06FwReleaseMinor;
3226 fw.ver_fix = bce_COM_b06FwReleaseFix;
3227 fw.start_addr = bce_COM_b06FwStartAddr;
3229 fw.text_addr = bce_COM_b06FwTextAddr;
3230 fw.text_len = bce_COM_b06FwTextLen;
3232 fw.text = bce_COM_b06FwText;
3234 fw.data_addr = bce_COM_b06FwDataAddr;
3235 fw.data_len = bce_COM_b06FwDataLen;
3237 fw.data = bce_COM_b06FwData;
3239 fw.sbss_addr = bce_COM_b06FwSbssAddr;
3240 fw.sbss_len = bce_COM_b06FwSbssLen;
3242 fw.sbss = bce_COM_b06FwSbss;
3244 fw.bss_addr = bce_COM_b06FwBssAddr;
3245 fw.bss_len = bce_COM_b06FwBssLen;
3247 fw.bss = bce_COM_b06FwBss;
3249 fw.rodata_addr = bce_COM_b06FwRodataAddr;
3250 fw.rodata_len = bce_COM_b06FwRodataLen;
3251 fw.rodata_index = 0;
3252 fw.rodata = bce_COM_b06FwRodata;
3255 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
3256 bce_load_cpu_fw(sc, &cpu_reg, &fw);
3257 bce_start_cpu(sc, &cpu_reg);
3261 /****************************************************************************/
3262 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */
3264 /* Loads the firmware for each CPU and starts the CPU. */
3268 /****************************************************************************/
3270 bce_init_cpus(struct bce_softc *sc)
3272 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3273 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3274 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax) {
3275 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
3276 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
3277 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
3278 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
3280 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
3281 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
3282 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
3283 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
3286 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
3287 sizeof(bce_rv2p_proc1), RV2P_PROC1);
3288 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
3289 sizeof(bce_rv2p_proc2), RV2P_PROC2);
3292 bce_init_rxp_cpu(sc);
3293 bce_init_txp_cpu(sc);
3294 bce_init_tpat_cpu(sc);
3295 bce_init_com_cpu(sc);
3296 bce_init_cp_cpu(sc);
3300 /****************************************************************************/
3301 /* Initialize context memory. */
3303 /* Clears the memory associated with each Context ID (CID). */
3307 /****************************************************************************/
3309 bce_init_ctx(struct bce_softc *sc)
3311 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3312 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3313 /* DRC: Replace this constant value with a #define. */
3314 int i, retry_cnt = 10;
3318 * BCM5709 context memory may be cached
3319 * in host memory so prepare the host memory
3322 val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT |
3324 val |= (BCM_PAGE_BITS - 8) << 16;
3325 REG_WR(sc, BCE_CTX_COMMAND, val);
3327 /* Wait for mem init command to complete. */
3328 for (i = 0; i < retry_cnt; i++) {
3329 val = REG_RD(sc, BCE_CTX_COMMAND);
3330 if (!(val & BCE_CTX_COMMAND_MEM_INIT))
3334 if (i == retry_cnt) {
3335 device_printf(sc->bce_dev,
3336 "Context memory initialization failed!\n");
3340 for (i = 0; i < sc->ctx_pages; i++) {
3344 * Set the physical address of the context
3347 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
3348 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
3349 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
3350 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
3351 BCE_ADDR_HI(sc->ctx_paddr[i]));
3352 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL,
3353 i | BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
3356 * Verify that the context memory write was successful.
3358 for (j = 0; j < retry_cnt; j++) {
3359 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
3361 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
3365 if (j == retry_cnt) {
3366 device_printf(sc->bce_dev,
3367 "Failed to initialize context page!\n");
3372 uint32_t vcid_addr, offset;
3375 * For the 5706/5708, context memory is local to
3376 * the controller, so initialize the controller
3380 vcid_addr = GET_CID_ADDR(96);
3382 vcid_addr -= PHY_CTX_SIZE;
3384 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
3385 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3387 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
3388 CTX_WR(sc, 0x00, offset, 0);
3390 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
3391 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3398 /****************************************************************************/
3399 /* Fetch the permanent MAC address of the controller. */
3403 /****************************************************************************/
3405 bce_get_mac_addr(struct bce_softc *sc)
3407 uint32_t mac_lo = 0, mac_hi = 0;
3410 * The NetXtreme II bootcode populates various NIC
3411 * power-on and runtime configuration items in a
3412 * shared memory area. The factory configured MAC
3413 * address is available from both NVRAM and the
3414 * shared memory area so we'll read the value from
3415 * shared memory for speed.
3418 mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER);
3419 mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
3421 if (mac_lo == 0 && mac_hi == 0) {
3422 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
3424 sc->eaddr[0] = (u_char)(mac_hi >> 8);
3425 sc->eaddr[1] = (u_char)(mac_hi >> 0);
3426 sc->eaddr[2] = (u_char)(mac_lo >> 24);
3427 sc->eaddr[3] = (u_char)(mac_lo >> 16);
3428 sc->eaddr[4] = (u_char)(mac_lo >> 8);
3429 sc->eaddr[5] = (u_char)(mac_lo >> 0);
3432 DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
3436 /****************************************************************************/
3437 /* Program the MAC address. */
3441 /****************************************************************************/
3443 bce_set_mac_addr(struct bce_softc *sc)
3445 const uint8_t *mac_addr = sc->eaddr;
3448 DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n",
3451 val = (mac_addr[0] << 8) | mac_addr[1];
3452 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
3454 val = (mac_addr[2] << 24) |
3455 (mac_addr[3] << 16) |
3456 (mac_addr[4] << 8) |
3458 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
3462 /****************************************************************************/
3463 /* Stop the controller. */
3467 /****************************************************************************/
3469 bce_stop(struct bce_softc *sc)
3471 struct ifnet *ifp = &sc->arpcom.ac_if;
3473 ASSERT_SERIALIZED(ifp->if_serializer);
3475 callout_stop(&sc->bce_tick_callout);
3477 /* Disable the transmit/receive blocks. */
3478 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
3479 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3482 bce_disable_intr(sc);
3484 /* Free the RX lists. */
3485 bce_free_rx_chain(sc);
3487 /* Free TX buffers. */
3488 bce_free_tx_chain(sc);
3491 sc->bce_coalchg_mask = 0;
3493 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3499 bce_reset(struct bce_softc *sc, uint32_t reset_code)
3504 /* Wait for pending PCI transactions to complete. */
3505 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
3506 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3507 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3508 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3509 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3510 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3514 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3515 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3516 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3517 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3518 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3521 /* Assume bootcode is running. */
3522 sc->bce_fw_timed_out = 0;
3523 sc->bce_drv_cardiac_arrest = 0;
3525 /* Give the firmware a chance to prepare for the reset. */
3526 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
3528 if_printf(&sc->arpcom.ac_if,
3529 "Firmware is not ready for reset\n");
3533 /* Set a firmware reminder that this is a soft reset. */
3534 bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE,
3535 BCE_DRV_RESET_SIGNATURE_MAGIC);
3537 /* Dummy read to force the chip to complete all current transactions. */
3538 val = REG_RD(sc, BCE_MISC_ID);
3541 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3542 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3543 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
3544 REG_RD(sc, BCE_MISC_COMMAND);
3547 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3548 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3550 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
3552 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3553 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3554 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3555 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
3557 /* Allow up to 30us for reset to complete. */
3558 for (i = 0; i < 10; i++) {
3559 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
3560 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3561 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3566 /* Check that reset completed successfully. */
3567 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3568 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3569 if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
3574 /* Make sure byte swapping is properly configured. */
3575 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
3576 if (val != 0x01020304) {
3577 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
3581 /* Just completed a reset, assume that firmware is running again. */
3582 sc->bce_fw_timed_out = 0;
3583 sc->bce_drv_cardiac_arrest = 0;
3585 /* Wait for the firmware to finish its initialization. */
3586 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3588 if_printf(&sc->arpcom.ac_if,
3589 "Firmware did not complete initialization!\n");
3596 bce_chipinit(struct bce_softc *sc)
3601 /* Make sure the interrupt is not active. */
3602 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
3603 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
3606 * Initialize DMA byte/word swapping, configure the number of DMA
3607 * channels and PCI clock compensation delay.
3609 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3610 BCE_DMA_CONFIG_DATA_WORD_SWAP |
3611 #if BYTE_ORDER == BIG_ENDIAN
3612 BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3614 BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3615 DMA_READ_CHANS << 12 |
3616 DMA_WRITE_CHANS << 16;
3618 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3620 if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3621 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3624 * This setting resolves a problem observed on certain Intel PCI
3625 * chipsets that cannot handle multiple outstanding DMA operations.
3626 * See errata E9_5706A1_65.
3628 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3629 BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3630 !(sc->bce_flags & BCE_PCIX_FLAG))
3631 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3633 REG_WR(sc, BCE_DMA_CONFIG, val);
3635 /* Enable the RX_V2P and Context state machines before access. */
3636 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3637 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3638 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3639 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3641 /* Initialize context mapping and zero out the quick contexts. */
3642 rc = bce_init_ctx(sc);
3646 /* Initialize the on-boards CPUs */
3649 /* Enable management frames (NC-SI) to flow to the MCP. */
3650 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3651 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) |
3652 BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3653 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3656 /* Prepare NVRAM for access. */
3657 rc = bce_init_nvram(sc);
3661 /* Set the kernel bypass block size */
3662 val = REG_RD(sc, BCE_MQ_CONFIG);
3663 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3664 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3666 /* Enable bins used on the 5709/5716. */
3667 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3668 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3669 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
3670 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
3671 val |= BCE_MQ_CONFIG_HALT_DIS;
3674 REG_WR(sc, BCE_MQ_CONFIG, val);
3676 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3677 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3678 REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3680 /* Set the page size and clear the RV2P processor stall bits. */
3681 val = (BCM_PAGE_BITS - 8) << 24;
3682 REG_WR(sc, BCE_RV2P_CONFIG, val);
3684 /* Configure page size. */
3685 val = REG_RD(sc, BCE_TBDR_CONFIG);
3686 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
3687 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3688 REG_WR(sc, BCE_TBDR_CONFIG, val);
3690 /* Set the perfect match control register to default. */
3691 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
3697 /****************************************************************************/
3698 /* Initialize the controller in preparation to send/receive traffic. */
3701 /* 0 for success, positive value for failure. */
3702 /****************************************************************************/
3704 bce_blockinit(struct bce_softc *sc)
3709 /* Load the hardware default MAC address. */
3710 bce_set_mac_addr(sc);
3712 /* Set the Ethernet backoff seed value */
3713 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
3714 sc->eaddr[3] + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
3715 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
3717 sc->last_status_idx = 0;
3718 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
3720 sc->pulse_check_status_idx = 0xffff;
3722 /* Set up link change interrupt generation. */
3723 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
3725 /* Program the physical address of the status block. */
3726 REG_WR(sc, BCE_HC_STATUS_ADDR_L, BCE_ADDR_LO(sc->status_block_paddr));
3727 REG_WR(sc, BCE_HC_STATUS_ADDR_H, BCE_ADDR_HI(sc->status_block_paddr));
3729 /* Program the physical address of the statistics block. */
3730 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
3731 BCE_ADDR_LO(sc->stats_block_paddr));
3732 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
3733 BCE_ADDR_HI(sc->stats_block_paddr));
3735 /* Program various host coalescing parameters. */
3736 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
3737 (sc->bce_tx_quick_cons_trip_int << 16) |
3738 sc->bce_tx_quick_cons_trip);
3739 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
3740 (sc->bce_rx_quick_cons_trip_int << 16) |
3741 sc->bce_rx_quick_cons_trip);
3742 REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
3743 (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
3744 REG_WR(sc, BCE_HC_TX_TICKS,
3745 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
3746 REG_WR(sc, BCE_HC_RX_TICKS,
3747 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
3748 REG_WR(sc, BCE_HC_COM_TICKS,
3749 (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
3750 REG_WR(sc, BCE_HC_CMD_TICKS,
3751 (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
3752 REG_WR(sc, BCE_HC_STATS_TICKS, (sc->bce_stats_ticks & 0xffff00));
3753 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
3755 val = BCE_HC_CONFIG_TX_TMR_MODE | BCE_HC_CONFIG_COLLECT_STATS;
3756 if (sc->bce_flags & BCE_ONESHOT_MSI_FLAG) {
3758 if_printf(&sc->arpcom.ac_if, "oneshot MSI\n");
3759 val |= BCE_HC_CONFIG_ONE_SHOT | BCE_HC_CONFIG_USE_INT_PARAM;
3761 REG_WR(sc, BCE_HC_CONFIG, val);
3763 /* Clear the internal statistics counters. */
3764 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
3766 /* Verify that bootcode is running. */
3767 reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);
3769 DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure),
3770 if_printf(&sc->arpcom.ac_if,
3771 "%s(%d): Simulating bootcode failure.\n",
3772 __FILE__, __LINE__);
3775 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
3776 BCE_DEV_INFO_SIGNATURE_MAGIC) {
3777 if_printf(&sc->arpcom.ac_if,
3778 "Bootcode not running! Found: 0x%08X, "
3779 "Expected: 08%08X\n",
3780 reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK,
3781 BCE_DEV_INFO_SIGNATURE_MAGIC);
3786 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3787 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3788 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3789 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3790 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3793 /* Allow bootcode to apply any additional fixes before enabling MAC. */
3794 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET);
3796 /* Enable link state change interrupt generation. */
3797 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3799 /* Enable the RXP. */
3800 bce_start_rxp_cpu(sc);
3802 /* Disable management frames (NC-SI) from flowing to the MCP. */
3803 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3804 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) &
3805 ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3806 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3809 /* Enable all remaining blocks in the MAC. */
3810 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3811 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3812 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3813 BCE_MISC_ENABLE_DEFAULT_XI);
3815 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
3817 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
3820 /* Save the current host coalescing block settings. */
3821 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
3827 /****************************************************************************/
3828 /* Encapsulate an mbuf cluster into the rx_bd chain. */
3830 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */
3831 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */
3835 /* 0 for success, positive value for failure. */
3836 /****************************************************************************/
3838 bce_newbuf_std(struct bce_softc *sc, uint16_t *prod, uint16_t *chain_prod,
3839 uint32_t *prod_bseq, int init)
3842 bus_dma_segment_t seg;
3846 uint16_t debug_chain_prod = *chain_prod;
3849 /* Make sure the inputs are valid. */
3850 DBRUNIF((*chain_prod > MAX_RX_BD(sc)),
3851 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3852 "RX producer out of range: 0x%04X > 0x%04X\n",
3854 *chain_prod, (uint16_t)MAX_RX_BD(sc)));
3856 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, "
3857 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3859 DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
3860 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3861 "Simulating mbuf allocation failure.\n",
3862 __FILE__, __LINE__);
3863 sc->mbuf_alloc_failed++;
3866 /* This is a new mbuf allocation. */
3867 m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
3870 DBRUNIF(1, sc->rx_mbuf_alloc++);
3872 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
3874 /* Map the mbuf cluster into device memory. */
3875 error = bus_dmamap_load_mbuf_segment(sc->rx_mbuf_tag,
3876 sc->rx_mbuf_tmpmap, m_new, &seg, 1, &nseg,
3881 if_printf(&sc->arpcom.ac_if,
3882 "Error mapping mbuf into RX chain!\n");
3884 DBRUNIF(1, sc->rx_mbuf_alloc--);
3888 if (sc->rx_mbuf_ptr[*chain_prod] != NULL) {
3889 bus_dmamap_unload(sc->rx_mbuf_tag,
3890 sc->rx_mbuf_map[*chain_prod]);
3893 map = sc->rx_mbuf_map[*chain_prod];
3894 sc->rx_mbuf_map[*chain_prod] = sc->rx_mbuf_tmpmap;
3895 sc->rx_mbuf_tmpmap = map;
3897 /* Watch for overflow. */
3898 DBRUNIF((sc->free_rx_bd > USABLE_RX_BD(sc)),
3899 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3900 "Too many free rx_bd (0x%04X > 0x%04X)!\n",
3901 __FILE__, __LINE__, sc->free_rx_bd,
3902 (uint16_t)USABLE_RX_BD(sc)));
3904 /* Update some debug statistic counters */
3905 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3906 sc->rx_low_watermark = sc->free_rx_bd);
3907 DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
3909 /* Save the mbuf and update our counter. */
3910 sc->rx_mbuf_ptr[*chain_prod] = m_new;
3911 sc->rx_mbuf_paddr[*chain_prod] = seg.ds_addr;
3914 bce_setup_rxdesc_std(sc, *chain_prod, prod_bseq);
3916 DBRUN(BCE_VERBOSE_RECV,
3917 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 1));
3919 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, "
3920 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3927 bce_setup_rxdesc_std(struct bce_softc *sc, uint16_t chain_prod, uint32_t *prod_bseq)
3933 paddr = sc->rx_mbuf_paddr[chain_prod];
3934 len = sc->rx_mbuf_ptr[chain_prod]->m_len;
3936 /* Setup the rx_bd for the first segment. */
3937 rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)];
3939 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(paddr));
3940 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(paddr));
3941 rxbd->rx_bd_len = htole32(len);
3942 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START);
3945 rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END);
3949 /****************************************************************************/
3950 /* Initialize the TX context memory. */
3954 /****************************************************************************/
3956 bce_init_tx_context(struct bce_softc *sc)
3960 /* Initialize the context ID for an L2 TX chain. */
3961 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3962 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3963 /* Set the CID type to support an L2 connection. */
3964 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3965 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val);
3966 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3967 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE_XI, val);
3969 /* Point the hardware to the first page in the chain. */
3970 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3971 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3972 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
3973 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3974 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3975 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
3977 /* Set the CID type to support an L2 connection. */
3978 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3979 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val);
3980 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3981 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val);
3983 /* Point the hardware to the first page in the chain. */
3984 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3985 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3986 BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
3987 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3988 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3989 BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
3994 /****************************************************************************/
3995 /* Allocate memory and initialize the TX data structures. */
3998 /* 0 for success, positive value for failure. */
3999 /****************************************************************************/
4001 bce_init_tx_chain(struct bce_softc *sc)
4006 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4008 /* Set the initial TX producer/consumer indices. */
4011 sc->tx_prod_bseq = 0;
4013 sc->max_tx_bd = USABLE_TX_BD(sc);
4014 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD(sc));
4015 DBRUNIF(1, sc->tx_full_count = 0);
4018 * The NetXtreme II supports a linked-list structre called
4019 * a Buffer Descriptor Chain (or BD chain). A BD chain
4020 * consists of a series of 1 or more chain pages, each of which
4021 * consists of a fixed number of BD entries.
4022 * The last BD entry on each page is a pointer to the next page
4023 * in the chain, and the last pointer in the BD chain
4024 * points back to the beginning of the chain.
4027 /* Set the TX next pointer chain entries. */
4028 for (i = 0; i < sc->tx_pages; i++) {
4031 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
4033 /* Check if we've reached the last page. */
4034 if (i == (sc->tx_pages - 1))
4039 txbd->tx_bd_haddr_hi =
4040 htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
4041 txbd->tx_bd_haddr_lo =
4042 htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
4044 bce_init_tx_context(sc);
4050 /****************************************************************************/
4051 /* Free memory and clear the TX data structures. */
4055 /****************************************************************************/
4057 bce_free_tx_chain(struct bce_softc *sc)
4061 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4063 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
4064 for (i = 0; i < TOTAL_TX_BD(sc); i++) {
4065 if (sc->tx_mbuf_ptr[i] != NULL) {
4066 bus_dmamap_unload(sc->tx_mbuf_tag, sc->tx_mbuf_map[i]);
4067 m_freem(sc->tx_mbuf_ptr[i]);
4068 sc->tx_mbuf_ptr[i] = NULL;
4069 DBRUNIF(1, sc->tx_mbuf_alloc--);
4073 /* Clear each TX chain page. */
4074 for (i = 0; i < sc->tx_pages; i++)
4075 bzero(sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
4078 /* Check if we lost any mbufs in the process. */
4079 DBRUNIF((sc->tx_mbuf_alloc),
4080 if_printf(&sc->arpcom.ac_if,
4081 "%s(%d): Memory leak! "
4082 "Lost %d mbufs from tx chain!\n",
4083 __FILE__, __LINE__, sc->tx_mbuf_alloc));
4085 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
4089 /****************************************************************************/
4090 /* Initialize the RX context memory. */
4094 /****************************************************************************/
4096 bce_init_rx_context(struct bce_softc *sc)
4100 /* Initialize the context ID for an L2 RX chain. */
4101 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
4102 BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
4105 * Set the level for generating pause frames
4106 * when the number of available rx_bd's gets
4107 * too low (the low watermark) and the level
4108 * when pause frames can be stopped (the high
4111 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4112 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4113 uint32_t lo_water, hi_water;
4115 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT;
4116 hi_water = USABLE_RX_BD(sc) / 4;
4118 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE;
4119 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE;
4123 else if (hi_water == 0)
4126 (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT);
4129 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val);
4131 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
4132 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4133 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4134 val = REG_RD(sc, BCE_MQ_MAP_L2_5);
4135 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
4138 /* Point the hardware to the first page in the chain. */
4139 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
4140 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val);
4141 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
4142 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val);
4146 /****************************************************************************/
4147 /* Allocate memory and initialize the RX data structures. */
4150 /* 0 for success, positive value for failure. */
4151 /****************************************************************************/
4153 bce_init_rx_chain(struct bce_softc *sc)
4157 uint16_t prod, chain_prod;
4160 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4162 /* Initialize the RX producer and consumer indices. */
4165 sc->rx_prod_bseq = 0;
4166 sc->free_rx_bd = USABLE_RX_BD(sc);
4167 sc->max_rx_bd = USABLE_RX_BD(sc);
4168 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD(sc));
4169 DBRUNIF(1, sc->rx_empty_count = 0);
4171 /* Initialize the RX next pointer chain entries. */
4172 for (i = 0; i < sc->rx_pages; i++) {
4175 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
4177 /* Check if we've reached the last page. */
4178 if (i == (sc->rx_pages - 1))
4183 /* Setup the chain page pointers. */
4184 rxbd->rx_bd_haddr_hi =
4185 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
4186 rxbd->rx_bd_haddr_lo =
4187 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
4190 /* Allocate mbuf clusters for the rx_bd chain. */
4191 prod = prod_bseq = 0;
4192 while (prod < TOTAL_RX_BD(sc)) {
4193 chain_prod = RX_CHAIN_IDX(sc, prod);
4194 if (bce_newbuf_std(sc, &prod, &chain_prod, &prod_bseq, 1)) {
4195 if_printf(&sc->arpcom.ac_if,
4196 "Error filling RX chain: rx_bd[0x%04X]!\n",
4201 prod = NEXT_RX_BD(prod);
4204 /* Save the RX chain producer index. */
4206 sc->rx_prod_bseq = prod_bseq;
4208 /* Tell the chip about the waiting rx_bd's. */
4209 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
4211 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
4214 bce_init_rx_context(sc);
4220 /****************************************************************************/
4221 /* Free memory and clear the RX data structures. */
4225 /****************************************************************************/
4227 bce_free_rx_chain(struct bce_softc *sc)
4231 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4233 /* Free any mbufs still in the RX mbuf chain. */
4234 for (i = 0; i < TOTAL_RX_BD(sc); i++) {
4235 if (sc->rx_mbuf_ptr[i] != NULL) {
4236 bus_dmamap_unload(sc->rx_mbuf_tag, sc->rx_mbuf_map[i]);
4237 m_freem(sc->rx_mbuf_ptr[i]);
4238 sc->rx_mbuf_ptr[i] = NULL;
4239 DBRUNIF(1, sc->rx_mbuf_alloc--);
4243 /* Clear each RX chain page. */
4244 for (i = 0; i < sc->rx_pages; i++)
4245 bzero(sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ);
4247 /* Check if we lost any mbufs in the process. */
4248 DBRUNIF((sc->rx_mbuf_alloc),
4249 if_printf(&sc->arpcom.ac_if,
4250 "%s(%d): Memory leak! "
4251 "Lost %d mbufs from rx chain!\n",
4252 __FILE__, __LINE__, sc->rx_mbuf_alloc));
4254 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
4258 /****************************************************************************/
4259 /* Set media options. */
4262 /* 0 for success, positive value for failure. */
4263 /****************************************************************************/
4265 bce_ifmedia_upd(struct ifnet *ifp)
4267 struct bce_softc *sc = ifp->if_softc;
4268 struct mii_data *mii = device_get_softc(sc->bce_miibus);
4272 * 'mii' will be NULL, when this function is called on following
4273 * code path: bce_attach() -> bce_mgmt_init()
4276 /* Make sure the MII bus has been enumerated. */
4278 if (mii->mii_instance) {
4279 struct mii_softc *miisc;
4281 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
4282 mii_phy_reset(miisc);
4284 error = mii_mediachg(mii);
4290 /****************************************************************************/
4291 /* Reports current media status. */
4295 /****************************************************************************/
4297 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4299 struct bce_softc *sc = ifp->if_softc;
4300 struct mii_data *mii = device_get_softc(sc->bce_miibus);
4303 ifmr->ifm_active = mii->mii_media_active;
4304 ifmr->ifm_status = mii->mii_media_status;
4308 /****************************************************************************/
4309 /* Handles PHY generated interrupt events. */
4313 /****************************************************************************/
4315 bce_phy_intr(struct bce_softc *sc)
4317 uint32_t new_link_state, old_link_state;
4318 struct ifnet *ifp = &sc->arpcom.ac_if;
4320 ASSERT_SERIALIZED(ifp->if_serializer);
4322 new_link_state = sc->status_block->status_attn_bits &
4323 STATUS_ATTN_BITS_LINK_STATE;
4324 old_link_state = sc->status_block->status_attn_bits_ack &
4325 STATUS_ATTN_BITS_LINK_STATE;
4327 /* Handle any changes if the link state has changed. */
4328 if (new_link_state != old_link_state) { /* XXX redundant? */
4329 DBRUN(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
4331 /* Update the status_attn_bits_ack field in the status block. */
4332 if (new_link_state) {
4333 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
4334 STATUS_ATTN_BITS_LINK_STATE);
4336 if_printf(ifp, "Link is now UP.\n");
4338 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
4339 STATUS_ATTN_BITS_LINK_STATE);
4341 if_printf(ifp, "Link is now DOWN.\n");
4345 * Assume link is down and allow tick routine to
4346 * update the state based on the actual media state.
4349 callout_stop(&sc->bce_tick_callout);
4350 bce_tick_serialized(sc);
4353 /* Acknowledge the link change interrupt. */
4354 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
4358 /****************************************************************************/
4359 /* Reads the receive consumer value from the status block (skipping over */
4360 /* chain page pointer if necessary). */
4364 /****************************************************************************/
4365 static __inline uint16_t
4366 bce_get_hw_rx_cons(struct bce_softc *sc)
4368 uint16_t hw_cons = sc->status_block->status_rx_quick_consumer_index0;
4370 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
4376 /****************************************************************************/
4377 /* Handles received frame interrupt events. */
4381 /****************************************************************************/
4383 bce_rx_intr(struct bce_softc *sc, int count, uint16_t hw_cons)
4385 struct ifnet *ifp = &sc->arpcom.ac_if;
4386 uint16_t sw_cons, sw_chain_cons, sw_prod, sw_chain_prod;
4387 uint32_t sw_prod_bseq;
4389 ASSERT_SERIALIZED(ifp->if_serializer);
4391 /* Get working copies of the driver's view of the RX indices. */
4392 sw_cons = sc->rx_cons;
4393 sw_prod = sc->rx_prod;
4394 sw_prod_bseq = sc->rx_prod_bseq;
4396 /* Scan through the receive chain as long as there is work to do. */
4397 while (sw_cons != hw_cons) {
4398 struct mbuf *m = NULL;
4399 struct l2_fhdr *l2fhdr = NULL;
4402 uint32_t status = 0;
4404 #ifdef DEVICE_POLLING
4405 if (count >= 0 && count-- == 0)
4410 * Convert the producer/consumer indices
4411 * to an actual rx_bd index.
4413 sw_chain_cons = RX_CHAIN_IDX(sc, sw_cons);
4414 sw_chain_prod = RX_CHAIN_IDX(sc, sw_prod);
4416 /* Get the used rx_bd. */
4417 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)]
4418 [RX_IDX(sw_chain_cons)];
4421 /* The mbuf is stored with the last rx_bd entry of a packet. */
4422 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) {
4423 if (sw_chain_cons != sw_chain_prod) {
4424 if_printf(ifp, "RX cons(%d) != prod(%d), "
4425 "drop!\n", sw_chain_cons,
4429 bce_setup_rxdesc_std(sc, sw_chain_cons,
4432 goto bce_rx_int_next_rx;
4435 /* Unmap the mbuf from DMA space. */
4436 bus_dmamap_sync(sc->rx_mbuf_tag,
4437 sc->rx_mbuf_map[sw_chain_cons],
4438 BUS_DMASYNC_POSTREAD);
4440 /* Save the mbuf from the driver's chain. */
4441 m = sc->rx_mbuf_ptr[sw_chain_cons];
4444 * Frames received on the NetXteme II are prepended
4445 * with an l2_fhdr structure which provides status
4446 * information about the received frame (including
4447 * VLAN tags and checksum info). The frames are also
4448 * automatically adjusted to align the IP header
4449 * (i.e. two null bytes are inserted before the
4450 * Ethernet header). As a result the data DMA'd by
4451 * the controller into the mbuf is as follows:
4453 * +---------+-----+---------------------+-----+
4454 * | l2_fhdr | pad | packet data | FCS |
4455 * +---------+-----+---------------------+-----+
4457 * The l2_fhdr needs to be checked and skipped and the
4458 * FCS needs to be stripped before sending the packet
4461 l2fhdr = mtod(m, struct l2_fhdr *);
4463 len = l2fhdr->l2_fhdr_pkt_len;
4464 status = l2fhdr->l2_fhdr_status;
4466 len -= ETHER_CRC_LEN;
4468 /* Check the received frame for errors. */
4469 if (status & (L2_FHDR_ERRORS_BAD_CRC |
4470 L2_FHDR_ERRORS_PHY_DECODE |
4471 L2_FHDR_ERRORS_ALIGNMENT |
4472 L2_FHDR_ERRORS_TOO_SHORT |
4473 L2_FHDR_ERRORS_GIANT_FRAME)) {
4476 /* Reuse the mbuf for a new frame. */
4477 bce_setup_rxdesc_std(sc, sw_chain_prod,
4480 goto bce_rx_int_next_rx;
4484 * Get a new mbuf for the rx_bd. If no new
4485 * mbufs are available then reuse the current mbuf,
4486 * log an ierror on the interface, and generate
4487 * an error in the system log.
4489 if (bce_newbuf_std(sc, &sw_prod, &sw_chain_prod,
4490 &sw_prod_bseq, 0)) {
4493 /* Try and reuse the exisitng mbuf. */
4494 bce_setup_rxdesc_std(sc, sw_chain_prod,
4497 goto bce_rx_int_next_rx;
4501 * Skip over the l2_fhdr when passing
4502 * the data up the stack.
4504 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN);
4506 m->m_pkthdr.len = m->m_len = len;
4507 m->m_pkthdr.rcvif = ifp;
4509 /* Validate the checksum if offload enabled. */
4510 if (ifp->if_capenable & IFCAP_RXCSUM) {
4511 /* Check for an IP datagram. */
4512 if (status & L2_FHDR_STATUS_IP_DATAGRAM) {
4513 m->m_pkthdr.csum_flags |=
4516 /* Check if the IP checksum is valid. */
4517 if ((l2fhdr->l2_fhdr_ip_xsum ^
4519 m->m_pkthdr.csum_flags |=
4524 /* Check for a valid TCP/UDP frame. */
4525 if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
4526 L2_FHDR_STATUS_UDP_DATAGRAM)) {
4528 /* Check for a good TCP/UDP checksum. */
4530 (L2_FHDR_ERRORS_TCP_XSUM |
4531 L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
4532 m->m_pkthdr.csum_data =
4533 l2fhdr->l2_fhdr_tcp_udp_xsum;
4534 m->m_pkthdr.csum_flags |=
4543 sw_prod = NEXT_RX_BD(sw_prod);
4546 sw_cons = NEXT_RX_BD(sw_cons);
4548 /* If we have a packet, pass it up the stack */
4550 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
4551 m->m_flags |= M_VLANTAG;
4552 m->m_pkthdr.ether_vlantag =
4553 l2fhdr->l2_fhdr_vlan_tag;
4555 ifp->if_input(ifp, m);
4559 sc->rx_cons = sw_cons;
4560 sc->rx_prod = sw_prod;
4561 sc->rx_prod_bseq = sw_prod_bseq;
4563 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
4565 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
4570 /****************************************************************************/
4571 /* Reads the transmit consumer value from the status block (skipping over */
4572 /* chain page pointer if necessary). */
4576 /****************************************************************************/
4577 static __inline uint16_t
4578 bce_get_hw_tx_cons(struct bce_softc *sc)
4580 uint16_t hw_cons = sc->status_block->status_tx_quick_consumer_index0;
4582 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
4588 /****************************************************************************/
4589 /* Handles transmit completion interrupt events. */
4593 /****************************************************************************/
4595 bce_tx_intr(struct bce_softc *sc, uint16_t hw_tx_cons)
4597 struct ifnet *ifp = &sc->arpcom.ac_if;
4598 uint16_t sw_tx_cons, sw_tx_chain_cons;
4600 ASSERT_SERIALIZED(ifp->if_serializer);
4602 /* Get the hardware's view of the TX consumer index. */
4603 sw_tx_cons = sc->tx_cons;
4605 /* Cycle through any completed TX chain page entries. */
4606 while (sw_tx_cons != hw_tx_cons) {
4607 sw_tx_chain_cons = TX_CHAIN_IDX(sc, sw_tx_cons);
4610 * Free the associated mbuf. Remember
4611 * that only the last tx_bd of a packet
4612 * has an mbuf pointer and DMA map.
4614 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
4615 /* Unmap the mbuf. */
4616 bus_dmamap_unload(sc->tx_mbuf_tag,
4617 sc->tx_mbuf_map[sw_tx_chain_cons]);
4619 /* Free the mbuf. */
4620 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
4621 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
4627 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
4630 if (sc->used_tx_bd == 0) {
4631 /* Clear the TX timeout timer. */
4635 /* Clear the tx hardware queue full flag. */
4636 if (sc->max_tx_bd - sc->used_tx_bd >= BCE_TX_SPARE_SPACE)
4637 ifp->if_flags &= ~IFF_OACTIVE;
4638 sc->tx_cons = sw_tx_cons;
4642 /****************************************************************************/
4643 /* Disables interrupt generation. */
4647 /****************************************************************************/
4649 bce_disable_intr(struct bce_softc *sc)
4651 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4652 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
4653 lwkt_serialize_handler_disable(sc->arpcom.ac_if.if_serializer);
4657 /****************************************************************************/
4658 /* Enables interrupt generation. */
4662 /****************************************************************************/
4664 bce_enable_intr(struct bce_softc *sc)
4666 lwkt_serialize_handler_enable(sc->arpcom.ac_if.if_serializer);
4668 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4669 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
4670 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
4671 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4672 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4674 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
4678 /****************************************************************************/
4679 /* Reenables interrupt generation during interrupt handling. */
4683 /****************************************************************************/
4685 bce_reenable_intr(struct bce_softc *sc)
4687 if (sc->bce_irq_type == PCI_INTR_TYPE_LEGACY) {
4688 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4689 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
4690 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
4692 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4693 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4696 /****************************************************************************/
4697 /* Handles controller initialization. */
4701 /****************************************************************************/
4705 struct bce_softc *sc = xsc;
4706 struct ifnet *ifp = &sc->arpcom.ac_if;
4710 ASSERT_SERIALIZED(ifp->if_serializer);
4712 /* Check if the driver is still running and bail out if it is. */
4713 if (ifp->if_flags & IFF_RUNNING)
4718 error = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
4720 if_printf(ifp, "Controller reset failed!\n");
4724 error = bce_chipinit(sc);
4726 if_printf(ifp, "Controller initialization failed!\n");
4730 error = bce_blockinit(sc);
4732 if_printf(ifp, "Block initialization failed!\n");
4736 /* Load our MAC address. */
4737 bcopy(IF_LLADDR(ifp), sc->eaddr, ETHER_ADDR_LEN);
4738 bce_set_mac_addr(sc);
4740 /* Calculate and program the Ethernet MTU size. */
4741 ether_mtu = ETHER_HDR_LEN + EVL_ENCAPLEN + ifp->if_mtu + ETHER_CRC_LEN;
4743 DBPRINT(sc, BCE_INFO, "%s(): setting mtu = %d\n", __func__, ether_mtu);
4746 * Program the mtu, enabling jumbo frame
4747 * support if necessary. Also set the mbuf
4748 * allocation count for RX frames.
4750 if (ether_mtu > ETHER_MAX_LEN + EVL_ENCAPLEN) {
4752 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
4753 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
4754 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
4755 sc->mbuf_alloc_size = MJUM9BYTES;
4757 panic("jumbo buffer is not supported yet");
4760 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
4761 sc->mbuf_alloc_size = MCLBYTES;
4764 /* Calculate the RX Ethernet frame size for rx_bd's. */
4765 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8;
4767 DBPRINT(sc, BCE_INFO,
4768 "%s(): mclbytes = %d, mbuf_alloc_size = %d, "
4769 "max_frame_size = %d\n",
4770 __func__, (int)MCLBYTES, sc->mbuf_alloc_size,
4771 sc->max_frame_size);
4773 /* Program appropriate promiscuous/multicast filtering. */
4774 bce_set_rx_mode(sc);
4776 /* Init RX buffer descriptor chain. */
4777 bce_init_rx_chain(sc); /* XXX return value */
4779 /* Init TX buffer descriptor chain. */
4780 bce_init_tx_chain(sc); /* XXX return value */
4782 #ifdef DEVICE_POLLING
4783 /* Disable interrupts if we are polling. */
4784 if (ifp->if_flags & IFF_POLLING) {
4785 bce_disable_intr(sc);
4787 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4788 (1 << 16) | sc->bce_rx_quick_cons_trip);
4789 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4790 (1 << 16) | sc->bce_tx_quick_cons_trip);
4793 /* Enable host interrupts. */
4794 bce_enable_intr(sc);
4796 bce_ifmedia_upd(ifp);
4798 ifp->if_flags |= IFF_RUNNING;
4799 ifp->if_flags &= ~IFF_OACTIVE;
4801 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
4808 /****************************************************************************/
4809 /* Initialize the controller just enough so that any management firmware */
4810 /* running on the device will continue to operate corectly. */
4814 /****************************************************************************/
4816 bce_mgmt_init(struct bce_softc *sc)
4818 struct ifnet *ifp = &sc->arpcom.ac_if;
4820 /* Bail out if management firmware is not running. */
4821 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
4824 /* Enable all critical blocks in the MAC. */
4825 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4826 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4827 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
4828 BCE_MISC_ENABLE_DEFAULT_XI);
4830 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
4832 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
4835 bce_ifmedia_upd(ifp);
4839 /****************************************************************************/
4840 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
4841 /* memory visible to the controller. */
4844 /* 0 for success, positive value for failure. */
4845 /****************************************************************************/
4847 bce_encap(struct bce_softc *sc, struct mbuf **m_head)
4849 bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
4850 bus_dmamap_t map, tmp_map;
4851 struct mbuf *m0 = *m_head;
4852 struct tx_bd *txbd = NULL;
4853 uint16_t vlan_tag = 0, flags = 0, mss = 0;
4854 uint16_t chain_prod, chain_prod_start, prod;
4856 int i, error, maxsegs, nsegs;
4858 /* Transfer any checksum offload flags to the bd. */
4859 if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
4860 error = bce_tso_setup(sc, m_head, &flags, &mss);
4864 } else if (m0->m_pkthdr.csum_flags & BCE_CSUM_FEATURES) {
4865 if (m0->m_pkthdr.csum_flags & CSUM_IP)
4866 flags |= TX_BD_FLAGS_IP_CKSUM;
4867 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
4868 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4871 /* Transfer any VLAN tags to the bd. */
4872 if (m0->m_flags & M_VLANTAG) {
4873 flags |= TX_BD_FLAGS_VLAN_TAG;
4874 vlan_tag = m0->m_pkthdr.ether_vlantag;
4878 chain_prod_start = chain_prod = TX_CHAIN_IDX(sc, prod);
4880 /* Map the mbuf into DMAable memory. */
4881 map = sc->tx_mbuf_map[chain_prod_start];
4883 maxsegs = sc->max_tx_bd - sc->used_tx_bd;
4884 KASSERT(maxsegs >= BCE_TX_SPARE_SPACE,
4885 ("not enough segments %d", maxsegs));
4886 if (maxsegs > BCE_MAX_SEGMENTS)
4887 maxsegs = BCE_MAX_SEGMENTS;
4889 /* Map the mbuf into our DMA address space. */
4890 error = bus_dmamap_load_mbuf_defrag(sc->tx_mbuf_tag, map, m_head,
4891 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
4894 bus_dmamap_sync(sc->tx_mbuf_tag, map, BUS_DMASYNC_PREWRITE);
4899 /* prod points to an empty tx_bd at this point. */
4900 prod_bseq = sc->tx_prod_bseq;
4903 * Cycle through each mbuf segment that makes up
4904 * the outgoing frame, gathering the mapping info
4905 * for that segment and creating a tx_bd to for
4908 for (i = 0; i < nsegs; i++) {
4909 chain_prod = TX_CHAIN_IDX(sc, prod);
4910 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)];
4912 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr));
4913 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr));
4914 txbd->tx_bd_mss_nbytes = htole32(mss << 16) |
4915 htole16(segs[i].ds_len);
4916 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
4917 txbd->tx_bd_flags = htole16(flags);
4919 prod_bseq += segs[i].ds_len;
4921 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
4922 prod = NEXT_TX_BD(prod);
4925 /* Set the END flag on the last TX buffer descriptor. */
4926 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
4929 * Ensure that the mbuf pointer for this transmission
4930 * is placed at the array index of the last
4931 * descriptor in this chain. This is done
4932 * because a single map is used for all
4933 * segments of the mbuf and we don't want to
4934 * unload the map before all of the segments
4937 sc->tx_mbuf_ptr[chain_prod] = m0;
4939 tmp_map = sc->tx_mbuf_map[chain_prod];
4940 sc->tx_mbuf_map[chain_prod] = map;
4941 sc->tx_mbuf_map[chain_prod_start] = tmp_map;
4943 sc->used_tx_bd += nsegs;
4945 /* prod points to the next free tx_bd at this point. */
4947 sc->tx_prod_bseq = prod_bseq;
4957 /****************************************************************************/
4958 /* Main transmit routine when called from another routine with a lock. */
4962 /****************************************************************************/
4964 bce_start(struct ifnet *ifp)
4966 struct bce_softc *sc = ifp->if_softc;
4969 ASSERT_SERIALIZED(ifp->if_serializer);
4971 /* If there's no link or the transmit queue is empty then just exit. */
4972 if (!sc->bce_link) {
4973 ifq_purge(&ifp->if_snd);
4977 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
4981 struct mbuf *m_head;
4984 * We keep BCE_TX_SPARE_SPACE entries, so bce_encap() is
4987 if (sc->max_tx_bd - sc->used_tx_bd < BCE_TX_SPARE_SPACE) {
4988 ifp->if_flags |= IFF_OACTIVE;
4992 /* Check for any frames to send. */
4993 m_head = ifq_dequeue(&ifp->if_snd, NULL);
4998 * Pack the data into the transmit ring. If we
4999 * don't have room, place the mbuf back at the
5000 * head of the queue and set the OACTIVE flag
5001 * to wait for the NIC to drain the chain.
5003 if (bce_encap(sc, &m_head)) {
5005 if (sc->used_tx_bd == 0) {
5008 ifp->if_flags |= IFF_OACTIVE;
5015 /* Send a copy of the frame to any BPF listeners. */
5016 ETHER_BPF_MTAP(ifp, m_head);
5020 /* no packets were dequeued */
5024 REG_WR(sc, BCE_MQ_COMMAND,
5025 REG_RD(sc, BCE_MQ_COMMAND) | BCE_MQ_COMMAND_NO_MAP_ERROR);
5027 /* Start the transmit. */
5028 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BIDX,
5030 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BSEQ,
5033 /* Set the tx timeout. */
5034 ifp->if_timer = BCE_TX_TIMEOUT;
5038 /****************************************************************************/
5039 /* Handles any IOCTL calls from the operating system. */
5042 /* 0 for success, positive value for failure. */
5043 /****************************************************************************/
5045 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
5047 struct bce_softc *sc = ifp->if_softc;
5048 struct ifreq *ifr = (struct ifreq *)data;
5049 struct mii_data *mii;
5050 int mask, error = 0;
5052 ASSERT_SERIALIZED(ifp->if_serializer);
5056 /* Check that the MTU setting is supported. */
5057 if (ifr->ifr_mtu < BCE_MIN_MTU ||
5059 ifr->ifr_mtu > BCE_MAX_JUMBO_MTU
5061 ifr->ifr_mtu > ETHERMTU
5068 DBPRINT(sc, BCE_INFO, "Setting new MTU of %d\n", ifr->ifr_mtu);
5070 ifp->if_mtu = ifr->ifr_mtu;
5071 ifp->if_flags &= ~IFF_RUNNING; /* Force reinitialize */
5076 if (ifp->if_flags & IFF_UP) {
5077 if (ifp->if_flags & IFF_RUNNING) {
5078 mask = ifp->if_flags ^ sc->bce_if_flags;
5080 if (mask & (IFF_PROMISC | IFF_ALLMULTI))
5081 bce_set_rx_mode(sc);
5085 } else if (ifp->if_flags & IFF_RUNNING) {
5088 /* If MFW is running, restart the controller a bit. */
5089 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5090 bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
5095 sc->bce_if_flags = ifp->if_flags;
5100 if (ifp->if_flags & IFF_RUNNING)
5101 bce_set_rx_mode(sc);
5106 DBPRINT(sc, BCE_VERBOSE, "bce_phy_flags = 0x%08X\n",
5108 DBPRINT(sc, BCE_VERBOSE, "Copper media set/get\n");
5110 mii = device_get_softc(sc->bce_miibus);
5111 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
5115 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
5116 DBPRINT(sc, BCE_INFO, "Received SIOCSIFCAP = 0x%08X\n",
5119 if (mask & IFCAP_HWCSUM) {
5120 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
5121 if (ifp->if_capenable & IFCAP_TXCSUM)
5122 ifp->if_hwassist |= BCE_CSUM_FEATURES;
5124 ifp->if_hwassist &= ~BCE_CSUM_FEATURES;
5126 if (mask & IFCAP_TSO) {
5127 ifp->if_capenable ^= IFCAP_TSO;
5128 if (ifp->if_capenable & IFCAP_TSO)
5129 ifp->if_hwassist |= CSUM_TSO;
5131 ifp->if_hwassist &= ~CSUM_TSO;
5136 error = ether_ioctl(ifp, command, data);
5143 /****************************************************************************/
5144 /* Transmit timeout handler. */
5148 /****************************************************************************/
5150 bce_watchdog(struct ifnet *ifp)
5152 struct bce_softc *sc = ifp->if_softc;
5154 ASSERT_SERIALIZED(ifp->if_serializer);
5156 DBRUN(BCE_VERBOSE_SEND,
5157 bce_dump_driver_state(sc);
5158 bce_dump_status_block(sc));
5161 * If we are in this routine because of pause frames, then
5162 * don't reset the hardware.
5164 if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED)
5167 if_printf(ifp, "Watchdog timeout occurred, resetting!\n");
5169 /* DBRUN(BCE_FATAL, bce_breakpoint(sc)); */
5171 ifp->if_flags &= ~IFF_RUNNING; /* Force reinitialize */
5176 if (!ifq_is_empty(&ifp->if_snd))
5181 #ifdef DEVICE_POLLING
5184 bce_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
5186 struct bce_softc *sc = ifp->if_softc;
5187 struct status_block *sblk = sc->status_block;
5188 uint16_t hw_tx_cons, hw_rx_cons;
5190 ASSERT_SERIALIZED(ifp->if_serializer);
5194 bce_disable_intr(sc);
5196 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5197 (1 << 16) | sc->bce_rx_quick_cons_trip);
5198 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5199 (1 << 16) | sc->bce_tx_quick_cons_trip);
5201 case POLL_DEREGISTER:
5202 bce_enable_intr(sc);
5204 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5205 (sc->bce_tx_quick_cons_trip_int << 16) |
5206 sc->bce_tx_quick_cons_trip);
5207 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5208 (sc->bce_rx_quick_cons_trip_int << 16) |
5209 sc->bce_rx_quick_cons_trip);
5216 * Save the status block index value for use when enabling
5219 sc->last_status_idx = sblk->status_idx;
5221 /* Make sure status index is extracted before rx/tx cons */
5224 if (cmd == POLL_AND_CHECK_STATUS) {
5225 uint32_t status_attn_bits;
5227 status_attn_bits = sblk->status_attn_bits;
5229 /* Was it a link change interrupt? */
5230 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5231 (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
5234 /* Clear any transient status updates during link state change. */
5235 REG_WR(sc, BCE_HC_COMMAND,
5236 sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5237 REG_RD(sc, BCE_HC_COMMAND);
5240 * If any other attention is asserted then
5241 * the chip is toast.
5243 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5244 (sblk->status_attn_bits_ack &
5245 ~STATUS_ATTN_BITS_LINK_STATE)) {
5246 if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5247 sblk->status_attn_bits);
5253 hw_rx_cons = bce_get_hw_rx_cons(sc);
5254 hw_tx_cons = bce_get_hw_tx_cons(sc);
5256 /* Check for any completed RX frames. */
5257 if (hw_rx_cons != sc->rx_cons)
5258 bce_rx_intr(sc, count, hw_rx_cons);
5260 /* Check for any completed TX frames. */
5261 if (hw_tx_cons != sc->tx_cons)
5262 bce_tx_intr(sc, hw_tx_cons);
5264 /* Check for new frames to transmit. */
5265 if (!ifq_is_empty(&ifp->if_snd))
5269 #endif /* DEVICE_POLLING */
5273 * Interrupt handler.
5275 /****************************************************************************/
5276 /* Main interrupt entry point. Verifies that the controller generated the */
5277 /* interrupt and then calls a separate routine for handle the various */
5278 /* interrupt causes (PHY, TX, RX). */
5281 /* 0 for success, positive value for failure. */
5282 /****************************************************************************/
5284 bce_intr(struct bce_softc *sc)
5286 struct ifnet *ifp = &sc->arpcom.ac_if;
5287 struct status_block *sblk;
5288 uint16_t hw_rx_cons, hw_tx_cons;
5289 uint32_t status_attn_bits;
5291 ASSERT_SERIALIZED(ifp->if_serializer);
5293 sblk = sc->status_block;
5296 * Save the status block index value for use during
5297 * the next interrupt.
5299 sc->last_status_idx = sblk->status_idx;
5301 /* Make sure status index is extracted before rx/tx cons */
5304 /* Check if the hardware has finished any work. */
5305 hw_rx_cons = bce_get_hw_rx_cons(sc);
5306 hw_tx_cons = bce_get_hw_tx_cons(sc);
5308 status_attn_bits = sblk->status_attn_bits;
5310 /* Was it a link change interrupt? */
5311 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5312 (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) {
5316 * Clear any transient status updates during link state
5319 REG_WR(sc, BCE_HC_COMMAND,
5320 sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5321 REG_RD(sc, BCE_HC_COMMAND);
5325 * If any other attention is asserted then
5326 * the chip is toast.
5328 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5329 (sblk->status_attn_bits_ack & ~STATUS_ATTN_BITS_LINK_STATE)) {
5330 if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5331 sblk->status_attn_bits);
5336 /* Check for any completed RX frames. */
5337 if (hw_rx_cons != sc->rx_cons)
5338 bce_rx_intr(sc, -1, hw_rx_cons);
5340 /* Check for any completed TX frames. */
5341 if (hw_tx_cons != sc->tx_cons)
5342 bce_tx_intr(sc, hw_tx_cons);
5344 /* Re-enable interrupts. */
5345 bce_reenable_intr(sc);
5347 if (sc->bce_coalchg_mask)
5348 bce_coal_change(sc);
5350 /* Handle any frames that arrived while handling the interrupt. */
5351 if (!ifq_is_empty(&ifp->if_snd))
5356 bce_intr_legacy(void *xsc)
5358 struct bce_softc *sc = xsc;
5359 struct status_block *sblk;
5361 sblk = sc->status_block;
5364 * If the hardware status block index matches the last value
5365 * read by the driver and we haven't asserted our interrupt
5366 * then there's nothing to do.
5368 if (sblk->status_idx == sc->last_status_idx &&
5369 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
5370 BCE_PCICFG_MISC_STATUS_INTA_VALUE))
5373 /* Ack the interrupt and stop others from occuring. */
5374 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5375 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
5376 BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5379 * Read back to deassert IRQ immediately to avoid too
5380 * many spurious interrupts.
5382 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
5388 bce_intr_msi(void *xsc)
5390 struct bce_softc *sc = xsc;
5392 /* Ack the interrupt and stop others from occuring. */
5393 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5394 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
5395 BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5401 bce_intr_msi_oneshot(void *xsc)
5407 /****************************************************************************/
5408 /* Programs the various packet receive modes (broadcast and multicast). */
5412 /****************************************************************************/
5414 bce_set_rx_mode(struct bce_softc *sc)
5416 struct ifnet *ifp = &sc->arpcom.ac_if;
5417 struct ifmultiaddr *ifma;
5418 uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
5419 uint32_t rx_mode, sort_mode;
5422 ASSERT_SERIALIZED(ifp->if_serializer);
5424 /* Initialize receive mode default settings. */
5425 rx_mode = sc->rx_mode &
5426 ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
5427 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
5428 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
5431 * ASF/IPMI/UMP firmware requires that VLAN tag stripping
5434 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
5435 !(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
5436 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
5439 * Check for promiscuous, all multicast, or selected
5440 * multicast address filtering.
5442 if (ifp->if_flags & IFF_PROMISC) {
5443 DBPRINT(sc, BCE_INFO, "Enabling promiscuous mode.\n");
5445 /* Enable promiscuous mode. */
5446 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
5447 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
5448 } else if (ifp->if_flags & IFF_ALLMULTI) {
5449 DBPRINT(sc, BCE_INFO, "Enabling all multicast mode.\n");
5451 /* Enable all multicast addresses. */
5452 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5453 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5456 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
5458 /* Accept one or more multicast(s). */
5459 DBPRINT(sc, BCE_INFO, "Enabling selective multicast mode.\n");
5461 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
5462 if (ifma->ifma_addr->sa_family != AF_LINK)
5465 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
5466 ETHER_ADDR_LEN) & 0xFF;
5467 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
5470 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5471 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5474 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
5477 /* Only make changes if the recive mode has actually changed. */
5478 if (rx_mode != sc->rx_mode) {
5479 DBPRINT(sc, BCE_VERBOSE, "Enabling new receive mode: 0x%08X\n",
5482 sc->rx_mode = rx_mode;
5483 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
5486 /* Disable and clear the exisitng sort before enabling a new sort. */
5487 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
5488 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
5489 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
5493 /****************************************************************************/
5494 /* Called periodically to updates statistics from the controllers */
5495 /* statistics block. */
5499 /****************************************************************************/
5501 bce_stats_update(struct bce_softc *sc)
5503 struct ifnet *ifp = &sc->arpcom.ac_if;
5504 struct statistics_block *stats = sc->stats_block;
5506 DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5508 ASSERT_SERIALIZED(ifp->if_serializer);
5511 * Certain controllers don't report carrier sense errors correctly.
5512 * See errata E11_5708CA0_1165.
5514 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
5515 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) {
5517 (u_long)stats->stat_Dot3StatsCarrierSenseErrors;
5521 * Update the sysctl statistics from the hardware statistics.
5523 sc->stat_IfHCInOctets =
5524 ((uint64_t)stats->stat_IfHCInOctets_hi << 32) +
5525 (uint64_t)stats->stat_IfHCInOctets_lo;
5527 sc->stat_IfHCInBadOctets =
5528 ((uint64_t)stats->stat_IfHCInBadOctets_hi << 32) +
5529 (uint64_t)stats->stat_IfHCInBadOctets_lo;
5531 sc->stat_IfHCOutOctets =
5532 ((uint64_t)stats->stat_IfHCOutOctets_hi << 32) +
5533 (uint64_t)stats->stat_IfHCOutOctets_lo;
5535 sc->stat_IfHCOutBadOctets =
5536 ((uint64_t)stats->stat_IfHCOutBadOctets_hi << 32) +
5537 (uint64_t)stats->stat_IfHCOutBadOctets_lo;
5539 sc->stat_IfHCInUcastPkts =
5540 ((uint64_t)stats->stat_IfHCInUcastPkts_hi << 32) +
5541 (uint64_t)stats->stat_IfHCInUcastPkts_lo;
5543 sc->stat_IfHCInMulticastPkts =
5544 ((uint64_t)stats->stat_IfHCInMulticastPkts_hi << 32) +
5545 (uint64_t)stats->stat_IfHCInMulticastPkts_lo;
5547 sc->stat_IfHCInBroadcastPkts =
5548 ((uint64_t)stats->stat_IfHCInBroadcastPkts_hi << 32) +
5549 (uint64_t)stats->stat_IfHCInBroadcastPkts_lo;
5551 sc->stat_IfHCOutUcastPkts =
5552 ((uint64_t)stats->stat_IfHCOutUcastPkts_hi << 32) +
5553 (uint64_t)stats->stat_IfHCOutUcastPkts_lo;
5555 sc->stat_IfHCOutMulticastPkts =
5556 ((uint64_t)stats->stat_IfHCOutMulticastPkts_hi << 32) +
5557 (uint64_t)stats->stat_IfHCOutMulticastPkts_lo;
5559 sc->stat_IfHCOutBroadcastPkts =
5560 ((uint64_t)stats->stat_IfHCOutBroadcastPkts_hi << 32) +
5561 (uint64_t)stats->stat_IfHCOutBroadcastPkts_lo;
5563 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
5564 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
5566 sc->stat_Dot3StatsCarrierSenseErrors =
5567 stats->stat_Dot3StatsCarrierSenseErrors;
5569 sc->stat_Dot3StatsFCSErrors =
5570 stats->stat_Dot3StatsFCSErrors;
5572 sc->stat_Dot3StatsAlignmentErrors =
5573 stats->stat_Dot3StatsAlignmentErrors;
5575 sc->stat_Dot3StatsSingleCollisionFrames =
5576 stats->stat_Dot3StatsSingleCollisionFrames;
5578 sc->stat_Dot3StatsMultipleCollisionFrames =
5579 stats->stat_Dot3StatsMultipleCollisionFrames;
5581 sc->stat_Dot3StatsDeferredTransmissions =
5582 stats->stat_Dot3StatsDeferredTransmissions;
5584 sc->stat_Dot3StatsExcessiveCollisions =
5585 stats->stat_Dot3StatsExcessiveCollisions;
5587 sc->stat_Dot3StatsLateCollisions =
5588 stats->stat_Dot3StatsLateCollisions;
5590 sc->stat_EtherStatsCollisions =
5591 stats->stat_EtherStatsCollisions;
5593 sc->stat_EtherStatsFragments =
5594 stats->stat_EtherStatsFragments;
5596 sc->stat_EtherStatsJabbers =
5597 stats->stat_EtherStatsJabbers;
5599 sc->stat_EtherStatsUndersizePkts =
5600 stats->stat_EtherStatsUndersizePkts;
5602 sc->stat_EtherStatsOverrsizePkts =
5603 stats->stat_EtherStatsOverrsizePkts;
5605 sc->stat_EtherStatsPktsRx64Octets =
5606 stats->stat_EtherStatsPktsRx64Octets;
5608 sc->stat_EtherStatsPktsRx65Octetsto127Octets =
5609 stats->stat_EtherStatsPktsRx65Octetsto127Octets;
5611 sc->stat_EtherStatsPktsRx128Octetsto255Octets =
5612 stats->stat_EtherStatsPktsRx128Octetsto255Octets;
5614 sc->stat_EtherStatsPktsRx256Octetsto511Octets =
5615 stats->stat_EtherStatsPktsRx256Octetsto511Octets;
5617 sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
5618 stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
5620 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
5621 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
5623 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
5624 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
5626 sc->stat_EtherStatsPktsTx64Octets =
5627 stats->stat_EtherStatsPktsTx64Octets;
5629 sc->stat_EtherStatsPktsTx65Octetsto127Octets =
5630 stats->stat_EtherStatsPktsTx65Octetsto127Octets;
5632 sc->stat_EtherStatsPktsTx128Octetsto255Octets =
5633 stats->stat_EtherStatsPktsTx128Octetsto255Octets;
5635 sc->stat_EtherStatsPktsTx256Octetsto511Octets =
5636 stats->stat_EtherStatsPktsTx256Octetsto511Octets;
5638 sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
5639 stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
5641 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
5642 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
5644 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
5645 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
5647 sc->stat_XonPauseFramesReceived =
5648 stats->stat_XonPauseFramesReceived;
5650 sc->stat_XoffPauseFramesReceived =
5651 stats->stat_XoffPauseFramesReceived;
5653 sc->stat_OutXonSent =
5654 stats->stat_OutXonSent;
5656 sc->stat_OutXoffSent =
5657 stats->stat_OutXoffSent;
5659 sc->stat_FlowControlDone =
5660 stats->stat_FlowControlDone;
5662 sc->stat_MacControlFramesReceived =
5663 stats->stat_MacControlFramesReceived;
5665 sc->stat_XoffStateEntered =
5666 stats->stat_XoffStateEntered;
5668 sc->stat_IfInFramesL2FilterDiscards =
5669 stats->stat_IfInFramesL2FilterDiscards;
5671 sc->stat_IfInRuleCheckerDiscards =
5672 stats->stat_IfInRuleCheckerDiscards;
5674 sc->stat_IfInFTQDiscards =
5675 stats->stat_IfInFTQDiscards;
5677 sc->stat_IfInMBUFDiscards =
5678 stats->stat_IfInMBUFDiscards;
5680 sc->stat_IfInRuleCheckerP4Hit =
5681 stats->stat_IfInRuleCheckerP4Hit;
5683 sc->stat_CatchupInRuleCheckerDiscards =
5684 stats->stat_CatchupInRuleCheckerDiscards;
5686 sc->stat_CatchupInFTQDiscards =
5687 stats->stat_CatchupInFTQDiscards;
5689 sc->stat_CatchupInMBUFDiscards =
5690 stats->stat_CatchupInMBUFDiscards;
5692 sc->stat_CatchupInRuleCheckerP4Hit =
5693 stats->stat_CatchupInRuleCheckerP4Hit;
5695 sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
5698 * Update the interface statistics from the
5699 * hardware statistics.
5701 ifp->if_collisions = (u_long)sc->stat_EtherStatsCollisions;
5703 ifp->if_ierrors = (u_long)sc->stat_EtherStatsUndersizePkts +
5704 (u_long)sc->stat_EtherStatsOverrsizePkts +
5705 (u_long)sc->stat_IfInMBUFDiscards +
5706 (u_long)sc->stat_Dot3StatsAlignmentErrors +
5707 (u_long)sc->stat_Dot3StatsFCSErrors +
5708 (u_long)sc->stat_IfInRuleCheckerDiscards +
5709 (u_long)sc->stat_IfInFTQDiscards +
5710 (u_long)sc->com_no_buffers;
5713 (u_long)sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
5714 (u_long)sc->stat_Dot3StatsExcessiveCollisions +
5715 (u_long)sc->stat_Dot3StatsLateCollisions;
5717 DBPRINT(sc, BCE_EXCESSIVE, "Exiting %s()\n", __func__);
5721 /****************************************************************************/
5722 /* Periodic function to notify the bootcode that the driver is still */
5727 /****************************************************************************/
5729 bce_pulse(void *xsc)
5731 struct bce_softc *sc = xsc;
5732 struct ifnet *ifp = &sc->arpcom.ac_if;
5735 lwkt_serialize_enter(ifp->if_serializer);
5737 if (ifp->if_flags & IFF_RUNNING) {
5738 if (sc->bce_irq_type == PCI_INTR_TYPE_MSI &&
5739 (sc->bce_flags & BCE_ONESHOT_MSI_FLAG) == 0)
5740 bce_pulse_check_msi(sc);
5743 /* Tell the firmware that the driver is still running. */
5744 msg = (uint32_t)++sc->bce_fw_drv_pulse_wr_seq;
5745 bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg);
5747 /* Update the bootcode condition. */
5748 sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
5750 /* Report whether the bootcode still knows the driver is running. */
5751 if (!sc->bce_drv_cardiac_arrest) {
5752 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) {
5753 sc->bce_drv_cardiac_arrest = 1;
5754 if_printf(ifp, "Bootcode lost the driver pulse! "
5755 "(bc_state = 0x%08X)\n", sc->bc_state);
5759 * Not supported by all bootcode versions.
5760 * (v5.0.11+ and v5.2.1+) Older bootcode
5761 * will require the driver to reset the
5762 * controller to clear this condition.
5764 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) {
5765 sc->bce_drv_cardiac_arrest = 0;
5766 if_printf(ifp, "Bootcode found the driver pulse! "
5767 "(bc_state = 0x%08X)\n", sc->bc_state);
5771 /* Schedule the next pulse. */
5772 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc);
5774 lwkt_serialize_exit(ifp->if_serializer);
5778 bce_pulse_check_msi(struct bce_softc *sc)
5782 if (bce_get_hw_rx_cons(sc) != sc->rx_cons) {
5784 } else if (bce_get_hw_tx_cons(sc) != sc->tx_cons) {
5787 struct status_block *sblk = sc->status_block;
5789 if ((sblk->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5790 (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
5797 msi_ctrl = REG_RD(sc, BCE_PCICFG_MSI_CONTROL);
5798 if ((msi_ctrl & BCE_PCICFG_MSI_CONTROL_ENABLE) == 0)
5801 if (sc->pulse_check_status_idx == sc->last_status_idx) {
5802 if_printf(&sc->arpcom.ac_if, "missing MSI\n");
5804 REG_WR(sc, BCE_PCICFG_MSI_CONTROL,
5805 msi_ctrl & ~BCE_PCICFG_MSI_CONTROL_ENABLE);
5806 REG_WR(sc, BCE_PCICFG_MSI_CONTROL, msi_ctrl);
5811 sc->pulse_check_status_idx = sc->last_status_idx;
5814 /****************************************************************************/
5815 /* Periodic function to perform maintenance tasks. */
5819 /****************************************************************************/
5821 bce_tick_serialized(struct bce_softc *sc)
5823 struct ifnet *ifp = &sc->arpcom.ac_if;
5824 struct mii_data *mii;
5826 ASSERT_SERIALIZED(ifp->if_serializer);
5828 /* Update the statistics from the hardware statistics block. */
5829 bce_stats_update(sc);
5831 /* Schedule the next tick. */
5832 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
5834 /* If link is up already up then we're done. */
5838 mii = device_get_softc(sc->bce_miibus);
5841 /* Check if the link has come up. */
5842 if ((mii->mii_media_status & IFM_ACTIVE) &&
5843 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
5845 /* Now that link is up, handle any outstanding TX traffic. */
5846 if (!ifq_is_empty(&ifp->if_snd))
5855 struct bce_softc *sc = xsc;
5856 struct ifnet *ifp = &sc->arpcom.ac_if;
5858 lwkt_serialize_enter(ifp->if_serializer);
5859 bce_tick_serialized(sc);
5860 lwkt_serialize_exit(ifp->if_serializer);
5865 /****************************************************************************/
5866 /* Allows the driver state to be dumped through the sysctl interface. */
5869 /* 0 for success, positive value for failure. */
5870 /****************************************************************************/
5872 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
5876 struct bce_softc *sc;
5879 error = sysctl_handle_int(oidp, &result, 0, req);
5881 if (error || !req->newptr)
5885 sc = (struct bce_softc *)arg1;
5886 bce_dump_driver_state(sc);
5893 /****************************************************************************/
5894 /* Allows the hardware state to be dumped through the sysctl interface. */
5897 /* 0 for success, positive value for failure. */
5898 /****************************************************************************/
5900 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
5904 struct bce_softc *sc;
5907 error = sysctl_handle_int(oidp, &result, 0, req);
5909 if (error || !req->newptr)
5913 sc = (struct bce_softc *)arg1;
5914 bce_dump_hw_state(sc);
5921 /****************************************************************************/
5922 /* Provides a sysctl interface to allows dumping the RX chain. */
5925 /* 0 for success, positive value for failure. */
5926 /****************************************************************************/
5928 bce_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS)
5932 struct bce_softc *sc;
5935 error = sysctl_handle_int(oidp, &result, 0, req);
5937 if (error || !req->newptr)
5941 sc = (struct bce_softc *)arg1;
5942 bce_dump_rx_chain(sc, 0, USABLE_RX_BD(sc));
5949 /****************************************************************************/
5950 /* Provides a sysctl interface to allows dumping the TX chain. */
5953 /* 0 for success, positive value for failure. */
5954 /****************************************************************************/
5956 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
5960 struct bce_softc *sc;
5963 error = sysctl_handle_int(oidp, &result, 0, req);
5965 if (error || !req->newptr)
5969 sc = (struct bce_softc *)arg1;
5970 bce_dump_tx_chain(sc, 0, USABLE_TX_BD(sc));
5977 /****************************************************************************/
5978 /* Provides a sysctl interface to allow reading arbitrary registers in the */
5979 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
5982 /* 0 for success, positive value for failure. */
5983 /****************************************************************************/
5985 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
5987 struct bce_softc *sc;
5989 uint32_t val, result;
5992 error = sysctl_handle_int(oidp, &result, 0, req);
5993 if (error || (req->newptr == NULL))
5996 /* Make sure the register is accessible. */
5997 if (result < 0x8000) {
5998 sc = (struct bce_softc *)arg1;
5999 val = REG_RD(sc, result);
6000 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
6002 } else if (result < 0x0280000) {
6003 sc = (struct bce_softc *)arg1;
6004 val = REG_RD_IND(sc, result);
6005 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
6012 /****************************************************************************/
6013 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */
6014 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
6017 /* 0 for success, positive value for failure. */
6018 /****************************************************************************/
6020 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
6022 struct bce_softc *sc;
6028 error = sysctl_handle_int(oidp, &result, 0, req);
6029 if (error || (req->newptr == NULL))
6032 /* Make sure the register is accessible. */
6033 if (result < 0x20) {
6034 sc = (struct bce_softc *)arg1;
6036 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
6037 if_printf(&sc->arpcom.ac_if,
6038 "phy 0x%02X = 0x%04X\n", result, val);
6044 /****************************************************************************/
6045 /* Provides a sysctl interface to forcing the driver to dump state and */
6046 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
6049 /* 0 for success, positive value for failure. */
6050 /****************************************************************************/
6052 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
6056 struct bce_softc *sc;
6059 error = sysctl_handle_int(oidp, &result, 0, req);
6061 if (error || !req->newptr)
6065 sc = (struct bce_softc *)arg1;
6074 /****************************************************************************/
6075 /* Adds any sysctl parameters for tuning or debugging purposes. */
6078 /* 0 for success, positive value for failure. */
6079 /****************************************************************************/
6081 bce_add_sysctls(struct bce_softc *sc)
6083 struct sysctl_ctx_list *ctx;
6084 struct sysctl_oid_list *children;
6086 sysctl_ctx_init(&sc->bce_sysctl_ctx);
6087 sc->bce_sysctl_tree = SYSCTL_ADD_NODE(&sc->bce_sysctl_ctx,
6088 SYSCTL_STATIC_CHILDREN(_hw),
6090 device_get_nameunit(sc->bce_dev),
6092 if (sc->bce_sysctl_tree == NULL) {
6093 device_printf(sc->bce_dev, "can't add sysctl node\n");
6097 ctx = &sc->bce_sysctl_ctx;
6098 children = SYSCTL_CHILDREN(sc->bce_sysctl_tree);
6100 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds_int",
6101 CTLTYPE_INT | CTLFLAG_RW,
6102 sc, 0, bce_sysctl_tx_bds_int, "I",
6103 "Send max coalesced BD count during interrupt");
6104 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds",
6105 CTLTYPE_INT | CTLFLAG_RW,
6106 sc, 0, bce_sysctl_tx_bds, "I",
6107 "Send max coalesced BD count");
6108 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks_int",
6109 CTLTYPE_INT | CTLFLAG_RW,
6110 sc, 0, bce_sysctl_tx_ticks_int, "I",
6111 "Send coalescing ticks during interrupt");
6112 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks",
6113 CTLTYPE_INT | CTLFLAG_RW,
6114 sc, 0, bce_sysctl_tx_ticks, "I",
6115 "Send coalescing ticks");
6117 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds_int",
6118 CTLTYPE_INT | CTLFLAG_RW,
6119 sc, 0, bce_sysctl_rx_bds_int, "I",
6120 "Receive max coalesced BD count during interrupt");
6121 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds",
6122 CTLTYPE_INT | CTLFLAG_RW,
6123 sc, 0, bce_sysctl_rx_bds, "I",
6124 "Receive max coalesced BD count");
6125 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks_int",
6126 CTLTYPE_INT | CTLFLAG_RW,
6127 sc, 0, bce_sysctl_rx_ticks_int, "I",
6128 "Receive coalescing ticks during interrupt");
6129 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks",
6130 CTLTYPE_INT | CTLFLAG_RW,
6131 sc, 0, bce_sysctl_rx_ticks, "I",
6132 "Receive coalescing ticks");
6134 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_pages",
6135 CTLFLAG_RD, &sc->rx_pages, 0, "# of RX pages");
6136 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_pages",
6137 CTLFLAG_RD, &sc->tx_pages, 0, "# of TX pages");
6140 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6142 CTLFLAG_RD, &sc->rx_low_watermark,
6143 0, "Lowest level of free rx_bd's");
6145 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6147 CTLFLAG_RD, &sc->rx_empty_count,
6148 0, "Number of times the RX chain was empty");
6150 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6152 CTLFLAG_RD, &sc->tx_hi_watermark,
6153 0, "Highest level of used tx_bd's");
6155 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6157 CTLFLAG_RD, &sc->tx_full_count,
6158 0, "Number of times the TX chain was full");
6160 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6161 "l2fhdr_status_errors",
6162 CTLFLAG_RD, &sc->l2fhdr_status_errors,
6163 0, "l2_fhdr status errors");
6165 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6166 "unexpected_attentions",
6167 CTLFLAG_RD, &sc->unexpected_attentions,
6168 0, "unexpected attentions");
6170 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6171 "lost_status_block_updates",
6172 CTLFLAG_RD, &sc->lost_status_block_updates,
6173 0, "lost status block updates");
6175 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6176 "mbuf_alloc_failed",
6177 CTLFLAG_RD, &sc->mbuf_alloc_failed,
6178 0, "mbuf cluster allocation failures");
6181 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6182 "stat_IfHCInOctets",
6183 CTLFLAG_RD, &sc->stat_IfHCInOctets,
6186 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6187 "stat_IfHCInBadOctets",
6188 CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
6189 "Bad bytes received");
6191 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6192 "stat_IfHCOutOctets",
6193 CTLFLAG_RD, &sc->stat_IfHCOutOctets,
6196 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6197 "stat_IfHCOutBadOctets",
6198 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
6201 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6202 "stat_IfHCInUcastPkts",
6203 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
6204 "Unicast packets received");
6206 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6207 "stat_IfHCInMulticastPkts",
6208 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
6209 "Multicast packets received");
6211 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6212 "stat_IfHCInBroadcastPkts",
6213 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
6214 "Broadcast packets received");
6216 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6217 "stat_IfHCOutUcastPkts",
6218 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
6219 "Unicast packets sent");
6221 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6222 "stat_IfHCOutMulticastPkts",
6223 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
6224 "Multicast packets sent");
6226 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6227 "stat_IfHCOutBroadcastPkts",
6228 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
6229 "Broadcast packets sent");
6231 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6232 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
6233 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
6234 0, "Internal MAC transmit errors");
6236 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6237 "stat_Dot3StatsCarrierSenseErrors",
6238 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
6239 0, "Carrier sense errors");
6241 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6242 "stat_Dot3StatsFCSErrors",
6243 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
6244 0, "Frame check sequence errors");
6246 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6247 "stat_Dot3StatsAlignmentErrors",
6248 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
6249 0, "Alignment errors");
6251 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6252 "stat_Dot3StatsSingleCollisionFrames",
6253 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
6254 0, "Single Collision Frames");
6256 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6257 "stat_Dot3StatsMultipleCollisionFrames",
6258 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
6259 0, "Multiple Collision Frames");
6261 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6262 "stat_Dot3StatsDeferredTransmissions",
6263 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
6264 0, "Deferred Transmissions");
6266 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6267 "stat_Dot3StatsExcessiveCollisions",
6268 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
6269 0, "Excessive Collisions");
6271 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6272 "stat_Dot3StatsLateCollisions",
6273 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
6274 0, "Late Collisions");
6276 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6277 "stat_EtherStatsCollisions",
6278 CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
6281 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6282 "stat_EtherStatsFragments",
6283 CTLFLAG_RD, &sc->stat_EtherStatsFragments,
6286 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6287 "stat_EtherStatsJabbers",
6288 CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
6291 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6292 "stat_EtherStatsUndersizePkts",
6293 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
6294 0, "Undersize packets");
6296 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6297 "stat_EtherStatsOverrsizePkts",
6298 CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts,
6299 0, "stat_EtherStatsOverrsizePkts");
6301 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6302 "stat_EtherStatsPktsRx64Octets",
6303 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
6304 0, "Bytes received in 64 byte packets");
6306 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6307 "stat_EtherStatsPktsRx65Octetsto127Octets",
6308 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
6309 0, "Bytes received in 65 to 127 byte packets");
6311 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6312 "stat_EtherStatsPktsRx128Octetsto255Octets",
6313 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
6314 0, "Bytes received in 128 to 255 byte packets");
6316 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6317 "stat_EtherStatsPktsRx256Octetsto511Octets",
6318 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
6319 0, "Bytes received in 256 to 511 byte packets");
6321 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6322 "stat_EtherStatsPktsRx512Octetsto1023Octets",
6323 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
6324 0, "Bytes received in 512 to 1023 byte packets");
6326 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6327 "stat_EtherStatsPktsRx1024Octetsto1522Octets",
6328 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
6329 0, "Bytes received in 1024 t0 1522 byte packets");
6331 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6332 "stat_EtherStatsPktsRx1523Octetsto9022Octets",
6333 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
6334 0, "Bytes received in 1523 to 9022 byte packets");
6336 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6337 "stat_EtherStatsPktsTx64Octets",
6338 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
6339 0, "Bytes sent in 64 byte packets");
6341 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6342 "stat_EtherStatsPktsTx65Octetsto127Octets",
6343 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
6344 0, "Bytes sent in 65 to 127 byte packets");
6346 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6347 "stat_EtherStatsPktsTx128Octetsto255Octets",
6348 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
6349 0, "Bytes sent in 128 to 255 byte packets");
6351 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6352 "stat_EtherStatsPktsTx256Octetsto511Octets",
6353 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
6354 0, "Bytes sent in 256 to 511 byte packets");
6356 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6357 "stat_EtherStatsPktsTx512Octetsto1023Octets",
6358 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
6359 0, "Bytes sent in 512 to 1023 byte packets");
6361 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6362 "stat_EtherStatsPktsTx1024Octetsto1522Octets",
6363 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
6364 0, "Bytes sent in 1024 to 1522 byte packets");
6366 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6367 "stat_EtherStatsPktsTx1523Octetsto9022Octets",
6368 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
6369 0, "Bytes sent in 1523 to 9022 byte packets");
6371 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6372 "stat_XonPauseFramesReceived",
6373 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
6374 0, "XON pause frames receved");
6376 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6377 "stat_XoffPauseFramesReceived",
6378 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
6379 0, "XOFF pause frames received");
6381 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6383 CTLFLAG_RD, &sc->stat_OutXonSent,
6384 0, "XON pause frames sent");
6386 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6388 CTLFLAG_RD, &sc->stat_OutXoffSent,
6389 0, "XOFF pause frames sent");
6391 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6392 "stat_FlowControlDone",
6393 CTLFLAG_RD, &sc->stat_FlowControlDone,
6394 0, "Flow control done");
6396 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6397 "stat_MacControlFramesReceived",
6398 CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
6399 0, "MAC control frames received");
6401 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6402 "stat_XoffStateEntered",
6403 CTLFLAG_RD, &sc->stat_XoffStateEntered,
6404 0, "XOFF state entered");
6406 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6407 "stat_IfInFramesL2FilterDiscards",
6408 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
6409 0, "Received L2 packets discarded");
6411 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6412 "stat_IfInRuleCheckerDiscards",
6413 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
6414 0, "Received packets discarded by rule");
6416 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6417 "stat_IfInFTQDiscards",
6418 CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
6419 0, "Received packet FTQ discards");
6421 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6422 "stat_IfInMBUFDiscards",
6423 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
6424 0, "Received packets discarded due to lack of controller buffer memory");
6426 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6427 "stat_IfInRuleCheckerP4Hit",
6428 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
6429 0, "Received packets rule checker hits");
6431 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6432 "stat_CatchupInRuleCheckerDiscards",
6433 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
6434 0, "Received packets discarded in Catchup path");
6436 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6437 "stat_CatchupInFTQDiscards",
6438 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
6439 0, "Received packets discarded in FTQ in Catchup path");
6441 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6442 "stat_CatchupInMBUFDiscards",
6443 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
6444 0, "Received packets discarded in controller buffer memory in Catchup path");
6446 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6447 "stat_CatchupInRuleCheckerP4Hit",
6448 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
6449 0, "Received packets rule checker hits in Catchup path");
6451 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6453 CTLFLAG_RD, &sc->com_no_buffers,
6454 0, "Valid packets received but no RX buffers available");
6457 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6458 "driver_state", CTLTYPE_INT | CTLFLAG_RW,
6460 bce_sysctl_driver_state, "I", "Drive state information");
6462 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6463 "hw_state", CTLTYPE_INT | CTLFLAG_RW,
6465 bce_sysctl_hw_state, "I", "Hardware state information");
6467 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6468 "dump_rx_chain", CTLTYPE_INT | CTLFLAG_RW,
6470 bce_sysctl_dump_rx_chain, "I", "Dump rx_bd chain");
6472 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6473 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
6475 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
6477 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6478 "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
6480 bce_sysctl_breakpoint, "I", "Driver breakpoint");
6482 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6483 "reg_read", CTLTYPE_INT | CTLFLAG_RW,
6485 bce_sysctl_reg_read, "I", "Register read");
6487 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6488 "phy_read", CTLTYPE_INT | CTLFLAG_RW,
6490 bce_sysctl_phy_read, "I", "PHY register read");
6497 /****************************************************************************/
6498 /* BCE Debug Routines */
6499 /****************************************************************************/
6502 /****************************************************************************/
6503 /* Freezes the controller to allow for a cohesive state dump. */
6507 /****************************************************************************/
6509 bce_freeze_controller(struct bce_softc *sc)
6513 val = REG_RD(sc, BCE_MISC_COMMAND);
6514 val |= BCE_MISC_COMMAND_DISABLE_ALL;
6515 REG_WR(sc, BCE_MISC_COMMAND, val);
6519 /****************************************************************************/
6520 /* Unfreezes the controller after a freeze operation. This may not always */
6521 /* work and the controller will require a reset! */
6525 /****************************************************************************/
6527 bce_unfreeze_controller(struct bce_softc *sc)
6531 val = REG_RD(sc, BCE_MISC_COMMAND);
6532 val |= BCE_MISC_COMMAND_ENABLE_ALL;
6533 REG_WR(sc, BCE_MISC_COMMAND, val);
6537 /****************************************************************************/
6538 /* Prints out information about an mbuf. */
6542 /****************************************************************************/
6544 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
6546 struct ifnet *ifp = &sc->arpcom.ac_if;
6547 uint32_t val_hi, val_lo;
6548 struct mbuf *mp = m;
6551 /* Index out of range. */
6552 if_printf(ifp, "mbuf: null pointer\n");
6557 val_hi = BCE_ADDR_HI(mp);
6558 val_lo = BCE_ADDR_LO(mp);
6559 if_printf(ifp, "mbuf: vaddr = 0x%08X:%08X, m_len = %d, "
6560 "m_flags = ( ", val_hi, val_lo, mp->m_len);
6562 if (mp->m_flags & M_EXT)
6564 if (mp->m_flags & M_PKTHDR)
6565 kprintf("M_PKTHDR ");
6566 if (mp->m_flags & M_EOR)
6569 if (mp->m_flags & M_RDONLY)
6570 kprintf("M_RDONLY ");
6573 val_hi = BCE_ADDR_HI(mp->m_data);
6574 val_lo = BCE_ADDR_LO(mp->m_data);
6575 kprintf(") m_data = 0x%08X:%08X\n", val_hi, val_lo);
6577 if (mp->m_flags & M_PKTHDR) {
6578 if_printf(ifp, "- m_pkthdr: flags = ( ");
6579 if (mp->m_flags & M_BCAST)
6580 kprintf("M_BCAST ");
6581 if (mp->m_flags & M_MCAST)
6582 kprintf("M_MCAST ");
6583 if (mp->m_flags & M_FRAG)
6585 if (mp->m_flags & M_FIRSTFRAG)
6586 kprintf("M_FIRSTFRAG ");
6587 if (mp->m_flags & M_LASTFRAG)
6588 kprintf("M_LASTFRAG ");
6590 if (mp->m_flags & M_VLANTAG)
6591 kprintf("M_VLANTAG ");
6594 if (mp->m_flags & M_PROMISC)
6595 kprintf("M_PROMISC ");
6597 kprintf(") csum_flags = ( ");
6598 if (mp->m_pkthdr.csum_flags & CSUM_IP)
6599 kprintf("CSUM_IP ");
6600 if (mp->m_pkthdr.csum_flags & CSUM_TCP)
6601 kprintf("CSUM_TCP ");
6602 if (mp->m_pkthdr.csum_flags & CSUM_UDP)
6603 kprintf("CSUM_UDP ");
6604 if (mp->m_pkthdr.csum_flags & CSUM_IP_FRAGS)
6605 kprintf("CSUM_IP_FRAGS ");
6606 if (mp->m_pkthdr.csum_flags & CSUM_FRAGMENT)
6607 kprintf("CSUM_FRAGMENT ");
6609 if (mp->m_pkthdr.csum_flags & CSUM_TSO)
6610 kprintf("CSUM_TSO ");
6612 if (mp->m_pkthdr.csum_flags & CSUM_IP_CHECKED)
6613 kprintf("CSUM_IP_CHECKED ");
6614 if (mp->m_pkthdr.csum_flags & CSUM_IP_VALID)
6615 kprintf("CSUM_IP_VALID ");
6616 if (mp->m_pkthdr.csum_flags & CSUM_DATA_VALID)
6617 kprintf("CSUM_DATA_VALID ");
6621 if (mp->m_flags & M_EXT) {
6622 val_hi = BCE_ADDR_HI(mp->m_ext.ext_buf);
6623 val_lo = BCE_ADDR_LO(mp->m_ext.ext_buf);
6624 if_printf(ifp, "- m_ext: vaddr = 0x%08X:%08X, "
6626 val_hi, val_lo, mp->m_ext.ext_size);
6633 /****************************************************************************/
6634 /* Prints out the mbufs in the TX mbuf chain. */
6638 /****************************************************************************/
6640 bce_dump_tx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6642 struct ifnet *ifp = &sc->arpcom.ac_if;
6646 "----------------------------"
6648 "----------------------------\n");
6650 for (i = 0; i < count; i++) {
6651 if_printf(ifp, "txmbuf[%d]\n", chain_prod);
6652 bce_dump_mbuf(sc, sc->tx_mbuf_ptr[chain_prod]);
6653 chain_prod = TX_CHAIN_IDX(sc, NEXT_TX_BD(chain_prod));
6657 "----------------------------"
6659 "----------------------------\n");
6663 /****************************************************************************/
6664 /* Prints out the mbufs in the RX mbuf chain. */
6668 /****************************************************************************/
6670 bce_dump_rx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6672 struct ifnet *ifp = &sc->arpcom.ac_if;
6676 "----------------------------"
6678 "----------------------------\n");
6680 for (i = 0; i < count; i++) {
6681 if_printf(ifp, "rxmbuf[0x%04X]\n", chain_prod);
6682 bce_dump_mbuf(sc, sc->rx_mbuf_ptr[chain_prod]);
6683 chain_prod = RX_CHAIN_IDX(sc, NEXT_RX_BD(chain_prod));
6687 "----------------------------"
6689 "----------------------------\n");
6693 /****************************************************************************/
6694 /* Prints out a tx_bd structure. */
6698 /****************************************************************************/
6700 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
6702 struct ifnet *ifp = &sc->arpcom.ac_if;
6704 if (idx > MAX_TX_BD(sc)) {
6705 /* Index out of range. */
6706 if_printf(ifp, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
6707 } else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) {
6708 /* TX Chain page pointer. */
6709 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6710 "chain page pointer\n",
6711 idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo);
6713 /* Normal tx_bd entry. */
6714 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6716 "vlan tag= 0x%04X, flags = 0x%04X (",
6717 idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo,
6718 txbd->tx_bd_mss_nbytes,
6719 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
6721 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT)
6722 kprintf(" CONN_FAULT");
6724 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM)
6725 kprintf(" TCP_UDP_CKSUM");
6727 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM)
6728 kprintf(" IP_CKSUM");
6730 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG)
6733 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW)
6734 kprintf(" COAL_NOW");
6736 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC)
6737 kprintf(" DONT_GEN_CRC");
6739 if (txbd->tx_bd_flags & TX_BD_FLAGS_START)
6742 if (txbd->tx_bd_flags & TX_BD_FLAGS_END)
6745 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO)
6748 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD)
6749 kprintf(" OPTION_WORD");
6751 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS)
6754 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP)
6762 /****************************************************************************/
6763 /* Prints out a rx_bd structure. */
6767 /****************************************************************************/
6769 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
6771 struct ifnet *ifp = &sc->arpcom.ac_if;
6773 if (idx > MAX_RX_BD(sc)) {
6774 /* Index out of range. */
6775 if_printf(ifp, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
6776 } else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) {
6777 /* TX Chain page pointer. */
6778 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6779 "chain page pointer\n",
6780 idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo);
6782 /* Normal tx_bd entry. */
6783 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6784 "nbytes = 0x%08X, flags = 0x%08X\n",
6785 idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo,
6786 rxbd->rx_bd_len, rxbd->rx_bd_flags);
6791 /****************************************************************************/
6792 /* Prints out a l2_fhdr structure. */
6796 /****************************************************************************/
6798 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
6800 if_printf(&sc->arpcom.ac_if, "l2_fhdr[0x%04X]: status = 0x%08X, "
6801 "pkt_len = 0x%04X, vlan = 0x%04x, "
6802 "ip_xsum = 0x%04X, tcp_udp_xsum = 0x%04X\n",
6803 idx, l2fhdr->l2_fhdr_status,
6804 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
6805 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
6809 /****************************************************************************/
6810 /* Prints out the tx chain. */
6814 /****************************************************************************/
6816 bce_dump_tx_chain(struct bce_softc *sc, int tx_prod, int count)
6818 struct ifnet *ifp = &sc->arpcom.ac_if;
6821 /* First some info about the tx_bd chain structure. */
6823 "----------------------------"
6825 "----------------------------\n");
6827 if_printf(ifp, "page size = 0x%08X, "
6828 "tx chain pages = 0x%08X\n",
6829 (uint32_t)BCM_PAGE_SIZE, (uint32_t)sc->tx_pages);
6831 if_printf(ifp, "tx_bd per page = 0x%08X, "
6832 "usable tx_bd per page = 0x%08X\n",
6833 (uint32_t)TOTAL_TX_BD_PER_PAGE,
6834 (uint32_t)USABLE_TX_BD_PER_PAGE);
6836 if_printf(ifp, "total tx_bd = 0x%08X\n", (uint32_t)TOTAL_TX_BD(sc));
6839 "----------------------------"
6841 "----------------------------\n");
6843 /* Now print out the tx_bd's themselves. */
6844 for (i = 0; i < count; i++) {
6847 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
6848 bce_dump_txbd(sc, tx_prod, txbd);
6849 tx_prod = TX_CHAIN_IDX(sc, NEXT_TX_BD(tx_prod));
6853 "----------------------------"
6855 "----------------------------\n");
6859 /****************************************************************************/
6860 /* Prints out the rx chain. */
6864 /****************************************************************************/
6866 bce_dump_rx_chain(struct bce_softc *sc, int rx_prod, int count)
6868 struct ifnet *ifp = &sc->arpcom.ac_if;
6871 /* First some info about the tx_bd chain structure. */
6873 "----------------------------"
6875 "----------------------------\n");
6877 if_printf(ifp, "page size = 0x%08X, "
6878 "rx chain pages = 0x%08X\n",
6879 (uint32_t)BCM_PAGE_SIZE, (uint32_t)sc->rx_pages);
6881 if_printf(ifp, "rx_bd per page = 0x%08X, "
6882 "usable rx_bd per page = 0x%08X\n",
6883 (uint32_t)TOTAL_RX_BD_PER_PAGE,
6884 (uint32_t)USABLE_RX_BD_PER_PAGE);
6886 if_printf(ifp, "total rx_bd = 0x%08X\n", (uint32_t)TOTAL_RX_BD(sc));
6889 "----------------------------"
6891 "----------------------------\n");
6893 /* Now print out the rx_bd's themselves. */
6894 for (i = 0; i < count; i++) {
6897 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
6898 bce_dump_rxbd(sc, rx_prod, rxbd);
6899 rx_prod = RX_CHAIN_IDX(sc, NEXT_RX_BD(rx_prod));
6903 "----------------------------"
6905 "----------------------------\n");
6909 /****************************************************************************/
6910 /* Prints out the status block from host memory. */
6914 /****************************************************************************/
6916 bce_dump_status_block(struct bce_softc *sc)
6918 struct status_block *sblk = sc->status_block;
6919 struct ifnet *ifp = &sc->arpcom.ac_if;
6922 "----------------------------"
6924 "----------------------------\n");
6926 if_printf(ifp, " 0x%08X - attn_bits\n", sblk->status_attn_bits);
6928 if_printf(ifp, " 0x%08X - attn_bits_ack\n",
6929 sblk->status_attn_bits_ack);
6931 if_printf(ifp, "0x%04X(0x%04X) - rx_cons0\n",
6932 sblk->status_rx_quick_consumer_index0,
6933 (uint16_t)RX_CHAIN_IDX(sc, sblk->status_rx_quick_consumer_index0));
6935 if_printf(ifp, "0x%04X(0x%04X) - tx_cons0\n",
6936 sblk->status_tx_quick_consumer_index0,
6937 (uint16_t)TX_CHAIN_IDX(sc, sblk->status_tx_quick_consumer_index0));
6939 if_printf(ifp, " 0x%04X - status_idx\n", sblk->status_idx);
6941 /* Theses indices are not used for normal L2 drivers. */
6942 if (sblk->status_rx_quick_consumer_index1) {
6943 if_printf(ifp, "0x%04X(0x%04X) - rx_cons1\n",
6944 sblk->status_rx_quick_consumer_index1,
6945 (uint16_t)RX_CHAIN_IDX(sc,
6946 sblk->status_rx_quick_consumer_index1));
6949 if (sblk->status_tx_quick_consumer_index1) {
6950 if_printf(ifp, "0x%04X(0x%04X) - tx_cons1\n",
6951 sblk->status_tx_quick_consumer_index1,
6952 (uint16_t)TX_CHAIN_IDX(sc,
6953 sblk->status_tx_quick_consumer_index1));
6956 if (sblk->status_rx_quick_consumer_index2) {
6957 if_printf(ifp, "0x%04X(0x%04X)- rx_cons2\n",
6958 sblk->status_rx_quick_consumer_index2,
6959 (uint16_t)RX_CHAIN_IDX(sc,
6960 sblk->status_rx_quick_consumer_index2));
6963 if (sblk->status_tx_quick_consumer_index2) {
6964 if_printf(ifp, "0x%04X(0x%04X) - tx_cons2\n",
6965 sblk->status_tx_quick_consumer_index2,
6966 (uint16_t)TX_CHAIN_IDX(sc,
6967 sblk->status_tx_quick_consumer_index2));
6970 if (sblk->status_rx_quick_consumer_index3) {
6971 if_printf(ifp, "0x%04X(0x%04X) - rx_cons3\n",
6972 sblk->status_rx_quick_consumer_index3,
6973 (uint16_t)RX_CHAIN_IDX(sc,
6974 sblk->status_rx_quick_consumer_index3));
6977 if (sblk->status_tx_quick_consumer_index3) {
6978 if_printf(ifp, "0x%04X(0x%04X) - tx_cons3\n",
6979 sblk->status_tx_quick_consumer_index3,
6980 (uint16_t)TX_CHAIN_IDX(sc,
6981 sblk->status_tx_quick_consumer_index3));
6984 if (sblk->status_rx_quick_consumer_index4 ||
6985 sblk->status_rx_quick_consumer_index5) {
6986 if_printf(ifp, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n",
6987 sblk->status_rx_quick_consumer_index4,
6988 sblk->status_rx_quick_consumer_index5);
6991 if (sblk->status_rx_quick_consumer_index6 ||
6992 sblk->status_rx_quick_consumer_index7) {
6993 if_printf(ifp, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n",
6994 sblk->status_rx_quick_consumer_index6,
6995 sblk->status_rx_quick_consumer_index7);
6998 if (sblk->status_rx_quick_consumer_index8 ||
6999 sblk->status_rx_quick_consumer_index9) {
7000 if_printf(ifp, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n",
7001 sblk->status_rx_quick_consumer_index8,
7002 sblk->status_rx_quick_consumer_index9);
7005 if (sblk->status_rx_quick_consumer_index10 ||
7006 sblk->status_rx_quick_consumer_index11) {
7007 if_printf(ifp, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n",
7008 sblk->status_rx_quick_consumer_index10,
7009 sblk->status_rx_quick_consumer_index11);
7012 if (sblk->status_rx_quick_consumer_index12 ||
7013 sblk->status_rx_quick_consumer_index13) {
7014 if_printf(ifp, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n",
7015 sblk->status_rx_quick_consumer_index12,
7016 sblk->status_rx_quick_consumer_index13);
7019 if (sblk->status_rx_quick_consumer_index14 ||
7020 sblk->status_rx_quick_consumer_index15) {
7021 if_printf(ifp, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n",
7022 sblk->status_rx_quick_consumer_index14,
7023 sblk->status_rx_quick_consumer_index15);
7026 if (sblk->status_completion_producer_index ||
7027 sblk->status_cmd_consumer_index) {
7028 if_printf(ifp, "com_prod = 0x%08X, cmd_cons = 0x%08X\n",
7029 sblk->status_completion_producer_index,
7030 sblk->status_cmd_consumer_index);
7034 "----------------------------"
7036 "----------------------------\n");
7040 /****************************************************************************/
7041 /* Prints out the statistics block. */
7045 /****************************************************************************/
7047 bce_dump_stats_block(struct bce_softc *sc)
7049 struct statistics_block *sblk = sc->stats_block;
7050 struct ifnet *ifp = &sc->arpcom.ac_if;
7054 " Stats Block (All Stats Not Shown Are 0) "
7055 "---------------\n");
7057 if (sblk->stat_IfHCInOctets_hi || sblk->stat_IfHCInOctets_lo) {
7058 if_printf(ifp, "0x%08X:%08X : IfHcInOctets\n",
7059 sblk->stat_IfHCInOctets_hi,
7060 sblk->stat_IfHCInOctets_lo);
7063 if (sblk->stat_IfHCInBadOctets_hi || sblk->stat_IfHCInBadOctets_lo) {
7064 if_printf(ifp, "0x%08X:%08X : IfHcInBadOctets\n",
7065 sblk->stat_IfHCInBadOctets_hi,
7066 sblk->stat_IfHCInBadOctets_lo);
7069 if (sblk->stat_IfHCOutOctets_hi || sblk->stat_IfHCOutOctets_lo) {
7070 if_printf(ifp, "0x%08X:%08X : IfHcOutOctets\n",
7071 sblk->stat_IfHCOutOctets_hi,
7072 sblk->stat_IfHCOutOctets_lo);
7075 if (sblk->stat_IfHCOutBadOctets_hi || sblk->stat_IfHCOutBadOctets_lo) {
7076 if_printf(ifp, "0x%08X:%08X : IfHcOutBadOctets\n",
7077 sblk->stat_IfHCOutBadOctets_hi,
7078 sblk->stat_IfHCOutBadOctets_lo);
7081 if (sblk->stat_IfHCInUcastPkts_hi || sblk->stat_IfHCInUcastPkts_lo) {
7082 if_printf(ifp, "0x%08X:%08X : IfHcInUcastPkts\n",
7083 sblk->stat_IfHCInUcastPkts_hi,
7084 sblk->stat_IfHCInUcastPkts_lo);
7087 if (sblk->stat_IfHCInBroadcastPkts_hi ||
7088 sblk->stat_IfHCInBroadcastPkts_lo) {
7089 if_printf(ifp, "0x%08X:%08X : IfHcInBroadcastPkts\n",
7090 sblk->stat_IfHCInBroadcastPkts_hi,
7091 sblk->stat_IfHCInBroadcastPkts_lo);
7094 if (sblk->stat_IfHCInMulticastPkts_hi ||
7095 sblk->stat_IfHCInMulticastPkts_lo) {
7096 if_printf(ifp, "0x%08X:%08X : IfHcInMulticastPkts\n",
7097 sblk->stat_IfHCInMulticastPkts_hi,
7098 sblk->stat_IfHCInMulticastPkts_lo);
7101 if (sblk->stat_IfHCOutUcastPkts_hi || sblk->stat_IfHCOutUcastPkts_lo) {
7102 if_printf(ifp, "0x%08X:%08X : IfHcOutUcastPkts\n",
7103 sblk->stat_IfHCOutUcastPkts_hi,
7104 sblk->stat_IfHCOutUcastPkts_lo);
7107 if (sblk->stat_IfHCOutBroadcastPkts_hi ||
7108 sblk->stat_IfHCOutBroadcastPkts_lo) {
7109 if_printf(ifp, "0x%08X:%08X : IfHcOutBroadcastPkts\n",
7110 sblk->stat_IfHCOutBroadcastPkts_hi,
7111 sblk->stat_IfHCOutBroadcastPkts_lo);
7114 if (sblk->stat_IfHCOutMulticastPkts_hi ||
7115 sblk->stat_IfHCOutMulticastPkts_lo) {
7116 if_printf(ifp, "0x%08X:%08X : IfHcOutMulticastPkts\n",
7117 sblk->stat_IfHCOutMulticastPkts_hi,
7118 sblk->stat_IfHCOutMulticastPkts_lo);
7121 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) {
7122 if_printf(ifp, " 0x%08X : "
7123 "emac_tx_stat_dot3statsinternalmactransmiterrors\n",
7124 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
7127 if (sblk->stat_Dot3StatsCarrierSenseErrors) {
7128 if_printf(ifp, " 0x%08X : "
7129 "Dot3StatsCarrierSenseErrors\n",
7130 sblk->stat_Dot3StatsCarrierSenseErrors);
7133 if (sblk->stat_Dot3StatsFCSErrors) {
7134 if_printf(ifp, " 0x%08X : Dot3StatsFCSErrors\n",
7135 sblk->stat_Dot3StatsFCSErrors);
7138 if (sblk->stat_Dot3StatsAlignmentErrors) {
7139 if_printf(ifp, " 0x%08X : Dot3StatsAlignmentErrors\n",
7140 sblk->stat_Dot3StatsAlignmentErrors);
7143 if (sblk->stat_Dot3StatsSingleCollisionFrames) {
7144 if_printf(ifp, " 0x%08X : "
7145 "Dot3StatsSingleCollisionFrames\n",
7146 sblk->stat_Dot3StatsSingleCollisionFrames);
7149 if (sblk->stat_Dot3StatsMultipleCollisionFrames) {
7150 if_printf(ifp, " 0x%08X : "
7151 "Dot3StatsMultipleCollisionFrames\n",
7152 sblk->stat_Dot3StatsMultipleCollisionFrames);
7155 if (sblk->stat_Dot3StatsDeferredTransmissions) {
7156 if_printf(ifp, " 0x%08X : "
7157 "Dot3StatsDeferredTransmissions\n",
7158 sblk->stat_Dot3StatsDeferredTransmissions);
7161 if (sblk->stat_Dot3StatsExcessiveCollisions) {
7162 if_printf(ifp, " 0x%08X : "
7163 "Dot3StatsExcessiveCollisions\n",
7164 sblk->stat_Dot3StatsExcessiveCollisions);
7167 if (sblk->stat_Dot3StatsLateCollisions) {
7168 if_printf(ifp, " 0x%08X : Dot3StatsLateCollisions\n",
7169 sblk->stat_Dot3StatsLateCollisions);
7172 if (sblk->stat_EtherStatsCollisions) {
7173 if_printf(ifp, " 0x%08X : EtherStatsCollisions\n",
7174 sblk->stat_EtherStatsCollisions);
7177 if (sblk->stat_EtherStatsFragments) {
7178 if_printf(ifp, " 0x%08X : EtherStatsFragments\n",
7179 sblk->stat_EtherStatsFragments);
7182 if (sblk->stat_EtherStatsJabbers) {
7183 if_printf(ifp, " 0x%08X : EtherStatsJabbers\n",
7184 sblk->stat_EtherStatsJabbers);
7187 if (sblk->stat_EtherStatsUndersizePkts) {
7188 if_printf(ifp, " 0x%08X : EtherStatsUndersizePkts\n",
7189 sblk->stat_EtherStatsUndersizePkts);
7192 if (sblk->stat_EtherStatsOverrsizePkts) {
7193 if_printf(ifp, " 0x%08X : EtherStatsOverrsizePkts\n",
7194 sblk->stat_EtherStatsOverrsizePkts);
7197 if (sblk->stat_EtherStatsPktsRx64Octets) {
7198 if_printf(ifp, " 0x%08X : EtherStatsPktsRx64Octets\n",
7199 sblk->stat_EtherStatsPktsRx64Octets);
7202 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) {
7203 if_printf(ifp, " 0x%08X : "
7204 "EtherStatsPktsRx65Octetsto127Octets\n",
7205 sblk->stat_EtherStatsPktsRx65Octetsto127Octets);
7208 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) {
7209 if_printf(ifp, " 0x%08X : "
7210 "EtherStatsPktsRx128Octetsto255Octets\n",
7211 sblk->stat_EtherStatsPktsRx128Octetsto255Octets);
7214 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) {
7215 if_printf(ifp, " 0x%08X : "
7216 "EtherStatsPktsRx256Octetsto511Octets\n",
7217 sblk->stat_EtherStatsPktsRx256Octetsto511Octets);
7220 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) {
7221 if_printf(ifp, " 0x%08X : "
7222 "EtherStatsPktsRx512Octetsto1023Octets\n",
7223 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets);
7226 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) {
7227 if_printf(ifp, " 0x%08X : "
7228 "EtherStatsPktsRx1024Octetsto1522Octets\n",
7229 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets);
7232 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) {
7233 if_printf(ifp, " 0x%08X : "
7234 "EtherStatsPktsRx1523Octetsto9022Octets\n",
7235 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets);
7238 if (sblk->stat_EtherStatsPktsTx64Octets) {
7239 if_printf(ifp, " 0x%08X : EtherStatsPktsTx64Octets\n",
7240 sblk->stat_EtherStatsPktsTx64Octets);
7243 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) {
7244 if_printf(ifp, " 0x%08X : "
7245 "EtherStatsPktsTx65Octetsto127Octets\n",
7246 sblk->stat_EtherStatsPktsTx65Octetsto127Octets);
7249 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) {
7250 if_printf(ifp, " 0x%08X : "
7251 "EtherStatsPktsTx128Octetsto255Octets\n",
7252 sblk->stat_EtherStatsPktsTx128Octetsto255Octets);
7255 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) {
7256 if_printf(ifp, " 0x%08X : "
7257 "EtherStatsPktsTx256Octetsto511Octets\n",
7258 sblk->stat_EtherStatsPktsTx256Octetsto511Octets);
7261 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) {
7262 if_printf(ifp, " 0x%08X : "
7263 "EtherStatsPktsTx512Octetsto1023Octets\n",
7264 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets);
7267 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) {
7268 if_printf(ifp, " 0x%08X : "
7269 "EtherStatsPktsTx1024Octetsto1522Octets\n",
7270 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets);
7273 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) {
7274 if_printf(ifp, " 0x%08X : "
7275 "EtherStatsPktsTx1523Octetsto9022Octets\n",
7276 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets);
7279 if (sblk->stat_XonPauseFramesReceived) {
7280 if_printf(ifp, " 0x%08X : XonPauseFramesReceived\n",
7281 sblk->stat_XonPauseFramesReceived);
7284 if (sblk->stat_XoffPauseFramesReceived) {
7285 if_printf(ifp, " 0x%08X : XoffPauseFramesReceived\n",
7286 sblk->stat_XoffPauseFramesReceived);
7289 if (sblk->stat_OutXonSent) {
7290 if_printf(ifp, " 0x%08X : OutXoffSent\n",
7291 sblk->stat_OutXonSent);
7294 if (sblk->stat_OutXoffSent) {
7295 if_printf(ifp, " 0x%08X : OutXoffSent\n",
7296 sblk->stat_OutXoffSent);
7299 if (sblk->stat_FlowControlDone) {
7300 if_printf(ifp, " 0x%08X : FlowControlDone\n",
7301 sblk->stat_FlowControlDone);
7304 if (sblk->stat_MacControlFramesReceived) {
7305 if_printf(ifp, " 0x%08X : MacControlFramesReceived\n",
7306 sblk->stat_MacControlFramesReceived);
7309 if (sblk->stat_XoffStateEntered) {
7310 if_printf(ifp, " 0x%08X : XoffStateEntered\n",
7311 sblk->stat_XoffStateEntered);
7314 if (sblk->stat_IfInFramesL2FilterDiscards) {
7315 if_printf(ifp, " 0x%08X : IfInFramesL2FilterDiscards\n", sblk->stat_IfInFramesL2FilterDiscards);
7318 if (sblk->stat_IfInRuleCheckerDiscards) {
7319 if_printf(ifp, " 0x%08X : IfInRuleCheckerDiscards\n",
7320 sblk->stat_IfInRuleCheckerDiscards);
7323 if (sblk->stat_IfInFTQDiscards) {
7324 if_printf(ifp, " 0x%08X : IfInFTQDiscards\n",
7325 sblk->stat_IfInFTQDiscards);
7328 if (sblk->stat_IfInMBUFDiscards) {
7329 if_printf(ifp, " 0x%08X : IfInMBUFDiscards\n",
7330 sblk->stat_IfInMBUFDiscards);
7333 if (sblk->stat_IfInRuleCheckerP4Hit) {
7334 if_printf(ifp, " 0x%08X : IfInRuleCheckerP4Hit\n",
7335 sblk->stat_IfInRuleCheckerP4Hit);
7338 if (sblk->stat_CatchupInRuleCheckerDiscards) {
7339 if_printf(ifp, " 0x%08X : "
7340 "CatchupInRuleCheckerDiscards\n",
7341 sblk->stat_CatchupInRuleCheckerDiscards);
7344 if (sblk->stat_CatchupInFTQDiscards) {
7345 if_printf(ifp, " 0x%08X : CatchupInFTQDiscards\n",
7346 sblk->stat_CatchupInFTQDiscards);
7349 if (sblk->stat_CatchupInMBUFDiscards) {
7350 if_printf(ifp, " 0x%08X : CatchupInMBUFDiscards\n",
7351 sblk->stat_CatchupInMBUFDiscards);
7354 if (sblk->stat_CatchupInRuleCheckerP4Hit) {
7355 if_printf(ifp, " 0x%08X : CatchupInRuleCheckerP4Hit\n",
7356 sblk->stat_CatchupInRuleCheckerP4Hit);
7360 "----------------------------"
7362 "----------------------------\n");
7366 /****************************************************************************/
7367 /* Prints out a summary of the driver state. */
7371 /****************************************************************************/
7373 bce_dump_driver_state(struct bce_softc *sc)
7375 struct ifnet *ifp = &sc->arpcom.ac_if;
7376 uint32_t val_hi, val_lo;
7379 "-----------------------------"
7381 "-----------------------------\n");
7383 val_hi = BCE_ADDR_HI(sc);
7384 val_lo = BCE_ADDR_LO(sc);
7385 if_printf(ifp, "0x%08X:%08X - (sc) driver softc structure "
7386 "virtual address\n", val_hi, val_lo);
7388 val_hi = BCE_ADDR_HI(sc->status_block);
7389 val_lo = BCE_ADDR_LO(sc->status_block);
7390 if_printf(ifp, "0x%08X:%08X - (sc->status_block) status block "
7391 "virtual address\n", val_hi, val_lo);
7393 val_hi = BCE_ADDR_HI(sc->stats_block);
7394 val_lo = BCE_ADDR_LO(sc->stats_block);
7395 if_printf(ifp, "0x%08X:%08X - (sc->stats_block) statistics block "
7396 "virtual address\n", val_hi, val_lo);
7398 val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
7399 val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
7400 if_printf(ifp, "0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
7401 "virtual adddress\n", val_hi, val_lo);
7403 val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
7404 val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
7405 if_printf(ifp, "0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
7406 "virtual address\n", val_hi, val_lo);
7408 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
7409 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
7410 if_printf(ifp, "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
7411 "virtual address\n", val_hi, val_lo);
7413 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
7414 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
7415 if_printf(ifp, "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
7416 "virtual address\n", val_hi, val_lo);
7418 if_printf(ifp, " 0x%08X - (sc->interrupts_generated) "
7419 "h/w intrs\n", sc->interrupts_generated);
7421 if_printf(ifp, " 0x%08X - (sc->rx_interrupts) "
7422 "rx interrupts handled\n", sc->rx_interrupts);
7424 if_printf(ifp, " 0x%08X - (sc->tx_interrupts) "
7425 "tx interrupts handled\n", sc->tx_interrupts);
7427 if_printf(ifp, " 0x%08X - (sc->last_status_idx) "
7428 "status block index\n", sc->last_status_idx);
7430 if_printf(ifp, " 0x%04X(0x%04X) - (sc->tx_prod) "
7431 "tx producer index\n",
7432 sc->tx_prod, (uint16_t)TX_CHAIN_IDX(sc, sc->tx_prod));
7434 if_printf(ifp, " 0x%04X(0x%04X) - (sc->tx_cons) "
7435 "tx consumer index\n",
7436 sc->tx_cons, (uint16_t)TX_CHAIN_IDX(sc, sc->tx_cons));
7438 if_printf(ifp, " 0x%08X - (sc->tx_prod_bseq) "
7439 "tx producer bseq index\n", sc->tx_prod_bseq);
7441 if_printf(ifp, " 0x%04X(0x%04X) - (sc->rx_prod) "
7442 "rx producer index\n",
7443 sc->rx_prod, (uint16_t)RX_CHAIN_IDX(sc, sc->rx_prod));
7445 if_printf(ifp, " 0x%04X(0x%04X) - (sc->rx_cons) "
7446 "rx consumer index\n",
7447 sc->rx_cons, (uint16_t)RX_CHAIN_IDX(sc, sc->rx_cons));
7449 if_printf(ifp, " 0x%08X - (sc->rx_prod_bseq) "
7450 "rx producer bseq index\n", sc->rx_prod_bseq);
7452 if_printf(ifp, " 0x%08X - (sc->rx_mbuf_alloc) "
7453 "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7455 if_printf(ifp, " 0x%08X - (sc->free_rx_bd) "
7456 "free rx_bd's\n", sc->free_rx_bd);
7458 if_printf(ifp, "0x%08X/%08X - (sc->rx_low_watermark) rx "
7459 "low watermark\n", sc->rx_low_watermark, sc->max_rx_bd);
7461 if_printf(ifp, " 0x%08X - (sc->txmbuf_alloc) "
7462 "tx mbufs allocated\n", sc->tx_mbuf_alloc);
7464 if_printf(ifp, " 0x%08X - (sc->rx_mbuf_alloc) "
7465 "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7467 if_printf(ifp, " 0x%08X - (sc->used_tx_bd) used tx_bd's\n",
7470 if_printf(ifp, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n",
7471 sc->tx_hi_watermark, sc->max_tx_bd);
7473 if_printf(ifp, " 0x%08X - (sc->mbuf_alloc_failed) "
7474 "failed mbuf alloc\n", sc->mbuf_alloc_failed);
7477 "----------------------------"
7479 "----------------------------\n");
7483 /****************************************************************************/
7484 /* Prints out the hardware state through a summary of important registers, */
7485 /* followed by a complete register dump. */
7489 /****************************************************************************/
7491 bce_dump_hw_state(struct bce_softc *sc)
7493 struct ifnet *ifp = &sc->arpcom.ac_if;
7498 "----------------------------"
7500 "----------------------------\n");
7502 if_printf(ifp, "%s - bootcode version\n", sc->bce_bc_ver);
7504 val1 = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
7505 if_printf(ifp, "0x%08X - (0x%06X) misc_enable_status_bits\n",
7506 val1, BCE_MISC_ENABLE_STATUS_BITS);
7508 val1 = REG_RD(sc, BCE_DMA_STATUS);
7509 if_printf(ifp, "0x%08X - (0x%04X) dma_status\n", val1, BCE_DMA_STATUS);
7511 val1 = REG_RD(sc, BCE_CTX_STATUS);
7512 if_printf(ifp, "0x%08X - (0x%04X) ctx_status\n", val1, BCE_CTX_STATUS);
7514 val1 = REG_RD(sc, BCE_EMAC_STATUS);
7515 if_printf(ifp, "0x%08X - (0x%04X) emac_status\n",
7516 val1, BCE_EMAC_STATUS);
7518 val1 = REG_RD(sc, BCE_RPM_STATUS);
7519 if_printf(ifp, "0x%08X - (0x%04X) rpm_status\n", val1, BCE_RPM_STATUS);
7521 val1 = REG_RD(sc, BCE_TBDR_STATUS);
7522 if_printf(ifp, "0x%08X - (0x%04X) tbdr_status\n",
7523 val1, BCE_TBDR_STATUS);
7525 val1 = REG_RD(sc, BCE_TDMA_STATUS);
7526 if_printf(ifp, "0x%08X - (0x%04X) tdma_status\n",
7527 val1, BCE_TDMA_STATUS);
7529 val1 = REG_RD(sc, BCE_HC_STATUS);
7530 if_printf(ifp, "0x%08X - (0x%06X) hc_status\n", val1, BCE_HC_STATUS);
7532 val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7533 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7534 val1, BCE_TXP_CPU_STATE);
7536 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7537 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7538 val1, BCE_TPAT_CPU_STATE);
7540 val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7541 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7542 val1, BCE_RXP_CPU_STATE);
7544 val1 = REG_RD_IND(sc, BCE_COM_CPU_STATE);
7545 if_printf(ifp, "0x%08X - (0x%06X) com_cpu_state\n",
7546 val1, BCE_COM_CPU_STATE);
7548 val1 = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
7549 if_printf(ifp, "0x%08X - (0x%06X) mcp_cpu_state\n",
7550 val1, BCE_MCP_CPU_STATE);
7552 val1 = REG_RD_IND(sc, BCE_CP_CPU_STATE);
7553 if_printf(ifp, "0x%08X - (0x%06X) cp_cpu_state\n",
7554 val1, BCE_CP_CPU_STATE);
7557 "----------------------------"
7559 "----------------------------\n");
7562 "----------------------------"
7564 "----------------------------\n");
7566 for (i = 0x400; i < 0x8000; i += 0x10) {
7567 if_printf(ifp, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7569 REG_RD(sc, i + 0x4),
7570 REG_RD(sc, i + 0x8),
7571 REG_RD(sc, i + 0xc));
7575 "----------------------------"
7577 "----------------------------\n");
7581 /****************************************************************************/
7582 /* Prints out the TXP state. */
7586 /****************************************************************************/
7588 bce_dump_txp_state(struct bce_softc *sc)
7590 struct ifnet *ifp = &sc->arpcom.ac_if;
7595 "----------------------------"
7597 "----------------------------\n");
7599 val1 = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
7600 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_mode\n",
7601 val1, BCE_TXP_CPU_MODE);
7603 val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7604 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7605 val1, BCE_TXP_CPU_STATE);
7607 val1 = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
7608 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_event_mask\n",
7609 val1, BCE_TXP_CPU_EVENT_MASK);
7612 "----------------------------"
7614 "----------------------------\n");
7616 for (i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
7617 /* Skip the big blank spaces */
7618 if (i < 0x454000 && i > 0x5ffff) {
7619 if_printf(ifp, "0x%04X: "
7620 "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7622 REG_RD_IND(sc, i + 0x4),
7623 REG_RD_IND(sc, i + 0x8),
7624 REG_RD_IND(sc, i + 0xc));
7629 "----------------------------"
7631 "----------------------------\n");
7635 /****************************************************************************/
7636 /* Prints out the RXP state. */
7640 /****************************************************************************/
7642 bce_dump_rxp_state(struct bce_softc *sc)
7644 struct ifnet *ifp = &sc->arpcom.ac_if;
7649 "----------------------------"
7651 "----------------------------\n");
7653 val1 = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
7654 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_mode\n",
7655 val1, BCE_RXP_CPU_MODE);
7657 val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7658 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7659 val1, BCE_RXP_CPU_STATE);
7661 val1 = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
7662 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_event_mask\n",
7663 val1, BCE_RXP_CPU_EVENT_MASK);
7666 "----------------------------"
7668 "----------------------------\n");
7670 for (i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
7671 /* Skip the big blank sapces */
7672 if (i < 0xc5400 && i > 0xdffff) {
7673 if_printf(ifp, "0x%04X: "
7674 "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7676 REG_RD_IND(sc, i + 0x4),
7677 REG_RD_IND(sc, i + 0x8),
7678 REG_RD_IND(sc, i + 0xc));
7683 "----------------------------"
7685 "----------------------------\n");
7689 /****************************************************************************/
7690 /* Prints out the TPAT state. */
7694 /****************************************************************************/
7696 bce_dump_tpat_state(struct bce_softc *sc)
7698 struct ifnet *ifp = &sc->arpcom.ac_if;
7703 "----------------------------"
7705 "----------------------------\n");
7707 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
7708 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_mode\n",
7709 val1, BCE_TPAT_CPU_MODE);
7711 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7712 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7713 val1, BCE_TPAT_CPU_STATE);
7715 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
7716 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_event_mask\n",
7717 val1, BCE_TPAT_CPU_EVENT_MASK);
7720 "----------------------------"
7722 "----------------------------\n");
7724 for (i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
7725 /* Skip the big blank spaces */
7726 if (i < 0x854000 && i > 0x9ffff) {
7727 if_printf(ifp, "0x%04X: "
7728 "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7730 REG_RD_IND(sc, i + 0x4),
7731 REG_RD_IND(sc, i + 0x8),
7732 REG_RD_IND(sc, i + 0xc));
7737 "----------------------------"
7739 "----------------------------\n");
7743 /****************************************************************************/
7744 /* Prints out the driver state and then enters the debugger. */
7748 /****************************************************************************/
7750 bce_breakpoint(struct bce_softc *sc)
7753 bce_freeze_controller(sc);
7756 bce_dump_driver_state(sc);
7757 bce_dump_status_block(sc);
7758 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD(sc));
7759 bce_dump_hw_state(sc);
7760 bce_dump_txp_state(sc);
7763 bce_unfreeze_controller(sc);
7766 /* Call the debugger. */
7770 #endif /* BCE_DEBUG */
7773 bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS)
7775 struct bce_softc *sc = arg1;
7777 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7778 &sc->bce_tx_quick_cons_trip_int,
7779 BCE_COALMASK_TX_BDS_INT);
7783 bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS)
7785 struct bce_softc *sc = arg1;
7787 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7788 &sc->bce_tx_quick_cons_trip,
7789 BCE_COALMASK_TX_BDS);
7793 bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS)
7795 struct bce_softc *sc = arg1;
7797 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7798 &sc->bce_tx_ticks_int,
7799 BCE_COALMASK_TX_TICKS_INT);
7803 bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS)
7805 struct bce_softc *sc = arg1;
7807 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7809 BCE_COALMASK_TX_TICKS);
7813 bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS)
7815 struct bce_softc *sc = arg1;
7817 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7818 &sc->bce_rx_quick_cons_trip_int,
7819 BCE_COALMASK_RX_BDS_INT);
7823 bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS)
7825 struct bce_softc *sc = arg1;
7827 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7828 &sc->bce_rx_quick_cons_trip,
7829 BCE_COALMASK_RX_BDS);
7833 bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS)
7835 struct bce_softc *sc = arg1;
7837 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7838 &sc->bce_rx_ticks_int,
7839 BCE_COALMASK_RX_TICKS_INT);
7843 bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS)
7845 struct bce_softc *sc = arg1;
7847 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7849 BCE_COALMASK_RX_TICKS);
7853 bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS, uint32_t *coal,
7854 uint32_t coalchg_mask)
7856 struct bce_softc *sc = arg1;
7857 struct ifnet *ifp = &sc->arpcom.ac_if;
7860 lwkt_serialize_enter(ifp->if_serializer);
7863 error = sysctl_handle_int(oidp, &v, 0, req);
7864 if (!error && req->newptr != NULL) {
7869 sc->bce_coalchg_mask |= coalchg_mask;
7873 lwkt_serialize_exit(ifp->if_serializer);
7878 bce_coal_change(struct bce_softc *sc)
7880 struct ifnet *ifp = &sc->arpcom.ac_if;
7882 ASSERT_SERIALIZED(ifp->if_serializer);
7884 if ((ifp->if_flags & IFF_RUNNING) == 0) {
7885 sc->bce_coalchg_mask = 0;
7889 if (sc->bce_coalchg_mask &
7890 (BCE_COALMASK_TX_BDS | BCE_COALMASK_TX_BDS_INT)) {
7891 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
7892 (sc->bce_tx_quick_cons_trip_int << 16) |
7893 sc->bce_tx_quick_cons_trip);
7895 if_printf(ifp, "tx_bds %u, tx_bds_int %u\n",
7896 sc->bce_tx_quick_cons_trip,
7897 sc->bce_tx_quick_cons_trip_int);
7901 if (sc->bce_coalchg_mask &
7902 (BCE_COALMASK_TX_TICKS | BCE_COALMASK_TX_TICKS_INT)) {
7903 REG_WR(sc, BCE_HC_TX_TICKS,
7904 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
7906 if_printf(ifp, "tx_ticks %u, tx_ticks_int %u\n",
7907 sc->bce_tx_ticks, sc->bce_tx_ticks_int);
7911 if (sc->bce_coalchg_mask &
7912 (BCE_COALMASK_RX_BDS | BCE_COALMASK_RX_BDS_INT)) {
7913 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
7914 (sc->bce_rx_quick_cons_trip_int << 16) |
7915 sc->bce_rx_quick_cons_trip);
7917 if_printf(ifp, "rx_bds %u, rx_bds_int %u\n",
7918 sc->bce_rx_quick_cons_trip,
7919 sc->bce_rx_quick_cons_trip_int);
7923 if (sc->bce_coalchg_mask &
7924 (BCE_COALMASK_RX_TICKS | BCE_COALMASK_RX_TICKS_INT)) {
7925 REG_WR(sc, BCE_HC_RX_TICKS,
7926 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
7928 if_printf(ifp, "rx_ticks %u, rx_ticks_int %u\n",
7929 sc->bce_rx_ticks, sc->bce_rx_ticks_int);
7933 sc->bce_coalchg_mask = 0;
7937 bce_tso_setup(struct bce_softc *sc, struct mbuf **mp,
7938 uint16_t *flags0, uint16_t *mss0)
7942 int thoff, iphlen, hoff;
7945 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
7947 hoff = m->m_pkthdr.csum_lhlen;
7948 iphlen = m->m_pkthdr.csum_iphlen;
7949 thoff = m->m_pkthdr.csum_thlen;
7951 KASSERT(hoff >= sizeof(struct ether_header),
7952 ("invalid ether header len %d", hoff));
7953 KASSERT(iphlen >= sizeof(struct ip),
7954 ("invalid ip header len %d", iphlen));
7955 KASSERT(thoff >= sizeof(struct tcphdr),
7956 ("invalid tcp header len %d", thoff));
7958 if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
7959 m = m_pullup(m, hoff + iphlen + thoff);
7967 /* Set the LSO flag in the TX BD */
7968 flags = TX_BD_FLAGS_SW_LSO;
7970 /* Set the length of IP + TCP options (in 32 bit words) */
7971 flags |= (((iphlen + thoff -
7972 sizeof(struct ip) - sizeof(struct tcphdr)) >> 2) << 8);
7974 *mss0 = htole16(m->m_pkthdr.tso_segsz);