1 @c Copyright (C) 1988-2015 Free Software Foundation, Inc.
2 @c This is part of the GCC manual.
3 @c For copying conditions, see the file gcc.texi.
7 @chapter Machine Descriptions
8 @cindex machine descriptions
10 A machine description has two parts: a file of instruction patterns
11 (@file{.md} file) and a C header file of macro definitions.
13 The @file{.md} file for a target machine contains a pattern for each
14 instruction that the target machine supports (or at least each instruction
15 that is worth telling the compiler about). It may also contain comments.
16 A semicolon causes the rest of the line to be a comment, unless the semicolon
17 is inside a quoted string.
19 See the next chapter for information on the C header file.
22 * Overview:: How the machine description is used.
23 * Patterns:: How to write instruction patterns.
24 * Example:: An explained example of a @code{define_insn} pattern.
25 * RTL Template:: The RTL template defines what insns match a pattern.
26 * Output Template:: The output template says how to make assembler code
28 * Output Statement:: For more generality, write C code to output
30 * Predicates:: Controlling what kinds of operands can be used
32 * Constraints:: Fine-tuning operand selection.
33 * Standard Names:: Names mark patterns to use for code generation.
34 * Pattern Ordering:: When the order of patterns makes a difference.
35 * Dependent Patterns:: Having one pattern may make you need another.
36 * Jump Patterns:: Special considerations for patterns for jump insns.
37 * Looping Patterns:: How to define patterns for special looping insns.
38 * Insn Canonicalizations::Canonicalization of Instructions
39 * Expander Definitions::Generating a sequence of several RTL insns
40 for a standard operation.
41 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
42 * Including Patterns:: Including Patterns in Machine Descriptions.
43 * Peephole Definitions::Defining machine-specific peephole optimizations.
44 * Insn Attributes:: Specifying the value of attributes for generated insns.
45 * Conditional Execution::Generating @code{define_insn} patterns for
47 * Define Subst:: Generating @code{define_insn} and @code{define_expand}
48 patterns from other patterns.
49 * Constant Definitions::Defining symbolic constants that can be used in the
51 * Iterators:: Using iterators to generate patterns from a template.
55 @section Overview of How the Machine Description is Used
57 There are three main conversions that happen in the compiler:
62 The front end reads the source code and builds a parse tree.
65 The parse tree is used to generate an RTL insn list based on named
69 The insn list is matched against the RTL templates to produce assembler
74 For the generate pass, only the names of the insns matter, from either a
75 named @code{define_insn} or a @code{define_expand}. The compiler will
76 choose the pattern with the right name and apply the operands according
77 to the documentation later in this chapter, without regard for the RTL
78 template or operand constraints. Note that the names the compiler looks
79 for are hard-coded in the compiler---it will ignore unnamed patterns and
80 patterns with names it doesn't know about, but if you don't provide a
81 named pattern it needs, it will abort.
83 If a @code{define_insn} is used, the template given is inserted into the
84 insn list. If a @code{define_expand} is used, one of three things
85 happens, based on the condition logic. The condition logic may manually
86 create new insns for the insn list, say via @code{emit_insn()}, and
87 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
88 compiler to use an alternate way of performing that task. If it invokes
89 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
90 is inserted, as if the @code{define_expand} were a @code{define_insn}.
92 Once the insn list is generated, various optimization passes convert,
93 replace, and rearrange the insns in the insn list. This is where the
94 @code{define_split} and @code{define_peephole} patterns get used, for
97 Finally, the insn list's RTL is matched up with the RTL templates in the
98 @code{define_insn} patterns, and those patterns are used to emit the
99 final assembly code. For this purpose, each named @code{define_insn}
100 acts like it's unnamed, since the names are ignored.
103 @section Everything about Instruction Patterns
105 @cindex instruction patterns
108 A @code{define_insn} expression is used to define instruction patterns
109 to which insns may be matched. A @code{define_insn} expression contains
110 an incomplete RTL expression, with pieces to be filled in later, operand
111 constraints that restrict how the pieces can be filled in, and an output
112 template or C code to generate the assembler output.
114 A @code{define_insn} is an RTL expression containing four or five operands:
118 An optional name. The presence of a name indicate that this instruction
119 pattern can perform a certain standard job for the RTL-generation
120 pass of the compiler. This pass knows certain names and will use
121 the instruction patterns with those names, if the names are defined
122 in the machine description.
124 The absence of a name is indicated by writing an empty string
125 where the name should go. Nameless instruction patterns are never
126 used for generating RTL code, but they may permit several simpler insns
127 to be combined later on.
129 Names that are not thus known and used in RTL-generation have no
130 effect; they are equivalent to no name at all.
132 For the purpose of debugging the compiler, you may also specify a
133 name beginning with the @samp{*} character. Such a name is used only
134 for identifying the instruction in RTL dumps; it is equivalent to having
135 a nameless pattern for all other purposes. Names beginning with the
136 @samp{*} character are not required to be unique.
139 The @dfn{RTL template}: This is a vector of incomplete RTL expressions
140 which describe the semantics of the instruction (@pxref{RTL Template}).
141 It is incomplete because it may contain @code{match_operand},
142 @code{match_operator}, and @code{match_dup} expressions that stand for
143 operands of the instruction.
145 If the vector has multiple elements, the RTL template is treated as a
146 @code{parallel} expression.
149 @cindex pattern conditions
150 @cindex conditions, in patterns
151 The condition: This is a string which contains a C expression. When the
152 compiler attempts to match RTL against a pattern, the condition is
153 evaluated. If the condition evaluates to @code{true}, the match is
154 permitted. The condition may be an empty string, which is treated
155 as always @code{true}.
157 @cindex named patterns and conditions
158 For a named pattern, the condition may not depend on the data in the
159 insn being matched, but only the target-machine-type flags. The compiler
160 needs to test these conditions during initialization in order to learn
161 exactly which named instructions are available in a particular run.
164 For nameless patterns, the condition is applied only when matching an
165 individual insn, and only after the insn has matched the pattern's
166 recognition template. The insn's operands may be found in the vector
169 For an insn where the condition has once matched, it
170 cannot later be used to control register allocation by excluding
171 certain register or value combinations.
174 The @dfn{output template} or @dfn{output statement}: This is either
175 a string, or a fragment of C code which returns a string.
177 When simple substitution isn't general enough, you can specify a piece
178 of C code to compute the output. @xref{Output Statement}.
181 The @dfn{insn attributes}: This is an optional vector containing the values of
182 attributes for insns matching this pattern (@pxref{Insn Attributes}).
186 @section Example of @code{define_insn}
187 @cindex @code{define_insn} example
189 Here is an example of an instruction pattern, taken from the machine
190 description for the 68000/68020.
195 (match_operand:SI 0 "general_operand" "rm"))]
199 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
201 return \"cmpl #0,%0\";
206 This can also be written using braced strings:
211 (match_operand:SI 0 "general_operand" "rm"))]
214 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
220 This describes an instruction which sets the condition codes based on the
221 value of a general operand. It has no condition, so any insn with an RTL
222 description of the form shown may be matched to this pattern. The name
223 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL
224 generation pass that, when it is necessary to test such a value, an insn
225 to do so can be constructed using this pattern.
227 The output control string is a piece of C code which chooses which
228 output template to return based on the kind of operand and the specific
229 type of CPU for which code is being generated.
231 @samp{"rm"} is an operand constraint. Its meaning is explained below.
234 @section RTL Template
235 @cindex RTL insn template
236 @cindex generating insns
237 @cindex insns, generating
238 @cindex recognizing insns
239 @cindex insns, recognizing
241 The RTL template is used to define which insns match the particular pattern
242 and how to find their operands. For named patterns, the RTL template also
243 says how to construct an insn from specified operands.
245 Construction involves substituting specified operands into a copy of the
246 template. Matching involves determining the values that serve as the
247 operands in the insn being matched. Both of these activities are
248 controlled by special expression types that direct matching and
249 substitution of the operands.
252 @findex match_operand
253 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
254 This expression is a placeholder for operand number @var{n} of
255 the insn. When constructing an insn, operand number @var{n}
256 will be substituted at this point. When matching an insn, whatever
257 appears at this position in the insn will be taken as operand
258 number @var{n}; but it must satisfy @var{predicate} or this instruction
259 pattern will not match at all.
261 Operand numbers must be chosen consecutively counting from zero in
262 each instruction pattern. There may be only one @code{match_operand}
263 expression in the pattern for each operand number. Usually operands
264 are numbered in the order of appearance in @code{match_operand}
265 expressions. In the case of a @code{define_expand}, any operand numbers
266 used only in @code{match_dup} expressions have higher values than all
267 other operand numbers.
269 @var{predicate} is a string that is the name of a function that
270 accepts two arguments, an expression and a machine mode.
271 @xref{Predicates}. During matching, the function will be called with
272 the putative operand as the expression and @var{m} as the mode
273 argument (if @var{m} is not specified, @code{VOIDmode} will be used,
274 which normally causes @var{predicate} to accept any mode). If it
275 returns zero, this instruction pattern fails to match.
276 @var{predicate} may be an empty string; then it means no test is to be
277 done on the operand, so anything which occurs in this position is
280 Most of the time, @var{predicate} will reject modes other than @var{m}---but
281 not always. For example, the predicate @code{address_operand} uses
282 @var{m} as the mode of memory ref that the address should be valid for.
283 Many predicates accept @code{const_int} nodes even though their mode is
286 @var{constraint} controls reloading and the choice of the best register
287 class to use for a value, as explained later (@pxref{Constraints}).
288 If the constraint would be an empty string, it can be omitted.
290 People are often unclear on the difference between the constraint and the
291 predicate. The predicate helps decide whether a given insn matches the
292 pattern. The constraint plays no role in this decision; instead, it
293 controls various decisions in the case of an insn which does match.
295 @findex match_scratch
296 @item (match_scratch:@var{m} @var{n} @var{constraint})
297 This expression is also a placeholder for operand number @var{n}
298 and indicates that operand must be a @code{scratch} or @code{reg}
301 When matching patterns, this is equivalent to
304 (match_operand:@var{m} @var{n} "scratch_operand" @var{constraint})
307 but, when generating RTL, it produces a (@code{scratch}:@var{m})
310 If the last few expressions in a @code{parallel} are @code{clobber}
311 expressions whose operands are either a hard register or
312 @code{match_scratch}, the combiner can add or delete them when
313 necessary. @xref{Side Effects}.
316 @item (match_dup @var{n})
317 This expression is also a placeholder for operand number @var{n}.
318 It is used when the operand needs to appear more than once in the
321 In construction, @code{match_dup} acts just like @code{match_operand}:
322 the operand is substituted into the insn being constructed. But in
323 matching, @code{match_dup} behaves differently. It assumes that operand
324 number @var{n} has already been determined by a @code{match_operand}
325 appearing earlier in the recognition template, and it matches only an
326 identical-looking expression.
328 Note that @code{match_dup} should not be used to tell the compiler that
329 a particular register is being used for two operands (example:
330 @code{add} that adds one register to another; the second register is
331 both an input operand and the output operand). Use a matching
332 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
333 operand is used in two places in the template, such as an instruction
334 that computes both a quotient and a remainder, where the opcode takes
335 two input operands but the RTL template has to refer to each of those
336 twice; once for the quotient pattern and once for the remainder pattern.
338 @findex match_operator
339 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
340 This pattern is a kind of placeholder for a variable RTL expression
343 When constructing an insn, it stands for an RTL expression whose
344 expression code is taken from that of operand @var{n}, and whose
345 operands are constructed from the patterns @var{operands}.
347 When matching an expression, it matches an expression if the function
348 @var{predicate} returns nonzero on that expression @emph{and} the
349 patterns @var{operands} match the operands of the expression.
351 Suppose that the function @code{commutative_operator} is defined as
352 follows, to match any expression whose operator is one of the
353 commutative arithmetic operators of RTL and whose mode is @var{mode}:
357 commutative_integer_operator (x, mode)
361 enum rtx_code code = GET_CODE (x);
362 if (GET_MODE (x) != mode)
364 return (GET_RTX_CLASS (code) == RTX_COMM_ARITH
365 || code == EQ || code == NE);
369 Then the following pattern will match any RTL expression consisting
370 of a commutative operator applied to two general operands:
373 (match_operator:SI 3 "commutative_operator"
374 [(match_operand:SI 1 "general_operand" "g")
375 (match_operand:SI 2 "general_operand" "g")])
378 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
379 because the expressions to be matched all contain two operands.
381 When this pattern does match, the two operands of the commutative
382 operator are recorded as operands 1 and 2 of the insn. (This is done
383 by the two instances of @code{match_operand}.) Operand 3 of the insn
384 will be the entire commutative expression: use @code{GET_CODE
385 (operands[3])} to see which commutative operator was used.
387 The machine mode @var{m} of @code{match_operator} works like that of
388 @code{match_operand}: it is passed as the second argument to the
389 predicate function, and that function is solely responsible for
390 deciding whether the expression to be matched ``has'' that mode.
392 When constructing an insn, argument 3 of the gen-function will specify
393 the operation (i.e.@: the expression code) for the expression to be
394 made. It should be an RTL expression, whose expression code is copied
395 into a new expression whose operands are arguments 1 and 2 of the
396 gen-function. The subexpressions of argument 3 are not used;
397 only its expression code matters.
399 When @code{match_operator} is used in a pattern for matching an insn,
400 it usually best if the operand number of the @code{match_operator}
401 is higher than that of the actual operands of the insn. This improves
402 register allocation because the register allocator often looks at
403 operands 1 and 2 of insns to see if it can do register tying.
405 There is no way to specify constraints in @code{match_operator}. The
406 operand of the insn which corresponds to the @code{match_operator}
407 never has any constraints because it is never reloaded as a whole.
408 However, if parts of its @var{operands} are matched by
409 @code{match_operand} patterns, those parts may have constraints of
413 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
414 Like @code{match_dup}, except that it applies to operators instead of
415 operands. When constructing an insn, operand number @var{n} will be
416 substituted at this point. But in matching, @code{match_op_dup} behaves
417 differently. It assumes that operand number @var{n} has already been
418 determined by a @code{match_operator} appearing earlier in the
419 recognition template, and it matches only an identical-looking
422 @findex match_parallel
423 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
424 This pattern is a placeholder for an insn that consists of a
425 @code{parallel} expression with a variable number of elements. This
426 expression should only appear at the top level of an insn pattern.
428 When constructing an insn, operand number @var{n} will be substituted at
429 this point. When matching an insn, it matches if the body of the insn
430 is a @code{parallel} expression with at least as many elements as the
431 vector of @var{subpat} expressions in the @code{match_parallel}, if each
432 @var{subpat} matches the corresponding element of the @code{parallel},
433 @emph{and} the function @var{predicate} returns nonzero on the
434 @code{parallel} that is the body of the insn. It is the responsibility
435 of the predicate to validate elements of the @code{parallel} beyond
436 those listed in the @code{match_parallel}.
438 A typical use of @code{match_parallel} is to match load and store
439 multiple expressions, which can contain a variable number of elements
440 in a @code{parallel}. For example,
444 [(match_parallel 0 "load_multiple_operation"
445 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
446 (match_operand:SI 2 "memory_operand" "m"))
448 (clobber (reg:SI 179))])]
453 This example comes from @file{a29k.md}. The function
454 @code{load_multiple_operation} is defined in @file{a29k.c} and checks
455 that subsequent elements in the @code{parallel} are the same as the
456 @code{set} in the pattern, except that they are referencing subsequent
457 registers and memory locations.
459 An insn that matches this pattern might look like:
463 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
465 (clobber (reg:SI 179))
467 (mem:SI (plus:SI (reg:SI 100)
470 (mem:SI (plus:SI (reg:SI 100)
474 @findex match_par_dup
475 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
476 Like @code{match_op_dup}, but for @code{match_parallel} instead of
477 @code{match_operator}.
481 @node Output Template
482 @section Output Templates and Operand Substitution
483 @cindex output templates
484 @cindex operand substitution
486 @cindex @samp{%} in template
488 The @dfn{output template} is a string which specifies how to output the
489 assembler code for an instruction pattern. Most of the template is a
490 fixed string which is output literally. The character @samp{%} is used
491 to specify where to substitute an operand; it can also be used to
492 identify places where different variants of the assembler require
495 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
496 operand @var{n} at that point in the string.
498 @samp{%} followed by a letter and a digit says to output an operand in an
499 alternate fashion. Four letters have standard, built-in meanings described
500 below. The machine description macro @code{PRINT_OPERAND} can define
501 additional letters with nonstandard meanings.
503 @samp{%c@var{digit}} can be used to substitute an operand that is a
504 constant value without the syntax that normally indicates an immediate
507 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
508 the constant is negated before printing.
510 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
511 memory reference, with the actual operand treated as the address. This may
512 be useful when outputting a ``load address'' instruction, because often the
513 assembler syntax for such an instruction requires you to write the operand
514 as if it were a memory reference.
516 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
519 @samp{%=} outputs a number which is unique to each instruction in the
520 entire compilation. This is useful for making local labels to be
521 referred to more than once in a single template that generates multiple
522 assembler instructions.
524 @samp{%} followed by a punctuation character specifies a substitution that
525 does not use an operand. Only one case is standard: @samp{%%} outputs a
526 @samp{%} into the assembler code. Other nonstandard cases can be
527 defined in the @code{PRINT_OPERAND} macro. You must also define
528 which punctuation characters are valid with the
529 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
533 The template may generate multiple assembler instructions. Write the text
534 for the instructions, with @samp{\;} between them.
536 @cindex matching operands
537 When the RTL contains two operands which are required by constraint to match
538 each other, the output template must refer only to the lower-numbered operand.
539 Matching operands are not always identical, and the rest of the compiler
540 arranges to put the proper RTL expression for printing into the lower-numbered
543 One use of nonstandard letters or punctuation following @samp{%} is to
544 distinguish between different assembler languages for the same machine; for
545 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
546 requires periods in most opcode names, while MIT syntax does not. For
547 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
548 syntax. The same file of patterns is used for both kinds of output syntax,
549 but the character sequence @samp{%.} is used in each place where Motorola
550 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
551 defines the sequence to output a period; the macro for MIT syntax defines
554 @cindex @code{#} in template
555 As a special case, a template consisting of the single character @code{#}
556 instructs the compiler to first split the insn, and then output the
557 resulting instructions separately. This helps eliminate redundancy in the
558 output templates. If you have a @code{define_insn} that needs to emit
559 multiple assembler instructions, and there is a matching @code{define_split}
560 already defined, then you can simply use @code{#} as the output template
561 instead of writing an output template that emits the multiple assembler
564 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
565 of the form @samp{@{option0|option1|option2@}} in the templates. These
566 describe multiple variants of assembler language syntax.
567 @xref{Instruction Output}.
569 @node Output Statement
570 @section C Statements for Assembler Output
571 @cindex output statements
572 @cindex C statements for assembler output
573 @cindex generating assembler output
575 Often a single fixed template string cannot produce correct and efficient
576 assembler code for all the cases that are recognized by a single
577 instruction pattern. For example, the opcodes may depend on the kinds of
578 operands; or some unfortunate combinations of operands may require extra
579 machine instructions.
581 If the output control string starts with a @samp{@@}, then it is actually
582 a series of templates, each on a separate line. (Blank lines and
583 leading spaces and tabs are ignored.) The templates correspond to the
584 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
585 if a target machine has a two-address add instruction @samp{addr} to add
586 into a register and another @samp{addm} to add a register to memory, you
587 might write this pattern:
590 (define_insn "addsi3"
591 [(set (match_operand:SI 0 "general_operand" "=r,m")
592 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
593 (match_operand:SI 2 "general_operand" "g,r")))]
600 @cindex @code{*} in template
601 @cindex asterisk in template
602 If the output control string starts with a @samp{*}, then it is not an
603 output template but rather a piece of C program that should compute a
604 template. It should execute a @code{return} statement to return the
605 template-string you want. Most such templates use C string literals, which
606 require doublequote characters to delimit them. To include these
607 doublequote characters in the string, prefix each one with @samp{\}.
609 If the output control string is written as a brace block instead of a
610 double-quoted string, it is automatically assumed to be C code. In that
611 case, it is not necessary to put in a leading asterisk, or to escape the
612 doublequotes surrounding C string literals.
614 The operands may be found in the array @code{operands}, whose C data type
617 It is very common to select different ways of generating assembler code
618 based on whether an immediate operand is within a certain range. Be
619 careful when doing this, because the result of @code{INTVAL} is an
620 integer on the host machine. If the host machine has more bits in an
621 @code{int} than the target machine has in the mode in which the constant
622 will be used, then some of the bits you get from @code{INTVAL} will be
623 superfluous. For proper results, you must carefully disregard the
624 values of those bits.
626 @findex output_asm_insn
627 It is possible to output an assembler instruction and then go on to output
628 or compute more of them, using the subroutine @code{output_asm_insn}. This
629 receives two arguments: a template-string and a vector of operands. The
630 vector may be @code{operands}, or it may be another array of @code{rtx}
631 that you declare locally and initialize yourself.
633 @findex which_alternative
634 When an insn pattern has multiple alternatives in its constraints, often
635 the appearance of the assembler code is determined mostly by which alternative
636 was matched. When this is so, the C code can test the variable
637 @code{which_alternative}, which is the ordinal number of the alternative
638 that was actually satisfied (0 for the first, 1 for the second alternative,
641 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
642 for registers and @samp{clrmem} for memory locations. Here is how
643 a pattern could use @code{which_alternative} to choose between them:
647 [(set (match_operand:SI 0 "general_operand" "=r,m")
651 return (which_alternative == 0
652 ? "clrreg %0" : "clrmem %0");
656 The example above, where the assembler code to generate was
657 @emph{solely} determined by the alternative, could also have been specified
658 as follows, having the output control string start with a @samp{@@}:
663 [(set (match_operand:SI 0 "general_operand" "=r,m")
672 If you just need a little bit of C code in one (or a few) alternatives,
673 you can use @samp{*} inside of a @samp{@@} multi-alternative template:
678 [(set (match_operand:SI 0 "general_operand" "=r,<,m")
683 * return stack_mem_p (operands[0]) ? \"push 0\" : \"clrmem %0\";
691 @cindex operand predicates
692 @cindex operator predicates
694 A predicate determines whether a @code{match_operand} or
695 @code{match_operator} expression matches, and therefore whether the
696 surrounding instruction pattern will be used for that combination of
697 operands. GCC has a number of machine-independent predicates, and you
698 can define machine-specific predicates as needed. By convention,
699 predicates used with @code{match_operand} have names that end in
700 @samp{_operand}, and those used with @code{match_operator} have names
701 that end in @samp{_operator}.
703 All predicates are Boolean functions (in the mathematical sense) of
704 two arguments: the RTL expression that is being considered at that
705 position in the instruction pattern, and the machine mode that the
706 @code{match_operand} or @code{match_operator} specifies. In this
707 section, the first argument is called @var{op} and the second argument
708 @var{mode}. Predicates can be called from C as ordinary two-argument
709 functions; this can be useful in output templates or other
710 machine-specific code.
712 Operand predicates can allow operands that are not actually acceptable
713 to the hardware, as long as the constraints give reload the ability to
714 fix them up (@pxref{Constraints}). However, GCC will usually generate
715 better code if the predicates specify the requirements of the machine
716 instructions as closely as possible. Reload cannot fix up operands
717 that must be constants (``immediate operands''); you must use a
718 predicate that allows only constants, or else enforce the requirement
719 in the extra condition.
721 @cindex predicates and machine modes
722 @cindex normal predicates
723 @cindex special predicates
724 Most predicates handle their @var{mode} argument in a uniform manner.
725 If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have
726 any mode. If @var{mode} is anything else, then @var{op} must have the
727 same mode, unless @var{op} is a @code{CONST_INT} or integer
728 @code{CONST_DOUBLE}. These RTL expressions always have
729 @code{VOIDmode}, so it would be counterproductive to check that their
730 mode matches. Instead, predicates that accept @code{CONST_INT} and/or
731 integer @code{CONST_DOUBLE} check that the value stored in the
732 constant will fit in the requested mode.
734 Predicates with this behavior are called @dfn{normal}.
735 @command{genrecog} can optimize the instruction recognizer based on
736 knowledge of how normal predicates treat modes. It can also diagnose
737 certain kinds of common errors in the use of normal predicates; for
738 instance, it is almost always an error to use a normal predicate
739 without specifying a mode.
741 Predicates that do something different with their @var{mode} argument
742 are called @dfn{special}. The generic predicates
743 @code{address_operand} and @code{pmode_register_operand} are special
744 predicates. @command{genrecog} does not do any optimizations or
745 diagnosis when special predicates are used.
748 * Machine-Independent Predicates:: Predicates available to all back ends.
749 * Defining Predicates:: How to write machine-specific predicate
753 @node Machine-Independent Predicates
754 @subsection Machine-Independent Predicates
755 @cindex machine-independent predicates
756 @cindex generic predicates
758 These are the generic predicates available to all back ends. They are
759 defined in @file{recog.c}. The first category of predicates allow
760 only constant, or @dfn{immediate}, operands.
762 @defun immediate_operand
763 This predicate allows any sort of constant that fits in @var{mode}.
764 It is an appropriate choice for instructions that take operands that
768 @defun const_int_operand
769 This predicate allows any @code{CONST_INT} expression that fits in
770 @var{mode}. It is an appropriate choice for an immediate operand that
771 does not allow a symbol or label.
774 @defun const_double_operand
775 This predicate accepts any @code{CONST_DOUBLE} expression that has
776 exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also
777 accept @code{CONST_INT}. It is intended for immediate floating point
782 The second category of predicates allow only some kind of machine
785 @defun register_operand
786 This predicate allows any @code{REG} or @code{SUBREG} expression that
787 is valid for @var{mode}. It is often suitable for arithmetic
788 instruction operands on a RISC machine.
791 @defun pmode_register_operand
792 This is a slight variant on @code{register_operand} which works around
793 a limitation in the machine-description reader.
796 (match_operand @var{n} "pmode_register_operand" @var{constraint})
803 (match_operand:P @var{n} "register_operand" @var{constraint})
807 would mean, if the machine-description reader accepted @samp{:P}
808 mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an
809 alias for some other mode, and might vary with machine-specific
810 options. @xref{Misc}.
813 @defun scratch_operand
814 This predicate allows hard registers and @code{SCRATCH} expressions,
815 but not pseudo-registers. It is used internally by @code{match_scratch};
816 it should not be used directly.
820 The third category of predicates allow only some kind of memory reference.
822 @defun memory_operand
823 This predicate allows any valid reference to a quantity of mode
824 @var{mode} in memory, as determined by the weak form of
825 @code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}).
828 @defun address_operand
829 This predicate is a little unusual; it allows any operand that is a
830 valid expression for the @emph{address} of a quantity of mode
831 @var{mode}, again determined by the weak form of
832 @code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if
833 @samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to
834 @code{memory_operand}, then @var{exp} is acceptable to
835 @code{address_operand}. Note that @var{exp} does not necessarily have
839 @defun indirect_operand
840 This is a stricter form of @code{memory_operand} which allows only
841 memory references with a @code{general_operand} as the address
842 expression. New uses of this predicate are discouraged, because
843 @code{general_operand} is very permissive, so it's hard to tell what
844 an @code{indirect_operand} does or does not allow. If a target has
845 different requirements for memory operands for different instructions,
846 it is better to define target-specific predicates which enforce the
847 hardware's requirements explicitly.
851 This predicate allows a memory reference suitable for pushing a value
852 onto the stack. This will be a @code{MEM} which refers to
853 @code{stack_pointer_rtx}, with a side-effect in its address expression
854 (@pxref{Incdec}); which one is determined by the
855 @code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}).
859 This predicate allows a memory reference suitable for popping a value
860 off the stack. Again, this will be a @code{MEM} referring to
861 @code{stack_pointer_rtx}, with a side-effect in its address
862 expression. However, this time @code{STACK_POP_CODE} is expected.
866 The fourth category of predicates allow some combination of the above
869 @defun nonmemory_operand
870 This predicate allows any immediate or register operand valid for @var{mode}.
873 @defun nonimmediate_operand
874 This predicate allows any register or memory operand valid for @var{mode}.
877 @defun general_operand
878 This predicate allows any immediate, register, or memory operand
879 valid for @var{mode}.
883 Finally, there are two generic operator predicates.
885 @defun comparison_operator
886 This predicate matches any expression which performs an arithmetic
887 comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the
891 @defun ordered_comparison_operator
892 This predicate matches any expression which performs an arithmetic
893 comparison in @var{mode} and whose expression code is valid for integer
894 modes; that is, the expression code will be one of @code{eq}, @code{ne},
895 @code{lt}, @code{ltu}, @code{le}, @code{leu}, @code{gt}, @code{gtu},
896 @code{ge}, @code{geu}.
899 @node Defining Predicates
900 @subsection Defining Machine-Specific Predicates
901 @cindex defining predicates
902 @findex define_predicate
903 @findex define_special_predicate
905 Many machines have requirements for their operands that cannot be
906 expressed precisely using the generic predicates. You can define
907 additional predicates using @code{define_predicate} and
908 @code{define_special_predicate} expressions. These expressions have
913 The name of the predicate, as it will be referred to in
914 @code{match_operand} or @code{match_operator} expressions.
917 An RTL expression which evaluates to true if the predicate allows the
918 operand @var{op}, false if it does not. This expression can only use
919 the following RTL codes:
923 When written inside a predicate expression, a @code{MATCH_OPERAND}
924 expression evaluates to true if the predicate it names would allow
925 @var{op}. The operand number and constraint are ignored. Due to
926 limitations in @command{genrecog}, you can only refer to generic
927 predicates and predicates that have already been defined.
930 This expression evaluates to true if @var{op} or a specified
931 subexpression of @var{op} has one of a given list of RTX codes.
933 The first operand of this expression is a string constant containing a
934 comma-separated list of RTX code names (in lower case). These are the
935 codes for which the @code{MATCH_CODE} will be true.
937 The second operand is a string constant which indicates what
938 subexpression of @var{op} to examine. If it is absent or the empty
939 string, @var{op} itself is examined. Otherwise, the string constant
940 must be a sequence of digits and/or lowercase letters. Each character
941 indicates a subexpression to extract from the current expression; for
942 the first character this is @var{op}, for the second and subsequent
943 characters it is the result of the previous character. A digit
944 @var{n} extracts @samp{@w{XEXP (@var{e}, @var{n})}}; a letter @var{l}
945 extracts @samp{@w{XVECEXP (@var{e}, 0, @var{n})}} where @var{n} is the
946 alphabetic ordinal of @var{l} (0 for `a', 1 for 'b', and so on). The
947 @code{MATCH_CODE} then examines the RTX code of the subexpression
948 extracted by the complete string. It is not possible to extract
949 components of an @code{rtvec} that is not at position 0 within its RTX
953 This expression has one operand, a string constant containing a C
954 expression. The predicate's arguments, @var{op} and @var{mode}, are
955 available with those names in the C expression. The @code{MATCH_TEST}
956 evaluates to true if the C expression evaluates to a nonzero value.
957 @code{MATCH_TEST} expressions must not have side effects.
963 The basic @samp{MATCH_} expressions can be combined using these
964 logical operators, which have the semantics of the C operators
965 @samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively. As
966 in Common Lisp, you may give an @code{AND} or @code{IOR} expression an
967 arbitrary number of arguments; this has exactly the same effect as
968 writing a chain of two-argument @code{AND} or @code{IOR} expressions.
972 An optional block of C code, which should execute
973 @samp{@w{return true}} if the predicate is found to match and
974 @samp{@w{return false}} if it does not. It must not have any side
975 effects. The predicate arguments, @var{op} and @var{mode}, are
976 available with those names.
978 If a code block is present in a predicate definition, then the RTL
979 expression must evaluate to true @emph{and} the code block must
980 execute @samp{@w{return true}} for the predicate to allow the operand.
981 The RTL expression is evaluated first; do not re-check anything in the
982 code block that was checked in the RTL expression.
985 The program @command{genrecog} scans @code{define_predicate} and
986 @code{define_special_predicate} expressions to determine which RTX
987 codes are possibly allowed. You should always make this explicit in
988 the RTL predicate expression, using @code{MATCH_OPERAND} and
991 Here is an example of a simple predicate definition, from the IA64
996 ;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.}
997 (define_predicate "small_addr_symbolic_operand"
998 (and (match_code "symbol_ref")
999 (match_test "SYMBOL_REF_SMALL_ADDR_P (op)")))
1004 And here is another, showing the use of the C block.
1008 ;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.}
1009 (define_predicate "gr_register_operand"
1010 (match_operand 0 "register_operand")
1013 if (GET_CODE (op) == SUBREG)
1014 op = SUBREG_REG (op);
1017 return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
1022 Predicates written with @code{define_predicate} automatically include
1023 a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same
1024 mode as @var{mode}, or @var{op} is a @code{CONST_INT} or
1025 @code{CONST_DOUBLE}. They do @emph{not} check specifically for
1026 integer @code{CONST_DOUBLE}, nor do they test that the value of either
1027 kind of constant fits in the requested mode. This is because
1028 target-specific predicates that take constants usually have to do more
1029 stringent value checks anyway. If you need the exact same treatment
1030 of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates
1031 provide, use a @code{MATCH_OPERAND} subexpression to call
1032 @code{const_int_operand}, @code{const_double_operand}, or
1033 @code{immediate_operand}.
1035 Predicates written with @code{define_special_predicate} do not get any
1036 automatic mode checks, and are treated as having special mode handling
1037 by @command{genrecog}.
1039 The program @command{genpreds} is responsible for generating code to
1040 test predicates. It also writes a header file containing function
1041 declarations for all machine-specific predicates. It is not necessary
1042 to declare these predicates in @file{@var{cpu}-protos.h}.
1045 @c Most of this node appears by itself (in a different place) even
1046 @c when the INTERNALS flag is clear. Passages that require the internals
1047 @c manual's context are conditionalized to appear only in the internals manual.
1050 @section Operand Constraints
1051 @cindex operand constraints
1054 Each @code{match_operand} in an instruction pattern can specify
1055 constraints for the operands allowed. The constraints allow you to
1056 fine-tune matching within the set of operands allowed by the
1062 @section Constraints for @code{asm} Operands
1063 @cindex operand constraints, @code{asm}
1064 @cindex constraints, @code{asm}
1065 @cindex @code{asm} constraints
1067 Here are specific details on what constraint letters you can use with
1068 @code{asm} operands.
1070 Constraints can say whether
1071 an operand may be in a register, and which kinds of register; whether the
1072 operand can be a memory reference, and which kinds of address; whether the
1073 operand may be an immediate constant, and which possible values it may
1074 have. Constraints can also require two operands to match.
1075 Side-effects aren't allowed in operands of inline @code{asm}, unless
1076 @samp{<} or @samp{>} constraints are used, because there is no guarantee
1077 that the side-effects will happen exactly once in an instruction that can update
1078 the addressing register.
1082 * Simple Constraints:: Basic use of constraints.
1083 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1084 * Class Preferences:: Constraints guide which hard register to put things in.
1085 * Modifiers:: More precise control over effects of constraints.
1086 * Machine Constraints:: Existing constraints for some particular machines.
1087 * Disable Insn Alternatives:: Disable insn alternatives using attributes.
1088 * Define Constraints:: How to define machine-specific constraints.
1089 * C Constraint Interface:: How to test constraints from C code.
1095 * Simple Constraints:: Basic use of constraints.
1096 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1097 * Modifiers:: More precise control over effects of constraints.
1098 * Machine Constraints:: Special constraints for some particular machines.
1102 @node Simple Constraints
1103 @subsection Simple Constraints
1104 @cindex simple constraints
1106 The simplest kind of constraint is a string full of letters, each of
1107 which describes one kind of operand that is permitted. Here are
1108 the letters that are allowed:
1112 Whitespace characters are ignored and can be inserted at any position
1113 except the first. This enables each alternative for different operands to
1114 be visually aligned in the machine description even if they have different
1115 number of constraints and modifiers.
1117 @cindex @samp{m} in constraint
1118 @cindex memory references in constraints
1120 A memory operand is allowed, with any kind of address that the machine
1121 supports in general.
1122 Note that the letter used for the general memory constraint can be
1123 re-defined by a back end using the @code{TARGET_MEM_CONSTRAINT} macro.
1125 @cindex offsettable address
1126 @cindex @samp{o} in constraint
1128 A memory operand is allowed, but only if the address is
1129 @dfn{offsettable}. This means that adding a small integer (actually,
1130 the width in bytes of the operand, as determined by its machine mode)
1131 may be added to the address and the result is also a valid memory
1134 @cindex autoincrement/decrement addressing
1135 For example, an address which is constant is offsettable; so is an
1136 address that is the sum of a register and a constant (as long as a
1137 slightly larger constant is also within the range of address-offsets
1138 supported by the machine); but an autoincrement or autodecrement
1139 address is not offsettable. More complicated indirect/indexed
1140 addresses may or may not be offsettable depending on the other
1141 addressing modes that the machine supports.
1143 Note that in an output operand which can be matched by another
1144 operand, the constraint letter @samp{o} is valid only when accompanied
1145 by both @samp{<} (if the target machine has predecrement addressing)
1146 and @samp{>} (if the target machine has preincrement addressing).
1148 @cindex @samp{V} in constraint
1150 A memory operand that is not offsettable. In other words, anything that
1151 would fit the @samp{m} constraint but not the @samp{o} constraint.
1153 @cindex @samp{<} in constraint
1155 A memory operand with autodecrement addressing (either predecrement or
1156 postdecrement) is allowed. In inline @code{asm} this constraint is only
1157 allowed if the operand is used exactly once in an instruction that can
1158 handle the side-effects. Not using an operand with @samp{<} in constraint
1159 string in the inline @code{asm} pattern at all or using it in multiple
1160 instructions isn't valid, because the side-effects wouldn't be performed
1161 or would be performed more than once. Furthermore, on some targets
1162 the operand with @samp{<} in constraint string must be accompanied by
1163 special instruction suffixes like @code{%U0} instruction suffix on PowerPC
1164 or @code{%P0} on IA-64.
1166 @cindex @samp{>} in constraint
1168 A memory operand with autoincrement addressing (either preincrement or
1169 postincrement) is allowed. In inline @code{asm} the same restrictions
1170 as for @samp{<} apply.
1172 @cindex @samp{r} in constraint
1173 @cindex registers in constraints
1175 A register operand is allowed provided that it is in a general
1178 @cindex constants in constraints
1179 @cindex @samp{i} in constraint
1181 An immediate integer operand (one with constant value) is allowed.
1182 This includes symbolic constants whose values will be known only at
1183 assembly time or later.
1185 @cindex @samp{n} in constraint
1187 An immediate integer operand with a known numeric value is allowed.
1188 Many systems cannot support assembly-time constants for operands less
1189 than a word wide. Constraints for these operands should use @samp{n}
1190 rather than @samp{i}.
1192 @cindex @samp{I} in constraint
1193 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
1194 Other letters in the range @samp{I} through @samp{P} may be defined in
1195 a machine-dependent fashion to permit immediate integer operands with
1196 explicit integer values in specified ranges. For example, on the
1197 68000, @samp{I} is defined to stand for the range of values 1 to 8.
1198 This is the range permitted as a shift count in the shift
1201 @cindex @samp{E} in constraint
1203 An immediate floating operand (expression code @code{const_double}) is
1204 allowed, but only if the target floating point format is the same as
1205 that of the host machine (on which the compiler is running).
1207 @cindex @samp{F} in constraint
1209 An immediate floating operand (expression code @code{const_double} or
1210 @code{const_vector}) is allowed.
1212 @cindex @samp{G} in constraint
1213 @cindex @samp{H} in constraint
1214 @item @samp{G}, @samp{H}
1215 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
1216 permit immediate floating operands in particular ranges of values.
1218 @cindex @samp{s} in constraint
1220 An immediate integer operand whose value is not an explicit integer is
1223 This might appear strange; if an insn allows a constant operand with a
1224 value not known at compile time, it certainly must allow any known
1225 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
1226 better code to be generated.
1228 For example, on the 68000 in a fullword instruction it is possible to
1229 use an immediate operand; but if the immediate value is between @minus{}128
1230 and 127, better code results from loading the value into a register and
1231 using the register. This is because the load into the register can be
1232 done with a @samp{moveq} instruction. We arrange for this to happen
1233 by defining the letter @samp{K} to mean ``any integer outside the
1234 range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
1237 @cindex @samp{g} in constraint
1239 Any register, memory or immediate integer operand is allowed, except for
1240 registers that are not general registers.
1242 @cindex @samp{X} in constraint
1245 Any operand whatsoever is allowed, even if it does not satisfy
1246 @code{general_operand}. This is normally used in the constraint of
1247 a @code{match_scratch} when certain alternatives will not actually
1248 require a scratch register.
1251 Any operand whatsoever is allowed.
1254 @cindex @samp{0} in constraint
1255 @cindex digits in constraint
1256 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
1257 An operand that matches the specified operand number is allowed. If a
1258 digit is used together with letters within the same alternative, the
1259 digit should come last.
1261 This number is allowed to be more than a single digit. If multiple
1262 digits are encountered consecutively, they are interpreted as a single
1263 decimal integer. There is scant chance for ambiguity, since to-date
1264 it has never been desirable that @samp{10} be interpreted as matching
1265 either operand 1 @emph{or} operand 0. Should this be desired, one
1266 can use multiple alternatives instead.
1268 @cindex matching constraint
1269 @cindex constraint, matching
1270 This is called a @dfn{matching constraint} and what it really means is
1271 that the assembler has only a single operand that fills two roles
1273 considered separate in the RTL insn. For example, an add insn has two
1274 input operands and one output operand in the RTL, but on most CISC
1277 which @code{asm} distinguishes. For example, an add instruction uses
1278 two input operands and an output operand, but on most CISC
1280 machines an add instruction really has only two operands, one of them an
1281 input-output operand:
1287 Matching constraints are used in these circumstances.
1288 More precisely, the two operands that match must include one input-only
1289 operand and one output-only operand. Moreover, the digit must be a
1290 smaller number than the number of the operand that uses it in the
1294 For operands to match in a particular case usually means that they
1295 are identical-looking RTL expressions. But in a few special cases
1296 specific kinds of dissimilarity are allowed. For example, @code{*x}
1297 as an input operand will match @code{*x++} as an output operand.
1298 For proper results in such cases, the output template should always
1299 use the output-operand's number when printing the operand.
1302 @cindex load address instruction
1303 @cindex push address instruction
1304 @cindex address constraints
1305 @cindex @samp{p} in constraint
1307 An operand that is a valid memory address is allowed. This is
1308 for ``load address'' and ``push address'' instructions.
1310 @findex address_operand
1311 @samp{p} in the constraint must be accompanied by @code{address_operand}
1312 as the predicate in the @code{match_operand}. This predicate interprets
1313 the mode specified in the @code{match_operand} as the mode of the memory
1314 reference for which the address would be valid.
1316 @cindex other register constraints
1317 @cindex extensible constraints
1318 @item @var{other-letters}
1319 Other letters can be defined in machine-dependent fashion to stand for
1320 particular classes of registers or other arbitrary operand types.
1321 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
1322 for data, address and floating point registers.
1326 In order to have valid assembler code, each operand must satisfy
1327 its constraint. But a failure to do so does not prevent the pattern
1328 from applying to an insn. Instead, it directs the compiler to modify
1329 the code so that the constraint will be satisfied. Usually this is
1330 done by copying an operand into a register.
1332 Contrast, therefore, the two instruction patterns that follow:
1336 [(set (match_operand:SI 0 "general_operand" "=r")
1337 (plus:SI (match_dup 0)
1338 (match_operand:SI 1 "general_operand" "r")))]
1344 which has two operands, one of which must appear in two places, and
1348 [(set (match_operand:SI 0 "general_operand" "=r")
1349 (plus:SI (match_operand:SI 1 "general_operand" "0")
1350 (match_operand:SI 2 "general_operand" "r")))]
1356 which has three operands, two of which are required by a constraint to be
1357 identical. If we are considering an insn of the form
1360 (insn @var{n} @var{prev} @var{next}
1362 (plus:SI (reg:SI 6) (reg:SI 109)))
1367 the first pattern would not apply at all, because this insn does not
1368 contain two identical subexpressions in the right place. The pattern would
1369 say, ``That does not look like an add instruction; try other patterns''.
1370 The second pattern would say, ``Yes, that's an add instruction, but there
1371 is something wrong with it''. It would direct the reload pass of the
1372 compiler to generate additional insns to make the constraint true. The
1373 results might look like this:
1376 (insn @var{n2} @var{prev} @var{n}
1377 (set (reg:SI 3) (reg:SI 6))
1380 (insn @var{n} @var{n2} @var{next}
1382 (plus:SI (reg:SI 3) (reg:SI 109)))
1386 It is up to you to make sure that each operand, in each pattern, has
1387 constraints that can handle any RTL expression that could be present for
1388 that operand. (When multiple alternatives are in use, each pattern must,
1389 for each possible combination of operand expressions, have at least one
1390 alternative which can handle that combination of operands.) The
1391 constraints don't need to @emph{allow} any possible operand---when this is
1392 the case, they do not constrain---but they must at least point the way to
1393 reloading any possible operand so that it will fit.
1397 If the constraint accepts whatever operands the predicate permits,
1398 there is no problem: reloading is never necessary for this operand.
1400 For example, an operand whose constraints permit everything except
1401 registers is safe provided its predicate rejects registers.
1403 An operand whose predicate accepts only constant values is safe
1404 provided its constraints include the letter @samp{i}. If any possible
1405 constant value is accepted, then nothing less than @samp{i} will do;
1406 if the predicate is more selective, then the constraints may also be
1410 Any operand expression can be reloaded by copying it into a register.
1411 So if an operand's constraints allow some kind of register, it is
1412 certain to be safe. It need not permit all classes of registers; the
1413 compiler knows how to copy a register into another register of the
1414 proper class in order to make an instruction valid.
1416 @cindex nonoffsettable memory reference
1417 @cindex memory reference, nonoffsettable
1419 A nonoffsettable memory reference can be reloaded by copying the
1420 address into a register. So if the constraint uses the letter
1421 @samp{o}, all memory references are taken care of.
1424 A constant operand can be reloaded by allocating space in memory to
1425 hold it as preinitialized data. Then the memory reference can be used
1426 in place of the constant. So if the constraint uses the letters
1427 @samp{o} or @samp{m}, constant operands are not a problem.
1430 If the constraint permits a constant and a pseudo register used in an insn
1431 was not allocated to a hard register and is equivalent to a constant,
1432 the register will be replaced with the constant. If the predicate does
1433 not permit a constant and the insn is re-recognized for some reason, the
1434 compiler will crash. Thus the predicate must always recognize any
1435 objects allowed by the constraint.
1438 If the operand's predicate can recognize registers, but the constraint does
1439 not permit them, it can make the compiler crash. When this operand happens
1440 to be a register, the reload pass will be stymied, because it does not know
1441 how to copy a register temporarily into memory.
1443 If the predicate accepts a unary operator, the constraint applies to the
1444 operand. For example, the MIPS processor at ISA level 3 supports an
1445 instruction which adds two registers in @code{SImode} to produce a
1446 @code{DImode} result, but only if the registers are correctly sign
1447 extended. This predicate for the input operands accepts a
1448 @code{sign_extend} of an @code{SImode} register. Write the constraint
1449 to indicate the type of register that is required for the operand of the
1453 @node Multi-Alternative
1454 @subsection Multiple Alternative Constraints
1455 @cindex multiple alternative constraints
1457 Sometimes a single instruction has multiple alternative sets of possible
1458 operands. For example, on the 68000, a logical-or instruction can combine
1459 register or an immediate value into memory, or it can combine any kind of
1460 operand into a register; but it cannot combine one memory location into
1463 These constraints are represented as multiple alternatives. An alternative
1464 can be described by a series of letters for each operand. The overall
1465 constraint for an operand is made from the letters for this operand
1466 from the first alternative, a comma, the letters for this operand from
1467 the second alternative, a comma, and so on until the last alternative.
1469 Here is how it is done for fullword logical-or on the 68000:
1472 (define_insn "iorsi3"
1473 [(set (match_operand:SI 0 "general_operand" "=m,d")
1474 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1475 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1479 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1480 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1481 2. The second alternative has @samp{d} (data register) for operand 0,
1482 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1483 @samp{%} in the constraints apply to all the alternatives; their
1484 meaning is explained in the next section (@pxref{Class Preferences}).
1487 @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL
1488 If all the operands fit any one alternative, the instruction is valid.
1489 Otherwise, for each alternative, the compiler counts how many instructions
1490 must be added to copy the operands so that that alternative applies.
1491 The alternative requiring the least copying is chosen. If two alternatives
1492 need the same amount of copying, the one that comes first is chosen.
1493 These choices can be altered with the @samp{?} and @samp{!} characters:
1496 @cindex @samp{?} in constraint
1497 @cindex question mark
1499 Disparage slightly the alternative that the @samp{?} appears in,
1500 as a choice when no alternative applies exactly. The compiler regards
1501 this alternative as one unit more costly for each @samp{?} that appears
1504 @cindex @samp{!} in constraint
1505 @cindex exclamation point
1507 Disparage severely the alternative that the @samp{!} appears in.
1508 This alternative can still be used if it fits without reloading,
1509 but if reloading is needed, some other alternative will be used.
1511 @cindex @samp{^} in constraint
1514 This constraint is analogous to @samp{?} but it disparages slightly
1515 the alternative only if the operand with the @samp{?} needs a reload.
1517 @cindex @samp{$} in constraint
1520 This constraint is analogous to @samp{!} but it disparages severely
1521 the alternative only if the operand with the @samp{$} needs a reload.
1525 When an insn pattern has multiple alternatives in its constraints, often
1526 the appearance of the assembler code is determined mostly by which
1527 alternative was matched. When this is so, the C code for writing the
1528 assembler code can use the variable @code{which_alternative}, which is
1529 the ordinal number of the alternative that was actually satisfied (0 for
1530 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1534 @node Class Preferences
1535 @subsection Register Class Preferences
1536 @cindex class preference constraints
1537 @cindex register class preference constraints
1539 @cindex voting between constraint alternatives
1540 The operand constraints have another function: they enable the compiler
1541 to decide which kind of hardware register a pseudo register is best
1542 allocated to. The compiler examines the constraints that apply to the
1543 insns that use the pseudo register, looking for the machine-dependent
1544 letters such as @samp{d} and @samp{a} that specify classes of registers.
1545 The pseudo register is put in whichever class gets the most ``votes''.
1546 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1547 favor of a general register. The machine description says which registers
1548 are considered general.
1550 Of course, on some machines all registers are equivalent, and no register
1551 classes are defined. Then none of this complexity is relevant.
1555 @subsection Constraint Modifier Characters
1556 @cindex modifiers in constraints
1557 @cindex constraint modifier characters
1559 @c prevent bad page break with this line
1560 Here are constraint modifier characters.
1563 @cindex @samp{=} in constraint
1565 Means that this operand is written to by this instruction:
1566 the previous value is discarded and replaced by new data.
1568 @cindex @samp{+} in constraint
1570 Means that this operand is both read and written by the instruction.
1572 When the compiler fixes up the operands to satisfy the constraints,
1573 it needs to know which operands are read by the instruction and
1574 which are written by it. @samp{=} identifies an operand which is only
1575 written; @samp{+} identifies an operand that is both read and written; all
1576 other operands are assumed to only be read.
1578 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1579 first character of the constraint string.
1581 @cindex @samp{&} in constraint
1582 @cindex earlyclobber operand
1584 Means (in a particular alternative) that this operand is an
1585 @dfn{earlyclobber} operand, which is written before the instruction is
1586 finished using the input operands. Therefore, this operand may not lie
1587 in a register that is read by the instruction or as part of any memory
1590 @samp{&} applies only to the alternative in which it is written. In
1591 constraints with multiple alternatives, sometimes one alternative
1592 requires @samp{&} while others do not. See, for example, the
1593 @samp{movdf} insn of the 68000.
1595 A operand which is read by the instruction can be tied to an earlyclobber
1596 operand if its only use as an input occurs before the early result is
1597 written. Adding alternatives of this form often allows GCC to produce
1598 better code when only some of the read operands can be affected by the
1599 earlyclobber. See, for example, the @samp{mulsi3} insn of the ARM@.
1601 Furthermore, if the @dfn{earlyclobber} operand is also a read/write
1602 operand, then that operand is written only after it's used.
1604 @samp{&} does not obviate the need to write @samp{=} or @samp{+}. As
1605 @dfn{earlyclobber} operands are always written, a read-only
1606 @dfn{earlyclobber} operand is ill-formed and will be rejected by the
1609 @cindex @samp{%} in constraint
1611 Declares the instruction to be commutative for this operand and the
1612 following operand. This means that the compiler may interchange the
1613 two operands if that is the cheapest way to make all operands fit the
1614 constraints. @samp{%} applies to all alternatives and must appear as
1615 the first character in the constraint. Only read-only operands can use
1619 This is often used in patterns for addition instructions
1620 that really have only two operands: the result must go in one of the
1621 arguments. Here for example, is how the 68000 halfword-add
1622 instruction is defined:
1625 (define_insn "addhi3"
1626 [(set (match_operand:HI 0 "general_operand" "=m,r")
1627 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1628 (match_operand:HI 2 "general_operand" "di,g")))]
1632 GCC can only handle one commutative pair in an asm; if you use more,
1633 the compiler may fail. Note that you need not use the modifier if
1634 the two alternatives are strictly identical; this would only waste
1635 time in the reload pass. The modifier is not operational after
1636 register allocation, so the result of @code{define_peephole2}
1637 and @code{define_split}s performed after reload cannot rely on
1638 @samp{%} to make the intended insn match.
1640 @cindex @samp{#} in constraint
1642 Says that all following characters, up to the next comma, are to be
1643 ignored as a constraint. They are significant only for choosing
1644 register preferences.
1646 @cindex @samp{*} in constraint
1648 Says that the following character should be ignored when choosing
1649 register preferences. @samp{*} has no effect on the meaning of the
1650 constraint as a constraint, and no effect on reloading. For LRA
1651 @samp{*} additionally disparages slightly the alternative if the
1652 following character matches the operand.
1655 Here is an example: the 68000 has an instruction to sign-extend a
1656 halfword in a data register, and can also sign-extend a value by
1657 copying it into an address register. While either kind of register is
1658 acceptable, the constraints on an address-register destination are
1659 less strict, so it is best if register allocation makes an address
1660 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1661 constraint letter (for data register) is ignored when computing
1662 register preferences.
1665 (define_insn "extendhisi2"
1666 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1668 (match_operand:HI 1 "general_operand" "0,g")))]
1674 @node Machine Constraints
1675 @subsection Constraints for Particular Machines
1676 @cindex machine specific constraints
1677 @cindex constraints, machine specific
1679 Whenever possible, you should use the general-purpose constraint letters
1680 in @code{asm} arguments, since they will convey meaning more readily to
1681 people reading your code. Failing that, use the constraint letters
1682 that usually have very similar meanings across architectures. The most
1683 commonly used constraints are @samp{m} and @samp{r} (for memory and
1684 general-purpose registers respectively; @pxref{Simple Constraints}), and
1685 @samp{I}, usually the letter indicating the most common
1686 immediate-constant format.
1688 Each architecture defines additional constraints. These constraints
1689 are used by the compiler itself for instruction generation, as well as
1690 for @code{asm} statements; therefore, some of the constraints are not
1691 particularly useful for @code{asm}. Here is a summary of some of the
1692 machine-dependent constraints available on some particular machines;
1693 it includes both constraints that are useful for @code{asm} and
1694 constraints that aren't. The compiler source file mentioned in the
1695 table heading for each architecture is the definitive reference for
1696 the meanings of that architecture's constraints.
1698 @c Please keep this table alphabetized by target!
1700 @item AArch64 family---@file{config/aarch64/constraints.md}
1703 The stack pointer register (@code{SP})
1706 Floating point or SIMD vector register
1709 Integer constant that is valid as an immediate operand in an @code{ADD}
1713 Integer constant that is valid as an immediate operand in a @code{SUB}
1714 instruction (once negated)
1717 Integer constant that can be used with a 32-bit logical instruction
1720 Integer constant that can be used with a 64-bit logical instruction
1723 Integer constant that is valid as an immediate operand in a 32-bit @code{MOV}
1724 pseudo instruction. The @code{MOV} may be assembled to one of several different
1725 machine instructions depending on the value
1728 Integer constant that is valid as an immediate operand in a 64-bit @code{MOV}
1732 An absolute symbolic address or a label reference
1735 Floating point constant zero
1738 Integer constant zero
1741 The high part (bits 12 and upwards) of the pc-relative address of a symbol
1742 within 4GB of the instruction
1745 A memory address which uses a single base register with no offset
1748 A memory address suitable for a load/store pair instruction in SI, DI, SF and
1754 @item ARC ---@file{config/arc/constraints.md}
1757 Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
1758 @code{r12}-@code{r15}. This constraint can only match when the @option{-mq}
1759 option is in effect.
1762 Registers usable as base-regs of memory addresses in ARCompact 16-bit memory
1763 instructions: @code{r0}-@code{r3}, @code{r12}-@code{r15}, @code{sp}.
1764 This constraint can only match when the @option{-mq}
1765 option is in effect.
1767 ARC FPX (dpfp) 64-bit registers. @code{D0}, @code{D1}.
1770 A signed 12-bit integer constant.
1773 constant for arithmetic/logical operations. This might be any constant
1774 that can be put into a long immediate by the assmbler or linker without
1775 involving a PIC relocation.
1778 A 3-bit unsigned integer constant.
1781 A 6-bit unsigned integer constant.
1784 One's complement of a 6-bit unsigned integer constant.
1787 Two's complement of a 6-bit unsigned integer constant.
1790 A 5-bit unsigned integer constant.
1793 A 7-bit unsigned integer constant.
1796 A 8-bit unsigned integer constant.
1799 Any const_double value.
1802 @item ARM family---@file{config/arm/constraints.md}
1806 In Thumb state, the core registers @code{r8}-@code{r15}.
1809 The stack pointer register.
1812 In Thumb State the core registers @code{r0}-@code{r7}. In ARM state this
1813 is an alias for the @code{r} constraint.
1816 VFP floating-point registers @code{s0}-@code{s31}. Used for 32 bit values.
1819 VFP floating-point registers @code{d0}-@code{d31} and the appropriate
1820 subset @code{d0}-@code{d15} based on command line options.
1821 Used for 64 bit values only. Not valid for Thumb1.
1824 The iWMMX co-processor registers.
1827 The iWMMX GR registers.
1830 The floating-point constant 0.0
1833 Integer that is valid as an immediate operand in a data processing
1834 instruction. That is, an integer in the range 0 to 255 rotated by a
1838 Integer in the range @minus{}4095 to 4095
1841 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1844 Integer that satisfies constraint @samp{I} when negated (twos complement)
1847 Integer in the range 0 to 32
1850 A memory reference where the exact address is in a single register
1851 (`@samp{m}' is preferable for @code{asm} statements)
1854 An item in the constant pool
1857 A symbol in the text segment of the current file
1860 A memory reference suitable for VFP load/store insns (reg+constant offset)
1863 A memory reference suitable for iWMMXt load/store instructions.
1866 A memory reference suitable for the ARMv4 ldrsb instruction.
1869 @item AVR family---@file{config/avr/constraints.md}
1872 Registers from r0 to r15
1875 Registers from r16 to r23
1878 Registers from r16 to r31
1881 Registers from r24 to r31. These registers can be used in @samp{adiw} command
1884 Pointer register (r26--r31)
1887 Base pointer register (r28--r31)
1890 Stack pointer register (SPH:SPL)
1893 Temporary register r0
1896 Register pair X (r27:r26)
1899 Register pair Y (r29:r28)
1902 Register pair Z (r31:r30)
1905 Constant greater than @minus{}1, less than 64
1908 Constant greater than @minus{}64, less than 1
1917 Constant that fits in 8 bits
1920 Constant integer @minus{}1
1923 Constant integer 8, 16, or 24
1929 A floating point constant 0.0
1932 A memory address based on Y or Z pointer with displacement.
1935 @item Blackfin family---@file{config/bfin/constraints.md}
1944 A call clobbered P register.
1947 A single register. If @var{n} is in the range 0 to 7, the corresponding D
1948 register. If it is @code{A}, then the register P0.
1951 Even-numbered D register
1954 Odd-numbered D register
1957 Accumulator register.
1960 Even-numbered accumulator register.
1963 Odd-numbered accumulator register.
1975 Registers used for circular buffering, i.e. I, B, or L registers.
1990 Any D, P, B, M, I or L register.
1993 Additional registers typically used only in prologues and epilogues: RETS,
1994 RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
1997 Any register except accumulators or CC.
2000 Signed 16 bit integer (in the range @minus{}32768 to 32767)
2003 Unsigned 16 bit integer (in the range 0 to 65535)
2006 Signed 7 bit integer (in the range @minus{}64 to 63)
2009 Unsigned 7 bit integer (in the range 0 to 127)
2012 Unsigned 5 bit integer (in the range 0 to 31)
2015 Signed 4 bit integer (in the range @minus{}8 to 7)
2018 Signed 3 bit integer (in the range @minus{}3 to 4)
2021 Unsigned 3 bit integer (in the range 0 to 7)
2024 Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4.
2027 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2028 use with either accumulator.
2031 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2032 use only with accumulator A1.
2041 An integer constant with exactly a single bit set.
2044 An integer constant with all bits set except exactly one.
2052 @item CR16 Architecture---@file{config/cr16/cr16.h}
2056 Registers from r0 to r14 (registers without stack pointer)
2059 Register from r0 to r11 (all 16-bit registers)
2062 Register from r12 to r15 (all 32-bit registers)
2065 Signed constant that fits in 4 bits
2068 Signed constant that fits in 5 bits
2071 Signed constant that fits in 6 bits
2074 Unsigned constant that fits in 4 bits
2077 Signed constant that fits in 32 bits
2080 Check for 64 bits wide constants for add/sub instructions
2083 Floating point constant that is legal for store immediate
2086 @item Epiphany---@file{config/epiphany/constraints.md}
2089 An unsigned 16-bit constant.
2092 An unsigned 5-bit constant.
2095 A signed 11-bit constant.
2098 A signed 11-bit constant added to @minus{}1.
2099 Can only match when the @option{-m1reg-@var{reg}} option is active.
2102 Left-shift of @minus{}1, i.e., a bit mask with a block of leading ones, the rest
2103 being a block of trailing zeroes.
2104 Can only match when the @option{-m1reg-@var{reg}} option is active.
2107 Right-shift of @minus{}1, i.e., a bit mask with a trailing block of ones, the
2108 rest being zeroes. Or to put it another way, one less than a power of two.
2109 Can only match when the @option{-m1reg-@var{reg}} option is active.
2112 Constant for arithmetic/logical operations.
2113 This is like @code{i}, except that for position independent code,
2114 no symbols / expressions needing relocations are allowed.
2117 Symbolic constant for call/jump instruction.
2120 The register class usable in short insns. This is a register class
2121 constraint, and can thus drive register allocation.
2122 This constraint won't match unless @option{-mprefer-short-insn-regs} is
2126 The the register class of registers that can be used to hold a
2127 sibcall call address. I.e., a caller-saved register.
2130 Core control register class.
2133 The register group usable in short insns.
2134 This constraint does not use a register class, so that it only
2135 passively matches suitable registers, and doesn't drive register allocation.
2139 Constant suitable for the addsi3_r pattern. This is a valid offset
2140 For byte, halfword, or word addressing.
2144 Matches the return address if it can be replaced with the link register.
2147 Matches the integer condition code register.
2150 Matches the return address if it is in a stack slot.
2153 Matches control register values to switch fp mode, which are encapsulated in
2154 @code{UNSPEC_FP_MODE}.
2157 @item FRV---@file{config/frv/frv.h}
2160 Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
2163 Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
2166 Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
2167 @code{icc0} to @code{icc3}).
2170 Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
2173 Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
2174 Odd registers are excluded not in the class but through the use of a machine
2175 mode larger than 4 bytes.
2178 Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
2181 Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
2182 Odd registers are excluded not in the class but through the use of a machine
2183 mode larger than 4 bytes.
2186 Register in the class @code{LR_REG} (the @code{lr} register).
2189 Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
2190 Register numbers not divisible by 4 are excluded not in the class but through
2191 the use of a machine mode larger than 8 bytes.
2194 Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
2197 Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
2200 Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
2203 Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
2206 Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
2207 Register numbers not divisible by 4 are excluded not in the class but through
2208 the use of a machine mode larger than 8 bytes.
2211 Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
2214 Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
2217 Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
2220 Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
2223 Floating point constant zero
2226 6-bit signed integer constant
2229 10-bit signed integer constant
2232 16-bit signed integer constant
2235 16-bit unsigned integer constant
2238 12-bit signed integer constant that is negative---i.e.@: in the
2239 range of @minus{}2048 to @minus{}1
2245 12-bit signed integer constant that is greater than zero---i.e.@: in the
2250 @item Hewlett-Packard PA-RISC---@file{config/pa/pa.h}
2256 Floating point register
2259 Shift amount register
2262 Floating point register (deprecated)
2265 Upper floating point register (32-bit), floating point register (64-bit)
2271 Signed 11-bit integer constant
2274 Signed 14-bit integer constant
2277 Integer constant that can be deposited with a @code{zdepi} instruction
2280 Signed 5-bit integer constant
2286 Integer constant that can be loaded with a @code{ldil} instruction
2289 Integer constant whose value plus one is a power of 2
2292 Integer constant that can be used for @code{and} operations in @code{depi}
2293 and @code{extru} instructions
2302 Floating-point constant 0.0
2305 A @code{lo_sum} data-linkage-table memory operand
2308 A memory operand that can be used as the destination operand of an
2309 integer store instruction
2312 A scaled or unscaled indexed memory operand
2315 A memory operand for floating-point loads and stores
2318 A register indirect memory operand
2321 @item Intel IA-64---@file{config/ia64/ia64.h}
2324 General register @code{r0} to @code{r3} for @code{addl} instruction
2330 Predicate register (@samp{c} as in ``conditional'')
2333 Application register residing in M-unit
2336 Application register residing in I-unit
2339 Floating-point register
2342 Memory operand. If used together with @samp{<} or @samp{>},
2343 the operand can have postincrement and postdecrement which
2344 require printing with @samp{%Pn} on IA-64.
2347 Floating-point constant 0.0 or 1.0
2350 14-bit signed integer constant
2353 22-bit signed integer constant
2356 8-bit signed integer constant for logical instructions
2359 8-bit adjusted signed integer constant for compare pseudo-ops
2362 6-bit unsigned integer constant for shift counts
2365 9-bit signed integer constant for load and store postincrements
2371 0 or @minus{}1 for @code{dep} instruction
2374 Non-volatile memory for floating-point loads and stores
2377 Integer constant in the range 1 to 4 for @code{shladd} instruction
2380 Memory operand except postincrement and postdecrement. This is
2381 now roughly the same as @samp{m} when not used together with @samp{<}
2385 @item M32C---@file{config/m32c/m32c.c}
2390 @samp{$sp}, @samp{$fb}, @samp{$sb}.
2393 Any control register, when they're 16 bits wide (nothing if control
2394 registers are 24 bits wide)
2397 Any control register, when they're 24 bits wide.
2406 $r0 or $r2, or $r2r0 for 32 bit values.
2409 $r1 or $r3, or $r3r1 for 32 bit values.
2412 A register that can hold a 64 bit value.
2415 $r0 or $r1 (registers with addressable high/low bytes)
2424 Address registers when they're 16 bits wide.
2427 Address registers when they're 24 bits wide.
2430 Registers that can hold QI values.
2433 Registers that can be used with displacements ($a0, $a1, $sb).
2436 Registers that can hold 32 bit values.
2439 Registers that can hold 16 bit values.
2442 Registers chat can hold 16 bit values, including all control
2446 $r0 through R1, plus $a0 and $a1.
2452 The memory-based pseudo-registers $mem0 through $mem15.
2455 Registers that can hold pointers (16 bit registers for r8c, m16c; 24
2456 bit registers for m32cm, m32c).
2459 Matches multiple registers in a PARALLEL to form a larger register.
2460 Used to match function return values.
2466 @minus{}128 @dots{} 127
2469 @minus{}32768 @dots{} 32767
2475 @minus{}8 @dots{} @minus{}1 or 1 @dots{} 8
2478 @minus{}16 @dots{} @minus{}1 or 1 @dots{} 16
2481 @minus{}32 @dots{} @minus{}1 or 1 @dots{} 32
2484 @minus{}65536 @dots{} @minus{}1
2487 An 8 bit value with exactly one bit set.
2490 A 16 bit value with exactly one bit set.
2493 The common src/dest memory addressing modes.
2496 Memory addressed using $a0 or $a1.
2499 Memory addressed with immediate addresses.
2502 Memory addressed using the stack pointer ($sp).
2505 Memory addressed using the frame base register ($fb).
2508 Memory addressed using the small base register ($sb).
2514 @item MeP---@file{config/mep/constraints.md}
2524 Any control register.
2527 Either the $hi or the $lo register.
2530 Coprocessor registers that can be directly loaded ($c0-$c15).
2533 Coprocessor registers that can be moved to each other.
2536 Coprocessor registers that can be moved to core registers.
2548 Registers which can be used in $tp-relative addressing.
2554 The coprocessor registers.
2557 The coprocessor control registers.
2563 User-defined register set A.
2566 User-defined register set B.
2569 User-defined register set C.
2572 User-defined register set D.
2575 Offsets for $gp-rel addressing.
2578 Constants that can be used directly with boolean insns.
2581 Constants that can be moved directly to registers.
2584 Small constants that can be added to registers.
2590 Small constants that can be compared to registers.
2593 Constants that can be loaded into the top half of registers.
2596 Signed 8-bit immediates.
2599 Symbols encoded for $tp-rel or $gp-rel addressing.
2602 Non-constant addresses for loading/saving coprocessor registers.
2605 The top half of a symbol's value.
2608 A register indirect address without offset.
2611 Symbolic references to the control bus.
2615 @item MicroBlaze---@file{config/microblaze/constraints.md}
2618 A general register (@code{r0} to @code{r31}).
2621 A status register (@code{rmsr}, @code{$fcc1} to @code{$fcc7}).
2625 @item MIPS---@file{config/mips/constraints.md}
2628 An address register. This is equivalent to @code{r} unless
2629 generating MIPS16 code.
2632 A floating-point register (if available).
2635 Formerly the @code{hi} register. This constraint is no longer supported.
2638 The @code{lo} register. Use this register to store values that are
2639 no bigger than a word.
2642 The concatenated @code{hi} and @code{lo} registers. Use this register
2643 to store doubleword values.
2646 A register suitable for use in an indirect jump. This will always be
2647 @code{$25} for @option{-mabicalls}.
2650 Register @code{$3}. Do not use this constraint in new code;
2651 it is retained only for compatibility with glibc.
2654 Equivalent to @code{r}; retained for backwards compatibility.
2657 A floating-point condition code register.
2660 A signed 16-bit constant (for arithmetic instructions).
2666 An unsigned 16-bit constant (for logic instructions).
2669 A signed 32-bit constant in which the lower 16 bits are zero.
2670 Such constants can be loaded using @code{lui}.
2673 A constant that cannot be loaded using @code{lui}, @code{addiu}
2677 A constant in the range @minus{}65535 to @minus{}1 (inclusive).
2680 A signed 15-bit constant.
2683 A constant in the range 1 to 65535 (inclusive).
2686 Floating-point zero.
2689 An address that can be used in a non-macro load or store.
2692 A memory operand whose address is formed by a base register and offset
2693 that is suitable for use in instructions with the same addressing mode
2694 as @code{ll} and @code{sc}.
2697 An address suitable for a @code{prefetch} instruction, or for any other
2698 instruction with the same addressing mode as @code{prefetch}.
2701 @item Motorola 680x0---@file{config/m68k/constraints.md}
2710 68881 floating-point register, if available
2713 Integer in the range 1 to 8
2716 16-bit signed number
2719 Signed number whose magnitude is greater than 0x80
2722 Integer in the range @minus{}8 to @minus{}1
2725 Signed number whose magnitude is greater than 0x100
2728 Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate
2731 16 (for rotate using swap)
2734 Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate
2737 Numbers that mov3q can handle
2740 Floating point constant that is not a 68881 constant
2743 Operands that satisfy 'm' when -mpcrel is in effect
2746 Operands that satisfy 's' when -mpcrel is not in effect
2749 Address register indirect addressing mode
2752 Register offset addressing
2767 Range of signed numbers that don't fit in 16 bits
2770 Integers valid for mvq
2773 Integers valid for a moveq followed by a swap
2776 Integers valid for mvz
2779 Integers valid for mvs
2785 Non-register operands allowed in clr
2789 @item Moxie---@file{config/moxie/constraints.md}
2798 A register indirect memory operand
2801 A constant in the range of 0 to 255.
2804 A constant in the range of 0 to @minus{}255.
2808 @item MSP430--@file{config/msp430/constraints.md}
2821 Integer constant -1^20..1^19.
2824 Integer constant 1-4.
2827 Memory references which do not require an extended MOVX instruction.
2830 Memory reference, labels only.
2833 Memory reference, stack only.
2837 @item NDS32---@file{config/nds32/constraints.md}
2840 LOW register class $r0 to $r7 constraint for V3/V3M ISA.
2842 LOW register class $r0 to $r7.
2844 MIDDLE register class $r0 to $r11, $r16 to $r19.
2846 HIGH register class $r12 to $r14, $r20 to $r31.
2848 Temporary assist register $ta (i.e.@: $r15).
2852 Unsigned immediate 3-bit value.
2854 Negative immediate 3-bit value in the range of @minus{}7--0.
2856 Unsigned immediate 4-bit value.
2858 Signed immediate 5-bit value.
2860 Unsigned immediate 5-bit value.
2862 Negative immediate 5-bit value in the range of @minus{}31--0.
2864 Unsigned immediate 5-bit value for movpi45 instruction with range 16--47.
2866 Unsigned immediate 6-bit value constraint for addri36.sp instruction.
2868 Unsigned immediate 8-bit value.
2870 Unsigned immediate 9-bit value.
2872 Signed immediate 10-bit value.
2874 Signed immediate 11-bit value.
2876 Signed immediate 15-bit value.
2878 Unsigned immediate 15-bit value.
2880 A constant which is not in the range of imm15u but ok for bclr instruction.
2882 A constant which is not in the range of imm15u but ok for bset instruction.
2884 A constant which is not in the range of imm15u but ok for btgl instruction.
2886 A constant whose compliment value is in the range of imm15u
2887 and ok for bitci instruction.
2889 Signed immediate 16-bit value.
2891 Signed immediate 17-bit value.
2893 Signed immediate 19-bit value.
2895 Signed immediate 20-bit value.
2897 The immediate value that can be simply set high 20-bit.
2899 The immediate value 0xff.
2901 The immediate value 0xffff.
2903 The immediate value 0x01.
2905 The immediate value 0x7ff.
2907 The immediate value with power of 2.
2909 The immediate value with power of 2 minus 1.
2911 Memory constraint for 333 format.
2913 Memory constraint for 45 format.
2915 Memory constraint for 37 format.
2918 @item Nios II family---@file{config/nios2/constraints.md}
2922 Integer that is valid as an immediate operand in an
2923 instruction taking a signed 16-bit number. Range
2924 @minus{}32768 to 32767.
2927 Integer that is valid as an immediate operand in an
2928 instruction taking an unsigned 16-bit number. Range
2932 Integer that is valid as an immediate operand in an
2933 instruction taking only the upper 16-bits of a
2934 32-bit number. Range 32-bit numbers with the lower
2938 Integer that is valid as an immediate operand for a
2939 shift instruction. Range 0 to 31.
2942 Integer that is valid as an immediate operand for
2943 only the value 0. Can be used in conjunction with
2944 the format modifier @code{z} to use @code{r0}
2945 instead of @code{0} in the assembly output.
2948 Integer that is valid as an immediate operand for
2949 a custom instruction opcode. Range 0 to 255.
2952 Matches immediates which are addresses in the small
2953 data section and therefore can be added to @code{gp}
2954 as a 16-bit immediate to re-create their 32-bit value.
2958 A @code{const} wrapped @code{UNSPEC} expression,
2959 representing a supported PIC or TLS relocation.
2964 @item PDP-11---@file{config/pdp11/constraints.md}
2967 Floating point registers AC0 through AC3. These can be loaded from/to
2968 memory with a single instruction.
2971 Odd numbered general registers (R1, R3, R5). These are used for
2972 16-bit multiply operations.
2975 Any of the floating point registers (AC0 through AC5).
2978 Floating point constant 0.
2981 An integer constant that fits in 16 bits.
2984 An integer constant whose low order 16 bits are zero.
2987 An integer constant that does not meet the constraints for codes
2988 @samp{I} or @samp{J}.
2991 The integer constant 1.
2994 The integer constant @minus{}1.
2997 The integer constant 0.
3000 Integer constants @minus{}4 through @minus{}1 and 1 through 4; shifts by these
3001 amounts are handled as multiple single-bit shifts rather than a single
3002 variable-length shift.
3005 A memory reference which requires an additional word (address or
3006 offset) after the opcode.
3009 A memory reference that is encoded within the opcode.
3013 @item PowerPC and IBM RS6000---@file{config/rs6000/constraints.md}
3016 Address base register
3019 Floating point register (containing 64-bit value)
3022 Floating point register (containing 32-bit value)
3025 Altivec vector register
3028 Any VSX register if the -mvsx option was used or NO_REGS.
3031 VSX vector register to hold vector double data or NO_REGS.
3034 VSX vector register to hold vector float data or NO_REGS.
3037 If @option{-mmfpgpr} was used, a floating point register or NO_REGS.
3040 Floating point register if direct moves are available, or NO_REGS.
3043 FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.
3046 FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.
3049 FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.
3052 Floating point register if the LFIWAX instruction is enabled or NO_REGS.
3055 VSX register if direct move instructions are enabled, or NO_REGS.
3058 No register (NO_REGS).
3061 General purpose register if 64-bit instructions are enabled or NO_REGS.
3064 VSX vector register to hold scalar double values or NO_REGS.
3067 VSX vector register to hold 128 bit integer or NO_REGS.
3070 Altivec register to use for float/32-bit int loads/stores or NO_REGS.
3073 Altivec register to use for double loads/stores or NO_REGS.
3076 FP or VSX register to perform float operations under @option{-mvsx} or NO_REGS.
3079 Floating point register if the STFIWX instruction is enabled or NO_REGS.
3082 FP or VSX register to perform ISA 2.07 float ops or NO_REGS.
3085 Floating point register if the LFIWZX instruction is enabled or NO_REGS.
3088 Int constant that is the element number of the 64-bit scalar in a vector.
3091 A memory address that will work with the @code{lq} and @code{stq}
3095 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
3104 @samp{LINK} register
3107 @samp{CR} register (condition register) number 0
3110 @samp{CR} register (condition register)
3113 @samp{XER[CA]} carry bit (part of the XER register)
3116 Signed 16-bit constant
3119 Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
3120 @code{SImode} constants)
3123 Unsigned 16-bit constant
3126 Signed 16-bit constant shifted left 16 bits
3129 Constant larger than 31
3138 Constant whose negation is a signed 16-bit constant
3141 Floating point constant that can be loaded into a register with one
3142 instruction per word
3145 Integer/Floating point constant that can be loaded into a register using
3150 Normally, @code{m} does not allow addresses that update the base register.
3151 If @samp{<} or @samp{>} constraint is also used, they are allowed and
3152 therefore on PowerPC targets in that case it is only safe
3153 to use @samp{m<>} in an @code{asm} statement if that @code{asm} statement
3154 accesses the operand exactly once. The @code{asm} statement must also
3155 use @samp{%U@var{<opno>}} as a placeholder for the ``update'' flag in the
3156 corresponding load or store instruction. For example:
3159 asm ("st%U0 %1,%0" : "=m<>" (mem) : "r" (val));
3165 asm ("st %1,%0" : "=m<>" (mem) : "r" (val));
3171 A ``stable'' memory operand; that is, one which does not include any
3172 automodification of the base register. This used to be useful when
3173 @samp{m} allowed automodification of the base register, but as those are now only
3174 allowed when @samp{<} or @samp{>} is used, @samp{es} is basically the same
3175 as @samp{m} without @samp{<} and @samp{>}.
3178 Memory operand that is an offset from a register (it is usually better
3179 to use @samp{m} or @samp{es} in @code{asm} statements)
3182 Memory operand that is an indexed or indirect from a register (it is
3183 usually better to use @samp{m} or @samp{es} in @code{asm} statements)
3189 Address operand that is an indexed or indirect from a register (@samp{p} is
3190 preferable for @code{asm} statements)
3193 Constant suitable as a 64-bit mask operand
3196 Constant suitable as a 32-bit mask operand
3199 System V Release 4 small data area reference
3202 AND masks that can be performed by two rldic@{l, r@} instructions
3205 Vector constant that does not require memory
3208 Vector constant that is all zeros.
3212 @item RL78---@file{config/rl78/constraints.md}
3216 An integer constant in the range 1 @dots{} 7.
3218 An integer constant in the range 0 @dots{} 255.
3220 An integer constant in the range @minus{}255 @dots{} 0
3222 The integer constant 1.
3224 The integer constant -1.
3226 The integer constant 0.
3228 The integer constant 2.
3230 The integer constant -2.
3232 An integer constant in the range 1 @dots{} 15.
3234 The built-in compare types--eq, ne, gtu, ltu, geu, and leu.
3236 The synthetic compare types--gt, lt, ge, and le.
3238 A memory reference with an absolute address.
3240 A memory reference using @code{BC} as a base register, with an optional offset.
3242 A memory reference using @code{AX}, @code{BC}, @code{DE}, or @code{HL} for the address, for calls.
3244 A memory reference using any 16-bit register pair for the address, for calls.
3246 A memory reference using @code{DE} as a base register, with an optional offset.
3248 A memory reference using @code{DE} as a base register, without any offset.
3250 Any memory reference to an address in the far address space.
3252 A memory reference using @code{HL} as a base register, with an optional one-byte offset.
3254 A memory reference using @code{HL} as a base register, with @code{B} or @code{C} as the index register.
3256 A memory reference using @code{HL} as a base register, without any offset.
3258 A memory reference using @code{SP} as a base register, with an optional one-byte offset.
3260 Any memory reference to an address in the near address space.
3262 The @code{AX} register.
3264 The @code{BC} register.
3266 The @code{DE} register.
3268 @code{A} through @code{L} registers.
3270 The @code{SP} register.
3272 The @code{HL} register.
3274 The 16-bit @code{R8} register.
3276 The 16-bit @code{R10} register.
3278 The registers reserved for interrupts (@code{R24} to @code{R31}).
3280 The @code{A} register.
3282 The @code{B} register.
3284 The @code{C} register.
3286 The @code{D} register.
3288 The @code{E} register.
3290 The @code{H} register.
3292 The @code{L} register.
3294 The virtual registers.
3296 The @code{PSW} register.
3298 The @code{X} register.
3302 @item RX---@file{config/rx/constraints.md}
3305 An address which does not involve register indirect addressing or
3306 pre/post increment/decrement addressing.
3312 A constant in the range @minus{}256 to 255, inclusive.
3315 A constant in the range @minus{}128 to 127, inclusive.
3318 A constant in the range @minus{}32768 to 32767, inclusive.
3321 A constant in the range @minus{}8388608 to 8388607, inclusive.
3324 A constant in the range 0 to 15, inclusive.
3328 @item S/390 and zSeries---@file{config/s390/s390.h}
3331 Address register (general purpose register except r0)
3334 Condition code register
3337 Data register (arbitrary general purpose register)
3340 Floating-point register
3343 Unsigned 8-bit constant (0--255)
3346 Unsigned 12-bit constant (0--4095)
3349 Signed 16-bit constant (@minus{}32768--32767)
3352 Value appropriate as displacement.
3355 for short displacement
3356 @item (@minus{}524288..524287)
3357 for long displacement
3361 Constant integer with a value of 0x7fffffff.
3364 Multiple letter constraint followed by 4 parameter letters.
3367 number of the part counting from most to least significant
3371 mode of the containing operand
3373 value of the other parts (F---all bits set)
3375 The constraint matches if the specified part of a constant
3376 has a value different from its other parts.
3379 Memory reference without index register and with short displacement.
3382 Memory reference with index register and short displacement.
3385 Memory reference without index register but with long displacement.
3388 Memory reference with index register and long displacement.
3391 Pointer with short displacement.
3394 Pointer with long displacement.
3397 Shift count operand.
3402 @item SPARC---@file{config/sparc/sparc.h}
3405 Floating-point register on the SPARC-V8 architecture and
3406 lower floating-point register on the SPARC-V9 architecture.
3409 Floating-point register. It is equivalent to @samp{f} on the
3410 SPARC-V8 architecture and contains both lower and upper
3411 floating-point registers on the SPARC-V9 architecture.
3414 Floating-point condition code register.
3417 Lower floating-point register. It is only valid on the SPARC-V9
3418 architecture when the Visual Instruction Set is available.
3421 Floating-point register. It is only valid on the SPARC-V9 architecture
3422 when the Visual Instruction Set is available.
3425 64-bit global or out register for the SPARC-V8+ architecture.
3428 The constant all-ones, for floating-point.
3431 Signed 5-bit constant
3437 Signed 13-bit constant
3443 32-bit constant with the low 12 bits clear (a constant that can be
3444 loaded with the @code{sethi} instruction)
3447 A constant in the range supported by @code{movcc} instructions (11-bit
3451 A constant in the range supported by @code{movrcc} instructions (10-bit
3455 Same as @samp{K}, except that it verifies that bits that are not in the
3456 lower 32-bit range are all zero. Must be used instead of @samp{K} for
3457 modes wider than @code{SImode}
3466 Signed 13-bit constant, sign-extended to 32 or 64 bits
3472 Floating-point constant whose integral representation can
3473 be moved into an integer register using a single sethi
3477 Floating-point constant whose integral representation can
3478 be moved into an integer register using a single mov
3482 Floating-point constant whose integral representation can
3483 be moved into an integer register using a high/lo_sum
3484 instruction sequence
3487 Memory address aligned to an 8-byte boundary
3493 Memory address for @samp{e} constraint registers
3496 Memory address with only a base register
3503 @item SPU---@file{config/spu/spu.h}
3506 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
3509 An immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
3512 An immediate for the @code{iohl} instruction. const_int is treated as a 64 bit value.
3515 An immediate which can be loaded with @code{fsmbi}.
3518 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
3521 An immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
3524 An immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
3527 An immediate for the @code{iohl} instruction. const_int is treated as a 32 bit value.
3530 A constant in the range [@minus{}64, 63] for shift/rotate instructions.
3533 An unsigned 7-bit constant for conversion/nop/channel instructions.
3536 A signed 10-bit constant for most arithmetic instructions.
3539 A signed 16 bit immediate for @code{stop}.
3542 An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}.
3545 An unsigned 7-bit constant whose 3 least significant bits are 0.
3548 An unsigned 3-bit constant for 16-byte rotates and shifts
3551 Call operand, reg, for indirect calls
3554 Call operand, symbol, for relative calls.
3557 Call operand, const_int, for absolute calls.
3560 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
3563 An immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
3566 An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
3569 An immediate for the @code{iohl} instruction. const_int is sign extended to 128 bit.
3573 @item TI C6X family---@file{config/c6x/constraints.md}
3576 Register file A (A0--A31).
3579 Register file B (B0--B31).
3582 Predicate registers in register file A (A0--A2 on C64X and
3583 higher, A1 and A2 otherwise).
3586 Predicate registers in register file B (B0--B2).
3589 A call-used register in register file B (B0--B9, B16--B31).
3592 Register file A, excluding predicate registers (A3--A31,
3593 plus A0 if not C64X or higher).
3596 Register file B, excluding predicate registers (B3--B31).
3599 Integer constant in the range 0 @dots{} 15.
3602 Integer constant in the range 0 @dots{} 31.
3605 Integer constant in the range @minus{}31 @dots{} 0.
3608 Integer constant in the range @minus{}16 @dots{} 15.
3611 Integer constant that can be the operand of an ADDA or a SUBA insn.
3614 Integer constant in the range 0 @dots{} 65535.
3617 Integer constant in the range @minus{}32768 @dots{} 32767.
3620 Integer constant in the range @math{-2^{20}} @dots{} @math{2^{20} - 1}.
3623 Integer constant that is a valid mask for the clr instruction.
3626 Integer constant that is a valid mask for the set instruction.
3629 Memory location with A base register.
3632 Memory location with B base register.
3636 On C64x+ targets, a GP-relative small data reference.
3639 Any kind of @code{SYMBOL_REF}, for use in a call address.
3642 Any kind of immediate operand, unless it matches the S0 constraint.
3645 Memory location with B base register, but not using a long offset.
3648 A memory operand with an address that can't be used in an unaligned access.
3652 Register B14 (aka DP).
3656 @item TILE-Gx---@file{config/tilegx/constraints.md}
3669 Each of these represents a register constraint for an individual
3670 register, from r0 to r10.
3673 Signed 8-bit integer constant.
3676 Signed 16-bit integer constant.
3679 Unsigned 16-bit integer constant.
3682 Integer constant that fits in one signed byte when incremented by one
3683 (@minus{}129 @dots{} 126).
3686 Memory operand. If used together with @samp{<} or @samp{>}, the
3687 operand can have postincrement which requires printing with @samp{%In}
3688 and @samp{%in} on TILE-Gx. For example:
3691 asm ("st_add %I0,%1,%i0" : "=m<>" (*mem) : "r" (val));
3695 A bit mask suitable for the BFINS instruction.
3698 Integer constant that is a byte tiled out eight times.
3701 The integer zero constant.
3704 Integer constant that is a sign-extended byte tiled out as four shorts.
3707 Integer constant that fits in one signed byte when incremented
3708 (@minus{}129 @dots{} 126), but excluding -1.
3711 Integer constant that has all 1 bits consecutive and starting at bit 0.
3714 A 16-bit fragment of a got, tls, or pc-relative reference.
3717 Memory operand except postincrement. This is roughly the same as
3718 @samp{m} when not used together with @samp{<} or @samp{>}.
3721 An 8-element vector constant with identical elements.
3724 A 4-element vector constant with identical elements.
3727 The integer constant 0xffffffff.
3730 The integer constant 0xffffffff00000000.
3734 @item TILEPro---@file{config/tilepro/constraints.md}
3747 Each of these represents a register constraint for an individual
3748 register, from r0 to r10.
3751 Signed 8-bit integer constant.
3754 Signed 16-bit integer constant.
3757 Nonzero integer constant with low 16 bits zero.
3760 Integer constant that fits in one signed byte when incremented by one
3761 (@minus{}129 @dots{} 126).
3764 Memory operand. If used together with @samp{<} or @samp{>}, the
3765 operand can have postincrement which requires printing with @samp{%In}
3766 and @samp{%in} on TILEPro. For example:
3769 asm ("swadd %I0,%1,%i0" : "=m<>" (mem) : "r" (val));
3773 A bit mask suitable for the MM instruction.
3776 Integer constant that is a byte tiled out four times.
3779 The integer zero constant.
3782 Integer constant that is a sign-extended byte tiled out as two shorts.
3785 Integer constant that fits in one signed byte when incremented
3786 (@minus{}129 @dots{} 126), but excluding -1.
3789 A symbolic operand, or a 16-bit fragment of a got, tls, or pc-relative
3793 Memory operand except postincrement. This is roughly the same as
3794 @samp{m} when not used together with @samp{<} or @samp{>}.
3797 A 4-element vector constant with identical elements.
3800 A 2-element vector constant with identical elements.
3804 @item Visium---@file{config/visium/constraints.md}
3807 EAM register @code{mdb}
3810 EAM register @code{mdc}
3813 Floating point register
3817 Register for sibcall optimization
3821 General register, but not @code{r29}, @code{r30} and @code{r31}
3833 Floating-point constant 0.0
3836 Integer constant in the range 0 .. 65535 (16-bit immediate)
3839 Integer constant in the range 1 .. 31 (5-bit immediate)
3842 Integer constant in the range @minus{}65535 .. @minus{}1 (16-bit negative immediate)
3845 Integer constant @minus{}1
3854 @item x86 family---@file{config/i386/constraints.md}
3857 Legacy register---the eight integer registers available on all
3858 i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
3859 @code{si}, @code{di}, @code{bp}, @code{sp}).
3862 Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a},
3863 @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.
3866 Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
3867 @code{c}, and @code{d}.
3871 Any register that can be used as the index in a base+index memory
3872 access: that is, any general register except the stack pointer.
3876 The @code{a} register.
3879 The @code{b} register.
3882 The @code{c} register.
3885 The @code{d} register.
3888 The @code{si} register.
3891 The @code{di} register.
3894 The @code{a} and @code{d} registers. This class is used for instructions
3895 that return double word results in the @code{ax:dx} register pair. Single
3896 word values will be allocated either in @code{ax} or @code{dx}.
3897 For example on i386 the following implements @code{rdtsc}:
3900 unsigned long long rdtsc (void)
3902 unsigned long long tick;
3903 __asm__ __volatile__("rdtsc":"=A"(tick));
3908 This is not correct on x86-64 as it would allocate tick in either @code{ax}
3909 or @code{dx}. You have to use the following variant instead:
3912 unsigned long long rdtsc (void)
3914 unsigned int tickl, tickh;
3915 __asm__ __volatile__("rdtsc":"=a"(tickl),"=d"(tickh));
3916 return ((unsigned long long)tickh << 32)|tickl;
3922 Any 80387 floating-point (stack) register.
3925 Top of 80387 floating-point stack (@code{%st(0)}).
3928 Second from top of 80387 floating-point stack (@code{%st(1)}).
3937 First SSE register (@code{%xmm0}).
3941 Any SSE register, when SSE2 is enabled.
3944 Any SSE register, when SSE2 and inter-unit moves are enabled.
3947 Any MMX register, when inter-unit moves are enabled.
3951 Integer constant in the range 0 @dots{} 31, for 32-bit shifts.
3954 Integer constant in the range 0 @dots{} 63, for 64-bit shifts.
3957 Signed 8-bit integer constant.
3960 @code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move.
3963 0, 1, 2, or 3 (shifts for the @code{lea} instruction).
3966 Unsigned 8-bit integer constant (for @code{in} and @code{out}
3971 Integer constant in the range 0 @dots{} 127, for 128-bit shifts.
3975 Standard 80387 floating point constant.
3978 Standard SSE floating point constant.
3981 32-bit signed integer constant, or a symbolic reference known
3982 to fit that range (for immediate operands in sign-extending x86-64
3986 32-bit unsigned integer constant, or a symbolic reference known
3987 to fit that range (for immediate operands in zero-extending x86-64
3992 @item Xstormy16---@file{config/stormy16/stormy16.h}
4007 Registers r0 through r7.
4010 Registers r0 and r1.
4016 Registers r8 and r9.
4019 A constant between 0 and 3 inclusive.
4022 A constant that has exactly one bit set.
4025 A constant that has exactly one bit clear.
4028 A constant between 0 and 255 inclusive.
4031 A constant between @minus{}255 and 0 inclusive.
4034 A constant between @minus{}3 and 0 inclusive.
4037 A constant between 1 and 4 inclusive.
4040 A constant between @minus{}4 and @minus{}1 inclusive.
4043 A memory reference that is a stack push.
4046 A memory reference that is a stack pop.
4049 A memory reference that refers to a constant address of known value.
4052 The register indicated by Rx (not implemented yet).
4055 A constant that is not between 2 and 15 inclusive.
4062 @item Xtensa---@file{config/xtensa/constraints.md}
4065 General-purpose 32-bit register
4068 One-bit boolean register
4071 MAC16 40-bit accumulator register
4074 Signed 12-bit integer constant, for use in MOVI instructions
4077 Signed 8-bit integer constant, for use in ADDI instructions
4080 Integer constant valid for BccI instructions
4083 Unsigned constant valid for BccUI instructions
4090 @node Disable Insn Alternatives
4091 @subsection Disable insn alternatives using the @code{enabled} attribute
4094 There are three insn attributes that may be used to selectively disable
4095 instruction alternatives:
4099 Says whether an alternative is available on the current subtarget.
4101 @item preferred_for_size
4102 Says whether an enabled alternative should be used in code that is
4105 @item preferred_for_speed
4106 Says whether an enabled alternative should be used in code that is
4107 optimized for speed.
4110 All these attributes should use @code{(const_int 1)} to allow an alternative
4111 or @code{(const_int 0)} to disallow it. The attributes must be a static
4112 property of the subtarget; they cannot for example depend on the
4113 current operands, on the current optimization level, on the location
4114 of the insn within the body of a loop, on whether register allocation
4115 has finished, or on the current compiler pass.
4117 The @code{enabled} attribute is a correctness property. It tells GCC to act
4118 as though the disabled alternatives were never defined in the first place.
4119 This is useful when adding new instructions to an existing pattern in
4120 cases where the new instructions are only available for certain cpu
4121 architecture levels (typically mapped to the @code{-march=} command-line
4124 In contrast, the @code{preferred_for_size} and @code{preferred_for_speed}
4125 attributes are strong optimization hints rather than correctness properties.
4126 @code{preferred_for_size} tells GCC which alternatives to consider when
4127 adding or modifying an instruction that GCC wants to optimize for size.
4128 @code{preferred_for_speed} does the same thing for speed. Note that things
4129 like code motion can lead to cases where code optimized for size uses
4130 alternatives that are not preferred for size, and similarly for speed.
4132 Although @code{define_insn}s can in principle specify the @code{enabled}
4133 attribute directly, it is often clearer to have subsiduary attributes
4134 for each architectural feature of interest. The @code{define_insn}s
4135 can then use these subsiduary attributes to say which alternatives
4136 require which features. The example below does this for @code{cpu_facility}.
4138 E.g. the following two patterns could easily be merged using the @code{enabled}
4143 (define_insn "*movdi_old"
4144 [(set (match_operand:DI 0 "register_operand" "=d")
4145 (match_operand:DI 1 "register_operand" " d"))]
4149 (define_insn "*movdi_new"
4150 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
4151 (match_operand:DI 1 "register_operand" " d,d,f"))]
4164 (define_insn "*movdi_combined"
4165 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
4166 (match_operand:DI 1 "register_operand" " d,d,f"))]
4172 [(set_attr "cpu_facility" "*,new,new")])
4176 with the @code{enabled} attribute defined like this:
4180 (define_attr "cpu_facility" "standard,new" (const_string "standard"))
4182 (define_attr "enabled" ""
4183 (cond [(eq_attr "cpu_facility" "standard") (const_int 1)
4184 (and (eq_attr "cpu_facility" "new")
4185 (ne (symbol_ref "TARGET_NEW") (const_int 0)))
4194 @node Define Constraints
4195 @subsection Defining Machine-Specific Constraints
4196 @cindex defining constraints
4197 @cindex constraints, defining
4199 Machine-specific constraints fall into two categories: register and
4200 non-register constraints. Within the latter category, constraints
4201 which allow subsets of all possible memory or address operands should
4202 be specially marked, to give @code{reload} more information.
4204 Machine-specific constraints can be given names of arbitrary length,
4205 but they must be entirely composed of letters, digits, underscores
4206 (@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they
4207 must begin with a letter or underscore.
4209 In order to avoid ambiguity in operand constraint strings, no
4210 constraint can have a name that begins with any other constraint's
4211 name. For example, if @code{x} is defined as a constraint name,
4212 @code{xy} may not be, and vice versa. As a consequence of this rule,
4213 no constraint may begin with one of the generic constraint letters:
4214 @samp{E F V X g i m n o p r s}.
4216 Register constraints correspond directly to register classes.
4217 @xref{Register Classes}. There is thus not much flexibility in their
4220 @deffn {MD Expression} define_register_constraint name regclass docstring
4221 All three arguments are string constants.
4222 @var{name} is the name of the constraint, as it will appear in
4223 @code{match_operand} expressions. If @var{name} is a multi-letter
4224 constraint its length shall be the same for all constraints starting
4225 with the same letter. @var{regclass} can be either the
4226 name of the corresponding register class (@pxref{Register Classes}),
4227 or a C expression which evaluates to the appropriate register class.
4228 If it is an expression, it must have no side effects, and it cannot
4229 look at the operand. The usual use of expressions is to map some
4230 register constraints to @code{NO_REGS} when the register class
4231 is not available on a given subarchitecture.
4233 @var{docstring} is a sentence documenting the meaning of the
4234 constraint. Docstrings are explained further below.
4237 Non-register constraints are more like predicates: the constraint
4238 definition gives a Boolean expression which indicates whether the
4241 @deffn {MD Expression} define_constraint name docstring exp
4242 The @var{name} and @var{docstring} arguments are the same as for
4243 @code{define_register_constraint}, but note that the docstring comes
4244 immediately after the name for these expressions. @var{exp} is an RTL
4245 expression, obeying the same rules as the RTL expressions in predicate
4246 definitions. @xref{Defining Predicates}, for details. If it
4247 evaluates true, the constraint matches; if it evaluates false, it
4248 doesn't. Constraint expressions should indicate which RTL codes they
4249 might match, just like predicate expressions.
4251 @code{match_test} C expressions have access to the
4252 following variables:
4256 The RTL object defining the operand.
4258 The machine mode of @var{op}.
4260 @samp{INTVAL (@var{op})}, if @var{op} is a @code{const_int}.
4262 @samp{CONST_DOUBLE_HIGH (@var{op})}, if @var{op} is an integer
4263 @code{const_double}.
4265 @samp{CONST_DOUBLE_LOW (@var{op})}, if @var{op} is an integer
4266 @code{const_double}.
4268 @samp{CONST_DOUBLE_REAL_VALUE (@var{op})}, if @var{op} is a floating-point
4269 @code{const_double}.
4272 The @var{*val} variables should only be used once another piece of the
4273 expression has verified that @var{op} is the appropriate kind of RTL
4277 Most non-register constraints should be defined with
4278 @code{define_constraint}. The remaining two definition expressions
4279 are only appropriate for constraints that should be handled specially
4280 by @code{reload} if they fail to match.
4282 @deffn {MD Expression} define_memory_constraint name docstring exp
4283 Use this expression for constraints that match a subset of all memory
4284 operands: that is, @code{reload} can make them match by converting the
4285 operand to the form @samp{@w{(mem (reg @var{X}))}}, where @var{X} is a
4286 base register (from the register class specified by
4287 @code{BASE_REG_CLASS}, @pxref{Register Classes}).
4289 For example, on the S/390, some instructions do not accept arbitrary
4290 memory references, but only those that do not make use of an index
4291 register. The constraint letter @samp{Q} is defined to represent a
4292 memory address of this type. If @samp{Q} is defined with
4293 @code{define_memory_constraint}, a @samp{Q} constraint can handle any
4294 memory operand, because @code{reload} knows it can simply copy the
4295 memory address into a base register if required. This is analogous to
4296 the way an @samp{o} constraint can handle any memory operand.
4298 The syntax and semantics are otherwise identical to
4299 @code{define_constraint}.
4302 @deffn {MD Expression} define_address_constraint name docstring exp
4303 Use this expression for constraints that match a subset of all address
4304 operands: that is, @code{reload} can make the constraint match by
4305 converting the operand to the form @samp{@w{(reg @var{X})}}, again
4306 with @var{X} a base register.
4308 Constraints defined with @code{define_address_constraint} can only be
4309 used with the @code{address_operand} predicate, or machine-specific
4310 predicates that work the same way. They are treated analogously to
4311 the generic @samp{p} constraint.
4313 The syntax and semantics are otherwise identical to
4314 @code{define_constraint}.
4317 For historical reasons, names beginning with the letters @samp{G H}
4318 are reserved for constraints that match only @code{const_double}s, and
4319 names beginning with the letters @samp{I J K L M N O P} are reserved
4320 for constraints that match only @code{const_int}s. This may change in
4321 the future. For the time being, constraints with these names must be
4322 written in a stylized form, so that @code{genpreds} can tell you did
4327 (define_constraint "[@var{GHIJKLMNOP}]@dots{}"
4329 (and (match_code "const_int") ; @r{@code{const_double} for G/H}
4330 @var{condition}@dots{})) ; @r{usually a @code{match_test}}
4333 @c the semicolons line up in the formatted manual
4335 It is fine to use names beginning with other letters for constraints
4336 that match @code{const_double}s or @code{const_int}s.
4338 Each docstring in a constraint definition should be one or more complete
4339 sentences, marked up in Texinfo format. @emph{They are currently unused.}
4340 In the future they will be copied into the GCC manual, in @ref{Machine
4341 Constraints}, replacing the hand-maintained tables currently found in
4342 that section. Also, in the future the compiler may use this to give
4343 more helpful diagnostics when poor choice of @code{asm} constraints
4344 causes a reload failure.
4346 If you put the pseudo-Texinfo directive @samp{@@internal} at the
4347 beginning of a docstring, then (in the future) it will appear only in
4348 the internals manual's version of the machine-specific constraint tables.
4349 Use this for constraints that should not appear in @code{asm} statements.
4351 @node C Constraint Interface
4352 @subsection Testing constraints from C
4353 @cindex testing constraints
4354 @cindex constraints, testing
4356 It is occasionally useful to test a constraint from C code rather than
4357 implicitly via the constraint string in a @code{match_operand}. The
4358 generated file @file{tm_p.h} declares a few interfaces for working
4359 with constraints. At present these are defined for all constraints
4360 except @code{g} (which is equivalent to @code{general_operand}).
4362 Some valid constraint names are not valid C identifiers, so there is a
4363 mangling scheme for referring to them from C@. Constraint names that
4364 do not contain angle brackets or underscores are left unchanged.
4365 Underscores are doubled, each @samp{<} is replaced with @samp{_l}, and
4366 each @samp{>} with @samp{_g}. Here are some examples:
4368 @c the @c's prevent double blank lines in the printed manual.
4370 @multitable {Original} {Mangled}
4371 @item @strong{Original} @tab @strong{Mangled} @c
4372 @item @code{x} @tab @code{x} @c
4373 @item @code{P42x} @tab @code{P42x} @c
4374 @item @code{P4_x} @tab @code{P4__x} @c
4375 @item @code{P4>x} @tab @code{P4_gx} @c
4376 @item @code{P4>>} @tab @code{P4_g_g} @c
4377 @item @code{P4_g>} @tab @code{P4__g_g} @c
4381 Throughout this section, the variable @var{c} is either a constraint
4382 in the abstract sense, or a constant from @code{enum constraint_num};
4383 the variable @var{m} is a mangled constraint name (usually as part of
4384 a larger identifier).
4386 @deftp Enum constraint_num
4387 For each constraint except @code{g}, there is a corresponding
4388 enumeration constant: @samp{CONSTRAINT_} plus the mangled name of the
4389 constraint. Functions that take an @code{enum constraint_num} as an
4390 argument expect one of these constants.
4393 @deftypefun {inline bool} satisfies_constraint_@var{m} (rtx @var{exp})
4394 For each non-register constraint @var{m} except @code{g}, there is
4395 one of these functions; it returns @code{true} if @var{exp} satisfies the
4396 constraint. These functions are only visible if @file{rtl.h} was included
4397 before @file{tm_p.h}.
4400 @deftypefun bool constraint_satisfied_p (rtx @var{exp}, enum constraint_num @var{c})
4401 Like the @code{satisfies_constraint_@var{m}} functions, but the
4402 constraint to test is given as an argument, @var{c}. If @var{c}
4403 specifies a register constraint, this function will always return
4407 @deftypefun {enum reg_class} reg_class_for_constraint (enum constraint_num @var{c})
4408 Returns the register class associated with @var{c}. If @var{c} is not
4409 a register constraint, or those registers are not available for the
4410 currently selected subtarget, returns @code{NO_REGS}.
4413 Here is an example use of @code{satisfies_constraint_@var{m}}. In
4414 peephole optimizations (@pxref{Peephole Definitions}), operand
4415 constraint strings are ignored, so if there are relevant constraints,
4416 they must be tested in the C condition. In the example, the
4417 optimization is applied if operand 2 does @emph{not} satisfy the
4418 @samp{K} constraint. (This is a simplified version of a peephole
4419 definition from the i386 machine description.)
4423 [(match_scratch:SI 3 "r")
4424 (set (match_operand:SI 0 "register_operand" "")
4425 (mult:SI (match_operand:SI 1 "memory_operand" "")
4426 (match_operand:SI 2 "immediate_operand" "")))]
4428 "!satisfies_constraint_K (operands[2])"
4430 [(set (match_dup 3) (match_dup 1))
4431 (set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))]
4436 @node Standard Names
4437 @section Standard Pattern Names For Generation
4438 @cindex standard pattern names
4439 @cindex pattern names
4440 @cindex names, pattern
4442 Here is a table of the instruction names that are meaningful in the RTL
4443 generation pass of the compiler. Giving one of these names to an
4444 instruction pattern tells the RTL generation pass that it can use the
4445 pattern to accomplish a certain task.
4448 @cindex @code{mov@var{m}} instruction pattern
4449 @item @samp{mov@var{m}}
4450 Here @var{m} stands for a two-letter machine mode name, in lowercase.
4451 This instruction pattern moves data with that machine mode from operand
4452 1 to operand 0. For example, @samp{movsi} moves full-word data.
4454 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
4455 own mode is wider than @var{m}, the effect of this instruction is
4456 to store the specified value in the part of the register that corresponds
4457 to mode @var{m}. Bits outside of @var{m}, but which are within the
4458 same target word as the @code{subreg} are undefined. Bits which are
4459 outside the target word are left unchanged.
4461 This class of patterns is special in several ways. First of all, each
4462 of these names up to and including full word size @emph{must} be defined,
4463 because there is no other way to copy a datum from one place to another.
4464 If there are patterns accepting operands in larger modes,
4465 @samp{mov@var{m}} must be defined for integer modes of those sizes.
4467 Second, these patterns are not used solely in the RTL generation pass.
4468 Even the reload pass can generate move insns to copy values from stack
4469 slots into temporary registers. When it does so, one of the operands is
4470 a hard register and the other is an operand that can need to be reloaded
4474 Therefore, when given such a pair of operands, the pattern must generate
4475 RTL which needs no reloading and needs no temporary registers---no
4476 registers other than the operands. For example, if you support the
4477 pattern with a @code{define_expand}, then in such a case the
4478 @code{define_expand} mustn't call @code{force_reg} or any other such
4479 function which might generate new pseudo registers.
4481 This requirement exists even for subword modes on a RISC machine where
4482 fetching those modes from memory normally requires several insns and
4483 some temporary registers.
4485 @findex change_address
4486 During reload a memory reference with an invalid address may be passed
4487 as an operand. Such an address will be replaced with a valid address
4488 later in the reload pass. In this case, nothing may be done with the
4489 address except to use it as it stands. If it is copied, it will not be
4490 replaced with a valid address. No attempt should be made to make such
4491 an address into a valid address and no routine (such as
4492 @code{change_address}) that will do so may be called. Note that
4493 @code{general_operand} will fail when applied to such an address.
4495 @findex reload_in_progress
4496 The global variable @code{reload_in_progress} (which must be explicitly
4497 declared if required) can be used to determine whether such special
4498 handling is required.
4500 The variety of operands that have reloads depends on the rest of the
4501 machine description, but typically on a RISC machine these can only be
4502 pseudo registers that did not get hard registers, while on other
4503 machines explicit memory references will get optional reloads.
4505 If a scratch register is required to move an object to or from memory,
4506 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
4508 If there are cases which need scratch registers during or after reload,
4509 you must provide an appropriate secondary_reload target hook.
4511 @findex can_create_pseudo_p
4512 The macro @code{can_create_pseudo_p} can be used to determine if it
4513 is unsafe to create new pseudo registers. If this variable is nonzero, then
4514 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
4516 The constraints on a @samp{mov@var{m}} must permit moving any hard
4517 register to any other hard register provided that
4518 @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
4519 @code{TARGET_REGISTER_MOVE_COST} applied to their classes returns a value
4522 It is obligatory to support floating point @samp{mov@var{m}}
4523 instructions into and out of any registers that can hold fixed point
4524 values, because unions and structures (which have modes @code{SImode} or
4525 @code{DImode}) can be in those registers and they may have floating
4528 There may also be a need to support fixed point @samp{mov@var{m}}
4529 instructions in and out of floating point registers. Unfortunately, I
4530 have forgotten why this was so, and I don't know whether it is still
4531 true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
4532 floating point registers, then the constraints of the fixed point
4533 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
4534 reload into a floating point register.
4536 @cindex @code{reload_in} instruction pattern
4537 @cindex @code{reload_out} instruction pattern
4538 @item @samp{reload_in@var{m}}
4539 @itemx @samp{reload_out@var{m}}
4540 These named patterns have been obsoleted by the target hook
4541 @code{secondary_reload}.
4543 Like @samp{mov@var{m}}, but used when a scratch register is required to
4544 move between operand 0 and operand 1. Operand 2 describes the scratch
4545 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
4546 macro in @pxref{Register Classes}.
4548 There are special restrictions on the form of the @code{match_operand}s
4549 used in these patterns. First, only the predicate for the reload
4550 operand is examined, i.e., @code{reload_in} examines operand 1, but not
4551 the predicates for operand 0 or 2. Second, there may be only one
4552 alternative in the constraints. Third, only a single register class
4553 letter may be used for the constraint; subsequent constraint letters
4554 are ignored. As a special exception, an empty constraint string
4555 matches the @code{ALL_REGS} register class. This may relieve ports
4556 of the burden of defining an @code{ALL_REGS} constraint letter just
4559 @cindex @code{movstrict@var{m}} instruction pattern
4560 @item @samp{movstrict@var{m}}
4561 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
4562 with mode @var{m} of a register whose natural mode is wider,
4563 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
4564 any of the register except the part which belongs to mode @var{m}.
4566 @cindex @code{movmisalign@var{m}} instruction pattern
4567 @item @samp{movmisalign@var{m}}
4568 This variant of a move pattern is designed to load or store a value
4569 from a memory address that is not naturally aligned for its mode.
4570 For a store, the memory will be in operand 0; for a load, the memory
4571 will be in operand 1. The other operand is guaranteed not to be a
4572 memory, so that it's easy to tell whether this is a load or store.
4574 This pattern is used by the autovectorizer, and when expanding a
4575 @code{MISALIGNED_INDIRECT_REF} expression.
4577 @cindex @code{load_multiple} instruction pattern
4578 @item @samp{load_multiple}
4579 Load several consecutive memory locations into consecutive registers.
4580 Operand 0 is the first of the consecutive registers, operand 1
4581 is the first memory location, and operand 2 is a constant: the
4582 number of consecutive registers.
4584 Define this only if the target machine really has such an instruction;
4585 do not define this if the most efficient way of loading consecutive
4586 registers from memory is to do them one at a time.
4588 On some machines, there are restrictions as to which consecutive
4589 registers can be stored into memory, such as particular starting or
4590 ending register numbers or only a range of valid counts. For those
4591 machines, use a @code{define_expand} (@pxref{Expander Definitions})
4592 and make the pattern fail if the restrictions are not met.
4594 Write the generated insn as a @code{parallel} with elements being a
4595 @code{set} of one register from the appropriate memory location (you may
4596 also need @code{use} or @code{clobber} elements). Use a
4597 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
4598 @file{rs6000.md} for examples of the use of this insn pattern.
4600 @cindex @samp{store_multiple} instruction pattern
4601 @item @samp{store_multiple}
4602 Similar to @samp{load_multiple}, but store several consecutive registers
4603 into consecutive memory locations. Operand 0 is the first of the
4604 consecutive memory locations, operand 1 is the first register, and
4605 operand 2 is a constant: the number of consecutive registers.
4607 @cindex @code{vec_load_lanes@var{m}@var{n}} instruction pattern
4608 @item @samp{vec_load_lanes@var{m}@var{n}}
4609 Perform an interleaved load of several vectors from memory operand 1
4610 into register operand 0. Both operands have mode @var{m}. The register
4611 operand is viewed as holding consecutive vectors of mode @var{n},
4612 while the memory operand is a flat array that contains the same number
4613 of elements. The operation is equivalent to:
4616 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4617 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4618 for (i = 0; i < c; i++)
4619 operand0[i][j] = operand1[j * c + i];
4622 For example, @samp{vec_load_lanestiv4hi} loads 8 16-bit values
4623 from memory into a register of mode @samp{TI}@. The register
4624 contains two consecutive vectors of mode @samp{V4HI}@.
4626 This pattern can only be used if:
4628 TARGET_ARRAY_MODE_SUPPORTED_P (@var{n}, @var{c})
4630 is true. GCC assumes that, if a target supports this kind of
4631 instruction for some mode @var{n}, it also supports unaligned
4632 loads for vectors of mode @var{n}.
4634 @cindex @code{vec_store_lanes@var{m}@var{n}} instruction pattern
4635 @item @samp{vec_store_lanes@var{m}@var{n}}
4636 Equivalent to @samp{vec_load_lanes@var{m}@var{n}}, with the memory
4637 and register operands reversed. That is, the instruction is
4641 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4642 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4643 for (i = 0; i < c; i++)
4644 operand0[j * c + i] = operand1[i][j];
4647 for a memory operand 0 and register operand 1.
4649 @cindex @code{vec_set@var{m}} instruction pattern
4650 @item @samp{vec_set@var{m}}
4651 Set given field in the vector value. Operand 0 is the vector to modify,
4652 operand 1 is new value of field and operand 2 specify the field index.
4654 @cindex @code{vec_extract@var{m}} instruction pattern
4655 @item @samp{vec_extract@var{m}}
4656 Extract given field from the vector value. Operand 1 is the vector, operand 2
4657 specify field index and operand 0 place to store value into.
4659 @cindex @code{vec_init@var{m}} instruction pattern
4660 @item @samp{vec_init@var{m}}
4661 Initialize the vector to given values. Operand 0 is the vector to initialize
4662 and operand 1 is parallel containing values for individual fields.
4664 @cindex @code{vcond@var{m}@var{n}} instruction pattern
4665 @item @samp{vcond@var{m}@var{n}}
4666 Output a conditional vector move. Operand 0 is the destination to
4667 receive a combination of operand 1 and operand 2, which are of mode @var{m},
4668 dependent on the outcome of the predicate in operand 3 which is a
4669 vector comparison with operands of mode @var{n} in operands 4 and 5. The
4670 modes @var{m} and @var{n} should have the same size. Operand 0
4671 will be set to the value @var{op1} & @var{msk} | @var{op2} & ~@var{msk}
4672 where @var{msk} is computed by element-wise evaluation of the vector
4673 comparison with a truth value of all-ones and a false value of all-zeros.
4675 @cindex @code{vec_perm@var{m}} instruction pattern
4676 @item @samp{vec_perm@var{m}}
4677 Output a (variable) vector permutation. Operand 0 is the destination
4678 to receive elements from operand 1 and operand 2, which are of mode
4679 @var{m}. Operand 3 is the @dfn{selector}. It is an integral mode
4680 vector of the same width and number of elements as mode @var{m}.
4682 The input elements are numbered from 0 in operand 1 through
4683 @math{2*@var{N}-1} in operand 2. The elements of the selector must
4684 be computed modulo @math{2*@var{N}}. Note that if
4685 @code{rtx_equal_p(operand1, operand2)}, this can be implemented
4686 with just operand 1 and selector elements modulo @var{N}.
4688 In order to make things easy for a number of targets, if there is no
4689 @samp{vec_perm} pattern for mode @var{m}, but there is for mode @var{q}
4690 where @var{q} is a vector of @code{QImode} of the same width as @var{m},
4691 the middle-end will lower the mode @var{m} @code{VEC_PERM_EXPR} to
4694 @cindex @code{vec_perm_const@var{m}} instruction pattern
4695 @item @samp{vec_perm_const@var{m}}
4696 Like @samp{vec_perm} except that the permutation is a compile-time
4697 constant. That is, operand 3, the @dfn{selector}, is a @code{CONST_VECTOR}.
4699 Some targets cannot perform a permutation with a variable selector,
4700 but can efficiently perform a constant permutation. Further, the
4701 target hook @code{vec_perm_ok} is queried to determine if the
4702 specific constant permutation is available efficiently; the named
4703 pattern is never expanded without @code{vec_perm_ok} returning true.
4705 There is no need for a target to supply both @samp{vec_perm@var{m}}
4706 and @samp{vec_perm_const@var{m}} if the former can trivially implement
4707 the operation with, say, the vector constant loaded into a register.
4709 @cindex @code{push@var{m}1} instruction pattern
4710 @item @samp{push@var{m}1}
4711 Output a push instruction. Operand 0 is value to push. Used only when
4712 @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
4713 missing and in such case an @code{mov} expander is used instead, with a
4714 @code{MEM} expression forming the push operation. The @code{mov} expander
4715 method is deprecated.
4717 @cindex @code{add@var{m}3} instruction pattern
4718 @item @samp{add@var{m}3}
4719 Add operand 2 and operand 1, storing the result in operand 0. All operands
4720 must have mode @var{m}. This can be used even on two-address machines, by
4721 means of constraints requiring operands 1 and 0 to be the same location.
4723 @cindex @code{addptr@var{m}3} instruction pattern
4724 @item @samp{addptr@var{m}3}
4725 Like @code{add@var{m}3} but is guaranteed to only be used for address
4726 calculations. The expanded code is not allowed to clobber the
4727 condition code. It only needs to be defined if @code{add@var{m}3}
4728 sets the condition code. If adds used for address calculations and
4729 normal adds are not compatible it is required to expand a distinct
4730 pattern (e.g. using an unspec). The pattern is used by LRA to emit
4731 address calculations. @code{add@var{m}3} is used if
4732 @code{addptr@var{m}3} is not defined.
4734 @cindex @code{ssadd@var{m}3} instruction pattern
4735 @cindex @code{usadd@var{m}3} instruction pattern
4736 @cindex @code{sub@var{m}3} instruction pattern
4737 @cindex @code{sssub@var{m}3} instruction pattern
4738 @cindex @code{ussub@var{m}3} instruction pattern
4739 @cindex @code{mul@var{m}3} instruction pattern
4740 @cindex @code{ssmul@var{m}3} instruction pattern
4741 @cindex @code{usmul@var{m}3} instruction pattern
4742 @cindex @code{div@var{m}3} instruction pattern
4743 @cindex @code{ssdiv@var{m}3} instruction pattern
4744 @cindex @code{udiv@var{m}3} instruction pattern
4745 @cindex @code{usdiv@var{m}3} instruction pattern
4746 @cindex @code{mod@var{m}3} instruction pattern
4747 @cindex @code{umod@var{m}3} instruction pattern
4748 @cindex @code{umin@var{m}3} instruction pattern
4749 @cindex @code{umax@var{m}3} instruction pattern
4750 @cindex @code{and@var{m}3} instruction pattern
4751 @cindex @code{ior@var{m}3} instruction pattern
4752 @cindex @code{xor@var{m}3} instruction pattern
4753 @item @samp{ssadd@var{m}3}, @samp{usadd@var{m}3}
4754 @itemx @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3}
4755 @itemx @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3}
4756 @itemx @samp{div@var{m}3}, @samp{ssdiv@var{m}3}
4757 @itemx @samp{udiv@var{m}3}, @samp{usdiv@var{m}3}
4758 @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3}
4759 @itemx @samp{umin@var{m}3}, @samp{umax@var{m}3}
4760 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
4761 Similar, for other arithmetic operations.
4763 @cindex @code{fma@var{m}4} instruction pattern
4764 @item @samp{fma@var{m}4}
4765 Multiply operand 2 and operand 1, then add operand 3, storing the
4766 result in operand 0 without doing an intermediate rounding step. All
4767 operands must have mode @var{m}. This pattern is used to implement
4768 the @code{fma}, @code{fmaf}, and @code{fmal} builtin functions from
4769 the ISO C99 standard.
4771 @cindex @code{fms@var{m}4} instruction pattern
4772 @item @samp{fms@var{m}4}
4773 Like @code{fma@var{m}4}, except operand 3 subtracted from the
4774 product instead of added to the product. This is represented
4778 (fma:@var{m} @var{op1} @var{op2} (neg:@var{m} @var{op3}))
4781 @cindex @code{fnma@var{m}4} instruction pattern
4782 @item @samp{fnma@var{m}4}
4783 Like @code{fma@var{m}4} except that the intermediate product
4784 is negated before being added to operand 3. This is represented
4788 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} @var{op3})
4791 @cindex @code{fnms@var{m}4} instruction pattern
4792 @item @samp{fnms@var{m}4}
4793 Like @code{fms@var{m}4} except that the intermediate product
4794 is negated before subtracting operand 3. This is represented
4798 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} (neg:@var{m} @var{op3}))
4801 @cindex @code{min@var{m}3} instruction pattern
4802 @cindex @code{max@var{m}3} instruction pattern
4803 @item @samp{smin@var{m}3}, @samp{smax@var{m}3}
4804 Signed minimum and maximum operations. When used with floating point,
4805 if both operands are zeros, or if either operand is @code{NaN}, then
4806 it is unspecified which of the two operands is returned as the result.
4808 @cindex @code{reduc_smin_@var{m}} instruction pattern
4809 @cindex @code{reduc_smax_@var{m}} instruction pattern
4810 @item @samp{reduc_smin_@var{m}}, @samp{reduc_smax_@var{m}}
4811 Find the signed minimum/maximum of the elements of a vector. The vector is
4812 operand 1, and the result is stored in the least significant bits of
4813 operand 0 (also a vector). The output and input vector should have the same
4814 modes. These are legacy optabs, and platforms should prefer to implement
4815 @samp{reduc_smin_scal_@var{m}} and @samp{reduc_smax_scal_@var{m}}.
4817 @cindex @code{reduc_umin_@var{m}} instruction pattern
4818 @cindex @code{reduc_umax_@var{m}} instruction pattern
4819 @item @samp{reduc_umin_@var{m}}, @samp{reduc_umax_@var{m}}
4820 Find the unsigned minimum/maximum of the elements of a vector. The vector is
4821 operand 1, and the result is stored in the least significant bits of
4822 operand 0 (also a vector). The output and input vector should have the same
4823 modes. These are legacy optabs, and platforms should prefer to implement
4824 @samp{reduc_umin_scal_@var{m}} and @samp{reduc_umax_scal_@var{m}}.
4826 @cindex @code{reduc_splus_@var{m}} instruction pattern
4827 @cindex @code{reduc_uplus_@var{m}} instruction pattern
4828 @item @samp{reduc_splus_@var{m}}, @samp{reduc_uplus_@var{m}}
4829 Compute the sum of the signed/unsigned elements of a vector. The vector is
4830 operand 1, and the result is stored in the least significant bits of operand 0
4831 (also a vector). The output and input vector should have the same modes.
4832 These are legacy optabs, and platforms should prefer to implement
4833 @samp{reduc_plus_scal_@var{m}}.
4835 @cindex @code{reduc_smin_scal_@var{m}} instruction pattern
4836 @cindex @code{reduc_smax_scal_@var{m}} instruction pattern
4837 @item @samp{reduc_smin_scal_@var{m}}, @samp{reduc_smax_scal_@var{m}}
4838 Find the signed minimum/maximum of the elements of a vector. The vector is
4839 operand 1, and operand 0 is the scalar result, with mode equal to the mode of
4840 the elements of the input vector.
4842 @cindex @code{reduc_umin_scal_@var{m}} instruction pattern
4843 @cindex @code{reduc_umax_scal_@var{m}} instruction pattern
4844 @item @samp{reduc_umin_scal_@var{m}}, @samp{reduc_umax_scal_@var{m}}
4845 Find the unsigned minimum/maximum of the elements of a vector. The vector is
4846 operand 1, and operand 0 is the scalar result, with mode equal to the mode of
4847 the elements of the input vector.
4849 @cindex @code{reduc_plus_scal_@var{m}} instruction pattern
4850 @item @samp{reduc_plus_scal_@var{m}}
4851 Compute the sum of the elements of a vector. The vector is operand 1, and
4852 operand 0 is the scalar result, with mode equal to the mode of the elements of
4855 @cindex @code{sdot_prod@var{m}} instruction pattern
4856 @item @samp{sdot_prod@var{m}}
4857 @cindex @code{udot_prod@var{m}} instruction pattern
4858 @itemx @samp{udot_prod@var{m}}
4859 Compute the sum of the products of two signed/unsigned elements.
4860 Operand 1 and operand 2 are of the same mode. Their product, which is of a
4861 wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or
4862 wider than the mode of the product. The result is placed in operand 0, which
4863 is of the same mode as operand 3.
4865 @cindex @code{ssad@var{m}} instruction pattern
4866 @item @samp{ssad@var{m}}
4867 @cindex @code{usad@var{m}} instruction pattern
4868 @item @samp{usad@var{m}}
4869 Compute the sum of absolute differences of two signed/unsigned elements.
4870 Operand 1 and operand 2 are of the same mode. Their absolute difference, which
4871 is of a wider mode, is computed and added to operand 3. Operand 3 is of a mode
4872 equal or wider than the mode of the absolute difference. The result is placed
4873 in operand 0, which is of the same mode as operand 3.
4875 @cindex @code{ssum_widen@var{m3}} instruction pattern
4876 @item @samp{ssum_widen@var{m3}}
4877 @cindex @code{usum_widen@var{m3}} instruction pattern
4878 @itemx @samp{usum_widen@var{m3}}
4879 Operands 0 and 2 are of the same mode, which is wider than the mode of
4880 operand 1. Add operand 1 to operand 2 and place the widened result in
4881 operand 0. (This is used express accumulation of elements into an accumulator
4884 @cindex @code{vec_shr_@var{m}} instruction pattern
4885 @item @samp{vec_shr_@var{m}}
4886 Whole vector right shift in bits, i.e. towards element 0.
4887 Operand 1 is a vector to be shifted.
4888 Operand 2 is an integer shift amount in bits.
4889 Operand 0 is where the resulting shifted vector is stored.
4890 The output and input vectors should have the same modes.
4892 @cindex @code{vec_pack_trunc_@var{m}} instruction pattern
4893 @item @samp{vec_pack_trunc_@var{m}}
4894 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
4895 are vectors of the same mode having N integral or floating point elements
4896 of size S@. Operand 0 is the resulting vector in which 2*N elements of
4897 size N/2 are concatenated after narrowing them down using truncation.
4899 @cindex @code{vec_pack_ssat_@var{m}} instruction pattern
4900 @cindex @code{vec_pack_usat_@var{m}} instruction pattern
4901 @item @samp{vec_pack_ssat_@var{m}}, @samp{vec_pack_usat_@var{m}}
4902 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
4903 are vectors of the same mode having N integral elements of size S.
4904 Operand 0 is the resulting vector in which the elements of the two input
4905 vectors are concatenated after narrowing them down using signed/unsigned
4906 saturating arithmetic.
4908 @cindex @code{vec_pack_sfix_trunc_@var{m}} instruction pattern
4909 @cindex @code{vec_pack_ufix_trunc_@var{m}} instruction pattern
4910 @item @samp{vec_pack_sfix_trunc_@var{m}}, @samp{vec_pack_ufix_trunc_@var{m}}
4911 Narrow, convert to signed/unsigned integral type and merge the elements
4912 of two vectors. Operands 1 and 2 are vectors of the same mode having N
4913 floating point elements of size S@. Operand 0 is the resulting vector
4914 in which 2*N elements of size N/2 are concatenated.
4916 @cindex @code{vec_unpacks_hi_@var{m}} instruction pattern
4917 @cindex @code{vec_unpacks_lo_@var{m}} instruction pattern
4918 @item @samp{vec_unpacks_hi_@var{m}}, @samp{vec_unpacks_lo_@var{m}}
4919 Extract and widen (promote) the high/low part of a vector of signed
4920 integral or floating point elements. The input vector (operand 1) has N
4921 elements of size S@. Widen (promote) the high/low elements of the vector
4922 using signed or floating point extension and place the resulting N/2
4923 values of size 2*S in the output vector (operand 0).
4925 @cindex @code{vec_unpacku_hi_@var{m}} instruction pattern
4926 @cindex @code{vec_unpacku_lo_@var{m}} instruction pattern
4927 @item @samp{vec_unpacku_hi_@var{m}}, @samp{vec_unpacku_lo_@var{m}}
4928 Extract and widen (promote) the high/low part of a vector of unsigned
4929 integral elements. The input vector (operand 1) has N elements of size S.
4930 Widen (promote) the high/low elements of the vector using zero extension and
4931 place the resulting N/2 values of size 2*S in the output vector (operand 0).
4933 @cindex @code{vec_unpacks_float_hi_@var{m}} instruction pattern
4934 @cindex @code{vec_unpacks_float_lo_@var{m}} instruction pattern
4935 @cindex @code{vec_unpacku_float_hi_@var{m}} instruction pattern
4936 @cindex @code{vec_unpacku_float_lo_@var{m}} instruction pattern
4937 @item @samp{vec_unpacks_float_hi_@var{m}}, @samp{vec_unpacks_float_lo_@var{m}}
4938 @itemx @samp{vec_unpacku_float_hi_@var{m}}, @samp{vec_unpacku_float_lo_@var{m}}
4939 Extract, convert to floating point type and widen the high/low part of a
4940 vector of signed/unsigned integral elements. The input vector (operand 1)
4941 has N elements of size S@. Convert the high/low elements of the vector using
4942 floating point conversion and place the resulting N/2 values of size 2*S in
4943 the output vector (operand 0).
4945 @cindex @code{vec_widen_umult_hi_@var{m}} instruction pattern
4946 @cindex @code{vec_widen_umult_lo_@var{m}} instruction pattern
4947 @cindex @code{vec_widen_smult_hi_@var{m}} instruction pattern
4948 @cindex @code{vec_widen_smult_lo_@var{m}} instruction pattern
4949 @cindex @code{vec_widen_umult_even_@var{m}} instruction pattern
4950 @cindex @code{vec_widen_umult_odd_@var{m}} instruction pattern
4951 @cindex @code{vec_widen_smult_even_@var{m}} instruction pattern
4952 @cindex @code{vec_widen_smult_odd_@var{m}} instruction pattern
4953 @item @samp{vec_widen_umult_hi_@var{m}}, @samp{vec_widen_umult_lo_@var{m}}
4954 @itemx @samp{vec_widen_smult_hi_@var{m}}, @samp{vec_widen_smult_lo_@var{m}}
4955 @itemx @samp{vec_widen_umult_even_@var{m}}, @samp{vec_widen_umult_odd_@var{m}}
4956 @itemx @samp{vec_widen_smult_even_@var{m}}, @samp{vec_widen_smult_odd_@var{m}}
4957 Signed/Unsigned widening multiplication. The two inputs (operands 1 and 2)
4958 are vectors with N signed/unsigned elements of size S@. Multiply the high/low
4959 or even/odd elements of the two vectors, and put the N/2 products of size 2*S
4960 in the output vector (operand 0). A target shouldn't implement even/odd pattern
4961 pair if it is less efficient than lo/hi one.
4963 @cindex @code{vec_widen_ushiftl_hi_@var{m}} instruction pattern
4964 @cindex @code{vec_widen_ushiftl_lo_@var{m}} instruction pattern
4965 @cindex @code{vec_widen_sshiftl_hi_@var{m}} instruction pattern
4966 @cindex @code{vec_widen_sshiftl_lo_@var{m}} instruction pattern
4967 @item @samp{vec_widen_ushiftl_hi_@var{m}}, @samp{vec_widen_ushiftl_lo_@var{m}}
4968 @itemx @samp{vec_widen_sshiftl_hi_@var{m}}, @samp{vec_widen_sshiftl_lo_@var{m}}
4969 Signed/Unsigned widening shift left. The first input (operand 1) is a vector
4970 with N signed/unsigned elements of size S@. Operand 2 is a constant. Shift
4971 the high/low elements of operand 1, and put the N/2 results of size 2*S in the
4972 output vector (operand 0).
4974 @cindex @code{mulhisi3} instruction pattern
4975 @item @samp{mulhisi3}
4976 Multiply operands 1 and 2, which have mode @code{HImode}, and store
4977 a @code{SImode} product in operand 0.
4979 @cindex @code{mulqihi3} instruction pattern
4980 @cindex @code{mulsidi3} instruction pattern
4981 @item @samp{mulqihi3}, @samp{mulsidi3}
4982 Similar widening-multiplication instructions of other widths.
4984 @cindex @code{umulqihi3} instruction pattern
4985 @cindex @code{umulhisi3} instruction pattern
4986 @cindex @code{umulsidi3} instruction pattern
4987 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
4988 Similar widening-multiplication instructions that do unsigned
4991 @cindex @code{usmulqihi3} instruction pattern
4992 @cindex @code{usmulhisi3} instruction pattern
4993 @cindex @code{usmulsidi3} instruction pattern
4994 @item @samp{usmulqihi3}, @samp{usmulhisi3}, @samp{usmulsidi3}
4995 Similar widening-multiplication instructions that interpret the first
4996 operand as unsigned and the second operand as signed, then do a signed
4999 @cindex @code{smul@var{m}3_highpart} instruction pattern
5000 @item @samp{smul@var{m}3_highpart}
5001 Perform a signed multiplication of operands 1 and 2, which have mode
5002 @var{m}, and store the most significant half of the product in operand 0.
5003 The least significant half of the product is discarded.
5005 @cindex @code{umul@var{m}3_highpart} instruction pattern
5006 @item @samp{umul@var{m}3_highpart}
5007 Similar, but the multiplication is unsigned.
5009 @cindex @code{madd@var{m}@var{n}4} instruction pattern
5010 @item @samp{madd@var{m}@var{n}4}
5011 Multiply operands 1 and 2, sign-extend them to mode @var{n}, add
5012 operand 3, and store the result in operand 0. Operands 1 and 2
5013 have mode @var{m} and operands 0 and 3 have mode @var{n}.
5014 Both modes must be integer or fixed-point modes and @var{n} must be twice
5015 the size of @var{m}.
5017 In other words, @code{madd@var{m}@var{n}4} is like
5018 @code{mul@var{m}@var{n}3} except that it also adds operand 3.
5020 These instructions are not allowed to @code{FAIL}.
5022 @cindex @code{umadd@var{m}@var{n}4} instruction pattern
5023 @item @samp{umadd@var{m}@var{n}4}
5024 Like @code{madd@var{m}@var{n}4}, but zero-extend the multiplication
5025 operands instead of sign-extending them.
5027 @cindex @code{ssmadd@var{m}@var{n}4} instruction pattern
5028 @item @samp{ssmadd@var{m}@var{n}4}
5029 Like @code{madd@var{m}@var{n}4}, but all involved operations must be
5032 @cindex @code{usmadd@var{m}@var{n}4} instruction pattern
5033 @item @samp{usmadd@var{m}@var{n}4}
5034 Like @code{umadd@var{m}@var{n}4}, but all involved operations must be
5035 unsigned-saturating.
5037 @cindex @code{msub@var{m}@var{n}4} instruction pattern
5038 @item @samp{msub@var{m}@var{n}4}
5039 Multiply operands 1 and 2, sign-extend them to mode @var{n}, subtract the
5040 result from operand 3, and store the result in operand 0. Operands 1 and 2
5041 have mode @var{m} and operands 0 and 3 have mode @var{n}.
5042 Both modes must be integer or fixed-point modes and @var{n} must be twice
5043 the size of @var{m}.
5045 In other words, @code{msub@var{m}@var{n}4} is like
5046 @code{mul@var{m}@var{n}3} except that it also subtracts the result
5049 These instructions are not allowed to @code{FAIL}.
5051 @cindex @code{umsub@var{m}@var{n}4} instruction pattern
5052 @item @samp{umsub@var{m}@var{n}4}
5053 Like @code{msub@var{m}@var{n}4}, but zero-extend the multiplication
5054 operands instead of sign-extending them.
5056 @cindex @code{ssmsub@var{m}@var{n}4} instruction pattern
5057 @item @samp{ssmsub@var{m}@var{n}4}
5058 Like @code{msub@var{m}@var{n}4}, but all involved operations must be
5061 @cindex @code{usmsub@var{m}@var{n}4} instruction pattern
5062 @item @samp{usmsub@var{m}@var{n}4}
5063 Like @code{umsub@var{m}@var{n}4}, but all involved operations must be
5064 unsigned-saturating.
5066 @cindex @code{divmod@var{m}4} instruction pattern
5067 @item @samp{divmod@var{m}4}
5068 Signed division that produces both a quotient and a remainder.
5069 Operand 1 is divided by operand 2 to produce a quotient stored
5070 in operand 0 and a remainder stored in operand 3.
5072 For machines with an instruction that produces both a quotient and a
5073 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
5074 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
5075 allows optimization in the relatively common case when both the quotient
5076 and remainder are computed.
5078 If an instruction that just produces a quotient or just a remainder
5079 exists and is more efficient than the instruction that produces both,
5080 write the output routine of @samp{divmod@var{m}4} to call
5081 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
5082 quotient or remainder and generate the appropriate instruction.
5084 @cindex @code{udivmod@var{m}4} instruction pattern
5085 @item @samp{udivmod@var{m}4}
5086 Similar, but does unsigned division.
5088 @anchor{shift patterns}
5089 @cindex @code{ashl@var{m}3} instruction pattern
5090 @cindex @code{ssashl@var{m}3} instruction pattern
5091 @cindex @code{usashl@var{m}3} instruction pattern
5092 @item @samp{ashl@var{m}3}, @samp{ssashl@var{m}3}, @samp{usashl@var{m}3}
5093 Arithmetic-shift operand 1 left by a number of bits specified by operand
5094 2, and store the result in operand 0. Here @var{m} is the mode of
5095 operand 0 and operand 1; operand 2's mode is specified by the
5096 instruction pattern, and the compiler will convert the operand to that
5097 mode before generating the instruction. The meaning of out-of-range shift
5098 counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}.
5099 @xref{TARGET_SHIFT_TRUNCATION_MASK}. Operand 2 is always a scalar type.
5101 @cindex @code{ashr@var{m}3} instruction pattern
5102 @cindex @code{lshr@var{m}3} instruction pattern
5103 @cindex @code{rotl@var{m}3} instruction pattern
5104 @cindex @code{rotr@var{m}3} instruction pattern
5105 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
5106 Other shift and rotate instructions, analogous to the
5107 @code{ashl@var{m}3} instructions. Operand 2 is always a scalar type.
5109 @cindex @code{vashl@var{m}3} instruction pattern
5110 @cindex @code{vashr@var{m}3} instruction pattern
5111 @cindex @code{vlshr@var{m}3} instruction pattern
5112 @cindex @code{vrotl@var{m}3} instruction pattern
5113 @cindex @code{vrotr@var{m}3} instruction pattern
5114 @item @samp{vashl@var{m}3}, @samp{vashr@var{m}3}, @samp{vlshr@var{m}3}, @samp{vrotl@var{m}3}, @samp{vrotr@var{m}3}
5115 Vector shift and rotate instructions that take vectors as operand 2
5116 instead of a scalar type.
5118 @cindex @code{bswap@var{m}2} instruction pattern
5119 @item @samp{bswap@var{m}2}
5120 Reverse the order of bytes of operand 1 and store the result in operand 0.
5122 @cindex @code{neg@var{m}2} instruction pattern
5123 @cindex @code{ssneg@var{m}2} instruction pattern
5124 @cindex @code{usneg@var{m}2} instruction pattern
5125 @item @samp{neg@var{m}2}, @samp{ssneg@var{m}2}, @samp{usneg@var{m}2}
5126 Negate operand 1 and store the result in operand 0.
5128 @cindex @code{abs@var{m}2} instruction pattern
5129 @item @samp{abs@var{m}2}
5130 Store the absolute value of operand 1 into operand 0.
5132 @cindex @code{sqrt@var{m}2} instruction pattern
5133 @item @samp{sqrt@var{m}2}
5134 Store the square root of operand 1 into operand 0.
5136 The @code{sqrt} built-in function of C always uses the mode which
5137 corresponds to the C data type @code{double} and the @code{sqrtf}
5138 built-in function uses the mode which corresponds to the C data
5141 @cindex @code{fmod@var{m}3} instruction pattern
5142 @item @samp{fmod@var{m}3}
5143 Store the remainder of dividing operand 1 by operand 2 into
5144 operand 0, rounded towards zero to an integer.
5146 The @code{fmod} built-in function of C always uses the mode which
5147 corresponds to the C data type @code{double} and the @code{fmodf}
5148 built-in function uses the mode which corresponds to the C data
5151 @cindex @code{remainder@var{m}3} instruction pattern
5152 @item @samp{remainder@var{m}3}
5153 Store the remainder of dividing operand 1 by operand 2 into
5154 operand 0, rounded to the nearest integer.
5156 The @code{remainder} built-in function of C always uses the mode
5157 which corresponds to the C data type @code{double} and the
5158 @code{remainderf} built-in function uses the mode which corresponds
5159 to the C data type @code{float}.
5161 @cindex @code{cos@var{m}2} instruction pattern
5162 @item @samp{cos@var{m}2}
5163 Store the cosine of operand 1 into operand 0.
5165 The @code{cos} built-in function of C always uses the mode which
5166 corresponds to the C data type @code{double} and the @code{cosf}
5167 built-in function uses the mode which corresponds to the C data
5170 @cindex @code{sin@var{m}2} instruction pattern
5171 @item @samp{sin@var{m}2}
5172 Store the sine of operand 1 into operand 0.
5174 The @code{sin} built-in function of C always uses the mode which
5175 corresponds to the C data type @code{double} and the @code{sinf}
5176 built-in function uses the mode which corresponds to the C data
5179 @cindex @code{sincos@var{m}3} instruction pattern
5180 @item @samp{sincos@var{m}3}
5181 Store the cosine of operand 2 into operand 0 and the sine of
5182 operand 2 into operand 1.
5184 The @code{sin} and @code{cos} built-in functions of C always use the
5185 mode which corresponds to the C data type @code{double} and the
5186 @code{sinf} and @code{cosf} built-in function use the mode which
5187 corresponds to the C data type @code{float}.
5188 Targets that can calculate the sine and cosine simultaneously can
5189 implement this pattern as opposed to implementing individual
5190 @code{sin@var{m}2} and @code{cos@var{m}2} patterns. The @code{sin}
5191 and @code{cos} built-in functions will then be expanded to the
5192 @code{sincos@var{m}3} pattern, with one of the output values
5195 @cindex @code{exp@var{m}2} instruction pattern
5196 @item @samp{exp@var{m}2}
5197 Store the exponential of operand 1 into operand 0.
5199 The @code{exp} built-in function of C always uses the mode which
5200 corresponds to the C data type @code{double} and the @code{expf}
5201 built-in function uses the mode which corresponds to the C data
5204 @cindex @code{log@var{m}2} instruction pattern
5205 @item @samp{log@var{m}2}
5206 Store the natural logarithm of operand 1 into operand 0.
5208 The @code{log} built-in function of C always uses the mode which
5209 corresponds to the C data type @code{double} and the @code{logf}
5210 built-in function uses the mode which corresponds to the C data
5213 @cindex @code{pow@var{m}3} instruction pattern
5214 @item @samp{pow@var{m}3}
5215 Store the value of operand 1 raised to the exponent operand 2
5218 The @code{pow} built-in function of C always uses the mode which
5219 corresponds to the C data type @code{double} and the @code{powf}
5220 built-in function uses the mode which corresponds to the C data
5223 @cindex @code{atan2@var{m}3} instruction pattern
5224 @item @samp{atan2@var{m}3}
5225 Store the arc tangent (inverse tangent) of operand 1 divided by
5226 operand 2 into operand 0, using the signs of both arguments to
5227 determine the quadrant of the result.
5229 The @code{atan2} built-in function of C always uses the mode which
5230 corresponds to the C data type @code{double} and the @code{atan2f}
5231 built-in function uses the mode which corresponds to the C data
5234 @cindex @code{floor@var{m}2} instruction pattern
5235 @item @samp{floor@var{m}2}
5236 Store the largest integral value not greater than argument.
5238 The @code{floor} built-in function of C always uses the mode which
5239 corresponds to the C data type @code{double} and the @code{floorf}
5240 built-in function uses the mode which corresponds to the C data
5243 @cindex @code{btrunc@var{m}2} instruction pattern
5244 @item @samp{btrunc@var{m}2}
5245 Store the argument rounded to integer towards zero.
5247 The @code{trunc} built-in function of C always uses the mode which
5248 corresponds to the C data type @code{double} and the @code{truncf}
5249 built-in function uses the mode which corresponds to the C data
5252 @cindex @code{round@var{m}2} instruction pattern
5253 @item @samp{round@var{m}2}
5254 Store the argument rounded to integer away from zero.
5256 The @code{round} built-in function of C always uses the mode which
5257 corresponds to the C data type @code{double} and the @code{roundf}
5258 built-in function uses the mode which corresponds to the C data
5261 @cindex @code{ceil@var{m}2} instruction pattern
5262 @item @samp{ceil@var{m}2}
5263 Store the argument rounded to integer away from zero.
5265 The @code{ceil} built-in function of C always uses the mode which
5266 corresponds to the C data type @code{double} and the @code{ceilf}
5267 built-in function uses the mode which corresponds to the C data
5270 @cindex @code{nearbyint@var{m}2} instruction pattern
5271 @item @samp{nearbyint@var{m}2}
5272 Store the argument rounded according to the default rounding mode
5274 The @code{nearbyint} built-in function of C always uses the mode which
5275 corresponds to the C data type @code{double} and the @code{nearbyintf}
5276 built-in function uses the mode which corresponds to the C data
5279 @cindex @code{rint@var{m}2} instruction pattern
5280 @item @samp{rint@var{m}2}
5281 Store the argument rounded according to the default rounding mode and
5282 raise the inexact exception when the result differs in value from
5285 The @code{rint} built-in function of C always uses the mode which
5286 corresponds to the C data type @code{double} and the @code{rintf}
5287 built-in function uses the mode which corresponds to the C data
5290 @cindex @code{lrint@var{m}@var{n}2}
5291 @item @samp{lrint@var{m}@var{n}2}
5292 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5293 point mode @var{n} as a signed number according to the current
5294 rounding mode and store in operand 0 (which has mode @var{n}).
5296 @cindex @code{lround@var{m}@var{n}2}
5297 @item @samp{lround@var{m}@var{n}2}
5298 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5299 point mode @var{n} as a signed number rounding to nearest and away
5300 from zero and store in operand 0 (which has mode @var{n}).
5302 @cindex @code{lfloor@var{m}@var{n}2}
5303 @item @samp{lfloor@var{m}@var{n}2}
5304 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5305 point mode @var{n} as a signed number rounding down and store in
5306 operand 0 (which has mode @var{n}).
5308 @cindex @code{lceil@var{m}@var{n}2}
5309 @item @samp{lceil@var{m}@var{n}2}
5310 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5311 point mode @var{n} as a signed number rounding up and store in
5312 operand 0 (which has mode @var{n}).
5314 @cindex @code{copysign@var{m}3} instruction pattern
5315 @item @samp{copysign@var{m}3}
5316 Store a value with the magnitude of operand 1 and the sign of operand
5319 The @code{copysign} built-in function of C always uses the mode which
5320 corresponds to the C data type @code{double} and the @code{copysignf}
5321 built-in function uses the mode which corresponds to the C data
5324 @cindex @code{ffs@var{m}2} instruction pattern
5325 @item @samp{ffs@var{m}2}
5326 Store into operand 0 one plus the index of the least significant 1-bit
5327 of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
5328 of operand 0; operand 1's mode is specified by the instruction
5329 pattern, and the compiler will convert the operand to that mode before
5330 generating the instruction.
5332 The @code{ffs} built-in function of C always uses the mode which
5333 corresponds to the C data type @code{int}.
5335 @cindex @code{clrsb@var{m}2} instruction pattern
5336 @item @samp{clrsb@var{m}2}
5337 Count leading redundant sign bits.
5338 Store into operand 0 the number of redundant sign bits in operand 1, starting
5339 at the most significant bit position.
5340 A redundant sign bit is defined as any sign bit after the first. As such,
5341 this count will be one less than the count of leading sign bits.
5343 @cindex @code{clz@var{m}2} instruction pattern
5344 @item @samp{clz@var{m}2}
5345 Store into operand 0 the number of leading 0-bits in operand 1, starting
5346 at the most significant bit position. If operand 1 is 0, the
5347 @code{CLZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
5348 the result is undefined or has a useful value.
5349 @var{m} is the mode of operand 0; operand 1's mode is
5350 specified by the instruction pattern, and the compiler will convert the
5351 operand to that mode before generating the instruction.
5353 @cindex @code{ctz@var{m}2} instruction pattern
5354 @item @samp{ctz@var{m}2}
5355 Store into operand 0 the number of trailing 0-bits in operand 1, starting
5356 at the least significant bit position. If operand 1 is 0, the
5357 @code{CTZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
5358 the result is undefined or has a useful value.
5359 @var{m} is the mode of operand 0; operand 1's mode is
5360 specified by the instruction pattern, and the compiler will convert the
5361 operand to that mode before generating the instruction.
5363 @cindex @code{popcount@var{m}2} instruction pattern
5364 @item @samp{popcount@var{m}2}
5365 Store into operand 0 the number of 1-bits in operand 1. @var{m} is the
5366 mode of operand 0; operand 1's mode is specified by the instruction
5367 pattern, and the compiler will convert the operand to that mode before
5368 generating the instruction.
5370 @cindex @code{parity@var{m}2} instruction pattern
5371 @item @samp{parity@var{m}2}
5372 Store into operand 0 the parity of operand 1, i.e.@: the number of 1-bits
5373 in operand 1 modulo 2. @var{m} is the mode of operand 0; operand 1's mode
5374 is specified by the instruction pattern, and the compiler will convert
5375 the operand to that mode before generating the instruction.
5377 @cindex @code{one_cmpl@var{m}2} instruction pattern
5378 @item @samp{one_cmpl@var{m}2}
5379 Store the bitwise-complement of operand 1 into operand 0.
5381 @cindex @code{movmem@var{m}} instruction pattern
5382 @item @samp{movmem@var{m}}
5383 Block move instruction. The destination and source blocks of memory
5384 are the first two operands, and both are @code{mem:BLK}s with an
5385 address in mode @code{Pmode}.
5387 The number of bytes to move is the third operand, in mode @var{m}.
5388 Usually, you specify @code{Pmode} for @var{m}. However, if you can
5389 generate better code knowing the range of valid lengths is smaller than
5390 those representable in a full Pmode pointer, you should provide
5392 mode corresponding to the range of values you can handle efficiently
5393 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
5394 that appear negative) and also a pattern with @code{Pmode}.
5396 The fourth operand is the known shared alignment of the source and
5397 destination, in the form of a @code{const_int} rtx. Thus, if the
5398 compiler knows that both source and destination are word-aligned,
5399 it may provide the value 4 for this operand.
5401 Optional operands 5 and 6 specify expected alignment and size of block
5402 respectively. The expected alignment differs from alignment in operand 4
5403 in a way that the blocks are not required to be aligned according to it in
5404 all cases. This expected alignment is also in bytes, just like operand 4.
5405 Expected size, when unknown, is set to @code{(const_int -1)}.
5407 Descriptions of multiple @code{movmem@var{m}} patterns can only be
5408 beneficial if the patterns for smaller modes have fewer restrictions
5409 on their first, second and fourth operands. Note that the mode @var{m}
5410 in @code{movmem@var{m}} does not impose any restriction on the mode of
5411 individually moved data units in the block.
5413 These patterns need not give special consideration to the possibility
5414 that the source and destination strings might overlap.
5416 @cindex @code{movstr} instruction pattern
5418 String copy instruction, with @code{stpcpy} semantics. Operand 0 is
5419 an output operand in mode @code{Pmode}. The addresses of the
5420 destination and source strings are operands 1 and 2, and both are
5421 @code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of
5422 the expansion of this pattern should store in operand 0 the address in
5423 which the @code{NUL} terminator was stored in the destination string.
5425 This patern has also several optional operands that are same as in
5428 @cindex @code{setmem@var{m}} instruction pattern
5429 @item @samp{setmem@var{m}}
5430 Block set instruction. The destination string is the first operand,
5431 given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The
5432 number of bytes to set is the second operand, in mode @var{m}. The value to
5433 initialize the memory with is the third operand. Targets that only support the
5434 clearing of memory should reject any value that is not the constant 0. See
5435 @samp{movmem@var{m}} for a discussion of the choice of mode.
5437 The fourth operand is the known alignment of the destination, in the form
5438 of a @code{const_int} rtx. Thus, if the compiler knows that the
5439 destination is word-aligned, it may provide the value 4 for this
5442 Optional operands 5 and 6 specify expected alignment and size of block
5443 respectively. The expected alignment differs from alignment in operand 4
5444 in a way that the blocks are not required to be aligned according to it in
5445 all cases. This expected alignment is also in bytes, just like operand 4.
5446 Expected size, when unknown, is set to @code{(const_int -1)}.
5447 Operand 7 is the minimal size of the block and operand 8 is the
5448 maximal size of the block (NULL if it can not be represented as CONST_INT).
5449 Operand 9 is the probable maximal size (i.e. we can not rely on it for correctness,
5450 but it can be used for choosing proper code sequence for a given size).
5452 The use for multiple @code{setmem@var{m}} is as for @code{movmem@var{m}}.
5454 @cindex @code{cmpstrn@var{m}} instruction pattern
5455 @item @samp{cmpstrn@var{m}}
5456 String compare instruction, with five operands. Operand 0 is the output;
5457 it has mode @var{m}. The remaining four operands are like the operands
5458 of @samp{movmem@var{m}}. The two memory blocks specified are compared
5459 byte by byte in lexicographic order starting at the beginning of each
5460 string. The instruction is not allowed to prefetch more than one byte
5461 at a time since either string may end in the first byte and reading past
5462 that may access an invalid page or segment and cause a fault. The
5463 comparison terminates early if the fetched bytes are different or if
5464 they are equal to zero. The effect of the instruction is to store a
5465 value in operand 0 whose sign indicates the result of the comparison.
5467 @cindex @code{cmpstr@var{m}} instruction pattern
5468 @item @samp{cmpstr@var{m}}
5469 String compare instruction, without known maximum length. Operand 0 is the
5470 output; it has mode @var{m}. The second and third operand are the blocks of
5471 memory to be compared; both are @code{mem:BLK} with an address in mode
5474 The fourth operand is the known shared alignment of the source and
5475 destination, in the form of a @code{const_int} rtx. Thus, if the
5476 compiler knows that both source and destination are word-aligned,
5477 it may provide the value 4 for this operand.
5479 The two memory blocks specified are compared byte by byte in lexicographic
5480 order starting at the beginning of each string. The instruction is not allowed
5481 to prefetch more than one byte at a time since either string may end in the
5482 first byte and reading past that may access an invalid page or segment and
5483 cause a fault. The comparison will terminate when the fetched bytes
5484 are different or if they are equal to zero. The effect of the
5485 instruction is to store a value in operand 0 whose sign indicates the
5486 result of the comparison.
5488 @cindex @code{cmpmem@var{m}} instruction pattern
5489 @item @samp{cmpmem@var{m}}
5490 Block compare instruction, with five operands like the operands
5491 of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
5492 byte by byte in lexicographic order starting at the beginning of each
5493 block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
5494 any bytes in the two memory blocks. Also unlike @samp{cmpstr@var{m}}
5495 the comparison will not stop if both bytes are zero. The effect of
5496 the instruction is to store a value in operand 0 whose sign indicates
5497 the result of the comparison.
5499 @cindex @code{strlen@var{m}} instruction pattern
5500 @item @samp{strlen@var{m}}
5501 Compute the length of a string, with three operands.
5502 Operand 0 is the result (of mode @var{m}), operand 1 is
5503 a @code{mem} referring to the first character of the string,
5504 operand 2 is the character to search for (normally zero),
5505 and operand 3 is a constant describing the known alignment
5506 of the beginning of the string.
5508 @cindex @code{float@var{m}@var{n}2} instruction pattern
5509 @item @samp{float@var{m}@var{n}2}
5510 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
5511 floating point mode @var{n} and store in operand 0 (which has mode
5514 @cindex @code{floatuns@var{m}@var{n}2} instruction pattern
5515 @item @samp{floatuns@var{m}@var{n}2}
5516 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
5517 to floating point mode @var{n} and store in operand 0 (which has mode
5520 @cindex @code{fix@var{m}@var{n}2} instruction pattern
5521 @item @samp{fix@var{m}@var{n}2}
5522 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5523 point mode @var{n} as a signed number and store in operand 0 (which
5524 has mode @var{n}). This instruction's result is defined only when
5525 the value of operand 1 is an integer.
5527 If the machine description defines this pattern, it also needs to
5528 define the @code{ftrunc} pattern.
5530 @cindex @code{fixuns@var{m}@var{n}2} instruction pattern
5531 @item @samp{fixuns@var{m}@var{n}2}
5532 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5533 point mode @var{n} as an unsigned number and store in operand 0 (which
5534 has mode @var{n}). This instruction's result is defined only when the
5535 value of operand 1 is an integer.
5537 @cindex @code{ftrunc@var{m}2} instruction pattern
5538 @item @samp{ftrunc@var{m}2}
5539 Convert operand 1 (valid for floating point mode @var{m}) to an
5540 integer value, still represented in floating point mode @var{m}, and
5541 store it in operand 0 (valid for floating point mode @var{m}).
5543 @cindex @code{fix_trunc@var{m}@var{n}2} instruction pattern
5544 @item @samp{fix_trunc@var{m}@var{n}2}
5545 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
5546 of mode @var{m} by converting the value to an integer.
5548 @cindex @code{fixuns_trunc@var{m}@var{n}2} instruction pattern
5549 @item @samp{fixuns_trunc@var{m}@var{n}2}
5550 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
5551 value of mode @var{m} by converting the value to an integer.
5553 @cindex @code{trunc@var{m}@var{n}2} instruction pattern
5554 @item @samp{trunc@var{m}@var{n}2}
5555 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
5556 store in operand 0 (which has mode @var{n}). Both modes must be fixed
5557 point or both floating point.
5559 @cindex @code{extend@var{m}@var{n}2} instruction pattern
5560 @item @samp{extend@var{m}@var{n}2}
5561 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
5562 store in operand 0 (which has mode @var{n}). Both modes must be fixed
5563 point or both floating point.
5565 @cindex @code{zero_extend@var{m}@var{n}2} instruction pattern
5566 @item @samp{zero_extend@var{m}@var{n}2}
5567 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
5568 store in operand 0 (which has mode @var{n}). Both modes must be fixed
5571 @cindex @code{fract@var{m}@var{n}2} instruction pattern
5572 @item @samp{fract@var{m}@var{n}2}
5573 Convert operand 1 of mode @var{m} to mode @var{n} and store in
5574 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
5575 could be fixed-point to fixed-point, signed integer to fixed-point,
5576 fixed-point to signed integer, floating-point to fixed-point,
5577 or fixed-point to floating-point.
5578 When overflows or underflows happen, the results are undefined.
5580 @cindex @code{satfract@var{m}@var{n}2} instruction pattern
5581 @item @samp{satfract@var{m}@var{n}2}
5582 Convert operand 1 of mode @var{m} to mode @var{n} and store in
5583 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
5584 could be fixed-point to fixed-point, signed integer to fixed-point,
5585 or floating-point to fixed-point.
5586 When overflows or underflows happen, the instruction saturates the
5587 results to the maximum or the minimum.
5589 @cindex @code{fractuns@var{m}@var{n}2} instruction pattern
5590 @item @samp{fractuns@var{m}@var{n}2}
5591 Convert operand 1 of mode @var{m} to mode @var{n} and store in
5592 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
5593 could be unsigned integer to fixed-point, or
5594 fixed-point to unsigned integer.
5595 When overflows or underflows happen, the results are undefined.
5597 @cindex @code{satfractuns@var{m}@var{n}2} instruction pattern
5598 @item @samp{satfractuns@var{m}@var{n}2}
5599 Convert unsigned integer operand 1 of mode @var{m} to fixed-point mode
5600 @var{n} and store in operand 0 (which has mode @var{n}).
5601 When overflows or underflows happen, the instruction saturates the
5602 results to the maximum or the minimum.
5604 @cindex @code{extv@var{m}} instruction pattern
5605 @item @samp{extv@var{m}}
5606 Extract a bit-field from register operand 1, sign-extend it, and store
5607 it in operand 0. Operand 2 specifies the width of the field in bits
5608 and operand 3 the starting bit, which counts from the most significant
5609 bit if @samp{BITS_BIG_ENDIAN} is true and from the least significant bit
5612 Operands 0 and 1 both have mode @var{m}. Operands 2 and 3 have a
5613 target-specific mode.
5615 @cindex @code{extvmisalign@var{m}} instruction pattern
5616 @item @samp{extvmisalign@var{m}}
5617 Extract a bit-field from memory operand 1, sign extend it, and store
5618 it in operand 0. Operand 2 specifies the width in bits and operand 3
5619 the starting bit. The starting bit is always somewhere in the first byte of
5620 operand 1; it counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
5621 is true and from the least significant bit otherwise.
5623 Operand 0 has mode @var{m} while operand 1 has @code{BLK} mode.
5624 Operands 2 and 3 have a target-specific mode.
5626 The instruction must not read beyond the last byte of the bit-field.
5628 @cindex @code{extzv@var{m}} instruction pattern
5629 @item @samp{extzv@var{m}}
5630 Like @samp{extv@var{m}} except that the bit-field value is zero-extended.
5632 @cindex @code{extzvmisalign@var{m}} instruction pattern
5633 @item @samp{extzvmisalign@var{m}}
5634 Like @samp{extvmisalign@var{m}} except that the bit-field value is
5637 @cindex @code{insv@var{m}} instruction pattern
5638 @item @samp{insv@var{m}}
5639 Insert operand 3 into a bit-field of register operand 0. Operand 1
5640 specifies the width of the field in bits and operand 2 the starting bit,
5641 which counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
5642 is true and from the least significant bit otherwise.
5644 Operands 0 and 3 both have mode @var{m}. Operands 1 and 2 have a
5645 target-specific mode.
5647 @cindex @code{insvmisalign@var{m}} instruction pattern
5648 @item @samp{insvmisalign@var{m}}
5649 Insert operand 3 into a bit-field of memory operand 0. Operand 1
5650 specifies the width of the field in bits and operand 2 the starting bit.
5651 The starting bit is always somewhere in the first byte of operand 0;
5652 it counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
5653 is true and from the least significant bit otherwise.
5655 Operand 3 has mode @var{m} while operand 0 has @code{BLK} mode.
5656 Operands 1 and 2 have a target-specific mode.
5658 The instruction must not read or write beyond the last byte of the bit-field.
5660 @cindex @code{extv} instruction pattern
5662 Extract a bit-field from operand 1 (a register or memory operand), where
5663 operand 2 specifies the width in bits and operand 3 the starting bit,
5664 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
5665 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
5666 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
5667 be valid for @code{word_mode}.
5669 The RTL generation pass generates this instruction only with constants
5670 for operands 2 and 3 and the constant is never zero for operand 2.
5672 The bit-field value is sign-extended to a full word integer
5673 before it is stored in operand 0.
5675 This pattern is deprecated; please use @samp{extv@var{m}} and
5676 @code{extvmisalign@var{m}} instead.
5678 @cindex @code{extzv} instruction pattern
5680 Like @samp{extv} except that the bit-field value is zero-extended.
5682 This pattern is deprecated; please use @samp{extzv@var{m}} and
5683 @code{extzvmisalign@var{m}} instead.
5685 @cindex @code{insv} instruction pattern
5687 Store operand 3 (which must be valid for @code{word_mode}) into a
5688 bit-field in operand 0, where operand 1 specifies the width in bits and
5689 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
5690 @code{word_mode}; often @code{word_mode} is allowed only for registers.
5691 Operands 1 and 2 must be valid for @code{word_mode}.
5693 The RTL generation pass generates this instruction only with constants
5694 for operands 1 and 2 and the constant is never zero for operand 1.
5696 This pattern is deprecated; please use @samp{insv@var{m}} and
5697 @code{insvmisalign@var{m}} instead.
5699 @cindex @code{mov@var{mode}cc} instruction pattern
5700 @item @samp{mov@var{mode}cc}
5701 Conditionally move operand 2 or operand 3 into operand 0 according to the
5702 comparison in operand 1. If the comparison is true, operand 2 is moved
5703 into operand 0, otherwise operand 3 is moved.
5705 The mode of the operands being compared need not be the same as the operands
5706 being moved. Some machines, sparc64 for example, have instructions that
5707 conditionally move an integer value based on the floating point condition
5708 codes and vice versa.
5710 If the machine does not have conditional move instructions, do not
5711 define these patterns.
5713 @cindex @code{add@var{mode}cc} instruction pattern
5714 @item @samp{add@var{mode}cc}
5715 Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
5716 move operand 2 or (operands 2 + operand 3) into operand 0 according to the
5717 comparison in operand 1. If the comparison is false, operand 2 is moved into
5718 operand 0, otherwise (operand 2 + operand 3) is moved.
5720 @cindex @code{cstore@var{mode}4} instruction pattern
5721 @item @samp{cstore@var{mode}4}
5722 Store zero or nonzero in operand 0 according to whether a comparison
5723 is true. Operand 1 is a comparison operator. Operand 2 and operand 3
5724 are the first and second operand of the comparison, respectively.
5725 You specify the mode that operand 0 must have when you write the
5726 @code{match_operand} expression. The compiler automatically sees which
5727 mode you have used and supplies an operand of that mode.
5729 The value stored for a true condition must have 1 as its low bit, or
5730 else must be negative. Otherwise the instruction is not suitable and
5731 you should omit it from the machine description. You describe to the
5732 compiler exactly which value is stored by defining the macro
5733 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
5734 found that can be used for all the possible comparison operators, you
5735 should pick one and use a @code{define_expand} to map all results
5736 onto the one you chose.
5738 These operations may @code{FAIL}, but should do so only in relatively
5739 uncommon cases; if they would @code{FAIL} for common cases involving
5740 integer comparisons, it is best to restrict the predicates to not
5741 allow these operands. Likewise if a given comparison operator will
5742 always fail, independent of the operands (for floating-point modes, the
5743 @code{ordered_comparison_operator} predicate is often useful in this case).
5745 If this pattern is omitted, the compiler will generate a conditional
5746 branch---for example, it may copy a constant one to the target and branching
5747 around an assignment of zero to the target---or a libcall. If the predicate
5748 for operand 1 only rejects some operators, it will also try reordering the
5749 operands and/or inverting the result value (e.g.@: by an exclusive OR).
5750 These possibilities could be cheaper or equivalent to the instructions
5751 used for the @samp{cstore@var{mode}4} pattern followed by those required
5752 to convert a positive result from @code{STORE_FLAG_VALUE} to 1; in this
5753 case, you can and should make operand 1's predicate reject some operators
5754 in the @samp{cstore@var{mode}4} pattern, or remove the pattern altogether
5755 from the machine description.
5757 @cindex @code{cbranch@var{mode}4} instruction pattern
5758 @item @samp{cbranch@var{mode}4}
5759 Conditional branch instruction combined with a compare instruction.
5760 Operand 0 is a comparison operator. Operand 1 and operand 2 are the
5761 first and second operands of the comparison, respectively. Operand 3
5762 is a @code{label_ref} that refers to the label to jump to.
5764 @cindex @code{jump} instruction pattern
5766 A jump inside a function; an unconditional branch. Operand 0 is the
5767 @code{label_ref} of the label to jump to. This pattern name is mandatory
5770 @cindex @code{call} instruction pattern
5772 Subroutine call instruction returning no value. Operand 0 is the
5773 function to call; operand 1 is the number of bytes of arguments pushed
5774 as a @code{const_int}; operand 2 is the number of registers used as
5777 On most machines, operand 2 is not actually stored into the RTL
5778 pattern. It is supplied for the sake of some RISC machines which need
5779 to put this information into the assembler code; they can put it in
5780 the RTL instead of operand 1.
5782 Operand 0 should be a @code{mem} RTX whose address is the address of the
5783 function. Note, however, that this address can be a @code{symbol_ref}
5784 expression even if it would not be a legitimate memory address on the
5785 target machine. If it is also not a valid argument for a call
5786 instruction, the pattern for this operation should be a
5787 @code{define_expand} (@pxref{Expander Definitions}) that places the
5788 address into a register and uses that register in the call instruction.
5790 @cindex @code{call_value} instruction pattern
5791 @item @samp{call_value}
5792 Subroutine call instruction returning a value. Operand 0 is the hard
5793 register in which the value is returned. There are three more
5794 operands, the same as the three operands of the @samp{call}
5795 instruction (but with numbers increased by one).
5797 Subroutines that return @code{BLKmode} objects use the @samp{call}
5800 @cindex @code{call_pop} instruction pattern
5801 @cindex @code{call_value_pop} instruction pattern
5802 @item @samp{call_pop}, @samp{call_value_pop}
5803 Similar to @samp{call} and @samp{call_value}, except used if defined and
5804 if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
5805 that contains both the function call and a @code{set} to indicate the
5806 adjustment made to the frame pointer.
5808 For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
5809 patterns increases the number of functions for which the frame pointer
5810 can be eliminated, if desired.
5812 @cindex @code{untyped_call} instruction pattern
5813 @item @samp{untyped_call}
5814 Subroutine call instruction returning a value of any type. Operand 0 is
5815 the function to call; operand 1 is a memory location where the result of
5816 calling the function is to be stored; operand 2 is a @code{parallel}
5817 expression where each element is a @code{set} expression that indicates
5818 the saving of a function return value into the result block.
5820 This instruction pattern should be defined to support
5821 @code{__builtin_apply} on machines where special instructions are needed
5822 to call a subroutine with arbitrary arguments or to save the value
5823 returned. This instruction pattern is required on machines that have
5824 multiple registers that can hold a return value
5825 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
5827 @cindex @code{return} instruction pattern
5829 Subroutine return instruction. This instruction pattern name should be
5830 defined only if a single instruction can do all the work of returning
5833 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
5834 RTL generation phase. In this case it is to support machines where
5835 multiple instructions are usually needed to return from a function, but
5836 some class of functions only requires one instruction to implement a
5837 return. Normally, the applicable functions are those which do not need
5838 to save any registers or allocate stack space.
5840 It is valid for this pattern to expand to an instruction using
5841 @code{simple_return} if no epilogue is required.
5843 @cindex @code{simple_return} instruction pattern
5844 @item @samp{simple_return}
5845 Subroutine return instruction. This instruction pattern name should be
5846 defined only if a single instruction can do all the work of returning
5847 from a function on a path where no epilogue is required. This pattern
5848 is very similar to the @code{return} instruction pattern, but it is emitted
5849 only by the shrink-wrapping optimization on paths where the function
5850 prologue has not been executed, and a function return should occur without
5851 any of the effects of the epilogue. Additional uses may be introduced on
5852 paths where both the prologue and the epilogue have executed.
5854 @findex reload_completed
5855 @findex leaf_function_p
5856 For such machines, the condition specified in this pattern should only
5857 be true when @code{reload_completed} is nonzero and the function's
5858 epilogue would only be a single instruction. For machines with register
5859 windows, the routine @code{leaf_function_p} may be used to determine if
5860 a register window push is required.
5862 Machines that have conditional return instructions should define patterns
5868 (if_then_else (match_operator
5869 0 "comparison_operator"
5870 [(cc0) (const_int 0)])
5877 where @var{condition} would normally be the same condition specified on the
5878 named @samp{return} pattern.
5880 @cindex @code{untyped_return} instruction pattern
5881 @item @samp{untyped_return}
5882 Untyped subroutine return instruction. This instruction pattern should
5883 be defined to support @code{__builtin_return} on machines where special
5884 instructions are needed to return a value of any type.
5886 Operand 0 is a memory location where the result of calling a function
5887 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
5888 expression where each element is a @code{set} expression that indicates
5889 the restoring of a function return value from the result block.
5891 @cindex @code{nop} instruction pattern
5893 No-op instruction. This instruction pattern name should always be defined
5894 to output a no-op in assembler code. @code{(const_int 0)} will do as an
5897 @cindex @code{indirect_jump} instruction pattern
5898 @item @samp{indirect_jump}
5899 An instruction to jump to an address which is operand zero.
5900 This pattern name is mandatory on all machines.
5902 @cindex @code{casesi} instruction pattern
5904 Instruction to jump through a dispatch table, including bounds checking.
5905 This instruction takes five operands:
5909 The index to dispatch on, which has mode @code{SImode}.
5912 The lower bound for indices in the table, an integer constant.
5915 The total range of indices in the table---the largest index
5916 minus the smallest one (both inclusive).
5919 A label that precedes the table itself.
5922 A label to jump to if the index has a value outside the bounds.
5925 The table is an @code{addr_vec} or @code{addr_diff_vec} inside of a
5926 @code{jump_table_data}. The number of elements in the table is one plus the
5927 difference between the upper bound and the lower bound.
5929 @cindex @code{tablejump} instruction pattern
5930 @item @samp{tablejump}
5931 Instruction to jump to a variable address. This is a low-level
5932 capability which can be used to implement a dispatch table when there
5933 is no @samp{casesi} pattern.
5935 This pattern requires two operands: the address or offset, and a label
5936 which should immediately precede the jump table. If the macro
5937 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
5938 operand is an offset which counts from the address of the table; otherwise,
5939 it is an absolute address to jump to. In either case, the first operand has
5942 The @samp{tablejump} insn is always the last insn before the jump
5943 table it uses. Its assembler code normally has no need to use the
5944 second operand, but you should incorporate it in the RTL pattern so
5945 that the jump optimizer will not delete the table as unreachable code.
5948 @cindex @code{decrement_and_branch_until_zero} instruction pattern
5949 @item @samp{decrement_and_branch_until_zero}
5950 Conditional branch instruction that decrements a register and
5951 jumps if the register is nonzero. Operand 0 is the register to
5952 decrement and test; operand 1 is the label to jump to if the
5953 register is nonzero. @xref{Looping Patterns}.
5955 This optional instruction pattern is only used by the combiner,
5956 typically for loops reversed by the loop optimizer when strength
5957 reduction is enabled.
5959 @cindex @code{doloop_end} instruction pattern
5960 @item @samp{doloop_end}
5961 Conditional branch instruction that decrements a register and
5962 jumps if the register is nonzero. Operand 0 is the register to
5963 decrement and test; operand 1 is the label to jump to if the
5964 register is nonzero.
5965 @xref{Looping Patterns}.
5967 This optional instruction pattern should be defined for machines with
5968 low-overhead looping instructions as the loop optimizer will try to
5969 modify suitable loops to utilize it. The target hook
5970 @code{TARGET_CAN_USE_DOLOOP_P} controls the conditions under which
5971 low-overhead loops can be used.
5973 @cindex @code{doloop_begin} instruction pattern
5974 @item @samp{doloop_begin}
5975 Companion instruction to @code{doloop_end} required for machines that
5976 need to perform some initialization, such as loading a special counter
5977 register. Operand 1 is the associated @code{doloop_end} pattern and
5978 operand 0 is the register that it decrements.
5980 If initialization insns do not always need to be emitted, use a
5981 @code{define_expand} (@pxref{Expander Definitions}) and make it fail.
5983 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
5984 @item @samp{canonicalize_funcptr_for_compare}
5985 Canonicalize the function pointer in operand 1 and store the result
5988 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
5989 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
5990 and also has mode @code{Pmode}.
5992 Canonicalization of a function pointer usually involves computing
5993 the address of the function which would be called if the function
5994 pointer were used in an indirect call.
5996 Only define this pattern if function pointers on the target machine
5997 can have different values but still call the same function when
5998 used in an indirect call.
6000 @cindex @code{save_stack_block} instruction pattern
6001 @cindex @code{save_stack_function} instruction pattern
6002 @cindex @code{save_stack_nonlocal} instruction pattern
6003 @cindex @code{restore_stack_block} instruction pattern
6004 @cindex @code{restore_stack_function} instruction pattern
6005 @cindex @code{restore_stack_nonlocal} instruction pattern
6006 @item @samp{save_stack_block}
6007 @itemx @samp{save_stack_function}
6008 @itemx @samp{save_stack_nonlocal}
6009 @itemx @samp{restore_stack_block}
6010 @itemx @samp{restore_stack_function}
6011 @itemx @samp{restore_stack_nonlocal}
6012 Most machines save and restore the stack pointer by copying it to or
6013 from an object of mode @code{Pmode}. Do not define these patterns on
6016 Some machines require special handling for stack pointer saves and
6017 restores. On those machines, define the patterns corresponding to the
6018 non-standard cases by using a @code{define_expand} (@pxref{Expander
6019 Definitions}) that produces the required insns. The three types of
6020 saves and restores are:
6024 @samp{save_stack_block} saves the stack pointer at the start of a block
6025 that allocates a variable-sized object, and @samp{restore_stack_block}
6026 restores the stack pointer when the block is exited.
6029 @samp{save_stack_function} and @samp{restore_stack_function} do a
6030 similar job for the outermost block of a function and are used when the
6031 function allocates variable-sized objects or calls @code{alloca}. Only
6032 the epilogue uses the restored stack pointer, allowing a simpler save or
6033 restore sequence on some machines.
6036 @samp{save_stack_nonlocal} is used in functions that contain labels
6037 branched to by nested functions. It saves the stack pointer in such a
6038 way that the inner function can use @samp{restore_stack_nonlocal} to
6039 restore the stack pointer. The compiler generates code to restore the
6040 frame and argument pointer registers, but some machines require saving
6041 and restoring additional data such as register window information or
6042 stack backchains. Place insns in these patterns to save and restore any
6046 When saving the stack pointer, operand 0 is the save area and operand 1
6047 is the stack pointer. The mode used to allocate the save area defaults
6048 to @code{Pmode} but you can override that choice by defining the
6049 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
6050 specify an integral mode, or @code{VOIDmode} if no save area is needed
6051 for a particular type of save (either because no save is needed or
6052 because a machine-specific save area can be used). Operand 0 is the
6053 stack pointer and operand 1 is the save area for restore operations. If
6054 @samp{save_stack_block} is defined, operand 0 must not be
6055 @code{VOIDmode} since these saves can be arbitrarily nested.
6057 A save area is a @code{mem} that is at a constant offset from
6058 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
6059 nonlocal gotos and a @code{reg} in the other two cases.
6061 @cindex @code{allocate_stack} instruction pattern
6062 @item @samp{allocate_stack}
6063 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
6064 the stack pointer to create space for dynamically allocated data.
6066 Store the resultant pointer to this space into operand 0. If you
6067 are allocating space from the main stack, do this by emitting a
6068 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
6069 If you are allocating the space elsewhere, generate code to copy the
6070 location of the space to operand 0. In the latter case, you must
6071 ensure this space gets freed when the corresponding space on the main
6074 Do not define this pattern if all that must be done is the subtraction.
6075 Some machines require other operations such as stack probes or
6076 maintaining the back chain. Define this pattern to emit those
6077 operations in addition to updating the stack pointer.
6079 @cindex @code{check_stack} instruction pattern
6080 @item @samp{check_stack}
6081 If stack checking (@pxref{Stack Checking}) cannot be done on your system by
6082 probing the stack, define this pattern to perform the needed check and signal
6083 an error if the stack has overflowed. The single operand is the address in
6084 the stack farthest from the current stack pointer that you need to validate.
6085 Normally, on platforms where this pattern is needed, you would obtain the
6086 stack limit from a global or thread-specific variable or register.
6088 @cindex @code{probe_stack_address} instruction pattern
6089 @item @samp{probe_stack_address}
6090 If stack checking (@pxref{Stack Checking}) can be done on your system by
6091 probing the stack but without the need to actually access it, define this
6092 pattern and signal an error if the stack has overflowed. The single operand
6093 is the memory address in the stack that needs to be probed.
6095 @cindex @code{probe_stack} instruction pattern
6096 @item @samp{probe_stack}
6097 If stack checking (@pxref{Stack Checking}) can be done on your system by
6098 probing the stack but doing it with a ``store zero'' instruction is not valid
6099 or optimal, define this pattern to do the probing differently and signal an
6100 error if the stack has overflowed. The single operand is the memory reference
6101 in the stack that needs to be probed.
6103 @cindex @code{nonlocal_goto} instruction pattern
6104 @item @samp{nonlocal_goto}
6105 Emit code to generate a non-local goto, e.g., a jump from one function
6106 to a label in an outer function. This pattern has four arguments,
6107 each representing a value to be used in the jump. The first
6108 argument is to be loaded into the frame pointer, the second is
6109 the address to branch to (code to dispatch to the actual label),
6110 the third is the address of a location where the stack is saved,
6111 and the last is the address of the label, to be placed in the
6112 location for the incoming static chain.
6114 On most machines you need not define this pattern, since GCC will
6115 already generate the correct code, which is to load the frame pointer
6116 and static chain, restore the stack (using the
6117 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
6118 to the dispatcher. You need only define this pattern if this code will
6119 not work on your machine.
6121 @cindex @code{nonlocal_goto_receiver} instruction pattern
6122 @item @samp{nonlocal_goto_receiver}
6123 This pattern, if defined, contains code needed at the target of a
6124 nonlocal goto after the code already generated by GCC@. You will not
6125 normally need to define this pattern. A typical reason why you might
6126 need this pattern is if some value, such as a pointer to a global table,
6127 must be restored when the frame pointer is restored. Note that a nonlocal
6128 goto only occurs within a unit-of-translation, so a global table pointer
6129 that is shared by all functions of a given module need not be restored.
6130 There are no arguments.
6132 @cindex @code{exception_receiver} instruction pattern
6133 @item @samp{exception_receiver}
6134 This pattern, if defined, contains code needed at the site of an
6135 exception handler that isn't needed at the site of a nonlocal goto. You
6136 will not normally need to define this pattern. A typical reason why you
6137 might need this pattern is if some value, such as a pointer to a global
6138 table, must be restored after control flow is branched to the handler of
6139 an exception. There are no arguments.
6141 @cindex @code{builtin_setjmp_setup} instruction pattern
6142 @item @samp{builtin_setjmp_setup}
6143 This pattern, if defined, contains additional code needed to initialize
6144 the @code{jmp_buf}. You will not normally need to define this pattern.
6145 A typical reason why you might need this pattern is if some value, such
6146 as a pointer to a global table, must be restored. Though it is
6147 preferred that the pointer value be recalculated if possible (given the
6148 address of a label for instance). The single argument is a pointer to
6149 the @code{jmp_buf}. Note that the buffer is five words long and that
6150 the first three are normally used by the generic mechanism.
6152 @cindex @code{builtin_setjmp_receiver} instruction pattern
6153 @item @samp{builtin_setjmp_receiver}
6154 This pattern, if defined, contains code needed at the site of a
6155 built-in setjmp that isn't needed at the site of a nonlocal goto. You
6156 will not normally need to define this pattern. A typical reason why you
6157 might need this pattern is if some value, such as a pointer to a global
6158 table, must be restored. It takes one argument, which is the label
6159 to which builtin_longjmp transferred control; this pattern may be emitted
6160 at a small offset from that label.
6162 @cindex @code{builtin_longjmp} instruction pattern
6163 @item @samp{builtin_longjmp}
6164 This pattern, if defined, performs the entire action of the longjmp.
6165 You will not normally need to define this pattern unless you also define
6166 @code{builtin_setjmp_setup}. The single argument is a pointer to the
6169 @cindex @code{eh_return} instruction pattern
6170 @item @samp{eh_return}
6171 This pattern, if defined, affects the way @code{__builtin_eh_return},
6172 and thence the call frame exception handling library routines, are
6173 built. It is intended to handle non-trivial actions needed along
6174 the abnormal return path.
6176 The address of the exception handler to which the function should return
6177 is passed as operand to this pattern. It will normally need to copied by
6178 the pattern to some special register or memory location.
6179 If the pattern needs to determine the location of the target call
6180 frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX},
6181 if defined; it will have already been assigned.
6183 If this pattern is not defined, the default action will be to simply
6184 copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
6185 that macro or this pattern needs to be defined if call frame exception
6186 handling is to be used.
6188 @cindex @code{prologue} instruction pattern
6189 @anchor{prologue instruction pattern}
6190 @item @samp{prologue}
6191 This pattern, if defined, emits RTL for entry to a function. The function
6192 entry is responsible for setting up the stack frame, initializing the frame
6193 pointer register, saving callee saved registers, etc.
6195 Using a prologue pattern is generally preferred over defining
6196 @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
6198 The @code{prologue} pattern is particularly useful for targets which perform
6199 instruction scheduling.
6201 @cindex @code{window_save} instruction pattern
6202 @anchor{window_save instruction pattern}
6203 @item @samp{window_save}
6204 This pattern, if defined, emits RTL for a register window save. It should
6205 be defined if the target machine has register windows but the window events
6206 are decoupled from calls to subroutines. The canonical example is the SPARC
6209 @cindex @code{epilogue} instruction pattern
6210 @anchor{epilogue instruction pattern}
6211 @item @samp{epilogue}
6212 This pattern emits RTL for exit from a function. The function
6213 exit is responsible for deallocating the stack frame, restoring callee saved
6214 registers and emitting the return instruction.
6216 Using an epilogue pattern is generally preferred over defining
6217 @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
6219 The @code{epilogue} pattern is particularly useful for targets which perform
6220 instruction scheduling or which have delay slots for their return instruction.
6222 @cindex @code{sibcall_epilogue} instruction pattern
6223 @item @samp{sibcall_epilogue}
6224 This pattern, if defined, emits RTL for exit from a function without the final
6225 branch back to the calling function. This pattern will be emitted before any
6226 sibling call (aka tail call) sites.
6228 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
6229 parameter passing or any stack slots for arguments passed to the current
6232 @cindex @code{trap} instruction pattern
6234 This pattern, if defined, signals an error, typically by causing some
6235 kind of signal to be raised. Among other places, it is used by the Java
6236 front end to signal `invalid array index' exceptions.
6238 @cindex @code{ctrap@var{MM}4} instruction pattern
6239 @item @samp{ctrap@var{MM}4}
6240 Conditional trap instruction. Operand 0 is a piece of RTL which
6241 performs a comparison, and operands 1 and 2 are the arms of the
6242 comparison. Operand 3 is the trap code, an integer.
6244 A typical @code{ctrap} pattern looks like
6247 (define_insn "ctrapsi4"
6248 [(trap_if (match_operator 0 "trap_operator"
6249 [(match_operand 1 "register_operand")
6250 (match_operand 2 "immediate_operand")])
6251 (match_operand 3 "const_int_operand" "i"))]
6256 @cindex @code{prefetch} instruction pattern
6257 @item @samp{prefetch}
6258 This pattern, if defined, emits code for a non-faulting data prefetch
6259 instruction. Operand 0 is the address of the memory to prefetch. Operand 1
6260 is a constant 1 if the prefetch is preparing for a write to the memory
6261 address, or a constant 0 otherwise. Operand 2 is the expected degree of
6262 temporal locality of the data and is a value between 0 and 3, inclusive; 0
6263 means that the data has no temporal locality, so it need not be left in the
6264 cache after the access; 3 means that the data has a high degree of temporal
6265 locality and should be left in all levels of cache possible; 1 and 2 mean,
6266 respectively, a low or moderate degree of temporal locality.
6268 Targets that do not support write prefetches or locality hints can ignore
6269 the values of operands 1 and 2.
6271 @cindex @code{blockage} instruction pattern
6272 @item @samp{blockage}
6273 This pattern defines a pseudo insn that prevents the instruction
6274 scheduler and other passes from moving instructions and using register
6275 equivalences across the boundary defined by the blockage insn.
6276 This needs to be an UNSPEC_VOLATILE pattern or a volatile ASM.
6278 @cindex @code{memory_barrier} instruction pattern
6279 @item @samp{memory_barrier}
6280 If the target memory model is not fully synchronous, then this pattern
6281 should be defined to an instruction that orders both loads and stores
6282 before the instruction with respect to loads and stores after the instruction.
6283 This pattern has no operands.
6285 @cindex @code{sync_compare_and_swap@var{mode}} instruction pattern
6286 @item @samp{sync_compare_and_swap@var{mode}}
6287 This pattern, if defined, emits code for an atomic compare-and-swap
6288 operation. Operand 1 is the memory on which the atomic operation is
6289 performed. Operand 2 is the ``old'' value to be compared against the
6290 current contents of the memory location. Operand 3 is the ``new'' value
6291 to store in the memory if the compare succeeds. Operand 0 is the result
6292 of the operation; it should contain the contents of the memory
6293 before the operation. If the compare succeeds, this should obviously be
6294 a copy of operand 2.
6296 This pattern must show that both operand 0 and operand 1 are modified.
6298 This pattern must issue any memory barrier instructions such that all
6299 memory operations before the atomic operation occur before the atomic
6300 operation and all memory operations after the atomic operation occur
6301 after the atomic operation.
6303 For targets where the success or failure of the compare-and-swap
6304 operation is available via the status flags, it is possible to
6305 avoid a separate compare operation and issue the subsequent
6306 branch or store-flag operation immediately after the compare-and-swap.
6307 To this end, GCC will look for a @code{MODE_CC} set in the
6308 output of @code{sync_compare_and_swap@var{mode}}; if the machine
6309 description includes such a set, the target should also define special
6310 @code{cbranchcc4} and/or @code{cstorecc4} instructions. GCC will then
6311 be able to take the destination of the @code{MODE_CC} set and pass it
6312 to the @code{cbranchcc4} or @code{cstorecc4} pattern as the first
6313 operand of the comparison (the second will be @code{(const_int 0)}).
6315 For targets where the operating system may provide support for this
6316 operation via library calls, the @code{sync_compare_and_swap_optab}
6317 may be initialized to a function with the same interface as the
6318 @code{__sync_val_compare_and_swap_@var{n}} built-in. If the entire
6319 set of @var{__sync} builtins are supported via library calls, the
6320 target can initialize all of the optabs at once with
6321 @code{init_sync_libfuncs}.
6322 For the purposes of C++11 @code{std::atomic::is_lock_free}, it is
6323 assumed that these library calls do @emph{not} use any kind of
6324 interruptable locking.
6326 @cindex @code{sync_add@var{mode}} instruction pattern
6327 @cindex @code{sync_sub@var{mode}} instruction pattern
6328 @cindex @code{sync_ior@var{mode}} instruction pattern
6329 @cindex @code{sync_and@var{mode}} instruction pattern
6330 @cindex @code{sync_xor@var{mode}} instruction pattern
6331 @cindex @code{sync_nand@var{mode}} instruction pattern
6332 @item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}}
6333 @itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}}
6334 @itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}}
6335 These patterns emit code for an atomic operation on memory.
6336 Operand 0 is the memory on which the atomic operation is performed.
6337 Operand 1 is the second operand to the binary operator.
6339 This pattern must issue any memory barrier instructions such that all
6340 memory operations before the atomic operation occur before the atomic
6341 operation and all memory operations after the atomic operation occur
6342 after the atomic operation.
6344 If these patterns are not defined, the operation will be constructed
6345 from a compare-and-swap operation, if defined.
6347 @cindex @code{sync_old_add@var{mode}} instruction pattern
6348 @cindex @code{sync_old_sub@var{mode}} instruction pattern
6349 @cindex @code{sync_old_ior@var{mode}} instruction pattern
6350 @cindex @code{sync_old_and@var{mode}} instruction pattern
6351 @cindex @code{sync_old_xor@var{mode}} instruction pattern
6352 @cindex @code{sync_old_nand@var{mode}} instruction pattern
6353 @item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}}
6354 @itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}}
6355 @itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}}
6356 These patterns emit code for an atomic operation on memory,
6357 and return the value that the memory contained before the operation.
6358 Operand 0 is the result value, operand 1 is the memory on which the
6359 atomic operation is performed, and operand 2 is the second operand
6360 to the binary operator.
6362 This pattern must issue any memory barrier instructions such that all
6363 memory operations before the atomic operation occur before the atomic
6364 operation and all memory operations after the atomic operation occur
6365 after the atomic operation.
6367 If these patterns are not defined, the operation will be constructed
6368 from a compare-and-swap operation, if defined.
6370 @cindex @code{sync_new_add@var{mode}} instruction pattern
6371 @cindex @code{sync_new_sub@var{mode}} instruction pattern
6372 @cindex @code{sync_new_ior@var{mode}} instruction pattern
6373 @cindex @code{sync_new_and@var{mode}} instruction pattern
6374 @cindex @code{sync_new_xor@var{mode}} instruction pattern
6375 @cindex @code{sync_new_nand@var{mode}} instruction pattern
6376 @item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}}
6377 @itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}}
6378 @itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}}
6379 These patterns are like their @code{sync_old_@var{op}} counterparts,
6380 except that they return the value that exists in the memory location
6381 after the operation, rather than before the operation.
6383 @cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern
6384 @item @samp{sync_lock_test_and_set@var{mode}}
6385 This pattern takes two forms, based on the capabilities of the target.
6386 In either case, operand 0 is the result of the operand, operand 1 is
6387 the memory on which the atomic operation is performed, and operand 2
6388 is the value to set in the lock.
6390 In the ideal case, this operation is an atomic exchange operation, in
6391 which the previous value in memory operand is copied into the result
6392 operand, and the value operand is stored in the memory operand.
6394 For less capable targets, any value operand that is not the constant 1
6395 should be rejected with @code{FAIL}. In this case the target may use
6396 an atomic test-and-set bit operation. The result operand should contain
6397 1 if the bit was previously set and 0 if the bit was previously clear.
6398 The true contents of the memory operand are implementation defined.
6400 This pattern must issue any memory barrier instructions such that the
6401 pattern as a whole acts as an acquire barrier, that is all memory
6402 operations after the pattern do not occur until the lock is acquired.
6404 If this pattern is not defined, the operation will be constructed from
6405 a compare-and-swap operation, if defined.
6407 @cindex @code{sync_lock_release@var{mode}} instruction pattern
6408 @item @samp{sync_lock_release@var{mode}}
6409 This pattern, if defined, releases a lock set by
6410 @code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory
6411 that contains the lock; operand 1 is the value to store in the lock.
6413 If the target doesn't implement full semantics for
6414 @code{sync_lock_test_and_set@var{mode}}, any value operand which is not
6415 the constant 0 should be rejected with @code{FAIL}, and the true contents
6416 of the memory operand are implementation defined.
6418 This pattern must issue any memory barrier instructions such that the
6419 pattern as a whole acts as a release barrier, that is the lock is
6420 released only after all previous memory operations have completed.
6422 If this pattern is not defined, then a @code{memory_barrier} pattern
6423 will be emitted, followed by a store of the value to the memory operand.
6425 @cindex @code{atomic_compare_and_swap@var{mode}} instruction pattern
6426 @item @samp{atomic_compare_and_swap@var{mode}}
6427 This pattern, if defined, emits code for an atomic compare-and-swap
6428 operation with memory model semantics. Operand 2 is the memory on which
6429 the atomic operation is performed. Operand 0 is an output operand which
6430 is set to true or false based on whether the operation succeeded. Operand
6431 1 is an output operand which is set to the contents of the memory before
6432 the operation was attempted. Operand 3 is the value that is expected to
6433 be in memory. Operand 4 is the value to put in memory if the expected
6434 value is found there. Operand 5 is set to 1 if this compare and swap is to
6435 be treated as a weak operation. Operand 6 is the memory model to be used
6436 if the operation is a success. Operand 7 is the memory model to be used
6437 if the operation fails.
6439 If memory referred to in operand 2 contains the value in operand 3, then
6440 operand 4 is stored in memory pointed to by operand 2 and fencing based on
6441 the memory model in operand 6 is issued.
6443 If memory referred to in operand 2 does not contain the value in operand 3,
6444 then fencing based on the memory model in operand 7 is issued.
6446 If a target does not support weak compare-and-swap operations, or the port
6447 elects not to implement weak operations, the argument in operand 5 can be
6448 ignored. Note a strong implementation must be provided.
6450 If this pattern is not provided, the @code{__atomic_compare_exchange}
6451 built-in functions will utilize the legacy @code{sync_compare_and_swap}
6452 pattern with an @code{__ATOMIC_SEQ_CST} memory model.
6454 @cindex @code{atomic_load@var{mode}} instruction pattern
6455 @item @samp{atomic_load@var{mode}}
6456 This pattern implements an atomic load operation with memory model
6457 semantics. Operand 1 is the memory address being loaded from. Operand 0
6458 is the result of the load. Operand 2 is the memory model to be used for
6461 If not present, the @code{__atomic_load} built-in function will either
6462 resort to a normal load with memory barriers, or a compare-and-swap
6463 operation if a normal load would not be atomic.
6465 @cindex @code{atomic_store@var{mode}} instruction pattern
6466 @item @samp{atomic_store@var{mode}}
6467 This pattern implements an atomic store operation with memory model
6468 semantics. Operand 0 is the memory address being stored to. Operand 1
6469 is the value to be written. Operand 2 is the memory model to be used for
6472 If not present, the @code{__atomic_store} built-in function will attempt to
6473 perform a normal store and surround it with any required memory fences. If
6474 the store would not be atomic, then an @code{__atomic_exchange} is
6475 attempted with the result being ignored.
6477 @cindex @code{atomic_exchange@var{mode}} instruction pattern
6478 @item @samp{atomic_exchange@var{mode}}
6479 This pattern implements an atomic exchange operation with memory model
6480 semantics. Operand 1 is the memory location the operation is performed on.
6481 Operand 0 is an output operand which is set to the original value contained
6482 in the memory pointed to by operand 1. Operand 2 is the value to be
6483 stored. Operand 3 is the memory model to be used.
6485 If this pattern is not present, the built-in function
6486 @code{__atomic_exchange} will attempt to preform the operation with a
6487 compare and swap loop.
6489 @cindex @code{atomic_add@var{mode}} instruction pattern
6490 @cindex @code{atomic_sub@var{mode}} instruction pattern
6491 @cindex @code{atomic_or@var{mode}} instruction pattern
6492 @cindex @code{atomic_and@var{mode}} instruction pattern
6493 @cindex @code{atomic_xor@var{mode}} instruction pattern
6494 @cindex @code{atomic_nand@var{mode}} instruction pattern
6495 @item @samp{atomic_add@var{mode}}, @samp{atomic_sub@var{mode}}
6496 @itemx @samp{atomic_or@var{mode}}, @samp{atomic_and@var{mode}}
6497 @itemx @samp{atomic_xor@var{mode}}, @samp{atomic_nand@var{mode}}
6498 These patterns emit code for an atomic operation on memory with memory
6499 model semantics. Operand 0 is the memory on which the atomic operation is
6500 performed. Operand 1 is the second operand to the binary operator.
6501 Operand 2 is the memory model to be used by the operation.
6503 If these patterns are not defined, attempts will be made to use legacy
6504 @code{sync} patterns, or equivalent patterns which return a result. If
6505 none of these are available a compare-and-swap loop will be used.
6507 @cindex @code{atomic_fetch_add@var{mode}} instruction pattern
6508 @cindex @code{atomic_fetch_sub@var{mode}} instruction pattern
6509 @cindex @code{atomic_fetch_or@var{mode}} instruction pattern
6510 @cindex @code{atomic_fetch_and@var{mode}} instruction pattern
6511 @cindex @code{atomic_fetch_xor@var{mode}} instruction pattern
6512 @cindex @code{atomic_fetch_nand@var{mode}} instruction pattern
6513 @item @samp{atomic_fetch_add@var{mode}}, @samp{atomic_fetch_sub@var{mode}}
6514 @itemx @samp{atomic_fetch_or@var{mode}}, @samp{atomic_fetch_and@var{mode}}
6515 @itemx @samp{atomic_fetch_xor@var{mode}}, @samp{atomic_fetch_nand@var{mode}}
6516 These patterns emit code for an atomic operation on memory with memory
6517 model semantics, and return the original value. Operand 0 is an output
6518 operand which contains the value of the memory location before the
6519 operation was performed. Operand 1 is the memory on which the atomic
6520 operation is performed. Operand 2 is the second operand to the binary
6521 operator. Operand 3 is the memory model to be used by the operation.
6523 If these patterns are not defined, attempts will be made to use legacy
6524 @code{sync} patterns. If none of these are available a compare-and-swap
6527 @cindex @code{atomic_add_fetch@var{mode}} instruction pattern
6528 @cindex @code{atomic_sub_fetch@var{mode}} instruction pattern
6529 @cindex @code{atomic_or_fetch@var{mode}} instruction pattern
6530 @cindex @code{atomic_and_fetch@var{mode}} instruction pattern
6531 @cindex @code{atomic_xor_fetch@var{mode}} instruction pattern
6532 @cindex @code{atomic_nand_fetch@var{mode}} instruction pattern
6533 @item @samp{atomic_add_fetch@var{mode}}, @samp{atomic_sub_fetch@var{mode}}
6534 @itemx @samp{atomic_or_fetch@var{mode}}, @samp{atomic_and_fetch@var{mode}}
6535 @itemx @samp{atomic_xor_fetch@var{mode}}, @samp{atomic_nand_fetch@var{mode}}
6536 These patterns emit code for an atomic operation on memory with memory
6537 model semantics and return the result after the operation is performed.
6538 Operand 0 is an output operand which contains the value after the
6539 operation. Operand 1 is the memory on which the atomic operation is
6540 performed. Operand 2 is the second operand to the binary operator.
6541 Operand 3 is the memory model to be used by the operation.
6543 If these patterns are not defined, attempts will be made to use legacy
6544 @code{sync} patterns, or equivalent patterns which return the result before
6545 the operation followed by the arithmetic operation required to produce the
6546 result. If none of these are available a compare-and-swap loop will be
6549 @cindex @code{atomic_test_and_set} instruction pattern
6550 @item @samp{atomic_test_and_set}
6551 This pattern emits code for @code{__builtin_atomic_test_and_set}.
6552 Operand 0 is an output operand which is set to true if the previous
6553 previous contents of the byte was "set", and false otherwise. Operand 1
6554 is the @code{QImode} memory to be modified. Operand 2 is the memory
6557 The specific value that defines "set" is implementation defined, and
6558 is normally based on what is performed by the native atomic test and set
6561 @cindex @code{mem_thread_fence@var{mode}} instruction pattern
6562 @item @samp{mem_thread_fence@var{mode}}
6563 This pattern emits code required to implement a thread fence with
6564 memory model semantics. Operand 0 is the memory model to be used.
6566 If this pattern is not specified, all memory models except
6567 @code{__ATOMIC_RELAXED} will result in issuing a @code{sync_synchronize}
6570 @cindex @code{mem_signal_fence@var{mode}} instruction pattern
6571 @item @samp{mem_signal_fence@var{mode}}
6572 This pattern emits code required to implement a signal fence with
6573 memory model semantics. Operand 0 is the memory model to be used.
6575 This pattern should impact the compiler optimizers the same way that
6576 mem_signal_fence does, but it does not need to issue any barrier
6579 If this pattern is not specified, all memory models except
6580 @code{__ATOMIC_RELAXED} will result in issuing a @code{sync_synchronize}
6583 @cindex @code{get_thread_pointer@var{mode}} instruction pattern
6584 @cindex @code{set_thread_pointer@var{mode}} instruction pattern
6585 @item @samp{get_thread_pointer@var{mode}}
6586 @itemx @samp{set_thread_pointer@var{mode}}
6587 These patterns emit code that reads/sets the TLS thread pointer. Currently,
6588 these are only needed if the target needs to support the
6589 @code{__builtin_thread_pointer} and @code{__builtin_set_thread_pointer}
6592 The get/set patterns have a single output/input operand respectively,
6593 with @var{mode} intended to be @code{Pmode}.
6595 @cindex @code{stack_protect_set} instruction pattern
6596 @item @samp{stack_protect_set}
6597 This pattern, if defined, moves a @code{ptr_mode} value from the memory
6598 in operand 1 to the memory in operand 0 without leaving the value in
6599 a register afterward. This is to avoid leaking the value some place
6600 that an attacker might use to rewrite the stack guard slot after
6601 having clobbered it.
6603 If this pattern is not defined, then a plain move pattern is generated.
6605 @cindex @code{stack_protect_test} instruction pattern
6606 @item @samp{stack_protect_test}
6607 This pattern, if defined, compares a @code{ptr_mode} value from the
6608 memory in operand 1 with the memory in operand 0 without leaving the
6609 value in a register afterward and branches to operand 2 if the values
6612 If this pattern is not defined, then a plain compare pattern and
6613 conditional branch pattern is used.
6615 @cindex @code{clear_cache} instruction pattern
6616 @item @samp{clear_cache}
6617 This pattern, if defined, flushes the instruction cache for a region of
6618 memory. The region is bounded to by the Pmode pointers in operand 0
6619 inclusive and operand 1 exclusive.
6621 If this pattern is not defined, a call to the library function
6622 @code{__clear_cache} is used.
6627 @c Each of the following nodes are wrapped in separate
6628 @c "@ifset INTERNALS" to work around memory limits for the default
6629 @c configuration in older tetex distributions. Known to not work:
6630 @c tetex-1.0.7, known to work: tetex-2.0.2.
6632 @node Pattern Ordering
6633 @section When the Order of Patterns Matters
6634 @cindex Pattern Ordering
6635 @cindex Ordering of Patterns
6637 Sometimes an insn can match more than one instruction pattern. Then the
6638 pattern that appears first in the machine description is the one used.
6639 Therefore, more specific patterns (patterns that will match fewer things)
6640 and faster instructions (those that will produce better code when they
6641 do match) should usually go first in the description.
6643 In some cases the effect of ordering the patterns can be used to hide
6644 a pattern when it is not valid. For example, the 68000 has an
6645 instruction for converting a fullword to floating point and another
6646 for converting a byte to floating point. An instruction converting
6647 an integer to floating point could match either one. We put the
6648 pattern to convert the fullword first to make sure that one will
6649 be used rather than the other. (Otherwise a large integer might
6650 be generated as a single-byte immediate quantity, which would not work.)
6651 Instead of using this pattern ordering it would be possible to make the
6652 pattern for convert-a-byte smart enough to deal properly with any
6657 @node Dependent Patterns
6658 @section Interdependence of Patterns
6659 @cindex Dependent Patterns
6660 @cindex Interdependence of Patterns
6662 In some cases machines support instructions identical except for the
6663 machine mode of one or more operands. For example, there may be
6664 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
6668 (set (match_operand:SI 0 @dots{})
6669 (extend:SI (match_operand:HI 1 @dots{})))
6671 (set (match_operand:SI 0 @dots{})
6672 (extend:SI (match_operand:QI 1 @dots{})))
6676 Constant integers do not specify a machine mode, so an instruction to
6677 extend a constant value could match either pattern. The pattern it
6678 actually will match is the one that appears first in the file. For correct
6679 results, this must be the one for the widest possible mode (@code{HImode},
6680 here). If the pattern matches the @code{QImode} instruction, the results
6681 will be incorrect if the constant value does not actually fit that mode.
6683 Such instructions to extend constants are rarely generated because they are
6684 optimized away, but they do occasionally happen in nonoptimized
6687 If a constraint in a pattern allows a constant, the reload pass may
6688 replace a register with a constant permitted by the constraint in some
6689 cases. Similarly for memory references. Because of this substitution,
6690 you should not provide separate patterns for increment and decrement
6691 instructions. Instead, they should be generated from the same pattern
6692 that supports register-register add insns by examining the operands and
6693 generating the appropriate machine instruction.
6698 @section Defining Jump Instruction Patterns
6699 @cindex jump instruction patterns
6700 @cindex defining jump instruction patterns
6702 GCC does not assume anything about how the machine realizes jumps.
6703 The machine description should define a single pattern, usually
6704 a @code{define_expand}, which expands to all the required insns.
6706 Usually, this would be a comparison insn to set the condition code
6707 and a separate branch insn testing the condition code and branching
6708 or not according to its value. For many machines, however,
6709 separating compares and branches is limiting, which is why the
6710 more flexible approach with one @code{define_expand} is used in GCC.
6711 The machine description becomes clearer for architectures that
6712 have compare-and-branch instructions but no condition code. It also
6713 works better when different sets of comparison operators are supported
6714 by different kinds of conditional branches (e.g. integer vs. floating-point),
6715 or by conditional branches with respect to conditional stores.
6717 Two separate insns are always used if the machine description represents
6718 a condition code register using the legacy RTL expression @code{(cc0)},
6719 and on most machines that use a separate condition code register
6720 (@pxref{Condition Code}). For machines that use @code{(cc0)}, in
6721 fact, the set and use of the condition code must be separate and
6722 adjacent@footnote{@code{note} insns can separate them, though.}, thus
6723 allowing flags in @code{cc_status} to be used (@pxref{Condition Code}) and
6724 so that the comparison and branch insns could be located from each other
6725 by using the functions @code{prev_cc0_setter} and @code{next_cc0_user}.
6727 Even in this case having a single entry point for conditional branches
6728 is advantageous, because it handles equally well the case where a single
6729 comparison instruction records the results of both signed and unsigned
6730 comparison of the given operands (with the branch insns coming in distinct
6731 signed and unsigned flavors) as in the x86 or SPARC, and the case where
6732 there are distinct signed and unsigned compare instructions and only
6733 one set of conditional branch instructions as in the PowerPC.
6737 @node Looping Patterns
6738 @section Defining Looping Instruction Patterns
6739 @cindex looping instruction patterns
6740 @cindex defining looping instruction patterns
6742 Some machines have special jump instructions that can be utilized to
6743 make loops more efficient. A common example is the 68000 @samp{dbra}
6744 instruction which performs a decrement of a register and a branch if the
6745 result was greater than zero. Other machines, in particular digital
6746 signal processors (DSPs), have special block repeat instructions to
6747 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
6748 DSPs have a block repeat instruction that loads special registers to
6749 mark the top and end of a loop and to count the number of loop
6750 iterations. This avoids the need for fetching and executing a
6751 @samp{dbra}-like instruction and avoids pipeline stalls associated with
6754 GCC has three special named patterns to support low overhead looping.
6755 They are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin},
6756 and @samp{doloop_end}. The first pattern,
6757 @samp{decrement_and_branch_until_zero}, is not emitted during RTL
6758 generation but may be emitted during the instruction combination phase.
6759 This requires the assistance of the loop optimizer, using information
6760 collected during strength reduction, to reverse a loop to count down to
6761 zero. Some targets also require the loop optimizer to add a
6762 @code{REG_NONNEG} note to indicate that the iteration count is always
6763 positive. This is needed if the target performs a signed loop
6764 termination test. For example, the 68000 uses a pattern similar to the
6765 following for its @code{dbra} instruction:
6769 (define_insn "decrement_and_branch_until_zero"
6772 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
6775 (label_ref (match_operand 1 "" ""))
6778 (plus:SI (match_dup 0)
6780 "find_reg_note (insn, REG_NONNEG, 0)"
6785 Note that since the insn is both a jump insn and has an output, it must
6786 deal with its own reloads, hence the `m' constraints. Also note that
6787 since this insn is generated by the instruction combination phase
6788 combining two sequential insns together into an implicit parallel insn,
6789 the iteration counter needs to be biased by the same amount as the
6790 decrement operation, in this case @minus{}1. Note that the following similar
6791 pattern will not be matched by the combiner.
6795 (define_insn "decrement_and_branch_until_zero"
6798 (ge (match_operand:SI 0 "general_operand" "+d*am")
6800 (label_ref (match_operand 1 "" ""))
6803 (plus:SI (match_dup 0)
6805 "find_reg_note (insn, REG_NONNEG, 0)"
6810 The other two special looping patterns, @samp{doloop_begin} and
6811 @samp{doloop_end}, are emitted by the loop optimizer for certain
6812 well-behaved loops with a finite number of loop iterations using
6813 information collected during strength reduction.
6815 The @samp{doloop_end} pattern describes the actual looping instruction
6816 (or the implicit looping operation) and the @samp{doloop_begin} pattern
6817 is an optional companion pattern that can be used for initialization
6818 needed for some low-overhead looping instructions.
6820 Note that some machines require the actual looping instruction to be
6821 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
6822 the true RTL for a looping instruction at the top of the loop can cause
6823 problems with flow analysis. So instead, a dummy @code{doloop} insn is
6824 emitted at the end of the loop. The machine dependent reorg pass checks
6825 for the presence of this @code{doloop} insn and then searches back to
6826 the top of the loop, where it inserts the true looping insn (provided
6827 there are no instructions in the loop which would cause problems). Any
6828 additional labels can be emitted at this point. In addition, if the
6829 desired special iteration counter register was not allocated, this
6830 machine dependent reorg pass could emit a traditional compare and jump
6833 The essential difference between the
6834 @samp{decrement_and_branch_until_zero} and the @samp{doloop_end}
6835 patterns is that the loop optimizer allocates an additional pseudo
6836 register for the latter as an iteration counter. This pseudo register
6837 cannot be used within the loop (i.e., general induction variables cannot
6838 be derived from it), however, in many cases the loop induction variable
6839 may become redundant and removed by the flow pass.
6844 @node Insn Canonicalizations
6845 @section Canonicalization of Instructions
6846 @cindex canonicalization of instructions
6847 @cindex insn canonicalization
6849 There are often cases where multiple RTL expressions could represent an
6850 operation performed by a single machine instruction. This situation is
6851 most commonly encountered with logical, branch, and multiply-accumulate
6852 instructions. In such cases, the compiler attempts to convert these
6853 multiple RTL expressions into a single canonical form to reduce the
6854 number of insn patterns required.
6856 In addition to algebraic simplifications, following canonicalizations
6861 For commutative and comparison operators, a constant is always made the
6862 second operand. If a machine only supports a constant as the second
6863 operand, only patterns that match a constant in the second operand need
6867 For associative operators, a sequence of operators will always chain
6868 to the left; for instance, only the left operand of an integer @code{plus}
6869 can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor},
6870 @code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and
6871 @code{umax} are associative when applied to integers, and sometimes to
6875 @cindex @code{neg}, canonicalization of
6876 @cindex @code{not}, canonicalization of
6877 @cindex @code{mult}, canonicalization of
6878 @cindex @code{plus}, canonicalization of
6879 @cindex @code{minus}, canonicalization of
6880 For these operators, if only one operand is a @code{neg}, @code{not},
6881 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
6885 In combinations of @code{neg}, @code{mult}, @code{plus}, and
6886 @code{minus}, the @code{neg} operations (if any) will be moved inside
6887 the operations as far as possible. For instance,
6888 @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but
6889 @code{(plus (mult (neg B) C) A)} is canonicalized as
6890 @code{(minus A (mult B C))}.
6892 @cindex @code{compare}, canonicalization of
6894 For the @code{compare} operator, a constant is always the second operand
6895 if the first argument is a condition code register or @code{(cc0)}.
6898 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
6899 @code{minus} is made the first operand under the same conditions as
6903 @code{(ltu (plus @var{a} @var{b}) @var{b})} is converted to
6904 @code{(ltu (plus @var{a} @var{b}) @var{a})}. Likewise with @code{geu} instead
6908 @code{(minus @var{x} (const_int @var{n}))} is converted to
6909 @code{(plus @var{x} (const_int @var{-n}))}.
6912 Within address computations (i.e., inside @code{mem}), a left shift is
6913 converted into the appropriate multiplication by a power of two.
6915 @cindex @code{ior}, canonicalization of
6916 @cindex @code{and}, canonicalization of
6917 @cindex De Morgan's law
6919 De Morgan's Law is used to move bitwise negation inside a bitwise
6920 logical-and or logical-or operation. If this results in only one
6921 operand being a @code{not} expression, it will be the first one.
6923 A machine that has an instruction that performs a bitwise logical-and of one
6924 operand with the bitwise negation of the other should specify the pattern
6925 for that instruction as
6929 [(set (match_operand:@var{m} 0 @dots{})
6930 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
6931 (match_operand:@var{m} 2 @dots{})))]
6937 Similarly, a pattern for a ``NAND'' instruction should be written
6941 [(set (match_operand:@var{m} 0 @dots{})
6942 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
6943 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
6948 In both cases, it is not necessary to include patterns for the many
6949 logically equivalent RTL expressions.
6951 @cindex @code{xor}, canonicalization of
6953 The only possible RTL expressions involving both bitwise exclusive-or
6954 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
6955 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
6958 The sum of three items, one of which is a constant, will only appear in
6962 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
6965 @cindex @code{zero_extract}, canonicalization of
6966 @cindex @code{sign_extract}, canonicalization of
6968 Equality comparisons of a group of bits (usually a single bit) with zero
6969 will be written using @code{zero_extract} rather than the equivalent
6970 @code{and} or @code{sign_extract} operations.
6972 @cindex @code{mult}, canonicalization of
6974 @code{(sign_extend:@var{m1} (mult:@var{m2} (sign_extend:@var{m2} @var{x})
6975 (sign_extend:@var{m2} @var{y})))} is converted to @code{(mult:@var{m1}
6976 (sign_extend:@var{m1} @var{x}) (sign_extend:@var{m1} @var{y}))}, and likewise
6977 for @code{zero_extend}.
6980 @code{(sign_extend:@var{m1} (mult:@var{m2} (ashiftrt:@var{m2}
6981 @var{x} @var{s}) (sign_extend:@var{m2} @var{y})))} is converted
6982 to @code{(mult:@var{m1} (sign_extend:@var{m1} (ashiftrt:@var{m2}
6983 @var{x} @var{s})) (sign_extend:@var{m1} @var{y}))}, and likewise for
6984 patterns using @code{zero_extend} and @code{lshiftrt}. If the second
6985 operand of @code{mult} is also a shift, then that is extended also.
6986 This transformation is only applied when it can be proven that the
6987 original operation had sufficient precision to prevent overflow.
6991 Further canonicalization rules are defined in the function
6992 @code{commutative_operand_precedence} in @file{gcc/rtlanal.c}.
6996 @node Expander Definitions
6997 @section Defining RTL Sequences for Code Generation
6998 @cindex expander definitions
6999 @cindex code generation RTL sequences
7000 @cindex defining RTL sequences for code generation
7002 On some target machines, some standard pattern names for RTL generation
7003 cannot be handled with single insn, but a sequence of RTL insns can
7004 represent them. For these target machines, you can write a
7005 @code{define_expand} to specify how to generate the sequence of RTL@.
7007 @findex define_expand
7008 A @code{define_expand} is an RTL expression that looks almost like a
7009 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
7010 only for RTL generation and it can produce more than one RTL insn.
7012 A @code{define_expand} RTX has four operands:
7016 The name. Each @code{define_expand} must have a name, since the only
7017 use for it is to refer to it by name.
7020 The RTL template. This is a vector of RTL expressions representing
7021 a sequence of separate instructions. Unlike @code{define_insn}, there
7022 is no implicit surrounding @code{PARALLEL}.
7025 The condition, a string containing a C expression. This expression is
7026 used to express how the availability of this pattern depends on
7027 subclasses of target machine, selected by command-line options when GCC
7028 is run. This is just like the condition of a @code{define_insn} that
7029 has a standard name. Therefore, the condition (if present) may not
7030 depend on the data in the insn being matched, but only the
7031 target-machine-type flags. The compiler needs to test these conditions
7032 during initialization in order to learn exactly which named instructions
7033 are available in a particular run.
7036 The preparation statements, a string containing zero or more C
7037 statements which are to be executed before RTL code is generated from
7040 Usually these statements prepare temporary registers for use as
7041 internal operands in the RTL template, but they can also generate RTL
7042 insns directly by calling routines such as @code{emit_insn}, etc.
7043 Any such insns precede the ones that come from the RTL template.
7046 Optionally, a vector containing the values of attributes. @xref{Insn
7050 Every RTL insn emitted by a @code{define_expand} must match some
7051 @code{define_insn} in the machine description. Otherwise, the compiler
7052 will crash when trying to generate code for the insn or trying to optimize
7055 The RTL template, in addition to controlling generation of RTL insns,
7056 also describes the operands that need to be specified when this pattern
7057 is used. In particular, it gives a predicate for each operand.
7059 A true operand, which needs to be specified in order to generate RTL from
7060 the pattern, should be described with a @code{match_operand} in its first
7061 occurrence in the RTL template. This enters information on the operand's
7062 predicate into the tables that record such things. GCC uses the
7063 information to preload the operand into a register if that is required for
7064 valid RTL code. If the operand is referred to more than once, subsequent
7065 references should use @code{match_dup}.
7067 The RTL template may also refer to internal ``operands'' which are
7068 temporary registers or labels used only within the sequence made by the
7069 @code{define_expand}. Internal operands are substituted into the RTL
7070 template with @code{match_dup}, never with @code{match_operand}. The
7071 values of the internal operands are not passed in as arguments by the
7072 compiler when it requests use of this pattern. Instead, they are computed
7073 within the pattern, in the preparation statements. These statements
7074 compute the values and store them into the appropriate elements of
7075 @code{operands} so that @code{match_dup} can find them.
7077 There are two special macros defined for use in the preparation statements:
7078 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
7085 Use the @code{DONE} macro to end RTL generation for the pattern. The
7086 only RTL insns resulting from the pattern on this occasion will be
7087 those already emitted by explicit calls to @code{emit_insn} within the
7088 preparation statements; the RTL template will not be generated.
7092 Make the pattern fail on this occasion. When a pattern fails, it means
7093 that the pattern was not truly available. The calling routines in the
7094 compiler will try other strategies for code generation using other patterns.
7096 Failure is currently supported only for binary (addition, multiplication,
7097 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
7101 If the preparation falls through (invokes neither @code{DONE} nor
7102 @code{FAIL}), then the @code{define_expand} acts like a
7103 @code{define_insn} in that the RTL template is used to generate the
7106 The RTL template is not used for matching, only for generating the
7107 initial insn list. If the preparation statement always invokes
7108 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
7109 list of operands, such as this example:
7113 (define_expand "addsi3"
7114 [(match_operand:SI 0 "register_operand" "")
7115 (match_operand:SI 1 "register_operand" "")
7116 (match_operand:SI 2 "register_operand" "")]
7122 handle_add (operands[0], operands[1], operands[2]);
7128 Here is an example, the definition of left-shift for the SPUR chip:
7132 (define_expand "ashlsi3"
7133 [(set (match_operand:SI 0 "register_operand" "")
7137 (match_operand:SI 1 "register_operand" "")
7138 (match_operand:SI 2 "nonmemory_operand" "")))]
7147 if (GET_CODE (operands[2]) != CONST_INT
7148 || (unsigned) INTVAL (operands[2]) > 3)
7155 This example uses @code{define_expand} so that it can generate an RTL insn
7156 for shifting when the shift-count is in the supported range of 0 to 3 but
7157 fail in other cases where machine insns aren't available. When it fails,
7158 the compiler tries another strategy using different patterns (such as, a
7161 If the compiler were able to handle nontrivial condition-strings in
7162 patterns with names, then it would be possible to use a
7163 @code{define_insn} in that case. Here is another case (zero-extension
7164 on the 68000) which makes more use of the power of @code{define_expand}:
7167 (define_expand "zero_extendhisi2"
7168 [(set (match_operand:SI 0 "general_operand" "")
7170 (set (strict_low_part
7174 (match_operand:HI 1 "general_operand" ""))]
7176 "operands[1] = make_safe_from (operands[1], operands[0]);")
7180 @findex make_safe_from
7181 Here two RTL insns are generated, one to clear the entire output operand
7182 and the other to copy the input operand into its low half. This sequence
7183 is incorrect if the input operand refers to [the old value of] the output
7184 operand, so the preparation statement makes sure this isn't so. The
7185 function @code{make_safe_from} copies the @code{operands[1]} into a
7186 temporary register if it refers to @code{operands[0]}. It does this
7187 by emitting another RTL insn.
7189 Finally, a third example shows the use of an internal operand.
7190 Zero-extension on the SPUR chip is done by @code{and}-ing the result
7191 against a halfword mask. But this mask cannot be represented by a
7192 @code{const_int} because the constant value is too large to be legitimate
7193 on this machine. So it must be copied into a register with
7194 @code{force_reg} and then the register used in the @code{and}.
7197 (define_expand "zero_extendhisi2"
7198 [(set (match_operand:SI 0 "register_operand" "")
7200 (match_operand:HI 1 "register_operand" "")
7205 = force_reg (SImode, GEN_INT (65535)); ")
7208 @emph{Note:} If the @code{define_expand} is used to serve a
7209 standard binary or unary arithmetic operation or a bit-field operation,
7210 then the last insn it generates must not be a @code{code_label},
7211 @code{barrier} or @code{note}. It must be an @code{insn},
7212 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
7213 at the end, emit an insn to copy the result of the operation into
7214 itself. Such an insn will generate no code, but it can avoid problems
7219 @node Insn Splitting
7220 @section Defining How to Split Instructions
7221 @cindex insn splitting
7222 @cindex instruction splitting
7223 @cindex splitting instructions
7225 There are two cases where you should specify how to split a pattern
7226 into multiple insns. On machines that have instructions requiring
7227 delay slots (@pxref{Delay Slots}) or that have instructions whose
7228 output is not available for multiple cycles (@pxref{Processor pipeline
7229 description}), the compiler phases that optimize these cases need to
7230 be able to move insns into one-instruction delay slots. However, some
7231 insns may generate more than one machine instruction. These insns
7232 cannot be placed into a delay slot.
7234 Often you can rewrite the single insn as a list of individual insns,
7235 each corresponding to one machine instruction. The disadvantage of
7236 doing so is that it will cause the compilation to be slower and require
7237 more space. If the resulting insns are too complex, it may also
7238 suppress some optimizations. The compiler splits the insn if there is a
7239 reason to believe that it might improve instruction or delay slot
7242 The insn combiner phase also splits putative insns. If three insns are
7243 merged into one insn with a complex expression that cannot be matched by
7244 some @code{define_insn} pattern, the combiner phase attempts to split
7245 the complex pattern into two insns that are recognized. Usually it can
7246 break the complex pattern into two patterns by splitting out some
7247 subexpression. However, in some other cases, such as performing an
7248 addition of a large constant in two insns on a RISC machine, the way to
7249 split the addition into two insns is machine-dependent.
7251 @findex define_split
7252 The @code{define_split} definition tells the compiler how to split a
7253 complex insn into several simpler insns. It looks like this:
7257 [@var{insn-pattern}]
7259 [@var{new-insn-pattern-1}
7260 @var{new-insn-pattern-2}
7262 "@var{preparation-statements}")
7265 @var{insn-pattern} is a pattern that needs to be split and
7266 @var{condition} is the final condition to be tested, as in a
7267 @code{define_insn}. When an insn matching @var{insn-pattern} and
7268 satisfying @var{condition} is found, it is replaced in the insn list
7269 with the insns given by @var{new-insn-pattern-1},
7270 @var{new-insn-pattern-2}, etc.
7272 The @var{preparation-statements} are similar to those statements that
7273 are specified for @code{define_expand} (@pxref{Expander Definitions})
7274 and are executed before the new RTL is generated to prepare for the
7275 generated code or emit some insns whose pattern is not fixed. Unlike
7276 those in @code{define_expand}, however, these statements must not
7277 generate any new pseudo-registers. Once reload has completed, they also
7278 must not allocate any space in the stack frame.
7280 Patterns are matched against @var{insn-pattern} in two different
7281 circumstances. If an insn needs to be split for delay slot scheduling
7282 or insn scheduling, the insn is already known to be valid, which means
7283 that it must have been matched by some @code{define_insn} and, if
7284 @code{reload_completed} is nonzero, is known to satisfy the constraints
7285 of that @code{define_insn}. In that case, the new insn patterns must
7286 also be insns that are matched by some @code{define_insn} and, if
7287 @code{reload_completed} is nonzero, must also satisfy the constraints
7288 of those definitions.
7290 As an example of this usage of @code{define_split}, consider the following
7291 example from @file{a29k.md}, which splits a @code{sign_extend} from
7292 @code{HImode} to @code{SImode} into a pair of shift insns:
7296 [(set (match_operand:SI 0 "gen_reg_operand" "")
7297 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
7300 (ashift:SI (match_dup 1)
7303 (ashiftrt:SI (match_dup 0)
7306 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
7309 When the combiner phase tries to split an insn pattern, it is always the
7310 case that the pattern is @emph{not} matched by any @code{define_insn}.
7311 The combiner pass first tries to split a single @code{set} expression
7312 and then the same @code{set} expression inside a @code{parallel}, but
7313 followed by a @code{clobber} of a pseudo-reg to use as a scratch
7314 register. In these cases, the combiner expects exactly two new insn
7315 patterns to be generated. It will verify that these patterns match some
7316 @code{define_insn} definitions, so you need not do this test in the
7317 @code{define_split} (of course, there is no point in writing a
7318 @code{define_split} that will never produce insns that match).
7320 Here is an example of this use of @code{define_split}, taken from
7325 [(set (match_operand:SI 0 "gen_reg_operand" "")
7326 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
7327 (match_operand:SI 2 "non_add_cint_operand" "")))]
7329 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
7330 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
7333 int low = INTVAL (operands[2]) & 0xffff;
7334 int high = (unsigned) INTVAL (operands[2]) >> 16;
7337 high++, low |= 0xffff0000;
7339 operands[3] = GEN_INT (high << 16);
7340 operands[4] = GEN_INT (low);
7344 Here the predicate @code{non_add_cint_operand} matches any
7345 @code{const_int} that is @emph{not} a valid operand of a single add
7346 insn. The add with the smaller displacement is written so that it
7347 can be substituted into the address of a subsequent operation.
7349 An example that uses a scratch register, from the same file, generates
7350 an equality comparison of a register and a large constant:
7354 [(set (match_operand:CC 0 "cc_reg_operand" "")
7355 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
7356 (match_operand:SI 2 "non_short_cint_operand" "")))
7357 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
7358 "find_single_use (operands[0], insn, 0)
7359 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
7360 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
7361 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
7362 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
7365 /* @r{Get the constant we are comparing against, C, and see what it
7366 looks like sign-extended to 16 bits. Then see what constant
7367 could be XOR'ed with C to get the sign-extended value.} */
7369 int c = INTVAL (operands[2]);
7370 int sextc = (c << 16) >> 16;
7371 int xorv = c ^ sextc;
7373 operands[4] = GEN_INT (xorv);
7374 operands[5] = GEN_INT (sextc);
7378 To avoid confusion, don't write a single @code{define_split} that
7379 accepts some insns that match some @code{define_insn} as well as some
7380 insns that don't. Instead, write two separate @code{define_split}
7381 definitions, one for the insns that are valid and one for the insns that
7384 The splitter is allowed to split jump instructions into sequence of
7385 jumps or create new jumps in while splitting non-jump instructions. As
7386 the central flowgraph and branch prediction information needs to be updated,
7387 several restriction apply.
7389 Splitting of jump instruction into sequence that over by another jump
7390 instruction is always valid, as compiler expect identical behavior of new
7391 jump. When new sequence contains multiple jump instructions or new labels,
7392 more assistance is needed. Splitter is required to create only unconditional
7393 jumps, or simple conditional jump instructions. Additionally it must attach a
7394 @code{REG_BR_PROB} note to each conditional jump. A global variable
7395 @code{split_branch_probability} holds the probability of the original branch in case
7396 it was a simple conditional jump, @minus{}1 otherwise. To simplify
7397 recomputing of edge frequencies, the new sequence is required to have only
7398 forward jumps to the newly created labels.
7400 @findex define_insn_and_split
7401 For the common case where the pattern of a define_split exactly matches the
7402 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
7406 (define_insn_and_split
7407 [@var{insn-pattern}]
7409 "@var{output-template}"
7410 "@var{split-condition}"
7411 [@var{new-insn-pattern-1}
7412 @var{new-insn-pattern-2}
7414 "@var{preparation-statements}"
7415 [@var{insn-attributes}])
7419 @var{insn-pattern}, @var{condition}, @var{output-template}, and
7420 @var{insn-attributes} are used as in @code{define_insn}. The
7421 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
7422 in a @code{define_split}. The @var{split-condition} is also used as in
7423 @code{define_split}, with the additional behavior that if the condition starts
7424 with @samp{&&}, the condition used for the split will be the constructed as a
7425 logical ``and'' of the split condition with the insn condition. For example,
7429 (define_insn_and_split "zero_extendhisi2_and"
7430 [(set (match_operand:SI 0 "register_operand" "=r")
7431 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
7432 (clobber (reg:CC 17))]
7433 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
7435 "&& reload_completed"
7436 [(parallel [(set (match_dup 0)
7437 (and:SI (match_dup 0) (const_int 65535)))
7438 (clobber (reg:CC 17))])]
7440 [(set_attr "type" "alu1")])
7444 In this case, the actual split condition will be
7445 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
7447 The @code{define_insn_and_split} construction provides exactly the same
7448 functionality as two separate @code{define_insn} and @code{define_split}
7449 patterns. It exists for compactness, and as a maintenance tool to prevent
7450 having to ensure the two patterns' templates match.
7454 @node Including Patterns
7455 @section Including Patterns in Machine Descriptions.
7456 @cindex insn includes
7459 The @code{include} pattern tells the compiler tools where to
7460 look for patterns that are in files other than in the file
7461 @file{.md}. This is used only at build time and there is no preprocessing allowed.
7475 (include "filestuff")
7479 Where @var{pathname} is a string that specifies the location of the file,
7480 specifies the include file to be in @file{gcc/config/target/filestuff}. The
7481 directory @file{gcc/config/target} is regarded as the default directory.
7484 Machine descriptions may be split up into smaller more manageable subsections
7485 and placed into subdirectories.
7491 (include "BOGUS/filestuff")
7495 the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
7497 Specifying an absolute path for the include file such as;
7500 (include "/u2/BOGUS/filestuff")
7503 is permitted but is not encouraged.
7505 @subsection RTL Generation Tool Options for Directory Search
7506 @cindex directory options .md
7507 @cindex options, directory search
7508 @cindex search options
7510 The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
7515 genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
7520 Add the directory @var{dir} to the head of the list of directories to be
7521 searched for header files. This can be used to override a system machine definition
7522 file, substituting your own version, since these directories are
7523 searched before the default machine description file directories. If you use more than
7524 one @option{-I} option, the directories are scanned in left-to-right
7525 order; the standard default directory come after.
7530 @node Peephole Definitions
7531 @section Machine-Specific Peephole Optimizers
7532 @cindex peephole optimizer definitions
7533 @cindex defining peephole optimizers
7535 In addition to instruction patterns the @file{md} file may contain
7536 definitions of machine-specific peephole optimizations.
7538 The combiner does not notice certain peephole optimizations when the data
7539 flow in the program does not suggest that it should try them. For example,
7540 sometimes two consecutive insns related in purpose can be combined even
7541 though the second one does not appear to use a register computed in the
7542 first one. A machine-specific peephole optimizer can detect such
7545 There are two forms of peephole definitions that may be used. The
7546 original @code{define_peephole} is run at assembly output time to
7547 match insns and substitute assembly text. Use of @code{define_peephole}
7550 A newer @code{define_peephole2} matches insns and substitutes new
7551 insns. The @code{peephole2} pass is run after register allocation
7552 but before scheduling, which may result in much better code for
7553 targets that do scheduling.
7556 * define_peephole:: RTL to Text Peephole Optimizers
7557 * define_peephole2:: RTL to RTL Peephole Optimizers
7562 @node define_peephole
7563 @subsection RTL to Text Peephole Optimizers
7564 @findex define_peephole
7567 A definition looks like this:
7571 [@var{insn-pattern-1}
7572 @var{insn-pattern-2}
7576 "@var{optional-insn-attributes}")
7580 The last string operand may be omitted if you are not using any
7581 machine-specific information in this machine description. If present,
7582 it must obey the same rules as in a @code{define_insn}.
7584 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
7585 consecutive insns. The optimization applies to a sequence of insns when
7586 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
7587 the next, and so on.
7589 Each of the insns matched by a peephole must also match a
7590 @code{define_insn}. Peepholes are checked only at the last stage just
7591 before code generation, and only optionally. Therefore, any insn which
7592 would match a peephole but no @code{define_insn} will cause a crash in code
7593 generation in an unoptimized compilation, or at various optimization
7596 The operands of the insns are matched with @code{match_operands},
7597 @code{match_operator}, and @code{match_dup}, as usual. What is not
7598 usual is that the operand numbers apply to all the insn patterns in the
7599 definition. So, you can check for identical operands in two insns by
7600 using @code{match_operand} in one insn and @code{match_dup} in the
7603 The operand constraints used in @code{match_operand} patterns do not have
7604 any direct effect on the applicability of the peephole, but they will
7605 be validated afterward, so make sure your constraints are general enough
7606 to apply whenever the peephole matches. If the peephole matches
7607 but the constraints are not satisfied, the compiler will crash.
7609 It is safe to omit constraints in all the operands of the peephole; or
7610 you can write constraints which serve as a double-check on the criteria
7613 Once a sequence of insns matches the patterns, the @var{condition} is
7614 checked. This is a C expression which makes the final decision whether to
7615 perform the optimization (we do so if the expression is nonzero). If
7616 @var{condition} is omitted (in other words, the string is empty) then the
7617 optimization is applied to every sequence of insns that matches the
7620 The defined peephole optimizations are applied after register allocation
7621 is complete. Therefore, the peephole definition can check which
7622 operands have ended up in which kinds of registers, just by looking at
7625 @findex prev_active_insn
7626 The way to refer to the operands in @var{condition} is to write
7627 @code{operands[@var{i}]} for operand number @var{i} (as matched by
7628 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
7629 to refer to the last of the insns being matched; use
7630 @code{prev_active_insn} to find the preceding insns.
7632 @findex dead_or_set_p
7633 When optimizing computations with intermediate results, you can use
7634 @var{condition} to match only when the intermediate results are not used
7635 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
7636 @var{op})}, where @var{insn} is the insn in which you expect the value
7637 to be used for the last time (from the value of @code{insn}, together
7638 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
7639 value (from @code{operands[@var{i}]}).
7641 Applying the optimization means replacing the sequence of insns with one
7642 new insn. The @var{template} controls ultimate output of assembler code
7643 for this combined insn. It works exactly like the template of a
7644 @code{define_insn}. Operand numbers in this template are the same ones
7645 used in matching the original sequence of insns.
7647 The result of a defined peephole optimizer does not need to match any of
7648 the insn patterns in the machine description; it does not even have an
7649 opportunity to match them. The peephole optimizer definition itself serves
7650 as the insn pattern to control how the insn is output.
7652 Defined peephole optimizers are run as assembler code is being output,
7653 so the insns they produce are never combined or rearranged in any way.
7655 Here is an example, taken from the 68000 machine description:
7659 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
7660 (set (match_operand:DF 0 "register_operand" "=f")
7661 (match_operand:DF 1 "register_operand" "ad"))]
7662 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
7665 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7667 output_asm_insn ("move.l %1,(sp)", xoperands);
7668 output_asm_insn ("move.l %1,-(sp)", operands);
7669 return "fmove.d (sp)+,%0";
7671 output_asm_insn ("movel %1,sp@@", xoperands);
7672 output_asm_insn ("movel %1,sp@@-", operands);
7673 return "fmoved sp@@+,%0";
7679 The effect of this optimization is to change
7705 If a peephole matches a sequence including one or more jump insns, you must
7706 take account of the flags such as @code{CC_REVERSED} which specify that the
7707 condition codes are represented in an unusual manner. The compiler
7708 automatically alters any ordinary conditional jumps which occur in such
7709 situations, but the compiler cannot alter jumps which have been replaced by
7710 peephole optimizations. So it is up to you to alter the assembler code
7711 that the peephole produces. Supply C code to write the assembler output,
7712 and in this C code check the condition code status flags and change the
7713 assembler code as appropriate.
7716 @var{insn-pattern-1} and so on look @emph{almost} like the second
7717 operand of @code{define_insn}. There is one important difference: the
7718 second operand of @code{define_insn} consists of one or more RTX's
7719 enclosed in square brackets. Usually, there is only one: then the same
7720 action can be written as an element of a @code{define_peephole}. But
7721 when there are multiple actions in a @code{define_insn}, they are
7722 implicitly enclosed in a @code{parallel}. Then you must explicitly
7723 write the @code{parallel}, and the square brackets within it, in the
7724 @code{define_peephole}. Thus, if an insn pattern looks like this,
7727 (define_insn "divmodsi4"
7728 [(set (match_operand:SI 0 "general_operand" "=d")
7729 (div:SI (match_operand:SI 1 "general_operand" "0")
7730 (match_operand:SI 2 "general_operand" "dmsK")))
7731 (set (match_operand:SI 3 "general_operand" "=d")
7732 (mod:SI (match_dup 1) (match_dup 2)))]
7734 "divsl%.l %2,%3:%0")
7738 then the way to mention this insn in a peephole is as follows:
7744 [(set (match_operand:SI 0 "general_operand" "=d")
7745 (div:SI (match_operand:SI 1 "general_operand" "0")
7746 (match_operand:SI 2 "general_operand" "dmsK")))
7747 (set (match_operand:SI 3 "general_operand" "=d")
7748 (mod:SI (match_dup 1) (match_dup 2)))])
7755 @node define_peephole2
7756 @subsection RTL to RTL Peephole Optimizers
7757 @findex define_peephole2
7759 The @code{define_peephole2} definition tells the compiler how to
7760 substitute one sequence of instructions for another sequence,
7761 what additional scratch registers may be needed and what their
7766 [@var{insn-pattern-1}
7767 @var{insn-pattern-2}
7770 [@var{new-insn-pattern-1}
7771 @var{new-insn-pattern-2}
7773 "@var{preparation-statements}")
7776 The definition is almost identical to @code{define_split}
7777 (@pxref{Insn Splitting}) except that the pattern to match is not a
7778 single instruction, but a sequence of instructions.
7780 It is possible to request additional scratch registers for use in the
7781 output template. If appropriate registers are not free, the pattern
7782 will simply not match.
7784 @findex match_scratch
7786 Scratch registers are requested with a @code{match_scratch} pattern at
7787 the top level of the input pattern. The allocated register (initially) will
7788 be dead at the point requested within the original sequence. If the scratch
7789 is used at more than a single point, a @code{match_dup} pattern at the
7790 top level of the input pattern marks the last position in the input sequence
7791 at which the register must be available.
7793 Here is an example from the IA-32 machine description:
7797 [(match_scratch:SI 2 "r")
7798 (parallel [(set (match_operand:SI 0 "register_operand" "")
7799 (match_operator:SI 3 "arith_or_logical_operator"
7801 (match_operand:SI 1 "memory_operand" "")]))
7802 (clobber (reg:CC 17))])]
7803 "! optimize_size && ! TARGET_READ_MODIFY"
7804 [(set (match_dup 2) (match_dup 1))
7805 (parallel [(set (match_dup 0)
7806 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
7807 (clobber (reg:CC 17))])]
7812 This pattern tries to split a load from its use in the hopes that we'll be
7813 able to schedule around the memory load latency. It allocates a single
7814 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
7815 to be live only at the point just before the arithmetic.
7817 A real example requiring extended scratch lifetimes is harder to come by,
7818 so here's a silly made-up example:
7822 [(match_scratch:SI 4 "r")
7823 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
7824 (set (match_operand:SI 2 "" "") (match_dup 1))
7826 (set (match_operand:SI 3 "" "") (match_dup 1))]
7827 "/* @r{determine 1 does not overlap 0 and 2} */"
7828 [(set (match_dup 4) (match_dup 1))
7829 (set (match_dup 0) (match_dup 4))
7830 (set (match_dup 2) (match_dup 4))
7831 (set (match_dup 3) (match_dup 4))]
7836 If we had not added the @code{(match_dup 4)} in the middle of the input
7837 sequence, it might have been the case that the register we chose at the
7838 beginning of the sequence is killed by the first or second @code{set}.
7842 @node Insn Attributes
7843 @section Instruction Attributes
7844 @cindex insn attributes
7845 @cindex instruction attributes
7847 In addition to describing the instruction supported by the target machine,
7848 the @file{md} file also defines a group of @dfn{attributes} and a set of
7849 values for each. Every generated insn is assigned a value for each attribute.
7850 One possible attribute would be the effect that the insn has on the machine's
7851 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
7852 to track the condition codes.
7855 * Defining Attributes:: Specifying attributes and their values.
7856 * Expressions:: Valid expressions for attribute values.
7857 * Tagging Insns:: Assigning attribute values to insns.
7858 * Attr Example:: An example of assigning attributes.
7859 * Insn Lengths:: Computing the length of insns.
7860 * Constant Attributes:: Defining attributes that are constant.
7861 * Mnemonic Attribute:: Obtain the instruction mnemonic as attribute value.
7862 * Delay Slots:: Defining delay slots required for a machine.
7863 * Processor pipeline description:: Specifying information for insn scheduling.
7868 @node Defining Attributes
7869 @subsection Defining Attributes and their Values
7870 @cindex defining attributes and their values
7871 @cindex attributes, defining
7874 The @code{define_attr} expression is used to define each attribute required
7875 by the target machine. It looks like:
7878 (define_attr @var{name} @var{list-of-values} @var{default})
7881 @var{name} is a string specifying the name of the attribute being
7882 defined. Some attributes are used in a special way by the rest of the
7883 compiler. The @code{enabled} attribute can be used to conditionally
7884 enable or disable insn alternatives (@pxref{Disable Insn
7885 Alternatives}). The @code{predicable} attribute, together with a
7886 suitable @code{define_cond_exec} (@pxref{Conditional Execution}), can
7887 be used to automatically generate conditional variants of instruction
7888 patterns. The @code{mnemonic} attribute can be used to check for the
7889 instruction mnemonic (@pxref{Mnemonic Attribute}). The compiler
7890 internally uses the names @code{ce_enabled} and @code{nonce_enabled},
7891 so they should not be used elsewhere as alternative names.
7893 @var{list-of-values} is either a string that specifies a comma-separated
7894 list of values that can be assigned to the attribute, or a null string to
7895 indicate that the attribute takes numeric values.
7897 @var{default} is an attribute expression that gives the value of this
7898 attribute for insns that match patterns whose definition does not include
7899 an explicit value for this attribute. @xref{Attr Example}, for more
7900 information on the handling of defaults. @xref{Constant Attributes},
7901 for information on attributes that do not depend on any particular insn.
7904 For each defined attribute, a number of definitions are written to the
7905 @file{insn-attr.h} file. For cases where an explicit set of values is
7906 specified for an attribute, the following are defined:
7910 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
7913 An enumerated class is defined for @samp{attr_@var{name}} with
7914 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
7915 the attribute name and value are first converted to uppercase.
7918 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
7919 returns the attribute value for that insn.
7922 For example, if the following is present in the @file{md} file:
7925 (define_attr "type" "branch,fp,load,store,arith" @dots{})
7929 the following lines will be written to the file @file{insn-attr.h}.
7932 #define HAVE_ATTR_type 1
7933 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
7934 TYPE_STORE, TYPE_ARITH@};
7935 extern enum attr_type get_attr_type ();
7938 If the attribute takes numeric values, no @code{enum} type will be
7939 defined and the function to obtain the attribute's value will return
7942 There are attributes which are tied to a specific meaning. These
7943 attributes are not free to use for other purposes:
7947 The @code{length} attribute is used to calculate the length of emitted
7948 code chunks. This is especially important when verifying branch
7949 distances. @xref{Insn Lengths}.
7952 The @code{enabled} attribute can be defined to prevent certain
7953 alternatives of an insn definition from being used during code
7954 generation. @xref{Disable Insn Alternatives}.
7957 The @code{mnemonic} attribute can be defined to implement instruction
7958 specific checks in e.g. the pipeline description.
7959 @xref{Mnemonic Attribute}.
7962 For each of these special attributes, the corresponding
7963 @samp{HAVE_ATTR_@var{name}} @samp{#define} is also written when the
7964 attribute is not defined; in that case, it is defined as @samp{0}.
7966 @findex define_enum_attr
7967 @anchor{define_enum_attr}
7968 Another way of defining an attribute is to use:
7971 (define_enum_attr "@var{attr}" "@var{enum}" @var{default})
7974 This works in just the same way as @code{define_attr}, except that
7975 the list of values is taken from a separate enumeration called
7976 @var{enum} (@pxref{define_enum}). This form allows you to use
7977 the same list of values for several attributes without having to
7978 repeat the list each time. For example:
7981 (define_enum "processor" [
7986 (define_enum_attr "arch" "processor"
7987 (const (symbol_ref "target_arch")))
7988 (define_enum_attr "tune" "processor"
7989 (const (symbol_ref "target_tune")))
7992 defines the same attributes as:
7995 (define_attr "arch" "model_a,model_b,@dots{}"
7996 (const (symbol_ref "target_arch")))
7997 (define_attr "tune" "model_a,model_b,@dots{}"
7998 (const (symbol_ref "target_tune")))
8001 but without duplicating the processor list. The second example defines two
8002 separate C enums (@code{attr_arch} and @code{attr_tune}) whereas the first
8003 defines a single C enum (@code{processor}).
8007 @subsection Attribute Expressions
8008 @cindex attribute expressions
8010 RTL expressions used to define attributes use the codes described above
8011 plus a few specific to attribute definitions, to be discussed below.
8012 Attribute value expressions must have one of the following forms:
8015 @cindex @code{const_int} and attributes
8016 @item (const_int @var{i})
8017 The integer @var{i} specifies the value of a numeric attribute. @var{i}
8018 must be non-negative.
8020 The value of a numeric attribute can be specified either with a
8021 @code{const_int}, or as an integer represented as a string in
8022 @code{const_string}, @code{eq_attr} (see below), @code{attr},
8023 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
8024 overrides on specific instructions (@pxref{Tagging Insns}).
8026 @cindex @code{const_string} and attributes
8027 @item (const_string @var{value})
8028 The string @var{value} specifies a constant attribute value.
8029 If @var{value} is specified as @samp{"*"}, it means that the default value of
8030 the attribute is to be used for the insn containing this expression.
8031 @samp{"*"} obviously cannot be used in the @var{default} expression
8032 of a @code{define_attr}.
8034 If the attribute whose value is being specified is numeric, @var{value}
8035 must be a string containing a non-negative integer (normally
8036 @code{const_int} would be used in this case). Otherwise, it must
8037 contain one of the valid values for the attribute.
8039 @cindex @code{if_then_else} and attributes
8040 @item (if_then_else @var{test} @var{true-value} @var{false-value})
8041 @var{test} specifies an attribute test, whose format is defined below.
8042 The value of this expression is @var{true-value} if @var{test} is true,
8043 otherwise it is @var{false-value}.
8045 @cindex @code{cond} and attributes
8046 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
8047 The first operand of this expression is a vector containing an even
8048 number of expressions and consisting of pairs of @var{test} and @var{value}
8049 expressions. The value of the @code{cond} expression is that of the
8050 @var{value} corresponding to the first true @var{test} expression. If
8051 none of the @var{test} expressions are true, the value of the @code{cond}
8052 expression is that of the @var{default} expression.
8055 @var{test} expressions can have one of the following forms:
8058 @cindex @code{const_int} and attribute tests
8059 @item (const_int @var{i})
8060 This test is true if @var{i} is nonzero and false otherwise.
8062 @cindex @code{not} and attributes
8063 @cindex @code{ior} and attributes
8064 @cindex @code{and} and attributes
8065 @item (not @var{test})
8066 @itemx (ior @var{test1} @var{test2})
8067 @itemx (and @var{test1} @var{test2})
8068 These tests are true if the indicated logical function is true.
8070 @cindex @code{match_operand} and attributes
8071 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
8072 This test is true if operand @var{n} of the insn whose attribute value
8073 is being determined has mode @var{m} (this part of the test is ignored
8074 if @var{m} is @code{VOIDmode}) and the function specified by the string
8075 @var{pred} returns a nonzero value when passed operand @var{n} and mode
8076 @var{m} (this part of the test is ignored if @var{pred} is the null
8079 The @var{constraints} operand is ignored and should be the null string.
8081 @cindex @code{match_test} and attributes
8082 @item (match_test @var{c-expr})
8083 The test is true if C expression @var{c-expr} is true. In non-constant
8084 attributes, @var{c-expr} has access to the following variables:
8088 The rtl instruction under test.
8089 @item which_alternative
8090 The @code{define_insn} alternative that @var{insn} matches.
8091 @xref{Output Statement}.
8093 An array of @var{insn}'s rtl operands.
8096 @var{c-expr} behaves like the condition in a C @code{if} statement,
8097 so there is no need to explicitly convert the expression into a boolean
8098 0 or 1 value. For example, the following two tests are equivalent:
8101 (match_test "x & 2")
8102 (match_test "(x & 2) != 0")
8105 @cindex @code{le} and attributes
8106 @cindex @code{leu} and attributes
8107 @cindex @code{lt} and attributes
8108 @cindex @code{gt} and attributes
8109 @cindex @code{gtu} and attributes
8110 @cindex @code{ge} and attributes
8111 @cindex @code{geu} and attributes
8112 @cindex @code{ne} and attributes
8113 @cindex @code{eq} and attributes
8114 @cindex @code{plus} and attributes
8115 @cindex @code{minus} and attributes
8116 @cindex @code{mult} and attributes
8117 @cindex @code{div} and attributes
8118 @cindex @code{mod} and attributes
8119 @cindex @code{abs} and attributes
8120 @cindex @code{neg} and attributes
8121 @cindex @code{ashift} and attributes
8122 @cindex @code{lshiftrt} and attributes
8123 @cindex @code{ashiftrt} and attributes
8124 @item (le @var{arith1} @var{arith2})
8125 @itemx (leu @var{arith1} @var{arith2})
8126 @itemx (lt @var{arith1} @var{arith2})
8127 @itemx (ltu @var{arith1} @var{arith2})
8128 @itemx (gt @var{arith1} @var{arith2})
8129 @itemx (gtu @var{arith1} @var{arith2})
8130 @itemx (ge @var{arith1} @var{arith2})
8131 @itemx (geu @var{arith1} @var{arith2})
8132 @itemx (ne @var{arith1} @var{arith2})
8133 @itemx (eq @var{arith1} @var{arith2})
8134 These tests are true if the indicated comparison of the two arithmetic
8135 expressions is true. Arithmetic expressions are formed with
8136 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
8137 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
8138 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
8141 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
8142 Lengths},for additional forms). @code{symbol_ref} is a string
8143 denoting a C expression that yields an @code{int} when evaluated by the
8144 @samp{get_attr_@dots{}} routine. It should normally be a global
8148 @item (eq_attr @var{name} @var{value})
8149 @var{name} is a string specifying the name of an attribute.
8151 @var{value} is a string that is either a valid value for attribute
8152 @var{name}, a comma-separated list of values, or @samp{!} followed by a
8153 value or list. If @var{value} does not begin with a @samp{!}, this
8154 test is true if the value of the @var{name} attribute of the current
8155 insn is in the list specified by @var{value}. If @var{value} begins
8156 with a @samp{!}, this test is true if the attribute's value is
8157 @emph{not} in the specified list.
8162 (eq_attr "type" "load,store")
8169 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
8172 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
8173 value of the compiler variable @code{which_alternative}
8174 (@pxref{Output Statement}) and the values must be small integers. For
8178 (eq_attr "alternative" "2,3")
8185 (ior (eq (symbol_ref "which_alternative") (const_int 2))
8186 (eq (symbol_ref "which_alternative") (const_int 3)))
8189 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
8190 where the value of the attribute being tested is known for all insns matching
8191 a particular pattern. This is by far the most common case.
8194 @item (attr_flag @var{name})
8195 The value of an @code{attr_flag} expression is true if the flag
8196 specified by @var{name} is true for the @code{insn} currently being
8199 @var{name} is a string specifying one of a fixed set of flags to test.
8200 Test the flags @code{forward} and @code{backward} to determine the
8201 direction of a conditional branch.
8203 This example describes a conditional branch delay slot which
8204 can be nullified for forward branches that are taken (annul-true) or
8205 for backward branches which are not taken (annul-false).
8208 (define_delay (eq_attr "type" "cbranch")
8209 [(eq_attr "in_branch_delay" "true")
8210 (and (eq_attr "in_branch_delay" "true")
8211 (attr_flag "forward"))
8212 (and (eq_attr "in_branch_delay" "true")
8213 (attr_flag "backward"))])
8216 The @code{forward} and @code{backward} flags are false if the current
8217 @code{insn} being scheduled is not a conditional branch.
8219 @code{attr_flag} is only used during delay slot scheduling and has no
8220 meaning to other passes of the compiler.
8223 @item (attr @var{name})
8224 The value of another attribute is returned. This is most useful
8225 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
8226 produce more efficient code for non-numeric attributes.
8232 @subsection Assigning Attribute Values to Insns
8233 @cindex tagging insns
8234 @cindex assigning attribute values to insns
8236 The value assigned to an attribute of an insn is primarily determined by
8237 which pattern is matched by that insn (or which @code{define_peephole}
8238 generated it). Every @code{define_insn} and @code{define_peephole} can
8239 have an optional last argument to specify the values of attributes for
8240 matching insns. The value of any attribute not specified in a particular
8241 insn is set to the default value for that attribute, as specified in its
8242 @code{define_attr}. Extensive use of default values for attributes
8243 permits the specification of the values for only one or two attributes
8244 in the definition of most insn patterns, as seen in the example in the
8247 The optional last argument of @code{define_insn} and
8248 @code{define_peephole} is a vector of expressions, each of which defines
8249 the value for a single attribute. The most general way of assigning an
8250 attribute's value is to use a @code{set} expression whose first operand is an
8251 @code{attr} expression giving the name of the attribute being set. The
8252 second operand of the @code{set} is an attribute expression
8253 (@pxref{Expressions}) giving the value of the attribute.
8255 When the attribute value depends on the @samp{alternative} attribute
8256 (i.e., which is the applicable alternative in the constraint of the
8257 insn), the @code{set_attr_alternative} expression can be used. It
8258 allows the specification of a vector of attribute expressions, one for
8262 When the generality of arbitrary attribute expressions is not required,
8263 the simpler @code{set_attr} expression can be used, which allows
8264 specifying a string giving either a single attribute value or a list
8265 of attribute values, one for each alternative.
8267 The form of each of the above specifications is shown below. In each case,
8268 @var{name} is a string specifying the attribute to be set.
8271 @item (set_attr @var{name} @var{value-string})
8272 @var{value-string} is either a string giving the desired attribute value,
8273 or a string containing a comma-separated list giving the values for
8274 succeeding alternatives. The number of elements must match the number
8275 of alternatives in the constraint of the insn pattern.
8277 Note that it may be useful to specify @samp{*} for some alternative, in
8278 which case the attribute will assume its default value for insns matching
8281 @findex set_attr_alternative
8282 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
8283 Depending on the alternative of the insn, the value will be one of the
8284 specified values. This is a shorthand for using a @code{cond} with
8285 tests on the @samp{alternative} attribute.
8288 @item (set (attr @var{name}) @var{value})
8289 The first operand of this @code{set} must be the special RTL expression
8290 @code{attr}, whose sole operand is a string giving the name of the
8291 attribute being set. @var{value} is the value of the attribute.
8294 The following shows three different ways of representing the same
8295 attribute value specification:
8298 (set_attr "type" "load,store,arith")
8300 (set_attr_alternative "type"
8301 [(const_string "load") (const_string "store")
8302 (const_string "arith")])
8305 (cond [(eq_attr "alternative" "1") (const_string "load")
8306 (eq_attr "alternative" "2") (const_string "store")]
8307 (const_string "arith")))
8311 @findex define_asm_attributes
8312 The @code{define_asm_attributes} expression provides a mechanism to
8313 specify the attributes assigned to insns produced from an @code{asm}
8314 statement. It has the form:
8317 (define_asm_attributes [@var{attr-sets}])
8321 where @var{attr-sets} is specified the same as for both the
8322 @code{define_insn} and the @code{define_peephole} expressions.
8324 These values will typically be the ``worst case'' attribute values. For
8325 example, they might indicate that the condition code will be clobbered.
8327 A specification for a @code{length} attribute is handled specially. The
8328 way to compute the length of an @code{asm} insn is to multiply the
8329 length specified in the expression @code{define_asm_attributes} by the
8330 number of machine instructions specified in the @code{asm} statement,
8331 determined by counting the number of semicolons and newlines in the
8332 string. Therefore, the value of the @code{length} attribute specified
8333 in a @code{define_asm_attributes} should be the maximum possible length
8334 of a single machine instruction.
8339 @subsection Example of Attribute Specifications
8340 @cindex attribute specifications example
8341 @cindex attribute specifications
8343 The judicious use of defaulting is important in the efficient use of
8344 insn attributes. Typically, insns are divided into @dfn{types} and an
8345 attribute, customarily called @code{type}, is used to represent this
8346 value. This attribute is normally used only to define the default value
8347 for other attributes. An example will clarify this usage.
8349 Assume we have a RISC machine with a condition code and in which only
8350 full-word operations are performed in registers. Let us assume that we
8351 can divide all insns into loads, stores, (integer) arithmetic
8352 operations, floating point operations, and branches.
8354 Here we will concern ourselves with determining the effect of an insn on
8355 the condition code and will limit ourselves to the following possible
8356 effects: The condition code can be set unpredictably (clobbered), not
8357 be changed, be set to agree with the results of the operation, or only
8358 changed if the item previously set into the condition code has been
8361 Here is part of a sample @file{md} file for such a machine:
8364 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
8366 (define_attr "cc" "clobber,unchanged,set,change0"
8367 (cond [(eq_attr "type" "load")
8368 (const_string "change0")
8369 (eq_attr "type" "store,branch")
8370 (const_string "unchanged")
8371 (eq_attr "type" "arith")
8372 (if_then_else (match_operand:SI 0 "" "")
8373 (const_string "set")
8374 (const_string "clobber"))]
8375 (const_string "clobber")))
8378 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
8379 (match_operand:SI 1 "general_operand" "r,m,r"))]
8385 [(set_attr "type" "arith,load,store")])
8388 Note that we assume in the above example that arithmetic operations
8389 performed on quantities smaller than a machine word clobber the condition
8390 code since they will set the condition code to a value corresponding to the
8396 @subsection Computing the Length of an Insn
8397 @cindex insn lengths, computing
8398 @cindex computing the length of an insn
8400 For many machines, multiple types of branch instructions are provided, each
8401 for different length branch displacements. In most cases, the assembler
8402 will choose the correct instruction to use. However, when the assembler
8403 cannot do so, GCC can when a special attribute, the @code{length}
8404 attribute, is defined. This attribute must be defined to have numeric
8405 values by specifying a null string in its @code{define_attr}.
8407 In the case of the @code{length} attribute, two additional forms of
8408 arithmetic terms are allowed in test expressions:
8411 @cindex @code{match_dup} and attributes
8412 @item (match_dup @var{n})
8413 This refers to the address of operand @var{n} of the current insn, which
8414 must be a @code{label_ref}.
8416 @cindex @code{pc} and attributes
8418 For non-branch instructions and backward branch instructions, this refers
8419 to the address of the current insn. But for forward branch instructions,
8420 this refers to the address of the next insn, because the length of the
8421 current insn is to be computed.
8424 @cindex @code{addr_vec}, length of
8425 @cindex @code{addr_diff_vec}, length of
8426 For normal insns, the length will be determined by value of the
8427 @code{length} attribute. In the case of @code{addr_vec} and
8428 @code{addr_diff_vec} insn patterns, the length is computed as
8429 the number of vectors multiplied by the size of each vector.
8431 Lengths are measured in addressable storage units (bytes).
8433 Note that it is possible to call functions via the @code{symbol_ref}
8434 mechanism to compute the length of an insn. However, if you use this
8435 mechanism you must provide dummy clauses to express the maximum length
8436 without using the function call. You can an example of this in the
8437 @code{pa} machine description for the @code{call_symref} pattern.
8439 The following macros can be used to refine the length computation:
8442 @findex ADJUST_INSN_LENGTH
8443 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
8444 If defined, modifies the length assigned to instruction @var{insn} as a
8445 function of the context in which it is used. @var{length} is an lvalue
8446 that contains the initially computed length of the insn and should be
8447 updated with the correct length of the insn.
8449 This macro will normally not be required. A case in which it is
8450 required is the ROMP@. On this machine, the size of an @code{addr_vec}
8451 insn must be increased by two to compensate for the fact that alignment
8455 @findex get_attr_length
8456 The routine that returns @code{get_attr_length} (the value of the
8457 @code{length} attribute) can be used by the output routine to
8458 determine the form of the branch instruction to be written, as the
8459 example below illustrates.
8461 As an example of the specification of variable-length branches, consider
8462 the IBM 360. If we adopt the convention that a register will be set to
8463 the starting address of a function, we can jump to labels within 4k of
8464 the start using a four-byte instruction. Otherwise, we need a six-byte
8465 sequence to load the address from memory and then branch to it.
8467 On such a machine, a pattern for a branch instruction might be specified
8473 (label_ref (match_operand 0 "" "")))]
8476 return (get_attr_length (insn) == 4
8477 ? "b %l0" : "l r15,=a(%l0); br r15");
8479 [(set (attr "length")
8480 (if_then_else (lt (match_dup 0) (const_int 4096))
8487 @node Constant Attributes
8488 @subsection Constant Attributes
8489 @cindex constant attributes
8491 A special form of @code{define_attr}, where the expression for the
8492 default value is a @code{const} expression, indicates an attribute that
8493 is constant for a given run of the compiler. Constant attributes may be
8494 used to specify which variety of processor is used. For example,
8497 (define_attr "cpu" "m88100,m88110,m88000"
8499 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
8500 (symbol_ref "TARGET_88110") (const_string "m88110")]
8501 (const_string "m88000"))))
8503 (define_attr "memory" "fast,slow"
8505 (if_then_else (symbol_ref "TARGET_FAST_MEM")
8506 (const_string "fast")
8507 (const_string "slow"))))
8510 The routine generated for constant attributes has no parameters as it
8511 does not depend on any particular insn. RTL expressions used to define
8512 the value of a constant attribute may use the @code{symbol_ref} form,
8513 but may not use either the @code{match_operand} form or @code{eq_attr}
8514 forms involving insn attributes.
8518 @node Mnemonic Attribute
8519 @subsection Mnemonic Attribute
8520 @cindex mnemonic attribute
8522 The @code{mnemonic} attribute is a string type attribute holding the
8523 instruction mnemonic for an insn alternative. The attribute values
8524 will automatically be generated by the machine description parser if
8525 there is an attribute definition in the md file:
8528 (define_attr "mnemonic" "unknown" (const_string "unknown"))
8531 The default value can be freely chosen as long as it does not collide
8532 with any of the instruction mnemonics. This value will be used
8533 whenever the machine description parser is not able to determine the
8534 mnemonic string. This might be the case for output templates
8535 containing more than a single instruction as in
8536 @code{"mvcle\t%0,%1,0\;jo\t.-4"}.
8538 The @code{mnemonic} attribute set is not generated automatically if the
8539 instruction string is generated via C code.
8541 An existing @code{mnemonic} attribute set in an insn definition will not
8542 be overriden by the md file parser. That way it is possible to
8543 manually set the instruction mnemonics for the cases where the md file
8544 parser fails to determine it automatically.
8546 The @code{mnemonic} attribute is useful for dealing with instruction
8547 specific properties in the pipeline description without defining
8548 additional insn attributes.
8551 (define_attr "ooo_expanded" ""
8552 (cond [(eq_attr "mnemonic" "dlr,dsgr,d,dsgf,stam,dsgfr,dlgr")
8560 @subsection Delay Slot Scheduling
8561 @cindex delay slots, defining
8563 The insn attribute mechanism can be used to specify the requirements for
8564 delay slots, if any, on a target machine. An instruction is said to
8565 require a @dfn{delay slot} if some instructions that are physically
8566 after the instruction are executed as if they were located before it.
8567 Classic examples are branch and call instructions, which often execute
8568 the following instruction before the branch or call is performed.
8570 On some machines, conditional branch instructions can optionally
8571 @dfn{annul} instructions in the delay slot. This means that the
8572 instruction will not be executed for certain branch outcomes. Both
8573 instructions that annul if the branch is true and instructions that
8574 annul if the branch is false are supported.
8576 Delay slot scheduling differs from instruction scheduling in that
8577 determining whether an instruction needs a delay slot is dependent only
8578 on the type of instruction being generated, not on data flow between the
8579 instructions. See the next section for a discussion of data-dependent
8580 instruction scheduling.
8582 @findex define_delay
8583 The requirement of an insn needing one or more delay slots is indicated
8584 via the @code{define_delay} expression. It has the following form:
8587 (define_delay @var{test}
8588 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
8589 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
8593 @var{test} is an attribute test that indicates whether this
8594 @code{define_delay} applies to a particular insn. If so, the number of
8595 required delay slots is determined by the length of the vector specified
8596 as the second argument. An insn placed in delay slot @var{n} must
8597 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
8598 attribute test that specifies which insns may be annulled if the branch
8599 is true. Similarly, @var{annul-false-n} specifies which insns in the
8600 delay slot may be annulled if the branch is false. If annulling is not
8601 supported for that delay slot, @code{(nil)} should be coded.
8603 For example, in the common case where branch and call insns require
8604 a single delay slot, which may contain any insn other than a branch or
8605 call, the following would be placed in the @file{md} file:
8608 (define_delay (eq_attr "type" "branch,call")
8609 [(eq_attr "type" "!branch,call") (nil) (nil)])
8612 Multiple @code{define_delay} expressions may be specified. In this
8613 case, each such expression specifies different delay slot requirements
8614 and there must be no insn for which tests in two @code{define_delay}
8615 expressions are both true.
8617 For example, if we have a machine that requires one delay slot for branches
8618 but two for calls, no delay slot can contain a branch or call insn,
8619 and any valid insn in the delay slot for the branch can be annulled if the
8620 branch is true, we might represent this as follows:
8623 (define_delay (eq_attr "type" "branch")
8624 [(eq_attr "type" "!branch,call")
8625 (eq_attr "type" "!branch,call")
8628 (define_delay (eq_attr "type" "call")
8629 [(eq_attr "type" "!branch,call") (nil) (nil)
8630 (eq_attr "type" "!branch,call") (nil) (nil)])
8632 @c the above is *still* too long. --mew 4feb93
8636 @node Processor pipeline description
8637 @subsection Specifying processor pipeline description
8638 @cindex processor pipeline description
8639 @cindex processor functional units
8640 @cindex instruction latency time
8641 @cindex interlock delays
8642 @cindex data dependence delays
8643 @cindex reservation delays
8644 @cindex pipeline hazard recognizer
8645 @cindex automaton based pipeline description
8646 @cindex regular expressions
8647 @cindex deterministic finite state automaton
8648 @cindex automaton based scheduler
8652 To achieve better performance, most modern processors
8653 (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
8654 processors) have many @dfn{functional units} on which several
8655 instructions can be executed simultaneously. An instruction starts
8656 execution if its issue conditions are satisfied. If not, the
8657 instruction is stalled until its conditions are satisfied. Such
8658 @dfn{interlock (pipeline) delay} causes interruption of the fetching
8659 of successor instructions (or demands nop instructions, e.g.@: for some
8662 There are two major kinds of interlock delays in modern processors.
8663 The first one is a data dependence delay determining @dfn{instruction
8664 latency time}. The instruction execution is not started until all
8665 source data have been evaluated by prior instructions (there are more
8666 complex cases when the instruction execution starts even when the data
8667 are not available but will be ready in given time after the
8668 instruction execution start). Taking the data dependence delays into
8669 account is simple. The data dependence (true, output, and
8670 anti-dependence) delay between two instructions is given by a
8671 constant. In most cases this approach is adequate. The second kind
8672 of interlock delays is a reservation delay. The reservation delay
8673 means that two instructions under execution will be in need of shared
8674 processors resources, i.e.@: buses, internal registers, and/or
8675 functional units, which are reserved for some time. Taking this kind
8676 of delay into account is complex especially for modern @acronym{RISC}
8679 The task of exploiting more processor parallelism is solved by an
8680 instruction scheduler. For a better solution to this problem, the
8681 instruction scheduler has to have an adequate description of the
8682 processor parallelism (or @dfn{pipeline description}). GCC
8683 machine descriptions describe processor parallelism and functional
8684 unit reservations for groups of instructions with the aid of
8685 @dfn{regular expressions}.
8687 The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to
8688 figure out the possibility of the instruction issue by the processor
8689 on a given simulated processor cycle. The pipeline hazard recognizer is
8690 automatically generated from the processor pipeline description. The
8691 pipeline hazard recognizer generated from the machine description
8692 is based on a deterministic finite state automaton (@acronym{DFA}):
8693 the instruction issue is possible if there is a transition from one
8694 automaton state to another one. This algorithm is very fast, and
8695 furthermore, its speed is not dependent on processor
8696 complexity@footnote{However, the size of the automaton depends on
8697 processor complexity. To limit this effect, machine descriptions
8698 can split orthogonal parts of the machine description among several
8699 automata: but then, since each of these must be stepped independently,
8700 this does cause a small decrease in the algorithm's performance.}.
8702 @cindex automaton based pipeline description
8703 The rest of this section describes the directives that constitute
8704 an automaton-based processor pipeline description. The order of
8705 these constructions within the machine description file is not
8708 @findex define_automaton
8709 @cindex pipeline hazard recognizer
8710 The following optional construction describes names of automata
8711 generated and used for the pipeline hazards recognition. Sometimes
8712 the generated finite state automaton used by the pipeline hazard
8713 recognizer is large. If we use more than one automaton and bind functional
8714 units to the automata, the total size of the automata is usually
8715 less than the size of the single automaton. If there is no one such
8716 construction, only one finite state automaton is generated.
8719 (define_automaton @var{automata-names})
8722 @var{automata-names} is a string giving names of the automata. The
8723 names are separated by commas. All the automata should have unique names.
8724 The automaton name is used in the constructions @code{define_cpu_unit} and
8725 @code{define_query_cpu_unit}.
8727 @findex define_cpu_unit
8728 @cindex processor functional units
8729 Each processor functional unit used in the description of instruction
8730 reservations should be described by the following construction.
8733 (define_cpu_unit @var{unit-names} [@var{automaton-name}])
8736 @var{unit-names} is a string giving the names of the functional units
8737 separated by commas. Don't use name @samp{nothing}, it is reserved
8740 @var{automaton-name} is a string giving the name of the automaton with
8741 which the unit is bound. The automaton should be described in
8742 construction @code{define_automaton}. You should give
8743 @dfn{automaton-name}, if there is a defined automaton.
8745 The assignment of units to automata are constrained by the uses of the
8746 units in insn reservations. The most important constraint is: if a
8747 unit reservation is present on a particular cycle of an alternative
8748 for an insn reservation, then some unit from the same automaton must
8749 be present on the same cycle for the other alternatives of the insn
8750 reservation. The rest of the constraints are mentioned in the
8751 description of the subsequent constructions.
8753 @findex define_query_cpu_unit
8754 @cindex querying function unit reservations
8755 The following construction describes CPU functional units analogously
8756 to @code{define_cpu_unit}. The reservation of such units can be
8757 queried for an automaton state. The instruction scheduler never
8758 queries reservation of functional units for given automaton state. So
8759 as a rule, you don't need this construction. This construction could
8760 be used for future code generation goals (e.g.@: to generate
8761 @acronym{VLIW} insn templates).
8764 (define_query_cpu_unit @var{unit-names} [@var{automaton-name}])
8767 @var{unit-names} is a string giving names of the functional units
8768 separated by commas.
8770 @var{automaton-name} is a string giving the name of the automaton with
8771 which the unit is bound.
8773 @findex define_insn_reservation
8774 @cindex instruction latency time
8775 @cindex regular expressions
8777 The following construction is the major one to describe pipeline
8778 characteristics of an instruction.
8781 (define_insn_reservation @var{insn-name} @var{default_latency}
8782 @var{condition} @var{regexp})
8785 @var{default_latency} is a number giving latency time of the
8786 instruction. There is an important difference between the old
8787 description and the automaton based pipeline description. The latency
8788 time is used for all dependencies when we use the old description. In
8789 the automaton based pipeline description, the given latency time is only
8790 used for true dependencies. The cost of anti-dependencies is always
8791 zero and the cost of output dependencies is the difference between
8792 latency times of the producing and consuming insns (if the difference
8793 is negative, the cost is considered to be zero). You can always
8794 change the default costs for any description by using the target hook
8795 @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
8797 @var{insn-name} is a string giving the internal name of the insn. The
8798 internal names are used in constructions @code{define_bypass} and in
8799 the automaton description file generated for debugging. The internal
8800 name has nothing in common with the names in @code{define_insn}. It is a
8801 good practice to use insn classes described in the processor manual.
8803 @var{condition} defines what RTL insns are described by this
8804 construction. You should remember that you will be in trouble if
8805 @var{condition} for two or more different
8806 @code{define_insn_reservation} constructions is TRUE for an insn. In
8807 this case what reservation will be used for the insn is not defined.
8808 Such cases are not checked during generation of the pipeline hazards
8809 recognizer because in general recognizing that two conditions may have
8810 the same value is quite difficult (especially if the conditions
8811 contain @code{symbol_ref}). It is also not checked during the
8812 pipeline hazard recognizer work because it would slow down the
8813 recognizer considerably.
8815 @var{regexp} is a string describing the reservation of the cpu's functional
8816 units by the instruction. The reservations are described by a regular
8817 expression according to the following syntax:
8820 regexp = regexp "," oneof
8823 oneof = oneof "|" allof
8826 allof = allof "+" repeat
8829 repeat = element "*" number
8832 element = cpu_function_unit_name
8841 @samp{,} is used for describing the start of the next cycle in
8845 @samp{|} is used for describing a reservation described by the first
8846 regular expression @strong{or} a reservation described by the second
8847 regular expression @strong{or} etc.
8850 @samp{+} is used for describing a reservation described by the first
8851 regular expression @strong{and} a reservation described by the
8852 second regular expression @strong{and} etc.
8855 @samp{*} is used for convenience and simply means a sequence in which
8856 the regular expression are repeated @var{number} times with cycle
8857 advancing (see @samp{,}).
8860 @samp{cpu_function_unit_name} denotes reservation of the named
8864 @samp{reservation_name} --- see description of construction
8865 @samp{define_reservation}.
8868 @samp{nothing} denotes no unit reservations.
8871 @findex define_reservation
8872 Sometimes unit reservations for different insns contain common parts.
8873 In such case, you can simplify the pipeline description by describing
8874 the common part by the following construction
8877 (define_reservation @var{reservation-name} @var{regexp})
8880 @var{reservation-name} is a string giving name of @var{regexp}.
8881 Functional unit names and reservation names are in the same name
8882 space. So the reservation names should be different from the
8883 functional unit names and can not be the reserved name @samp{nothing}.
8885 @findex define_bypass
8886 @cindex instruction latency time
8888 The following construction is used to describe exceptions in the
8889 latency time for given instruction pair. This is so called bypasses.
8892 (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names}
8896 @var{number} defines when the result generated by the instructions
8897 given in string @var{out_insn_names} will be ready for the
8898 instructions given in string @var{in_insn_names}. Each of these
8899 strings is a comma-separated list of filename-style globs and
8900 they refer to the names of @code{define_insn_reservation}s.
8903 (define_bypass 1 "cpu1_load_*, cpu1_store_*" "cpu1_load_*")
8905 defines a bypass between instructions that start with
8906 @samp{cpu1_load_} or @samp{cpu1_store_} and those that start with
8909 @var{guard} is an optional string giving the name of a C function which
8910 defines an additional guard for the bypass. The function will get the
8911 two insns as parameters. If the function returns zero the bypass will
8912 be ignored for this case. The additional guard is necessary to
8913 recognize complicated bypasses, e.g.@: when the consumer is only an address
8914 of insn @samp{store} (not a stored value).
8916 If there are more one bypass with the same output and input insns, the
8917 chosen bypass is the first bypass with a guard in description whose
8918 guard function returns nonzero. If there is no such bypass, then
8919 bypass without the guard function is chosen.
8921 @findex exclusion_set
8922 @findex presence_set
8923 @findex final_presence_set
8925 @findex final_absence_set
8928 The following five constructions are usually used to describe
8929 @acronym{VLIW} processors, or more precisely, to describe a placement
8930 of small instructions into @acronym{VLIW} instruction slots. They
8931 can be used for @acronym{RISC} processors, too.
8934 (exclusion_set @var{unit-names} @var{unit-names})
8935 (presence_set @var{unit-names} @var{patterns})
8936 (final_presence_set @var{unit-names} @var{patterns})
8937 (absence_set @var{unit-names} @var{patterns})
8938 (final_absence_set @var{unit-names} @var{patterns})
8941 @var{unit-names} is a string giving names of functional units
8942 separated by commas.
8944 @var{patterns} is a string giving patterns of functional units
8945 separated by comma. Currently pattern is one unit or units
8946 separated by white-spaces.
8948 The first construction (@samp{exclusion_set}) means that each
8949 functional unit in the first string can not be reserved simultaneously
8950 with a unit whose name is in the second string and vice versa. For
8951 example, the construction is useful for describing processors
8952 (e.g.@: some SPARC processors) with a fully pipelined floating point
8953 functional unit which can execute simultaneously only single floating
8954 point insns or only double floating point insns.
8956 The second construction (@samp{presence_set}) means that each
8957 functional unit in the first string can not be reserved unless at
8958 least one of pattern of units whose names are in the second string is
8959 reserved. This is an asymmetric relation. For example, it is useful
8960 for description that @acronym{VLIW} @samp{slot1} is reserved after
8961 @samp{slot0} reservation. We could describe it by the following
8965 (presence_set "slot1" "slot0")
8968 Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0}
8969 reservation. In this case we could write
8972 (presence_set "slot1" "slot0 b0")
8975 The third construction (@samp{final_presence_set}) is analogous to
8976 @samp{presence_set}. The difference between them is when checking is
8977 done. When an instruction is issued in given automaton state
8978 reflecting all current and planned unit reservations, the automaton
8979 state is changed. The first state is a source state, the second one
8980 is a result state. Checking for @samp{presence_set} is done on the
8981 source state reservation, checking for @samp{final_presence_set} is
8982 done on the result reservation. This construction is useful to
8983 describe a reservation which is actually two subsequent reservations.
8984 For example, if we use
8987 (presence_set "slot1" "slot0")
8990 the following insn will be never issued (because @samp{slot1} requires
8991 @samp{slot0} which is absent in the source state).
8994 (define_reservation "insn_and_nop" "slot0 + slot1")
8997 but it can be issued if we use analogous @samp{final_presence_set}.
8999 The forth construction (@samp{absence_set}) means that each functional
9000 unit in the first string can be reserved only if each pattern of units
9001 whose names are in the second string is not reserved. This is an
9002 asymmetric relation (actually @samp{exclusion_set} is analogous to
9003 this one but it is symmetric). For example it might be useful in a
9004 @acronym{VLIW} description to say that @samp{slot0} cannot be reserved
9005 after either @samp{slot1} or @samp{slot2} have been reserved. This
9006 can be described as:
9009 (absence_set "slot0" "slot1, slot2")
9012 Or @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0}
9013 are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
9014 this case we could write
9017 (absence_set "slot2" "slot0 b0, slot1 b1")
9020 All functional units mentioned in a set should belong to the same
9023 The last construction (@samp{final_absence_set}) is analogous to
9024 @samp{absence_set} but checking is done on the result (state)
9025 reservation. See comments for @samp{final_presence_set}.
9027 @findex automata_option
9028 @cindex deterministic finite state automaton
9029 @cindex nondeterministic finite state automaton
9030 @cindex finite state automaton minimization
9031 You can control the generator of the pipeline hazard recognizer with
9032 the following construction.
9035 (automata_option @var{options})
9038 @var{options} is a string giving options which affect the generated
9039 code. Currently there are the following options:
9043 @dfn{no-minimization} makes no minimization of the automaton. This is
9044 only worth to do when we are debugging the description and need to
9045 look more accurately at reservations of states.
9048 @dfn{time} means printing time statistics about the generation of
9052 @dfn{stats} means printing statistics about the generated automata
9053 such as the number of DFA states, NDFA states and arcs.
9056 @dfn{v} means a generation of the file describing the result automata.
9057 The file has suffix @samp{.dfa} and can be used for the description
9058 verification and debugging.
9061 @dfn{w} means a generation of warning instead of error for
9062 non-critical errors.
9065 @dfn{no-comb-vect} prevents the automaton generator from generating
9066 two data structures and comparing them for space efficiency. Using
9067 a comb vector to represent transitions may be better, but it can be
9068 very expensive to construct. This option is useful if the build
9069 process spends an unacceptably long time in genautomata.
9072 @dfn{ndfa} makes nondeterministic finite state automata. This affects
9073 the treatment of operator @samp{|} in the regular expressions. The
9074 usual treatment of the operator is to try the first alternative and,
9075 if the reservation is not possible, the second alternative. The
9076 nondeterministic treatment means trying all alternatives, some of them
9077 may be rejected by reservations in the subsequent insns.
9080 @dfn{collapse-ndfa} modifies the behaviour of the generator when
9081 producing an automaton. An additional state transition to collapse a
9082 nondeterministic @acronym{NDFA} state to a deterministic @acronym{DFA}
9083 state is generated. It can be triggered by passing @code{const0_rtx} to
9084 state_transition. In such an automaton, cycle advance transitions are
9085 available only for these collapsed states. This option is useful for
9086 ports that want to use the @code{ndfa} option, but also want to use
9087 @code{define_query_cpu_unit} to assign units to insns issued in a cycle.
9090 @dfn{progress} means output of a progress bar showing how many states
9091 were generated so far for automaton being processed. This is useful
9092 during debugging a @acronym{DFA} description. If you see too many
9093 generated states, you could interrupt the generator of the pipeline
9094 hazard recognizer and try to figure out a reason for generation of the
9098 As an example, consider a superscalar @acronym{RISC} machine which can
9099 issue three insns (two integer insns and one floating point insn) on
9100 the cycle but can finish only two insns. To describe this, we define
9101 the following functional units.
9104 (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline")
9105 (define_cpu_unit "port0, port1")
9108 All simple integer insns can be executed in any integer pipeline and
9109 their result is ready in two cycles. The simple integer insns are
9110 issued into the first pipeline unless it is reserved, otherwise they
9111 are issued into the second pipeline. Integer division and
9112 multiplication insns can be executed only in the second integer
9113 pipeline and their results are ready correspondingly in 8 and 4
9114 cycles. The integer division is not pipelined, i.e.@: the subsequent
9115 integer division insn can not be issued until the current division
9116 insn finished. Floating point insns are fully pipelined and their
9117 results are ready in 3 cycles. Where the result of a floating point
9118 insn is used by an integer insn, an additional delay of one cycle is
9119 incurred. To describe all of this we could specify
9122 (define_cpu_unit "div")
9124 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
9125 "(i0_pipeline | i1_pipeline), (port0 | port1)")
9127 (define_insn_reservation "mult" 4 (eq_attr "type" "mult")
9128 "i1_pipeline, nothing*2, (port0 | port1)")
9130 (define_insn_reservation "div" 8 (eq_attr "type" "div")
9131 "i1_pipeline, div*7, div + (port0 | port1)")
9133 (define_insn_reservation "float" 3 (eq_attr "type" "float")
9134 "f_pipeline, nothing, (port0 | port1))
9136 (define_bypass 4 "float" "simple,mult,div")
9139 To simplify the description we could describe the following reservation
9142 (define_reservation "finish" "port0|port1")
9145 and use it in all @code{define_insn_reservation} as in the following
9149 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
9150 "(i0_pipeline | i1_pipeline), finish")
9156 @node Conditional Execution
9157 @section Conditional Execution
9158 @cindex conditional execution
9161 A number of architectures provide for some form of conditional
9162 execution, or predication. The hallmark of this feature is the
9163 ability to nullify most of the instructions in the instruction set.
9164 When the instruction set is large and not entirely symmetric, it
9165 can be quite tedious to describe these forms directly in the
9166 @file{.md} file. An alternative is the @code{define_cond_exec} template.
9168 @findex define_cond_exec
9171 [@var{predicate-pattern}]
9173 "@var{output-template}"
9174 "@var{optional-insn-attribues}")
9177 @var{predicate-pattern} is the condition that must be true for the
9178 insn to be executed at runtime and should match a relational operator.
9179 One can use @code{match_operator} to match several relational operators
9180 at once. Any @code{match_operand} operands must have no more than one
9183 @var{condition} is a C expression that must be true for the generated
9186 @findex current_insn_predicate
9187 @var{output-template} is a string similar to the @code{define_insn}
9188 output template (@pxref{Output Template}), except that the @samp{*}
9189 and @samp{@@} special cases do not apply. This is only useful if the
9190 assembly text for the predicate is a simple prefix to the main insn.
9191 In order to handle the general case, there is a global variable
9192 @code{current_insn_predicate} that will contain the entire predicate
9193 if the current insn is predicated, and will otherwise be @code{NULL}.
9195 @var{optional-insn-attributes} is an optional vector of attributes that gets
9196 appended to the insn attributes of the produced cond_exec rtx. It can
9197 be used to add some distinguishing attribute to cond_exec rtxs produced
9198 that way. An example usage would be to use this attribute in conjunction
9199 with attributes on the main pattern to disable particular alternatives under
9202 When @code{define_cond_exec} is used, an implicit reference to
9203 the @code{predicable} instruction attribute is made.
9204 @xref{Insn Attributes}. This attribute must be a boolean (i.e.@: have
9205 exactly two elements in its @var{list-of-values}), with the possible
9206 values being @code{no} and @code{yes}. The default and all uses in
9207 the insns must be a simple constant, not a complex expressions. It
9208 may, however, depend on the alternative, by using a comma-separated
9209 list of values. If that is the case, the port should also define an
9210 @code{enabled} attribute (@pxref{Disable Insn Alternatives}), which
9211 should also allow only @code{no} and @code{yes} as its values.
9213 For each @code{define_insn} for which the @code{predicable}
9214 attribute is true, a new @code{define_insn} pattern will be
9215 generated that matches a predicated version of the instruction.
9219 (define_insn "addsi"
9220 [(set (match_operand:SI 0 "register_operand" "r")
9221 (plus:SI (match_operand:SI 1 "register_operand" "r")
9222 (match_operand:SI 2 "register_operand" "r")))]
9227 [(ne (match_operand:CC 0 "register_operand" "c")
9234 generates a new pattern
9239 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
9240 (set (match_operand:SI 0 "register_operand" "r")
9241 (plus:SI (match_operand:SI 1 "register_operand" "r")
9242 (match_operand:SI 2 "register_operand" "r"))))]
9243 "(@var{test2}) && (@var{test1})"
9244 "(%3) add %2,%1,%0")
9250 @section RTL Templates Transformations
9251 @cindex define_subst
9253 For some hardware architectures there are common cases when the RTL
9254 templates for the instructions can be derived from the other RTL
9255 templates using simple transformations. E.g., @file{i386.md} contains
9256 an RTL template for the ordinary @code{sub} instruction---
9257 @code{*subsi_1}, and for the @code{sub} instruction with subsequent
9258 zero-extension---@code{*subsi_1_zext}. Such cases can be easily
9259 implemented by a single meta-template capable of generating a modified
9260 case based on the initial one:
9262 @findex define_subst
9264 (define_subst "@var{name}"
9265 [@var{input-template}]
9267 [@var{output-template}])
9269 @var{input-template} is a pattern describing the source RTL template,
9270 which will be transformed.
9272 @var{condition} is a C expression that is conjunct with the condition
9273 from the input-template to generate a condition to be used in the
9276 @var{output-template} is a pattern that will be used in the resulting
9279 @code{define_subst} mechanism is tightly coupled with the notion of the
9280 subst attribute (@pxref{Subst Iterators}). The use of
9281 @code{define_subst} is triggered by a reference to a subst attribute in
9282 the transforming RTL template. This reference initiates duplication of
9283 the source RTL template and substitution of the attributes with their
9284 values. The source RTL template is left unchanged, while the copy is
9285 transformed by @code{define_subst}. This transformation can fail in the
9286 case when the source RTL template is not matched against the
9287 input-template of the @code{define_subst}. In such case the copy is
9290 @code{define_subst} can be used only in @code{define_insn} and
9291 @code{define_expand}, it cannot be used in other expressions (e.g. in
9292 @code{define_insn_and_split}).
9295 * Define Subst Example:: Example of @code{define_subst} work.
9296 * Define Subst Pattern Matching:: Process of template comparison.
9297 * Define Subst Output Template:: Generation of output template.
9300 @node Define Subst Example
9301 @subsection @code{define_subst} Example
9302 @cindex define_subst
9304 To illustrate how @code{define_subst} works, let us examine a simple
9305 template transformation.
9307 Suppose there are two kinds of instructions: one that touches flags and
9308 the other that does not. The instructions of the second type could be
9309 generated with the following @code{define_subst}:
9312 (define_subst "add_clobber_subst"
9313 [(set (match_operand:SI 0 "" "")
9314 (match_operand:SI 1 "" ""))]
9318 (clobber (reg:CC FLAGS_REG))]
9321 This @code{define_subst} can be applied to any RTL pattern containing
9322 @code{set} of mode SI and generates a copy with clobber when it is
9325 Assume there is an RTL template for a @code{max} instruction to be used
9326 in @code{define_subst} mentioned above:
9329 (define_insn "maxsi"
9330 [(set (match_operand:SI 0 "register_operand" "=r")
9332 (match_operand:SI 1 "register_operand" "r")
9333 (match_operand:SI 2 "register_operand" "r")))]
9335 "max\t@{%2, %1, %0|%0, %1, %2@}"
9339 To mark the RTL template for @code{define_subst} application,
9340 subst-attributes are used. They should be declared in advance:
9343 (define_subst_attr "add_clobber_name" "add_clobber_subst" "_noclobber" "_clobber")
9346 Here @samp{add_clobber_name} is the attribute name,
9347 @samp{add_clobber_subst} is the name of the corresponding
9348 @code{define_subst}, the third argument (@samp{_noclobber}) is the
9349 attribute value that would be substituted into the unchanged version of
9350 the source RTL template, and the last argument (@samp{_clobber}) is the
9351 value that would be substituted into the second, transformed,
9352 version of the RTL template.
9354 Once the subst-attribute has been defined, it should be used in RTL
9355 templates which need to be processed by the @code{define_subst}. So,
9356 the original RTL template should be changed:
9359 (define_insn "maxsi<add_clobber_name>"
9360 [(set (match_operand:SI 0 "register_operand" "=r")
9362 (match_operand:SI 1 "register_operand" "r")
9363 (match_operand:SI 2 "register_operand" "r")))]
9365 "max\t@{%2, %1, %0|%0, %1, %2@}"
9369 The result of the @code{define_subst} usage would look like the following:
9372 (define_insn "maxsi_noclobber"
9373 [(set (match_operand:SI 0 "register_operand" "=r")
9375 (match_operand:SI 1 "register_operand" "r")
9376 (match_operand:SI 2 "register_operand" "r")))]
9378 "max\t@{%2, %1, %0|%0, %1, %2@}"
9380 (define_insn "maxsi_clobber"
9381 [(set (match_operand:SI 0 "register_operand" "=r")
9383 (match_operand:SI 1 "register_operand" "r")
9384 (match_operand:SI 2 "register_operand" "r")))
9385 (clobber (reg:CC FLAGS_REG))]
9387 "max\t@{%2, %1, %0|%0, %1, %2@}"
9391 @node Define Subst Pattern Matching
9392 @subsection Pattern Matching in @code{define_subst}
9393 @cindex define_subst
9395 All expressions, allowed in @code{define_insn} or @code{define_expand},
9396 are allowed in the input-template of @code{define_subst}, except
9397 @code{match_par_dup}, @code{match_scratch}, @code{match_parallel}. The
9398 meanings of expressions in the input-template were changed:
9400 @code{match_operand} matches any expression (possibly, a subtree in
9401 RTL-template), if modes of the @code{match_operand} and this expression
9402 are the same, or mode of the @code{match_operand} is @code{VOIDmode}, or
9403 this expression is @code{match_dup}, @code{match_op_dup}. If the
9404 expression is @code{match_operand} too, and predicate of
9405 @code{match_operand} from the input pattern is not empty, then the
9406 predicates are compared. That can be used for more accurate filtering
9407 of accepted RTL-templates.
9409 @code{match_operator} matches common operators (like @code{plus},
9410 @code{minus}), @code{unspec}, @code{unspec_volatile} operators and
9411 @code{match_operator}s from the original pattern if the modes match and
9412 @code{match_operator} from the input pattern has the same number of
9413 operands as the operator from the original pattern.
9415 @node Define Subst Output Template
9416 @subsection Generation of output template in @code{define_subst}
9417 @cindex define_subst
9419 If all necessary checks for @code{define_subst} application pass, a new
9420 RTL-pattern, based on the output-template, is created to replace the old
9421 template. Like in input-patterns, meanings of some RTL expressions are
9422 changed when they are used in output-patterns of a @code{define_subst}.
9423 Thus, @code{match_dup} is used for copying the whole expression from the
9424 original pattern, which matched corresponding @code{match_operand} from
9427 @code{match_dup N} is used in the output template to be replaced with
9428 the expression from the original pattern, which matched
9429 @code{match_operand N} from the input pattern. As a consequence,
9430 @code{match_dup} cannot be used to point to @code{match_operand}s from
9431 the output pattern, it should always refer to a @code{match_operand}
9432 from the input pattern.
9434 In the output template one can refer to the expressions from the
9435 original pattern and create new ones. For instance, some operands could
9436 be added by means of standard @code{match_operand}.
9438 After replacing @code{match_dup} with some RTL-subtree from the original
9439 pattern, it could happen that several @code{match_operand}s in the
9440 output pattern have the same indexes. It is unknown, how many and what
9441 indexes would be used in the expression which would replace
9442 @code{match_dup}, so such conflicts in indexes are inevitable. To
9443 overcome this issue, @code{match_operands} and @code{match_operators},
9444 which were introduced into the output pattern, are renumerated when all
9445 @code{match_dup}s are replaced.
9447 Number of alternatives in @code{match_operand}s introduced into the
9448 output template @code{M} could differ from the number of alternatives in
9449 the original pattern @code{N}, so in the resultant pattern there would
9450 be @code{N*M} alternatives. Thus, constraints from the original pattern
9451 would be duplicated @code{N} times, constraints from the output pattern
9452 would be duplicated @code{M} times, producing all possible combinations.
9456 @node Constant Definitions
9457 @section Constant Definitions
9458 @cindex constant definitions
9459 @findex define_constants
9461 Using literal constants inside instruction patterns reduces legibility and
9462 can be a maintenance problem.
9464 To overcome this problem, you may use the @code{define_constants}
9465 expression. It contains a vector of name-value pairs. From that
9466 point on, wherever any of the names appears in the MD file, it is as
9467 if the corresponding value had been written instead. You may use
9468 @code{define_constants} multiple times; each appearance adds more
9469 constants to the table. It is an error to redefine a constant with
9472 To come back to the a29k load multiple example, instead of
9476 [(match_parallel 0 "load_multiple_operation"
9477 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
9478 (match_operand:SI 2 "memory_operand" "m"))
9480 (clobber (reg:SI 179))])]
9496 [(match_parallel 0 "load_multiple_operation"
9497 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
9498 (match_operand:SI 2 "memory_operand" "m"))
9500 (clobber (reg:SI R_CR))])]
9505 The constants that are defined with a define_constant are also output
9506 in the insn-codes.h header file as #defines.
9508 @cindex enumerations
9509 @findex define_c_enum
9510 You can also use the machine description file to define enumerations.
9511 Like the constants defined by @code{define_constant}, these enumerations
9512 are visible to both the machine description file and the main C code.
9514 The syntax is as follows:
9517 (define_c_enum "@var{name}" [
9525 This definition causes the equivalent of the following C code to appear
9526 in @file{insn-constants.h}:
9533 @var{valuen} = @var{n}
9535 #define NUM_@var{cname}_VALUES (@var{n} + 1)
9538 where @var{cname} is the capitalized form of @var{name}.
9539 It also makes each @var{valuei} available in the machine description
9540 file, just as if it had been declared with:
9543 (define_constants [(@var{valuei} @var{i})])
9546 Each @var{valuei} is usually an upper-case identifier and usually
9547 begins with @var{cname}.
9549 You can split the enumeration definition into as many statements as
9550 you like. The above example is directly equivalent to:
9553 (define_c_enum "@var{name}" [@var{value0}])
9554 (define_c_enum "@var{name}" [@var{value1}])
9556 (define_c_enum "@var{name}" [@var{valuen}])
9559 Splitting the enumeration helps to improve the modularity of each
9560 individual @code{.md} file. For example, if a port defines its
9561 synchronization instructions in a separate @file{sync.md} file,
9562 it is convenient to define all synchronization-specific enumeration
9563 values in @file{sync.md} rather than in the main @file{.md} file.
9565 Some enumeration names have special significance to GCC:
9569 @findex unspec_volatile
9570 If an enumeration called @code{unspecv} is defined, GCC will use it
9571 when printing out @code{unspec_volatile} expressions. For example:
9574 (define_c_enum "unspecv" [
9579 causes GCC to print @samp{(unspec_volatile @dots{} 0)} as:
9582 (unspec_volatile ... UNSPECV_BLOCKAGE)
9587 If an enumeration called @code{unspec} is defined, GCC will use
9588 it when printing out @code{unspec} expressions. GCC will also use
9589 it when printing out @code{unspec_volatile} expressions unless an
9590 @code{unspecv} enumeration is also defined. You can therefore
9591 decide whether to keep separate enumerations for volatile and
9592 non-volatile expressions or whether to use the same enumeration
9597 @anchor{define_enum}
9598 Another way of defining an enumeration is to use @code{define_enum}:
9601 (define_enum "@var{name}" [
9609 This directive implies:
9612 (define_c_enum "@var{name}" [
9613 @var{cname}_@var{cvalue0}
9614 @var{cname}_@var{cvalue1}
9616 @var{cname}_@var{cvaluen}
9620 @findex define_enum_attr
9621 where @var{cvaluei} is the capitalized form of @var{valuei}.
9622 However, unlike @code{define_c_enum}, the enumerations defined
9623 by @code{define_enum} can be used in attribute specifications
9624 (@pxref{define_enum_attr}).
9629 @cindex iterators in @file{.md} files
9631 Ports often need to define similar patterns for more than one machine
9632 mode or for more than one rtx code. GCC provides some simple iterator
9633 facilities to make this process easier.
9636 * Mode Iterators:: Generating variations of patterns for different modes.
9637 * Code Iterators:: Doing the same for codes.
9638 * Int Iterators:: Doing the same for integers.
9639 * Subst Iterators:: Generating variations of patterns for define_subst.
9642 @node Mode Iterators
9643 @subsection Mode Iterators
9644 @cindex mode iterators in @file{.md} files
9646 Ports often need to define similar patterns for two or more different modes.
9651 If a processor has hardware support for both single and double
9652 floating-point arithmetic, the @code{SFmode} patterns tend to be
9653 very similar to the @code{DFmode} ones.
9656 If a port uses @code{SImode} pointers in one configuration and
9657 @code{DImode} pointers in another, it will usually have very similar
9658 @code{SImode} and @code{DImode} patterns for manipulating pointers.
9661 Mode iterators allow several patterns to be instantiated from one
9662 @file{.md} file template. They can be used with any type of
9663 rtx-based construct, such as a @code{define_insn},
9664 @code{define_split}, or @code{define_peephole2}.
9667 * Defining Mode Iterators:: Defining a new mode iterator.
9668 * Substitutions:: Combining mode iterators with substitutions
9669 * Examples:: Examples
9672 @node Defining Mode Iterators
9673 @subsubsection Defining Mode Iterators
9674 @findex define_mode_iterator
9676 The syntax for defining a mode iterator is:
9679 (define_mode_iterator @var{name} [(@var{mode1} "@var{cond1}") @dots{} (@var{moden} "@var{condn}")])
9682 This allows subsequent @file{.md} file constructs to use the mode suffix
9683 @code{:@var{name}}. Every construct that does so will be expanded
9684 @var{n} times, once with every use of @code{:@var{name}} replaced by
9685 @code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}},
9686 and so on. In the expansion for a particular @var{modei}, every
9687 C condition will also require that @var{condi} be true.
9692 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
9695 defines a new mode suffix @code{:P}. Every construct that uses
9696 @code{:P} will be expanded twice, once with every @code{:P} replaced
9697 by @code{:SI} and once with every @code{:P} replaced by @code{:DI}.
9698 The @code{:SI} version will only apply if @code{Pmode == SImode} and
9699 the @code{:DI} version will only apply if @code{Pmode == DImode}.
9701 As with other @file{.md} conditions, an empty string is treated
9702 as ``always true''. @code{(@var{mode} "")} can also be abbreviated
9703 to @code{@var{mode}}. For example:
9706 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
9709 means that the @code{:DI} expansion only applies if @code{TARGET_64BIT}
9710 but that the @code{:SI} expansion has no such constraint.
9712 Iterators are applied in the order they are defined. This can be
9713 significant if two iterators are used in a construct that requires
9714 substitutions. @xref{Substitutions}.
9717 @subsubsection Substitution in Mode Iterators
9718 @findex define_mode_attr
9720 If an @file{.md} file construct uses mode iterators, each version of the
9721 construct will often need slightly different strings or modes. For
9726 When a @code{define_expand} defines several @code{add@var{m}3} patterns
9727 (@pxref{Standard Names}), each expander will need to use the
9728 appropriate mode name for @var{m}.
9731 When a @code{define_insn} defines several instruction patterns,
9732 each instruction will often use a different assembler mnemonic.
9735 When a @code{define_insn} requires operands with different modes,
9736 using an iterator for one of the operand modes usually requires a specific
9737 mode for the other operand(s).
9740 GCC supports such variations through a system of ``mode attributes''.
9741 There are two standard attributes: @code{mode}, which is the name of
9742 the mode in lower case, and @code{MODE}, which is the same thing in
9743 upper case. You can define other attributes using:
9746 (define_mode_attr @var{name} [(@var{mode1} "@var{value1}") @dots{} (@var{moden} "@var{valuen}")])
9749 where @var{name} is the name of the attribute and @var{valuei}
9750 is the value associated with @var{modei}.
9752 When GCC replaces some @var{:iterator} with @var{:mode}, it will scan
9753 each string and mode in the pattern for sequences of the form
9754 @code{<@var{iterator}:@var{attr}>}, where @var{attr} is the name of a
9755 mode attribute. If the attribute is defined for @var{mode}, the whole
9756 @code{<@dots{}>} sequence will be replaced by the appropriate attribute
9759 For example, suppose an @file{.md} file has:
9762 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
9763 (define_mode_attr load [(SI "lw") (DI "ld")])
9766 If one of the patterns that uses @code{:P} contains the string
9767 @code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern
9768 will use @code{"lw\t%0,%1"} and the @code{DI} version will use
9771 Here is an example of using an attribute for a mode:
9774 (define_mode_iterator LONG [SI DI])
9775 (define_mode_attr SHORT [(SI "HI") (DI "SI")])
9776 (define_insn @dots{}
9777 (sign_extend:LONG (match_operand:<LONG:SHORT> @dots{})) @dots{})
9780 The @code{@var{iterator}:} prefix may be omitted, in which case the
9781 substitution will be attempted for every iterator expansion.
9784 @subsubsection Mode Iterator Examples
9786 Here is an example from the MIPS port. It defines the following
9787 modes and attributes (among others):
9790 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
9791 (define_mode_attr d [(SI "") (DI "d")])
9794 and uses the following template to define both @code{subsi3}
9798 (define_insn "sub<mode>3"
9799 [(set (match_operand:GPR 0 "register_operand" "=d")
9800 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
9801 (match_operand:GPR 2 "register_operand" "d")))]
9804 [(set_attr "type" "arith")
9805 (set_attr "mode" "<MODE>")])
9808 This is exactly equivalent to:
9811 (define_insn "subsi3"
9812 [(set (match_operand:SI 0 "register_operand" "=d")
9813 (minus:SI (match_operand:SI 1 "register_operand" "d")
9814 (match_operand:SI 2 "register_operand" "d")))]
9817 [(set_attr "type" "arith")
9818 (set_attr "mode" "SI")])
9820 (define_insn "subdi3"
9821 [(set (match_operand:DI 0 "register_operand" "=d")
9822 (minus:DI (match_operand:DI 1 "register_operand" "d")
9823 (match_operand:DI 2 "register_operand" "d")))]
9826 [(set_attr "type" "arith")
9827 (set_attr "mode" "DI")])
9830 @node Code Iterators
9831 @subsection Code Iterators
9832 @cindex code iterators in @file{.md} files
9833 @findex define_code_iterator
9834 @findex define_code_attr
9836 Code iterators operate in a similar way to mode iterators. @xref{Mode Iterators}.
9841 (define_code_iterator @var{name} [(@var{code1} "@var{cond1}") @dots{} (@var{coden} "@var{condn}")])
9844 defines a pseudo rtx code @var{name} that can be instantiated as
9845 @var{codei} if condition @var{condi} is true. Each @var{codei}
9846 must have the same rtx format. @xref{RTL Classes}.
9848 As with mode iterators, each pattern that uses @var{name} will be
9849 expanded @var{n} times, once with all uses of @var{name} replaced by
9850 @var{code1}, once with all uses replaced by @var{code2}, and so on.
9851 @xref{Defining Mode Iterators}.
9853 It is possible to define attributes for codes as well as for modes.
9854 There are two standard code attributes: @code{code}, the name of the
9855 code in lower case, and @code{CODE}, the name of the code in upper case.
9856 Other attributes are defined using:
9859 (define_code_attr @var{name} [(@var{code1} "@var{value1}") @dots{} (@var{coden} "@var{valuen}")])
9862 Here's an example of code iterators in action, taken from the MIPS port:
9865 (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
9866 eq ne gt ge lt le gtu geu ltu leu])
9868 (define_expand "b<code>"
9870 (if_then_else (any_cond:CC (cc0)
9872 (label_ref (match_operand 0 ""))
9876 gen_conditional_branch (operands, <CODE>);
9881 This is equivalent to:
9884 (define_expand "bunordered"
9886 (if_then_else (unordered:CC (cc0)
9888 (label_ref (match_operand 0 ""))
9892 gen_conditional_branch (operands, UNORDERED);
9896 (define_expand "bordered"
9898 (if_then_else (ordered:CC (cc0)
9900 (label_ref (match_operand 0 ""))
9904 gen_conditional_branch (operands, ORDERED);
9912 @subsection Int Iterators
9913 @cindex int iterators in @file{.md} files
9914 @findex define_int_iterator
9915 @findex define_int_attr
9917 Int iterators operate in a similar way to code iterators. @xref{Code Iterators}.
9922 (define_int_iterator @var{name} [(@var{int1} "@var{cond1}") @dots{} (@var{intn} "@var{condn}")])
9925 defines a pseudo integer constant @var{name} that can be instantiated as
9926 @var{inti} if condition @var{condi} is true. Each @var{int}
9927 must have the same rtx format. @xref{RTL Classes}. Int iterators can appear
9928 in only those rtx fields that have 'i' as the specifier. This means that
9929 each @var{int} has to be a constant defined using define_constant or
9932 As with mode and code iterators, each pattern that uses @var{name} will be
9933 expanded @var{n} times, once with all uses of @var{name} replaced by
9934 @var{int1}, once with all uses replaced by @var{int2}, and so on.
9935 @xref{Defining Mode Iterators}.
9937 It is possible to define attributes for ints as well as for codes and modes.
9938 Attributes are defined using:
9941 (define_int_attr @var{name} [(@var{int1} "@var{value1}") @dots{} (@var{intn} "@var{valuen}")])
9944 Here's an example of int iterators in action, taken from the ARM port:
9947 (define_int_iterator QABSNEG [UNSPEC_VQABS UNSPEC_VQNEG])
9949 (define_int_attr absneg [(UNSPEC_VQABS "abs") (UNSPEC_VQNEG "neg")])
9951 (define_insn "neon_vq<absneg><mode>"
9952 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
9953 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
9954 (match_operand:SI 2 "immediate_operand" "i")]
9957 "vq<absneg>.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
9958 [(set_attr "type" "neon_vqneg_vqabs")]
9963 This is equivalent to:
9966 (define_insn "neon_vqabs<mode>"
9967 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
9968 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
9969 (match_operand:SI 2 "immediate_operand" "i")]
9972 "vqabs.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
9973 [(set_attr "type" "neon_vqneg_vqabs")]
9976 (define_insn "neon_vqneg<mode>"
9977 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
9978 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
9979 (match_operand:SI 2 "immediate_operand" "i")]
9982 "vqneg.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
9983 [(set_attr "type" "neon_vqneg_vqabs")]
9988 @node Subst Iterators
9989 @subsection Subst Iterators
9990 @cindex subst iterators in @file{.md} files
9991 @findex define_subst
9992 @findex define_subst_attr
9994 Subst iterators are special type of iterators with the following
9995 restrictions: they could not be declared explicitly, they always have
9996 only two values, and they do not have explicit dedicated name.
9997 Subst-iterators are triggered only when corresponding subst-attribute is
9998 used in RTL-pattern.
10000 Subst iterators transform templates in the following way: the templates
10001 are duplicated, the subst-attributes in these templates are replaced
10002 with the corresponding values, and a new attribute is implicitly added
10003 to the given @code{define_insn}/@code{define_expand}. The name of the
10004 added attribute matches the name of @code{define_subst}. Such
10005 attributes are declared implicitly, and it is not allowed to have a
10006 @code{define_attr} named as a @code{define_subst}.
10008 Each subst iterator is linked to a @code{define_subst}. It is declared
10009 implicitly by the first appearance of the corresponding
10010 @code{define_subst_attr}, and it is not allowed to define it explicitly.
10012 Declarations of subst-attributes have the following syntax:
10014 @findex define_subst_attr
10016 (define_subst_attr "@var{name}"
10018 "@var{no-subst-value}"
10019 "@var{subst-applied-value}")
10022 @var{name} is a string with which the given subst-attribute could be
10025 @var{subst-name} shows which @code{define_subst} should be applied to an
10026 RTL-template if the given subst-attribute is present in the
10029 @var{no-subst-value} is a value with which subst-attribute would be
10030 replaced in the first copy of the original RTL-template.
10032 @var{subst-applied-value} is a value with which subst-attribute would be
10033 replaced in the second copy of the original RTL-template.