sys/dev/netif/bge/if_bge.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
  34  */
  35
  36 /*
  37  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  38  *
  39  * Written by Bill Paul <wpaul@windriver.com>
  40  * Senior Engineer, Wind River Systems
  41  */
  42
  43 /*
  44  * The Broadcom BCM5700 is based on technology originally developed by
  45  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  46  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  47  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  48  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  49  * frames, highly configurable RX filtering, and 16 RX and TX queues
  50  * (which, along with RX filter rules, can be used for QOS applications).
  51  * Other features, such as TCP segmentation, may be available as part
  52  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  53  * firmware images can be stored in hardware and need not be compiled
  54  * into the driver.
  55  *
  56  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  57  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  58  *
  59  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  60  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  61  * does not support external SSRAM.
  62  *
  63  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  64  * brand name, which is functionally similar but lacks PCI-X support.
  65  *
  66  * Without external SSRAM, you can only have at most 4 TX rings,
  67  * and the use of the mini RX ring is disabled. This seems to imply
  68  * that these features are simply not available on the BCM5701. As a
  69  * result, this driver does not implement any support for the mini RX
  70  * ring.
  71  */
  72
  73 #include "opt_polling.h"
  74
  75 #include <sys/param.h>
  76 #include <sys/bus.h>
  77 #include <sys/endian.h>
  78 #include <sys/kernel.h>
  79 #include <sys/ktr.h>
  80 #include <sys/interrupt.h>
  81 #include <sys/mbuf.h>
  82 #include <sys/malloc.h>
  83 #include <sys/queue.h>
  84 #include <sys/rman.h>
  85 #include <sys/serialize.h>
  86 #include <sys/socket.h>
  87 #include <sys/sockio.h>
  88 #include <sys/sysctl.h>
  89
  90 #include <net/bpf.h>
  91 #include <net/ethernet.h>
  92 #include <net/if.h>
  93 #include <net/if_arp.h>
  94 #include <net/if_dl.h>
  95 #include <net/if_media.h>
  96 #include <net/if_types.h>
  97 #include <net/ifq_var.h>
  98 #include <net/vlan/if_vlan_var.h>
  99 #include <net/vlan/if_vlan_ether.h>
 100
 101 #include <dev/netif/mii_layer/mii.h>
 102 #include <dev/netif/mii_layer/miivar.h>
 103 #include <dev/netif/mii_layer/brgphyreg.h>
 104
 105 #include <bus/pci/pcidevs.h>
 106 #include <bus/pci/pcireg.h>
 107 #include <bus/pci/pcivar.h>
 108
 109 #include <dev/netif/bge/if_bgereg.h>
 110
 111 /* "device miibus" required.  See GENERIC if you get errors here. */
 112 #include "miibus_if.h"
 113
 114 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP)
 115 #define BGE_MIN_FRAME           60
 116
 117 static const struct bge_type bge_devs[] = {
 118         { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
 119                 "3COM 3C996 Gigabit Ethernet" },
 120
 121         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
 122                 "Alteon BCM5700 Gigabit Ethernet" },
 123         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
 124                 "Alteon BCM5701 Gigabit Ethernet" },
 125
 126         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
 127                 "Altima AC1000 Gigabit Ethernet" },
 128         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
 129                 "Altima AC1002 Gigabit Ethernet" },
 130         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
 131                 "Altima AC9100 Gigabit Ethernet" },
 132
 133         { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
 134                 "Apple BCM5701 Gigabit Ethernet" },
 135
 136         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
 137                 "Broadcom BCM5700 Gigabit Ethernet" },
 138         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
 139                 "Broadcom BCM5701 Gigabit Ethernet" },
 140         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
 141                 "Broadcom BCM5702 Gigabit Ethernet" },
 142         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
 143                 "Broadcom BCM5702X Gigabit Ethernet" },
 144         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
 145                 "Broadcom BCM5702 Gigabit Ethernet" },
 146         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
 147                 "Broadcom BCM5703 Gigabit Ethernet" },
 148         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
 149                 "Broadcom BCM5703X Gigabit Ethernet" },
 150         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
 151                 "Broadcom BCM5703 Gigabit Ethernet" },
 152         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
 153                 "Broadcom BCM5704C Dual Gigabit Ethernet" },
 154         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
 155                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 156         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
 157                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 158         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
 159                 "Broadcom BCM5705 Gigabit Ethernet" },
 160         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
 161                 "Broadcom BCM5705F Gigabit Ethernet" },
 162         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
 163                 "Broadcom BCM5705K Gigabit Ethernet" },
 164         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
 165                 "Broadcom BCM5705M Gigabit Ethernet" },
 166         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
 167                 "Broadcom BCM5705M Gigabit Ethernet" },
 168         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
 169                 "Broadcom BCM5714C Gigabit Ethernet" },
 170         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
 171                 "Broadcom BCM5714S Gigabit Ethernet" },
 172         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
 173                 "Broadcom BCM5715 Gigabit Ethernet" },
 174         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
 175                 "Broadcom BCM5715S Gigabit Ethernet" },
 176         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
 177                 "Broadcom BCM5720 Gigabit Ethernet" },
 178         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
 179                 "Broadcom BCM5721 Gigabit Ethernet" },
 180         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
 181                 "Broadcom BCM5722 Gigabit Ethernet" },
 182         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723,
 183                 "Broadcom BCM5723 Gigabit Ethernet" },
 184         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
 185                 "Broadcom BCM5750 Gigabit Ethernet" },
 186         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
 187                 "Broadcom BCM5750M Gigabit Ethernet" },
 188         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
 189                 "Broadcom BCM5751 Gigabit Ethernet" },
 190         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
 191                 "Broadcom BCM5751F Gigabit Ethernet" },
 192         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
 193                 "Broadcom BCM5751M Gigabit Ethernet" },
 194         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
 195                 "Broadcom BCM5752 Gigabit Ethernet" },
 196         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
 197                 "Broadcom BCM5752M Gigabit Ethernet" },
 198         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
 199                 "Broadcom BCM5753 Gigabit Ethernet" },
 200         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
 201                 "Broadcom BCM5753F Gigabit Ethernet" },
 202         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
 203                 "Broadcom BCM5753M Gigabit Ethernet" },
 204         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
 205                 "Broadcom BCM5754 Gigabit Ethernet" },
 206         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
 207                 "Broadcom BCM5754M Gigabit Ethernet" },
 208         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
 209                 "Broadcom BCM5755 Gigabit Ethernet" },
 210         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
 211                 "Broadcom BCM5755M Gigabit Ethernet" },
 212         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
 213                 "Broadcom BCM5756 Gigabit Ethernet" },
 214         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761,
 215                 "Broadcom BCM5761 Gigabit Ethernet" },
 216         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761E,
 217                 "Broadcom BCM5761E Gigabit Ethernet" },
 218         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761S,
 219                 "Broadcom BCM5761S Gigabit Ethernet" },
 220         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761SE,
 221                 "Broadcom BCM5761SE Gigabit Ethernet" },
 222         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5764,
 223                 "Broadcom BCM5764 Gigabit Ethernet" },
 224         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
 225                 "Broadcom BCM5780 Gigabit Ethernet" },
 226         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
 227                 "Broadcom BCM5780S Gigabit Ethernet" },
 228         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
 229                 "Broadcom BCM5781 Gigabit Ethernet" },
 230         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
 231                 "Broadcom BCM5782 Gigabit Ethernet" },
 232         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5784,
 233                 "Broadcom BCM5784 Gigabit Ethernet" },
 234         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785F,
 235                 "Broadcom BCM5785F Gigabit Ethernet" },
 236         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785G,
 237                 "Broadcom BCM5785G Gigabit Ethernet" },
 238         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
 239                 "Broadcom BCM5786 Gigabit Ethernet" },
 240         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
 241                 "Broadcom BCM5787 Gigabit Ethernet" },
 242         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
 243                 "Broadcom BCM5787F Gigabit Ethernet" },
 244         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
 245                 "Broadcom BCM5787M Gigabit Ethernet" },
 246         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
 247                 "Broadcom BCM5788 Gigabit Ethernet" },
 248         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
 249                 "Broadcom BCM5789 Gigabit Ethernet" },
 250         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
 251                 "Broadcom BCM5901 Fast Ethernet" },
 252         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
 253                 "Broadcom BCM5901A2 Fast Ethernet" },
 254         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
 255                 "Broadcom BCM5903M Fast Ethernet" },
 256         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906,
 257                 "Broadcom BCM5906 Fast Ethernet"},
 258         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M,
 259                 "Broadcom BCM5906M Fast Ethernet"},
 260         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57760,
 261                 "Broadcom BCM57760 Gigabit Ethernet"},
 262         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57780,
 263                 "Broadcom BCM57780 Gigabit Ethernet"},
 264         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57788,
 265                 "Broadcom BCM57788 Gigabit Ethernet"},
 266         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57790,
 267                 "Broadcom BCM57790 Gigabit Ethernet"},
 268         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
 269                 "SysKonnect Gigabit Ethernet" },
 270
 271         { 0, 0, NULL }
 272 };
 273
 274 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 275 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 276 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 277 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 278 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 279 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
 280 #define BGE_IS_5788(sc)                 ((sc)->bge_flags & BGE_FLAG_5788)
 281
 282 #define BGE_IS_CRIPPLED(sc)             \
 283         (BGE_IS_5788((sc)) || (sc)->bge_asicrev == BGE_ASICREV_BCM5700)
 284
 285 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
 286
 287 static int      bge_probe(device_t);
 288 static int      bge_attach(device_t);
 289 static int      bge_detach(device_t);
 290 static void     bge_txeof(struct bge_softc *, uint16_t);
 291 static void     bge_rxeof(struct bge_softc *, uint16_t);
 292
 293 static void     bge_tick(void *);
 294 static void     bge_stats_update(struct bge_softc *);
 295 static void     bge_stats_update_regs(struct bge_softc *);
 296 static struct mbuf *
 297                 bge_defrag_shortdma(struct mbuf *);
 298 static int      bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
 299
 300 #ifdef DEVICE_POLLING
 301 static void     bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 302 #endif
 303 static void     bge_intr(void *);
 304 static void     bge_intr_status_tag(void *);
 305 static void     bge_enable_intr(struct bge_softc *);
 306 static void     bge_disable_intr(struct bge_softc *);
 307 static void     bge_start(struct ifnet *);
 308 static int      bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 309 static void     bge_init(void *);
 310 static void     bge_stop(struct bge_softc *);
 311 static void     bge_watchdog(struct ifnet *);
 312 static void     bge_shutdown(device_t);
 313 static int      bge_suspend(device_t);
 314 static int      bge_resume(device_t);
 315 static int      bge_ifmedia_upd(struct ifnet *);
 316 static void     bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 317
 318 static uint8_t  bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
 319 static int      bge_read_nvram(struct bge_softc *, caddr_t, int, int);
 320
 321 static uint8_t  bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
 322 static int      bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
 323
 324 static void     bge_setmulti(struct bge_softc *);
 325 static void     bge_setpromisc(struct bge_softc *);
 326
 327 static int      bge_alloc_jumbo_mem(struct bge_softc *);
 328 static void     bge_free_jumbo_mem(struct bge_softc *);
 329 static struct bge_jslot
 330                 *bge_jalloc(struct bge_softc *);
 331 static void     bge_jfree(void *);
 332 static void     bge_jref(void *);
 333 static int      bge_newbuf_std(struct bge_softc *, int, int);
 334 static int      bge_newbuf_jumbo(struct bge_softc *, int, int);
 335 static void     bge_setup_rxdesc_std(struct bge_softc *, int);
 336 static void     bge_setup_rxdesc_jumbo(struct bge_softc *, int);
 337 static int      bge_init_rx_ring_std(struct bge_softc *);
 338 static void     bge_free_rx_ring_std(struct bge_softc *);
 339 static int      bge_init_rx_ring_jumbo(struct bge_softc *);
 340 static void     bge_free_rx_ring_jumbo(struct bge_softc *);
 341 static void     bge_free_tx_ring(struct bge_softc *);
 342 static int      bge_init_tx_ring(struct bge_softc *);
 343
 344 static int      bge_chipinit(struct bge_softc *);
 345 static int      bge_blockinit(struct bge_softc *);
 346 static void     bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
 347
 348 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
 349 static void     bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
 350 #ifdef notdef
 351 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
 352 #endif
 353 static void     bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
 354 static void     bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
 355 static void     bge_writembx(struct bge_softc *, int, int);
 356
 357 static int      bge_miibus_readreg(device_t, int, int);
 358 static int      bge_miibus_writereg(device_t, int, int, int);
 359 static void     bge_miibus_statchg(device_t);
 360 static void     bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
 361 static void     bge_tbi_link_upd(struct bge_softc *, uint32_t);
 362 static void     bge_copper_link_upd(struct bge_softc *, uint32_t);
 363 static void     bge_autopoll_link_upd(struct bge_softc *, uint32_t);
 364 static void     bge_link_poll(struct bge_softc *);
 365
 366 static void     bge_reset(struct bge_softc *);
 367
 368 static int      bge_dma_alloc(struct bge_softc *);
 369 static void     bge_dma_free(struct bge_softc *);
 370 static int      bge_dma_block_alloc(struct bge_softc *, bus_size_t,
 371                                     bus_dma_tag_t *, bus_dmamap_t *,
 372                                     void **, bus_addr_t *);
 373 static void     bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
 374
 375 static int      bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
 376 static int      bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
 377 static int      bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
 378 static int      bge_get_eaddr(struct bge_softc *, uint8_t[]);
 379
 380 static void     bge_coal_change(struct bge_softc *);
 381 static int      bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
 382 static int      bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
 383 static int      bge_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS);
 384 static int      bge_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS);
 385 static int      bge_sysctl_rx_coal_ticks_int(SYSCTL_HANDLER_ARGS);
 386 static int      bge_sysctl_tx_coal_ticks_int(SYSCTL_HANDLER_ARGS);
 387 static int      bge_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS);
 388 static int      bge_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS);
 389 static int      bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *,
 390                     int, int, uint32_t);
 391
 392 /*
 393  * Set following tunable to 1 for some IBM blade servers with the DNLK
 394  * switch module. Auto negotiation is broken for those configurations.
 395  */
 396 static int      bge_fake_autoneg = 0;
 397 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
 398
 399 #if !defined(KTR_IF_BGE)
 400 #define KTR_IF_BGE      KTR_ALL
 401 #endif
 402 KTR_INFO_MASTER(if_bge);
 403 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr");
 404 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt");
 405 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt");
 406 #define logif(name)     KTR_LOG(if_bge_ ## name)
 407
 408 static device_method_t bge_methods[] = {
 409         /* Device interface */
 410         DEVMETHOD(device_probe,         bge_probe),
 411         DEVMETHOD(device_attach,        bge_attach),
 412         DEVMETHOD(device_detach,        bge_detach),
 413         DEVMETHOD(device_shutdown,      bge_shutdown),
 414         DEVMETHOD(device_suspend,       bge_suspend),
 415         DEVMETHOD(device_resume,        bge_resume),
 416
 417         /* bus interface */
 418         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 419         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 420
 421         /* MII interface */
 422         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 423         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 424         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 425
 426         { 0, 0 }
 427 };
 428
 429 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
 430 static devclass_t bge_devclass;
 431
 432 DECLARE_DUMMY_MODULE(if_bge);
 433 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, NULL, NULL);
 434 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, NULL, NULL);
 435
 436 static uint32_t
 437 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
 438 {
 439         device_t dev = sc->bge_dev;
 440         uint32_t val;
 441
 442         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 443             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 444                 return 0;
 445
 446         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 447         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 448         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 449         return (val);
 450 }
 451
 452 static void
 453 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 454 {
 455         device_t dev = sc->bge_dev;
 456
 457         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 458             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 459                 return;
 460
 461         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 462         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 463         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 464 }
 465
 466 #ifdef notdef
 467 static uint32_t
 468 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
 469 {
 470         device_t dev = sc->bge_dev;
 471
 472         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 473         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 474 }
 475 #endif
 476
 477 static void
 478 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 479 {
 480         device_t dev = sc->bge_dev;
 481
 482         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 483         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 484 }
 485
 486 static void
 487 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
 488 {
 489         CSR_WRITE_4(sc, off, val);
 490 }
 491
 492 static void
 493 bge_writembx(struct bge_softc *sc, int off, int val)
 494 {
 495         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 496                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 497
 498         CSR_WRITE_4(sc, off, val);
 499         if (sc->bge_mbox_reorder)
 500                 CSR_READ_4(sc, off);
 501 }
 502
 503 static uint8_t
 504 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 505 {
 506         uint32_t access, byte = 0;
 507         int i;
 508
 509         /* Lock. */
 510         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 511         for (i = 0; i < 8000; i++) {
 512                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
 513                         break;
 514                 DELAY(20);
 515         }
 516         if (i == 8000)
 517                 return (1);
 518
 519         /* Enable access. */
 520         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
 521         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
 522
 523         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
 524         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
 525         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 526                 DELAY(10);
 527                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
 528                         DELAY(10);
 529                         break;
 530                 }
 531         }
 532
 533         if (i == BGE_TIMEOUT * 10) {
 534                 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
 535                 return (1);
 536         }
 537
 538         /* Get result. */
 539         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
 540
 541         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
 542
 543         /* Disable access. */
 544         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
 545
 546         /* Unlock. */
 547         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
 548         CSR_READ_4(sc, BGE_NVRAM_SWARB);
 549
 550         return (0);
 551 }
 552
 553 /*
 554  * Read a sequence of bytes from NVRAM.
 555  */
 556 static int
 557 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 558 {
 559         int err = 0, i;
 560         uint8_t byte = 0;
 561
 562         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 563                 return (1);
 564
 565         for (i = 0; i < cnt; i++) {
 566                 err = bge_nvram_getbyte(sc, off + i, &byte);
 567                 if (err)
 568                         break;
 569                 *(dest + i) = byte;
 570         }
 571
 572         return (err ? 1 : 0);
 573 }
 574
 575 /*
 576  * Read a byte of data stored in the EEPROM at address 'addr.' The
 577  * BCM570x supports both the traditional bitbang interface and an
 578  * auto access interface for reading the EEPROM. We use the auto
 579  * access method.
 580  */
 581 static uint8_t
 582 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
 583 {
 584         int i;
 585         uint32_t byte = 0;
 586
 587         /*
 588          * Enable use of auto EEPROM access so we can avoid
 589          * having to use the bitbang method.
 590          */
 591         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 592
 593         /* Reset the EEPROM, load the clock period. */
 594         CSR_WRITE_4(sc, BGE_EE_ADDR,
 595             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 596         DELAY(20);
 597
 598         /* Issue the read EEPROM command. */
 599         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 600
 601         /* Wait for completion */
 602         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 603                 DELAY(10);
 604                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 605                         break;
 606         }
 607
 608         if (i == BGE_TIMEOUT) {
 609                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 610                 return(1);
 611         }
 612
 613         /* Get result. */
 614         byte = CSR_READ_4(sc, BGE_EE_DATA);
 615
 616         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 617
 618         return(0);
 619 }
 620
 621 /*
 622  * Read a sequence of bytes from the EEPROM.
 623  */
 624 static int
 625 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
 626 {
 627         size_t i;
 628         int err;
 629         uint8_t byte;
 630
 631         for (byte = 0, err = 0, i = 0; i < len; i++) {
 632                 err = bge_eeprom_getbyte(sc, off + i, &byte);
 633                 if (err)
 634                         break;
 635                 *(dest + i) = byte;
 636         }
 637
 638         return(err ? 1 : 0);
 639 }
 640
 641 static int
 642 bge_miibus_readreg(device_t dev, int phy, int reg)
 643 {
 644         struct bge_softc *sc = device_get_softc(dev);
 645         uint32_t val;
 646         int i;
 647
 648         KASSERT(phy == sc->bge_phyno,
 649             ("invalid phyno %d, should be %d", phy, sc->bge_phyno));
 650
 651         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 652         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
 653                 CSR_WRITE_4(sc, BGE_MI_MODE,
 654                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 655                 DELAY(80);
 656         }
 657
 658         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
 659             BGE_MIPHY(phy) | BGE_MIREG(reg));
 660
 661         /* Poll for the PHY register access to complete. */
 662         for (i = 0; i < BGE_TIMEOUT; i++) {
 663                 DELAY(10);
 664                 val = CSR_READ_4(sc, BGE_MI_COMM);
 665                 if ((val & BGE_MICOMM_BUSY) == 0) {
 666                         DELAY(5);
 667                         val = CSR_READ_4(sc, BGE_MI_COMM);
 668                         break;
 669                 }
 670         }
 671         if (i == BGE_TIMEOUT) {
 672                 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
 673                     "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
 674                 val = 0;
 675         }
 676
 677         /* Restore the autopoll bit if necessary. */
 678         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
 679                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
 680                 DELAY(80);
 681         }
 682
 683         if (val & BGE_MICOMM_READFAIL)
 684                 return 0;
 685
 686         return (val & 0xFFFF);
 687 }
 688
 689 static int
 690 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 691 {
 692         struct bge_softc *sc = device_get_softc(dev);
 693         int i;
 694
 695         KASSERT(phy == sc->bge_phyno,
 696             ("invalid phyno %d, should be %d", phy, sc->bge_phyno));
 697
 698         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 699             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
 700                return 0;
 701
 702         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 703         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
 704                 CSR_WRITE_4(sc, BGE_MI_MODE,
 705                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 706                 DELAY(80);
 707         }
 708
 709         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
 710             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
 711
 712         for (i = 0; i < BGE_TIMEOUT; i++) {
 713                 DELAY(10);
 714                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 715                         DELAY(5);
 716                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 717                         break;
 718                 }
 719         }
 720         if (i == BGE_TIMEOUT) {
 721                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
 722                     "(phy %d, reg %d, val %d)\n", phy, reg, val);
 723         }
 724
 725         /* Restore the autopoll bit if necessary. */
 726         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
 727                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
 728                 DELAY(80);
 729         }
 730
 731         return 0;
 732 }
 733
 734 static void
 735 bge_miibus_statchg(device_t dev)
 736 {
 737         struct bge_softc *sc;
 738         struct mii_data *mii;
 739
 740         sc = device_get_softc(dev);
 741         mii = device_get_softc(sc->bge_miibus);
 742
 743         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
 744             (IFM_ACTIVE | IFM_AVALID)) {
 745                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 746                 case IFM_10_T:
 747                 case IFM_100_TX:
 748                         sc->bge_link = 1;
 749                         break;
 750                 case IFM_1000_T:
 751                 case IFM_1000_SX:
 752                 case IFM_2500_SX:
 753                         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 754                                 sc->bge_link = 1;
 755                         else
 756                                 sc->bge_link = 0;
 757                         break;
 758                 default:
 759                         sc->bge_link = 0;
 760                         break;
 761                 }
 762         } else {
 763                 sc->bge_link = 0;
 764         }
 765         if (sc->bge_link == 0)
 766                 return;
 767
 768         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 769         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
 770             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
 771                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 772         } else {
 773                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 774         }
 775
 776         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 777                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 778         } else {
 779                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 780         }
 781 }
 782
 783 /*
 784  * Memory management for jumbo frames.
 785  */
 786 static int
 787 bge_alloc_jumbo_mem(struct bge_softc *sc)
 788 {
 789         struct ifnet *ifp = &sc->arpcom.ac_if;
 790         struct bge_jslot *entry;
 791         uint8_t *ptr;
 792         bus_addr_t paddr;
 793         int i, error;
 794
 795         /*
 796          * Create tag for jumbo mbufs.
 797          * This is really a bit of a kludge. We allocate a special
 798          * jumbo buffer pool which (thanks to the way our DMA
 799          * memory allocation works) will consist of contiguous
 800          * pages. This means that even though a jumbo buffer might
 801          * be larger than a page size, we don't really need to
 802          * map it into more than one DMA segment. However, the
 803          * default mbuf tag will result in multi-segment mappings,
 804          * so we have to create a special jumbo mbuf tag that
 805          * lets us get away with mapping the jumbo buffers as
 806          * a single segment. I think eventually the driver should
 807          * be changed so that it uses ordinary mbufs and cluster
 808          * buffers, i.e. jumbo frames can span multiple DMA
 809          * descriptors. But that's a project for another day.
 810          */
 811
 812         /*
 813          * Create DMA stuffs for jumbo RX ring.
 814          */
 815         error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
 816                                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
 817                                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
 818                                     (void *)&sc->bge_ldata.bge_rx_jumbo_ring,
 819                                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
 820         if (error) {
 821                 if_printf(ifp, "could not create jumbo RX ring\n");
 822                 return error;
 823         }
 824
 825         /*
 826          * Create DMA stuffs for jumbo buffer block.
 827          */
 828         error = bge_dma_block_alloc(sc, BGE_JMEM,
 829                                     &sc->bge_cdata.bge_jumbo_tag,
 830                                     &sc->bge_cdata.bge_jumbo_map,
 831                                     (void **)&sc->bge_ldata.bge_jumbo_buf,
 832                                     &paddr);
 833         if (error) {
 834                 if_printf(ifp, "could not create jumbo buffer\n");
 835                 return error;
 836         }
 837
 838         SLIST_INIT(&sc->bge_jfree_listhead);
 839
 840         /*
 841          * Now divide it up into 9K pieces and save the addresses
 842          * in an array. Note that we play an evil trick here by using
 843          * the first few bytes in the buffer to hold the the address
 844          * of the softc structure for this interface. This is because
 845          * bge_jfree() needs it, but it is called by the mbuf management
 846          * code which will not pass it to us explicitly.
 847          */
 848         for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
 849                 entry = &sc->bge_cdata.bge_jslots[i];
 850                 entry->bge_sc = sc;
 851                 entry->bge_buf = ptr;
 852                 entry->bge_paddr = paddr;
 853                 entry->bge_inuse = 0;
 854                 entry->bge_slot = i;
 855                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
 856
 857                 ptr += BGE_JLEN;
 858                 paddr += BGE_JLEN;
 859         }
 860         return 0;
 861 }
 862
 863 static void
 864 bge_free_jumbo_mem(struct bge_softc *sc)
 865 {
 866         /* Destroy jumbo RX ring. */
 867         bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
 868                            sc->bge_cdata.bge_rx_jumbo_ring_map,
 869                            sc->bge_ldata.bge_rx_jumbo_ring);
 870
 871         /* Destroy jumbo buffer block. */
 872         bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
 873                            sc->bge_cdata.bge_jumbo_map,
 874                            sc->bge_ldata.bge_jumbo_buf);
 875 }
 876
 877 /*
 878  * Allocate a jumbo buffer.
 879  */
 880 static struct bge_jslot *
 881 bge_jalloc(struct bge_softc *sc)
 882 {
 883         struct bge_jslot *entry;
 884
 885         lwkt_serialize_enter(&sc->bge_jslot_serializer);
 886         entry = SLIST_FIRST(&sc->bge_jfree_listhead);
 887         if (entry) {
 888                 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
 889                 entry->bge_inuse = 1;
 890         } else {
 891                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 892         }
 893         lwkt_serialize_exit(&sc->bge_jslot_serializer);
 894         return(entry);
 895 }
 896
 897 /*
 898  * Adjust usage count on a jumbo buffer.
 899  */
 900 static void
 901 bge_jref(void *arg)
 902 {
 903         struct bge_jslot *entry = (struct bge_jslot *)arg;
 904         struct bge_softc *sc = entry->bge_sc;
 905
 906         if (sc == NULL)
 907                 panic("bge_jref: can't find softc pointer!");
 908
 909         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 910                 panic("bge_jref: asked to reference buffer "
 911                     "that we don't manage!");
 912         } else if (entry->bge_inuse == 0) {
 913                 panic("bge_jref: buffer already free!");
 914         } else {
 915                 atomic_add_int(&entry->bge_inuse, 1);
 916         }
 917 }
 918
 919 /*
 920  * Release a jumbo buffer.
 921  */
 922 static void
 923 bge_jfree(void *arg)
 924 {
 925         struct bge_jslot *entry = (struct bge_jslot *)arg;
 926         struct bge_softc *sc = entry->bge_sc;
 927
 928         if (sc == NULL)
 929                 panic("bge_jfree: can't find softc pointer!");
 930
 931         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 932                 panic("bge_jfree: asked to free buffer that we don't manage!");
 933         } else if (entry->bge_inuse == 0) {
 934                 panic("bge_jfree: buffer already free!");
 935         } else {
 936                 /*
 937                  * Possible MP race to 0, use the serializer.  The atomic insn
 938                  * is still needed for races against bge_jref().
 939                  */
 940                 lwkt_serialize_enter(&sc->bge_jslot_serializer);
 941                 atomic_subtract_int(&entry->bge_inuse, 1);
 942                 if (entry->bge_inuse == 0) {
 943                         SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
 944                                           entry, jslot_link);
 945                 }
 946                 lwkt_serialize_exit(&sc->bge_jslot_serializer);
 947         }
 948 }
 949
 950
 951 /*
 952  * Intialize a standard receive ring descriptor.
 953  */
 954 static int
 955 bge_newbuf_std(struct bge_softc *sc, int i, int init)
 956 {
 957         struct mbuf *m_new = NULL;
 958         bus_dma_segment_t seg;
 959         bus_dmamap_t map;
 960         int error, nsegs;
 961
 962         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
 963         if (m_new == NULL)
 964                 return ENOBUFS;
 965         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 966
 967         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 968                 m_adj(m_new, ETHER_ALIGN);
 969
 970         error = bus_dmamap_load_mbuf_segment(sc->bge_cdata.bge_rx_mtag,
 971                         sc->bge_cdata.bge_rx_tmpmap, m_new,
 972                         &seg, 1, &nsegs, BUS_DMA_NOWAIT);
 973         if (error) {
 974                 m_freem(m_new);
 975                 return error;
 976         }
 977
 978         if (!init) {
 979                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 980                                 sc->bge_cdata.bge_rx_std_dmamap[i],
 981                                 BUS_DMASYNC_POSTREAD);
 982                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
 983                         sc->bge_cdata.bge_rx_std_dmamap[i]);
 984         }
 985
 986         map = sc->bge_cdata.bge_rx_tmpmap;
 987         sc->bge_cdata.bge_rx_tmpmap = sc->bge_cdata.bge_rx_std_dmamap[i];
 988         sc->bge_cdata.bge_rx_std_dmamap[i] = map;
 989
 990         sc->bge_cdata.bge_rx_std_chain[i].bge_mbuf = m_new;
 991         sc->bge_cdata.bge_rx_std_chain[i].bge_paddr = seg.ds_addr;
 992
 993         bge_setup_rxdesc_std(sc, i);
 994         return 0;
 995 }
 996
 997 static void
 998 bge_setup_rxdesc_std(struct bge_softc *sc, int i)
 999 {
1000         struct bge_rxchain *rc;
1001         struct bge_rx_bd *r;
1002
1003         rc = &sc->bge_cdata.bge_rx_std_chain[i];
1004         r = &sc->bge_ldata.bge_rx_std_ring[i];
1005
1006         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1007         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1008         r->bge_len = rc->bge_mbuf->m_len;
1009         r->bge_idx = i;
1010         r->bge_flags = BGE_RXBDFLAG_END;
1011 }
1012
1013 /*
1014  * Initialize a jumbo receive ring descriptor. This allocates
1015  * a jumbo buffer from the pool managed internally by the driver.
1016  */
1017 static int
1018 bge_newbuf_jumbo(struct bge_softc *sc, int i, int init)
1019 {
1020         struct mbuf *m_new = NULL;
1021         struct bge_jslot *buf;
1022         bus_addr_t paddr;
1023
1024         /* Allocate the mbuf. */
1025         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
1026         if (m_new == NULL)
1027                 return ENOBUFS;
1028
1029         /* Allocate the jumbo buffer */
1030         buf = bge_jalloc(sc);
1031         if (buf == NULL) {
1032                 m_freem(m_new);
1033                 return ENOBUFS;
1034         }
1035
1036         /* Attach the buffer to the mbuf. */
1037         m_new->m_ext.ext_arg = buf;
1038         m_new->m_ext.ext_buf = buf->bge_buf;
1039         m_new->m_ext.ext_free = bge_jfree;
1040         m_new->m_ext.ext_ref = bge_jref;
1041         m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
1042
1043         m_new->m_flags |= M_EXT;
1044
1045         m_new->m_data = m_new->m_ext.ext_buf;
1046         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
1047
1048         paddr = buf->bge_paddr;
1049         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
1050                 m_adj(m_new, ETHER_ALIGN);
1051                 paddr += ETHER_ALIGN;
1052         }
1053
1054         /* Save necessary information */
1055         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_mbuf = m_new;
1056         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_paddr = paddr;
1057
1058         /* Set up the descriptor. */
1059         bge_setup_rxdesc_jumbo(sc, i);
1060         return 0;
1061 }
1062
1063 static void
1064 bge_setup_rxdesc_jumbo(struct bge_softc *sc, int i)
1065 {
1066         struct bge_rx_bd *r;
1067         struct bge_rxchain *rc;
1068
1069         r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
1070         rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1071
1072         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1073         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1074         r->bge_len = rc->bge_mbuf->m_len;
1075         r->bge_idx = i;
1076         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
1077 }
1078
1079 static int
1080 bge_init_rx_ring_std(struct bge_softc *sc)
1081 {
1082         int i, error;
1083
1084         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1085                 error = bge_newbuf_std(sc, i, 1);
1086                 if (error)
1087                         return error;
1088         };
1089
1090         sc->bge_std = BGE_STD_RX_RING_CNT - 1;
1091         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1092
1093         return(0);
1094 }
1095
1096 static void
1097 bge_free_rx_ring_std(struct bge_softc *sc)
1098 {
1099         int i;
1100
1101         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1102                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_std_chain[i];
1103
1104                 if (rc->bge_mbuf != NULL) {
1105                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1106                                           sc->bge_cdata.bge_rx_std_dmamap[i]);
1107                         m_freem(rc->bge_mbuf);
1108                         rc->bge_mbuf = NULL;
1109                 }
1110                 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
1111                     sizeof(struct bge_rx_bd));
1112         }
1113 }
1114
1115 static int
1116 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1117 {
1118         struct bge_rcb *rcb;
1119         int i, error;
1120
1121         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1122                 error = bge_newbuf_jumbo(sc, i, 1);
1123                 if (error)
1124                         return error;
1125         };
1126
1127         sc->bge_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
1128
1129         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1130         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
1131         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1132
1133         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1134
1135         return(0);
1136 }
1137
1138 static void
1139 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1140 {
1141         int i;
1142
1143         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1144                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1145
1146                 if (rc->bge_mbuf != NULL) {
1147                         m_freem(rc->bge_mbuf);
1148                         rc->bge_mbuf = NULL;
1149                 }
1150                 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
1151                     sizeof(struct bge_rx_bd));
1152         }
1153 }
1154
1155 static void
1156 bge_free_tx_ring(struct bge_softc *sc)
1157 {
1158         int i;
1159
1160         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1161                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1162                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1163                                           sc->bge_cdata.bge_tx_dmamap[i]);
1164                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1165                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1166                 }
1167                 bzero(&sc->bge_ldata.bge_tx_ring[i],
1168                     sizeof(struct bge_tx_bd));
1169         }
1170 }
1171
1172 static int
1173 bge_init_tx_ring(struct bge_softc *sc)
1174 {
1175         sc->bge_txcnt = 0;
1176         sc->bge_tx_saved_considx = 0;
1177         sc->bge_tx_prodidx = 0;
1178
1179         /* Initialize transmit producer index for host-memory send ring. */
1180         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1181
1182         /* 5700 b2 errata */
1183         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1184                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1185
1186         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1187         /* 5700 b2 errata */
1188         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1189                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1190
1191         return(0);
1192 }
1193
1194 static void
1195 bge_setmulti(struct bge_softc *sc)
1196 {
1197         struct ifnet *ifp;
1198         struct ifmultiaddr *ifma;
1199         uint32_t hashes[4] = { 0, 0, 0, 0 };
1200         int h, i;
1201
1202         ifp = &sc->arpcom.ac_if;
1203
1204         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1205                 for (i = 0; i < 4; i++)
1206                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1207                 return;
1208         }
1209
1210         /* First, zot all the existing filters. */
1211         for (i = 0; i < 4; i++)
1212                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1213
1214         /* Now program new ones. */
1215         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1216                 if (ifma->ifma_addr->sa_family != AF_LINK)
1217                         continue;
1218                 h = ether_crc32_le(
1219                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1220                     ETHER_ADDR_LEN) & 0x7f;
1221                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1222         }
1223
1224         for (i = 0; i < 4; i++)
1225                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1226 }
1227
1228 /*
1229  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1230  * self-test results.
1231  */
1232 static int
1233 bge_chipinit(struct bge_softc *sc)
1234 {
1235         int i;
1236         uint32_t dma_rw_ctl;
1237         uint16_t val;
1238
1239         /* Set endian type before we access any non-PCI registers. */
1240         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
1241             BGE_INIT | sc->bge_pci_miscctl, 4);
1242
1243         /* Clear the MAC control register */
1244         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1245
1246         /*
1247          * Clear the MAC statistics block in the NIC's
1248          * internal memory.
1249          */
1250         for (i = BGE_STATS_BLOCK;
1251             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1252                 BGE_MEMWIN_WRITE(sc, i, 0);
1253
1254         for (i = BGE_STATUS_BLOCK;
1255             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1256                 BGE_MEMWIN_WRITE(sc, i, 0);
1257
1258         if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1259                 /*
1260                  * Fix data corruption caused by non-qword write with WB.
1261                  * Fix master abort in PCI mode.
1262                  * Fix PCI latency timer.
1263                  */
1264                 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1265                 val |= (1 << 10) | (1 << 12) | (1 << 13);
1266                 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1267         }
1268
1269         /* Set up the PCI DMA control register. */
1270         if (sc->bge_flags & BGE_FLAG_PCIE) {
1271                 /* PCI Express */
1272                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1273                     (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1274                     (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1275         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1276                 /* PCI-X bus */
1277                 if (BGE_IS_5714_FAMILY(sc)) {
1278                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1279                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1280                         /* XXX magic values, Broadcom-supplied Linux driver */
1281                         if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1282                                 dma_rw_ctl |= (1 << 20) | (1 << 18) |
1283                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1284                         } else {
1285                                 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1286                         }
1287                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1288                         /*
1289                          * In the BCM5703, the DMA read watermark should
1290                          * be set to less than or equal to the maximum
1291                          * memory read byte count of the PCI-X command
1292                          * register.
1293                          */
1294                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1295                             (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1296                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1297                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1298                         /*
1299                          * The 5704 uses a different encoding of read/write
1300                          * watermarks.
1301                          */
1302                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1303                             (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1304                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1305                 } else {
1306                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1307                             (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1308                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1309                             (0x0F);
1310                 }
1311
1312                 /*
1313                  * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1314                  * for hardware bugs.
1315                  */
1316                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1317                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1318                         uint32_t tmp;
1319
1320                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1321                         if (tmp == 0x6 || tmp == 0x7)
1322                                 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1323                 }
1324         } else {
1325                 /* Conventional PCI bus */
1326                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1327                     (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1328                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1329                     (0x0F);
1330         }
1331
1332         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1333             sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1334             sc->bge_asicrev == BGE_ASICREV_BCM5705)
1335                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1336         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1337
1338         /*
1339          * Set up general mode register.
1340          */
1341         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1342             BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1343             BGE_MODECTL_TX_NO_PHDR_CSUM);
1344
1345         /*
1346          * BCM5701 B5 have a bug causing data corruption when using
1347          * 64-bit DMA reads, which can be terminated early and then
1348          * completed later as 32-bit accesses, in combination with
1349          * certain bridges.
1350          */
1351         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1352             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1353                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1354
1355         /*
1356          * Disable memory write invalidate.  Apparently it is not supported
1357          * properly by these devices.
1358          */
1359         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1360
1361         /* Set the timer prescaler (always 66Mhz) */
1362         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1363
1364         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1365                 DELAY(40);      /* XXX */
1366
1367                 /* Put PHY into ready state */
1368                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1369                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1370                 DELAY(40);
1371         }
1372
1373         return(0);
1374 }
1375
1376 static int
1377 bge_blockinit(struct bge_softc *sc)
1378 {
1379         struct bge_rcb *rcb;
1380         bus_size_t vrcb;
1381         bge_hostaddr taddr;
1382         uint32_t val;
1383         int i, limit;
1384
1385         /*
1386          * Initialize the memory window pointer register so that
1387          * we can access the first 32K of internal NIC RAM. This will
1388          * allow us to set up the TX send ring RCBs and the RX return
1389          * ring RCBs, plus other things which live in NIC memory.
1390          */
1391         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1392
1393         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1394
1395         if (!BGE_IS_5705_PLUS(sc)) {
1396                 /* Configure mbuf memory pool */
1397                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1398                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1399                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1400                 else
1401                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1402
1403                 /* Configure DMA resource pool */
1404                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1405                     BGE_DMA_DESCRIPTORS);
1406                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1407         }
1408
1409         /* Configure mbuf pool watermarks */
1410         if (!BGE_IS_5705_PLUS(sc)) {
1411                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1412                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1413                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1414         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1415                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1416                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1417                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1418         } else {
1419                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1420                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1421                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1422         }
1423
1424         /* Configure DMA resource watermarks */
1425         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1426         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1427
1428         /* Enable buffer manager */
1429         CSR_WRITE_4(sc, BGE_BMAN_MODE,
1430             BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1431
1432         /* Poll for buffer manager start indication */
1433         for (i = 0; i < BGE_TIMEOUT; i++) {
1434                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1435                         break;
1436                 DELAY(10);
1437         }
1438
1439         if (i == BGE_TIMEOUT) {
1440                 if_printf(&sc->arpcom.ac_if,
1441                           "buffer manager failed to start\n");
1442                 return(ENXIO);
1443         }
1444
1445         /* Enable flow-through queues */
1446         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1447         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1448
1449         /* Wait until queue initialization is complete */
1450         for (i = 0; i < BGE_TIMEOUT; i++) {
1451                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1452                         break;
1453                 DELAY(10);
1454         }
1455
1456         if (i == BGE_TIMEOUT) {
1457                 if_printf(&sc->arpcom.ac_if,
1458                           "flow-through queue init failed\n");
1459                 return(ENXIO);
1460         }
1461
1462         /*
1463          * Summary of rings supported by the controller:
1464          *
1465          * Standard Receive Producer Ring
1466          * - This ring is used to feed receive buffers for "standard"
1467          *   sized frames (typically 1536 bytes) to the controller.
1468          *
1469          * Jumbo Receive Producer Ring
1470          * - This ring is used to feed receive buffers for jumbo sized
1471          *   frames (i.e. anything bigger than the "standard" frames)
1472          *   to the controller.
1473          *
1474          * Mini Receive Producer Ring
1475          * - This ring is used to feed receive buffers for "mini"
1476          *   sized frames to the controller.
1477          * - This feature required external memory for the controller
1478          *   but was never used in a production system.  Should always
1479          *   be disabled.
1480          *
1481          * Receive Return Ring
1482          * - After the controller has placed an incoming frame into a
1483          *   receive buffer that buffer is moved into a receive return
1484          *   ring.  The driver is then responsible to passing the
1485          *   buffer up to the stack.  Many versions of the controller
1486          *   support multiple RR rings.
1487          *
1488          * Send Ring
1489          * - This ring is used for outgoing frames.  Many versions of
1490          *   the controller support multiple send rings.
1491          */
1492
1493         /* Initialize the standard receive producer ring control block. */
1494         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1495         rcb->bge_hostaddr.bge_addr_lo =
1496             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1497         rcb->bge_hostaddr.bge_addr_hi =
1498             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1499         if (BGE_IS_5705_PLUS(sc)) {
1500                 /*
1501                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1502                  * Bits 15-2 : Reserved (should be 0)
1503                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1504                  * Bit 0     : Reserved
1505                  */
1506                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1507         } else {
1508                 /*
1509                  * Ring size is always XXX entries
1510                  * Bits 31-16: Maximum RX frame size
1511                  * Bits 15-2 : Reserved (should be 0)
1512                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1513                  * Bit 0     : Reserved
1514                  */
1515                 rcb->bge_maxlen_flags =
1516                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1517         }
1518         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1519         /* Write the standard receive producer ring control block. */
1520         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1521         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1522         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1523         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1524         /* Reset the standard receive producer ring producer index. */
1525         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1526
1527         /*
1528          * Initialize the jumbo RX producer ring control
1529          * block.  We set the 'ring disabled' bit in the
1530          * flags field until we're actually ready to start
1531          * using this ring (i.e. once we set the MTU
1532          * high enough to require it).
1533          */
1534         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1535                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1536                 /* Get the jumbo receive producer ring RCB parameters. */
1537                 rcb->bge_hostaddr.bge_addr_lo =
1538                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1539                 rcb->bge_hostaddr.bge_addr_hi =
1540                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1541                 rcb->bge_maxlen_flags =
1542                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1543                     BGE_RCB_FLAG_RING_DISABLED);
1544                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1545                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1546                     rcb->bge_hostaddr.bge_addr_hi);
1547                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1548                     rcb->bge_hostaddr.bge_addr_lo);
1549                 /* Program the jumbo receive producer ring RCB parameters. */
1550                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1551                     rcb->bge_maxlen_flags);
1552                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1553                 /* Reset the jumbo receive producer ring producer index. */
1554                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1555         }
1556
1557         /* Disable the mini receive producer ring RCB. */
1558         if (BGE_IS_5700_FAMILY(sc)) {
1559                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1560                 rcb->bge_maxlen_flags =
1561                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1562                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1563                     rcb->bge_maxlen_flags);
1564                 /* Reset the mini receive producer ring producer index. */
1565                 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1566         }
1567
1568         /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
1569         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
1570             (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
1571              sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
1572              sc->bge_chipid == BGE_CHIPID_BCM5906_A2)) {
1573                 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
1574                     (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
1575         }
1576
1577         /*
1578          * The BD ring replenish thresholds control how often the
1579          * hardware fetches new BD's from the producer rings in host
1580          * memory.  Setting the value too low on a busy system can
1581          * starve the hardware and recue the throughpout.
1582          *
1583          * Set the BD ring replentish thresholds. The recommended
1584          * values are 1/8th the number of descriptors allocated to
1585          * each ring.
1586          */
1587         if (BGE_IS_5705_PLUS(sc))
1588                 val = 8;
1589         else
1590                 val = BGE_STD_RX_RING_CNT / 8;
1591         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1592         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1593                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1594                     BGE_JUMBO_RX_RING_CNT/8);
1595         }
1596
1597         /*
1598          * Disable all send rings by setting the 'ring disabled' bit
1599          * in the flags field of all the TX send ring control blocks,
1600          * located in NIC memory.
1601          */
1602         if (!BGE_IS_5705_PLUS(sc)) {
1603                 /* 5700 to 5704 had 16 send rings. */
1604                 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
1605         } else {
1606                 limit = 1;
1607         }
1608         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1609         for (i = 0; i < limit; i++) {
1610                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1611                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1612                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1613                 vrcb += sizeof(struct bge_rcb);
1614         }
1615
1616         /* Configure send ring RCB 0 (we use only the first ring) */
1617         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1618         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1619         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1620         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1621         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1622             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1623         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1624             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1625
1626         /*
1627          * Disable all receive return rings by setting the
1628          * 'ring diabled' bit in the flags field of all the receive
1629          * return ring control blocks, located in NIC memory.
1630          */
1631         if (!BGE_IS_5705_PLUS(sc))
1632                 limit = BGE_RX_RINGS_MAX;
1633         else if (sc->bge_asicrev == BGE_ASICREV_BCM5755)
1634                 limit = 4;
1635         else
1636                 limit = 1;
1637         /* Disable all receive return rings. */
1638         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1639         for (i = 0; i < limit; i++) {
1640                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1641                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1642                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1643                     BGE_RCB_FLAG_RING_DISABLED);
1644                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1645                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1646                     (i * (sizeof(uint64_t))), 0);
1647                 vrcb += sizeof(struct bge_rcb);
1648         }
1649
1650         /*
1651          * Set up receive return ring 0.  Note that the NIC address
1652          * for RX return rings is 0x0.  The return rings live entirely
1653          * within the host, so the nicaddr field in the RCB isn't used.
1654          */
1655         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1656         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1657         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1658         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1659         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1660         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1661             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1662
1663         /* Set random backoff seed for TX */
1664         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1665             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1666             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1667             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1668             BGE_TX_BACKOFF_SEED_MASK);
1669
1670         /* Set inter-packet gap */
1671         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1672
1673         /*
1674          * Specify which ring to use for packets that don't match
1675          * any RX rules.
1676          */
1677         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1678
1679         /*
1680          * Configure number of RX lists. One interrupt distribution
1681          * list, sixteen active lists, one bad frames class.
1682          */
1683         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1684
1685         /* Inialize RX list placement stats mask. */
1686         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1687         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1688
1689         /* Disable host coalescing until we get it set up */
1690         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1691
1692         /* Poll to make sure it's shut down. */
1693         for (i = 0; i < BGE_TIMEOUT; i++) {
1694                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1695                         break;
1696                 DELAY(10);
1697         }
1698
1699         if (i == BGE_TIMEOUT) {
1700                 if_printf(&sc->arpcom.ac_if,
1701                           "host coalescing engine failed to idle\n");
1702                 return(ENXIO);
1703         }
1704
1705         /* Set up host coalescing defaults */
1706         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1707         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1708         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_coal_bds);
1709         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_coal_bds);
1710         if (!BGE_IS_5705_PLUS(sc)) {
1711                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT,
1712                     sc->bge_rx_coal_ticks_int);
1713                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT,
1714                     sc->bge_tx_coal_ticks_int);
1715         }
1716         /*
1717          * NOTE:
1718          * The datasheet (57XX-PG105-R) says BCM5705+ do not
1719          * have following two registers; obviously it is wrong.
1720          */
1721         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, sc->bge_rx_coal_bds_int);
1722         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, sc->bge_tx_coal_bds_int);
1723
1724         /* Set up address of statistics block */
1725         if (!BGE_IS_5705_PLUS(sc)) {
1726                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1727                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1728                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1729                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1730
1731                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1732                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1733                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1734         }
1735
1736         /* Set up address of status block */
1737         bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
1738         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1739             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1740         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1741             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1742
1743         /*
1744          * Set up status block partail update size.
1745          *
1746          * Because only single TX ring, RX produce ring and Rx return ring
1747          * are used, ask device to update only minimum part of status block
1748          * except for BCM5700 AX/BX, whose status block partial update size
1749          * can't be configured.
1750          */
1751         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1752             sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
1753                 /* XXX Actually reserved on BCM5700 AX/BX */
1754                 val = BGE_STATBLKSZ_FULL;
1755         } else {
1756                 val = BGE_STATBLKSZ_32BYTE;
1757         }
1758 #if 0
1759         /*
1760          * Does not seem to have visible effect in both
1761          * bulk data (1472B UDP datagram) and tiny data
1762          * (18B UDP datagram) TX tests.
1763          */
1764         if (!BGE_IS_CRIPPLED(sc))
1765                 val |= BGE_HCCMODE_CLRTICK_TX;
1766 #endif
1767
1768         /* Turn on host coalescing state machine */
1769         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1770
1771         /* Turn on RX BD completion state machine and enable attentions */
1772         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1773             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1774
1775         /* Turn on RX list placement state machine */
1776         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1777
1778         /* Turn on RX list selector state machine. */
1779         if (!BGE_IS_5705_PLUS(sc))
1780                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1781
1782         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1783             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1784             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1785             BGE_MACMODE_FRMHDR_DMA_ENB;
1786
1787         if (sc->bge_flags & BGE_FLAG_TBI)
1788                 val |= BGE_PORTMODE_TBI;
1789         else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
1790                 val |= BGE_PORTMODE_GMII;
1791         else
1792                 val |= BGE_PORTMODE_MII;
1793
1794         /* Turn on DMA, clear stats */
1795         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1796
1797         /* Set misc. local control, enable interrupts on attentions */
1798         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1799
1800 #ifdef notdef
1801         /* Assert GPIO pins for PHY reset */
1802         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1803             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1804         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1805             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1806 #endif
1807
1808         /* Turn on DMA completion state machine */
1809         if (!BGE_IS_5705_PLUS(sc))
1810                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1811
1812         /* Turn on write DMA state machine */
1813         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1814         if (BGE_IS_5755_PLUS(sc)) {
1815                 /* Enable host coalescing bug fix. */
1816                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1817         }
1818         if (sc->bge_asicrev == BGE_ASICREV_BCM5785) {
1819                 /* Request larger DMA burst size to get better performance. */
1820                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1821         }
1822         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1823         DELAY(40);
1824
1825         if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
1826             sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1827             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1828             sc->bge_asicrev == BGE_ASICREV_BCM57780) {
1829                 /*
1830                  * Enable fix for read DMA FIFO overruns.
1831                  * The fix is to limit the number of RX BDs
1832                  * the hardware would fetch at a fime.
1833                  */
1834                 val = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
1835                 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL,
1836                     val| BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1837         }
1838
1839         /* Turn on read DMA state machine */
1840         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1841         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1842             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1843             sc->bge_asicrev == BGE_ASICREV_BCM57780)
1844                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1845                   BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1846                   BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1847         if (sc->bge_flags & BGE_FLAG_PCIE)
1848                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1849         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1850         DELAY(40);
1851
1852         /* Turn on RX data completion state machine */
1853         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1854
1855         /* Turn on RX BD initiator state machine */
1856         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1857
1858         /* Turn on RX data and RX BD initiator state machine */
1859         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1860
1861         /* Turn on Mbuf cluster free state machine */
1862         if (!BGE_IS_5705_PLUS(sc))
1863                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1864
1865         /* Turn on send BD completion state machine */
1866         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1867
1868         /* Turn on send data completion state machine */
1869         val = BGE_SDCMODE_ENABLE;
1870         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1871                 val |= BGE_SDCMODE_CDELAY;
1872         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1873
1874         /* Turn on send data initiator state machine */
1875         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1876
1877         /* Turn on send BD initiator state machine */
1878         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1879
1880         /* Turn on send BD selector state machine */
1881         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1882
1883         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1884         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1885             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1886
1887         /* ack/clear link change events */
1888         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1889             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1890             BGE_MACSTAT_LINK_CHANGED);
1891         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1892
1893         /*
1894          * Enable attention when the link has changed state for
1895          * devices that use auto polling.
1896          */
1897         if (sc->bge_flags & BGE_FLAG_TBI) {
1898                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1899         } else {
1900                 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
1901                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1902                         DELAY(80);
1903                 }
1904                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1905                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1906                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1907                             BGE_EVTENB_MI_INTERRUPT);
1908                 }
1909         }
1910
1911         /*
1912          * Clear any pending link state attention.
1913          * Otherwise some link state change events may be lost until attention
1914          * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1915          * It's not necessary on newer BCM chips - perhaps enabling link
1916          * state change attentions implies clearing pending attention.
1917          */
1918         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1919             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1920             BGE_MACSTAT_LINK_CHANGED);
1921
1922         /* Enable link state change attentions. */
1923         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1924
1925         return(0);
1926 }
1927
1928 /*
1929  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1930  * against our list and return its name if we find a match. Note
1931  * that since the Broadcom controller contains VPD support, we
1932  * can get the device name string from the controller itself instead
1933  * of the compiled-in string. This is a little slow, but it guarantees
1934  * we'll always announce the right product name.
1935  */
1936 static int
1937 bge_probe(device_t dev)
1938 {
1939         const struct bge_type *t;
1940         uint16_t product, vendor;
1941
1942         product = pci_get_device(dev);
1943         vendor = pci_get_vendor(dev);
1944
1945         for (t = bge_devs; t->bge_name != NULL; t++) {
1946                 if (vendor == t->bge_vid && product == t->bge_did)
1947                         break;
1948         }
1949         if (t->bge_name == NULL)
1950                 return(ENXIO);
1951
1952         device_set_desc(dev, t->bge_name);
1953         return(0);
1954 }
1955
1956 static int
1957 bge_attach(device_t dev)
1958 {
1959         struct ifnet *ifp;
1960         struct bge_softc *sc;
1961         uint32_t hwcfg = 0, misccfg;
1962         int error = 0, rid, capmask;
1963         uint8_t ether_addr[ETHER_ADDR_LEN];
1964         uint16_t product, vendor;
1965         driver_intr_t *intr_func;
1966         uintptr_t mii_priv = 0;
1967
1968         sc = device_get_softc(dev);
1969         sc->bge_dev = dev;
1970         callout_init(&sc->bge_stat_timer);
1971         lwkt_serialize_init(&sc->bge_jslot_serializer);
1972
1973 #ifndef BURN_BRIDGES
1974         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1975                 uint32_t irq, mem;
1976
1977                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1978                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1979
1980                 device_printf(dev, "chip is in D%d power mode "
1981                     "-- setting to D0\n", pci_get_powerstate(dev));
1982
1983                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1984
1985                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1986                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1987         }
1988 #endif  /* !BURN_BRIDGE */
1989
1990         /*
1991          * Map control/status registers.
1992          */
1993         pci_enable_busmaster(dev);
1994
1995         rid = BGE_PCI_BAR0;
1996         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1997             RF_ACTIVE);
1998
1999         if (sc->bge_res == NULL) {
2000                 device_printf(dev, "couldn't map memory\n");
2001                 return ENXIO;
2002         }
2003
2004         sc->bge_btag = rman_get_bustag(sc->bge_res);
2005         sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
2006
2007         /* Save various chip information */
2008         sc->bge_chipid =
2009             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2010             BGE_PCIMISCCTL_ASICREV_SHIFT;
2011         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG)
2012                 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
2013         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2014         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2015
2016         /* Save chipset family. */
2017         switch (sc->bge_asicrev) {
2018         case BGE_ASICREV_BCM5755:
2019         case BGE_ASICREV_BCM5761:
2020         case BGE_ASICREV_BCM5784:
2021         case BGE_ASICREV_BCM5785:
2022         case BGE_ASICREV_BCM5787:
2023         case BGE_ASICREV_BCM57780:
2024             sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
2025                 BGE_FLAG_5705_PLUS;
2026             break;
2027
2028         case BGE_ASICREV_BCM5700:
2029         case BGE_ASICREV_BCM5701:
2030         case BGE_ASICREV_BCM5703:
2031         case BGE_ASICREV_BCM5704:
2032                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2033                 break;
2034
2035         case BGE_ASICREV_BCM5714_A0:
2036         case BGE_ASICREV_BCM5780:
2037         case BGE_ASICREV_BCM5714:
2038                 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
2039                 /* Fall through */
2040
2041         case BGE_ASICREV_BCM5750:
2042         case BGE_ASICREV_BCM5752:
2043         case BGE_ASICREV_BCM5906:
2044                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2045                 /* Fall through */
2046
2047         case BGE_ASICREV_BCM5705:
2048                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2049                 break;
2050         }
2051
2052         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
2053                 sc->bge_flags |= BGE_FLAG_NO_EEPROM;
2054
2055         misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
2056         if (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2057             (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
2058              misccfg == BGE_MISCCFG_BOARD_ID_5788M))
2059                 sc->bge_flags |= BGE_FLAG_5788;
2060
2061         /* BCM5755 or higher and BCM5906 have short DMA bug. */
2062         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
2063                 sc->bge_flags |= BGE_FLAG_SHORTDMA;
2064
2065         /*
2066          * Check if this is a PCI-X or PCI Express device.
2067          */
2068         if (BGE_IS_5705_PLUS(sc)) {
2069                 if (pci_is_pcie(dev)) {
2070                         sc->bge_flags |= BGE_FLAG_PCIE;
2071                         sc->bge_pciecap = pci_get_pciecap_ptr(sc->bge_dev);
2072                         pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
2073                 }
2074         } else {
2075                 /*
2076                  * Check if the device is in PCI-X Mode.
2077                  * (This bit is not valid on PCI Express controllers.)
2078                  */
2079                 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
2080                     BGE_PCISTATE_PCI_BUSMODE) == 0) {
2081                         sc->bge_flags |= BGE_FLAG_PCIX;
2082                         sc->bge_pcixcap = pci_get_pcixcap_ptr(sc->bge_dev);
2083                         sc->bge_mbox_reorder = device_getenv_int(sc->bge_dev,
2084                             "mbox_reorder", 0);
2085                 }
2086         }
2087         device_printf(dev, "CHIP ID 0x%08x; "
2088                       "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
2089                       sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
2090                       (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X"
2091                       : ((sc->bge_flags & BGE_FLAG_PCIE) ?
2092                         "PCI-E" : "PCI"));
2093
2094         /*
2095          * The 40bit DMA bug applies to the 5714/5715 controllers and is
2096          * not actually a MAC controller bug but an issue with the embedded
2097          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
2098          */
2099         if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
2100                 sc->bge_flags |= BGE_FLAG_MAXADDR_40BIT;
2101
2102         /* Identify the chips that use an CPMU. */
2103         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2104             sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2105             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2106             sc->bge_asicrev == BGE_ASICREV_BCM57780)
2107                 sc->bge_flags |= BGE_FLAG_CPMU;
2108
2109         /*
2110          * When using the BCM5701 in PCI-X mode, data corruption has
2111          * been observed in the first few bytes of some received packets.
2112          * Aligning the packet buffer in memory eliminates the corruption.
2113          * Unfortunately, this misaligns the packet payloads.  On platforms
2114          * which do not support unaligned accesses, we will realign the
2115          * payloads by copying the received packets.
2116          */
2117         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2118             (sc->bge_flags & BGE_FLAG_PCIX))
2119                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2120
2121         if (!BGE_IS_CRIPPLED(sc)) {
2122                 if (device_getenv_int(dev, "status_tag", 1)) {
2123                         sc->bge_flags |= BGE_FLAG_STATUS_TAG;
2124                         sc->bge_pci_miscctl = BGE_PCIMISCCTL_TAGGED_STATUS;
2125                         if (bootverbose)
2126                                 device_printf(dev, "enable status tag\n");
2127                 }
2128         }
2129
2130         /*
2131          * Set various PHY quirk flags.
2132          */
2133         product = pci_get_device(dev);
2134         vendor = pci_get_vendor(dev);
2135
2136         if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2137              sc->bge_asicrev == BGE_ASICREV_BCM5701) &&
2138             pci_get_subvendor(dev) == PCI_VENDOR_DELL)
2139                 mii_priv |= BRGPHY_FLAG_NO_3LED;
2140
2141         capmask = MII_CAPMASK_DEFAULT;
2142         if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
2143              (misccfg == 0x4000 || misccfg == 0x8000)) ||
2144             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2145              vendor == PCI_VENDOR_BROADCOM &&
2146              (product == PCI_PRODUCT_BROADCOM_BCM5901 ||
2147               product == PCI_PRODUCT_BROADCOM_BCM5901A2 ||
2148               product == PCI_PRODUCT_BROADCOM_BCM5705F)) ||
2149             (vendor == PCI_VENDOR_BROADCOM &&
2150              (product == PCI_PRODUCT_BROADCOM_BCM5751F ||
2151               product == PCI_PRODUCT_BROADCOM_BCM5753F ||
2152               product == PCI_PRODUCT_BROADCOM_BCM5787F)) ||
2153             product == PCI_PRODUCT_BROADCOM_BCM57790 ||
2154             sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2155                 /* 10/100 only */
2156                 capmask &= ~BMSR_EXTSTAT;
2157         }
2158
2159         mii_priv |= BRGPHY_FLAG_WIRESPEED;
2160         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2161             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2162              (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2163               sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
2164             sc->bge_asicrev == BGE_ASICREV_BCM5906)
2165                 mii_priv &= ~BRGPHY_FLAG_WIRESPEED;
2166
2167         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2168             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
2169                 mii_priv |= BRGPHY_FLAG_CRC_BUG;
2170
2171         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2172             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2173                 mii_priv |= BRGPHY_FLAG_ADC_BUG;
2174
2175         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2176                 mii_priv |= BRGPHY_FLAG_5704_A0;
2177
2178         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
2179                 mii_priv |= BRGPHY_FLAG_5906;
2180
2181         if (BGE_IS_5705_PLUS(sc) &&
2182             sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2183             /* sc->bge_asicrev != BGE_ASICREV_BCM5717 && */
2184             sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
2185             /* sc->bge_asicrev != BGE_ASICREV_BCM57765 && */
2186             sc->bge_asicrev != BGE_ASICREV_BCM57780) {
2187                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2188                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2189                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2190                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2191                         if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
2192                             product != PCI_PRODUCT_BROADCOM_BCM5756)
2193                                 mii_priv |= BRGPHY_FLAG_JITTER_BUG;
2194                         if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
2195                                 mii_priv |= BRGPHY_FLAG_ADJUST_TRIM;
2196                 } else {
2197                         mii_priv |= BRGPHY_FLAG_BER_BUG;
2198                 }
2199         }
2200
2201         /* Allocate interrupt */
2202         rid = 0;
2203         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2204             RF_SHAREABLE | RF_ACTIVE);
2205         if (sc->bge_irq == NULL) {
2206                 device_printf(dev, "couldn't map interrupt\n");
2207                 error = ENXIO;
2208                 goto fail;
2209         }
2210
2211         /* Initialize if_name earlier, so if_printf could be used */
2212         ifp = &sc->arpcom.ac_if;
2213         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2214
2215         /* Try to reset the chip. */
2216         bge_reset(sc);
2217
2218         if (bge_chipinit(sc)) {
2219                 device_printf(dev, "chip initialization failed\n");
2220                 error = ENXIO;
2221                 goto fail;
2222         }
2223
2224         /*
2225          * Get station address
2226          */
2227         error = bge_get_eaddr(sc, ether_addr);
2228         if (error) {
2229                 device_printf(dev, "failed to read station address\n");
2230                 goto fail;
2231         }
2232
2233         /* 5705/5750 limits RX return ring to 512 entries. */
2234         if (BGE_IS_5705_PLUS(sc))
2235                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2236         else
2237                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2238
2239         error = bge_dma_alloc(sc);
2240         if (error)
2241                 goto fail;
2242
2243         /* Set default tuneable values. */
2244         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2245         sc->bge_rx_coal_ticks = BGE_RX_COAL_TICKS_DEF;
2246         sc->bge_tx_coal_ticks = BGE_TX_COAL_TICKS_DEF;
2247         sc->bge_rx_coal_bds = BGE_RX_COAL_BDS_DEF;
2248         sc->bge_tx_coal_bds = BGE_TX_COAL_BDS_DEF;
2249         if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
2250                 sc->bge_rx_coal_ticks_int = BGE_RX_COAL_TICKS_DEF;
2251                 sc->bge_tx_coal_ticks_int = BGE_TX_COAL_TICKS_DEF;
2252                 sc->bge_rx_coal_bds_int = BGE_RX_COAL_BDS_DEF;
2253                 sc->bge_tx_coal_bds_int = BGE_TX_COAL_BDS_DEF;
2254         } else {
2255                 sc->bge_rx_coal_ticks_int = BGE_RX_COAL_TICKS_MIN;
2256                 sc->bge_tx_coal_ticks_int = BGE_TX_COAL_TICKS_MIN;
2257                 sc->bge_rx_coal_bds_int = BGE_RX_COAL_BDS_MIN;
2258                 sc->bge_tx_coal_bds_int = BGE_TX_COAL_BDS_MIN;
2259         }
2260
2261         /* Set up ifnet structure */
2262         ifp->if_softc = sc;
2263         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2264         ifp->if_ioctl = bge_ioctl;
2265         ifp->if_start = bge_start;
2266 #ifdef DEVICE_POLLING
2267         ifp->if_poll = bge_poll;
2268 #endif
2269         ifp->if_watchdog = bge_watchdog;
2270         ifp->if_init = bge_init;
2271         ifp->if_mtu = ETHERMTU;
2272         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2273         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
2274         ifq_set_ready(&ifp->if_snd);
2275
2276         /*
2277          * 5700 B0 chips do not support checksumming correctly due
2278          * to hardware bugs.
2279          */
2280         if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
2281                 ifp->if_capabilities |= IFCAP_HWCSUM;
2282                 ifp->if_hwassist = BGE_CSUM_FEATURES;
2283         }
2284         ifp->if_capenable = ifp->if_capabilities;
2285
2286         /*
2287          * Figure out what sort of media we have by checking the
2288          * hardware config word in the first 32k of NIC internal memory,
2289          * or fall back to examining the EEPROM if necessary.
2290          * Note: on some BCM5700 cards, this value appears to be unset.
2291          * If that's the case, we have to rely on identifying the NIC
2292          * by its PCI subsystem ID, as we do below for the SysKonnect
2293          * SK-9D41.
2294          */
2295         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) {
2296                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2297         } else {
2298                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2299                                     sizeof(hwcfg))) {
2300                         device_printf(dev, "failed to read EEPROM\n");
2301                         error = ENXIO;
2302                         goto fail;
2303                 }
2304                 hwcfg = ntohl(hwcfg);
2305         }
2306
2307         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2308         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
2309             (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
2310                 if (BGE_IS_5714_FAMILY(sc))
2311                         sc->bge_flags |= BGE_FLAG_MII_SERDES;
2312                 else
2313                         sc->bge_flags |= BGE_FLAG_TBI;
2314         }
2315
2316         /* Setup MI MODE */
2317         if (sc->bge_flags & BGE_FLAG_CPMU)
2318                 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
2319         else
2320                 sc->bge_mi_mode = BGE_MIMODE_BASE;
2321         if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) {
2322                 /* Enable auto polling for BCM570[0-5]. */
2323                 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
2324         }
2325
2326         /* Setup link status update stuffs */
2327         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2328             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
2329                 sc->bge_link_upd = bge_bcm5700_link_upd;
2330                 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
2331         } else if (sc->bge_flags & BGE_FLAG_TBI) {
2332                 sc->bge_link_upd = bge_tbi_link_upd;
2333                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2334         } else if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2335                 sc->bge_link_upd = bge_autopoll_link_upd;
2336                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2337         } else {
2338                 sc->bge_link_upd = bge_copper_link_upd;
2339                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2340         }
2341
2342         /*
2343          * Broadcom's own driver always assumes the internal
2344          * PHY is at GMII address 1.  On some chips, the PHY responds
2345          * to accesses at all addresses, which could cause us to
2346          * bogusly attach the PHY 32 times at probe type.  Always
2347          * restricting the lookup to address 1 is simpler than
2348          * trying to figure out which chips revisions should be
2349          * special-cased.
2350          */
2351         sc->bge_phyno = 1;
2352
2353         if (sc->bge_flags & BGE_FLAG_TBI) {
2354                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
2355                     bge_ifmedia_upd, bge_ifmedia_sts);
2356                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2357                 ifmedia_add(&sc->bge_ifmedia,
2358                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2359                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2360                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
2361                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2362         } else {
2363                 struct mii_probe_args mii_args;
2364
2365                 mii_probe_args_init(&mii_args, bge_ifmedia_upd, bge_ifmedia_sts);
2366                 mii_args.mii_probemask = 1 << sc->bge_phyno;
2367                 mii_args.mii_capmask = capmask;
2368                 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
2369                 mii_args.mii_priv = mii_priv;
2370
2371                 error = mii_probe(dev, &sc->bge_miibus, &mii_args);
2372                 if (error) {
2373                         device_printf(dev, "MII without any PHY!\n");
2374                         goto fail;
2375                 }
2376         }
2377
2378         /*
2379          * Create sysctl nodes.
2380          */
2381         sysctl_ctx_init(&sc->bge_sysctl_ctx);
2382         sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
2383                                               SYSCTL_STATIC_CHILDREN(_hw),
2384                                               OID_AUTO,
2385                                               device_get_nameunit(dev),
2386                                               CTLFLAG_RD, 0, "");
2387         if (sc->bge_sysctl_tree == NULL) {
2388                 device_printf(dev, "can't add sysctl node\n");
2389                 error = ENXIO;
2390                 goto fail;
2391         }
2392
2393         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2394                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2395                         OID_AUTO, "rx_coal_ticks",
2396                         CTLTYPE_INT | CTLFLAG_RW,
2397                         sc, 0, bge_sysctl_rx_coal_ticks, "I",
2398                         "Receive coalescing ticks (usec).");
2399         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2400                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2401                         OID_AUTO, "tx_coal_ticks",
2402                         CTLTYPE_INT | CTLFLAG_RW,
2403                         sc, 0, bge_sysctl_tx_coal_ticks, "I",
2404                         "Transmit coalescing ticks (usec).");
2405         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2406                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2407                         OID_AUTO, "rx_coal_bds",
2408                         CTLTYPE_INT | CTLFLAG_RW,
2409                         sc, 0, bge_sysctl_rx_coal_bds, "I",
2410                         "Receive max coalesced BD count.");
2411         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2412                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2413                         OID_AUTO, "tx_coal_bds",
2414                         CTLTYPE_INT | CTLFLAG_RW,
2415                         sc, 0, bge_sysctl_tx_coal_bds, "I",
2416                         "Transmit max coalesced BD count.");
2417         if (sc->bge_flags & BGE_FLAG_PCIE) {
2418                 /*
2419                  * A common design characteristic for many Broadcom
2420                  * client controllers is that they only support a
2421                  * single outstanding DMA read operation on the PCIe
2422                  * bus. This means that it will take twice as long to
2423                  * fetch a TX frame that is split into header and
2424                  * payload buffers as it does to fetch a single,
2425                  * contiguous TX frame (2 reads vs. 1 read). For these
2426                  * controllers, coalescing buffers to reduce the number
2427                  * of memory reads is effective way to get maximum
2428                  * performance(about 940Mbps).  Without collapsing TX
2429                  * buffers the maximum TCP bulk transfer performance
2430                  * is about 850Mbps. However forcing coalescing mbufs
2431                  * consumes a lot of CPU cycles, so leave it off by
2432                  * default.
2433                  */
2434                 SYSCTL_ADD_INT(&sc->bge_sysctl_ctx,
2435                                SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2436                                OID_AUTO, "force_defrag", CTLFLAG_RW,
2437                                &sc->bge_force_defrag, 0,
2438                                "Force defragment on TX path");
2439         }
2440         if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
2441                 if (!BGE_IS_5705_PLUS(sc)) {
2442                         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2443                             SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2444                             "rx_coal_ticks_int", CTLTYPE_INT | CTLFLAG_RW,
2445                             sc, 0, bge_sysctl_rx_coal_ticks_int, "I",
2446                             "Receive coalescing ticks "
2447                             "during interrupt (usec).");
2448                         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2449                             SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2450                             "tx_coal_ticks_int", CTLTYPE_INT | CTLFLAG_RW,
2451                             sc, 0, bge_sysctl_tx_coal_ticks_int, "I",
2452                             "Transmit coalescing ticks "
2453                             "during interrupt (usec).");
2454                 }
2455                 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2456                     SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2457                     "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2458                     sc, 0, bge_sysctl_rx_coal_bds_int, "I",
2459                     "Receive max coalesced BD count during interrupt.");
2460                 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2461                     SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2462                     "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2463                     sc, 0, bge_sysctl_tx_coal_bds_int, "I",
2464                     "Transmit max coalesced BD count during interrupt.");
2465         }
2466
2467         /*
2468          * Call MI attach routine.
2469          */
2470         ether_ifattach(ifp, ether_addr, NULL);
2471
2472         if (sc->bge_flags & BGE_FLAG_STATUS_TAG)
2473                 intr_func = bge_intr_status_tag;
2474         else
2475                 intr_func = bge_intr;
2476
2477         error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE, intr_func, sc,
2478             &sc->bge_intrhand, ifp->if_serializer);
2479         if (error) {
2480                 ether_ifdetach(ifp);
2481                 device_printf(dev, "couldn't set up irq\n");
2482                 goto fail;
2483         }
2484
2485         ifp->if_cpuid = rman_get_cpuid(sc->bge_irq);
2486         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
2487
2488         return(0);
2489 fail:
2490         bge_detach(dev);
2491         return(error);
2492 }
2493
2494 static int
2495 bge_detach(device_t dev)
2496 {
2497         struct bge_softc *sc = device_get_softc(dev);
2498
2499         if (device_is_attached(dev)) {
2500                 struct ifnet *ifp = &sc->arpcom.ac_if;
2501
2502                 lwkt_serialize_enter(ifp->if_serializer);
2503                 bge_stop(sc);
2504                 bge_reset(sc);
2505                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2506                 lwkt_serialize_exit(ifp->if_serializer);
2507
2508                 ether_ifdetach(ifp);
2509         }
2510
2511         if (sc->bge_flags & BGE_FLAG_TBI)
2512                 ifmedia_removeall(&sc->bge_ifmedia);
2513         if (sc->bge_miibus)
2514                 device_delete_child(dev, sc->bge_miibus);
2515         bus_generic_detach(dev);
2516
2517         if (sc->bge_irq != NULL)
2518                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
2519
2520         if (sc->bge_res != NULL)
2521                 bus_release_resource(dev, SYS_RES_MEMORY,
2522                     BGE_PCI_BAR0, sc->bge_res);
2523
2524         if (sc->bge_sysctl_tree != NULL)
2525                 sysctl_ctx_free(&sc->bge_sysctl_ctx);
2526
2527         bge_dma_free(sc);
2528
2529         return 0;
2530 }
2531
2532 static void
2533 bge_reset(struct bge_softc *sc)
2534 {
2535         device_t dev;
2536         uint32_t cachesize, command, pcistate, reset;
2537         void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
2538         int i, val = 0;
2539
2540         dev = sc->bge_dev;
2541
2542         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
2543             sc->bge_asicrev != BGE_ASICREV_BCM5906) {
2544                 if (sc->bge_flags & BGE_FLAG_PCIE)
2545                         write_op = bge_writemem_direct;
2546                 else
2547                         write_op = bge_writemem_ind;
2548         } else {
2549                 write_op = bge_writereg_ind;
2550         }
2551
2552         /* Save some important PCI state. */
2553         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2554         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2555         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2556
2557         pci_write_config(dev, BGE_PCI_MISC_CTL,
2558             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2559             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2560             sc->bge_pci_miscctl, 4);
2561
2562         /* Disable fastboot on controllers that support it. */
2563         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2564             BGE_IS_5755_PLUS(sc)) {
2565                 if (bootverbose)
2566                         if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2567                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2568         }
2569
2570         /*
2571          * Write the magic number to SRAM at offset 0xB50.
2572          * When firmware finishes its initialization it will
2573          * write ~BGE_MAGIC_NUMBER to the same location.
2574          */
2575         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2576
2577         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2578
2579         /* XXX: Broadcom Linux driver. */
2580         if (sc->bge_flags & BGE_FLAG_PCIE) {
2581                 if (CSR_READ_4(sc, 0x7e2c) == 0x60)     /* PCIE 1.0 */
2582                         CSR_WRITE_4(sc, 0x7e2c, 0x20);
2583                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2584                         /* Prevent PCIE link training during global reset */
2585                         CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2586                         reset |= (1<<29);
2587                 }
2588         }
2589
2590         /*
2591          * Set GPHY Power Down Override to leave GPHY
2592          * powered up in D0 uninitialized.
2593          */
2594         if (BGE_IS_5705_PLUS(sc) && (sc->bge_flags & BGE_FLAG_CPMU) == 0)
2595                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2596
2597         /* Issue global reset */
2598         write_op(sc, BGE_MISC_CFG, reset);
2599
2600         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2601                 uint32_t status, ctrl;
2602
2603                 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2604                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2605                     status | BGE_VCPU_STATUS_DRV_RESET);
2606                 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2607                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2608                     ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2609         }
2610
2611         DELAY(1000);
2612
2613         /* XXX: Broadcom Linux driver. */
2614         if (sc->bge_flags & BGE_FLAG_PCIE) {
2615                 uint16_t devctl;
2616
2617                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2618                         uint32_t v;
2619
2620                         DELAY(500000); /* wait for link training to complete */
2621                         v = pci_read_config(dev, 0xc4, 4);
2622                         pci_write_config(dev, 0xc4, v | (1<<15), 4);
2623                 }
2624
2625                 /* Clear enable no snoop and disable relaxed ordering. */
2626                 devctl = pci_read_config(dev,
2627                     sc->bge_pciecap + PCIER_DEVCTRL, 2);
2628                 devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
2629                 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVCTRL,
2630                     devctl, 2);
2631
2632                 /* Clear error status. */
2633                 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVSTS,
2634                     PCIEM_DEVSTS_CORR_ERR |
2635                     PCIEM_DEVSTS_NFATAL_ERR |
2636                     PCIEM_DEVSTS_FATAL_ERR |
2637                     PCIEM_DEVSTS_UNSUPP_REQ, 2);
2638         }
2639
2640         /* Reset some of the PCI state that got zapped by reset */
2641         pci_write_config(dev, BGE_PCI_MISC_CTL,
2642             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2643             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2644             sc->bge_pci_miscctl, 4);
2645         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2646         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2647         write_op(sc, BGE_MISC_CFG, (65 << 1));
2648
2649         /*
2650          * Disable PCI-X relaxed ordering to ensure status block update
2651          * comes first then packet buffer DMA. Otherwise driver may
2652          * read stale status block.
2653          */
2654         if (sc->bge_flags & BGE_FLAG_PCIX) {
2655                 uint16_t devctl;
2656
2657                 devctl = pci_read_config(dev,
2658                     sc->bge_pcixcap + PCIXR_COMMAND, 2);
2659                 devctl &= ~PCIXM_COMMAND_ERO;
2660                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
2661                         devctl &= ~PCIXM_COMMAND_MAX_READ;
2662                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
2663                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2664                         devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
2665                             PCIXM_COMMAND_MAX_READ);
2666                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
2667                 }
2668                 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
2669                     devctl, 2);
2670         }
2671
2672         /* Enable memory arbiter. */
2673         if (BGE_IS_5714_FAMILY(sc)) {
2674                 uint32_t val;
2675
2676                 val = CSR_READ_4(sc, BGE_MARB_MODE);
2677                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2678         } else {
2679                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2680         }
2681
2682         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2683                 for (i = 0; i < BGE_TIMEOUT; i++) {
2684                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2685                         if (val & BGE_VCPU_STATUS_INIT_DONE)
2686                                 break;
2687                         DELAY(100);
2688                 }
2689                 if (i == BGE_TIMEOUT) {
2690                         if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2691                         return;
2692                 }
2693         } else {
2694                 /*
2695                  * Poll until we see the 1's complement of the magic number.
2696                  * This indicates that the firmware initialization
2697                  * is complete.
2698                  */
2699                 for (i = 0; i < BGE_FIRMWARE_TIMEOUT; i++) {
2700                         val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2701                         if (val == ~BGE_MAGIC_NUMBER)
2702                                 break;
2703                         DELAY(10);
2704                 }
2705                 if (i == BGE_FIRMWARE_TIMEOUT) {
2706                         if_printf(&sc->arpcom.ac_if, "firmware handshake "
2707                                   "timed out, found 0x%08x\n", val);
2708                         return;
2709                 }
2710         }
2711
2712         /*
2713          * XXX Wait for the value of the PCISTATE register to
2714          * return to its original pre-reset state. This is a
2715          * fairly good indicator of reset completion. If we don't
2716          * wait for the reset to fully complete, trying to read
2717          * from the device's non-PCI registers may yield garbage
2718          * results.
2719          */
2720         for (i = 0; i < BGE_TIMEOUT; i++) {
2721                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2722                         break;
2723                 DELAY(10);
2724         }
2725
2726         /* Fix up byte swapping */
2727         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2728             BGE_MODECTL_BYTESWAP_DATA);
2729
2730         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2731
2732         /*
2733          * The 5704 in TBI mode apparently needs some special
2734          * adjustment to insure the SERDES drive level is set
2735          * to 1.2V.
2736          */
2737         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2738             (sc->bge_flags & BGE_FLAG_TBI)) {
2739                 uint32_t serdescfg;
2740
2741                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2742                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2743                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2744         }
2745
2746         /* XXX: Broadcom Linux driver. */
2747         if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2748             sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
2749             sc->bge_asicrev != BGE_ASICREV_BCM5785) {
2750                 uint32_t v;
2751
2752                 /* Enable Data FIFO protection. */
2753                 v = CSR_READ_4(sc, 0x7c00);
2754                 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2755         }
2756
2757         DELAY(10000);
2758 }
2759
2760 /*
2761  * Frame reception handling. This is called if there's a frame
2762  * on the receive return list.
2763  *
2764  * Note: we have to be able to handle two possibilities here:
2765  * 1) the frame is from the jumbo recieve ring
2766  * 2) the frame is from the standard receive ring
2767  */
2768
2769 static void
2770 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod)
2771 {
2772         struct ifnet *ifp;
2773         int stdcnt = 0, jumbocnt = 0;
2774
2775         ifp = &sc->arpcom.ac_if;
2776
2777         while (sc->bge_rx_saved_considx != rx_prod) {
2778                 struct bge_rx_bd        *cur_rx;
2779                 uint32_t                rxidx;
2780                 struct mbuf             *m = NULL;
2781                 uint16_t                vlan_tag = 0;
2782                 int                     have_tag = 0;
2783
2784                 cur_rx =
2785             &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2786
2787                 rxidx = cur_rx->bge_idx;
2788                 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2789                 logif(rx_pkt);
2790
2791                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2792                         have_tag = 1;
2793                         vlan_tag = cur_rx->bge_vlan_tag;
2794                 }
2795
2796                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2797                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2798                         jumbocnt++;
2799
2800                         if (rxidx != sc->bge_jumbo) {
2801                                 ifp->if_ierrors++;
2802                                 if_printf(ifp, "sw jumbo index(%d) "
2803                                     "and hw jumbo index(%d) mismatch, drop!\n",
2804                                     sc->bge_jumbo, rxidx);
2805                                 bge_setup_rxdesc_jumbo(sc, rxidx);
2806                                 continue;
2807                         }
2808
2809                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx].bge_mbuf;
2810                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2811                                 ifp->if_ierrors++;
2812                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2813                                 continue;
2814                         }
2815                         if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 0)) {
2816                                 ifp->if_ierrors++;
2817                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2818                                 continue;
2819                         }
2820                 } else {
2821                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2822                         stdcnt++;
2823
2824                         if (rxidx != sc->bge_std) {
2825                                 ifp->if_ierrors++;
2826                                 if_printf(ifp, "sw std index(%d) "
2827                                     "and hw std index(%d) mismatch, drop!\n",
2828                                     sc->bge_std, rxidx);
2829                                 bge_setup_rxdesc_std(sc, rxidx);
2830                                 continue;
2831                         }
2832
2833                         m = sc->bge_cdata.bge_rx_std_chain[rxidx].bge_mbuf;
2834                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2835                                 ifp->if_ierrors++;
2836                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2837                                 continue;
2838                         }
2839                         if (bge_newbuf_std(sc, sc->bge_std, 0)) {
2840                                 ifp->if_ierrors++;
2841                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2842                                 continue;
2843                         }
2844                 }
2845
2846                 ifp->if_ipackets++;
2847 #if !defined(__i386__) && !defined(__x86_64__)
2848                 /*
2849                  * The x86 allows unaligned accesses, but for other
2850                  * platforms we must make sure the payload is aligned.
2851                  */
2852                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2853                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2854                             cur_rx->bge_len);
2855                         m->m_data += ETHER_ALIGN;
2856                 }
2857 #endif
2858                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2859                 m->m_pkthdr.rcvif = ifp;
2860
2861                 if (ifp->if_capenable & IFCAP_RXCSUM) {
2862                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2863                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2864                                 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2865                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2866                         }
2867                         if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
2868                             m->m_pkthdr.len >= BGE_MIN_FRAME) {
2869                                 m->m_pkthdr.csum_data =
2870                                         cur_rx->bge_tcp_udp_csum;
2871                                 m->m_pkthdr.csum_flags |=
2872                                         CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2873                         }
2874                 }
2875
2876                 /*
2877                  * If we received a packet with a vlan tag, pass it
2878                  * to vlan_input() instead of ether_input().
2879                  */
2880                 if (have_tag) {
2881                         m->m_flags |= M_VLANTAG;
2882                         m->m_pkthdr.ether_vlantag = vlan_tag;
2883                         have_tag = vlan_tag = 0;
2884                 }
2885                 ifp->if_input(ifp, m);
2886         }
2887
2888         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2889         if (stdcnt)
2890                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2891         if (jumbocnt)
2892                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2893 }
2894
2895 static void
2896 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
2897 {
2898         struct bge_tx_bd *cur_tx = NULL;
2899         struct ifnet *ifp;
2900
2901         ifp = &sc->arpcom.ac_if;
2902
2903         /*
2904          * Go through our tx ring and free mbufs for those
2905          * frames that have been sent.
2906          */
2907         while (sc->bge_tx_saved_considx != tx_cons) {
2908                 uint32_t idx = 0;
2909
2910                 idx = sc->bge_tx_saved_considx;
2911                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
2912                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2913                         ifp->if_opackets++;
2914                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2915                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
2916                             sc->bge_cdata.bge_tx_dmamap[idx]);
2917                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2918                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
2919                 }
2920                 sc->bge_txcnt--;
2921                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2922                 logif(tx_pkt);
2923         }
2924
2925         if (cur_tx != NULL &&
2926             (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2927             (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
2928                 ifp->if_flags &= ~IFF_OACTIVE;
2929
2930         if (sc->bge_txcnt == 0)
2931                 ifp->if_timer = 0;
2932
2933         if (!ifq_is_empty(&ifp->if_snd))
2934                 if_devstart(ifp);
2935 }
2936
2937 #ifdef DEVICE_POLLING
2938
2939 static void
2940 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2941 {
2942         struct bge_softc *sc = ifp->if_softc;
2943         struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
2944         uint16_t rx_prod, tx_cons;
2945
2946         switch(cmd) {
2947         case POLL_REGISTER:
2948                 bge_disable_intr(sc);
2949                 break;
2950         case POLL_DEREGISTER:
2951                 bge_enable_intr(sc);
2952                 break;
2953         case POLL_AND_CHECK_STATUS:
2954                 /*
2955                  * Process link state changes.
2956                  */
2957                 bge_link_poll(sc);
2958                 /* Fall through */
2959         case POLL_ONLY:
2960                 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
2961                         sc->bge_status_tag = sblk->bge_status_tag;
2962                         /*
2963                          * Use a load fence to ensure that status_tag
2964                          * is saved  before rx_prod and tx_cons.
2965                          */
2966                         cpu_lfence();
2967                 }
2968                 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2969                 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2970                 if (ifp->if_flags & IFF_RUNNING) {
2971                         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2972                         if (sc->bge_rx_saved_considx != rx_prod)
2973                                 bge_rxeof(sc, rx_prod);
2974
2975                         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2976                         if (sc->bge_tx_saved_considx != tx_cons)
2977                                 bge_txeof(sc, tx_cons);
2978                 }
2979                 break;
2980         }
2981 }
2982
2983 #endif
2984
2985 static void
2986 bge_intr(void *xsc)
2987 {
2988         struct bge_softc *sc = xsc;
2989         struct ifnet *ifp = &sc->arpcom.ac_if;
2990
2991         logif(intr);
2992
2993         /*
2994          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
2995          * disable interrupts by writing nonzero like we used to, since with
2996          * our current organization this just gives complications and
2997          * pessimizations for re-enabling interrupts.  We used to have races
2998          * instead of the necessary complications.  Disabling interrupts
2999          * would just reduce the chance of a status update while we are
3000          * running (by switching to the interrupt-mode coalescence
3001          * parameters), but this chance is already very low so it is more
3002          * efficient to get another interrupt than prevent it.
3003          *
3004          * We do the ack first to ensure another interrupt if there is a
3005          * status update after the ack.  We don't check for the status
3006          * changing later because it is more efficient to get another
3007          * interrupt than prevent it, not quite as above (not checking is
3008          * a smaller optimization than not toggling the interrupt enable,
3009          * since checking doesn't involve PCI accesses and toggling require
3010          * the status check).  So toggling would probably be a pessimization
3011          * even with MSI.  It would only be needed for using a task queue.
3012          */
3013         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3014
3015         /*
3016          * Process link state changes.
3017          */
3018         bge_link_poll(sc);
3019
3020         if (ifp->if_flags & IFF_RUNNING) {
3021                 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
3022                 uint16_t rx_prod, tx_cons;
3023
3024                 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
3025                 if (sc->bge_rx_saved_considx != rx_prod)
3026                         bge_rxeof(sc, rx_prod);
3027
3028                 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
3029                 if (sc->bge_tx_saved_considx != tx_cons)
3030                         bge_txeof(sc, tx_cons);
3031         }
3032
3033         if (sc->bge_coal_chg)
3034                 bge_coal_change(sc);
3035 }
3036
3037 static void
3038 bge_intr_status_tag(void *xsc)
3039 {
3040         struct bge_softc *sc = xsc;
3041         struct ifnet *ifp = &sc->arpcom.ac_if;
3042         struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
3043         uint16_t rx_prod, tx_cons;
3044         uint32_t status;
3045
3046         if (sc->bge_status_tag == sblk->bge_status_tag) {
3047                 uint32_t val;
3048
3049                 val = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4);
3050                 if (val & BGE_PCISTAT_INTR_NOTACT)
3051                         return;
3052         }
3053
3054         /*
3055          * NOTE:
3056          * Interrupt will have to be disabled if tagged status
3057          * is used, else interrupt will always be asserted on
3058          * certain chips (at least on BCM5750 AX/BX).
3059          */
3060         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3061
3062         sc->bge_status_tag = sblk->bge_status_tag;
3063         /*
3064          * Use a load fence to ensure that status_tag is saved
3065          * before rx_prod, tx_cons and status.
3066          */
3067         cpu_lfence();
3068
3069         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
3070         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
3071         status = sblk->bge_status;
3072
3073         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bge_link_evt)
3074                 bge_link_poll(sc);
3075
3076         if (ifp->if_flags & IFF_RUNNING) {
3077                 if (sc->bge_rx_saved_considx != rx_prod)
3078                         bge_rxeof(sc, rx_prod);
3079
3080                 if (sc->bge_tx_saved_considx != tx_cons)
3081                         bge_txeof(sc, tx_cons);
3082         }
3083
3084         bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24);
3085
3086         if (sc->bge_coal_chg)
3087                 bge_coal_change(sc);
3088 }
3089
3090 static void
3091 bge_tick(void *xsc)
3092 {
3093         struct bge_softc *sc = xsc;
3094         struct ifnet *ifp = &sc->arpcom.ac_if;
3095
3096         lwkt_serialize_enter(ifp->if_serializer);
3097
3098         if (BGE_IS_5705_PLUS(sc))
3099                 bge_stats_update_regs(sc);
3100         else
3101                 bge_stats_update(sc);
3102
3103         if (sc->bge_flags & BGE_FLAG_TBI) {
3104                 /*
3105                  * Since in TBI mode auto-polling can't be used we should poll
3106                  * link status manually. Here we register pending link event
3107                  * and trigger interrupt.
3108                  */
3109                 sc->bge_link_evt++;
3110                 if (BGE_IS_CRIPPLED(sc))
3111                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3112                 else
3113                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3114         } else if (!sc->bge_link) {
3115                 mii_tick(device_get_softc(sc->bge_miibus));
3116         }
3117
3118         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3119
3120         lwkt_serialize_exit(ifp->if_serializer);
3121 }
3122
3123 static void
3124 bge_stats_update_regs(struct bge_softc *sc)
3125 {
3126         struct ifnet *ifp = &sc->arpcom.ac_if;
3127         struct bge_mac_stats_regs stats;
3128         uint32_t *s;
3129         int i;
3130
3131         s = (uint32_t *)&stats;
3132         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
3133                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
3134                 s++;
3135         }
3136
3137         ifp->if_collisions +=
3138            (stats.dot3StatsSingleCollisionFrames +
3139            stats.dot3StatsMultipleCollisionFrames +
3140            stats.dot3StatsExcessiveCollisions +
3141            stats.dot3StatsLateCollisions) -
3142            ifp->if_collisions;
3143 }
3144
3145 static void
3146 bge_stats_update(struct bge_softc *sc)
3147 {
3148         struct ifnet *ifp = &sc->arpcom.ac_if;
3149         bus_size_t stats;
3150
3151         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
3152
3153 #define READ_STAT(sc, stats, stat)      \
3154         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
3155
3156         ifp->if_collisions +=
3157            (READ_STAT(sc, stats,
3158                 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
3159             READ_STAT(sc, stats,
3160                 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
3161             READ_STAT(sc, stats,
3162                 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
3163             READ_STAT(sc, stats,
3164                 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
3165            ifp->if_collisions;
3166
3167 #undef READ_STAT
3168
3169 #ifdef notdef
3170         ifp->if_collisions +=
3171            (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
3172            sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
3173            sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
3174            sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
3175            ifp->if_collisions;
3176 #endif
3177 }
3178
3179 /*
3180  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
3181  * pointers to descriptors.
3182  */
3183 static int
3184 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
3185 {
3186         struct bge_tx_bd *d = NULL;
3187         uint16_t csum_flags = 0;
3188         bus_dma_segment_t segs[BGE_NSEG_NEW];
3189         bus_dmamap_t map;
3190         int error, maxsegs, nsegs, idx, i;
3191         struct mbuf *m_head = *m_head0, *m_new;
3192
3193         if (m_head->m_pkthdr.csum_flags) {
3194                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3195                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3196                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
3197                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3198                 if (m_head->m_flags & M_LASTFRAG)
3199                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3200                 else if (m_head->m_flags & M_FRAG)
3201                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3202         }
3203
3204         idx = *txidx;
3205         map = sc->bge_cdata.bge_tx_dmamap[idx];
3206
3207         maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
3208         KASSERT(maxsegs >= BGE_NSEG_SPARE,
3209                 ("not enough segments %d", maxsegs));
3210
3211         if (maxsegs > BGE_NSEG_NEW)
3212                 maxsegs = BGE_NSEG_NEW;
3213
3214         /*
3215          * Pad outbound frame to BGE_MIN_FRAME for an unusual reason.
3216          * The bge hardware will pad out Tx runts to BGE_MIN_FRAME,
3217          * but when such padded frames employ the bge IP/TCP checksum
3218          * offload, the hardware checksum assist gives incorrect results
3219          * (possibly from incorporating its own padding into the UDP/TCP
3220          * checksum; who knows).  If we pad such runts with zeros, the
3221          * onboard checksum comes out correct.
3222          */
3223         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
3224             m_head->m_pkthdr.len < BGE_MIN_FRAME) {
3225                 error = m_devpad(m_head, BGE_MIN_FRAME);
3226                 if (error)
3227                         goto back;
3228         }
3229
3230         if ((sc->bge_flags & BGE_FLAG_SHORTDMA) && m_head->m_next != NULL) {
3231                 m_new = bge_defrag_shortdma(m_head);
3232                 if (m_new == NULL) {
3233                         error = ENOBUFS;
3234                         goto back;
3235                 }
3236                 *m_head0 = m_head = m_new;
3237         }
3238         if (sc->bge_force_defrag && (sc->bge_flags & BGE_FLAG_PCIE) &&
3239             m_head->m_next != NULL) {
3240                 /*
3241                  * Forcefully defragment mbuf chain to overcome hardware
3242                  * limitation which only support a single outstanding
3243                  * DMA read operation.  If it fails, keep moving on using
3244                  * the original mbuf chain.
3245                  */
3246                 m_new = m_defrag(m_head, MB_DONTWAIT);
3247                 if (m_new != NULL)
3248                         *m_head0 = m_head = m_new;
3249         }
3250
3251         error = bus_dmamap_load_mbuf_defrag(sc->bge_cdata.bge_tx_mtag, map,
3252                         m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3253         if (error)
3254                 goto back;
3255
3256         m_head = *m_head0;
3257         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
3258
3259         for (i = 0; ; i++) {
3260                 d = &sc->bge_ldata.bge_tx_ring[idx];
3261
3262                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
3263                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
3264                 d->bge_len = segs[i].ds_len;
3265                 d->bge_flags = csum_flags;
3266
3267                 if (i == nsegs - 1)
3268                         break;
3269                 BGE_INC(idx, BGE_TX_RING_CNT);
3270         }
3271         /* Mark the last segment as end of packet... */
3272         d->bge_flags |= BGE_TXBDFLAG_END;
3273
3274         /* Set vlan tag to the first segment of the packet. */
3275         d = &sc->bge_ldata.bge_tx_ring[*txidx];
3276         if (m_head->m_flags & M_VLANTAG) {
3277                 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
3278                 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
3279         } else {
3280                 d->bge_vlan_tag = 0;
3281         }
3282
3283         /*
3284          * Insure that the map for this transmission is placed at
3285          * the array index of the last descriptor in this chain.
3286          */
3287         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
3288         sc->bge_cdata.bge_tx_dmamap[idx] = map;
3289         sc->bge_cdata.bge_tx_chain[idx] = m_head;
3290         sc->bge_txcnt += nsegs;
3291
3292         BGE_INC(idx, BGE_TX_RING_CNT);
3293         *txidx = idx;
3294 back:
3295         if (error) {
3296                 m_freem(*m_head0);
3297                 *m_head0 = NULL;
3298         }
3299         return error;
3300 }
3301
3302 /*
3303  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3304  * to the mbuf data regions directly in the transmit descriptors.
3305  */
3306 static void
3307 bge_start(struct ifnet *ifp)
3308 {
3309         struct bge_softc *sc = ifp->if_softc;
3310         struct mbuf *m_head = NULL;
3311         uint32_t prodidx;
3312         int need_trans;
3313
3314         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
3315                 return;
3316
3317         prodidx = sc->bge_tx_prodidx;
3318
3319         need_trans = 0;
3320         while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
3321                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3322                 if (m_head == NULL)
3323                         break;
3324
3325                 /*
3326                  * XXX
3327                  * The code inside the if() block is never reached since we
3328                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
3329                  * requests to checksum TCP/UDP in a fragmented packet.
3330                  *
3331                  * XXX
3332                  * safety overkill.  If this is a fragmented packet chain
3333                  * with delayed TCP/UDP checksums, then only encapsulate
3334                  * it if we have enough descriptors to handle the entire
3335                  * chain at once.
3336                  * (paranoia -- may not actually be needed)
3337                  */
3338                 if ((m_head->m_flags & M_FIRSTFRAG) &&
3339                     (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
3340                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3341                             m_head->m_pkthdr.csum_data + BGE_NSEG_RSVD) {
3342                                 ifp->if_flags |= IFF_OACTIVE;
3343                                 ifq_prepend(&ifp->if_snd, m_head);
3344                                 break;
3345                         }
3346                 }
3347
3348                 /*
3349                  * Sanity check: avoid coming within BGE_NSEG_RSVD
3350                  * descriptors of the end of the ring.  Also make
3351                  * sure there are BGE_NSEG_SPARE descriptors for
3352                  * jumbo buffers' defragmentation.
3353                  */
3354                 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3355                     (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
3356                         ifp->if_flags |= IFF_OACTIVE;
3357                         ifq_prepend(&ifp->if_snd, m_head);
3358                         break;
3359                 }
3360
3361                 /*
3362                  * Pack the data into the transmit ring. If we
3363                  * don't have room, set the OACTIVE flag and wait
3364                  * for the NIC to drain the ring.
3365                  */
3366                 if (bge_encap(sc, &m_head, &prodidx)) {
3367                         ifp->if_flags |= IFF_OACTIVE;
3368                         ifp->if_oerrors++;
3369                         break;
3370                 }
3371                 need_trans = 1;
3372
3373                 ETHER_BPF_MTAP(ifp, m_head);
3374         }
3375
3376         if (!need_trans)
3377                 return;
3378
3379         /* Transmit */
3380         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3381         /* 5700 b2 errata */
3382         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
3383                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3384
3385         sc->bge_tx_prodidx = prodidx;
3386
3387         /*
3388          * Set a timeout in case the chip goes out to lunch.
3389          */
3390         ifp->if_timer = 5;
3391 }
3392
3393 static void
3394 bge_init(void *xsc)
3395 {
3396         struct bge_softc *sc = xsc;
3397         struct ifnet *ifp = &sc->arpcom.ac_if;
3398         uint16_t *m;
3399         uint32_t mode;
3400
3401         ASSERT_SERIALIZED(ifp->if_serializer);
3402
3403         /* Cancel pending I/O and flush buffers. */
3404         bge_stop(sc);
3405         bge_reset(sc);
3406         bge_chipinit(sc);
3407
3408         /*
3409          * Init the various state machines, ring
3410          * control blocks and firmware.
3411          */
3412         if (bge_blockinit(sc)) {
3413                 if_printf(ifp, "initialization failure\n");
3414                 bge_stop(sc);
3415                 return;
3416         }
3417
3418         /* Specify MTU. */
3419         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3420             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
3421
3422         /* Load our MAC address. */
3423         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
3424         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3425         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3426
3427         /* Enable or disable promiscuous mode as needed. */
3428         bge_setpromisc(sc);
3429
3430         /* Program multicast filter. */
3431         bge_setmulti(sc);
3432
3433         /* Init RX ring. */
3434         if (bge_init_rx_ring_std(sc)) {
3435                 if_printf(ifp, "RX ring initialization failed\n");
3436                 bge_stop(sc);
3437                 return;
3438         }
3439
3440         /*
3441          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
3442          * memory to insure that the chip has in fact read the first
3443          * entry of the ring.
3444          */
3445         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
3446                 uint32_t                v, i;
3447                 for (i = 0; i < 10; i++) {
3448                         DELAY(20);
3449                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
3450                         if (v == (MCLBYTES - ETHER_ALIGN))
3451                                 break;
3452                 }
3453                 if (i == 10)
3454                         if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
3455         }
3456
3457         /* Init jumbo RX ring. */
3458         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3459                 if (bge_init_rx_ring_jumbo(sc)) {
3460                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
3461                         bge_stop(sc);
3462                         return;
3463                 }
3464         }
3465
3466         /* Init our RX return ring index */
3467         sc->bge_rx_saved_considx = 0;
3468
3469         /* Init TX ring. */
3470         bge_init_tx_ring(sc);
3471
3472         /* Enable TX MAC state machine lockup fix. */
3473         mode = CSR_READ_4(sc, BGE_TX_MODE);
3474         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
3475                 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
3476         /* Turn on transmitter */
3477         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
3478
3479         /* Turn on receiver */
3480         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3481
3482         /*
3483          * Set the number of good frames to receive after RX MBUF
3484          * Low Watermark has been reached.  After the RX MAC receives
3485          * this number of frames, it will drop subsequent incoming
3486          * frames until the MBUF High Watermark is reached.
3487          */
3488         CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3489
3490         /* Tell firmware we're alive. */
3491         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3492
3493         /* Enable host interrupts if polling(4) is not enabled. */
3494         PCI_SETBIT(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4);
3495 #ifdef DEVICE_POLLING
3496         if (ifp->if_flags & IFF_POLLING)
3497                 bge_disable_intr(sc);
3498         else
3499 #endif
3500         bge_enable_intr(sc);
3501
3502         bge_ifmedia_upd(ifp);
3503
3504         ifp->if_flags |= IFF_RUNNING;
3505         ifp->if_flags &= ~IFF_OACTIVE;
3506
3507         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3508 }
3509
3510 /*
3511  * Set media options.
3512  */
3513 static int
3514 bge_ifmedia_upd(struct ifnet *ifp)
3515 {
3516         struct bge_softc *sc = ifp->if_softc;
3517
3518         /* If this is a 1000baseX NIC, enable the TBI port. */
3519         if (sc->bge_flags & BGE_FLAG_TBI) {
3520                 struct ifmedia *ifm = &sc->bge_ifmedia;
3521
3522                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3523                         return(EINVAL);
3524
3525                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3526                 case IFM_AUTO:
3527                         /*
3528                          * The BCM5704 ASIC appears to have a special
3529                          * mechanism for programming the autoneg
3530                          * advertisement registers in TBI mode.
3531                          */
3532                         if (!bge_fake_autoneg &&
3533                             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3534                                 uint32_t sgdig;
3535
3536                                 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3537                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3538                                 sgdig |= BGE_SGDIGCFG_AUTO |
3539                                          BGE_SGDIGCFG_PAUSE_CAP |
3540                                          BGE_SGDIGCFG_ASYM_PAUSE;
3541                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3542                                             sgdig | BGE_SGDIGCFG_SEND);
3543                                 DELAY(5);
3544                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3545                         }
3546                         break;
3547                 case IFM_1000_SX:
3548                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3549                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3550                                     BGE_MACMODE_HALF_DUPLEX);
3551                         } else {
3552                                 BGE_SETBIT(sc, BGE_MAC_MODE,
3553                                     BGE_MACMODE_HALF_DUPLEX);
3554                         }
3555                         break;
3556                 default:
3557                         return(EINVAL);
3558                 }
3559         } else {
3560                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3561
3562                 sc->bge_link_evt++;
3563                 sc->bge_link = 0;
3564                 if (mii->mii_instance) {
3565                         struct mii_softc *miisc;
3566
3567                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3568                                 mii_phy_reset(miisc);
3569                 }
3570                 mii_mediachg(mii);
3571
3572                 /*
3573                  * Force an interrupt so that we will call bge_link_upd
3574                  * if needed and clear any pending link state attention.
3575                  * Without this we are not getting any further interrupts
3576                  * for link state changes and thus will not UP the link and
3577                  * not be able to send in bge_start.  The only way to get
3578                  * things working was to receive a packet and get an RX
3579                  * intr.
3580                  *
3581                  * bge_tick should help for fiber cards and we might not
3582                  * need to do this here if BGE_FLAG_TBI is set but as
3583                  * we poll for fiber anyway it should not harm.
3584                  */
3585                 if (BGE_IS_CRIPPLED(sc))
3586                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3587                 else
3588                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3589         }
3590         return(0);
3591 }
3592
3593 /*
3594  * Report current media status.
3595  */
3596 static void
3597 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3598 {
3599         struct bge_softc *sc = ifp->if_softc;
3600
3601         if (sc->bge_flags & BGE_FLAG_TBI) {
3602                 ifmr->ifm_status = IFM_AVALID;
3603                 ifmr->ifm_active = IFM_ETHER;
3604                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3605                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3606                         ifmr->ifm_status |= IFM_ACTIVE;
3607                 } else {
3608                         ifmr->ifm_active |= IFM_NONE;
3609                         return;
3610                 }
3611
3612                 ifmr->ifm_active |= IFM_1000_SX;
3613                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3614                         ifmr->ifm_active |= IFM_HDX;
3615                 else
3616                         ifmr->ifm_active |= IFM_FDX;
3617         } else {
3618                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3619
3620                 mii_pollstat(mii);
3621                 ifmr->ifm_active = mii->mii_media_active;
3622                 ifmr->ifm_status = mii->mii_media_status;
3623         }
3624 }
3625
3626 static int
3627 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3628 {
3629         struct bge_softc *sc = ifp->if_softc;
3630         struct ifreq *ifr = (struct ifreq *)data;
3631         int mask, error = 0;
3632
3633         ASSERT_SERIALIZED(ifp->if_serializer);
3634
3635         switch (command) {
3636         case SIOCSIFMTU:
3637                 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3638                     (BGE_IS_JUMBO_CAPABLE(sc) &&
3639                      ifr->ifr_mtu > BGE_JUMBO_MTU)) {
3640                         error = EINVAL;
3641                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3642                         ifp->if_mtu = ifr->ifr_mtu;
3643                         if (ifp->if_flags & IFF_RUNNING)
3644                                 bge_init(sc);
3645                 }
3646                 break;
3647         case SIOCSIFFLAGS:
3648                 if (ifp->if_flags & IFF_UP) {
3649                         if (ifp->if_flags & IFF_RUNNING) {
3650                                 mask = ifp->if_flags ^ sc->bge_if_flags;
3651
3652                                 /*
3653                                  * If only the state of the PROMISC flag
3654                                  * changed, then just use the 'set promisc
3655                                  * mode' command instead of reinitializing
3656                                  * the entire NIC. Doing a full re-init
3657                                  * means reloading the firmware and waiting
3658                                  * for it to start up, which may take a
3659                                  * second or two.  Similarly for ALLMULTI.
3660                                  */
3661                                 if (mask & IFF_PROMISC)
3662                                         bge_setpromisc(sc);
3663                                 if (mask & IFF_ALLMULTI)
3664                                         bge_setmulti(sc);
3665                         } else {
3666                                 bge_init(sc);
3667                         }
3668                 } else if (ifp->if_flags & IFF_RUNNING) {
3669                         bge_stop(sc);
3670                 }
3671                 sc->bge_if_flags = ifp->if_flags;
3672                 break;
3673         case SIOCADDMULTI:
3674         case SIOCDELMULTI:
3675                 if (ifp->if_flags & IFF_RUNNING)
3676                         bge_setmulti(sc);
3677                 break;
3678         case SIOCSIFMEDIA:
3679         case SIOCGIFMEDIA:
3680                 if (sc->bge_flags & BGE_FLAG_TBI) {
3681                         error = ifmedia_ioctl(ifp, ifr,
3682                             &sc->bge_ifmedia, command);
3683                 } else {
3684                         struct mii_data *mii;
3685
3686                         mii = device_get_softc(sc->bge_miibus);
3687                         error = ifmedia_ioctl(ifp, ifr,
3688                                               &mii->mii_media, command);
3689                 }
3690                 break;
3691         case SIOCSIFCAP:
3692                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3693                 if (mask & IFCAP_HWCSUM) {
3694                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3695                         if (IFCAP_HWCSUM & ifp->if_capenable)
3696                                 ifp->if_hwassist = BGE_CSUM_FEATURES;
3697                         else
3698                                 ifp->if_hwassist = 0;
3699                 }
3700                 break;
3701         default:
3702                 error = ether_ioctl(ifp, command, data);
3703                 break;
3704         }
3705         return error;
3706 }
3707
3708 static void
3709 bge_watchdog(struct ifnet *ifp)
3710 {
3711         struct bge_softc *sc = ifp->if_softc;
3712
3713         if_printf(ifp, "watchdog timeout -- resetting\n");
3714
3715         bge_init(sc);
3716
3717         ifp->if_oerrors++;
3718
3719         if (!ifq_is_empty(&ifp->if_snd))
3720                 if_devstart(ifp);
3721 }
3722
3723 /*
3724  * Stop the adapter and free any mbufs allocated to the
3725  * RX and TX lists.
3726  */
3727 static void
3728 bge_stop(struct bge_softc *sc)
3729 {
3730         struct ifnet *ifp = &sc->arpcom.ac_if;
3731
3732         ASSERT_SERIALIZED(ifp->if_serializer);
3733
3734         callout_stop(&sc->bge_stat_timer);
3735
3736         /*
3737          * Disable all of the receiver blocks
3738          */
3739         bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3740         bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3741         bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3742         if (BGE_IS_5700_FAMILY(sc))
3743                 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3744         bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3745         bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3746         bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3747
3748         /*
3749          * Disable all of the transmit blocks
3750          */
3751         bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3752         bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3753         bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3754         bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3755         bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3756         if (BGE_IS_5700_FAMILY(sc))
3757                 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3758         bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3759
3760         /*
3761          * Shut down all of the memory managers and related
3762          * state machines.
3763          */
3764         bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3765         bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3766         if (BGE_IS_5700_FAMILY(sc))
3767                 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3768         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3769         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3770         if (!BGE_IS_5705_PLUS(sc)) {
3771                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3772                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3773         }
3774
3775         /* Disable host interrupts. */
3776         bge_disable_intr(sc);
3777
3778         /*
3779          * Tell firmware we're shutting down.
3780          */
3781         BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3782
3783         /* Free the RX lists. */
3784         bge_free_rx_ring_std(sc);
3785
3786         /* Free jumbo RX list. */
3787         if (BGE_IS_JUMBO_CAPABLE(sc))
3788                 bge_free_rx_ring_jumbo(sc);
3789
3790         /* Free TX buffers. */
3791         bge_free_tx_ring(sc);
3792
3793         sc->bge_status_tag = 0;
3794         sc->bge_link = 0;
3795         sc->bge_coal_chg = 0;
3796
3797         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3798
3799         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3800         ifp->if_timer = 0;
3801 }
3802
3803 /*
3804  * Stop all chip I/O so that the kernel's probe routines don't
3805  * get confused by errant DMAs when rebooting.
3806  */
3807 static void
3808 bge_shutdown(device_t dev)
3809 {
3810         struct bge_softc *sc = device_get_softc(dev);
3811         struct ifnet *ifp = &sc->arpcom.ac_if;
3812
3813         lwkt_serialize_enter(ifp->if_serializer);
3814         bge_stop(sc);
3815         bge_reset(sc);
3816         lwkt_serialize_exit(ifp->if_serializer);
3817 }
3818
3819 static int
3820 bge_suspend(device_t dev)
3821 {
3822         struct bge_softc *sc = device_get_softc(dev);
3823         struct ifnet *ifp = &sc->arpcom.ac_if;
3824
3825         lwkt_serialize_enter(ifp->if_serializer);
3826         bge_stop(sc);
3827         lwkt_serialize_exit(ifp->if_serializer);
3828
3829         return 0;
3830 }
3831
3832 static int
3833 bge_resume(device_t dev)
3834 {
3835         struct bge_softc *sc = device_get_softc(dev);
3836         struct ifnet *ifp = &sc->arpcom.ac_if;
3837
3838         lwkt_serialize_enter(ifp->if_serializer);
3839
3840         if (ifp->if_flags & IFF_UP) {
3841                 bge_init(sc);
3842
3843                 if (!ifq_is_empty(&ifp->if_snd))
3844                         if_devstart(ifp);
3845         }
3846
3847         lwkt_serialize_exit(ifp->if_serializer);
3848
3849         return 0;
3850 }
3851
3852 static void
3853 bge_setpromisc(struct bge_softc *sc)
3854 {
3855         struct ifnet *ifp = &sc->arpcom.ac_if;
3856
3857         if (ifp->if_flags & IFF_PROMISC)
3858                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3859         else
3860                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3861 }
3862
3863 static void
3864 bge_dma_free(struct bge_softc *sc)
3865 {
3866         int i;
3867
3868         /* Destroy RX mbuf DMA stuffs. */
3869         if (sc->bge_cdata.bge_rx_mtag != NULL) {
3870                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3871                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3872                             sc->bge_cdata.bge_rx_std_dmamap[i]);
3873                 }
3874                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3875                                    sc->bge_cdata.bge_rx_tmpmap);
3876                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3877         }
3878
3879         /* Destroy TX mbuf DMA stuffs. */
3880         if (sc->bge_cdata.bge_tx_mtag != NULL) {
3881                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3882                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
3883                             sc->bge_cdata.bge_tx_dmamap[i]);
3884                 }
3885                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
3886         }
3887
3888         /* Destroy standard RX ring */
3889         bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
3890                            sc->bge_cdata.bge_rx_std_ring_map,
3891                            sc->bge_ldata.bge_rx_std_ring);
3892
3893         if (BGE_IS_JUMBO_CAPABLE(sc))
3894                 bge_free_jumbo_mem(sc);
3895
3896         /* Destroy RX return ring */
3897         bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
3898                            sc->bge_cdata.bge_rx_return_ring_map,
3899                            sc->bge_ldata.bge_rx_return_ring);
3900
3901         /* Destroy TX ring */
3902         bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
3903                            sc->bge_cdata.bge_tx_ring_map,
3904                            sc->bge_ldata.bge_tx_ring);
3905
3906         /* Destroy status block */
3907         bge_dma_block_free(sc->bge_cdata.bge_status_tag,
3908                            sc->bge_cdata.bge_status_map,
3909                            sc->bge_ldata.bge_status_block);
3910
3911         /* Destroy statistics block */
3912         bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
3913                            sc->bge_cdata.bge_stats_map,
3914                            sc->bge_ldata.bge_stats);
3915
3916         /* Destroy the parent tag */
3917         if (sc->bge_cdata.bge_parent_tag != NULL)
3918                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
3919 }
3920
3921 static int
3922 bge_dma_alloc(struct bge_softc *sc)
3923 {
3924         struct ifnet *ifp = &sc->arpcom.ac_if;
3925         int i, error;
3926         bus_addr_t lowaddr;
3927
3928         lowaddr = BUS_SPACE_MAXADDR;
3929         if (sc->bge_flags & BGE_FLAG_MAXADDR_40BIT)
3930                 lowaddr = BGE_DMA_MAXADDR_40BIT;
3931
3932         /*
3933          * Allocate the parent bus DMA tag appropriate for PCI.
3934          *
3935          * All of the NetExtreme/NetLink controllers have 4GB boundary
3936          * DMA bug.
3937          * Whenever an address crosses a multiple of the 4GB boundary
3938          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3939          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3940          * state machine will lockup and cause the device to hang.
3941          */
3942         error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G,
3943                                    lowaddr, BUS_SPACE_MAXADDR,
3944                                    NULL, NULL,
3945                                    BUS_SPACE_MAXSIZE_32BIT, 0,
3946                                    BUS_SPACE_MAXSIZE_32BIT,
3947                                    0, &sc->bge_cdata.bge_parent_tag);
3948         if (error) {
3949                 if_printf(ifp, "could not allocate parent dma tag\n");
3950                 return error;
3951         }
3952
3953         /*
3954          * Create DMA tag and maps for RX mbufs.
3955          */
3956         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3957                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3958                                    NULL, NULL, MCLBYTES, 1, MCLBYTES,
3959                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
3960                                    &sc->bge_cdata.bge_rx_mtag);
3961         if (error) {
3962                 if_printf(ifp, "could not allocate RX mbuf dma tag\n");
3963                 return error;
3964         }
3965
3966         error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
3967                                   BUS_DMA_WAITOK, &sc->bge_cdata.bge_rx_tmpmap);
3968         if (error) {
3969                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3970                 sc->bge_cdata.bge_rx_mtag = NULL;
3971                 return error;
3972         }
3973
3974         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3975                 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
3976                                           BUS_DMA_WAITOK,
3977                                           &sc->bge_cdata.bge_rx_std_dmamap[i]);
3978                 if (error) {
3979                         int j;
3980
3981                         for (j = 0; j < i; ++j) {
3982                                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3983                                         sc->bge_cdata.bge_rx_std_dmamap[j]);
3984                         }
3985                         bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3986                         sc->bge_cdata.bge_rx_mtag = NULL;
3987
3988                         if_printf(ifp, "could not create DMA map for RX\n");
3989                         return error;
3990                 }
3991         }
3992
3993         /*
3994          * Create DMA tag and maps for TX mbufs.
3995          */
3996         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3997                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3998                                    NULL, NULL,
3999                                    BGE_JUMBO_FRAMELEN, BGE_NSEG_NEW, MCLBYTES,
4000                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
4001                                    BUS_DMA_ONEBPAGE,
4002                                    &sc->bge_cdata.bge_tx_mtag);
4003         if (error) {
4004                 if_printf(ifp, "could not allocate TX mbuf dma tag\n");
4005                 return error;
4006         }
4007
4008         for (i = 0; i < BGE_TX_RING_CNT; i++) {
4009                 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag,
4010                                           BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
4011                                           &sc->bge_cdata.bge_tx_dmamap[i]);
4012                 if (error) {
4013                         int j;
4014
4015                         for (j = 0; j < i; ++j) {
4016                                 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
4017                                         sc->bge_cdata.bge_tx_dmamap[j]);
4018                         }
4019                         bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
4020                         sc->bge_cdata.bge_tx_mtag = NULL;
4021
4022                         if_printf(ifp, "could not create DMA map for TX\n");
4023                         return error;
4024                 }
4025         }
4026
4027         /*
4028          * Create DMA stuffs for standard RX ring.
4029          */
4030         error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
4031                                     &sc->bge_cdata.bge_rx_std_ring_tag,
4032                                     &sc->bge_cdata.bge_rx_std_ring_map,
4033                                     (void *)&sc->bge_ldata.bge_rx_std_ring,
4034                                     &sc->bge_ldata.bge_rx_std_ring_paddr);
4035         if (error) {
4036                 if_printf(ifp, "could not create std RX ring\n");
4037                 return error;
4038         }
4039
4040         /*
4041          * Create jumbo buffer pool.
4042          */
4043         if (BGE_IS_JUMBO_CAPABLE(sc)) {
4044                 error = bge_alloc_jumbo_mem(sc);
4045                 if (error) {
4046                         if_printf(ifp, "could not create jumbo buffer pool\n");
4047                         return error;
4048                 }
4049         }
4050
4051         /*
4052          * Create DMA stuffs for RX return ring.
4053          */
4054         error = bge_dma_block_alloc(sc, BGE_RX_RTN_RING_SZ(sc),
4055                                     &sc->bge_cdata.bge_rx_return_ring_tag,
4056                                     &sc->bge_cdata.bge_rx_return_ring_map,
4057                                     (void *)&sc->bge_ldata.bge_rx_return_ring,
4058                                     &sc->bge_ldata.bge_rx_return_ring_paddr);
4059         if (error) {
4060                 if_printf(ifp, "could not create RX ret ring\n");
4061                 return error;
4062         }
4063
4064         /*
4065          * Create DMA stuffs for TX ring.
4066          */
4067         error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ,
4068                                     &sc->bge_cdata.bge_tx_ring_tag,
4069                                     &sc->bge_cdata.bge_tx_ring_map,
4070                                     (void *)&sc->bge_ldata.bge_tx_ring,
4071                                     &sc->bge_ldata.bge_tx_ring_paddr);
4072         if (error) {
4073                 if_printf(ifp, "could not create TX ring\n");
4074                 return error;
4075         }
4076
4077         /*
4078          * Create DMA stuffs for status block.
4079          */
4080         error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
4081                                     &sc->bge_cdata.bge_status_tag,
4082                                     &sc->bge_cdata.bge_status_map,
4083                                     (void *)&sc->bge_ldata.bge_status_block,
4084                                     &sc->bge_ldata.bge_status_block_paddr);
4085         if (error) {
4086                 if_printf(ifp, "could not create status block\n");
4087                 return error;
4088         }
4089
4090         /*
4091          * Create DMA stuffs for statistics block.
4092          */
4093         error = bge_dma_block_alloc(sc, BGE_STATS_SZ,
4094                                     &sc->bge_cdata.bge_stats_tag,
4095                                     &sc->bge_cdata.bge_stats_map,
4096                                     (void *)&sc->bge_ldata.bge_stats,
4097                                     &sc->bge_ldata.bge_stats_paddr);
4098         if (error) {
4099                 if_printf(ifp, "could not create stats block\n");
4100                 return error;
4101         }
4102         return 0;
4103 }
4104
4105 static int
4106 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
4107                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
4108 {
4109         bus_dmamem_t dmem;
4110         int error;
4111
4112         error = bus_dmamem_coherent(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0,
4113                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
4114                                     size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
4115         if (error)
4116                 return error;
4117
4118         *tag = dmem.dmem_tag;
4119         *map = dmem.dmem_map;
4120         *addr = dmem.dmem_addr;
4121         *paddr = dmem.dmem_busaddr;
4122
4123         return 0;
4124 }
4125
4126 static void
4127 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
4128 {
4129         if (tag != NULL) {
4130                 bus_dmamap_unload(tag, map);
4131                 bus_dmamem_free(tag, addr, map);
4132                 bus_dma_tag_destroy(tag);
4133         }
4134 }
4135
4136 /*
4137  * Grrr. The link status word in the status block does
4138  * not work correctly on the BCM5700 rev AX and BX chips,
4139  * according to all available information. Hence, we have
4140  * to enable MII interrupts in order to properly obtain
4141  * async link changes. Unfortunately, this also means that
4142  * we have to read the MAC status register to detect link
4143  * changes, thereby adding an additional register access to
4144  * the interrupt handler.
4145  *
4146  * XXX: perhaps link state detection procedure used for
4147  * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
4148  */
4149 static void
4150 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused)
4151 {
4152         struct ifnet *ifp = &sc->arpcom.ac_if;
4153         struct mii_data *mii = device_get_softc(sc->bge_miibus);
4154
4155         mii_pollstat(mii);
4156
4157         if (!sc->bge_link &&
4158             (mii->mii_media_status & IFM_ACTIVE) &&
4159             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4160                 sc->bge_link++;
4161                 if (bootverbose)
4162                         if_printf(ifp, "link UP\n");
4163         } else if (sc->bge_link &&
4164             (!(mii->mii_media_status & IFM_ACTIVE) ||
4165             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4166                 sc->bge_link = 0;
4167                 if (bootverbose)
4168                         if_printf(ifp, "link DOWN\n");
4169         }
4170
4171         /* Clear the interrupt. */
4172         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT);
4173         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
4174         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS);
4175 }
4176
4177 static void
4178 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status)
4179 {
4180         struct ifnet *ifp = &sc->arpcom.ac_if;
4181
4182 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
4183
4184         /*
4185          * Sometimes PCS encoding errors are detected in
4186          * TBI mode (on fiber NICs), and for some reason
4187          * the chip will signal them as link changes.
4188          * If we get a link change event, but the 'PCS
4189          * encoding error' bit in the MAC status register
4190          * is set, don't bother doing a link check.
4191          * This avoids spurious "gigabit link up" messages
4192          * that sometimes appear on fiber NICs during
4193          * periods of heavy traffic.
4194          */
4195         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
4196                 if (!sc->bge_link) {
4197                         sc->bge_link++;
4198                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4199                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
4200                                     BGE_MACMODE_TBI_SEND_CFGS);
4201                         }
4202                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
4203
4204                         if (bootverbose)
4205                                 if_printf(ifp, "link UP\n");
4206
4207                         ifp->if_link_state = LINK_STATE_UP;
4208                         if_link_state_change(ifp);
4209                 }
4210         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
4211                 if (sc->bge_link) {
4212                         sc->bge_link = 0;
4213
4214                         if (bootverbose)
4215                                 if_printf(ifp, "link DOWN\n");
4216
4217                         ifp->if_link_state = LINK_STATE_DOWN;
4218                         if_link_state_change(ifp);
4219                 }
4220         }
4221
4222 #undef PCS_ENCODE_ERR
4223
4224         /* Clear the attention. */
4225         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4226             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4227             BGE_MACSTAT_LINK_CHANGED);
4228 }
4229
4230 static void
4231 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused)
4232 {
4233         struct ifnet *ifp = &sc->arpcom.ac_if;
4234         struct mii_data *mii = device_get_softc(sc->bge_miibus);
4235
4236         mii_pollstat(mii);
4237         bge_miibus_statchg(sc->bge_dev);
4238
4239         if (bootverbose) {
4240                 if (sc->bge_link)
4241                         if_printf(ifp, "link UP\n");
4242                 else
4243                         if_printf(ifp, "link DOWN\n");
4244         }
4245
4246         /* Clear the attention. */
4247         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4248             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4249             BGE_MACSTAT_LINK_CHANGED);
4250 }
4251
4252 static void
4253 bge_autopoll_link_upd(struct bge_softc *sc, uint32_t status __unused)
4254 {
4255         struct ifnet *ifp = &sc->arpcom.ac_if;
4256         struct mii_data *mii = device_get_softc(sc->bge_miibus);
4257
4258         mii_pollstat(mii);
4259
4260         if (!sc->bge_link &&
4261             (mii->mii_media_status & IFM_ACTIVE) &&
4262             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4263                 sc->bge_link++;
4264                 if (bootverbose)
4265                         if_printf(ifp, "link UP\n");
4266         } else if (sc->bge_link &&
4267             (!(mii->mii_media_status & IFM_ACTIVE) ||
4268             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4269                 sc->bge_link = 0;
4270                 if (bootverbose)
4271                         if_printf(ifp, "link DOWN\n");
4272         }
4273
4274         /* Clear the attention. */
4275         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4276             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4277             BGE_MACSTAT_LINK_CHANGED);
4278 }
4279
4280 static int
4281 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
4282 {
4283         struct bge_softc *sc = arg1;
4284
4285         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4286             &sc->bge_rx_coal_ticks,
4287             BGE_RX_COAL_TICKS_MIN, BGE_RX_COAL_TICKS_MAX,
4288             BGE_RX_COAL_TICKS_CHG);
4289 }
4290
4291 static int
4292 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
4293 {
4294         struct bge_softc *sc = arg1;
4295
4296         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4297             &sc->bge_tx_coal_ticks,
4298             BGE_TX_COAL_TICKS_MIN, BGE_TX_COAL_TICKS_MAX,
4299             BGE_TX_COAL_TICKS_CHG);
4300 }
4301
4302 static int
4303 bge_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS)
4304 {
4305         struct bge_softc *sc = arg1;
4306
4307         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4308             &sc->bge_rx_coal_bds,
4309             BGE_RX_COAL_BDS_MIN, BGE_RX_COAL_BDS_MAX,
4310             BGE_RX_COAL_BDS_CHG);
4311 }
4312
4313 static int
4314 bge_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS)
4315 {
4316         struct bge_softc *sc = arg1;
4317
4318         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4319             &sc->bge_tx_coal_bds,
4320             BGE_TX_COAL_BDS_MIN, BGE_TX_COAL_BDS_MAX,
4321             BGE_TX_COAL_BDS_CHG);
4322 }
4323
4324 static int
4325 bge_sysctl_rx_coal_ticks_int(SYSCTL_HANDLER_ARGS)
4326 {
4327         struct bge_softc *sc = arg1;
4328
4329         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4330             &sc->bge_rx_coal_ticks_int,
4331             BGE_RX_COAL_TICKS_MIN, BGE_RX_COAL_TICKS_MAX,
4332             BGE_RX_COAL_TICKS_INT_CHG);
4333 }
4334
4335 static int
4336 bge_sysctl_tx_coal_ticks_int(SYSCTL_HANDLER_ARGS)
4337 {
4338         struct bge_softc *sc = arg1;
4339
4340         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4341             &sc->bge_tx_coal_ticks_int,
4342             BGE_TX_COAL_TICKS_MIN, BGE_TX_COAL_TICKS_MAX,
4343             BGE_TX_COAL_TICKS_INT_CHG);
4344 }
4345
4346 static int
4347 bge_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS)
4348 {
4349         struct bge_softc *sc = arg1;
4350
4351         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4352             &sc->bge_rx_coal_bds_int,
4353             BGE_RX_COAL_BDS_MIN, BGE_RX_COAL_BDS_MAX,
4354             BGE_RX_COAL_BDS_INT_CHG);
4355 }
4356
4357 static int
4358 bge_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS)
4359 {
4360         struct bge_softc *sc = arg1;
4361
4362         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4363             &sc->bge_tx_coal_bds_int,
4364             BGE_TX_COAL_BDS_MIN, BGE_TX_COAL_BDS_MAX,
4365             BGE_TX_COAL_BDS_INT_CHG);
4366 }
4367
4368 static int
4369 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
4370     int coal_min, int coal_max, uint32_t coal_chg_mask)
4371 {
4372         struct bge_softc *sc = arg1;
4373         struct ifnet *ifp = &sc->arpcom.ac_if;
4374         int error = 0, v;
4375
4376         lwkt_serialize_enter(ifp->if_serializer);
4377
4378         v = *coal;
4379         error = sysctl_handle_int(oidp, &v, 0, req);
4380         if (!error && req->newptr != NULL) {
4381                 if (v < coal_min || v > coal_max) {
4382                         error = EINVAL;
4383                 } else {
4384                         *coal = v;
4385                         sc->bge_coal_chg |= coal_chg_mask;
4386                 }
4387         }
4388
4389         lwkt_serialize_exit(ifp->if_serializer);
4390         return error;
4391 }
4392
4393 static void
4394 bge_coal_change(struct bge_softc *sc)
4395 {
4396         struct ifnet *ifp = &sc->arpcom.ac_if;
4397         uint32_t val;
4398
4399         ASSERT_SERIALIZED(ifp->if_serializer);
4400
4401         if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_CHG) {
4402                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
4403                             sc->bge_rx_coal_ticks);
4404                 DELAY(10);
4405                 val = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
4406
4407                 if (bootverbose) {
4408                         if_printf(ifp, "rx_coal_ticks -> %u\n",
4409                                   sc->bge_rx_coal_ticks);
4410                 }
4411         }
4412
4413         if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_CHG) {
4414                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
4415                             sc->bge_tx_coal_ticks);
4416                 DELAY(10);
4417                 val = CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
4418
4419                 if (bootverbose) {
4420                         if_printf(ifp, "tx_coal_ticks -> %u\n",
4421                                   sc->bge_tx_coal_ticks);
4422                 }
4423         }
4424
4425         if (sc->bge_coal_chg & BGE_RX_COAL_BDS_CHG) {
4426                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
4427                             sc->bge_rx_coal_bds);
4428                 DELAY(10);
4429                 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
4430
4431                 if (bootverbose) {
4432                         if_printf(ifp, "rx_coal_bds -> %u\n",
4433                                   sc->bge_rx_coal_bds);
4434                 }
4435         }
4436
4437         if (sc->bge_coal_chg & BGE_TX_COAL_BDS_CHG) {
4438                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
4439                             sc->bge_tx_coal_bds);
4440                 DELAY(10);
4441                 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
4442
4443                 if (bootverbose) {
4444                         if_printf(ifp, "tx_max_coal_bds -> %u\n",
4445                                   sc->bge_tx_coal_bds);
4446                 }
4447         }
4448
4449         if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_INT_CHG) {
4450                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT,
4451                     sc->bge_rx_coal_ticks_int);
4452                 DELAY(10);
4453                 val = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS_INT);
4454
4455                 if (bootverbose) {
4456                         if_printf(ifp, "rx_coal_ticks_int -> %u\n",
4457                             sc->bge_rx_coal_ticks_int);
4458                 }
4459         }
4460
4461         if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_INT_CHG) {
4462                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT,
4463                     sc->bge_tx_coal_ticks_int);
4464                 DELAY(10);
4465                 val = CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS_INT);
4466
4467                 if (bootverbose) {
4468                         if_printf(ifp, "tx_coal_ticks_int -> %u\n",
4469                             sc->bge_tx_coal_ticks_int);
4470                 }
4471         }
4472
4473         if (sc->bge_coal_chg & BGE_RX_COAL_BDS_INT_CHG) {
4474                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT,
4475                     sc->bge_rx_coal_bds_int);
4476                 DELAY(10);
4477                 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT);
4478
4479                 if (bootverbose) {
4480                         if_printf(ifp, "rx_coal_bds_int -> %u\n",
4481                             sc->bge_rx_coal_bds_int);
4482                 }
4483         }
4484
4485         if (sc->bge_coal_chg & BGE_TX_COAL_BDS_INT_CHG) {
4486                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT,
4487                     sc->bge_tx_coal_bds_int);
4488                 DELAY(10);
4489                 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT);
4490
4491                 if (bootverbose) {
4492                         if_printf(ifp, "tx_coal_bds_int -> %u\n",
4493                             sc->bge_tx_coal_bds_int);
4494                 }
4495         }
4496
4497         sc->bge_coal_chg = 0;
4498 }
4499
4500 static void
4501 bge_enable_intr(struct bge_softc *sc)
4502 {
4503         struct ifnet *ifp = &sc->arpcom.ac_if;
4504
4505         lwkt_serialize_handler_enable(ifp->if_serializer);
4506
4507         /*
4508          * Enable interrupt.
4509          */
4510         bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24);
4511
4512         /*
4513          * Unmask the interrupt when we stop polling.
4514          */
4515         PCI_CLRBIT(sc->bge_dev, BGE_PCI_MISC_CTL,
4516             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
4517
4518         /*
4519          * Trigger another interrupt, since above writing
4520          * to interrupt mailbox0 may acknowledge pending
4521          * interrupt.
4522          */
4523         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4524 }
4525
4526 static void
4527 bge_disable_intr(struct bge_softc *sc)
4528 {
4529         struct ifnet *ifp = &sc->arpcom.ac_if;
4530
4531         /*
4532          * Mask the interrupt when we start polling.
4533          */
4534         PCI_SETBIT(sc->bge_dev, BGE_PCI_MISC_CTL,
4535             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
4536
4537         /*
4538          * Acknowledge possible asserted interrupt.
4539          */
4540         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4541
4542         lwkt_serialize_handler_disable(ifp->if_serializer);
4543 }
4544
4545 static int
4546 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
4547 {
4548         uint32_t mac_addr;
4549         int ret = 1;
4550
4551         mac_addr = bge_readmem_ind(sc, 0x0c14);
4552         if ((mac_addr >> 16) == 0x484b) {
4553                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
4554                 ether_addr[1] = (uint8_t)mac_addr;
4555                 mac_addr = bge_readmem_ind(sc, 0x0c18);
4556                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
4557                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
4558                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
4559                 ether_addr[5] = (uint8_t)mac_addr;
4560                 ret = 0;
4561         }
4562         return ret;
4563 }
4564
4565 static int
4566 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
4567 {
4568         int mac_offset = BGE_EE_MAC_OFFSET;
4569
4570         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
4571                 mac_offset = BGE_EE_MAC_OFFSET_5906;
4572
4573         return bge_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
4574 }
4575
4576 static int
4577 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
4578 {
4579         if (sc->bge_flags & BGE_FLAG_NO_EEPROM)
4580                 return 1;
4581
4582         return bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4583                                ETHER_ADDR_LEN);
4584 }
4585
4586 static int
4587 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
4588 {
4589         static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
4590                 /* NOTE: Order is critical */
4591                 bge_get_eaddr_mem,
4592                 bge_get_eaddr_nvram,
4593                 bge_get_eaddr_eeprom,
4594                 NULL
4595         };
4596         const bge_eaddr_fcn_t *func;
4597
4598         for (func = bge_eaddr_funcs; *func != NULL; ++func) {
4599                 if ((*func)(sc, eaddr) == 0)
4600                         break;
4601         }
4602         return (*func == NULL ? ENXIO : 0);
4603 }
4604
4605 /*
4606  * NOTE: 'm' is not freed upon failure
4607  */
4608 struct mbuf *
4609 bge_defrag_shortdma(struct mbuf *m)
4610 {
4611         struct mbuf *n;
4612         int found;
4613
4614         /*
4615          * If device receive two back-to-back send BDs with less than
4616          * or equal to 8 total bytes then the device may hang.  The two
4617          * back-to-back send BDs must in the same frame for this failure
4618          * to occur.  Scan mbuf chains and see whether two back-to-back
4619          * send BDs are there.  If this is the case, allocate new mbuf
4620          * and copy the frame to workaround the silicon bug.
4621          */
4622         for (n = m, found = 0; n != NULL; n = n->m_next) {
4623                 if (n->m_len < 8) {
4624                         found++;
4625                         if (found > 1)
4626                                 break;
4627                         continue;
4628                 }
4629                 found = 0;
4630         }
4631
4632         if (found > 1)
4633                 n = m_defrag(m, MB_DONTWAIT);
4634         else
4635                 n = m;
4636         return n;
4637 }
4638
4639 static void
4640 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)
4641 {
4642         int i;
4643
4644         BGE_CLRBIT(sc, reg, bit);
4645         for (i = 0; i < BGE_TIMEOUT; i++) {
4646                 if ((CSR_READ_4(sc, reg) & bit) == 0)
4647                         return;
4648                 DELAY(100);
4649         }
4650 }
4651
4652 static void
4653 bge_link_poll(struct bge_softc *sc)
4654 {
4655         uint32_t status;
4656
4657         status = CSR_READ_4(sc, BGE_MAC_STS);
4658         if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
4659                 sc->bge_link_evt = 0;
4660                 sc->bge_link_upd(sc, status);
4661         }
4662 }