2 * Copyright 2008 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Jerome Glisse <glisse@freedesktop.org>
27 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_cs.c 254885 2013-08-25 19:37:15Z dumbbell $
31 #include <uapi_drm/radeon_drm.h>
32 #include "radeon_reg.h"
35 static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
37 struct drm_device *ddev = p->rdev->ddev;
38 struct radeon_cs_chunk *chunk;
42 if (p->chunk_relocs_idx == -1) {
45 chunk = &p->chunks[p->chunk_relocs_idx];
47 /* FIXME: we assume that each relocs use 4 dwords */
48 p->nrelocs = chunk->length_dw / 4;
49 p->relocs_ptr = kmalloc(p->nrelocs * sizeof(void *), M_DRM,
51 if (p->relocs_ptr == NULL) {
54 p->relocs = kmalloc(p->nrelocs * sizeof(struct radeon_cs_reloc),
55 M_DRM, M_ZERO | M_WAITOK);
56 if (p->relocs == NULL) {
59 for (i = 0; i < p->nrelocs; i++) {
60 struct drm_radeon_cs_reloc *r;
63 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
64 for (j = 0; j < i; j++) {
65 if (r->handle == p->relocs[j].handle) {
66 p->relocs_ptr[i] = &p->relocs[j];
72 p->relocs[i].handle = 0;
76 p->relocs[i].gobj = drm_gem_object_lookup(ddev, p->filp,
78 if (p->relocs[i].gobj == NULL) {
79 DRM_ERROR("gem object lookup failed 0x%x\n",
83 p->relocs_ptr[i] = &p->relocs[i];
84 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
85 p->relocs[i].lobj.bo = p->relocs[i].robj;
86 p->relocs[i].lobj.written = !!r->write_domain;
88 /* the first reloc of an UVD job is the
89 msg and that must be in VRAM */
90 if (p->ring == R600_RING_TYPE_UVD_INDEX && i == 0) {
91 /* TODO: is this still needed for NI+ ? */
92 p->relocs[i].lobj.domain =
93 RADEON_GEM_DOMAIN_VRAM;
95 p->relocs[i].lobj.alt_domain =
96 RADEON_GEM_DOMAIN_VRAM;
99 uint32_t domain = r->write_domain ?
100 r->write_domain : r->read_domains;
102 p->relocs[i].lobj.domain = domain;
103 if (domain == RADEON_GEM_DOMAIN_VRAM)
104 domain |= RADEON_GEM_DOMAIN_GTT;
105 p->relocs[i].lobj.alt_domain = domain;
108 p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
109 p->relocs[i].handle = r->handle;
111 radeon_bo_list_add_object(&p->relocs[i].lobj,
114 return radeon_bo_list_validate(&p->validated, p->ring);
117 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
119 p->priority = priority;
123 DRM_ERROR("unknown ring id: %d\n", ring);
125 case RADEON_CS_RING_GFX:
126 p->ring = RADEON_RING_TYPE_GFX_INDEX;
128 case RADEON_CS_RING_COMPUTE:
129 if (p->rdev->family >= CHIP_TAHITI) {
131 p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
133 p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
135 p->ring = RADEON_RING_TYPE_GFX_INDEX;
137 case RADEON_CS_RING_DMA:
138 if (p->rdev->family >= CHIP_CAYMAN) {
140 p->ring = R600_RING_TYPE_DMA_INDEX;
142 p->ring = CAYMAN_RING_TYPE_DMA1_INDEX;
143 } else if (p->rdev->family >= CHIP_R600) {
144 p->ring = R600_RING_TYPE_DMA_INDEX;
149 case RADEON_CS_RING_UVD:
150 p->ring = R600_RING_TYPE_UVD_INDEX;
156 static void radeon_cs_sync_rings(struct radeon_cs_parser *p)
160 for (i = 0; i < p->nrelocs; i++) {
161 if (!p->relocs[i].robj)
164 radeon_ib_sync_to(&p->ib, p->relocs[i].robj->tbo.sync_obj);
168 /* XXX: note that this is called from the legacy UMS CS ioctl as well */
169 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
171 struct drm_radeon_cs *cs = data;
172 uint64_t *chunk_array_ptr;
174 u32 ring = RADEON_CS_RING_GFX;
177 if (!cs->num_chunks) {
181 INIT_LIST_HEAD(&p->validated);
184 p->ib.semaphore = NULL;
185 p->const_ib.sa_bo = NULL;
186 p->const_ib.semaphore = NULL;
187 p->chunk_ib_idx = -1;
188 p->chunk_relocs_idx = -1;
189 p->chunk_flags_idx = -1;
190 p->chunk_const_ib_idx = -1;
191 p->chunks_array = kmalloc(cs->num_chunks * sizeof(uint64_t),
192 M_DRM, M_ZERO | M_WAITOK);
193 if (p->chunks_array == NULL) {
196 chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
197 if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
198 sizeof(uint64_t)*cs->num_chunks)) {
202 p->nchunks = cs->num_chunks;
203 p->chunks = kmalloc(p->nchunks * sizeof(struct radeon_cs_chunk),
204 M_DRM, M_ZERO | M_WAITOK);
205 if (p->chunks == NULL) {
208 for (i = 0; i < p->nchunks; i++) {
209 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
210 struct drm_radeon_cs_chunk user_chunk;
211 uint32_t __user *cdata;
213 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
214 if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
215 sizeof(struct drm_radeon_cs_chunk))) {
218 p->chunks[i].length_dw = user_chunk.length_dw;
219 p->chunks[i].kdata = NULL;
220 p->chunks[i].chunk_id = user_chunk.chunk_id;
221 p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;
222 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
223 p->chunk_relocs_idx = i;
225 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
227 /* zero length IB isn't useful */
228 if (p->chunks[i].length_dw == 0)
231 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
232 p->chunk_const_ib_idx = i;
233 /* zero length CONST IB isn't useful */
234 if (p->chunks[i].length_dw == 0)
237 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
238 p->chunk_flags_idx = i;
239 /* zero length flags aren't useful */
240 if (p->chunks[i].length_dw == 0)
244 cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
245 if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) ||
246 (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
247 size = p->chunks[i].length_dw * sizeof(uint32_t);
248 p->chunks[i].kdata = kmalloc(size, M_DRM,
250 if (p->chunks[i].kdata == NULL) {
253 if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
254 p->chunks[i].user_ptr, size)) {
257 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
258 p->cs_flags = p->chunks[i].kdata[0];
259 if (p->chunks[i].length_dw > 1)
260 ring = p->chunks[i].kdata[1];
261 if (p->chunks[i].length_dw > 2)
262 priority = (s32)p->chunks[i].kdata[2];
267 /* these are KMS only */
269 if ((p->cs_flags & RADEON_CS_USE_VM) &&
270 !p->rdev->vm_manager.enabled) {
271 DRM_ERROR("VM not active on asic!\n");
275 if (radeon_cs_get_ring(p, ring, priority))
278 /* we only support VM on some SI+ rings */
279 if ((p->rdev->asic->ring[p->ring].cs_parse == NULL) &&
280 ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
281 DRM_ERROR("Ring %d requires VM!\n", p->ring);
286 /* deal with non-vm */
287 if ((p->chunk_ib_idx != -1) &&
288 ((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
289 (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
290 if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
291 DRM_ERROR("cs IB too big: %d\n",
292 p->chunks[p->chunk_ib_idx].length_dw);
295 if (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) {
296 p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE,
299 p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE,
302 if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL ||
303 p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
304 drm_free(p->chunks[p->chunk_ib_idx].kpage[0],
306 drm_free(p->chunks[p->chunk_ib_idx].kpage[1],
308 p->chunks[p->chunk_ib_idx].kpage[0] = NULL;
309 p->chunks[p->chunk_ib_idx].kpage[1] = NULL;
313 p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
314 p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
315 p->chunks[p->chunk_ib_idx].last_copied_page = -1;
316 p->chunks[p->chunk_ib_idx].last_page_index =
317 ((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
324 * cs_parser_fini() - clean parser states
325 * @parser: parser structure holding parsing context.
326 * @error: error number
328 * If error is set than unvalidate buffer, otherwise just free memory
329 * used by parsing context.
331 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
336 ttm_eu_fence_buffer_objects(&parser->validated,
339 ttm_eu_backoff_reservation(&parser->validated);
342 if (parser->relocs != NULL) {
343 for (i = 0; i < parser->nrelocs; i++) {
344 if (parser->relocs[i].gobj)
345 drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
348 drm_free(parser->track, M_DRM);
349 drm_free(parser->relocs, M_DRM);
350 drm_free(parser->relocs_ptr, M_DRM);
351 for (i = 0; i < parser->nchunks; i++) {
352 drm_free(parser->chunks[i].kdata, M_DRM);
353 if ((parser->rdev->flags & RADEON_IS_AGP)) {
354 drm_free(parser->chunks[i].kpage[0], M_DRM);
355 drm_free(parser->chunks[i].kpage[1], M_DRM);
358 drm_free(parser->chunks, M_DRM);
359 drm_free(parser->chunks_array, M_DRM);
360 radeon_ib_free(parser->rdev, &parser->ib);
361 radeon_ib_free(parser->rdev, &parser->const_ib);
364 static int radeon_cs_ib_chunk(struct radeon_device *rdev,
365 struct radeon_cs_parser *parser)
367 struct radeon_cs_chunk *ib_chunk;
370 if (parser->chunk_ib_idx == -1)
373 if (parser->cs_flags & RADEON_CS_USE_VM)
376 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
377 /* Copy the packet into the IB, the parser will read from the
378 * input memory (cached) and write to the IB (which can be
381 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
382 NULL, ib_chunk->length_dw * 4);
384 DRM_ERROR("Failed to get ib !\n");
387 parser->ib.length_dw = ib_chunk->length_dw;
388 r = radeon_cs_parse(rdev, parser->ring, parser);
389 if (r || parser->parser_error) {
390 DRM_ERROR("Invalid command stream !\n");
393 r = radeon_cs_finish_pages(parser);
395 DRM_ERROR("Invalid command stream !\n");
398 radeon_cs_sync_rings(parser);
399 r = radeon_ib_schedule(rdev, &parser->ib, NULL);
401 DRM_ERROR("Failed to schedule IB !\n");
406 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
407 struct radeon_vm *vm)
409 struct radeon_device *rdev = parser->rdev;
410 struct radeon_bo_list *lobj;
411 struct radeon_bo *bo;
414 r = radeon_vm_bo_update_pte(rdev, vm, rdev->ring_tmp_bo.bo, &rdev->ring_tmp_bo.bo->tbo.mem);
418 list_for_each_entry(lobj, &parser->validated, tv.head) {
420 r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
428 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
429 struct radeon_cs_parser *parser)
431 struct radeon_cs_chunk *ib_chunk;
432 struct radeon_fpriv *fpriv = parser->filp->driver_priv;
433 struct radeon_vm *vm = &fpriv->vm;
436 if (parser->chunk_ib_idx == -1)
438 if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
441 if ((rdev->family >= CHIP_TAHITI) &&
442 (parser->chunk_const_ib_idx != -1)) {
443 ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
444 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
445 DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
448 r = radeon_ib_get(rdev, parser->ring, &parser->const_ib,
449 vm, ib_chunk->length_dw * 4);
451 DRM_ERROR("Failed to get const ib !\n");
454 parser->const_ib.is_const_ib = true;
455 parser->const_ib.length_dw = ib_chunk->length_dw;
456 /* Copy the packet into the IB */
457 if (DRM_COPY_FROM_USER(parser->const_ib.ptr, ib_chunk->user_ptr,
458 ib_chunk->length_dw * 4)) {
461 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib);
467 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
468 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
469 DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
472 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
473 vm, ib_chunk->length_dw * 4);
475 DRM_ERROR("Failed to get ib !\n");
478 parser->ib.length_dw = ib_chunk->length_dw;
479 /* Copy the packet into the IB */
480 if (DRM_COPY_FROM_USER(parser->ib.ptr, ib_chunk->user_ptr,
481 ib_chunk->length_dw * 4)) {
484 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib);
489 lockmgr(&rdev->vm_manager.lock, LK_EXCLUSIVE);
490 lockmgr(&vm->mutex, LK_EXCLUSIVE);
491 r = radeon_vm_alloc_pt(rdev, vm);
495 r = radeon_bo_vm_update_pte(parser, vm);
499 radeon_cs_sync_rings(parser);
500 radeon_ib_sync_to(&parser->ib, vm->fence);
501 radeon_ib_sync_to(&parser->ib, radeon_vm_grab_id(
502 rdev, vm, parser->ring));
504 if ((rdev->family >= CHIP_TAHITI) &&
505 (parser->chunk_const_ib_idx != -1)) {
506 r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib);
508 r = radeon_ib_schedule(rdev, &parser->ib, NULL);
512 radeon_vm_fence(rdev, vm, parser->ib.fence);
516 radeon_vm_add_to_lru(rdev, vm);
517 lockmgr(&vm->mutex, LK_RELEASE);
518 lockmgr(&rdev->vm_manager.lock, LK_RELEASE);
522 static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r)
525 r = radeon_gpu_reset(rdev);
532 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
534 struct radeon_device *rdev = dev->dev_private;
535 struct radeon_cs_parser parser;
538 lockmgr(&rdev->exclusive_lock, LK_EXCLUSIVE);
539 if (!rdev->accel_working) {
540 lockmgr(&rdev->exclusive_lock, LK_RELEASE);
543 /* initialize parser */
544 memset(&parser, 0, sizeof(struct radeon_cs_parser));
547 parser.dev = rdev->dev;
548 parser.family = rdev->family;
549 r = radeon_cs_parser_init(&parser, data);
551 DRM_ERROR("Failed to initialize parser !\n");
552 radeon_cs_parser_fini(&parser, r);
553 lockmgr(&rdev->exclusive_lock, LK_RELEASE);
554 r = radeon_cs_handle_lockup(rdev, r);
557 r = radeon_cs_parser_relocs(&parser);
559 if (r != -ERESTARTSYS)
560 DRM_ERROR("Failed to parse relocation %d!\n", r);
561 radeon_cs_parser_fini(&parser, r);
562 lockmgr(&rdev->exclusive_lock, LK_RELEASE);
563 r = radeon_cs_handle_lockup(rdev, r);
567 if (parser.ring == R600_RING_TYPE_UVD_INDEX)
568 radeon_uvd_note_usage(rdev);
570 r = radeon_cs_ib_chunk(rdev, &parser);
574 r = radeon_cs_ib_vm_chunk(rdev, &parser);
579 radeon_cs_parser_fini(&parser, r);
580 lockmgr(&rdev->exclusive_lock, LK_RELEASE);
581 r = radeon_cs_handle_lockup(rdev, r);
585 int radeon_cs_finish_pages(struct radeon_cs_parser *p)
587 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
589 int size = PAGE_SIZE;
591 for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
592 if (i == ibc->last_page_index) {
593 size = (ibc->length_dw * 4) % PAGE_SIZE;
598 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
599 (char *)ibc->user_ptr + (i * PAGE_SIZE),
606 static int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
609 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
611 int size = PAGE_SIZE;
612 bool copy1 = (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) ?
615 for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
616 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
617 (char *)ibc->user_ptr + (i * PAGE_SIZE),
619 p->parser_error = -EFAULT;
624 if (pg_idx == ibc->last_page_index) {
625 size = (ibc->length_dw * 4) % PAGE_SIZE;
630 new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
632 ibc->kpage[new_page] = p->ib.ptr + (pg_idx * (PAGE_SIZE / 4));
634 if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
635 (char *)ibc->user_ptr + (pg_idx * PAGE_SIZE),
637 p->parser_error = -EFAULT;
641 /* copy to IB for non single case */
643 memcpy((void *)(p->ib.ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size);
645 ibc->last_copied_page = pg_idx;
646 ibc->kpage_idx[new_page] = pg_idx;
651 u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
653 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
654 u32 pg_idx, pg_offset;
658 pg_idx = (idx * 4) / PAGE_SIZE;
659 pg_offset = (idx * 4) % PAGE_SIZE;
661 if (ibc->kpage_idx[0] == pg_idx)
662 return ibc->kpage[0][pg_offset/4];
663 if (ibc->kpage_idx[1] == pg_idx)
664 return ibc->kpage[1][pg_offset/4];
666 new_page = radeon_cs_update_pages(p, pg_idx);
668 p->parser_error = new_page;
672 idx_value = ibc->kpage[new_page][pg_offset/4];
677 * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet
678 * @parser: parser structure holding parsing context.
679 * @pkt: where to store packet information
681 * Assume that chunk_ib_index is properly set. Will return -EINVAL
682 * if packet is bigger than remaining ib size. or if packets is unknown.
684 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
685 struct radeon_cs_packet *pkt,
688 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
689 struct radeon_device *rdev = p->rdev;
692 if (idx >= ib_chunk->length_dw) {
693 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
694 idx, ib_chunk->length_dw);
697 header = radeon_get_ib_value(p, idx);
699 pkt->type = RADEON_CP_PACKET_GET_TYPE(header);
700 pkt->count = RADEON_CP_PACKET_GET_COUNT(header);
703 case RADEON_PACKET_TYPE0:
704 if (rdev->family < CHIP_R600) {
705 pkt->reg = R100_CP_PACKET0_GET_REG(header);
707 RADEON_CP_PACKET0_GET_ONE_REG_WR(header);
709 pkt->reg = R600_CP_PACKET0_GET_REG(header);
711 case RADEON_PACKET_TYPE3:
712 pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header);
714 case RADEON_PACKET_TYPE2:
718 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
721 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
722 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
723 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
730 * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP
731 * @p: structure holding the parser context.
733 * Check if the next packet is NOP relocation packet3.
735 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
737 struct radeon_cs_packet p3reloc;
740 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
743 if (p3reloc.type != RADEON_PACKET_TYPE3)
745 if (p3reloc.opcode != RADEON_PACKET3_NOP)
751 * radeon_cs_dump_packet() - dump raw packet context
752 * @p: structure holding the parser context.
753 * @pkt: structure holding the packet.
755 * Used mostly for debugging and error reporting.
757 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
758 struct radeon_cs_packet *pkt)
760 volatile uint32_t *ib;
766 for (i = 0; i <= (pkt->count + 1); i++, idx++)
767 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
771 * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet
772 * @parser: parser structure holding parsing context.
773 * @data: pointer to relocation data
774 * @offset_start: starting offset
775 * @offset_mask: offset mask (to align start offset on)
776 * @reloc: reloc informations
778 * Check if next packet is relocation packet3, do bo validation and compute
779 * GPU offset using the provided start.
781 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
782 struct radeon_cs_reloc **cs_reloc,
785 struct radeon_cs_chunk *relocs_chunk;
786 struct radeon_cs_packet p3reloc;
790 if (p->chunk_relocs_idx == -1) {
791 DRM_ERROR("No relocation chunk !\n");
795 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
796 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
799 p->idx += p3reloc.count + 2;
800 if (p3reloc.type != RADEON_PACKET_TYPE3 ||
801 p3reloc.opcode != RADEON_PACKET3_NOP) {
802 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
804 radeon_cs_dump_packet(p, &p3reloc);
807 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
808 if (idx >= relocs_chunk->length_dw) {
809 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
810 idx, relocs_chunk->length_dw);
811 radeon_cs_dump_packet(p, &p3reloc);
814 /* FIXME: we assume reloc size is 4 dwords */
816 *cs_reloc = p->relocs;
817 (*cs_reloc)->lobj.gpu_offset =
818 (u64)relocs_chunk->kdata[idx + 3] << 32;
819 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
821 *cs_reloc = p->relocs_ptr[(idx / 4)];