1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi_drm/i915_drm.h>
34 #include <uapi_drm/drm_fourcc.h>
37 #include "i915_params.h"
39 #include "intel_bios.h"
40 #include "intel_ringbuffer.h"
41 #include "intel_lrc.h"
42 #include "i915_gem_gtt.h"
43 #include "i915_gem_render_state.h"
44 #include <linux/io-mapping.h>
45 #include <linux/i2c.h>
46 #include <linux/i2c-algo-bit.h>
47 #include <drm/intel-gtt.h>
48 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49 #include <drm/drm_gem.h>
50 #include <linux/backlight.h>
51 #include <linux/hashtable.h>
52 #include <linux/kref.h>
53 #include <linux/kconfig.h>
54 #include <linux/pm_qos.h>
55 #include <linux/delay.h>
56 #include "intel_guc.h"
58 #define CONFIG_DRM_FBDEV_EMULATION 1
59 #define CONFIG_DRM_I915_KMS 1
60 #define CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT 1
64 /* General customization:
67 #define DRIVER_NAME "i915"
68 #define DRIVER_DESC "Intel Graphics"
69 #define DRIVER_DATE "20160229"
72 /* Many gcc seem to no see through this and fall over :( */
74 #define WARN_ON(x) ({ \
75 bool __i915_warn_cond = (x); \
76 if (__builtin_constant_p(__i915_warn_cond)) \
77 BUILD_BUG_ON(__i915_warn_cond); \
78 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
80 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
84 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
86 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
87 (long) (x), __func__);
89 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
90 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
91 * which may not necessarily be a user visible problem. This will either
92 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
93 * enable distros and users to tailor their preferred amount of i915 abrt
96 #define I915_STATE_WARN(condition, format...) ({ \
97 int __ret_warn_on = !!(condition); \
98 if (unlikely(__ret_warn_on)) \
99 if (!WARN(i915.verbose_state_checks, format)) \
101 unlikely(__ret_warn_on); \
104 #define I915_STATE_WARN_ON(x) \
105 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
107 static inline const char *yesno(bool v)
109 return v ? "yes" : "no";
112 static inline const char *onoff(bool v)
114 return v ? "on" : "off";
123 I915_MAX_PIPES = _PIPE_EDP
125 #define pipe_name(p) ((p) + 'A')
134 #define transcoder_name(t) ((t) + 'A')
137 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
138 * number of planes per CRTC. Not all platforms really have this many planes,
139 * which means some arrays of size I915_MAX_PLANES may have unused entries
140 * between the topmost sprite plane and the cursor plane.
149 #define plane_name(p) ((p) + 'A')
151 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
161 #define port_name(p) ((p) + 'A')
163 #define I915_NUM_PHYS_VLV 2
175 enum intel_display_power_domain {
179 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
180 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
181 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
182 POWER_DOMAIN_TRANSCODER_A,
183 POWER_DOMAIN_TRANSCODER_B,
184 POWER_DOMAIN_TRANSCODER_C,
185 POWER_DOMAIN_TRANSCODER_EDP,
186 POWER_DOMAIN_PORT_DDI_A_LANES,
187 POWER_DOMAIN_PORT_DDI_B_LANES,
188 POWER_DOMAIN_PORT_DDI_C_LANES,
189 POWER_DOMAIN_PORT_DDI_D_LANES,
190 POWER_DOMAIN_PORT_DDI_E_LANES,
191 POWER_DOMAIN_PORT_DSI,
192 POWER_DOMAIN_PORT_CRT,
193 POWER_DOMAIN_PORT_OTHER,
202 POWER_DOMAIN_MODESET,
208 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
209 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
210 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
211 #define POWER_DOMAIN_TRANSCODER(tran) \
212 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
213 (tran) + POWER_DOMAIN_TRANSCODER_A)
217 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
229 #define for_each_hpd_pin(__pin) \
230 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
232 struct i915_hotplug {
233 struct work_struct hotplug_work;
236 unsigned long last_jiffies;
241 HPD_MARK_DISABLED = 2
243 } stats[HPD_NUM_PINS];
245 struct delayed_work reenable_work;
247 struct intel_digital_port *irq_port[I915_MAX_PORTS];
250 struct work_struct dig_port_work;
253 * if we get a HPD irq from DP and a HPD irq from non-DP
254 * the non-DP HPD could block the workqueue on a mode config
255 * mutex getting, that userspace may have taken. However
256 * userspace is waiting on the DP workqueue to run which is
257 * blocked behind the non-DP one.
259 struct workqueue_struct *dp_wq;
262 #define I915_GEM_GPU_DOMAINS \
263 (I915_GEM_DOMAIN_RENDER | \
264 I915_GEM_DOMAIN_SAMPLER | \
265 I915_GEM_DOMAIN_COMMAND | \
266 I915_GEM_DOMAIN_INSTRUCTION | \
267 I915_GEM_DOMAIN_VERTEX)
269 #define for_each_pipe(__dev_priv, __p) \
270 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
271 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
272 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
273 for_each_if ((__mask) & (1 << (__p)))
274 #define for_each_plane(__dev_priv, __pipe, __p) \
276 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
278 #define for_each_sprite(__dev_priv, __p, __s) \
280 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
283 #define for_each_crtc(dev, crtc) \
284 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
286 #define for_each_intel_plane(dev, intel_plane) \
287 list_for_each_entry(intel_plane, \
288 &dev->mode_config.plane_list, \
291 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
292 list_for_each_entry(intel_plane, \
293 &(dev)->mode_config.plane_list, \
295 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
297 #define for_each_intel_crtc(dev, intel_crtc) \
298 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
300 #define for_each_intel_encoder(dev, intel_encoder) \
301 list_for_each_entry(intel_encoder, \
302 &(dev)->mode_config.encoder_list, \
305 #define for_each_intel_connector(dev, intel_connector) \
306 list_for_each_entry(intel_connector, \
307 &dev->mode_config.connector_list, \
310 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
311 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
312 for_each_if ((intel_encoder)->base.crtc == (__crtc))
314 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
315 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
316 for_each_if ((intel_connector)->base.encoder == (__encoder))
318 #define for_each_power_domain(domain, mask) \
319 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
320 for_each_if ((1 << (domain)) & (mask))
322 struct drm_i915_private;
323 struct i915_mm_struct;
324 struct i915_mmu_object;
326 struct drm_i915_file_private {
327 struct drm_i915_private *dev_priv;
328 struct drm_file *file;
331 struct spinlock lock;
332 struct list_head request_list;
333 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
334 * chosen to prevent the CPU getting more than a frame ahead of the GPU
335 * (when using lax throttling for the frontbuffer). We also use it to
336 * offer free GPU waitboosts for severely congested workloads.
338 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
340 struct idr context_idr;
342 struct intel_rps_client {
343 struct list_head link;
347 unsigned int bsd_ring;
351 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
352 /* real shared dpll ids must be >= 0 */
353 DPLL_ID_PCH_PLL_A = 0,
354 DPLL_ID_PCH_PLL_B = 1,
361 DPLL_ID_SKL_DPLL1 = 0,
362 DPLL_ID_SKL_DPLL2 = 1,
363 DPLL_ID_SKL_DPLL3 = 2,
365 #define I915_NUM_PLLS 3
367 struct intel_dpll_hw_state {
380 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
381 * lower part of ctrl1 and they get shifted into position when writing
382 * the register. This allows us to easily compare the state to share
386 /* HDMI only, 0 when used for DP */
387 uint32_t cfgcr1, cfgcr2;
390 uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
394 struct intel_shared_dpll_config {
395 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
396 struct intel_dpll_hw_state hw_state;
399 struct intel_shared_dpll {
400 struct intel_shared_dpll_config config;
402 int active; /* count of number of active CRTCs (i.e. DPMS on) */
403 bool on; /* is the PLL actually active? Disabled during modeset */
405 /* should match the index in the dev_priv->shared_dplls array */
406 enum intel_dpll_id id;
407 /* The mode_set hook is optional and should be used together with the
408 * intel_prepare_shared_dpll function. */
409 void (*mode_set)(struct drm_i915_private *dev_priv,
410 struct intel_shared_dpll *pll);
411 void (*enable)(struct drm_i915_private *dev_priv,
412 struct intel_shared_dpll *pll);
413 void (*disable)(struct drm_i915_private *dev_priv,
414 struct intel_shared_dpll *pll);
415 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
416 struct intel_shared_dpll *pll,
417 struct intel_dpll_hw_state *hw_state);
425 /* Used by dp and fdi links */
426 struct intel_link_m_n {
434 void intel_link_compute_m_n(int bpp, int nlanes,
435 int pixel_clock, int link_clock,
436 struct intel_link_m_n *m_n);
438 /* Interface history:
441 * 1.2: Add Power Management
442 * 1.3: Add vblank support
443 * 1.4: Fix cmdbuffer path, add heap destroy
444 * 1.5: Add vblank pipe configuration
445 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
446 * - Support vertical blank on secondary display pipe
448 #define DRIVER_MAJOR 1
449 #define DRIVER_MINOR 6
450 #define DRIVER_PATCHLEVEL 0
452 #define WATCH_LISTS 0
454 struct opregion_header;
455 struct opregion_acpi;
456 struct opregion_swsci;
457 struct opregion_asle;
459 struct intel_opregion {
460 struct opregion_header *header;
461 struct opregion_acpi *acpi;
462 struct opregion_swsci *swsci;
463 u32 swsci_gbda_sub_functions;
464 u32 swsci_sbcb_sub_functions;
465 struct opregion_asle *asle;
470 struct work_struct asle_work;
472 #define OPREGION_SIZE (8*1024)
474 struct intel_overlay;
475 struct intel_overlay_error_state;
477 #define I915_FENCE_REG_NONE -1
478 #define I915_MAX_NUM_FENCES 32
479 /* 32 fences + sign bit for FENCE_REG_NONE */
480 #define I915_MAX_NUM_FENCE_BITS 6
482 struct drm_i915_fence_reg {
483 struct list_head lru_list;
484 struct drm_i915_gem_object *obj;
488 struct sdvo_device_mapping {
497 struct intel_display_error_state;
499 struct drm_i915_error_state {
508 /* Generic register state */
516 u32 error; /* gen6+ */
517 u32 err_int; /* gen7 */
518 u32 fault_data0; /* gen8, gen9 */
519 u32 fault_data1; /* gen8, gen9 */
525 u32 extra_instdone[I915_NUM_INSTDONE_REG];
526 u64 fence[I915_MAX_NUM_FENCES];
527 struct intel_overlay_error_state *overlay;
528 struct intel_display_error_state *display;
529 struct drm_i915_error_object *semaphore_obj;
531 struct drm_i915_error_ring {
533 /* Software tracked state */
536 enum intel_ring_hangcheck_action hangcheck_action;
539 /* our own tracking of ring head and tail */
543 u32 semaphore_seqno[I915_NUM_RINGS - 1];
562 u32 rc_psmi; /* sleep state */
563 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
565 struct drm_i915_error_object {
569 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
571 struct drm_i915_error_request {
586 char comm[TASK_COMM_LEN];
587 } ring[I915_NUM_RINGS];
589 struct drm_i915_error_buffer {
592 u32 rseqno[I915_NUM_RINGS], wseqno;
596 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
604 } **active_bo, **pinned_bo;
606 u32 *active_bo_count, *pinned_bo_count;
610 struct intel_connector;
611 struct intel_encoder;
612 struct intel_crtc_state;
613 struct intel_initial_plane_config;
618 struct drm_i915_display_funcs {
619 int (*get_display_clock_speed)(struct drm_device *dev);
620 int (*get_fifo_size)(struct drm_device *dev, int plane);
622 * find_dpll() - Find the best values for the PLL
623 * @limit: limits for the PLL
624 * @crtc: current CRTC
625 * @target: target frequency in kHz
626 * @refclk: reference clock frequency in kHz
627 * @match_clock: if provided, @best_clock P divider must
628 * match the P divider from @match_clock
629 * used for LVDS downclocking
630 * @best_clock: best PLL values found
632 * Returns true on success, false on failure.
634 bool (*find_dpll)(const struct intel_limit *limit,
635 struct intel_crtc_state *crtc_state,
636 int target, int refclk,
637 struct dpll *match_clock,
638 struct dpll *best_clock);
639 int (*compute_pipe_wm)(struct intel_crtc *crtc,
640 struct drm_atomic_state *state);
641 void (*program_watermarks)(struct intel_crtc_state *cstate);
642 void (*update_wm)(struct drm_crtc *crtc);
643 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
644 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
645 /* Returns the active state of the crtc, and if the crtc is active,
646 * fills out the pipe-config with the hw state. */
647 bool (*get_pipe_config)(struct intel_crtc *,
648 struct intel_crtc_state *);
649 void (*get_initial_plane_config)(struct intel_crtc *,
650 struct intel_initial_plane_config *);
651 int (*crtc_compute_clock)(struct intel_crtc *crtc,
652 struct intel_crtc_state *crtc_state);
653 void (*crtc_enable)(struct drm_crtc *crtc);
654 void (*crtc_disable)(struct drm_crtc *crtc);
655 void (*audio_codec_enable)(struct drm_connector *connector,
656 struct intel_encoder *encoder,
657 const struct drm_display_mode *adjusted_mode);
658 void (*audio_codec_disable)(struct intel_encoder *encoder);
659 void (*fdi_link_train)(struct drm_crtc *crtc);
660 void (*init_clock_gating)(struct drm_device *dev);
661 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
662 struct drm_framebuffer *fb,
663 struct drm_i915_gem_object *obj,
664 struct drm_i915_gem_request *req,
666 void (*hpd_irq_setup)(struct drm_device *dev);
667 /* clock updates for mode set */
669 /* render clock increase/decrease */
670 /* display clock increase/decrease */
671 /* pll clock increase/decrease */
674 enum forcewake_domain_id {
675 FW_DOMAIN_ID_RENDER = 0,
676 FW_DOMAIN_ID_BLITTER,
682 enum forcewake_domains {
683 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
684 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
685 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
686 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
691 struct intel_uncore_funcs {
692 void (*force_wake_get)(struct drm_i915_private *dev_priv,
693 enum forcewake_domains domains);
694 void (*force_wake_put)(struct drm_i915_private *dev_priv,
695 enum forcewake_domains domains);
697 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
698 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
699 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
700 u64 (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
702 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
703 uint8_t val, bool trace);
704 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
705 uint16_t val, bool trace);
706 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
707 uint32_t val, bool trace);
708 void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,
709 u64 val, bool trace);
712 struct intel_uncore {
713 struct lock lock; /** lock is also taken in irq contexts. */
715 struct intel_uncore_funcs funcs;
718 enum forcewake_domains fw_domains;
720 struct intel_uncore_forcewake_domain {
721 struct drm_i915_private *i915;
722 enum forcewake_domain_id id;
724 struct timer_list timer;
731 } fw_domain[FW_DOMAIN_ID_COUNT];
733 int unclaimed_mmio_check;
736 /* Iterate over initialised fw domains */
737 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
738 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
739 (i__) < FW_DOMAIN_ID_COUNT; \
740 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
741 for_each_if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
743 #define for_each_fw_domain(domain__, dev_priv__, i__) \
744 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
746 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
747 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
748 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
751 struct work_struct work;
753 uint32_t *dmc_payload;
754 uint32_t dmc_fw_size;
757 i915_reg_t mmioaddr[8];
758 uint32_t mmiodata[8];
762 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
763 func(is_mobile) sep \
766 func(is_i945gm) sep \
768 func(need_gfx_hws) sep \
770 func(is_pineview) sep \
771 func(is_broadwater) sep \
772 func(is_crestline) sep \
773 func(is_ivybridge) sep \
774 func(is_valleyview) sep \
775 func(is_cherryview) sep \
776 func(is_haswell) sep \
777 func(is_skylake) sep \
778 func(is_broxton) sep \
779 func(is_kabylake) sep \
780 func(is_preliminary) sep \
782 func(has_pipe_cxsr) sep \
783 func(has_hotplug) sep \
784 func(cursor_needs_physical) sep \
785 func(has_overlay) sep \
786 func(overlay_needs_physical) sep \
787 func(supports_tv) sep \
792 #define DEFINE_FLAG(name) u8 name:1
793 #define SEP_SEMICOLON ;
795 struct intel_device_info {
796 u32 display_mmio_offset;
799 u8 num_sprites[I915_MAX_PIPES];
801 u8 ring_mask; /* Rings supported by the HW */
802 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
803 /* Register offsets for the various display pipes and transcoders */
804 int pipe_offsets[I915_MAX_TRANSCODERS];
805 int trans_offsets[I915_MAX_TRANSCODERS];
806 int palette_offsets[I915_MAX_PIPES];
807 int cursor_offsets[I915_MAX_PIPES];
809 /* Slice/subslice/EU info */
812 u8 subslice_per_slice;
815 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
818 u8 has_subslice_pg:1;
825 enum i915_cache_level {
827 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
828 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
829 caches, eg sampler/render caches, and the
830 large Last-Level-Cache. LLC is coherent with
831 the CPU, but L3 is only visible to the GPU. */
832 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
835 struct i915_ctx_hang_stats {
836 /* This context had batch pending when hang was declared */
837 unsigned batch_pending;
839 /* This context had batch active when hang was declared */
840 unsigned batch_active;
842 /* Time when this context was last blamed for a GPU reset */
843 unsigned long guilty_ts;
845 /* If the contexts causes a second GPU hang within this time,
846 * it is permanently banned from submitting any more work.
848 unsigned long ban_period_seconds;
850 /* This context is banned to submit more work */
854 /* This must match up with the value previously used for execbuf2.rsvd1. */
855 #define DEFAULT_CONTEXT_HANDLE 0
857 #define CONTEXT_NO_ZEROMAP (1<<0)
859 * struct intel_context - as the name implies, represents a context.
860 * @ref: reference count.
861 * @user_handle: userspace tracking identity for this context.
862 * @remap_slice: l3 row remapping information.
863 * @flags: context specific flags:
864 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
865 * @file_priv: filp associated with this context (NULL for global default
867 * @hang_stats: information about the role of this context in possible GPU
869 * @ppgtt: virtual memory space used by this context.
870 * @legacy_hw_ctx: render context backing object and whether it is correctly
871 * initialized (legacy ring submission mechanism only).
872 * @link: link in the global list of contexts.
874 * Contexts are memory images used by the hardware to store copies of their
877 struct intel_context {
881 struct drm_i915_private *i915;
883 struct drm_i915_file_private *file_priv;
884 struct i915_ctx_hang_stats hang_stats;
885 struct i915_hw_ppgtt *ppgtt;
887 /* Legacy ring buffer submission */
889 struct drm_i915_gem_object *rcs_state;
895 struct drm_i915_gem_object *state;
896 struct intel_ringbuffer *ringbuf;
898 struct i915_vma *lrc_vma;
900 uint32_t *lrc_reg_state;
901 } engine[I915_NUM_RINGS];
903 struct list_head link;
915 /* This is always the inner lock when overlapping with struct_mutex and
916 * it's the outer lock when overlapping with stolen_lock. */
919 unsigned int possible_framebuffer_bits;
920 unsigned int busy_bits;
921 unsigned int visible_pipes_mask;
922 struct intel_crtc *crtc;
924 struct drm_mm_node compressed_fb;
925 struct drm_mm_node *compressed_llb;
932 struct intel_fbc_state_cache {
934 unsigned int mode_flags;
935 uint32_t hsw_bdw_pixel_rate;
939 unsigned int rotation;
947 uint32_t pixel_format;
950 unsigned int tiling_mode;
954 struct intel_fbc_reg_params {
958 unsigned int fence_y_offset;
963 uint32_t pixel_format;
971 struct intel_fbc_work {
973 u32 scheduled_vblank;
974 struct work_struct work;
977 const char *no_fbc_reason;
981 * HIGH_RR is the highest eDP panel refresh rate read from EDID
982 * LOW_RR is the lowest eDP panel refresh rate found from EDID
983 * parsing for same resolution.
985 enum drrs_refresh_rate_type {
988 DRRS_MAX_RR, /* RR count */
991 enum drrs_support_type {
992 DRRS_NOT_SUPPORTED = 0,
993 STATIC_DRRS_SUPPORT = 1,
994 SEAMLESS_DRRS_SUPPORT = 2
1000 struct delayed_work work;
1001 struct intel_dp *dp;
1002 unsigned busy_frontbuffer_bits;
1003 enum drrs_refresh_rate_type refresh_rate_type;
1004 enum drrs_support_type type;
1011 struct intel_dp *enabled;
1013 struct delayed_work work;
1014 unsigned busy_frontbuffer_bits;
1016 bool aux_frame_sync;
1021 PCH_NONE = 0, /* No PCH present */
1022 PCH_IBX, /* Ibexpeak PCH */
1023 PCH_CPT, /* Cougarpoint PCH */
1024 PCH_LPT, /* Lynxpoint PCH */
1025 PCH_SPT, /* Sunrisepoint PCH */
1029 enum intel_sbi_destination {
1034 #define QUIRK_PIPEA_FORCE (1<<0)
1035 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1036 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1037 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1038 #define QUIRK_PIPEB_FORCE (1<<4)
1039 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1042 struct intel_fbc_work;
1044 struct intel_gmbus {
1045 struct i2c_adapter adapter;
1048 i915_reg_t gpio_reg;
1049 struct i2c_algo_bit_data bit_algo;
1050 struct drm_i915_private *dev_priv;
1053 struct i915_suspend_saved_registers {
1056 u32 savePP_ON_DELAYS;
1057 u32 savePP_OFF_DELAYS;
1062 u32 saveFBC_CONTROL;
1063 u32 saveCACHE_MODE_0;
1064 u32 saveMI_ARB_STATE;
1068 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1069 u32 savePCH_PORT_HOTPLUG;
1073 struct vlv_s0ix_state {
1080 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1081 u32 media_max_req_count;
1082 u32 gfx_max_req_count;
1108 u32 rp_down_timeout;
1114 /* Display 1 CZ domain */
1119 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1121 /* GT SA CZ domain */
1128 /* Display 2 CZ domain */
1132 u32 clock_gate_dis2;
1135 struct intel_rps_ei {
1141 struct intel_gen6_power_mgmt {
1143 * work, interrupts_enabled and pm_iir are protected by
1144 * dev_priv->irq_lock
1146 struct work_struct work;
1147 bool interrupts_enabled;
1150 /* Frequencies are stored in potentially platform dependent multiples.
1151 * In other words, *_freq needs to be multiplied by X to be interesting.
1152 * Soft limits are those which are used for the dynamic reclocking done
1153 * by the driver (raise frequencies under heavy loads, and lower for
1154 * lighter loads). Hard limits are those imposed by the hardware.
1156 * A distinction is made for overclocking, which is never enabled by
1157 * default, and is considered to be above the hard limit if it's
1160 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1161 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1162 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1163 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1164 u8 min_freq; /* AKA RPn. Minimum frequency */
1165 u8 idle_freq; /* Frequency to request when we are idle */
1166 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1167 u8 rp1_freq; /* "less than" RP0 power/freqency */
1168 u8 rp0_freq; /* Non-overclocked max frequency. */
1170 u8 up_threshold; /* Current %busy required to uplock */
1171 u8 down_threshold; /* Current %busy required to downclock */
1174 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1176 struct lock client_lock;
1177 struct list_head clients;
1181 struct delayed_work delayed_resume_work;
1184 struct intel_rps_client semaphores, mmioflips;
1186 /* manual wa residency calculations */
1187 struct intel_rps_ei up_ei, down_ei;
1190 * Protects RPS/RC6 register access and PCU communication.
1191 * Must be taken after struct_mutex if nested. Note that
1192 * this lock may be held for long periods of time when
1193 * talking to hw - so only take it when talking to hw!
1195 struct lock hw_lock;
1198 /* defined intel_pm.c */
1199 extern struct lock mchdev_lock;
1201 struct intel_ilk_power_mgmt {
1209 unsigned long last_time1;
1210 unsigned long chipset_power;
1213 unsigned long gfx_power;
1220 struct drm_i915_private;
1221 struct i915_power_well;
1223 struct i915_power_well_ops {
1225 * Synchronize the well's hw state to match the current sw state, for
1226 * example enable/disable it based on the current refcount. Called
1227 * during driver init and resume time, possibly after first calling
1228 * the enable/disable handlers.
1230 void (*sync_hw)(struct drm_i915_private *dev_priv,
1231 struct i915_power_well *power_well);
1233 * Enable the well and resources that depend on it (for example
1234 * interrupts located on the well). Called after the 0->1 refcount
1237 void (*enable)(struct drm_i915_private *dev_priv,
1238 struct i915_power_well *power_well);
1240 * Disable the well and resources that depend on it. Called after
1241 * the 1->0 refcount transition.
1243 void (*disable)(struct drm_i915_private *dev_priv,
1244 struct i915_power_well *power_well);
1245 /* Returns the hw enabled state. */
1246 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1247 struct i915_power_well *power_well);
1250 /* Power well structure for haswell */
1251 struct i915_power_well {
1254 /* power well enable/disable usage count */
1256 /* cached hw enabled state */
1258 unsigned long domains;
1260 const struct i915_power_well_ops *ops;
1263 struct i915_power_domains {
1265 * Power wells needed for initialization at driver init and suspend
1266 * time are on. They are kept on until after the first modeset.
1270 int power_well_count;
1273 int domain_use_count[POWER_DOMAIN_NUM];
1274 struct i915_power_well *power_wells;
1277 #define MAX_L3_SLICES 2
1278 struct intel_l3_parity {
1279 u32 *remap_info[MAX_L3_SLICES];
1280 struct work_struct error_work;
1284 struct i915_gem_mm {
1285 /** Memory allocator for GTT stolen memory */
1286 struct drm_mm stolen;
1287 /** Protects the usage of the GTT stolen memory allocator. This is
1288 * always the inner lock when overlapping with struct_mutex. */
1289 struct lock stolen_lock;
1291 /** List of all objects in gtt_space. Used to restore gtt
1292 * mappings on resume */
1293 struct list_head bound_list;
1295 * List of objects which are not bound to the GTT (thus
1296 * are idle and not used by the GPU) but still have
1297 * (presumably uncached) pages still attached.
1299 struct list_head unbound_list;
1301 /** Usable portion of the GTT for GEM */
1302 unsigned long stolen_base; /* limited to low memory (32-bit) */
1304 /** PPGTT used for aliasing the PPGTT with the GTT */
1305 struct i915_hw_ppgtt *aliasing_ppgtt;
1307 struct notifier_block oom_notifier;
1309 struct shrinker shrinker;
1311 bool shrinker_no_lock_stealing;
1313 /** LRU list of objects with fence regs on them. */
1314 struct list_head fence_list;
1317 * We leave the user IRQ off as much as possible,
1318 * but this means that requests will finish and never
1319 * be retired once the system goes idle. Set a timer to
1320 * fire periodically while the ring is running. When it
1321 * fires, go retire requests.
1323 struct delayed_work retire_work;
1326 * When we detect an idle GPU, we want to turn on
1327 * powersaving features. So once we see that there
1328 * are no more requests outstanding and no more
1329 * arrive within a small period of time, we fire
1330 * off the idle_work.
1332 struct delayed_work idle_work;
1335 * Are we in a non-interruptible section of code like
1341 * Is the GPU currently considered idle, or busy executing userspace
1342 * requests? Whilst idle, we attempt to power down the hardware and
1343 * display clocks. In order to reduce the effect on performance, there
1344 * is a slight delay before we do so.
1348 /* the indicator for dispatch video commands on two BSD rings */
1349 unsigned int bsd_ring_dispatch_index;
1351 /** Bit 6 swizzling required for X tiling */
1352 uint32_t bit_6_swizzle_x;
1353 /** Bit 6 swizzling required for Y tiling */
1354 uint32_t bit_6_swizzle_y;
1356 /* accounting, useful for userland debugging */
1357 struct spinlock object_stat_lock;
1358 size_t object_memory;
1362 struct drm_i915_error_state_buf {
1363 struct drm_i915_private *i915;
1372 struct i915_error_state_file_priv {
1373 struct drm_device *dev;
1374 struct drm_i915_error_state *error;
1377 struct i915_gpu_error {
1378 /* For hangcheck timer */
1379 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1380 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1381 /* Hang gpu twice in this window and your context gets banned */
1382 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1384 struct workqueue_struct *hangcheck_wq;
1385 struct delayed_work hangcheck_work;
1387 /* For reset and error_state handling. */
1389 /* Protected by the above dev->gpu_error.lock. */
1390 struct drm_i915_error_state *first_error;
1392 unsigned long missed_irq_rings;
1395 * State variable controlling the reset flow and count
1397 * This is a counter which gets incremented when reset is triggered,
1398 * and again when reset has been handled. So odd values (lowest bit set)
1399 * means that reset is in progress and even values that
1400 * (reset_counter >> 1):th reset was successfully completed.
1402 * If reset is not completed succesfully, the I915_WEDGE bit is
1403 * set meaning that hardware is terminally sour and there is no
1404 * recovery. All waiters on the reset_queue will be woken when
1407 * This counter is used by the wait_seqno code to notice that reset
1408 * event happened and it needs to restart the entire ioctl (since most
1409 * likely the seqno it waited for won't ever signal anytime soon).
1411 * This is important for lock-free wait paths, where no contended lock
1412 * naturally enforces the correct ordering between the bail-out of the
1413 * waiter and the gpu reset work code.
1415 atomic_t reset_counter;
1417 #define I915_RESET_IN_PROGRESS_FLAG 1
1418 #define I915_WEDGED (1 << 31)
1421 * Waitqueue to signal when the reset has completed. Used by clients
1422 * that wait for dev_priv->mm.wedged to settle.
1424 wait_queue_head_t reset_queue;
1426 /* Userspace knobs for gpu hang simulation;
1427 * combines both a ring mask, and extra flags
1430 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1431 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1433 /* For missed irq/seqno simulation. */
1434 unsigned int test_irq_rings;
1436 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1437 bool reload_in_reset;
1440 enum modeset_restore {
1441 MODESET_ON_LID_OPEN,
1446 #define DP_AUX_A 0x40
1447 #define DP_AUX_B 0x10
1448 #define DP_AUX_C 0x20
1449 #define DP_AUX_D 0x30
1451 #define DDC_PIN_B 0x05
1452 #define DDC_PIN_C 0x04
1453 #define DDC_PIN_D 0x06
1455 struct ddi_vbt_port_info {
1457 * This is an index in the HDMI/DVI DDI buffer translation table.
1458 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1459 * populate this field.
1461 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1462 uint8_t hdmi_level_shift;
1464 uint8_t supports_dvi:1;
1465 uint8_t supports_hdmi:1;
1466 uint8_t supports_dp:1;
1468 uint8_t alternate_aux_channel;
1469 uint8_t alternate_ddc_pin;
1471 uint8_t dp_boost_level;
1472 uint8_t hdmi_boost_level;
1475 enum psr_lines_to_wait {
1476 PSR_0_LINES_TO_WAIT = 0,
1478 PSR_4_LINES_TO_WAIT,
1482 struct intel_vbt_data {
1483 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1484 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1487 unsigned int int_tv_support:1;
1488 unsigned int lvds_dither:1;
1489 unsigned int lvds_vbt:1;
1490 unsigned int int_crt_support:1;
1491 unsigned int lvds_use_ssc:1;
1492 unsigned int display_clock_mode:1;
1493 unsigned int fdi_rx_polarity_inverted:1;
1494 unsigned int has_mipi:1;
1496 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1498 enum drrs_support_type drrs_type;
1503 int edp_preemphasis;
1505 bool edp_initialized;
1508 struct edp_power_seq edp_pps;
1512 bool require_aux_wakeup;
1514 enum psr_lines_to_wait lines_to_wait;
1515 int tp1_wakeup_time;
1516 int tp2_tp3_wakeup_time;
1522 bool active_low_pwm;
1523 u8 min_brightness; /* min_brightness/255 of max */
1530 struct mipi_config *config;
1531 struct mipi_pps_data *pps;
1535 const u8 *sequence[MIPI_SEQ_MAX];
1541 union child_device_config *child_dev;
1543 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1546 enum intel_ddb_partitioning {
1548 INTEL_DDB_PART_5_6, /* IVB+ */
1551 struct intel_wm_level {
1559 struct ilk_wm_values {
1560 uint32_t wm_pipe[3];
1562 uint32_t wm_lp_spr[3];
1563 uint32_t wm_linetime[3];
1565 enum intel_ddb_partitioning partitioning;
1568 struct vlv_pipe_wm {
1579 struct vlv_wm_values {
1580 struct vlv_pipe_wm pipe[3];
1581 struct vlv_sr_wm sr;
1591 struct skl_ddb_entry {
1592 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1595 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1597 return entry->end - entry->start;
1600 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1601 const struct skl_ddb_entry *e2)
1603 if (e1->start == e2->start && e1->end == e2->end)
1609 struct skl_ddb_allocation {
1610 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1611 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1612 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1615 struct skl_wm_values {
1616 bool dirty[I915_MAX_PIPES];
1617 struct skl_ddb_allocation ddb;
1618 uint32_t wm_linetime[I915_MAX_PIPES];
1619 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1620 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1623 struct skl_wm_level {
1624 bool plane_en[I915_MAX_PLANES];
1625 uint16_t plane_res_b[I915_MAX_PLANES];
1626 uint8_t plane_res_l[I915_MAX_PLANES];
1630 * This struct helps tracking the state needed for runtime PM, which puts the
1631 * device in PCI D3 state. Notice that when this happens, nothing on the
1632 * graphics device works, even register access, so we don't get interrupts nor
1635 * Every piece of our code that needs to actually touch the hardware needs to
1636 * either call intel_runtime_pm_get or call intel_display_power_get with the
1637 * appropriate power domain.
1639 * Our driver uses the autosuspend delay feature, which means we'll only really
1640 * suspend if we stay with zero refcount for a certain amount of time. The
1641 * default value is currently very conservative (see intel_runtime_pm_enable), but
1642 * it can be changed with the standard runtime PM files from sysfs.
1644 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1645 * goes back to false exactly before we reenable the IRQs. We use this variable
1646 * to check if someone is trying to enable/disable IRQs while they're supposed
1647 * to be disabled. This shouldn't happen and we'll print some error messages in
1650 * For more, read the Documentation/power/runtime_pm.txt.
1652 struct i915_runtime_pm {
1653 atomic_t wakeref_count;
1654 atomic_t atomic_seq;
1659 enum intel_pipe_crc_source {
1660 INTEL_PIPE_CRC_SOURCE_NONE,
1661 INTEL_PIPE_CRC_SOURCE_PLANE1,
1662 INTEL_PIPE_CRC_SOURCE_PLANE2,
1663 INTEL_PIPE_CRC_SOURCE_PF,
1664 INTEL_PIPE_CRC_SOURCE_PIPE,
1665 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1666 INTEL_PIPE_CRC_SOURCE_TV,
1667 INTEL_PIPE_CRC_SOURCE_DP_B,
1668 INTEL_PIPE_CRC_SOURCE_DP_C,
1669 INTEL_PIPE_CRC_SOURCE_DP_D,
1670 INTEL_PIPE_CRC_SOURCE_AUTO,
1671 INTEL_PIPE_CRC_SOURCE_MAX,
1674 struct intel_pipe_crc_entry {
1679 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1680 struct intel_pipe_crc {
1681 struct spinlock lock;
1682 bool opened; /* exclusive access to the result file */
1683 struct intel_pipe_crc_entry *entries;
1684 enum intel_pipe_crc_source source;
1686 wait_queue_head_t wq;
1689 struct i915_frontbuffer_tracking {
1693 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1700 struct i915_wa_reg {
1703 /* bitmask representing WA bits */
1708 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1709 * allowing it for RCS as we don't foresee any requirement of having
1710 * a whitelist for other engines. When it is really required for
1711 * other engines then the limit need to be increased.
1713 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1715 struct i915_workarounds {
1716 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1718 u32 hw_whitelist_count[I915_NUM_RINGS];
1721 struct i915_virtual_gpu {
1725 struct i915_execbuffer_params {
1726 struct drm_device *dev;
1727 struct drm_file *file;
1728 uint32_t dispatch_flags;
1729 uint32_t args_batch_start_offset;
1730 uint64_t batch_obj_vm_offset;
1731 struct intel_engine_cs *ring;
1732 struct drm_i915_gem_object *batch_obj;
1733 struct intel_context *ctx;
1734 struct drm_i915_gem_request *request;
1737 /* used in computing the new watermarks state */
1738 struct intel_wm_config {
1739 unsigned int num_pipes_active;
1740 bool sprites_enabled;
1741 bool sprites_scaled;
1744 struct drm_i915_private {
1745 struct drm_device *dev;
1746 struct kmem_cache *objects;
1747 struct kmem_cache *vmas;
1748 struct kmem_cache *requests;
1750 struct intel_device_info info;
1752 int relative_constants_mode;
1756 struct intel_uncore uncore;
1758 struct i915_virtual_gpu vgpu;
1760 struct intel_guc guc;
1762 struct intel_csr csr;
1764 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1766 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1767 * controller on different i2c buses. */
1768 struct lock gmbus_mutex;
1771 * Base address of the gmbus and gpio block.
1773 uint32_t gpio_mmio_base;
1775 /* MMIO base address for MIPI regs */
1776 uint32_t mipi_mmio_base;
1778 uint32_t psr_mmio_base;
1780 wait_queue_head_t gmbus_wait_queue;
1782 struct pci_dev *bridge_dev;
1783 struct intel_engine_cs ring[I915_NUM_RINGS];
1784 struct drm_i915_gem_object *semaphore_obj;
1785 uint32_t last_seqno, next_seqno;
1787 struct drm_dma_handle *status_page_dmah;
1788 struct resource *mch_res;
1791 /* protects the irq masks */
1792 struct lock irq_lock;
1794 /* protects the mmio flip data */
1795 struct spinlock mmio_flip_lock;
1797 bool display_irqs_enabled;
1799 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1800 struct pm_qos_request pm_qos;
1802 /* Sideband mailbox protection */
1803 struct lock sb_lock;
1805 /** Cached value of IMR to avoid reads in updating the bitfield */
1808 u32 de_irq_mask[I915_MAX_PIPES];
1813 u32 pipestat_irq_mask[I915_MAX_PIPES];
1815 struct i915_hotplug hotplug;
1816 struct intel_fbc fbc;
1817 struct i915_drrs drrs;
1818 struct intel_opregion opregion;
1819 struct intel_vbt_data vbt;
1821 bool preserve_bios_swizzle;
1824 struct intel_overlay *overlay;
1826 /* backlight registers and fields in struct intel_panel */
1827 struct lock backlight_lock;
1830 bool no_aux_handshake;
1832 /* protects panel power sequencer state */
1833 struct lock pps_mutex;
1835 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1836 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1838 unsigned int fsb_freq, mem_freq, is_ddr3;
1839 unsigned int skl_boot_cdclk;
1840 unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
1841 unsigned int max_dotclk_freq;
1842 unsigned int hpll_freq;
1843 unsigned int czclk_freq;
1846 * wq - Driver workqueue for GEM.
1848 * NOTE: Work items scheduled here are not allowed to grab any modeset
1849 * locks, for otherwise the flushing done in the pageflip code will
1850 * result in deadlocks.
1852 struct workqueue_struct *wq;
1854 /* Display functions */
1855 struct drm_i915_display_funcs display;
1857 /* PCH chipset type */
1858 enum intel_pch pch_type;
1859 unsigned short pch_id;
1861 unsigned long quirks;
1863 enum modeset_restore modeset_restore;
1864 struct lock modeset_restore_lock;
1865 struct drm_atomic_state *modeset_restore_state;
1867 struct list_head vm_list; /* Global list of all address spaces */
1868 struct i915_gtt gtt; /* VM representing the global address space */
1870 struct i915_gem_mm mm;
1871 DECLARE_HASHTABLE(mm_structs, 7);
1872 struct lock mm_lock;
1874 /* Kernel Modesetting */
1876 struct sdvo_device_mapping sdvo_mappings[2];
1878 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1879 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1880 wait_queue_head_t pending_flip_queue;
1882 #ifdef CONFIG_DEBUG_FS
1883 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1886 /* dpll and cdclk state is protected by connection_mutex */
1887 int num_shared_dpll;
1888 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1890 unsigned int active_crtcs;
1891 unsigned int min_pixclk[I915_MAX_PIPES];
1893 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1895 struct i915_workarounds workarounds;
1897 /* Reclocking support */
1898 bool render_reclock_avail;
1900 struct i915_frontbuffer_tracking fb_tracking;
1904 bool mchbar_need_disable;
1906 struct intel_l3_parity l3_parity;
1908 /* Cannot be determined by PCIID. You must always read a register. */
1911 /* gen6+ rps state */
1912 struct intel_gen6_power_mgmt rps;
1914 /* ilk-only ips/rps state. Everything in here is protected by the global
1915 * mchdev_lock in intel_pm.c */
1916 struct intel_ilk_power_mgmt ips;
1918 struct i915_power_domains power_domains;
1920 struct i915_psr psr;
1922 struct i915_gpu_error gpu_error;
1924 struct drm_i915_gem_object *vlv_pctx;
1926 #ifdef CONFIG_DRM_FBDEV_EMULATION
1927 /* list of fbdev register on this device */
1928 struct intel_fbdev *fbdev;
1929 struct work_struct fbdev_suspend_work;
1932 struct drm_property *broadcast_rgb_property;
1933 struct drm_property *force_audio_property;
1935 /* hda/i915 audio component */
1936 struct i915_audio_component *audio_component;
1937 bool audio_component_registered;
1939 * av_mutex - mutex for audio/video sync
1942 struct lock av_mutex;
1944 uint32_t hw_context_size;
1945 struct list_head context_list;
1949 u32 chv_phy_control;
1952 bool suspended_to_idle;
1953 struct i915_suspend_saved_registers regfile;
1954 struct vlv_s0ix_state vlv_s0ix_state;
1958 * Raw watermark latency values:
1959 * in 0.1us units for WM0,
1960 * in 0.5us units for WM1+.
1963 uint16_t pri_latency[5];
1965 uint16_t spr_latency[5];
1967 uint16_t cur_latency[5];
1969 * Raw watermark memory latency values
1970 * for SKL for all 8 levels
1973 uint16_t skl_latency[8];
1975 /* Committed wm config */
1976 struct intel_wm_config config;
1979 * The skl_wm_values structure is a bit too big for stack
1980 * allocation, so we keep the staging struct where we store
1981 * intermediate results here instead.
1983 struct skl_wm_values skl_results;
1985 /* current hardware state */
1987 struct ilk_wm_values hw;
1988 struct skl_wm_values skl_hw;
1989 struct vlv_wm_values vlv;
1996 struct i915_runtime_pm pm;
1998 uint32_t bios_vgacntr;
2000 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2002 int (*execbuf_submit)(struct i915_execbuffer_params *params,
2003 struct drm_i915_gem_execbuffer2 *args,
2004 struct list_head *vmas);
2005 int (*init_rings)(struct drm_device *dev);
2006 void (*cleanup_ring)(struct intel_engine_cs *ring);
2007 void (*stop_ring)(struct intel_engine_cs *ring);
2010 struct intel_context *kernel_context;
2012 bool edp_low_vswing;
2014 /* perform PHY state sanity checks? */
2015 bool chv_phy_assert[2];
2017 struct intel_encoder *dig_port_map[I915_MAX_PORTS];
2020 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2021 * will be rejected. Instead look for a better place.
2025 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2027 return dev->dev_private;
2030 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
2035 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2037 return container_of(guc, struct drm_i915_private, guc);
2040 /* Iterate over initialised rings */
2041 #define for_each_ring(ring__, dev_priv__, i__) \
2042 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
2043 for_each_if ((((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))))
2045 enum hdmi_force_audio {
2046 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2047 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2048 HDMI_AUDIO_AUTO, /* trust EDID */
2049 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2052 #define I915_GTT_OFFSET_NONE ((u32)-1)
2054 struct drm_i915_gem_object_ops {
2056 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2058 /* Interface between the GEM object and its backing storage.
2059 * get_pages() is called once prior to the use of the associated set
2060 * of pages before to binding them into the GTT, and put_pages() is
2061 * called after we no longer need them. As we expect there to be
2062 * associated cost with migrating pages between the backing storage
2063 * and making them available for the GPU (e.g. clflush), we may hold
2064 * onto the pages after they are no longer referenced by the GPU
2065 * in case they may be used again shortly (for example migrating the
2066 * pages to a different memory domain within the GTT). put_pages()
2067 * will therefore most likely be called when the object itself is
2068 * being released or under memory pressure (where we attempt to
2069 * reap pages for the shrinker).
2071 int (*get_pages)(struct drm_i915_gem_object *);
2072 void (*put_pages)(struct drm_i915_gem_object *);
2074 int (*dmabuf_export)(struct drm_i915_gem_object *);
2075 void (*release)(struct drm_i915_gem_object *);
2079 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2080 * considered to be the frontbuffer for the given plane interface-wise. This
2081 * doesn't mean that the hw necessarily already scans it out, but that any
2082 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2084 * We have one bit per pipe and per scanout plane type.
2086 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2087 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2088 #define INTEL_FRONTBUFFER_BITS \
2089 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2090 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2091 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2092 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2093 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2094 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2095 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2096 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2097 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2098 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2099 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2101 struct drm_i915_gem_object {
2102 struct drm_gem_object base;
2104 const struct drm_i915_gem_object_ops *ops;
2106 /** List of VMAs backed by this object */
2107 struct list_head vma_list;
2109 /** Stolen memory for this object, instead of being backed by shmem. */
2110 struct drm_mm_node *stolen;
2111 struct list_head global_list;
2113 struct list_head ring_list[I915_NUM_RINGS];
2114 /** Used in execbuf to temporarily hold a ref */
2115 struct list_head obj_exec_link;
2117 struct list_head batch_pool_link;
2120 * This is set if the object is on the active lists (has pending
2121 * rendering and so a non-zero seqno), and is not set if it i s on
2122 * inactive (ready to be unbound) list.
2124 unsigned int active:I915_NUM_RINGS;
2127 * This is set if the object has been written to since last bound
2130 unsigned int dirty:1;
2133 * Fence register bits (if any) for this object. Will be set
2134 * as needed when mapped into the GTT.
2135 * Protected by dev->struct_mutex.
2137 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2140 * Advice: are the backing pages purgeable?
2142 unsigned int madv:2;
2145 * Current tiling mode for the object.
2147 unsigned int tiling_mode:2;
2149 * Whether the tiling parameters for the currently associated fence
2150 * register have changed. Note that for the purposes of tracking
2151 * tiling changes we also treat the unfenced register, the register
2152 * slot that the object occupies whilst it executes a fenced
2153 * command (such as BLT on gen2/3), as a "fence".
2155 unsigned int fence_dirty:1;
2158 * Is the object at the current location in the gtt mappable and
2159 * fenceable? Used to avoid costly recalculations.
2161 unsigned int map_and_fenceable:1;
2164 * Whether the current gtt mapping needs to be mappable (and isn't just
2165 * mappable by accident). Track pin and fault separate for a more
2166 * accurate mappable working set.
2168 unsigned int fault_mappable:1;
2171 * Is the object to be mapped as read-only to the GPU
2172 * Only honoured if hardware has relevant pte bit
2174 unsigned long gt_ro:1;
2175 unsigned int cache_level:3;
2176 unsigned int cache_dirty:1;
2178 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2180 unsigned int pin_display;
2182 struct sg_table *pages;
2183 int pages_pin_count;
2185 struct scatterlist *sg;
2189 /* prime dma-buf support */
2190 void *dma_buf_vmapping;
2193 /** Breadcrumb of last rendering to the buffer.
2194 * There can only be one writer, but we allow for multiple readers.
2195 * If there is a writer that necessarily implies that all other
2196 * read requests are complete - but we may only be lazily clearing
2197 * the read requests. A read request is naturally the most recent
2198 * request on a ring, so we may have two different write and read
2199 * requests on one ring where the write request is older than the
2200 * read request. This allows for the CPU to read from an active
2201 * buffer by only waiting for the write to complete.
2203 struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS];
2204 struct drm_i915_gem_request *last_write_req;
2205 /** Breadcrumb of last fenced GPU access to the buffer. */
2206 struct drm_i915_gem_request *last_fenced_req;
2208 /** Current tiling stride for the object, if it's tiled. */
2211 /** References from framebuffers, locks out tiling changes. */
2212 unsigned long framebuffer_references;
2214 /** Record of address bit 17 of each page at last unbind. */
2215 unsigned long *bit_17;
2218 /** for phy allocated objects */
2219 struct drm_dma_handle *phys_handle;
2221 struct i915_gem_userptr {
2223 unsigned read_only :1;
2224 unsigned workers :4;
2225 #define I915_GEM_USERPTR_MAX_WORKERS 15
2227 struct i915_mm_struct *mm;
2228 struct i915_mmu_object *mmu_object;
2229 struct work_struct *work;
2233 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2235 void i915_gem_track_fb(struct drm_i915_gem_object *old,
2236 struct drm_i915_gem_object *new,
2237 unsigned frontbuffer_bits);
2240 * Request queue structure.
2242 * The request queue allows us to note sequence numbers that have been emitted
2243 * and may be associated with active buffers to be retired.
2245 * By keeping this list, we can avoid having to do questionable sequence
2246 * number comparisons on buffer last_read|write_seqno. It also allows an
2247 * emission time to be associated with the request for tracking how far ahead
2248 * of the GPU the submission is.
2250 * The requests are reference counted, so upon creation they should have an
2251 * initial reference taken using kref_init
2253 struct drm_i915_gem_request {
2256 /** On Which ring this request was generated */
2257 struct drm_i915_private *i915;
2258 struct intel_engine_cs *ring;
2260 /** GEM sequence number associated with the previous request,
2261 * when the HWS breadcrumb is equal to this the GPU is processing
2266 /** GEM sequence number associated with this request,
2267 * when the HWS breadcrumb is equal or greater than this the GPU
2268 * has finished processing this request.
2272 /** Position in the ringbuffer of the start of the request */
2276 * Position in the ringbuffer of the start of the postfix.
2277 * This is required to calculate the maximum available ringbuffer
2278 * space without overwriting the postfix.
2282 /** Position in the ringbuffer of the end of the whole request */
2286 * Context and ring buffer related to this request
2287 * Contexts are refcounted, so when this request is associated with a
2288 * context, we must increment the context's refcount, to guarantee that
2289 * it persists while any request is linked to it. Requests themselves
2290 * are also refcounted, so the request will only be freed when the last
2291 * reference to it is dismissed, and the code in
2292 * i915_gem_request_free() will then decrement the refcount on the
2295 struct intel_context *ctx;
2296 struct intel_ringbuffer *ringbuf;
2298 /** Batch buffer related to this request if any (used for
2299 error state dump only) */
2300 struct drm_i915_gem_object *batch_obj;
2302 /** Time at which this request was emitted, in jiffies. */
2303 unsigned long emitted_jiffies;
2305 /** global list entry for this request */
2306 struct list_head list;
2308 struct drm_i915_file_private *file_priv;
2309 /** file_priv list entry for this request */
2310 struct list_head client_list;
2312 /** process identifier submitting this request */
2316 * The ELSP only accepts two elements at a time, so we queue
2317 * context/tail pairs on a given queue (ring->execlist_queue) until the
2318 * hardware is available. The queue serves a double purpose: we also use
2319 * it to keep track of the up to 2 contexts currently in the hardware
2320 * (usually one in execution and the other queued up by the GPU): We
2321 * only remove elements from the head of the queue when the hardware
2322 * informs us that an element has been completed.
2324 * All accesses to the queue are mediated by a spinlock
2325 * (ring->execlist_lock).
2328 /** Execlist link in the submission queue.*/
2329 struct list_head execlist_link;
2331 /** Execlists no. of times this request has been sent to the ELSP */
2336 struct drm_i915_gem_request * __must_check
2337 i915_gem_request_alloc(struct intel_engine_cs *engine,
2338 struct intel_context *ctx);
2339 void i915_gem_request_cancel(struct drm_i915_gem_request *req);
2340 void i915_gem_request_free(struct kref *req_ref);
2341 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
2342 struct drm_file *file);
2344 static inline uint32_t
2345 i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2347 return req ? req->seqno : 0;
2350 static inline struct intel_engine_cs *
2351 i915_gem_request_get_ring(struct drm_i915_gem_request *req)
2353 return req ? req->ring : NULL;
2356 static inline struct drm_i915_gem_request *
2357 i915_gem_request_reference(struct drm_i915_gem_request *req)
2360 kref_get(&req->ref);
2365 i915_gem_request_unreference(struct drm_i915_gem_request *req)
2367 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
2368 kref_put(&req->ref, i915_gem_request_free);
2372 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
2374 struct drm_device *dev;
2379 dev = req->ring->dev;
2380 if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
2381 mutex_unlock(&dev->struct_mutex);
2384 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2385 struct drm_i915_gem_request *src)
2388 i915_gem_request_reference(src);
2391 i915_gem_request_unreference(*pdst);
2397 * XXX: i915_gem_request_completed should be here but currently needs the
2398 * definition of i915_seqno_passed() which is below. It will be moved in
2399 * a later patch when the call to i915_seqno_passed() is obsoleted...
2403 * A command that requires special handling by the command parser.
2405 struct drm_i915_cmd_descriptor {
2407 * Flags describing how the command parser processes the command.
2409 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2410 * a length mask if not set
2411 * CMD_DESC_SKIP: The command is allowed but does not follow the
2412 * standard length encoding for the opcode range in
2414 * CMD_DESC_REJECT: The command is never allowed
2415 * CMD_DESC_REGISTER: The command should be checked against the
2416 * register whitelist for the appropriate ring
2417 * CMD_DESC_MASTER: The command is allowed if the submitting process
2421 #define CMD_DESC_FIXED (1<<0)
2422 #define CMD_DESC_SKIP (1<<1)
2423 #define CMD_DESC_REJECT (1<<2)
2424 #define CMD_DESC_REGISTER (1<<3)
2425 #define CMD_DESC_BITMASK (1<<4)
2426 #define CMD_DESC_MASTER (1<<5)
2429 * The command's unique identification bits and the bitmask to get them.
2430 * This isn't strictly the opcode field as defined in the spec and may
2431 * also include type, subtype, and/or subop fields.
2439 * The command's length. The command is either fixed length (i.e. does
2440 * not include a length field) or has a length field mask. The flag
2441 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2442 * a length mask. All command entries in a command table must include
2443 * length information.
2451 * Describes where to find a register address in the command to check
2452 * against the ring's register whitelist. Only valid if flags has the
2453 * CMD_DESC_REGISTER bit set.
2455 * A non-zero step value implies that the command may access multiple
2456 * registers in sequence (e.g. LRI), in that case step gives the
2457 * distance in dwords between individual offset fields.
2465 #define MAX_CMD_DESC_BITMASKS 3
2467 * Describes command checks where a particular dword is masked and
2468 * compared against an expected value. If the command does not match
2469 * the expected value, the parser rejects it. Only valid if flags has
2470 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2473 * If the check specifies a non-zero condition_mask then the parser
2474 * only performs the check when the bits specified by condition_mask
2481 u32 condition_offset;
2483 } bits[MAX_CMD_DESC_BITMASKS];
2487 * A table of commands requiring special handling by the command parser.
2489 * Each ring has an array of tables. Each table consists of an array of command
2490 * descriptors, which must be sorted with command opcodes in ascending order.
2492 struct drm_i915_cmd_table {
2493 const struct drm_i915_cmd_descriptor *table;
2497 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2498 #define __I915__(p) ({ \
2499 const struct drm_i915_private *__p; \
2500 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2501 __p = (const struct drm_i915_private *)p; \
2502 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2503 __p = to_i915((const struct drm_device *)p); \
2506 #define INTEL_INFO(p) (&__I915__(p)->info)
2507 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2508 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2510 #define REVID_FOREVER 0xff
2512 * Return true if revision is in range [since,until] inclusive.
2514 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2516 #define IS_REVID(p, since, until) \
2517 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2519 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2520 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2521 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2522 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2523 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2524 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2525 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2526 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2527 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2528 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2529 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2530 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2531 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2532 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2533 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2534 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2535 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2536 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2537 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2538 INTEL_DEVID(dev) == 0x0152 || \
2539 INTEL_DEVID(dev) == 0x015a)
2540 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2541 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
2542 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2543 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev))
2544 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2545 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2546 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2547 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2548 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2549 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2550 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2551 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2552 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2553 (INTEL_DEVID(dev) & 0xf) == 0xe))
2554 /* ULX machines are also considered ULT. */
2555 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2556 (INTEL_DEVID(dev) & 0xf) == 0xe)
2557 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2558 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2559 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2560 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2561 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2562 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2563 /* ULX machines are also considered ULT. */
2564 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2565 INTEL_DEVID(dev) == 0x0A1E)
2566 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2567 INTEL_DEVID(dev) == 0x1913 || \
2568 INTEL_DEVID(dev) == 0x1916 || \
2569 INTEL_DEVID(dev) == 0x1921 || \
2570 INTEL_DEVID(dev) == 0x1926)
2571 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2572 INTEL_DEVID(dev) == 0x1915 || \
2573 INTEL_DEVID(dev) == 0x191E)
2574 #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2575 INTEL_DEVID(dev) == 0x5913 || \
2576 INTEL_DEVID(dev) == 0x5916 || \
2577 INTEL_DEVID(dev) == 0x5921 || \
2578 INTEL_DEVID(dev) == 0x5926)
2579 #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2580 INTEL_DEVID(dev) == 0x5915 || \
2581 INTEL_DEVID(dev) == 0x591E)
2582 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2583 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2584 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2585 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2587 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2589 #define SKL_REVID_A0 0x0
2590 #define SKL_REVID_B0 0x1
2591 #define SKL_REVID_C0 0x2
2592 #define SKL_REVID_D0 0x3
2593 #define SKL_REVID_E0 0x4
2594 #define SKL_REVID_F0 0x5
2596 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2598 #define BXT_REVID_A0 0x0
2599 #define BXT_REVID_A1 0x1
2600 #define BXT_REVID_B0 0x3
2601 #define BXT_REVID_C0 0x9
2603 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2606 * The genX designation typically refers to the render engine, so render
2607 * capability related checks should use IS_GEN, while display and other checks
2608 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2611 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2612 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2613 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2614 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2615 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2616 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2617 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2618 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2620 #define RENDER_RING (1<<RCS)
2621 #define BSD_RING (1<<VCS)
2622 #define BLT_RING (1<<BCS)
2623 #define VEBOX_RING (1<<VECS)
2624 #define BSD2_RING (1<<VCS2)
2625 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2626 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2627 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2628 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2629 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2630 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2631 __I915__(dev)->ellc_size)
2632 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2634 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2635 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2636 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2637 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2638 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2640 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2641 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2643 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2644 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2646 /* WaRsDisableCoarsePowerGating:skl,bxt */
2647 #define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \
2648 IS_SKL_GT3(dev) || \
2652 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2653 * even when in MSI mode. This results in spurious interrupt warnings if the
2654 * legacy irq no. is shared with another device. The kernel then disables that
2655 * interrupt source and so prevents the other device from working properly.
2657 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2658 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2660 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2661 * rows, which changed the alignment requirements and fence programming.
2663 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2665 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2666 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2668 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2669 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2670 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2672 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2674 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2675 INTEL_INFO(dev)->gen >= 9)
2677 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2678 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2679 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2680 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2681 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2682 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2683 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2684 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2686 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2687 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2689 #define HAS_CSR(dev) (IS_GEN9(dev))
2691 #define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2692 #define HAS_GUC_SCHED(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2694 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2695 INTEL_INFO(dev)->gen >= 8)
2697 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2698 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2701 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2702 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2703 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2704 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2705 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2706 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2707 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2708 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2709 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2710 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2712 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2713 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2714 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2715 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2716 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2717 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2718 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2719 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2720 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2722 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2723 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2725 /* DPF == dynamic parity feature */
2726 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2727 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2729 #define GT_FREQUENCY_MULTIPLIER 50
2730 #define GEN9_FREQ_SCALER 3
2732 #include "i915_trace.h"
2734 extern const struct drm_ioctl_desc i915_ioctls[];
2735 extern int i915_max_ioctl;
2737 extern int i915_suspend_switcheroo(device_t kdev);
2738 extern int i915_resume_switcheroo(struct drm_device *dev);
2741 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2742 extern int i915_driver_unload(struct drm_device *);
2743 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2744 extern void i915_driver_lastclose(struct drm_device * dev);
2745 extern void i915_driver_preclose(struct drm_device *dev,
2746 struct drm_file *file);
2747 extern void i915_driver_postclose(struct drm_device *dev,
2748 struct drm_file *file);
2749 #ifdef CONFIG_COMPAT
2750 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2753 extern int intel_gpu_reset(struct drm_device *dev);
2754 extern bool intel_has_gpu_reset(struct drm_device *dev);
2755 extern int i915_reset(struct drm_device *dev);
2756 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2757 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2758 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2759 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2760 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2762 /* intel_hotplug.c */
2763 void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
2764 void intel_hpd_init(struct drm_i915_private *dev_priv);
2765 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2766 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2767 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2770 void i915_queue_hangcheck(struct drm_device *dev);
2772 void i915_handle_error(struct drm_device *dev, bool wedged,
2773 const char *fmt, ...);
2775 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2776 int intel_irq_install(struct drm_i915_private *dev_priv);
2777 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2779 extern void intel_uncore_sanitize(struct drm_device *dev);
2780 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2781 bool restore_forcewake);
2782 extern void intel_uncore_init(struct drm_device *dev);
2783 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2784 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2785 extern void intel_uncore_fini(struct drm_device *dev);
2786 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2787 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2788 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2789 enum forcewake_domains domains);
2790 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2791 enum forcewake_domains domains);
2792 /* Like above but the caller must manage the uncore.lock itself.
2793 * Must be used with I915_READ_FW and friends.
2795 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2796 enum forcewake_domains domains);
2797 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2798 enum forcewake_domains domains);
2799 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2800 static inline bool intel_vgpu_active(struct drm_device *dev)
2802 return to_i915(dev)->vgpu.active;
2806 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum i915_pipe pipe,
2810 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum i915_pipe pipe,
2813 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2814 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2815 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2818 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2819 uint32_t interrupt_mask,
2820 uint32_t enabled_irq_mask);
2822 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2824 ilk_update_display_irq(dev_priv, bits, bits);
2827 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2829 ilk_update_display_irq(dev_priv, bits, 0);
2831 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2832 enum i915_pipe pipe,
2833 uint32_t interrupt_mask,
2834 uint32_t enabled_irq_mask);
2835 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
2836 enum i915_pipe pipe, uint32_t bits)
2838 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
2840 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
2841 enum i915_pipe pipe, uint32_t bits)
2843 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
2845 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2846 uint32_t interrupt_mask,
2847 uint32_t enabled_irq_mask);
2849 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2851 ibx_display_interrupt_update(dev_priv, bits, bits);
2854 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2856 ibx_display_interrupt_update(dev_priv, bits, 0);
2861 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2862 struct drm_file *file_priv);
2863 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2864 struct drm_file *file_priv);
2865 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2866 struct drm_file *file_priv);
2867 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2868 struct drm_file *file_priv);
2869 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2870 struct drm_file *file_priv);
2871 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2872 struct drm_file *file_priv);
2873 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2874 struct drm_file *file_priv);
2875 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2876 struct drm_i915_gem_request *req);
2877 void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params);
2878 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
2879 struct drm_i915_gem_execbuffer2 *args,
2880 struct list_head *vmas);
2881 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2882 struct drm_file *file_priv);
2883 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2884 struct drm_file *file_priv);
2885 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2886 struct drm_file *file_priv);
2887 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2888 struct drm_file *file);
2889 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2890 struct drm_file *file);
2891 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2892 struct drm_file *file_priv);
2893 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2894 struct drm_file *file_priv);
2895 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2896 struct drm_file *file_priv);
2897 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2898 struct drm_file *file_priv);
2899 int i915_gem_init_userptr(struct drm_device *dev);
2900 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2901 struct drm_file *file);
2902 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2903 struct drm_file *file_priv);
2904 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2905 struct drm_file *file_priv);
2906 void i915_gem_load_init(struct drm_device *dev);
2907 void i915_gem_load_cleanup(struct drm_device *dev);
2908 void *i915_gem_object_alloc(struct drm_device *dev);
2909 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2910 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2911 const struct drm_i915_gem_object_ops *ops);
2912 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2914 struct drm_i915_gem_object *i915_gem_object_create_from_data(
2915 struct drm_device *dev, const void *data, size_t size);
2916 void i915_gem_free_object(struct drm_gem_object *obj);
2917 void i915_gem_vma_destroy(struct i915_vma *vma);
2919 /* Flags used by pin/bind&friends. */
2920 #define PIN_MAPPABLE (1<<0)
2921 #define PIN_NONBLOCK (1<<1)
2922 #define PIN_GLOBAL (1<<2)
2923 #define PIN_OFFSET_BIAS (1<<3)
2924 #define PIN_USER (1<<4)
2925 #define PIN_UPDATE (1<<5)
2926 #define PIN_ZONE_4G (1<<6)
2927 #define PIN_HIGH (1<<7)
2928 #define PIN_OFFSET_FIXED (1<<8)
2929 #define PIN_OFFSET_MASK (~4095)
2931 i915_gem_object_pin(struct drm_i915_gem_object *obj,
2932 struct i915_address_space *vm,
2936 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2937 const struct i915_ggtt_view *view,
2941 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2943 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
2944 int __must_check i915_vma_unbind(struct i915_vma *vma);
2946 * BEWARE: Do not use the function below unless you can _absolutely_
2947 * _guarantee_ VMA in question is _not in use_ anywhere.
2949 int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
2950 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2951 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2952 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2954 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2955 int *needs_clflush);
2957 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2959 static inline int __sg_page_count(struct scatterlist *sg)
2961 return sg->length >> PAGE_SHIFT;
2965 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);
2967 static inline struct vm_page *
2968 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2970 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
2973 if (n < obj->get_page.last) {
2974 obj->get_page.sg = obj->pages->sgl;
2975 obj->get_page.last = 0;
2978 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
2979 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
2981 if (unlikely(sg_is_chain(obj->get_page.sg)))
2982 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
2986 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2989 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2991 BUG_ON(obj->pages == NULL);
2992 obj->pages_pin_count++;
2994 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2996 BUG_ON(obj->pages_pin_count == 0);
2997 obj->pages_pin_count--;
3000 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3001 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
3002 struct intel_engine_cs *to,
3003 struct drm_i915_gem_request **to_req);
3004 void i915_vma_move_to_active(struct i915_vma *vma,
3005 struct drm_i915_gem_request *req);
3006 int i915_gem_dumb_create(struct drm_file *file_priv,
3007 struct drm_device *dev,
3008 struct drm_mode_create_dumb *args);
3009 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3010 uint32_t handle, uint64_t *offset);
3012 * Returns true if seq1 is later than seq2.
3015 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
3017 return (int32_t)(seq1 - seq2) >= 0;
3020 static inline bool i915_gem_request_started(struct drm_i915_gem_request *req,
3021 bool lazy_coherency)
3023 u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
3024 return i915_seqno_passed(seqno, req->previous_seqno);
3027 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
3028 bool lazy_coherency)
3030 u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
3031 return i915_seqno_passed(seqno, req->seqno);
3034 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
3035 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
3037 struct drm_i915_gem_request *
3038 i915_gem_find_active_request(struct intel_engine_cs *ring);
3040 bool i915_gem_retire_requests(struct drm_device *dev);
3041 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
3042 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
3043 bool interruptible);
3045 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3047 return unlikely(atomic_read(&error->reset_counter)
3048 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
3051 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3053 return atomic_read(&error->reset_counter) & I915_WEDGED;
3056 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3058 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
3061 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
3063 return dev_priv->gpu_error.stop_rings == 0 ||
3064 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
3067 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
3069 return dev_priv->gpu_error.stop_rings == 0 ||
3070 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
3073 void i915_gem_reset(struct drm_device *dev);
3074 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3075 int __must_check i915_gem_init(struct drm_device *dev);
3076 int i915_gem_init_rings(struct drm_device *dev);
3077 int __must_check i915_gem_init_hw(struct drm_device *dev);
3078 int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
3079 void i915_gem_init_swizzling(struct drm_device *dev);
3080 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
3081 int __must_check i915_gpu_idle(struct drm_device *dev);
3082 int __must_check i915_gem_suspend(struct drm_device *dev);
3083 void __i915_add_request(struct drm_i915_gem_request *req,
3084 struct drm_i915_gem_object *batch_obj,
3086 #define i915_add_request(req) \
3087 __i915_add_request(req, NULL, true)
3088 #define i915_add_request_no_flush(req) \
3089 __i915_add_request(req, NULL, false)
3090 int __i915_wait_request(struct drm_i915_gem_request *req,
3091 unsigned reset_counter,
3094 struct intel_rps_client *rps);
3095 int __must_check i915_wait_request(struct drm_i915_gem_request *req);
3096 int i915_gem_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot, vm_page_t *mres);
3098 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
3101 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3104 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3106 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3108 const struct i915_ggtt_view *view);
3109 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
3110 const struct i915_ggtt_view *view);
3111 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3113 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3114 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3117 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
3119 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
3120 int tiling_mode, bool fenced);
3122 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3123 enum i915_cache_level cache_level);
3126 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3127 struct dma_buf *dma_buf);
3129 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3130 struct drm_gem_object *gem_obj, int flags);
3133 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
3134 const struct i915_ggtt_view *view);
3135 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
3136 struct i915_address_space *vm);
3138 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
3140 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3143 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
3144 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3145 const struct i915_ggtt_view *view);
3146 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3147 struct i915_address_space *vm);
3149 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
3150 struct i915_address_space *vm);
3152 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3153 struct i915_address_space *vm);
3155 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
3156 const struct i915_ggtt_view *view);
3159 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3160 struct i915_address_space *vm);
3162 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3163 const struct i915_ggtt_view *view);
3165 static inline struct i915_vma *
3166 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
3168 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
3170 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3172 /* Some GGTT VM helpers */
3173 #define i915_obj_to_ggtt(obj) \
3174 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
3176 static inline struct i915_hw_ppgtt *
3177 i915_vm_to_ppgtt(struct i915_address_space *vm)
3179 WARN_ON(i915_is_ggtt(vm));
3180 return container_of(vm, struct i915_hw_ppgtt, base);
3184 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
3186 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3189 static inline unsigned long
3190 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
3192 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
3195 static inline int __must_check
3196 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
3200 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
3201 alignment, flags | PIN_GLOBAL);
3205 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
3207 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
3210 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3211 const struct i915_ggtt_view *view);
3213 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3215 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3218 /* i915_gem_fence.c */
3219 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
3220 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
3222 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
3223 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
3225 void i915_gem_restore_fences(struct drm_device *dev);
3227 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3228 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3229 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3231 /* i915_gem_context.c */
3232 int __must_check i915_gem_context_init(struct drm_device *dev);
3233 void i915_gem_context_fini(struct drm_device *dev);
3234 void i915_gem_context_reset(struct drm_device *dev);
3235 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3236 int i915_gem_context_enable(struct drm_i915_gem_request *req);
3237 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3238 int i915_switch_context(struct drm_i915_gem_request *req);
3239 struct intel_context *
3240 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
3241 void i915_gem_context_free(struct kref *ctx_ref);
3242 struct drm_i915_gem_object *
3243 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3244 static inline void i915_gem_context_reference(struct intel_context *ctx)
3246 kref_get(&ctx->ref);
3249 static inline void i915_gem_context_unreference(struct intel_context *ctx)
3251 kref_put(&ctx->ref, i915_gem_context_free);
3254 static inline bool i915_gem_context_is_default(const struct intel_context *c)
3256 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3259 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3260 struct drm_file *file);
3261 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3262 struct drm_file *file);
3263 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3264 struct drm_file *file_priv);
3265 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3266 struct drm_file *file_priv);
3268 /* i915_gem_evict.c */
3269 int __must_check i915_gem_evict_something(struct drm_device *dev,
3270 struct i915_address_space *vm,
3273 unsigned cache_level,
3274 unsigned long start,
3277 int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3278 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3280 /* belongs in i915_gem_gtt.h */
3281 static inline void i915_gem_chipset_flush(struct drm_device *dev)
3283 if (INTEL_INFO(dev)->gen < 6)
3284 intel_gtt_chipset_flush();
3287 /* i915_gem_stolen.c */
3288 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3289 struct drm_mm_node *node, u64 size,
3290 unsigned alignment);
3291 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3292 struct drm_mm_node *node, u64 size,
3293 unsigned alignment, u64 start,
3295 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3296 struct drm_mm_node *node);
3297 int i915_gem_init_stolen(struct drm_device *dev);
3298 void i915_gem_cleanup_stolen(struct drm_device *dev);
3299 struct drm_i915_gem_object *
3300 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3301 struct drm_i915_gem_object *
3302 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3307 /* i915_gem_shrinker.c */
3308 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3309 unsigned long target,
3311 #define I915_SHRINK_PURGEABLE 0x1
3312 #define I915_SHRINK_UNBOUND 0x2
3313 #define I915_SHRINK_BOUND 0x4
3314 #define I915_SHRINK_ACTIVE 0x8
3315 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3316 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3317 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3320 /* i915_gem_tiling.c */
3321 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3323 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3325 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3326 obj->tiling_mode != I915_TILING_NONE;
3329 /* i915_gem_debug.c */
3331 int i915_verify_lists(struct drm_device *dev);
3333 #define i915_verify_lists(dev) 0
3336 /* i915_debugfs.c */
3337 int i915_debugfs_init(struct drm_minor *minor);
3338 void i915_debugfs_cleanup(struct drm_minor *minor);
3339 #ifdef CONFIG_DEBUG_FS
3340 int i915_debugfs_connector_add(struct drm_connector *connector);
3341 void intel_display_crc_init(struct drm_device *dev);
3343 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3345 static inline void intel_display_crc_init(struct drm_device *dev) {}
3348 /* i915_gpu_error.c */
3350 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3351 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3352 const struct i915_error_state_file_priv *error);
3353 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3354 struct drm_i915_private *i915,
3355 size_t count, loff_t pos);
3356 static inline void i915_error_state_buf_release(
3357 struct drm_i915_error_state_buf *eb)
3361 void i915_capture_error_state(struct drm_device *dev, bool wedge,
3362 const char *error_msg);
3363 void i915_error_state_get(struct drm_device *dev,
3364 struct i915_error_state_file_priv *error_priv);
3365 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3366 void i915_destroy_error_state(struct drm_device *dev);
3368 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3369 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3371 /* i915_cmd_parser.c */
3372 int i915_cmd_parser_get_version(void);
3373 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
3374 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
3375 bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
3376 int i915_parse_cmds(struct intel_engine_cs *ring,
3377 struct drm_i915_gem_object *batch_obj,
3378 struct drm_i915_gem_object *shadow_batch_obj,
3379 u32 batch_start_offset,
3383 /* i915_suspend.c */
3384 extern int i915_save_state(struct drm_device *dev);
3385 extern int i915_restore_state(struct drm_device *dev);
3388 void i915_setup_sysfs(struct drm_device *dev_priv);
3389 void i915_teardown_sysfs(struct drm_device *dev_priv);
3392 extern int intel_setup_gmbus(struct drm_device *dev);
3393 extern void intel_teardown_gmbus(struct drm_device *dev);
3394 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3397 extern struct i2c_adapter *
3398 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3399 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3400 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3401 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3403 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3405 extern void intel_i2c_reset(struct drm_device *dev);
3408 int intel_bios_init(struct drm_i915_private *dev_priv);
3409 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3411 /* intel_opregion.c */
3413 extern int intel_opregion_setup(struct drm_device *dev);
3414 extern void intel_opregion_init(struct drm_device *dev);
3415 extern void intel_opregion_fini(struct drm_device *dev);
3416 extern void intel_opregion_asle_intr(struct drm_device *dev);
3417 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3419 extern int intel_opregion_notify_adapter(struct drm_device *dev,
3422 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3423 static inline void intel_opregion_init(struct drm_device *dev) { return; }
3424 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3425 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3427 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3432 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3440 extern void intel_register_dsm_handler(void);
3441 extern void intel_unregister_dsm_handler(void);
3443 static inline void intel_register_dsm_handler(void) { return; }
3444 static inline void intel_unregister_dsm_handler(void) { return; }
3445 #endif /* CONFIG_ACPI */
3448 extern void intel_modeset_init_hw(struct drm_device *dev);
3449 extern void intel_modeset_init(struct drm_device *dev);
3450 extern void intel_modeset_gem_init(struct drm_device *dev);
3451 extern void intel_modeset_cleanup(struct drm_device *dev);
3452 extern void intel_connector_unregister(struct intel_connector *);
3453 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3454 extern void intel_display_resume(struct drm_device *dev);
3455 extern void i915_redisable_vga(struct drm_device *dev);
3456 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3457 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3458 extern void intel_init_pch_refclk(struct drm_device *dev);
3459 extern void intel_set_rps(struct drm_device *dev, u8 val);
3460 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3462 extern void intel_detect_pch(struct drm_device *dev);
3463 extern int intel_enable_rc6(const struct drm_device *dev);
3465 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
3466 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3467 struct drm_file *file);
3468 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3469 struct drm_file *file);
3471 struct intel_device_info *i915_get_device_id(int device);
3474 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3475 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3476 struct intel_overlay_error_state *error);
3478 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3479 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3480 struct drm_device *dev,
3481 struct intel_display_error_state *error);
3483 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3484 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3486 /* intel_sideband.c */
3487 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3488 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3489 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3490 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3491 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3492 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3493 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3494 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3495 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3496 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3497 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3498 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg);
3499 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg, u32 val);
3500 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3501 enum intel_sbi_destination destination);
3502 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3503 enum intel_sbi_destination destination);
3504 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3505 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3507 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3508 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3510 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3511 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3513 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3514 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3515 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3516 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3518 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3519 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3520 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3521 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3523 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3524 * will be implemented using 2 32-bit writes in an arbitrary order with
3525 * an arbitrary delay between them. This can cause the hardware to
3526 * act upon the intermediate value, possibly leading to corruption and
3527 * machine death. You have been warned.
3529 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3530 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3532 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3533 u32 upper, lower, old_upper, loop = 0; \
3534 upper = I915_READ(upper_reg); \
3536 old_upper = upper; \
3537 lower = I915_READ(lower_reg); \
3538 upper = I915_READ(upper_reg); \
3539 } while (upper != old_upper && loop++ < 2); \
3540 (u64)upper << 32 | lower; })
3542 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3543 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3545 #define __raw_read(x, s) \
3546 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3549 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3552 #define __raw_write(x, s) \
3553 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3554 i915_reg_t reg, uint##x##_t val) \
3556 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3571 /* These are untraced mmio-accessors that are only valid to be used inside
3572 * criticial sections inside IRQ handlers where forcewake is explicitly
3574 * Think twice, and think again, before using these.
3575 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3576 * intel_uncore_forcewake_irqunlock().
3578 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3579 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3580 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3582 /* "Broadcast RGB" property */
3583 #define INTEL_BROADCAST_RGB_AUTO 0
3584 #define INTEL_BROADCAST_RGB_FULL 1
3585 #define INTEL_BROADCAST_RGB_LIMITED 2
3587 static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
3589 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3590 return VLV_VGACNTRL;
3591 else if (INTEL_INFO(dev)->gen >= 5)
3592 return CPU_VGACNTRL;
3597 static inline void __user *to_user_ptr(u64 address)
3599 return (void __user *)(uintptr_t)address;
3602 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3604 unsigned long j = msecs_to_jiffies(m);
3606 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3609 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3611 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3614 static inline unsigned long
3615 timespec_to_jiffies_timeout(const struct timespec *value)
3617 unsigned long j = timespec_to_jiffies(value);
3619 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3623 * If you need to wait X milliseconds between events A and B, but event B
3624 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3625 * when event A happened, then just before event B you call this function and
3626 * pass the timestamp as the first argument, and X as the second argument.
3629 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3631 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3634 * Don't re-read the value of "jiffies" every time since it may change
3635 * behind our back and break the math.
3637 tmp_jiffies = jiffies;
3638 target_jiffies = timestamp_jiffies +
3639 msecs_to_jiffies_timeout(to_wait_ms);
3641 if (time_after(target_jiffies, tmp_jiffies)) {
3642 remaining_jiffies = target_jiffies - tmp_jiffies;
3644 while (remaining_jiffies)
3646 schedule_timeout_uninterruptible(remaining_jiffies);
3648 msleep(jiffies_to_msecs(remaining_jiffies));
3653 static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
3654 struct drm_i915_gem_request *req)
3656 if (ring->trace_irq_req == NULL && ring->irq_get(ring))
3657 i915_gem_request_assign(&ring->trace_irq_req, req);