2 * Copyright (c) 2003 Hidetoshi Shimokawa
3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the acknowledgement as bellow:
17 * This product includes software developed by K. Kobayashi and H. Shimokawa
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
34 * $FreeBSD: src/sys/dev/firewire/fwohci.c,v 1.72 2004/01/22 14:41:17 simokawa Exp $
35 * $FreeBSD: src/sys/dev/firewire/fwohci.c,v 1.1.2.19 2003/05/01 06:24:37 simokawa Exp $
36 * $DragonFly: src/sys/bus/firewire/fwohci.c,v 1.15 2006/12/22 23:12:16 swildner Exp $
46 #include <sys/param.h>
47 #include <sys/systm.h>
49 #include <sys/malloc.h>
50 #include <sys/sockio.h>
52 #include <sys/kernel.h>
54 #include <sys/device.h>
55 #include <sys/endian.h>
57 #include <sys/thread2.h>
59 #if defined(__DragonFly__) || __FreeBSD_version < 500000
60 #include <machine/clock.h> /* for DELAY() */
65 #include "firewirereg.h"
67 #include "fwohcireg.h"
68 #include "fwohcivar.h"
69 #include "firewire_phy.h"
71 #include <dev/firewire/firewire.h>
72 #include <dev/firewire/firewirereg.h>
73 #include <dev/firewire/fwdma.h>
74 #include <dev/firewire/fwohcireg.h>
75 #include <dev/firewire/fwohcivar.h>
76 #include <dev/firewire/firewire_phy.h>
81 static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL",
82 "STOR","LOAD","NOP ","STOP",};
84 static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3",
85 "UNDEF","REG","SYS","DEV"};
86 static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"};
87 char fwohcicode[32][0x20]={
88 "No stat","Undef","long","miss Ack err",
89 "underrun","overrun","desc err", "data read err",
90 "data write err","bus reset","timeout","tcode err",
91 "Undef","Undef","unknown event","flushed",
92 "Undef","ack complete","ack pend","Undef",
93 "ack busy_X","ack busy_A","ack busy_B","Undef",
94 "Undef","Undef","Undef","ack tardy",
95 "Undef","ack data_err","ack type_err",""};
98 extern char *linkspeed[];
99 u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31};
101 static struct tcode_info tinfo[] = {
102 /* hdr_len block flag*/
103 /* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL},
104 /* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY},
105 /* 2 WRES */ {12, FWTI_RES},
107 /* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL},
108 /* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL},
109 /* 6 RRESQ */ {16, FWTI_RES},
110 /* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY},
111 /* 8 CYCS */ { 0, 0},
112 /* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY},
113 /* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR},
114 /* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY},
117 /* e PHY */ {12, FWTI_REQ},
121 #define OHCI_WRITE_SIGMASK 0xffff0000
122 #define OHCI_READ_SIGMASK 0xffff0000
124 #define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x))
125 #define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r))
127 static void fwohci_ibr (struct firewire_comm *);
128 static void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *);
129 static void fwohci_db_free (struct fwohci_dbch *);
130 static void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int);
131 static void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *);
132 static void fwohci_start_atq (struct firewire_comm *);
133 static void fwohci_start_ats (struct firewire_comm *);
134 static void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *);
135 static u_int32_t fwphy_wrdata ( struct fwohci_softc *, u_int32_t, u_int32_t);
136 static u_int32_t fwphy_rddata ( struct fwohci_softc *, u_int32_t);
137 static int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *);
138 static int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *);
139 static int fwohci_irx_enable (struct firewire_comm *, int);
140 static int fwohci_irx_disable (struct firewire_comm *, int);
141 #if BYTE_ORDER == BIG_ENDIAN
142 static void fwohci_irx_post (struct firewire_comm *, u_int32_t *);
144 static int fwohci_itxbuf_enable (struct firewire_comm *, int);
145 static int fwohci_itx_disable (struct firewire_comm *, int);
146 static void fwohci_timeout (void *);
147 static void fwohci_set_intr (struct firewire_comm *, int);
149 static int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *);
150 static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int);
151 static void dump_db (struct fwohci_softc *, u_int32_t);
152 static void print_db (struct fwohcidb_tr *, struct fwohcidb *, u_int32_t , u_int32_t);
153 static void dump_dma (struct fwohci_softc *, u_int32_t);
154 static u_int32_t fwohci_cyctimer (struct firewire_comm *);
155 static void fwohci_rbuf_update (struct fwohci_softc *, int);
156 static void fwohci_tbuf_update (struct fwohci_softc *, int);
157 void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *);
159 static void fwohci_complete(void *, int);
163 * memory allocated for DMA programs
165 #define DMA_PROG_ALLOC (8 * PAGE_SIZE)
167 #define NDB FWMAXQUEUE
169 #define OHCI_VERSION 0x00
170 #define OHCI_ATRETRY 0x08
171 #define OHCI_CROMHDR 0x18
172 #define OHCI_BUS_OPT 0x20
173 #define OHCI_BUSIRMC (1 << 31)
174 #define OHCI_BUSCMC (1 << 30)
175 #define OHCI_BUSISC (1 << 29)
176 #define OHCI_BUSBMC (1 << 28)
177 #define OHCI_BUSPMC (1 << 27)
178 #define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\
179 OHCI_BUSBMC | OHCI_BUSPMC
181 #define OHCI_EUID_HI 0x24
182 #define OHCI_EUID_LO 0x28
184 #define OHCI_CROMPTR 0x34
185 #define OHCI_HCCCTL 0x50
186 #define OHCI_HCCCTLCLR 0x54
187 #define OHCI_AREQHI 0x100
188 #define OHCI_AREQHICLR 0x104
189 #define OHCI_AREQLO 0x108
190 #define OHCI_AREQLOCLR 0x10c
191 #define OHCI_PREQHI 0x110
192 #define OHCI_PREQHICLR 0x114
193 #define OHCI_PREQLO 0x118
194 #define OHCI_PREQLOCLR 0x11c
195 #define OHCI_PREQUPPER 0x120
197 #define OHCI_SID_BUF 0x64
198 #define OHCI_SID_CNT 0x68
199 #define OHCI_SID_ERR (1 << 31)
200 #define OHCI_SID_CNT_MASK 0xffc
202 #define OHCI_IT_STAT 0x90
203 #define OHCI_IT_STATCLR 0x94
204 #define OHCI_IT_MASK 0x98
205 #define OHCI_IT_MASKCLR 0x9c
207 #define OHCI_IR_STAT 0xa0
208 #define OHCI_IR_STATCLR 0xa4
209 #define OHCI_IR_MASK 0xa8
210 #define OHCI_IR_MASKCLR 0xac
212 #define OHCI_LNKCTL 0xe0
213 #define OHCI_LNKCTLCLR 0xe4
215 #define OHCI_PHYACCESS 0xec
216 #define OHCI_CYCLETIMER 0xf0
218 #define OHCI_DMACTL(off) (off)
219 #define OHCI_DMACTLCLR(off) (off + 4)
220 #define OHCI_DMACMD(off) (off + 0xc)
221 #define OHCI_DMAMATCH(off) (off + 0x10)
223 #define OHCI_ATQOFF 0x180
224 #define OHCI_ATQCTL OHCI_ATQOFF
225 #define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4)
226 #define OHCI_ATQCMD (OHCI_ATQOFF + 0xc)
227 #define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10)
229 #define OHCI_ATSOFF 0x1a0
230 #define OHCI_ATSCTL OHCI_ATSOFF
231 #define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4)
232 #define OHCI_ATSCMD (OHCI_ATSOFF + 0xc)
233 #define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10)
235 #define OHCI_ARQOFF 0x1c0
236 #define OHCI_ARQCTL OHCI_ARQOFF
237 #define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4)
238 #define OHCI_ARQCMD (OHCI_ARQOFF + 0xc)
239 #define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10)
241 #define OHCI_ARSOFF 0x1e0
242 #define OHCI_ARSCTL OHCI_ARSOFF
243 #define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4)
244 #define OHCI_ARSCMD (OHCI_ARSOFF + 0xc)
245 #define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10)
247 #define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH))
248 #define OHCI_ITCTL(CH) (OHCI_ITOFF(CH))
249 #define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4)
250 #define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc)
252 #define OHCI_IROFF(CH) (0x400 + 0x20 * (CH))
253 #define OHCI_IRCTL(CH) (OHCI_IROFF(CH))
254 #define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4)
255 #define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc)
256 #define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10)
258 d_ioctl_t fwohci_ioctl;
261 * Communication with PHY device
264 fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data)
271 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA));
272 OWRITE(sc, OHCI_PHYACCESS, fun);
275 return(fwphy_rddata( sc, addr));
279 fwohci_set_bus_manager(struct firewire_comm *fc, u_int node)
281 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
285 #define OHCI_CSR_DATA 0x0c
286 #define OHCI_CSR_COMP 0x10
287 #define OHCI_CSR_CONT 0x14
288 #define OHCI_BUS_MANAGER_ID 0
290 OWRITE(sc, OHCI_CSR_DATA, node);
291 OWRITE(sc, OHCI_CSR_COMP, 0x3f);
292 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID);
293 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++)
295 bm = OREAD(sc, OHCI_CSR_DATA);
296 if((bm & 0x3f) == 0x3f)
299 device_printf(sc->fc.dev,
300 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i);
306 fwphy_rddata(struct fwohci_softc *sc, u_int addr)
312 #define MAX_RETRY 100
314 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL);
315 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR);
316 OWRITE(sc, OHCI_PHYACCESS, fun);
317 for ( i = 0 ; i < MAX_RETRY ; i ++ ){
318 fun = OREAD(sc, OHCI_PHYACCESS);
319 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0)
325 device_printf(sc->fc.dev, "phy read failed(1).\n");
326 if (++retry < MAX_RETRY) {
331 /* Make sure that SCLK is started */
332 stat = OREAD(sc, FWOHCI_INTSTAT);
333 if ((stat & OHCI_INT_REG_FAIL) != 0 ||
334 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) {
336 device_printf(sc->fc.dev, "phy read failed(2).\n");
337 if (++retry < MAX_RETRY) {
342 if (bootverbose || retry >= MAX_RETRY)
343 device_printf(sc->fc.dev,
344 "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry);
346 return((fun >> PHYDEV_RDDATA )& 0xff);
348 /* Device specific ioctl. */
350 fwohci_ioctl (struct dev_ioctl_args *ap)
352 cdev_t dev = ap->a_head.a_dev;
353 struct firewire_softc *sc;
354 struct fwohci_softc *fc;
355 int unit = DEV2UNIT(dev);
357 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) ap->a_data;
358 u_int32_t *dmach = (u_int32_t *) ap->a_data;
360 sc = devclass_get_softc(firewire_devclass, unit);
364 fc = (struct fwohci_softc *)sc->fc;
371 #define OHCI_MAX_REG 0x800
372 if(reg->addr <= OHCI_MAX_REG){
373 OWRITE(fc, reg->addr, reg->data);
374 reg->data = OREAD(fc, reg->addr);
380 if(reg->addr <= OHCI_MAX_REG){
381 reg->data = OREAD(fc, reg->addr);
386 /* Read DMA descriptors for debug */
388 if(*dmach <= OHCI_MAX_DMA_CH ){
389 dump_dma(fc, *dmach);
395 /* Read/Write Phy registers */
396 #define OHCI_MAX_PHY_REG 0xf
397 case FWOHCI_RDPHYREG:
398 if (reg->addr <= OHCI_MAX_PHY_REG)
399 reg->data = fwphy_rddata(fc, reg->addr);
403 case FWOHCI_WRPHYREG:
404 if (reg->addr <= OHCI_MAX_PHY_REG)
405 reg->data = fwphy_wrdata(fc, reg->addr, reg->data);
417 fwohci_probe_phy(struct fwohci_softc *sc, device_t dev)
422 * probe PHY parameters
423 * 0. to prove PHY version, whether compliance of 1394a.
424 * 1. to probe maximum speed supported by the PHY and
425 * number of port supported by core-logic.
426 * It is not actually available port on your PC .
428 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS);
429 reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
431 if((reg >> 5) != 7 ){
432 sc->fc.mode &= ~FWPHYASYST;
433 sc->fc.nport = reg & FW_PHY_NP;
434 sc->fc.speed = reg & FW_PHY_SPD >> 6;
435 if (sc->fc.speed > MAX_SPEED) {
436 device_printf(dev, "invalid speed %d (fixed to %d).\n",
437 sc->fc.speed, MAX_SPEED);
438 sc->fc.speed = MAX_SPEED;
441 "Phy 1394 only %s, %d ports.\n",
442 linkspeed[sc->fc.speed], sc->fc.nport);
444 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG);
445 sc->fc.mode |= FWPHYASYST;
446 sc->fc.nport = reg & FW_PHY_NP;
447 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5;
448 if (sc->fc.speed > MAX_SPEED) {
449 device_printf(dev, "invalid speed %d (fixed to %d).\n",
450 sc->fc.speed, MAX_SPEED);
451 sc->fc.speed = MAX_SPEED;
454 "Phy 1394a available %s, %d ports.\n",
455 linkspeed[sc->fc.speed], sc->fc.nport);
457 /* check programPhyEnable */
458 reg2 = fwphy_rddata(sc, 5);
460 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) {
461 #else /* XXX force to enable 1394a */
466 "Enable 1394a Enhancements\n");
469 /* set aPhyEnhanceEnable */
470 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN);
471 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY);
476 reg2 = fwphy_wrdata(sc, 5, reg2);
479 reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
480 if((reg >> 5) == 7 ){
481 reg = fwphy_rddata(sc, 4);
483 fwphy_wrdata(sc, 4, reg);
484 reg = fwphy_rddata(sc, 4);
491 fwohci_reset(struct fwohci_softc *sc, device_t dev)
493 int i, max_rec, speed;
495 struct fwohcidb_tr *db_tr;
497 /* Disable interrupt */
498 OWRITE(sc, FWOHCI_INTMASKCLR, ~0);
500 /* Now stopping all DMA channel */
501 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
502 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
503 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
504 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
506 OWRITE(sc, OHCI_IR_MASKCLR, ~0);
507 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
508 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
509 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
512 /* FLUSH FIFO and reset Transmitter/Reciever */
513 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
515 device_printf(dev, "resetting OHCI...");
517 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) {
518 if (i++ > 100) break;
522 kprintf("done (loop=%d)\n", i);
525 fwohci_probe_phy(sc, dev);
528 reg = OREAD(sc, OHCI_BUS_OPT);
529 reg2 = reg | OHCI_BUSFNC;
530 max_rec = (reg & 0x0000f000) >> 12;
531 speed = (reg & 0x00000007);
532 device_printf(dev, "Link %s, max_rec %d bytes.\n",
533 linkspeed[speed], MAXREC(max_rec));
534 /* XXX fix max_rec */
535 sc->fc.maxrec = sc->fc.speed + 8;
536 if (max_rec != sc->fc.maxrec) {
537 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12);
538 device_printf(dev, "max_rec %d -> %d\n",
539 MAXREC(max_rec), MAXREC(sc->fc.maxrec));
542 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2);
543 OWRITE(sc, OHCI_BUS_OPT, reg2);
545 /* Initialize registers */
546 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]);
547 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr);
548 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND);
549 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR);
550 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr);
551 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID);
554 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN);
556 /* Force to start async RX DMA */
557 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING;
558 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING;
559 fwohci_rx_enable(sc, &sc->arrq);
560 fwohci_rx_enable(sc, &sc->arrs);
562 /* Initialize async TX */
563 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
564 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
567 OWRITE(sc, FWOHCI_RETRY,
568 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */
569 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ;
571 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq);
572 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq);
573 sc->atrq.bottom = sc->atrq.top;
574 sc->atrs.bottom = sc->atrs.top;
576 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ;
577 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
580 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ;
581 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
586 /* Enable interrupt */
587 OWRITE(sc, FWOHCI_INTMASK,
588 OHCI_INT_ERR | OHCI_INT_PHY_SID
589 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
590 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
591 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR);
592 fwohci_set_intr(&sc->fc, 1);
597 fwohci_init(struct fwohci_softc *sc, device_t dev)
604 TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc);
608 reg = OREAD(sc, OHCI_VERSION);
609 mver = (reg >> 16) & 0xff;
610 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n",
611 mver, reg & 0xff, (reg>>24) & 1);
612 if (mver < 1 || mver > 9) {
613 device_printf(dev, "invalid OHCI version\n");
617 /* Available Isochrounous DMA channel probe */
618 OWRITE(sc, OHCI_IT_MASK, 0xffffffff);
619 OWRITE(sc, OHCI_IR_MASK, 0xffffffff);
620 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK);
621 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff);
622 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff);
623 for (i = 0; i < 0x20; i++)
624 if ((reg & (1 << i)) == 0)
627 device_printf(dev, "No. of Isochronous channel is %d.\n", i);
631 sc->fc.arq = &sc->arrq.xferq;
632 sc->fc.ars = &sc->arrs.xferq;
633 sc->fc.atq = &sc->atrq.xferq;
634 sc->fc.ats = &sc->atrs.xferq;
636 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
637 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
638 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
639 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
641 sc->arrq.xferq.start = NULL;
642 sc->arrs.xferq.start = NULL;
643 sc->atrq.xferq.start = fwohci_start_atq;
644 sc->atrs.xferq.start = fwohci_start_ats;
646 sc->arrq.xferq.buf = NULL;
647 sc->arrs.xferq.buf = NULL;
648 sc->atrq.xferq.buf = NULL;
649 sc->atrs.xferq.buf = NULL;
651 sc->arrq.xferq.dmach = -1;
652 sc->arrs.xferq.dmach = -1;
653 sc->atrq.xferq.dmach = -1;
654 sc->atrs.xferq.dmach = -1;
658 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */
662 sc->arrs.ndb = NDB / 2;
664 sc->atrs.ndb = NDB / 2;
666 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
667 sc->fc.it[i] = &sc->it[i].xferq;
668 sc->fc.ir[i] = &sc->ir[i].xferq;
669 sc->it[i].xferq.dmach = i;
670 sc->ir[i].xferq.dmach = i;
675 sc->fc.tcode = tinfo;
678 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE,
679 &sc->crom_dma, BUS_DMA_WAITOK);
680 if(sc->fc.config_rom == NULL){
681 device_printf(dev, "config_rom alloc failed.");
686 bzero(&sc->fc.config_rom[0], CROMSIZE);
687 sc->fc.config_rom[1] = 0x31333934;
688 sc->fc.config_rom[2] = 0xf000a002;
689 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI);
690 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO);
691 sc->fc.config_rom[5] = 0;
692 sc->fc.config_rom[0] = (4 << 24) | (5 << 16);
694 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4);
698 /* SID recieve buffer must allign 2^11 */
699 #define OHCI_SIDSIZE (1 << 11)
700 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE,
701 &sc->sid_dma, BUS_DMA_WAITOK);
702 if (sc->sid_buf == NULL) {
703 device_printf(dev, "sid_buf alloc failed.");
707 fwdma_malloc(&sc->fc, sizeof(u_int32_t), sizeof(u_int32_t),
708 &sc->dummy_dma, BUS_DMA_WAITOK);
710 if (sc->dummy_dma.v_addr == NULL) {
711 device_printf(dev, "dummy_dma alloc failed.");
715 fwohci_db_init(sc, &sc->arrq);
716 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0)
719 fwohci_db_init(sc, &sc->arrs);
720 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0)
723 fwohci_db_init(sc, &sc->atrq);
724 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0)
727 fwohci_db_init(sc, &sc->atrs);
728 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0)
731 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H);
732 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L);
733 for( i = 0 ; i < 8 ; i ++)
734 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i);
735 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
736 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]);
738 sc->fc.ioctl = fwohci_ioctl;
739 sc->fc.cyctimer = fwohci_cyctimer;
740 sc->fc.set_bmr = fwohci_set_bus_manager;
741 sc->fc.ibr = fwohci_ibr;
742 sc->fc.irx_enable = fwohci_irx_enable;
743 sc->fc.irx_disable = fwohci_irx_disable;
745 sc->fc.itx_enable = fwohci_itxbuf_enable;
746 sc->fc.itx_disable = fwohci_itx_disable;
747 #if BYTE_ORDER == BIG_ENDIAN
748 sc->fc.irx_post = fwohci_irx_post;
750 sc->fc.irx_post = NULL;
752 sc->fc.itx_post = NULL;
753 sc->fc.timeout = fwohci_timeout;
754 sc->fc.poll = fwohci_poll;
755 sc->fc.set_intr = fwohci_set_intr;
757 sc->intmask = sc->irstat = sc->itstat = 0;
760 fwohci_reset(sc, dev);
766 fwohci_timeout(void *arg)
768 struct fwohci_softc *sc;
770 sc = (struct fwohci_softc *)arg;
774 fwohci_cyctimer(struct firewire_comm *fc)
776 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
777 return(OREAD(sc, OHCI_CYCLETIMER));
781 fwohci_detach(struct fwohci_softc *sc, device_t dev)
785 if (sc->sid_buf != NULL)
786 fwdma_free(&sc->fc, &sc->sid_dma);
787 if (sc->fc.config_rom != NULL)
788 fwdma_free(&sc->fc, &sc->crom_dma);
790 fwohci_db_free(&sc->arrq);
791 fwohci_db_free(&sc->arrs);
793 fwohci_db_free(&sc->atrq);
794 fwohci_db_free(&sc->atrs);
796 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
797 fwohci_db_free(&sc->it[i]);
798 fwohci_db_free(&sc->ir[i]);
804 #define LAST_DB(dbtr, db) do { \
805 struct fwohcidb_tr *_dbtr = (dbtr); \
806 int _cnt = _dbtr->dbcnt; \
807 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \
811 fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error)
813 struct fwohcidb_tr *db_tr;
815 bus_dma_segment_t *s;
818 db_tr = (struct fwohcidb_tr *)arg;
819 db = &db_tr->db[db_tr->dbcnt];
821 if (firewire_debug || error != EFBIG)
822 kprintf("fwohci_execute_db: error=%d\n", error);
825 for (i = 0; i < nseg; i++) {
827 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr);
828 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len);
829 FWOHCI_DMA_WRITE(db->db.desc.res, 0);
836 fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg,
837 bus_size_t size, int error)
839 fwohci_execute_db(arg, segs, nseg, error);
843 fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
846 int tcode, hdr_len, pl_off;
849 struct fw_xfer *xfer;
851 struct fwohci_txpkthdr *ohcifp;
852 struct fwohcidb_tr *db_tr;
855 struct tcode_info *info;
856 static int maxdesc=0;
858 if(&sc->atrq == dbch){
860 }else if(&sc->atrs == dbch){
866 if (dbch->flags & FWOHCI_DBCH_FULL)
872 xfer = STAILQ_FIRST(&dbch->xferq.q);
876 if(dbch->xferq.queued == 0 ){
877 device_printf(sc->fc.dev, "TX queue empty\n");
879 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link);
881 xfer->state = FWXF_START;
883 fp = &xfer->send.hdr;
884 tcode = fp->mode.common.tcode;
886 ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed;
887 info = &tinfo[tcode];
888 hdr_len = pl_off = info->hdr_len;
890 ld = &ohcifp->mode.ld[0];
891 ld[0] = ld[1] = ld[2] = ld[3] = 0;
892 for( i = 0 ; i < pl_off ; i+= 4)
893 ld[i/4] = fp->mode.ld[i/4];
895 ohcifp->mode.common.spd = xfer->send.spd & 0x7;
896 if (tcode == FWTCODE_STREAM ){
898 ohcifp->mode.stream.len = fp->mode.stream.len;
899 } else if (tcode == FWTCODE_PHY) {
901 ld[1] = fp->mode.ld[1];
902 ld[2] = fp->mode.ld[2];
903 ohcifp->mode.common.spd = 0;
904 ohcifp->mode.common.tcode = FWOHCITCODE_PHY;
906 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst;
907 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS;
908 ohcifp->mode.asycomm.tlrt |= FWRETRY_X;
911 FWOHCI_DMA_WRITE(db->db.desc.cmd,
912 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len);
913 FWOHCI_DMA_WRITE(db->db.desc.addr, 0);
914 FWOHCI_DMA_WRITE(db->db.desc.res, 0);
915 /* Specify bound timer of asy. responce */
916 if(&sc->atrs == dbch){
917 FWOHCI_DMA_WRITE(db->db.desc.res,
918 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13));
920 #if BYTE_ORDER == BIG_ENDIAN
921 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ)
923 for (i = 0; i < hdr_len/4; i ++)
924 FWOHCI_DMA_WRITE(ld[i], ld[i]);
929 db = &db_tr->db[db_tr->dbcnt];
930 if (xfer->send.pay_len > 0) {
933 if (xfer->mbuf == NULL) {
934 err = bus_dmamap_load(dbch->dmat, db_tr->dma_map,
935 &xfer->send.payload[0], xfer->send.pay_len,
936 fwohci_execute_db, db_tr,
939 /* XXX we can handle only 6 (=8-2) mbuf chains */
940 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map,
942 fwohci_execute_db2, db_tr,
948 device_printf(sc->fc.dev, "EFBIG.\n");
949 m0 = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
951 m_copydata(xfer->mbuf, 0,
952 xfer->mbuf->m_pkthdr.len,
954 m0->m_len = m0->m_pkthdr.len =
955 xfer->mbuf->m_pkthdr.len;
960 device_printf(sc->fc.dev, "m_getcl failed.\n");
964 kprintf("dmamap_load: err=%d\n", err);
965 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
966 BUS_DMASYNC_PREWRITE);
967 #if 0 /* OHCI_OUTPUT_MODE == 0 */
968 for (i = 2; i < db_tr->dbcnt; i++)
969 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd,
973 if (maxdesc < db_tr->dbcnt) {
974 maxdesc = db_tr->dbcnt;
976 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc);
980 FWOHCI_DMA_SET(db->db.desc.cmd,
981 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS);
982 FWOHCI_DMA_WRITE(db->db.desc.depend,
983 STAILQ_NEXT(db_tr, link)->bus_addr);
986 fsegment = db_tr->dbcnt;
987 if (dbch->pdb_tr != NULL) {
988 LAST_DB(dbch->pdb_tr, db);
989 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt);
991 dbch->pdb_tr = db_tr;
992 db_tr = STAILQ_NEXT(db_tr, link);
993 if(db_tr != dbch->bottom){
996 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n");
997 dbch->flags |= FWOHCI_DBCH_FULL;
1001 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1002 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1004 if(dbch->xferq.flag & FWXFERQ_RUNNING) {
1005 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);
1008 device_printf(sc->fc.dev, "start AT DMA status=%x\n",
1009 OREAD(sc, OHCI_DMACTL(off)));
1010 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment);
1011 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
1012 dbch->xferq.flag |= FWXFERQ_RUNNING;
1021 fwohci_start_atq(struct firewire_comm *fc)
1023 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1024 fwohci_start( sc, &(sc->atrq));
1029 fwohci_start_ats(struct firewire_comm *fc)
1031 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1032 fwohci_start( sc, &(sc->atrs));
1037 fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1040 struct fwohcidb_tr *tr;
1041 struct fwohcidb *db;
1042 struct fw_xfer *xfer;
1046 struct firewire_comm *fc = (struct firewire_comm *)sc;
1048 if(&sc->atrq == dbch){
1051 }else if(&sc->atrs == dbch){
1060 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD);
1061 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE);
1062 while(dbch->xferq.queued > 0){
1064 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT;
1065 if(!(status & OHCI_CNTL_DMA_ACTIVE)){
1066 if (fc->status != FWBUSRESET)
1067 /* maybe out of order?? */
1070 bus_dmamap_sync(dbch->dmat, tr->dma_map,
1071 BUS_DMASYNC_POSTWRITE);
1072 bus_dmamap_unload(dbch->dmat, tr->dma_map);
1077 if(status & OHCI_CNTL_DMA_DEAD) {
1079 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
1080 device_printf(sc->fc.dev, "force reset AT FIFO\n");
1081 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN);
1082 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN);
1083 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
1085 stat = status & FWOHCIEV_MASK;
1087 case FWOHCIEV_ACKPEND:
1088 case FWOHCIEV_ACKCOMPL:
1091 case FWOHCIEV_ACKBSA:
1092 case FWOHCIEV_ACKBSB:
1093 case FWOHCIEV_ACKBSX:
1094 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
1097 case FWOHCIEV_FLUSHED:
1098 case FWOHCIEV_ACKTARD:
1099 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
1102 case FWOHCIEV_MISSACK:
1103 case FWOHCIEV_UNDRRUN:
1104 case FWOHCIEV_OVRRUN:
1105 case FWOHCIEV_DESCERR:
1106 case FWOHCIEV_DTRDERR:
1107 case FWOHCIEV_TIMEOUT:
1108 case FWOHCIEV_TCODERR:
1109 case FWOHCIEV_UNKNOWN:
1110 case FWOHCIEV_ACKDERR:
1111 case FWOHCIEV_ACKTERR:
1113 device_printf(sc->fc.dev, "txd err=%2x %s\n",
1114 stat, fwohcicode[stat]);
1118 if (tr->xfer != NULL) {
1120 if (xfer->state == FWXF_RCVD) {
1123 kprintf("already rcvd\n");
1127 xfer->state = FWXF_SENT;
1128 if (err == EBUSY && fc->status != FWBUSRESET) {
1129 xfer->state = FWXF_BUSY;
1131 if (xfer->retry_req != NULL)
1132 xfer->retry_req(xfer);
1134 xfer->recv.pay_len = 0;
1137 } else if (stat != FWOHCIEV_ACKPEND) {
1138 if (stat != FWOHCIEV_ACKCOMPL)
1139 xfer->state = FWXF_SENTERR;
1141 xfer->recv.pay_len = 0;
1146 * The watchdog timer takes care of split
1147 * transcation timeout for ACKPEND case.
1150 kprintf("this shouldn't happen\n");
1152 dbch->xferq.queued --;
1156 tr = STAILQ_NEXT(tr, link);
1158 if (dbch->bottom == dbch->top) {
1159 /* we reaches the end of context program */
1160 if (firewire_debug && dbch->xferq.queued > 0)
1161 kprintf("queued > 0\n");
1166 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) {
1167 kprintf("make free slot\n");
1168 dbch->flags &= ~FWOHCI_DBCH_FULL;
1169 fwohci_start(sc, dbch);
1175 fwohci_db_free(struct fwohci_dbch *dbch)
1177 struct fwohcidb_tr *db_tr;
1180 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1183 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb;
1184 db_tr = STAILQ_NEXT(db_tr, link), idb++){
1185 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 &&
1186 db_tr->buf != NULL) {
1187 fwdma_free_size(dbch->dmat, db_tr->dma_map,
1188 db_tr->buf, dbch->xferq.psize);
1190 } else if (db_tr->dma_map != NULL)
1191 bus_dmamap_destroy(dbch->dmat, db_tr->dma_map);
1194 db_tr = STAILQ_FIRST(&dbch->db_trq);
1195 fwdma_free_multiseg(dbch->am);
1197 STAILQ_INIT(&dbch->db_trq);
1198 dbch->flags &= ~FWOHCI_DBCH_INIT;
1202 fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1205 struct fwohcidb_tr *db_tr;
1207 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0)
1210 /* create dma_tag for buffers */
1211 #define MAX_REQCOUNT 0xffff
1212 if (bus_dma_tag_create(/*parent*/ sc->fc.dmat,
1213 /*alignment*/ 1, /*boundary*/ 0,
1214 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT,
1215 /*highaddr*/ BUS_SPACE_MAXADDR,
1216 /*filter*/NULL, /*filterarg*/NULL,
1217 /*maxsize*/ dbch->xferq.psize,
1218 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1,
1219 /*maxsegsz*/ MAX_REQCOUNT,
1221 #if defined(__FreeBSD__) && __FreeBSD_version >= 501102
1222 /*lockfunc*/busdma_lock_mutex,
1228 /* allocate DB entries and attach one to each DMA channels */
1229 /* DB entry must start at 16 bytes bounary. */
1230 STAILQ_INIT(&dbch->db_trq);
1231 db_tr = (struct fwohcidb_tr *)
1232 kmalloc(sizeof(struct fwohcidb_tr) * dbch->ndb,
1233 M_FW, M_WAITOK | M_ZERO);
1235 kprintf("fwohci_db_init: malloc(1) failed\n");
1239 #define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc)
1240 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch),
1241 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK);
1242 if (dbch->am == NULL) {
1243 kprintf("fwohci_db_init: fwdma_malloc_multiseg failed\n");
1247 /* Attach DB to DMA ch. */
1248 for(idb = 0 ; idb < dbch->ndb ; idb++){
1250 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb);
1251 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb);
1252 /* create dmamap for buffers */
1253 /* XXX do we need 4bytes alignment tag? */
1254 /* XXX don't alloc dma_map for AR */
1255 if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) {
1256 kprintf("bus_dmamap_create failed\n");
1257 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */
1258 fwohci_db_free(dbch);
1261 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link);
1262 if (dbch->xferq.flag & FWXFERQ_EXTBUF) {
1263 if (idb % dbch->xferq.bnpacket == 0)
1264 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1265 ].start = (caddr_t)db_tr;
1266 if ((idb + 1) % dbch->xferq.bnpacket == 0)
1267 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1268 ].end = (caddr_t)db_tr;
1272 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next
1273 = STAILQ_FIRST(&dbch->db_trq);
1275 dbch->xferq.queued = 0;
1276 dbch->pdb_tr = NULL;
1277 dbch->top = STAILQ_FIRST(&dbch->db_trq);
1278 dbch->bottom = dbch->top;
1279 dbch->flags = FWOHCI_DBCH_INIT;
1283 fwohci_itx_disable(struct firewire_comm *fc, int dmach)
1285 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1288 OWRITE(sc, OHCI_ITCTLCLR(dmach),
1289 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S);
1290 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach);
1291 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach);
1292 /* XXX we cannot free buffers until the DMA really stops */
1293 tsleep((void *)&sleepch, FWPRI, "fwitxd", hz);
1294 fwohci_db_free(&sc->it[dmach]);
1295 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1300 fwohci_irx_disable(struct firewire_comm *fc, int dmach)
1302 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1305 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1306 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1307 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1308 /* XXX we cannot free buffers until the DMA really stops */
1309 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz);
1310 fwohci_db_free(&sc->ir[dmach]);
1311 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1315 #if BYTE_ORDER == BIG_ENDIAN
1317 fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld)
1319 qld[0] = FWOHCI_DMA_READ(qld[0]);
1325 fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1328 int idb, z, i, dmach = 0, ldesc;
1330 struct fwohcidb_tr *db_tr;
1331 struct fwohcidb *db;
1333 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){
1338 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
1339 if( &sc->it[dmach] == dbch){
1340 off = OHCI_ITOFF(dmach);
1348 if(dbch->xferq.flag & FWXFERQ_RUNNING)
1350 dbch->xferq.flag |= FWXFERQ_RUNNING;
1351 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1352 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1355 for (idb = 0; idb < dbch->ndb; idb ++) {
1356 fwohci_add_tx_buf(dbch, db_tr, idb);
1357 if(STAILQ_NEXT(db_tr, link) == NULL){
1361 ldesc = db_tr->dbcnt - 1;
1362 FWOHCI_DMA_WRITE(db[0].db.desc.depend,
1363 STAILQ_NEXT(db_tr, link)->bus_addr | z);
1364 db[ldesc].db.desc.depend = db[0].db.desc.depend;
1365 if(dbch->xferq.flag & FWXFERQ_EXTBUF){
1366 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
1368 db[ldesc].db.desc.cmd,
1369 OHCI_INTERRUPT_ALWAYS);
1370 /* OHCI 1.1 and above */
1373 OHCI_INTERRUPT_ALWAYS);
1376 db_tr = STAILQ_NEXT(db_tr, link);
1379 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf);
1384 fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1387 int idb, z, i, dmach = 0, ldesc;
1389 struct fwohcidb_tr *db_tr;
1390 struct fwohcidb *db;
1393 if(&sc->arrq == dbch){
1395 }else if(&sc->arrs == dbch){
1398 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
1399 if( &sc->ir[dmach] == dbch){
1400 off = OHCI_IROFF(dmach);
1409 if(dbch->xferq.flag & FWXFERQ_STREAM){
1410 if(dbch->xferq.flag & FWXFERQ_RUNNING)
1413 if(dbch->xferq.flag & FWXFERQ_RUNNING){
1418 dbch->xferq.flag |= FWXFERQ_RUNNING;
1419 dbch->top = STAILQ_FIRST(&dbch->db_trq);
1420 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1421 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1424 for (idb = 0; idb < dbch->ndb; idb ++) {
1425 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma);
1426 if (STAILQ_NEXT(db_tr, link) == NULL)
1429 ldesc = db_tr->dbcnt - 1;
1430 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend,
1431 STAILQ_NEXT(db_tr, link)->bus_addr | z);
1432 if(dbch->xferq.flag & FWXFERQ_EXTBUF){
1433 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
1435 db[ldesc].db.desc.cmd,
1436 OHCI_INTERRUPT_ALWAYS);
1438 db[ldesc].db.desc.depend,
1442 db_tr = STAILQ_NEXT(db_tr, link);
1445 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf);
1446 dbch->buf_offset = 0;
1447 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1448 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1449 if(dbch->xferq.flag & FWXFERQ_STREAM){
1452 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z);
1454 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
1459 fwohci_next_cycle(struct firewire_comm *fc, int cycle_now)
1461 int sec, cycle, cycle_match;
1463 cycle = cycle_now & 0x1fff;
1464 sec = cycle_now >> 13;
1465 #define CYCLE_MOD 0x10
1467 #define CYCLE_DELAY 8 /* min delay to start DMA */
1469 #define CYCLE_DELAY 7000 /* min delay to start DMA */
1471 cycle = cycle + CYCLE_DELAY;
1472 if (cycle >= 8000) {
1476 cycle = roundup2(cycle, CYCLE_MOD);
1477 if (cycle >= 8000) {
1484 cycle_match = ((sec << 13) | cycle) & 0x7ffff;
1486 return(cycle_match);
1490 fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach)
1492 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1494 unsigned short tag, ich;
1495 struct fwohci_dbch *dbch;
1496 int cycle_match, cycle_now, ldesc;
1498 struct fw_bulkxfer *first, *chunk, *prev;
1499 struct fw_xferq *it;
1501 dbch = &sc->it[dmach];
1504 tag = (it->flag >> 6) & 3;
1505 ich = it->flag & 0x3f;
1506 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) {
1507 dbch->ndb = it->bnpacket * it->bnchunk;
1509 fwohci_db_init(sc, dbch);
1510 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1512 err = fwohci_tx_enable(sc, dbch);
1517 ldesc = dbch->ndesc - 1;
1519 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link);
1520 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) {
1521 struct fwohcidb *db;
1523 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket,
1524 BUS_DMASYNC_PREWRITE);
1525 fwohci_txbufdb(sc, dmach, chunk);
1527 db = ((struct fwohcidb_tr *)(prev->end))->db;
1528 #if 0 /* XXX necessary? */
1529 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd,
1530 OHCI_BRANCH_ALWAYS);
1532 #if 0 /* if bulkxfer->npacket changes */
1533 db[ldesc].db.desc.depend = db[0].db.desc.depend =
1534 ((struct fwohcidb_tr *)
1535 (chunk->start))->bus_addr | dbch->ndesc;
1537 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc);
1538 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
1541 STAILQ_REMOVE_HEAD(&it->stvalid, link);
1542 STAILQ_INSERT_TAIL(&it->stdma, chunk, link);
1545 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1546 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1548 stat = OREAD(sc, OHCI_ITCTL(dmach));
1549 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S))
1550 kprintf("stat 0x%x\n", stat);
1552 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S))
1556 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1558 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach);
1559 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach);
1560 OWRITE(sc, OHCI_IT_MASK, 1 << dmach);
1561 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT);
1563 first = STAILQ_FIRST(&it->stdma);
1564 OWRITE(sc, OHCI_ITCMD(dmach),
1565 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc);
1566 if (firewire_debug) {
1567 kprintf("fwohci_itxbuf_enable: kick 0x%08x\n", stat);
1569 dump_dma(sc, ITX_CH + dmach);
1572 if ((stat & OHCI_CNTL_DMA_RUN) == 0) {
1574 /* Don't start until all chunks are buffered */
1575 if (STAILQ_FIRST(&it->stfree) != NULL)
1579 /* Clear cycle match counter bits */
1580 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000);
1582 /* 2bit second + 13bit cycle */
1583 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff;
1584 cycle_match = fwohci_next_cycle(fc, cycle_now);
1586 OWRITE(sc, OHCI_ITCTL(dmach),
1587 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16)
1588 | OHCI_CNTL_DMA_RUN);
1590 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN);
1592 if (firewire_debug) {
1593 kprintf("cycle_match: 0x%04x->0x%04x\n",
1594 cycle_now, cycle_match);
1595 dump_dma(sc, ITX_CH + dmach);
1596 dump_db(sc, ITX_CH + dmach);
1598 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) {
1599 device_printf(sc->fc.dev,
1600 "IT DMA underrun (0x%08x)\n", stat);
1601 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE);
1608 fwohci_irx_enable(struct firewire_comm *fc, int dmach)
1610 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1612 unsigned short tag, ich;
1614 struct fwohci_dbch *dbch;
1615 struct fwohcidb_tr *db_tr;
1616 struct fw_bulkxfer *first, *prev, *chunk;
1617 struct fw_xferq *ir;
1619 dbch = &sc->ir[dmach];
1622 if ((ir->flag & FWXFERQ_RUNNING) == 0) {
1623 tag = (ir->flag >> 6) & 3;
1624 ich = ir->flag & 0x3f;
1625 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich);
1628 dbch->ndb = ir->bnpacket * ir->bnchunk;
1630 fwohci_db_init(sc, dbch);
1631 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1633 err = fwohci_rx_enable(sc, dbch);
1638 first = STAILQ_FIRST(&ir->stfree);
1639 if (first == NULL) {
1640 device_printf(fc->dev, "IR DMA no free chunk\n");
1644 ldesc = dbch->ndesc - 1;
1646 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link);
1647 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) {
1648 struct fwohcidb *db;
1650 #if 1 /* XXX for if_fwe */
1651 if (chunk->mbuf != NULL) {
1652 db_tr = (struct fwohcidb_tr *)(chunk->start);
1654 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map,
1655 chunk->mbuf, fwohci_execute_db2, db_tr,
1657 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd,
1658 OHCI_UPDATE | OHCI_INPUT_LAST |
1659 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS);
1662 db = ((struct fwohcidb_tr *)(chunk->end))->db;
1663 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0);
1664 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf);
1666 db = ((struct fwohcidb_tr *)(prev->end))->db;
1667 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
1669 STAILQ_REMOVE_HEAD(&ir->stfree, link);
1670 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link);
1673 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1674 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1676 stat = OREAD(sc, OHCI_IRCTL(dmach));
1677 if (stat & OHCI_CNTL_DMA_ACTIVE)
1679 if (stat & OHCI_CNTL_DMA_RUN) {
1680 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1681 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat);
1685 kprintf("start IR DMA 0x%x\n", stat);
1686 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1687 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1688 OWRITE(sc, OHCI_IR_MASK, 1 << dmach);
1689 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000);
1690 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR);
1691 OWRITE(sc, OHCI_IRCMD(dmach),
1692 ((struct fwohcidb_tr *)(first->start))->bus_addr
1694 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN);
1695 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR);
1697 dump_db(sc, IRX_CH + dmach);
1703 fwohci_stop(struct fwohci_softc *sc, device_t dev)
1707 /* Now stopping all DMA channel */
1708 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
1709 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
1710 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1711 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1713 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
1714 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
1715 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
1718 /* FLUSH FIFO and reset Transmitter/Reciever */
1719 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
1721 /* Stop interrupt */
1722 OWRITE(sc, FWOHCI_INTMASKCLR,
1723 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID
1725 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
1726 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
1727 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS
1728 | OHCI_INT_PHY_BUS_R);
1730 if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0)
1731 fw_drain_txq(&sc->fc);
1733 /* XXX Link down? Bus reset? */
1738 fwohci_resume(struct fwohci_softc *sc, device_t dev)
1741 struct fw_xferq *ir;
1742 struct fw_bulkxfer *chunk;
1744 fwohci_reset(sc, dev);
1745 /* XXX resume isochronus receive automatically. (how about TX?) */
1746 for(i = 0; i < sc->fc.nisodma; i ++) {
1747 ir = &sc->ir[i].xferq;
1748 if((ir->flag & FWXFERQ_RUNNING) != 0) {
1749 device_printf(sc->fc.dev,
1750 "resume iso receive ch: %d\n", i);
1751 ir->flag &= ~FWXFERQ_RUNNING;
1752 /* requeue stdma to stfree */
1753 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) {
1754 STAILQ_REMOVE_HEAD(&ir->stdma, link);
1755 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link);
1757 sc->fc.irx_enable(&sc->fc, i);
1761 bus_generic_resume(dev);
1762 sc->fc.ibr(&sc->fc);
1768 fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count)
1770 u_int32_t irstat, itstat;
1772 struct firewire_comm *fc = (struct firewire_comm *)sc;
1775 if(stat & OREAD(sc, FWOHCI_INTMASK))
1776 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n",
1777 stat & OHCI_INT_EN ? "DMA_EN ":"",
1778 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"",
1779 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"",
1780 stat & OHCI_INT_ERR ? "INT_ERR ":"",
1781 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"",
1782 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"",
1783 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"",
1784 stat & OHCI_INT_CYC_START ? "CYC_START ":"",
1785 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"",
1786 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"",
1787 stat & OHCI_INT_PHY_SID ? "SID ":"",
1788 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"",
1789 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"",
1790 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"",
1791 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"",
1792 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"",
1793 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"",
1794 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"",
1795 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"",
1796 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"",
1797 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"",
1798 stat, OREAD(sc, FWOHCI_INTMASK)
1802 if(stat & OHCI_INT_PHY_BUS_R ){
1803 if (fc->status == FWBUSRESET)
1805 /* Disable bus reset interrupt until sid recv. */
1806 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R);
1808 device_printf(fc->dev, "BUS reset\n");
1809 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST);
1810 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC);
1812 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1813 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING;
1814 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1815 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING;
1818 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R);
1821 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0]));
1822 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2]));
1825 if((stat & OHCI_INT_DMA_IR )){
1827 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR);
1829 #if defined(__DragonFly__) || __FreeBSD_version < 500000
1830 irstat = sc->irstat;
1833 irstat = atomic_readandclear_int(&sc->irstat);
1835 for(i = 0; i < fc->nisodma ; i++){
1836 struct fwohci_dbch *dbch;
1838 if((irstat & (1 << i)) != 0){
1840 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) {
1841 device_printf(sc->fc.dev,
1842 "dma(%d) not active\n", i);
1845 fwohci_rbuf_update(sc, i);
1849 if((stat & OHCI_INT_DMA_IT )){
1851 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT);
1853 #if defined(__DragonFly__) || __FreeBSD_version < 500000
1854 itstat = sc->itstat;
1857 itstat = atomic_readandclear_int(&sc->itstat);
1859 for(i = 0; i < fc->nisodma ; i++){
1860 if((itstat & (1 << i)) != 0){
1861 fwohci_tbuf_update(sc, i);
1865 if((stat & OHCI_INT_DMA_PRRS )){
1867 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS);
1870 dump_dma(sc, ARRS_CH);
1871 dump_db(sc, ARRS_CH);
1873 fwohci_arcv(sc, &sc->arrs, count);
1875 if((stat & OHCI_INT_DMA_PRRQ )){
1877 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ);
1880 dump_dma(sc, ARRQ_CH);
1881 dump_db(sc, ARRQ_CH);
1883 fwohci_arcv(sc, &sc->arrq, count);
1885 if(stat & OHCI_INT_PHY_SID){
1886 u_int32_t *buf, node_id;
1890 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID);
1892 /* Enable bus reset interrupt */
1893 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R);
1894 /* Allow async. request to us */
1895 OWRITE(sc, OHCI_AREQHI, 1 << 31);
1896 /* XXX insecure ?? */
1897 OWRITE(sc, OHCI_PREQHI, 0x7fffffff);
1898 OWRITE(sc, OHCI_PREQLO, 0xffffffff);
1899 OWRITE(sc, OHCI_PREQUPPER, 0x10000);
1900 /* Set ATRetries register */
1901 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff);
1903 ** Checking whether the node is root or not. If root, turn on
1906 node_id = OREAD(sc, FWOHCI_NODEID);
1907 plen = OREAD(sc, OHCI_SID_CNT);
1909 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ",
1910 node_id, (plen >> 16) & 0xff);
1911 if (!(node_id & OHCI_NODE_VALID)) {
1912 kprintf("Bus reset failure\n");
1915 if (node_id & OHCI_NODE_ROOT) {
1916 kprintf("CYCLEMASTER mode\n");
1917 OWRITE(sc, OHCI_LNKCTL,
1918 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER);
1920 kprintf("non CYCLEMASTER mode\n");
1921 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR);
1922 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER);
1924 fc->nodeid = node_id & 0x3f;
1926 if (plen & OHCI_SID_ERR) {
1927 device_printf(fc->dev, "SID Error\n");
1930 plen &= OHCI_SID_CNT_MASK;
1931 if (plen < 4 || plen > OHCI_SIDSIZE) {
1932 device_printf(fc->dev, "invalid SID len = %d\n", plen);
1935 plen -= 4; /* chop control info */
1936 buf = (u_int32_t *)kmalloc(OHCI_SIDSIZE, M_FW, M_INTWAIT);
1938 device_printf(fc->dev, "malloc failed\n");
1941 for (i = 0; i < plen / 4; i ++)
1942 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]);
1944 /* pending all pre-bus_reset packets */
1945 fwohci_txd(sc, &sc->atrq);
1946 fwohci_txd(sc, &sc->atrs);
1947 fwohci_arcv(sc, &sc->arrs, -1);
1948 fwohci_arcv(sc, &sc->arrq, -1);
1951 fw_sidrcv(fc, buf, plen);
1955 if((stat & OHCI_INT_DMA_ATRQ )){
1957 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ);
1959 fwohci_txd(sc, &(sc->atrq));
1961 if((stat & OHCI_INT_DMA_ATRS )){
1963 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS);
1965 fwohci_txd(sc, &(sc->atrs));
1967 if((stat & OHCI_INT_PW_ERR )){
1969 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR);
1971 device_printf(fc->dev, "posted write error\n");
1973 if((stat & OHCI_INT_ERR )){
1975 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR);
1977 device_printf(fc->dev, "unrecoverable error\n");
1979 if((stat & OHCI_INT_PHY_INT)) {
1981 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT);
1983 device_printf(fc->dev, "phy int\n");
1989 #if FWOHCI_TASKQUEUE
1991 fwohci_complete(void *arg, int pending)
1993 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
1997 stat = atomic_readandclear_int(&sc->intstat);
1999 fwohci_intr_body(sc, stat, -1);
2007 fwochi_check_stat(struct fwohci_softc *sc)
2009 u_int32_t stat, irstat, itstat;
2011 stat = OREAD(sc, FWOHCI_INTSTAT);
2012 if (stat == 0xffffffff) {
2013 device_printf(sc->fc.dev,
2014 "device physically ejected?\n");
2019 OWRITE(sc, FWOHCI_INTSTATCLR, stat);
2021 if (stat & OHCI_INT_DMA_IR) {
2022 irstat = OREAD(sc, OHCI_IR_STAT);
2023 OWRITE(sc, OHCI_IR_STATCLR, irstat);
2024 atomic_set_int(&sc->irstat, irstat);
2026 if (stat & OHCI_INT_DMA_IT) {
2027 itstat = OREAD(sc, OHCI_IT_STAT);
2028 OWRITE(sc, OHCI_IT_STATCLR, itstat);
2029 atomic_set_int(&sc->itstat, itstat);
2035 fwohci_intr(void *arg)
2037 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
2039 #if !FWOHCI_TASKQUEUE
2040 u_int32_t bus_reset = 0;
2043 if (!(sc->intmask & OHCI_INT_EN)) {
2048 #if !FWOHCI_TASKQUEUE
2051 stat = fwochi_check_stat(sc);
2052 if (stat == 0 || stat == 0xffffffff)
2054 #if FWOHCI_TASKQUEUE
2055 atomic_set_int(&sc->intstat, stat);
2056 /* XXX mask bus reset intr. during bus reset phase */
2058 taskqueue_enqueue(taskqueue_swi_giant, &sc->fwohci_task_complete);
2060 /* We cannot clear bus reset event during bus reset phase */
2061 if ((stat & ~bus_reset) == 0)
2063 bus_reset = stat & OHCI_INT_PHY_BUS_R;
2064 fwohci_intr_body(sc, stat, -1);
2070 fwohci_poll(struct firewire_comm *fc, int quick, int count)
2073 struct fwohci_softc *sc;
2076 sc = (struct fwohci_softc *)fc;
2077 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT |
2078 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ |
2079 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS;
2085 stat = fwochi_check_stat(sc);
2086 if (stat == 0 || stat == 0xffffffff)
2090 fwohci_intr_body(sc, stat, count);
2095 fwohci_set_intr(struct firewire_comm *fc, int enable)
2097 struct fwohci_softc *sc;
2099 sc = (struct fwohci_softc *)fc;
2101 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable);
2103 sc->intmask |= OHCI_INT_EN;
2104 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN);
2106 sc->intmask &= ~OHCI_INT_EN;
2107 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN);
2112 fwohci_tbuf_update(struct fwohci_softc *sc, int dmach)
2114 struct firewire_comm *fc = &sc->fc;
2115 struct fwohcidb *db;
2116 struct fw_bulkxfer *chunk;
2117 struct fw_xferq *it;
2118 u_int32_t stat, count;
2122 ldesc = sc->it[dmach].ndesc - 1;
2123 crit_enter(); /* unnecessary? */
2124 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD);
2126 dump_db(sc, ITX_CH + dmach);
2127 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) {
2128 db = ((struct fwohcidb_tr *)(chunk->end))->db;
2129 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res)
2130 >> OHCI_STATUS_SHIFT;
2131 db = ((struct fwohcidb_tr *)(chunk->start))->db;
2133 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res)
2137 STAILQ_REMOVE_HEAD(&it->stdma, link);
2138 switch (stat & FWOHCIEV_MASK){
2139 case FWOHCIEV_ACKCOMPL:
2141 device_printf(fc->dev, "0x%08x\n", count);
2145 device_printf(fc->dev,
2146 "Isochronous transmit err %02x(%s)\n",
2147 stat, fwohcicode[stat & 0x1f]);
2149 STAILQ_INSERT_TAIL(&it->stfree, chunk, link);
2158 fwohci_rbuf_update(struct fwohci_softc *sc, int dmach)
2160 struct firewire_comm *fc = &sc->fc;
2161 struct fwohcidb_tr *db_tr;
2162 struct fw_bulkxfer *chunk;
2163 struct fw_xferq *ir;
2168 ldesc = sc->ir[dmach].ndesc - 1;
2173 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD);
2174 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) {
2175 db_tr = (struct fwohcidb_tr *)chunk->end;
2176 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res)
2177 >> OHCI_STATUS_SHIFT;
2181 if (chunk->mbuf != NULL) {
2182 bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map,
2183 BUS_DMASYNC_POSTREAD);
2184 bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map);
2185 } else if (ir->buf != NULL) {
2186 fwdma_sync_multiseg(ir->buf, chunk->poffset,
2187 ir->bnpacket, BUS_DMASYNC_POSTREAD);
2190 kprintf("fwohci_rbuf_update: this shouldn't happend\n");
2193 STAILQ_REMOVE_HEAD(&ir->stdma, link);
2194 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link);
2195 switch (stat & FWOHCIEV_MASK) {
2196 case FWOHCIEV_ACKCOMPL:
2200 chunk->resp = EINVAL;
2201 device_printf(fc->dev,
2202 "Isochronous receive err %02x(%s)\n",
2203 stat, fwohcicode[stat & 0x1f]);
2209 if (ir->flag & FWXFERQ_HANDLER)
2217 dump_dma(struct fwohci_softc *sc, u_int32_t ch)
2219 u_int32_t off, cntl, stat, cmd, match;
2229 }else if(ch < IRX_CH){
2230 off = OHCI_ITCTL(ch - ITX_CH);
2232 off = OHCI_IRCTL(ch - IRX_CH);
2234 cntl = stat = OREAD(sc, off);
2235 cmd = OREAD(sc, off + 0xc);
2236 match = OREAD(sc, off + 0x10);
2238 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n",
2245 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n",
2247 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
2248 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
2249 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
2250 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
2251 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
2252 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
2253 fwohcicode[stat & 0x1f],
2257 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch);
2262 dump_db(struct fwohci_softc *sc, u_int32_t ch)
2264 struct fwohci_dbch *dbch;
2265 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL;
2266 struct fwohcidb *curr = NULL, *prev, *next = NULL;
2281 }else if(ch < IRX_CH){
2282 off = OHCI_ITCTL(ch - ITX_CH);
2283 dbch = &sc->it[ch - ITX_CH];
2285 off = OHCI_IRCTL(ch - IRX_CH);
2286 dbch = &sc->ir[ch - IRX_CH];
2288 cmd = OREAD(sc, off + 0xc);
2290 if( dbch->ndb == 0 ){
2291 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch);
2296 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){
2301 cp = STAILQ_NEXT(pp, link);
2306 np = STAILQ_NEXT(cp, link);
2307 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){
2308 if ((cmd & 0xfffffff0) == cp->bus_addr) {
2318 pp = STAILQ_NEXT(pp, link);
2324 kprintf("Prev DB %d\n", ch);
2325 print_db(pp, prev, ch, dbch->ndesc);
2327 kprintf("Current DB %d\n", ch);
2328 print_db(cp, curr, ch, dbch->ndesc);
2330 kprintf("Next DB %d\n", ch);
2331 print_db(np, next, ch, dbch->ndesc);
2334 kprintf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd);
2340 print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db,
2341 u_int32_t ch, u_int32_t max)
2348 kprintf("No Descriptor is found\n");
2352 kprintf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n",
2364 for( i = 0 ; i <= max ; i ++){
2365 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd);
2366 res = FWOHCI_DMA_READ(db[i].db.desc.res);
2367 key = cmd & OHCI_KEY_MASK;
2368 stat = res >> OHCI_STATUS_SHIFT;
2369 #if defined(__DragonFly__) || __FreeBSD_version < 500000
2370 kprintf("%08x %s %s %s %s %5d %08x %08x %04x:%04x",
2373 kprintf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x",
2374 (uintmax_t)db_tr->bus_addr,
2376 dbcode[(cmd >> 28) & 0xf],
2377 dbkey[(cmd >> 24) & 0x7],
2378 dbcond[(cmd >> 20) & 0x3],
2379 dbcond[(cmd >> 18) & 0x3],
2380 cmd & OHCI_COUNT_MASK,
2381 FWOHCI_DMA_READ(db[i].db.desc.addr),
2382 FWOHCI_DMA_READ(db[i].db.desc.depend),
2384 res & OHCI_COUNT_MASK);
2386 kprintf(" %s%s%s%s%s%s %s(%x)\n",
2387 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
2388 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
2389 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
2390 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
2391 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
2392 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
2393 fwohcicode[stat & 0x1f],
2397 kprintf(" Nostat\n");
2399 if(key == OHCI_KEY_ST2 ){
2400 kprintf("0x%08x 0x%08x 0x%08x 0x%08x\n",
2401 FWOHCI_DMA_READ(db[i+1].db.immed[0]),
2402 FWOHCI_DMA_READ(db[i+1].db.immed[1]),
2403 FWOHCI_DMA_READ(db[i+1].db.immed[2]),
2404 FWOHCI_DMA_READ(db[i+1].db.immed[3]));
2406 if(key == OHCI_KEY_DEVICE){
2409 if((cmd & OHCI_BRANCH_MASK)
2410 == OHCI_BRANCH_ALWAYS){
2413 if((cmd & OHCI_CMD_MASK)
2414 == OHCI_OUTPUT_LAST){
2417 if((cmd & OHCI_CMD_MASK)
2418 == OHCI_INPUT_LAST){
2421 if(key == OHCI_KEY_ST2 ){
2429 fwohci_ibr(struct firewire_comm *fc)
2431 struct fwohci_softc *sc;
2434 device_printf(fc->dev, "Initiate bus reset\n");
2435 sc = (struct fwohci_softc *)fc;
2438 * Set root hold-off bit so that non cyclemaster capable node
2439 * shouldn't became the root node.
2442 fun = fwphy_rddata(sc, FW_PHY_IBR_REG);
2443 fun |= FW_PHY_IBR | FW_PHY_RHB;
2444 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun);
2445 #else /* Short bus reset */
2446 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG);
2447 fun |= FW_PHY_ISBR | FW_PHY_RHB;
2448 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun);
2453 fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer)
2455 struct fwohcidb_tr *db_tr, *fdb_tr;
2456 struct fwohci_dbch *dbch;
2457 struct fwohcidb *db;
2459 struct fwohci_txpkthdr *ohcifp;
2460 unsigned short chtag;
2463 dbch = &sc->it[dmach];
2464 chtag = sc->it[dmach].xferq.flag & 0xff;
2466 db_tr = (struct fwohcidb_tr *)(bulkxfer->start);
2467 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end);
2469 device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr);
2471 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) {
2473 fp = (struct fw_pkt *)db_tr->buf;
2474 ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed;
2475 ohcifp->mode.ld[0] = fp->mode.ld[0];
2476 ohcifp->mode.common.spd = 0 & 0x7;
2477 ohcifp->mode.stream.len = fp->mode.stream.len;
2478 ohcifp->mode.stream.chtag = chtag;
2479 ohcifp->mode.stream.tcode = 0xa;
2480 #if BYTE_ORDER == BIG_ENDIAN
2481 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]);
2482 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]);
2485 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK);
2486 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len);
2487 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0);
2488 #if 0 /* if bulkxfer->npackets changes */
2489 db[2].db.desc.cmd = OHCI_OUTPUT_LAST
2491 | OHCI_BRANCH_ALWAYS;
2492 db[0].db.desc.depend =
2493 = db[dbch->ndesc - 1].db.desc.depend
2494 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc;
2496 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc);
2497 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc);
2499 bulkxfer->end = (caddr_t)db_tr;
2500 db_tr = STAILQ_NEXT(db_tr, link);
2502 db = ((struct fwohcidb_tr *)bulkxfer->end)->db;
2503 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf);
2504 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf);
2505 #if 0 /* if bulkxfer->npackets changes */
2506 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS;
2507 /* OHCI 1.1 and above */
2508 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS;
2511 db_tr = (struct fwohcidb_tr *)bulkxfer->start;
2512 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end;
2513 device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr);
2519 fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr,
2522 struct fwohcidb *db = db_tr->db;
2523 struct fw_xferq *it;
2531 db_tr->buf = fwdma_v_addr(it->buf, poffset);
2534 FWOHCI_DMA_WRITE(db[0].db.desc.cmd,
2535 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8);
2536 FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0);
2537 bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed));
2538 FWOHCI_DMA_WRITE(db[2].db.desc.addr,
2539 fwdma_bus_addr(it->buf, poffset) + sizeof(u_int32_t));
2541 FWOHCI_DMA_WRITE(db[2].db.desc.cmd,
2542 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS);
2544 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0);
2545 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0);
2551 fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr,
2552 int poffset, struct fwdma_alloc *dummy_dma)
2554 struct fwohcidb *db = db_tr->db;
2555 struct fw_xferq *ir;
2561 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) {
2562 db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map,
2563 ir->psize, &dbuf[0], BUS_DMA_NOWAIT);
2564 if (db_tr->buf == NULL)
2567 dsiz[0] = ir->psize;
2568 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2569 BUS_DMASYNC_PREREAD);
2572 if (dummy_dma != NULL) {
2573 dsiz[db_tr->dbcnt] = sizeof(u_int32_t);
2574 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr;
2576 dsiz[db_tr->dbcnt] = ir->psize;
2577 if (ir->buf != NULL) {
2578 db_tr->buf = fwdma_v_addr(ir->buf, poffset);
2579 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset);
2583 for(i = 0 ; i < db_tr->dbcnt ; i++){
2584 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]);
2585 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]);
2586 if (ir->flag & FWXFERQ_STREAM) {
2587 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE);
2589 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]);
2591 ldesc = db_tr->dbcnt - 1;
2592 if (ir->flag & FWXFERQ_STREAM) {
2593 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST);
2595 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS);
2601 fwohci_arcv_swap(struct fw_pkt *fp, int len)
2606 #if BYTE_ORDER == BIG_ENDIAN
2610 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]);
2612 kprintf("ld0: x%08x\n", ld0);
2614 fp0 = (struct fw_pkt *)&ld0;
2615 /* determine length to swap */
2616 switch (fp0->mode.common.tcode) {
2621 case FWOHCITCODE_PHY:
2632 kprintf("Unknown tcode %d\n", fp0->mode.common.tcode);
2635 hlen = tinfo[fp0->mode.common.tcode].hdr_len;
2638 kprintf("splitted header\n");
2641 #if BYTE_ORDER == BIG_ENDIAN
2642 for(i = 0; i < slen/4; i ++)
2643 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]);
2649 fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp)
2651 struct tcode_info *info;
2654 info = &tinfo[fp->mode.common.tcode];
2655 r = info->hdr_len + sizeof(u_int32_t);
2656 if ((info->flag & FWTI_BLOCK_ASY) != 0)
2657 r += roundup2(fp->mode.wreqb.len, sizeof(u_int32_t));
2659 if (r == sizeof(u_int32_t))
2661 device_printf(sc->fc.dev, "Unknown tcode %d\n",
2662 fp->mode.common.tcode);
2664 if (r > dbch->xferq.psize) {
2665 device_printf(sc->fc.dev, "Invalid packet length %d\n", r);
2673 fwohci_arcv_free_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr)
2675 struct fwohcidb *db = &db_tr->db[0];
2677 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf);
2678 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize);
2679 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1);
2680 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
2681 dbch->bottom = db_tr;
2685 fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
2687 struct fwohcidb_tr *db_tr;
2688 struct iovec vec[2];
2689 struct fw_pkt pktbuf;
2693 u_int32_t stat, off, status;
2695 int len, plen, hlen, pcnt, offset;
2699 if(&sc->arrq == dbch){
2701 }else if(&sc->arrs == dbch){
2710 /* XXX we cannot handle a packet which lies in more than two buf */
2711 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD);
2712 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE);
2713 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT;
2714 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK;
2716 kprintf("status 0x%04x, resCount 0x%04x\n", status, resCount);
2718 while (status & OHCI_CNTL_DMA_ACTIVE) {
2719 len = dbch->xferq.psize - resCount;
2720 ld = (u_int8_t *)db_tr->buf;
2721 if (dbch->pdb_tr == NULL) {
2722 len -= dbch->buf_offset;
2723 ld += dbch->buf_offset;
2726 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2727 BUS_DMASYNC_POSTREAD);
2729 if (count >= 0 && count-- == 0)
2731 if(dbch->pdb_tr != NULL){
2732 /* we have a fragment in previous buffer */
2735 offset = dbch->buf_offset;
2738 buf = dbch->pdb_tr->buf + offset;
2739 rlen = dbch->xferq.psize - offset;
2741 kprintf("rlen=%d, offset=%d\n",
2742 rlen, dbch->buf_offset);
2743 if (dbch->buf_offset < 0) {
2744 /* splitted in header, pull up */
2747 p = (char *)&pktbuf;
2748 bcopy(buf, p, rlen);
2750 /* this must be too long but harmless */
2751 rlen = sizeof(pktbuf) - rlen;
2753 kprintf("why rlen < 0\n");
2754 bcopy(db_tr->buf, p, rlen);
2757 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf));
2759 kprintf("hlen < 0 shouldn't happen");
2761 offset = sizeof(pktbuf);
2762 vec[0].iov_base = (char *)&pktbuf;
2763 vec[0].iov_len = offset;
2765 /* splitted in payload */
2767 vec[0].iov_base = buf;
2768 vec[0].iov_len = rlen;
2770 fp=(struct fw_pkt *)vec[0].iov_base;
2773 /* no fragment in previous buffer */
2774 fp=(struct fw_pkt *)ld;
2775 hlen = fwohci_arcv_swap(fp, len);
2777 /* XXX need reset */
2780 dbch->pdb_tr = db_tr;
2781 dbch->buf_offset = - dbch->buf_offset;
2784 kprintf("resCount = %d !?\n",
2786 /* XXX clear pdb_tr */
2792 plen = fwohci_get_plen(sc, dbch, fp) - offset;
2794 /* minimum header size + trailer
2795 = sizeof(fw_pkt) so this shouldn't happens */
2796 kprintf("plen(%d) is negative! offset=%d\n",
2798 /* XXX clear pdb_tr */
2804 dbch->pdb_tr = db_tr;
2806 kprintf("splitted payload\n");
2809 kprintf("resCount = %d !?\n",
2811 /* XXX clear pdb_tr */
2814 vec[nvec].iov_base = ld;
2815 vec[nvec].iov_len = plen;
2819 dbch->buf_offset = ld - (u_int8_t *)db_tr->buf;
2821 kprintf("nvec == 0\n");
2823 /* DMA result-code will be written at the tail of packet */
2824 #if BYTE_ORDER == BIG_ENDIAN
2825 stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16;
2827 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat;
2830 kprintf("plen: %d, stat %x\n",
2833 spd = (stat >> 5) & 0x3;
2836 case FWOHCIEV_ACKPEND:
2838 kprintf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode);
2841 case FWOHCIEV_ACKCOMPL:
2843 struct fw_rcv_buf rb;
2845 if ((vec[nvec-1].iov_len -=
2846 sizeof(struct fwohci_trailer)) == 0)
2855 case FWOHCIEV_BUSRST:
2856 if (sc->fc.status != FWBUSRESET)
2857 kprintf("got BUSRST packet!?\n");
2860 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]);
2867 if (dbch->pdb_tr != NULL) {
2868 fwohci_arcv_free_buf(dbch, dbch->pdb_tr);
2869 dbch->pdb_tr = NULL;
2874 if (resCount == 0) {
2875 /* done on this buffer */
2876 if (dbch->pdb_tr == NULL) {
2877 fwohci_arcv_free_buf(dbch, db_tr);
2878 dbch->buf_offset = 0;
2880 if (dbch->pdb_tr != db_tr)
2881 kprintf("pdb_tr != db_tr\n");
2882 db_tr = STAILQ_NEXT(db_tr, link);
2883 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2884 >> OHCI_STATUS_SHIFT;
2885 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2887 /* XXX check buffer overrun */
2890 dbch->buf_offset = dbch->xferq.psize - resCount;
2893 /* XXX make sure DMA is not dead */
2897 kprintf("fwohci_arcv: no packets\n");