drivers/irqchip/irq-mips-gic.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
   7  * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
   8  */
   9
  10 #define pr_fmt(fmt) "irq-mips-gic: " fmt
  11
  12 #include <linux/bitfield.h>
  13 #include <linux/bitmap.h>
  14 #include <linux/clocksource.h>
  15 #include <linux/cpuhotplug.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/irq.h>
  19 #include <linux/irqchip.h>
  20 #include <linux/irqdomain.h>
  21 #include <linux/of_address.h>
  22 #include <linux/percpu.h>
  23 #include <linux/sched.h>
  24 #include <linux/smp.h>
  25
  26 #include <asm/mips-cps.h>
  27 #include <asm/setup.h>
  28 #include <asm/traps.h>
  29
  30 #include <dt-bindings/interrupt-controller/mips-gic.h>
  31
  32 #define GIC_MAX_INTRS           256
  33 #define GIC_MAX_LONGS           BITS_TO_LONGS(GIC_MAX_INTRS)
  34
  35 /* Add 2 to convert GIC CPU pin to core interrupt */
  36 #define GIC_CPU_PIN_OFFSET      2
  37
  38 /* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
  39 #define GIC_PIN_TO_VEC_OFFSET   1
  40
  41 /* Convert between local/shared IRQ number and GIC HW IRQ number. */
  42 #define GIC_LOCAL_HWIRQ_BASE    0
  43 #define GIC_LOCAL_TO_HWIRQ(x)   (GIC_LOCAL_HWIRQ_BASE + (x))
  44 #define GIC_HWIRQ_TO_LOCAL(x)   ((x) - GIC_LOCAL_HWIRQ_BASE)
  45 #define GIC_SHARED_HWIRQ_BASE   GIC_NUM_LOCAL_INTRS
  46 #define GIC_SHARED_TO_HWIRQ(x)  (GIC_SHARED_HWIRQ_BASE + (x))
  47 #define GIC_HWIRQ_TO_SHARED(x)  ((x) - GIC_SHARED_HWIRQ_BASE)
  48
  49 void __iomem *mips_gic_base;
  50
  51 static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[GIC_MAX_LONGS], pcpu_masks);
  52
  53 static DEFINE_SPINLOCK(gic_lock);
  54 static struct irq_domain *gic_irq_domain;
  55 static struct irq_domain *gic_ipi_domain;
  56 static int gic_shared_intrs;
  57 static unsigned int gic_cpu_pin;
  58 static unsigned int timer_cpu_pin;
  59 static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
  60 static DECLARE_BITMAP(ipi_resrv, GIC_MAX_INTRS);
  61 static DECLARE_BITMAP(ipi_available, GIC_MAX_INTRS);
  62
  63 static struct gic_all_vpes_chip_data {
  64         u32     map;
  65         bool    mask;
  66 } gic_all_vpes_chip_data[GIC_NUM_LOCAL_INTRS];
  67
  68 static void gic_clear_pcpu_masks(unsigned int intr)
  69 {
  70         unsigned int i;
  71
  72         /* Clear the interrupt's bit in all pcpu_masks */
  73         for_each_possible_cpu(i)
  74                 clear_bit(intr, per_cpu_ptr(pcpu_masks, i));
  75 }
  76
  77 static bool gic_local_irq_is_routable(int intr)
  78 {
  79         u32 vpe_ctl;
  80
  81         /* All local interrupts are routable in EIC mode. */
  82         if (cpu_has_veic)
  83                 return true;
  84
  85         vpe_ctl = read_gic_vl_ctl();
  86         switch (intr) {
  87         case GIC_LOCAL_INT_TIMER:
  88                 return vpe_ctl & GIC_VX_CTL_TIMER_ROUTABLE;
  89         case GIC_LOCAL_INT_PERFCTR:
  90                 return vpe_ctl & GIC_VX_CTL_PERFCNT_ROUTABLE;
  91         case GIC_LOCAL_INT_FDC:
  92                 return vpe_ctl & GIC_VX_CTL_FDC_ROUTABLE;
  93         case GIC_LOCAL_INT_SWINT0:
  94         case GIC_LOCAL_INT_SWINT1:
  95                 return vpe_ctl & GIC_VX_CTL_SWINT_ROUTABLE;
  96         default:
  97                 return true;
  98         }
  99 }
 100
 101 static void gic_bind_eic_interrupt(int irq, int set)
 102 {
 103         /* Convert irq vector # to hw int # */
 104         irq -= GIC_PIN_TO_VEC_OFFSET;
 105
 106         /* Set irq to use shadow set */
 107         write_gic_vl_eic_shadow_set(irq, set);
 108 }
 109
 110 static void gic_send_ipi(struct irq_data *d, unsigned int cpu)
 111 {
 112         irq_hw_number_t hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(d));
 113
 114         write_gic_wedge(GIC_WEDGE_RW | hwirq);
 115 }
 116
 117 int gic_get_c0_compare_int(void)
 118 {
 119         if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER))
 120                 return MIPS_CPU_IRQ_BASE + cp0_compare_irq;
 121         return irq_create_mapping(gic_irq_domain,
 122                                   GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER));
 123 }
 124
 125 int gic_get_c0_perfcount_int(void)
 126 {
 127         if (!gic_local_irq_is_routable(GIC_LOCAL_INT_PERFCTR)) {
 128                 /* Is the performance counter shared with the timer? */
 129                 if (cp0_perfcount_irq < 0)
 130                         return -1;
 131                 return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
 132         }
 133         return irq_create_mapping(gic_irq_domain,
 134                                   GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR));
 135 }
 136
 137 int gic_get_c0_fdc_int(void)
 138 {
 139         if (!gic_local_irq_is_routable(GIC_LOCAL_INT_FDC)) {
 140                 /* Is the FDC IRQ even present? */
 141                 if (cp0_fdc_irq < 0)
 142                         return -1;
 143                 return MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
 144         }
 145
 146         return irq_create_mapping(gic_irq_domain,
 147                                   GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC));
 148 }
 149
 150 static void gic_handle_shared_int(bool chained)
 151 {
 152         unsigned int intr;
 153         unsigned long *pcpu_mask;
 154         DECLARE_BITMAP(pending, GIC_MAX_INTRS);
 155
 156         /* Get per-cpu bitmaps */
 157         pcpu_mask = this_cpu_ptr(pcpu_masks);
 158
 159         if (mips_cm_is64)
 160                 __ioread64_copy(pending, addr_gic_pend(),
 161                                 DIV_ROUND_UP(gic_shared_intrs, 64));
 162         else
 163                 __ioread32_copy(pending, addr_gic_pend(),
 164                                 DIV_ROUND_UP(gic_shared_intrs, 32));
 165
 166         bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs);
 167
 168         for_each_set_bit(intr, pending, gic_shared_intrs) {
 169                 if (chained)
 170                         generic_handle_domain_irq(gic_irq_domain,
 171                                                   GIC_SHARED_TO_HWIRQ(intr));
 172                 else
 173                         do_domain_IRQ(gic_irq_domain,
 174                                       GIC_SHARED_TO_HWIRQ(intr));
 175         }
 176 }
 177
 178 static void gic_mask_irq(struct irq_data *d)
 179 {
 180         unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
 181
 182         write_gic_rmask(intr);
 183         gic_clear_pcpu_masks(intr);
 184 }
 185
 186 static void gic_unmask_irq(struct irq_data *d)
 187 {
 188         unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
 189         unsigned int cpu;
 190
 191         write_gic_smask(intr);
 192
 193         gic_clear_pcpu_masks(intr);
 194         cpu = cpumask_first(irq_data_get_effective_affinity_mask(d));
 195         set_bit(intr, per_cpu_ptr(pcpu_masks, cpu));
 196 }
 197
 198 static void gic_ack_irq(struct irq_data *d)
 199 {
 200         unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
 201
 202         write_gic_wedge(irq);
 203 }
 204
 205 static int gic_set_type(struct irq_data *d, unsigned int type)
 206 {
 207         unsigned int irq, pol, trig, dual;
 208         unsigned long flags;
 209
 210         irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
 211
 212         spin_lock_irqsave(&gic_lock, flags);
 213         switch (type & IRQ_TYPE_SENSE_MASK) {
 214         case IRQ_TYPE_EDGE_FALLING:
 215                 pol = GIC_POL_FALLING_EDGE;
 216                 trig = GIC_TRIG_EDGE;
 217                 dual = GIC_DUAL_SINGLE;
 218                 break;
 219         case IRQ_TYPE_EDGE_RISING:
 220                 pol = GIC_POL_RISING_EDGE;
 221                 trig = GIC_TRIG_EDGE;
 222                 dual = GIC_DUAL_SINGLE;
 223                 break;
 224         case IRQ_TYPE_EDGE_BOTH:
 225                 pol = 0; /* Doesn't matter */
 226                 trig = GIC_TRIG_EDGE;
 227                 dual = GIC_DUAL_DUAL;
 228                 break;
 229         case IRQ_TYPE_LEVEL_LOW:
 230                 pol = GIC_POL_ACTIVE_LOW;
 231                 trig = GIC_TRIG_LEVEL;
 232                 dual = GIC_DUAL_SINGLE;
 233                 break;
 234         case IRQ_TYPE_LEVEL_HIGH:
 235         default:
 236                 pol = GIC_POL_ACTIVE_HIGH;
 237                 trig = GIC_TRIG_LEVEL;
 238                 dual = GIC_DUAL_SINGLE;
 239                 break;
 240         }
 241
 242         change_gic_pol(irq, pol);
 243         change_gic_trig(irq, trig);
 244         change_gic_dual(irq, dual);
 245
 246         if (trig == GIC_TRIG_EDGE)
 247                 irq_set_chip_handler_name_locked(d, &gic_edge_irq_controller,
 248                                                  handle_edge_irq, NULL);
 249         else
 250                 irq_set_chip_handler_name_locked(d, &gic_level_irq_controller,
 251                                                  handle_level_irq, NULL);
 252         spin_unlock_irqrestore(&gic_lock, flags);
 253
 254         return 0;
 255 }
 256
 257 #ifdef CONFIG_SMP
 258 static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
 259                             bool force)
 260 {
 261         unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
 262         unsigned long flags;
 263         unsigned int cpu;
 264
 265         cpu = cpumask_first_and(cpumask, cpu_online_mask);
 266         if (cpu >= NR_CPUS)
 267                 return -EINVAL;
 268
 269         /* Assumption : cpumask refers to a single CPU */
 270         spin_lock_irqsave(&gic_lock, flags);
 271
 272         /* Re-route this IRQ */
 273         write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpu)));
 274
 275         /* Update the pcpu_masks */
 276         gic_clear_pcpu_masks(irq);
 277         if (read_gic_mask(irq))
 278                 set_bit(irq, per_cpu_ptr(pcpu_masks, cpu));
 279
 280         irq_data_update_effective_affinity(d, cpumask_of(cpu));
 281         spin_unlock_irqrestore(&gic_lock, flags);
 282
 283         return IRQ_SET_MASK_OK;
 284 }
 285 #endif
 286
 287 static struct irq_chip gic_level_irq_controller = {
 288         .name                   =       "MIPS GIC",
 289         .irq_mask               =       gic_mask_irq,
 290         .irq_unmask             =       gic_unmask_irq,
 291         .irq_set_type           =       gic_set_type,
 292 #ifdef CONFIG_SMP
 293         .irq_set_affinity       =       gic_set_affinity,
 294 #endif
 295 };
 296
 297 static struct irq_chip gic_edge_irq_controller = {
 298         .name                   =       "MIPS GIC",
 299         .irq_ack                =       gic_ack_irq,
 300         .irq_mask               =       gic_mask_irq,
 301         .irq_unmask             =       gic_unmask_irq,
 302         .irq_set_type           =       gic_set_type,
 303 #ifdef CONFIG_SMP
 304         .irq_set_affinity       =       gic_set_affinity,
 305 #endif
 306         .ipi_send_single        =       gic_send_ipi,
 307 };
 308
 309 static void gic_handle_local_int(bool chained)
 310 {
 311         unsigned long pending, masked;
 312         unsigned int intr;
 313
 314         pending = read_gic_vl_pend();
 315         masked = read_gic_vl_mask();
 316
 317         bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS);
 318
 319         for_each_set_bit(intr, &pending, GIC_NUM_LOCAL_INTRS) {
 320                 if (chained)
 321                         generic_handle_domain_irq(gic_irq_domain,
 322                                                   GIC_LOCAL_TO_HWIRQ(intr));
 323                 else
 324                         do_domain_IRQ(gic_irq_domain,
 325                                       GIC_LOCAL_TO_HWIRQ(intr));
 326         }
 327 }
 328
 329 static void gic_mask_local_irq(struct irq_data *d)
 330 {
 331         int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
 332
 333         write_gic_vl_rmask(BIT(intr));
 334 }
 335
 336 static void gic_unmask_local_irq(struct irq_data *d)
 337 {
 338         int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
 339
 340         write_gic_vl_smask(BIT(intr));
 341 }
 342
 343 static struct irq_chip gic_local_irq_controller = {
 344         .name                   =       "MIPS GIC Local",
 345         .irq_mask               =       gic_mask_local_irq,
 346         .irq_unmask             =       gic_unmask_local_irq,
 347 };
 348
 349 static void gic_mask_local_irq_all_vpes(struct irq_data *d)
 350 {
 351         struct gic_all_vpes_chip_data *cd;
 352         unsigned long flags;
 353         int intr, cpu;
 354
 355         intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
 356         cd = irq_data_get_irq_chip_data(d);
 357         cd->mask = false;
 358
 359         spin_lock_irqsave(&gic_lock, flags);
 360         for_each_online_cpu(cpu) {
 361                 write_gic_vl_other(mips_cm_vp_id(cpu));
 362                 write_gic_vo_rmask(BIT(intr));
 363         }
 364         spin_unlock_irqrestore(&gic_lock, flags);
 365 }
 366
 367 static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
 368 {
 369         struct gic_all_vpes_chip_data *cd;
 370         unsigned long flags;
 371         int intr, cpu;
 372
 373         intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
 374         cd = irq_data_get_irq_chip_data(d);
 375         cd->mask = true;
 376
 377         spin_lock_irqsave(&gic_lock, flags);
 378         for_each_online_cpu(cpu) {
 379                 write_gic_vl_other(mips_cm_vp_id(cpu));
 380                 write_gic_vo_smask(BIT(intr));
 381         }
 382         spin_unlock_irqrestore(&gic_lock, flags);
 383 }
 384
 385 static void gic_all_vpes_irq_cpu_online(void)
 386 {
 387         static const unsigned int local_intrs[] = {
 388                 GIC_LOCAL_INT_TIMER,
 389                 GIC_LOCAL_INT_PERFCTR,
 390                 GIC_LOCAL_INT_FDC,
 391         };
 392         unsigned long flags;
 393         int i;
 394
 395         spin_lock_irqsave(&gic_lock, flags);
 396
 397         for (i = 0; i < ARRAY_SIZE(local_intrs); i++) {
 398                 unsigned int intr = local_intrs[i];
 399                 struct gic_all_vpes_chip_data *cd;
 400
 401                 cd = &gic_all_vpes_chip_data[intr];
 402                 write_gic_vl_map(mips_gic_vx_map_reg(intr), cd->map);
 403                 if (cd->mask)
 404                         write_gic_vl_smask(BIT(intr));
 405         }
 406
 407         spin_unlock_irqrestore(&gic_lock, flags);
 408 }
 409
 410 static struct irq_chip gic_all_vpes_local_irq_controller = {
 411         .name                   = "MIPS GIC Local",
 412         .irq_mask               = gic_mask_local_irq_all_vpes,
 413         .irq_unmask             = gic_unmask_local_irq_all_vpes,
 414 };
 415
 416 static void __gic_irq_dispatch(void)
 417 {
 418         gic_handle_local_int(false);
 419         gic_handle_shared_int(false);
 420 }
 421
 422 static void gic_irq_dispatch(struct irq_desc *desc)
 423 {
 424         gic_handle_local_int(true);
 425         gic_handle_shared_int(true);
 426 }
 427
 428 static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq,
 429                                      irq_hw_number_t hw, unsigned int cpu)
 430 {
 431         int intr = GIC_HWIRQ_TO_SHARED(hw);
 432         struct irq_data *data;
 433         unsigned long flags;
 434
 435         data = irq_get_irq_data(virq);
 436
 437         spin_lock_irqsave(&gic_lock, flags);
 438         write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin);
 439         write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu)));
 440         irq_data_update_effective_affinity(data, cpumask_of(cpu));
 441         spin_unlock_irqrestore(&gic_lock, flags);
 442
 443         return 0;
 444 }
 445
 446 static int gic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
 447                                 const u32 *intspec, unsigned int intsize,
 448                                 irq_hw_number_t *out_hwirq,
 449                                 unsigned int *out_type)
 450 {
 451         if (intsize != 3)
 452                 return -EINVAL;
 453
 454         if (intspec[0] == GIC_SHARED)
 455                 *out_hwirq = GIC_SHARED_TO_HWIRQ(intspec[1]);
 456         else if (intspec[0] == GIC_LOCAL)
 457                 *out_hwirq = GIC_LOCAL_TO_HWIRQ(intspec[1]);
 458         else
 459                 return -EINVAL;
 460         *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
 461
 462         return 0;
 463 }
 464
 465 static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
 466                               irq_hw_number_t hwirq)
 467 {
 468         struct gic_all_vpes_chip_data *cd;
 469         unsigned long flags;
 470         unsigned int intr;
 471         int err, cpu;
 472         u32 map;
 473
 474         if (hwirq >= GIC_SHARED_HWIRQ_BASE) {
 475                 /* verify that shared irqs don't conflict with an IPI irq */
 476                 if (test_bit(GIC_HWIRQ_TO_SHARED(hwirq), ipi_resrv))
 477                         return -EBUSY;
 478
 479                 err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
 480                                                     &gic_level_irq_controller,
 481                                                     NULL);
 482                 if (err)
 483                         return err;
 484
 485                 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
 486                 return gic_shared_irq_domain_map(d, virq, hwirq, 0);
 487         }
 488
 489         intr = GIC_HWIRQ_TO_LOCAL(hwirq);
 490         map = GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin;
 491
 492         /*
 493          * If adding support for more per-cpu interrupts, keep the the
 494          * array in gic_all_vpes_irq_cpu_online() in sync.
 495          */
 496         switch (intr) {
 497         case GIC_LOCAL_INT_TIMER:
 498                 /* CONFIG_MIPS_CMP workaround (see __gic_init) */
 499                 map = GIC_MAP_PIN_MAP_TO_PIN | timer_cpu_pin;
 500                 fallthrough;
 501         case GIC_LOCAL_INT_PERFCTR:
 502         case GIC_LOCAL_INT_FDC:
 503                 /*
 504                  * HACK: These are all really percpu interrupts, but
 505                  * the rest of the MIPS kernel code does not use the
 506                  * percpu IRQ API for them.
 507                  */
 508                 cd = &gic_all_vpes_chip_data[intr];
 509                 cd->map = map;
 510                 err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
 511                                                     &gic_all_vpes_local_irq_controller,
 512                                                     cd);
 513                 if (err)
 514                         return err;
 515
 516                 irq_set_handler(virq, handle_percpu_irq);
 517                 break;
 518
 519         default:
 520                 err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
 521                                                     &gic_local_irq_controller,
 522                                                     NULL);
 523                 if (err)
 524                         return err;
 525
 526                 irq_set_handler(virq, handle_percpu_devid_irq);
 527                 irq_set_percpu_devid(virq);
 528                 break;
 529         }
 530
 531         if (!gic_local_irq_is_routable(intr))
 532                 return -EPERM;
 533
 534         spin_lock_irqsave(&gic_lock, flags);
 535         for_each_online_cpu(cpu) {
 536                 write_gic_vl_other(mips_cm_vp_id(cpu));
 537                 write_gic_vo_map(mips_gic_vx_map_reg(intr), map);
 538         }
 539         spin_unlock_irqrestore(&gic_lock, flags);
 540
 541         return 0;
 542 }
 543
 544 static int gic_irq_domain_alloc(struct irq_domain *d, unsigned int virq,
 545                                 unsigned int nr_irqs, void *arg)
 546 {
 547         struct irq_fwspec *fwspec = arg;
 548         irq_hw_number_t hwirq;
 549
 550         if (fwspec->param[0] == GIC_SHARED)
 551                 hwirq = GIC_SHARED_TO_HWIRQ(fwspec->param[1]);
 552         else
 553                 hwirq = GIC_LOCAL_TO_HWIRQ(fwspec->param[1]);
 554
 555         return gic_irq_domain_map(d, virq, hwirq);
 556 }
 557
 558 void gic_irq_domain_free(struct irq_domain *d, unsigned int virq,
 559                          unsigned int nr_irqs)
 560 {
 561 }
 562
 563 static const struct irq_domain_ops gic_irq_domain_ops = {
 564         .xlate = gic_irq_domain_xlate,
 565         .alloc = gic_irq_domain_alloc,
 566         .free = gic_irq_domain_free,
 567         .map = gic_irq_domain_map,
 568 };
 569
 570 static int gic_ipi_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
 571                                 const u32 *intspec, unsigned int intsize,
 572                                 irq_hw_number_t *out_hwirq,
 573                                 unsigned int *out_type)
 574 {
 575         /*
 576          * There's nothing to translate here. hwirq is dynamically allocated and
 577          * the irq type is always edge triggered.
 578          * */
 579         *out_hwirq = 0;
 580         *out_type = IRQ_TYPE_EDGE_RISING;
 581
 582         return 0;
 583 }
 584
 585 static int gic_ipi_domain_alloc(struct irq_domain *d, unsigned int virq,
 586                                 unsigned int nr_irqs, void *arg)
 587 {
 588         struct cpumask *ipimask = arg;
 589         irq_hw_number_t hwirq, base_hwirq;
 590         int cpu, ret, i;
 591
 592         base_hwirq = find_first_bit(ipi_available, gic_shared_intrs);
 593         if (base_hwirq == gic_shared_intrs)
 594                 return -ENOMEM;
 595
 596         /* check that we have enough space */
 597         for (i = base_hwirq; i < nr_irqs; i++) {
 598                 if (!test_bit(i, ipi_available))
 599                         return -EBUSY;
 600         }
 601         bitmap_clear(ipi_available, base_hwirq, nr_irqs);
 602
 603         /* map the hwirq for each cpu consecutively */
 604         i = 0;
 605         for_each_cpu(cpu, ipimask) {
 606                 hwirq = GIC_SHARED_TO_HWIRQ(base_hwirq + i);
 607
 608                 ret = irq_domain_set_hwirq_and_chip(d, virq + i, hwirq,
 609                                                     &gic_edge_irq_controller,
 610                                                     NULL);
 611                 if (ret)
 612                         goto error;
 613
 614                 ret = irq_domain_set_hwirq_and_chip(d->parent, virq + i, hwirq,
 615                                                     &gic_edge_irq_controller,
 616                                                     NULL);
 617                 if (ret)
 618                         goto error;
 619
 620                 ret = irq_set_irq_type(virq + i, IRQ_TYPE_EDGE_RISING);
 621                 if (ret)
 622                         goto error;
 623
 624                 ret = gic_shared_irq_domain_map(d, virq + i, hwirq, cpu);
 625                 if (ret)
 626                         goto error;
 627
 628                 i++;
 629         }
 630
 631         return 0;
 632 error:
 633         bitmap_set(ipi_available, base_hwirq, nr_irqs);
 634         return ret;
 635 }
 636
 637 static void gic_ipi_domain_free(struct irq_domain *d, unsigned int virq,
 638                                 unsigned int nr_irqs)
 639 {
 640         irq_hw_number_t base_hwirq;
 641         struct irq_data *data;
 642
 643         data = irq_get_irq_data(virq);
 644         if (!data)
 645                 return;
 646
 647         base_hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(data));
 648         bitmap_set(ipi_available, base_hwirq, nr_irqs);
 649 }
 650
 651 static int gic_ipi_domain_match(struct irq_domain *d, struct device_node *node,
 652                                 enum irq_domain_bus_token bus_token)
 653 {
 654         bool is_ipi;
 655
 656         switch (bus_token) {
 657         case DOMAIN_BUS_IPI:
 658                 is_ipi = d->bus_token == bus_token;
 659                 return (!node || to_of_node(d->fwnode) == node) && is_ipi;
 660                 break;
 661         default:
 662                 return 0;
 663         }
 664 }
 665
 666 static const struct irq_domain_ops gic_ipi_domain_ops = {
 667         .xlate = gic_ipi_domain_xlate,
 668         .alloc = gic_ipi_domain_alloc,
 669         .free = gic_ipi_domain_free,
 670         .match = gic_ipi_domain_match,
 671 };
 672
 673 static int gic_cpu_startup(unsigned int cpu)
 674 {
 675         /* Enable or disable EIC */
 676         change_gic_vl_ctl(GIC_VX_CTL_EIC,
 677                           cpu_has_veic ? GIC_VX_CTL_EIC : 0);
 678
 679         /* Clear all local IRQ masks (ie. disable all local interrupts) */
 680         write_gic_vl_rmask(~0);
 681
 682         /* Enable desired interrupts */
 683         gic_all_vpes_irq_cpu_online();
 684
 685         return 0;
 686 }
 687
 688 static int __init gic_of_init(struct device_node *node,
 689                               struct device_node *parent)
 690 {
 691         unsigned int cpu_vec, i, gicconfig, v[2], num_ipis;
 692         unsigned long reserved;
 693         phys_addr_t gic_base;
 694         struct resource res;
 695         size_t gic_len;
 696
 697         /* Find the first available CPU vector. */
 698         i = 0;
 699         reserved = (C_SW0 | C_SW1) >> __ffs(C_SW0);
 700         while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors",
 701                                            i++, &cpu_vec))
 702                 reserved |= BIT(cpu_vec);
 703
 704         cpu_vec = find_first_zero_bit(&reserved, hweight_long(ST0_IM));
 705         if (cpu_vec == hweight_long(ST0_IM)) {
 706                 pr_err("No CPU vectors available\n");
 707                 return -ENODEV;
 708         }
 709
 710         if (of_address_to_resource(node, 0, &res)) {
 711                 /*
 712                  * Probe the CM for the GIC base address if not specified
 713                  * in the device-tree.
 714                  */
 715                 if (mips_cm_present()) {
 716                         gic_base = read_gcr_gic_base() &
 717                                 ~CM_GCR_GIC_BASE_GICEN;
 718                         gic_len = 0x20000;
 719                         pr_warn("Using inherited base address %pa\n",
 720                                 &gic_base);
 721                 } else {
 722                         pr_err("Failed to get memory range\n");
 723                         return -ENODEV;
 724                 }
 725         } else {
 726                 gic_base = res.start;
 727                 gic_len = resource_size(&res);
 728         }
 729
 730         if (mips_cm_present()) {
 731                 write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN);
 732                 /* Ensure GIC region is enabled before trying to access it */
 733                 __sync();
 734         }
 735
 736         mips_gic_base = ioremap(gic_base, gic_len);
 737
 738         gicconfig = read_gic_config();
 739         gic_shared_intrs = FIELD_GET(GIC_CONFIG_NUMINTERRUPTS, gicconfig);
 740         gic_shared_intrs = (gic_shared_intrs + 1) * 8;
 741
 742         if (cpu_has_veic) {
 743                 /* Always use vector 1 in EIC mode */
 744                 gic_cpu_pin = 0;
 745                 timer_cpu_pin = gic_cpu_pin;
 746                 set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET,
 747                                __gic_irq_dispatch);
 748         } else {
 749                 gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET;
 750                 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec,
 751                                         gic_irq_dispatch);
 752                 /*
 753                  * With the CMP implementation of SMP (deprecated), other CPUs
 754                  * are started by the bootloader and put into a timer based
 755                  * waiting poll loop. We must not re-route those CPU's local
 756                  * timer interrupts as the wait instruction will never finish,
 757                  * so just handle whatever CPU interrupt it is routed to by
 758                  * default.
 759                  *
 760                  * This workaround should be removed when CMP support is
 761                  * dropped.
 762                  */
 763                 if (IS_ENABLED(CONFIG_MIPS_CMP) &&
 764                     gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) {
 765                         timer_cpu_pin = read_gic_vl_timer_map() & GIC_MAP_PIN_MAP;
 766                         irq_set_chained_handler(MIPS_CPU_IRQ_BASE +
 767                                                 GIC_CPU_PIN_OFFSET +
 768                                                 timer_cpu_pin,
 769                                                 gic_irq_dispatch);
 770                 } else {
 771                         timer_cpu_pin = gic_cpu_pin;
 772                 }
 773         }
 774
 775         gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS +
 776                                                gic_shared_intrs, 0,
 777                                                &gic_irq_domain_ops, NULL);
 778         if (!gic_irq_domain) {
 779                 pr_err("Failed to add IRQ domain");
 780                 return -ENXIO;
 781         }
 782
 783         gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain,
 784                                                   IRQ_DOMAIN_FLAG_IPI_PER_CPU,
 785                                                   GIC_NUM_LOCAL_INTRS + gic_shared_intrs,
 786                                                   node, &gic_ipi_domain_ops, NULL);
 787         if (!gic_ipi_domain) {
 788                 pr_err("Failed to add IPI domain");
 789                 return -ENXIO;
 790         }
 791
 792         irq_domain_update_bus_token(gic_ipi_domain, DOMAIN_BUS_IPI);
 793
 794         if (node &&
 795             !of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) {
 796                 bitmap_set(ipi_resrv, v[0], v[1]);
 797         } else {
 798                 /*
 799                  * Reserve 2 interrupts per possible CPU/VP for use as IPIs,
 800                  * meeting the requirements of arch/mips SMP.
 801                  */
 802                 num_ipis = 2 * num_possible_cpus();
 803                 bitmap_set(ipi_resrv, gic_shared_intrs - num_ipis, num_ipis);
 804         }
 805
 806         bitmap_copy(ipi_available, ipi_resrv, GIC_MAX_INTRS);
 807
 808         board_bind_eic_interrupt = &gic_bind_eic_interrupt;
 809
 810         /* Setup defaults */
 811         for (i = 0; i < gic_shared_intrs; i++) {
 812                 change_gic_pol(i, GIC_POL_ACTIVE_HIGH);
 813                 change_gic_trig(i, GIC_TRIG_LEVEL);
 814                 write_gic_rmask(i);
 815         }
 816
 817         return cpuhp_setup_state(CPUHP_AP_IRQ_MIPS_GIC_STARTING,
 818                                  "irqchip/mips/gic:starting",
 819                                  gic_cpu_startup, NULL);
 820 }
 821 IRQCHIP_DECLARE(mips_gic, "mti,gic", gic_of_init);