drivers/clocksource/timer-riscv.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2012 Regents of the University of California
   4  * Copyright (C) 2017 SiFive
   5  *
   6  * All RISC-V systems have a timer attached to every hart.  These timers can
   7  * either be read from the "time" and "timeh" CSRs, and can use the SBI to
   8  * setup events, or directly accessed using MMIO registers.
   9  */
  10
  11 #define pr_fmt(fmt) "riscv-timer: " fmt
  12
  13 #include <linux/clocksource.h>
  14 #include <linux/clockchips.h>
  15 #include <linux/cpu.h>
  16 #include <linux/delay.h>
  17 #include <linux/irq.h>
  18 #include <linux/irqdomain.h>
  19 #include <linux/module.h>
  20 #include <linux/sched_clock.h>
  21 #include <linux/io-64-nonatomic-lo-hi.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/of_irq.h>
  24 #include <clocksource/timer-riscv.h>
  25 #include <asm/smp.h>
  26 #include <asm/hwcap.h>
  27 #include <asm/sbi.h>
  28 #include <asm/timex.h>
  29
  30 static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available);
  31 static bool riscv_timer_cannot_wake_cpu;
  32
  33 static int riscv_clock_next_event(unsigned long delta,
  34                 struct clock_event_device *ce)
  35 {
  36         u64 next_tval = get_cycles64() + delta;
  37
  38         csr_set(CSR_IE, IE_TIE);
  39         if (static_branch_likely(&riscv_sstc_available)) {
  40 #if defined(CONFIG_32BIT)
  41                 csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF);
  42                 csr_write(CSR_STIMECMPH, next_tval >> 32);
  43 #else
  44                 csr_write(CSR_STIMECMP, next_tval);
  45 #endif
  46         } else
  47                 sbi_set_timer(next_tval);
  48
  49         return 0;
  50 }
  51
  52 static unsigned int riscv_clock_event_irq;
  53 static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
  54         .name                   = "riscv_timer_clockevent",
  55         .features               = CLOCK_EVT_FEAT_ONESHOT,
  56         .rating                 = 100,
  57         .set_next_event         = riscv_clock_next_event,
  58 };
  59
  60 /*
  61  * It is guaranteed that all the timers across all the harts are synchronized
  62  * within one tick of each other, so while this could technically go
  63  * backwards when hopping between CPUs, practically it won't happen.
  64  */
  65 static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs)
  66 {
  67         return get_cycles64();
  68 }
  69
  70 static u64 notrace riscv_sched_clock(void)
  71 {
  72         return get_cycles64();
  73 }
  74
  75 static struct clocksource riscv_clocksource = {
  76         .name           = "riscv_clocksource",
  77         .rating         = 400,
  78         .mask           = CLOCKSOURCE_MASK(64),
  79         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  80         .read           = riscv_clocksource_rdtime,
  81 #if IS_ENABLED(CONFIG_GENERIC_GETTIMEOFDAY)
  82         .vdso_clock_mode = VDSO_CLOCKMODE_ARCHTIMER,
  83 #else
  84         .vdso_clock_mode = VDSO_CLOCKMODE_NONE,
  85 #endif
  86 };
  87
  88 static int riscv_timer_starting_cpu(unsigned int cpu)
  89 {
  90         struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);
  91
  92         ce->cpumask = cpumask_of(cpu);
  93         ce->irq = riscv_clock_event_irq;
  94         if (riscv_timer_cannot_wake_cpu)
  95                 ce->features |= CLOCK_EVT_FEAT_C3STOP;
  96         clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);
  97
  98         enable_percpu_irq(riscv_clock_event_irq,
  99                           irq_get_trigger_type(riscv_clock_event_irq));
 100         return 0;
 101 }
 102
 103 static int riscv_timer_dying_cpu(unsigned int cpu)
 104 {
 105         disable_percpu_irq(riscv_clock_event_irq);
 106         return 0;
 107 }
 108
 109 void riscv_cs_get_mult_shift(u32 *mult, u32 *shift)
 110 {
 111         *mult = riscv_clocksource.mult;
 112         *shift = riscv_clocksource.shift;
 113 }
 114 EXPORT_SYMBOL_GPL(riscv_cs_get_mult_shift);
 115
 116 /* called directly from the low-level interrupt handler */
 117 static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
 118 {
 119         struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event);
 120
 121         csr_clear(CSR_IE, IE_TIE);
 122         evdev->event_handler(evdev);
 123
 124         return IRQ_HANDLED;
 125 }
 126
 127 static int __init riscv_timer_init_dt(struct device_node *n)
 128 {
 129         int cpuid, error;
 130         unsigned long hartid;
 131         struct device_node *child;
 132         struct irq_domain *domain;
 133
 134         error = riscv_of_processor_hartid(n, &hartid);
 135         if (error < 0) {
 136                 pr_warn("Not valid hartid for node [%pOF] error = [%lu]\n",
 137                         n, hartid);
 138                 return error;
 139         }
 140
 141         cpuid = riscv_hartid_to_cpuid(hartid);
 142         if (cpuid < 0) {
 143                 pr_warn("Invalid cpuid for hartid [%lu]\n", hartid);
 144                 return cpuid;
 145         }
 146
 147         if (cpuid != smp_processor_id())
 148                 return 0;
 149
 150         child = of_find_compatible_node(NULL, NULL, "riscv,timer");
 151         if (child) {
 152                 riscv_timer_cannot_wake_cpu = of_property_read_bool(child,
 153                                         "riscv,timer-cannot-wake-cpu");
 154                 of_node_put(child);
 155         }
 156
 157         domain = NULL;
 158         child = of_get_compatible_child(n, "riscv,cpu-intc");
 159         if (!child) {
 160                 pr_err("Failed to find INTC node [%pOF]\n", n);
 161                 return -ENODEV;
 162         }
 163         domain = irq_find_host(child);
 164         of_node_put(child);
 165         if (!domain) {
 166                 pr_err("Failed to find IRQ domain for node [%pOF]\n", n);
 167                 return -ENODEV;
 168         }
 169
 170         riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER);
 171         if (!riscv_clock_event_irq) {
 172                 pr_err("Failed to map timer interrupt for node [%pOF]\n", n);
 173                 return -ENODEV;
 174         }
 175
 176         pr_info("%s: Registering clocksource cpuid [%d] hartid [%lu]\n",
 177                __func__, cpuid, hartid);
 178         error = clocksource_register_hz(&riscv_clocksource, riscv_timebase);
 179         if (error) {
 180                 pr_err("RISCV timer register failed [%d] for cpu = [%d]\n",
 181                        error, cpuid);
 182                 return error;
 183         }
 184
 185         sched_clock_register(riscv_sched_clock, 64, riscv_timebase);
 186
 187         error = request_percpu_irq(riscv_clock_event_irq,
 188                                     riscv_timer_interrupt,
 189                                     "riscv-timer", &riscv_clock_event);
 190         if (error) {
 191                 pr_err("registering percpu irq failed [%d]\n", error);
 192                 return error;
 193         }
 194
 195         if (riscv_isa_extension_available(NULL, SSTC)) {
 196                 pr_info("Timer interrupt in S-mode is available via sstc extension\n");
 197                 static_branch_enable(&riscv_sstc_available);
 198         }
 199
 200         error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
 201                          "clockevents/riscv/timer:starting",
 202                          riscv_timer_starting_cpu, riscv_timer_dying_cpu);
 203         if (error)
 204                 pr_err("cpu hp setup state failed for RISCV timer [%d]\n",
 205                        error);
 206
 207         return error;
 208 }
 209
 210 TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);