drivers/nvmem/imx-ocotp.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * i.MX6 OCOTP fusebox driver
   4  *
   5  * Copyright (c) 2015 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
   6  *
   7  * Copyright 2019 NXP
   8  *
   9  * Based on the barebox ocotp driver,
  10  * Copyright (c) 2010 Baruch Siach <baruch@tkos.co.il>,
  11  *      Orex Computed Radiography
  12  *
  13  * Write support based on the fsl_otp driver,
  14  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/device.h>
  19 #include <linux/io.h>
  20 #include <linux/module.h>
  21 #include <linux/nvmem-provider.h>
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27
  28 #define IMX_OCOTP_OFFSET_B0W0           0x400 /* Offset from base address of the
  29                                                * OTP Bank0 Word0
  30                                                */
  31 #define IMX_OCOTP_OFFSET_PER_WORD       0x10  /* Offset between the start addr
  32                                                * of two consecutive OTP words.
  33                                                */
  34
  35 #define IMX_OCOTP_ADDR_CTRL             0x0000
  36 #define IMX_OCOTP_ADDR_CTRL_SET         0x0004
  37 #define IMX_OCOTP_ADDR_CTRL_CLR         0x0008
  38 #define IMX_OCOTP_ADDR_TIMING           0x0010
  39 #define IMX_OCOTP_ADDR_DATA0            0x0020
  40 #define IMX_OCOTP_ADDR_DATA1            0x0030
  41 #define IMX_OCOTP_ADDR_DATA2            0x0040
  42 #define IMX_OCOTP_ADDR_DATA3            0x0050
  43
  44 #define IMX_OCOTP_BM_CTRL_ADDR          0x000000FF
  45 #define IMX_OCOTP_BM_CTRL_BUSY          0x00000100
  46 #define IMX_OCOTP_BM_CTRL_ERROR         0x00000200
  47 #define IMX_OCOTP_BM_CTRL_REL_SHADOWS   0x00000400
  48
  49 #define IMX_OCOTP_BM_CTRL_ADDR_8MP              0x000001FF
  50 #define IMX_OCOTP_BM_CTRL_BUSY_8MP              0x00000200
  51 #define IMX_OCOTP_BM_CTRL_ERROR_8MP             0x00000400
  52 #define IMX_OCOTP_BM_CTRL_REL_SHADOWS_8MP       0x00000800
  53
  54 #define IMX_OCOTP_BM_CTRL_DEFAULT                               \
  55         {                                                       \
  56                 .bm_addr = IMX_OCOTP_BM_CTRL_ADDR,              \
  57                 .bm_busy = IMX_OCOTP_BM_CTRL_BUSY,              \
  58                 .bm_error = IMX_OCOTP_BM_CTRL_ERROR,            \
  59                 .bm_rel_shadows = IMX_OCOTP_BM_CTRL_REL_SHADOWS,\
  60         }
  61
  62 #define IMX_OCOTP_BM_CTRL_8MP                                   \
  63         {                                                       \
  64                 .bm_addr = IMX_OCOTP_BM_CTRL_ADDR_8MP,          \
  65                 .bm_busy = IMX_OCOTP_BM_CTRL_BUSY_8MP,          \
  66                 .bm_error = IMX_OCOTP_BM_CTRL_ERROR_8MP,        \
  67                 .bm_rel_shadows = IMX_OCOTP_BM_CTRL_REL_SHADOWS_8MP,\
  68         }
  69
  70 #define TIMING_STROBE_PROG_US           10      /* Min time to blow a fuse */
  71 #define TIMING_STROBE_READ_NS           37      /* Min time before read */
  72 #define TIMING_RELAX_NS                 17
  73 #define DEF_FSOURCE                     1001    /* > 1000 ns */
  74 #define DEF_STROBE_PROG                 10000   /* IPG clocks */
  75 #define IMX_OCOTP_WR_UNLOCK             0x3E770000
  76 #define IMX_OCOTP_READ_LOCKED_VAL       0xBADABADA
  77
  78 static DEFINE_MUTEX(ocotp_mutex);
  79
  80 struct ocotp_priv {
  81         struct device *dev;
  82         struct clk *clk;
  83         void __iomem *base;
  84         const struct ocotp_params *params;
  85         struct nvmem_config *config;
  86 };
  87
  88 struct ocotp_ctrl_reg {
  89         u32 bm_addr;
  90         u32 bm_busy;
  91         u32 bm_error;
  92         u32 bm_rel_shadows;
  93 };
  94
  95 struct ocotp_params {
  96         unsigned int nregs;
  97         unsigned int bank_address_words;
  98         void (*set_timing)(struct ocotp_priv *priv);
  99         struct ocotp_ctrl_reg ctrl;
 100         bool reverse_mac_address;
 101 };
 102
 103 static int imx_ocotp_wait_for_busy(struct ocotp_priv *priv, u32 flags)
 104 {
 105         int count;
 106         u32 c, mask;
 107         u32 bm_ctrl_busy, bm_ctrl_error;
 108         void __iomem *base = priv->base;
 109
 110         bm_ctrl_busy = priv->params->ctrl.bm_busy;
 111         bm_ctrl_error = priv->params->ctrl.bm_error;
 112
 113         mask = bm_ctrl_busy | bm_ctrl_error | flags;
 114
 115         for (count = 10000; count >= 0; count--) {
 116                 c = readl(base + IMX_OCOTP_ADDR_CTRL);
 117                 if (!(c & mask))
 118                         break;
 119                 cpu_relax();
 120         }
 121
 122         if (count < 0) {
 123                 /* HW_OCOTP_CTRL[ERROR] will be set under the following
 124                  * conditions:
 125                  * - A write is performed to a shadow register during a shadow
 126                  *   reload (essentially, while HW_OCOTP_CTRL[RELOAD_SHADOWS] is
 127                  *   set. In addition, the contents of the shadow register shall
 128                  *   not be updated.
 129                  * - A write is performed to a shadow register which has been
 130                  *   locked.
 131                  * - A read is performed to from a shadow register which has
 132                  *   been read locked.
 133                  * - A program is performed to a fuse word which has been locked
 134                  * - A read is performed to from a fuse word which has been read
 135                  *   locked.
 136                  */
 137                 if (c & bm_ctrl_error)
 138                         return -EPERM;
 139                 return -ETIMEDOUT;
 140         }
 141
 142         return 0;
 143 }
 144
 145 static void imx_ocotp_clr_err_if_set(struct ocotp_priv *priv)
 146 {
 147         u32 c, bm_ctrl_error;
 148         void __iomem *base = priv->base;
 149
 150         bm_ctrl_error = priv->params->ctrl.bm_error;
 151
 152         c = readl(base + IMX_OCOTP_ADDR_CTRL);
 153         if (!(c & bm_ctrl_error))
 154                 return;
 155
 156         writel(bm_ctrl_error, base + IMX_OCOTP_ADDR_CTRL_CLR);
 157 }
 158
 159 static int imx_ocotp_read(void *context, unsigned int offset,
 160                           void *val, size_t bytes)
 161 {
 162         struct ocotp_priv *priv = context;
 163         unsigned int count;
 164         u8 *buf, *p;
 165         int i, ret;
 166         u32 index, num_bytes;
 167
 168         index = offset >> 2;
 169         num_bytes = round_up((offset % 4) + bytes, 4);
 170         count = num_bytes >> 2;
 171
 172         if (count > (priv->params->nregs - index))
 173                 count = priv->params->nregs - index;
 174
 175         p = kzalloc(num_bytes, GFP_KERNEL);
 176         if (!p)
 177                 return -ENOMEM;
 178
 179         mutex_lock(&ocotp_mutex);
 180
 181         buf = p;
 182
 183         ret = clk_prepare_enable(priv->clk);
 184         if (ret < 0) {
 185                 mutex_unlock(&ocotp_mutex);
 186                 dev_err(priv->dev, "failed to prepare/enable ocotp clk\n");
 187                 kfree(p);
 188                 return ret;
 189         }
 190
 191         ret = imx_ocotp_wait_for_busy(priv, 0);
 192         if (ret < 0) {
 193                 dev_err(priv->dev, "timeout during read setup\n");
 194                 goto read_end;
 195         }
 196
 197         for (i = index; i < (index + count); i++) {
 198                 *(u32 *)buf = readl(priv->base + IMX_OCOTP_OFFSET_B0W0 +
 199                                i * IMX_OCOTP_OFFSET_PER_WORD);
 200
 201                 /* 47.3.1.2
 202                  * For "read locked" registers 0xBADABADA will be returned and
 203                  * HW_OCOTP_CTRL[ERROR] will be set. It must be cleared by
 204                  * software before any new write, read or reload access can be
 205                  * issued
 206                  */
 207                 if (*((u32 *)buf) == IMX_OCOTP_READ_LOCKED_VAL)
 208                         imx_ocotp_clr_err_if_set(priv);
 209
 210                 buf += 4;
 211         }
 212
 213         index = offset % 4;
 214         memcpy(val, &p[index], bytes);
 215
 216 read_end:
 217         clk_disable_unprepare(priv->clk);
 218         mutex_unlock(&ocotp_mutex);
 219
 220         kfree(p);
 221
 222         return ret;
 223 }
 224
 225 static int imx_ocotp_cell_pp(void *context, const char *id, int index,
 226                              unsigned int offset, void *data, size_t bytes)
 227 {
 228         u8 *buf = data;
 229         int i;
 230
 231         /* Deal with some post processing of nvmem cell data */
 232         if (id && !strcmp(id, "mac-address"))
 233                 for (i = 0; i < bytes / 2; i++)
 234                         swap(buf[i], buf[bytes - i - 1]);
 235
 236         return 0;
 237 }
 238
 239 static void imx_ocotp_set_imx6_timing(struct ocotp_priv *priv)
 240 {
 241         unsigned long clk_rate;
 242         unsigned long strobe_read, relax, strobe_prog;
 243         u32 timing;
 244
 245         /* 47.3.1.3.1
 246          * Program HW_OCOTP_TIMING[STROBE_PROG] and HW_OCOTP_TIMING[RELAX]
 247          * fields with timing values to match the current frequency of the
 248          * ipg_clk. OTP writes will work at maximum bus frequencies as long
 249          * as the HW_OCOTP_TIMING parameters are set correctly.
 250          *
 251          * Note: there are minimum timings required to ensure an OTP fuse burns
 252          * correctly that are independent of the ipg_clk. Those values are not
 253          * formally documented anywhere however, working from the minimum
 254          * timings given in u-boot we can say:
 255          *
 256          * - Minimum STROBE_PROG time is 10 microseconds. Intuitively 10
 257          *   microseconds feels about right as representative of a minimum time
 258          *   to physically burn out a fuse.
 259          *
 260          * - Minimum STROBE_READ i.e. the time to wait post OTP fuse burn before
 261          *   performing another read is 37 nanoseconds
 262          *
 263          * - Minimum RELAX timing is 17 nanoseconds. This final RELAX minimum
 264          *   timing is not entirely clear the documentation says "This
 265          *   count value specifies the time to add to all default timing
 266          *   parameters other than the Tpgm and Trd. It is given in number
 267          *   of ipg_clk periods." where Tpgm and Trd refer to STROBE_PROG
 268          *   and STROBE_READ respectively. What the other timing parameters
 269          *   are though, is not specified. Experience shows a zero RELAX
 270          *   value will mess up a re-load of the shadow registers post OTP
 271          *   burn.
 272          */
 273         clk_rate = clk_get_rate(priv->clk);
 274
 275         relax = DIV_ROUND_UP(clk_rate * TIMING_RELAX_NS, 1000000000) - 1;
 276         strobe_read = DIV_ROUND_UP(clk_rate * TIMING_STROBE_READ_NS,
 277                                    1000000000);
 278         strobe_read += 2 * (relax + 1) - 1;
 279         strobe_prog = DIV_ROUND_CLOSEST(clk_rate * TIMING_STROBE_PROG_US,
 280                                         1000000);
 281         strobe_prog += 2 * (relax + 1) - 1;
 282
 283         timing = readl(priv->base + IMX_OCOTP_ADDR_TIMING) & 0x0FC00000;
 284         timing |= strobe_prog & 0x00000FFF;
 285         timing |= (relax       << 12) & 0x0000F000;
 286         timing |= (strobe_read << 16) & 0x003F0000;
 287
 288         writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
 289 }
 290
 291 static void imx_ocotp_set_imx7_timing(struct ocotp_priv *priv)
 292 {
 293         unsigned long clk_rate;
 294         u64 fsource, strobe_prog;
 295         u32 timing;
 296
 297         /* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1
 298          * 6.4.3.3
 299          */
 300         clk_rate = clk_get_rate(priv->clk);
 301         fsource = DIV_ROUND_UP_ULL((u64)clk_rate * DEF_FSOURCE,
 302                                    NSEC_PER_SEC) + 1;
 303         strobe_prog = DIV_ROUND_CLOSEST_ULL((u64)clk_rate * DEF_STROBE_PROG,
 304                                             NSEC_PER_SEC) + 1;
 305
 306         timing = strobe_prog & 0x00000FFF;
 307         timing |= (fsource << 12) & 0x000FF000;
 308
 309         writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
 310 }
 311
 312 static int imx_ocotp_write(void *context, unsigned int offset, void *val,
 313                            size_t bytes)
 314 {
 315         struct ocotp_priv *priv = context;
 316         u32 *buf = val;
 317         int ret;
 318
 319         u32 ctrl;
 320         u8 waddr;
 321         u8 word = 0;
 322
 323         /* allow only writing one complete OTP word at a time */
 324         if ((bytes != priv->config->word_size) ||
 325             (offset % priv->config->word_size))
 326                 return -EINVAL;
 327
 328         mutex_lock(&ocotp_mutex);
 329
 330         ret = clk_prepare_enable(priv->clk);
 331         if (ret < 0) {
 332                 mutex_unlock(&ocotp_mutex);
 333                 dev_err(priv->dev, "failed to prepare/enable ocotp clk\n");
 334                 return ret;
 335         }
 336
 337         /* Setup the write timing values */
 338         priv->params->set_timing(priv);
 339
 340         /* 47.3.1.3.2
 341          * Check that HW_OCOTP_CTRL[BUSY] and HW_OCOTP_CTRL[ERROR] are clear.
 342          * Overlapped accesses are not supported by the controller. Any pending
 343          * write or reload must be completed before a write access can be
 344          * requested.
 345          */
 346         ret = imx_ocotp_wait_for_busy(priv, 0);
 347         if (ret < 0) {
 348                 dev_err(priv->dev, "timeout during timing setup\n");
 349                 goto write_end;
 350         }
 351
 352         /* 47.3.1.3.3
 353          * Write the requested address to HW_OCOTP_CTRL[ADDR] and program the
 354          * unlock code into HW_OCOTP_CTRL[WR_UNLOCK]. This must be programmed
 355          * for each write access. The lock code is documented in the register
 356          * description. Both the unlock code and address can be written in the
 357          * same operation.
 358          */
 359         if (priv->params->bank_address_words != 0) {
 360                 /*
 361                  * In banked/i.MX7 mode the OTP register bank goes into waddr
 362                  * see i.MX 7Solo Applications Processor Reference Manual, Rev.
 363                  * 0.1 section 6.4.3.1
 364                  */
 365                 offset = offset / priv->config->word_size;
 366                 waddr = offset / priv->params->bank_address_words;
 367                 word  = offset & (priv->params->bank_address_words - 1);
 368         } else {
 369                 /*
 370                  * Non-banked i.MX6 mode.
 371                  * OTP write/read address specifies one of 128 word address
 372                  * locations
 373                  */
 374                 waddr = offset / 4;
 375         }
 376
 377         ctrl = readl(priv->base + IMX_OCOTP_ADDR_CTRL);
 378         ctrl &= ~priv->params->ctrl.bm_addr;
 379         ctrl |= waddr & priv->params->ctrl.bm_addr;
 380         ctrl |= IMX_OCOTP_WR_UNLOCK;
 381
 382         writel(ctrl, priv->base + IMX_OCOTP_ADDR_CTRL);
 383
 384         /* 47.3.1.3.4
 385          * Write the data to the HW_OCOTP_DATA register. This will automatically
 386          * set HW_OCOTP_CTRL[BUSY] and clear HW_OCOTP_CTRL[WR_UNLOCK]. To
 387          * protect programming same OTP bit twice, before program OCOTP will
 388          * automatically read fuse value in OTP and use read value to mask
 389          * program data. The controller will use masked program data to program
 390          * a 32-bit word in the OTP per the address in HW_OCOTP_CTRL[ADDR]. Bit
 391          * fields with 1's will result in that OTP bit being programmed. Bit
 392          * fields with 0's will be ignored. At the same time that the write is
 393          * accepted, the controller makes an internal copy of
 394          * HW_OCOTP_CTRL[ADDR] which cannot be updated until the next write
 395          * sequence is initiated. This copy guarantees that erroneous writes to
 396          * HW_OCOTP_CTRL[ADDR] will not affect an active write operation. It
 397          * should also be noted that during the programming HW_OCOTP_DATA will
 398          * shift right (with zero fill). This shifting is required to program
 399          * the OTP serially. During the write operation, HW_OCOTP_DATA cannot be
 400          * modified.
 401          * Note: on i.MX7 there are four data fields to write for banked write
 402          *       with the fuse blowing operation only taking place after data0
 403          *       has been written. This is why data0 must always be the last
 404          *       register written.
 405          */
 406         if (priv->params->bank_address_words != 0) {
 407                 /* Banked/i.MX7 mode */
 408                 switch (word) {
 409                 case 0:
 410                         writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
 411                         writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
 412                         writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
 413                         writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
 414                         break;
 415                 case 1:
 416                         writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA1);
 417                         writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
 418                         writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
 419                         writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
 420                         break;
 421                 case 2:
 422                         writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
 423                         writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA2);
 424                         writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
 425                         writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
 426                         break;
 427                 case 3:
 428                         writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
 429                         writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
 430                         writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA3);
 431                         writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
 432                         break;
 433                 }
 434         } else {
 435                 /* Non-banked i.MX6 mode */
 436                 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
 437         }
 438
 439         /* 47.4.1.4.5
 440          * Once complete, the controller will clear BUSY. A write request to a
 441          * protected or locked region will result in no OTP access and no
 442          * setting of HW_OCOTP_CTRL[BUSY]. In addition HW_OCOTP_CTRL[ERROR] will
 443          * be set. It must be cleared by software before any new write access
 444          * can be issued.
 445          */
 446         ret = imx_ocotp_wait_for_busy(priv, 0);
 447         if (ret < 0) {
 448                 if (ret == -EPERM) {
 449                         dev_err(priv->dev, "failed write to locked region");
 450                         imx_ocotp_clr_err_if_set(priv);
 451                 } else {
 452                         dev_err(priv->dev, "timeout during data write\n");
 453                 }
 454                 goto write_end;
 455         }
 456
 457         /* 47.3.1.4
 458          * Write Postamble: Due to internal electrical characteristics of the
 459          * OTP during writes, all OTP operations following a write must be
 460          * separated by 2 us after the clearing of HW_OCOTP_CTRL_BUSY following
 461          * the write.
 462          */
 463         udelay(2);
 464
 465         /* reload all shadow registers */
 466         writel(priv->params->ctrl.bm_rel_shadows,
 467                priv->base + IMX_OCOTP_ADDR_CTRL_SET);
 468         ret = imx_ocotp_wait_for_busy(priv,
 469                                       priv->params->ctrl.bm_rel_shadows);
 470         if (ret < 0)
 471                 dev_err(priv->dev, "timeout during shadow register reload\n");
 472
 473 write_end:
 474         clk_disable_unprepare(priv->clk);
 475         mutex_unlock(&ocotp_mutex);
 476         return ret < 0 ? ret : bytes;
 477 }
 478
 479 static struct nvmem_config imx_ocotp_nvmem_config = {
 480         .name = "imx-ocotp",
 481         .read_only = false,
 482         .word_size = 4,
 483         .stride = 1,
 484         .reg_read = imx_ocotp_read,
 485         .reg_write = imx_ocotp_write,
 486 };
 487
 488 static const struct ocotp_params imx6q_params = {
 489         .nregs = 128,
 490         .bank_address_words = 0,
 491         .set_timing = imx_ocotp_set_imx6_timing,
 492         .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
 493 };
 494
 495 static const struct ocotp_params imx6sl_params = {
 496         .nregs = 64,
 497         .bank_address_words = 0,
 498         .set_timing = imx_ocotp_set_imx6_timing,
 499         .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
 500 };
 501
 502 static const struct ocotp_params imx6sll_params = {
 503         .nregs = 128,
 504         .bank_address_words = 0,
 505         .set_timing = imx_ocotp_set_imx6_timing,
 506         .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
 507 };
 508
 509 static const struct ocotp_params imx6sx_params = {
 510         .nregs = 128,
 511         .bank_address_words = 0,
 512         .set_timing = imx_ocotp_set_imx6_timing,
 513         .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
 514 };
 515
 516 static const struct ocotp_params imx6ul_params = {
 517         .nregs = 128,
 518         .bank_address_words = 0,
 519         .set_timing = imx_ocotp_set_imx6_timing,
 520         .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
 521 };
 522
 523 static const struct ocotp_params imx6ull_params = {
 524         .nregs = 64,
 525         .bank_address_words = 0,
 526         .set_timing = imx_ocotp_set_imx6_timing,
 527         .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
 528 };
 529
 530 static const struct ocotp_params imx7d_params = {
 531         .nregs = 64,
 532         .bank_address_words = 4,
 533         .set_timing = imx_ocotp_set_imx7_timing,
 534         .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
 535 };
 536
 537 static const struct ocotp_params imx7ulp_params = {
 538         .nregs = 256,
 539         .bank_address_words = 0,
 540         .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
 541 };
 542
 543 static const struct ocotp_params imx8mq_params = {
 544         .nregs = 256,
 545         .bank_address_words = 0,
 546         .set_timing = imx_ocotp_set_imx6_timing,
 547         .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
 548         .reverse_mac_address = true,
 549 };
 550
 551 static const struct ocotp_params imx8mm_params = {
 552         .nregs = 256,
 553         .bank_address_words = 0,
 554         .set_timing = imx_ocotp_set_imx6_timing,
 555         .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
 556         .reverse_mac_address = true,
 557 };
 558
 559 static const struct ocotp_params imx8mn_params = {
 560         .nregs = 256,
 561         .bank_address_words = 0,
 562         .set_timing = imx_ocotp_set_imx6_timing,
 563         .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
 564         .reverse_mac_address = true,
 565 };
 566
 567 static const struct ocotp_params imx8mp_params = {
 568         .nregs = 384,
 569         .bank_address_words = 0,
 570         .set_timing = imx_ocotp_set_imx6_timing,
 571         .ctrl = IMX_OCOTP_BM_CTRL_8MP,
 572         .reverse_mac_address = true,
 573 };
 574
 575 static const struct of_device_id imx_ocotp_dt_ids[] = {
 576         { .compatible = "fsl,imx6q-ocotp",  .data = &imx6q_params },
 577         { .compatible = "fsl,imx6sl-ocotp", .data = &imx6sl_params },
 578         { .compatible = "fsl,imx6sx-ocotp", .data = &imx6sx_params },
 579         { .compatible = "fsl,imx6ul-ocotp", .data = &imx6ul_params },
 580         { .compatible = "fsl,imx6ull-ocotp", .data = &imx6ull_params },
 581         { .compatible = "fsl,imx7d-ocotp",  .data = &imx7d_params },
 582         { .compatible = "fsl,imx6sll-ocotp", .data = &imx6sll_params },
 583         { .compatible = "fsl,imx7ulp-ocotp", .data = &imx7ulp_params },
 584         { .compatible = "fsl,imx8mq-ocotp", .data = &imx8mq_params },
 585         { .compatible = "fsl,imx8mm-ocotp", .data = &imx8mm_params },
 586         { .compatible = "fsl,imx8mn-ocotp", .data = &imx8mn_params },
 587         { .compatible = "fsl,imx8mp-ocotp", .data = &imx8mp_params },
 588         { },
 589 };
 590 MODULE_DEVICE_TABLE(of, imx_ocotp_dt_ids);
 591
 592 static void imx_ocotp_fixup_cell_info(struct nvmem_device *nvmem,
 593                                       struct nvmem_layout *layout,
 594                                       struct nvmem_cell_info *cell)
 595 {
 596         cell->read_post_process = imx_ocotp_cell_pp;
 597 }
 598
 599 struct nvmem_layout imx_ocotp_layout = {
 600         .fixup_cell_info = imx_ocotp_fixup_cell_info,
 601 };
 602
 603 static int imx_ocotp_probe(struct platform_device *pdev)
 604 {
 605         struct device *dev = &pdev->dev;
 606         struct ocotp_priv *priv;
 607         struct nvmem_device *nvmem;
 608
 609         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 610         if (!priv)
 611                 return -ENOMEM;
 612
 613         priv->dev = dev;
 614
 615         priv->base = devm_platform_ioremap_resource(pdev, 0);
 616         if (IS_ERR(priv->base))
 617                 return PTR_ERR(priv->base);
 618
 619         priv->clk = devm_clk_get(dev, NULL);
 620         if (IS_ERR(priv->clk))
 621                 return PTR_ERR(priv->clk);
 622
 623         priv->params = of_device_get_match_data(&pdev->dev);
 624         imx_ocotp_nvmem_config.size = 4 * priv->params->nregs;
 625         imx_ocotp_nvmem_config.dev = dev;
 626         imx_ocotp_nvmem_config.priv = priv;
 627         if (priv->params->reverse_mac_address)
 628                 imx_ocotp_nvmem_config.layout = &imx_ocotp_layout;
 629
 630         priv->config = &imx_ocotp_nvmem_config;
 631
 632         clk_prepare_enable(priv->clk);
 633         imx_ocotp_clr_err_if_set(priv);
 634         clk_disable_unprepare(priv->clk);
 635
 636         nvmem = devm_nvmem_register(dev, &imx_ocotp_nvmem_config);
 637
 638         return PTR_ERR_OR_ZERO(nvmem);
 639 }
 640
 641 static struct platform_driver imx_ocotp_driver = {
 642         .probe  = imx_ocotp_probe,
 643         .driver = {
 644                 .name   = "imx_ocotp",
 645                 .of_match_table = imx_ocotp_dt_ids,
 646         },
 647 };
 648 module_platform_driver(imx_ocotp_driver);
 649
 650 MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>");
 651 MODULE_DESCRIPTION("i.MX6/i.MX7 OCOTP fuse box driver");
 652 MODULE_LICENSE("GPL v2");