drivers/infiniband/hw/qedr/main.c

   1 /* QLogic qedr NIC Driver
   2  * Copyright (c) 2015-2016  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #include <linux/module.h>
  33 #include <rdma/ib_verbs.h>
  34 #include <rdma/ib_addr.h>
  35 #include <rdma/ib_user_verbs.h>
  36 #include <rdma/iw_cm.h>
  37 #include <rdma/ib_mad.h>
  38 #include <linux/netdevice.h>
  39 #include <linux/iommu.h>
  40 #include <linux/pci.h>
  41 #include <net/addrconf.h>
  42 #include <linux/idr.h>
  43
  44 #include <linux/qed/qed_chain.h>
  45 #include <linux/qed/qed_if.h>
  46 #include "qedr.h"
  47 #include "verbs.h"
  48 #include <rdma/qedr-abi.h>
  49 #include "qedr_iw_cm.h"
  50
  51 MODULE_DESCRIPTION("QLogic 40G/100G ROCE Driver");
  52 MODULE_AUTHOR("QLogic Corporation");
  53 MODULE_LICENSE("Dual BSD/GPL");
  54
  55 #define QEDR_WQ_MULTIPLIER_DFT  (3)
  56
  57 static void qedr_ib_dispatch_event(struct qedr_dev *dev, u8 port_num,
  58                                    enum ib_event_type type)
  59 {
  60         struct ib_event ibev;
  61
  62         ibev.device = &dev->ibdev;
  63         ibev.element.port_num = port_num;
  64         ibev.event = type;
  65
  66         ib_dispatch_event(&ibev);
  67 }
  68
  69 static enum rdma_link_layer qedr_link_layer(struct ib_device *device,
  70                                             u8 port_num)
  71 {
  72         return IB_LINK_LAYER_ETHERNET;
  73 }
  74
  75 static void qedr_get_dev_fw_str(struct ib_device *ibdev, char *str)
  76 {
  77         struct qedr_dev *qedr = get_qedr_dev(ibdev);
  78         u32 fw_ver = (u32)qedr->attr.fw_ver;
  79
  80         snprintf(str, IB_FW_VERSION_NAME_MAX, "%d. %d. %d. %d",
  81                  (fw_ver >> 24) & 0xFF, (fw_ver >> 16) & 0xFF,
  82                  (fw_ver >> 8) & 0xFF, fw_ver & 0xFF);
  83 }
  84
  85 static struct net_device *qedr_get_netdev(struct ib_device *dev, u8 port_num)
  86 {
  87         struct qedr_dev *qdev;
  88
  89         qdev = get_qedr_dev(dev);
  90         dev_hold(qdev->ndev);
  91
  92         /* The HW vendor's device driver must guarantee
  93          * that this function returns NULL before the net device reaches
  94          * NETDEV_UNREGISTER_FINAL state.
  95          */
  96         return qdev->ndev;
  97 }
  98
  99 static int qedr_roce_port_immutable(struct ib_device *ibdev, u8 port_num,
 100                                     struct ib_port_immutable *immutable)
 101 {
 102         struct ib_port_attr attr;
 103         int err;
 104
 105         err = qedr_query_port(ibdev, port_num, &attr);
 106         if (err)
 107                 return err;
 108
 109         immutable->pkey_tbl_len = attr.pkey_tbl_len;
 110         immutable->gid_tbl_len = attr.gid_tbl_len;
 111         immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE |
 112             RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
 113         immutable->max_mad_size = IB_MGMT_MAD_SIZE;
 114
 115         return 0;
 116 }
 117
 118 static int qedr_iw_port_immutable(struct ib_device *ibdev, u8 port_num,
 119                                   struct ib_port_immutable *immutable)
 120 {
 121         struct ib_port_attr attr;
 122         int err;
 123
 124         err = qedr_query_port(ibdev, port_num, &attr);
 125         if (err)
 126                 return err;
 127
 128         immutable->pkey_tbl_len = 1;
 129         immutable->gid_tbl_len = 1;
 130         immutable->core_cap_flags = RDMA_CORE_PORT_IWARP;
 131         immutable->max_mad_size = 0;
 132
 133         return 0;
 134 }
 135
 136 static int qedr_iw_register_device(struct qedr_dev *dev)
 137 {
 138         dev->ibdev.node_type = RDMA_NODE_RNIC;
 139         dev->ibdev.query_gid = qedr_iw_query_gid;
 140
 141         dev->ibdev.get_port_immutable = qedr_iw_port_immutable;
 142
 143         dev->ibdev.iwcm = kzalloc(sizeof(*dev->ibdev.iwcm), GFP_KERNEL);
 144         if (!dev->ibdev.iwcm)
 145                 return -ENOMEM;
 146
 147         dev->ibdev.iwcm->connect = qedr_iw_connect;
 148         dev->ibdev.iwcm->accept = qedr_iw_accept;
 149         dev->ibdev.iwcm->reject = qedr_iw_reject;
 150         dev->ibdev.iwcm->create_listen = qedr_iw_create_listen;
 151         dev->ibdev.iwcm->destroy_listen = qedr_iw_destroy_listen;
 152         dev->ibdev.iwcm->add_ref = qedr_iw_qp_add_ref;
 153         dev->ibdev.iwcm->rem_ref = qedr_iw_qp_rem_ref;
 154         dev->ibdev.iwcm->get_qp = qedr_iw_get_qp;
 155
 156         memcpy(dev->ibdev.iwcm->ifname,
 157                dev->ndev->name, sizeof(dev->ibdev.iwcm->ifname));
 158
 159         return 0;
 160 }
 161
 162 static void qedr_roce_register_device(struct qedr_dev *dev)
 163 {
 164         dev->ibdev.node_type = RDMA_NODE_IB_CA;
 165         dev->ibdev.query_gid = qedr_query_gid;
 166
 167         dev->ibdev.add_gid = qedr_add_gid;
 168         dev->ibdev.del_gid = qedr_del_gid;
 169
 170         dev->ibdev.get_port_immutable = qedr_roce_port_immutable;
 171 }
 172
 173 static int qedr_register_device(struct qedr_dev *dev)
 174 {
 175         int rc;
 176
 177         strlcpy(dev->ibdev.name, "qedr%d", IB_DEVICE_NAME_MAX);
 178
 179         dev->ibdev.node_guid = dev->attr.node_guid;
 180         memcpy(dev->ibdev.node_desc, QEDR_NODE_DESC, sizeof(QEDR_NODE_DESC));
 181         dev->ibdev.owner = THIS_MODULE;
 182         dev->ibdev.uverbs_abi_ver = QEDR_ABI_VERSION;
 183
 184         dev->ibdev.uverbs_cmd_mask = QEDR_UVERBS(GET_CONTEXT) |
 185                                      QEDR_UVERBS(QUERY_DEVICE) |
 186                                      QEDR_UVERBS(QUERY_PORT) |
 187                                      QEDR_UVERBS(ALLOC_PD) |
 188                                      QEDR_UVERBS(DEALLOC_PD) |
 189                                      QEDR_UVERBS(CREATE_COMP_CHANNEL) |
 190                                      QEDR_UVERBS(CREATE_CQ) |
 191                                      QEDR_UVERBS(RESIZE_CQ) |
 192                                      QEDR_UVERBS(DESTROY_CQ) |
 193                                      QEDR_UVERBS(REQ_NOTIFY_CQ) |
 194                                      QEDR_UVERBS(CREATE_QP) |
 195                                      QEDR_UVERBS(MODIFY_QP) |
 196                                      QEDR_UVERBS(QUERY_QP) |
 197                                      QEDR_UVERBS(DESTROY_QP) |
 198                                      QEDR_UVERBS(REG_MR) |
 199                                      QEDR_UVERBS(DEREG_MR) |
 200                                      QEDR_UVERBS(POLL_CQ) |
 201                                      QEDR_UVERBS(POST_SEND) |
 202                                      QEDR_UVERBS(POST_RECV);
 203
 204         if (IS_IWARP(dev)) {
 205                 rc = qedr_iw_register_device(dev);
 206                 if (rc)
 207                         return rc;
 208         } else {
 209                 qedr_roce_register_device(dev);
 210         }
 211
 212         dev->ibdev.phys_port_cnt = 1;
 213         dev->ibdev.num_comp_vectors = dev->num_cnq;
 214
 215         dev->ibdev.query_device = qedr_query_device;
 216         dev->ibdev.query_port = qedr_query_port;
 217         dev->ibdev.modify_port = qedr_modify_port;
 218
 219         dev->ibdev.alloc_ucontext = qedr_alloc_ucontext;
 220         dev->ibdev.dealloc_ucontext = qedr_dealloc_ucontext;
 221         dev->ibdev.mmap = qedr_mmap;
 222
 223         dev->ibdev.alloc_pd = qedr_alloc_pd;
 224         dev->ibdev.dealloc_pd = qedr_dealloc_pd;
 225
 226         dev->ibdev.create_cq = qedr_create_cq;
 227         dev->ibdev.destroy_cq = qedr_destroy_cq;
 228         dev->ibdev.resize_cq = qedr_resize_cq;
 229         dev->ibdev.req_notify_cq = qedr_arm_cq;
 230
 231         dev->ibdev.create_qp = qedr_create_qp;
 232         dev->ibdev.modify_qp = qedr_modify_qp;
 233         dev->ibdev.query_qp = qedr_query_qp;
 234         dev->ibdev.destroy_qp = qedr_destroy_qp;
 235
 236         dev->ibdev.query_pkey = qedr_query_pkey;
 237
 238         dev->ibdev.create_ah = qedr_create_ah;
 239         dev->ibdev.destroy_ah = qedr_destroy_ah;
 240
 241         dev->ibdev.get_dma_mr = qedr_get_dma_mr;
 242         dev->ibdev.dereg_mr = qedr_dereg_mr;
 243         dev->ibdev.reg_user_mr = qedr_reg_user_mr;
 244         dev->ibdev.alloc_mr = qedr_alloc_mr;
 245         dev->ibdev.map_mr_sg = qedr_map_mr_sg;
 246
 247         dev->ibdev.poll_cq = qedr_poll_cq;
 248         dev->ibdev.post_send = qedr_post_send;
 249         dev->ibdev.post_recv = qedr_post_recv;
 250
 251         dev->ibdev.process_mad = qedr_process_mad;
 252
 253         dev->ibdev.get_netdev = qedr_get_netdev;
 254
 255         dev->ibdev.dev.parent = &dev->pdev->dev;
 256
 257         dev->ibdev.get_link_layer = qedr_link_layer;
 258         dev->ibdev.get_dev_fw_str = qedr_get_dev_fw_str;
 259
 260         return ib_register_device(&dev->ibdev, NULL);
 261 }
 262
 263 /* This function allocates fast-path status block memory */
 264 static int qedr_alloc_mem_sb(struct qedr_dev *dev,
 265                              struct qed_sb_info *sb_info, u16 sb_id)
 266 {
 267         struct status_block *sb_virt;
 268         dma_addr_t sb_phys;
 269         int rc;
 270
 271         sb_virt = dma_alloc_coherent(&dev->pdev->dev,
 272                                      sizeof(*sb_virt), &sb_phys, GFP_KERNEL);
 273         if (!sb_virt)
 274                 return -ENOMEM;
 275
 276         rc = dev->ops->common->sb_init(dev->cdev, sb_info,
 277                                        sb_virt, sb_phys, sb_id,
 278                                        QED_SB_TYPE_CNQ);
 279         if (rc) {
 280                 pr_err("Status block initialization failed\n");
 281                 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_virt),
 282                                   sb_virt, sb_phys);
 283                 return rc;
 284         }
 285
 286         return 0;
 287 }
 288
 289 static void qedr_free_mem_sb(struct qedr_dev *dev,
 290                              struct qed_sb_info *sb_info, int sb_id)
 291 {
 292         if (sb_info->sb_virt) {
 293                 dev->ops->common->sb_release(dev->cdev, sb_info, sb_id);
 294                 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_info->sb_virt),
 295                                   (void *)sb_info->sb_virt, sb_info->sb_phys);
 296         }
 297 }
 298
 299 static void qedr_free_resources(struct qedr_dev *dev)
 300 {
 301         int i;
 302
 303         if (IS_IWARP(dev))
 304                 destroy_workqueue(dev->iwarp_wq);
 305
 306         for (i = 0; i < dev->num_cnq; i++) {
 307                 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
 308                 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
 309         }
 310
 311         kfree(dev->cnq_array);
 312         kfree(dev->sb_array);
 313         kfree(dev->sgid_tbl);
 314 }
 315
 316 static int qedr_alloc_resources(struct qedr_dev *dev)
 317 {
 318         struct qedr_cnq *cnq;
 319         __le16 *cons_pi;
 320         u16 n_entries;
 321         int i, rc;
 322
 323         dev->sgid_tbl = kzalloc(sizeof(union ib_gid) *
 324                                 QEDR_MAX_SGID, GFP_KERNEL);
 325         if (!dev->sgid_tbl)
 326                 return -ENOMEM;
 327
 328         spin_lock_init(&dev->sgid_lock);
 329
 330         if (IS_IWARP(dev)) {
 331                 spin_lock_init(&dev->idr_lock);
 332                 idr_init(&dev->qpidr);
 333                 dev->iwarp_wq = create_singlethread_workqueue("qedr_iwarpq");
 334         }
 335
 336         /* Allocate Status blocks for CNQ */
 337         dev->sb_array = kcalloc(dev->num_cnq, sizeof(*dev->sb_array),
 338                                 GFP_KERNEL);
 339         if (!dev->sb_array) {
 340                 rc = -ENOMEM;
 341                 goto err1;
 342         }
 343
 344         dev->cnq_array = kcalloc(dev->num_cnq,
 345                                  sizeof(*dev->cnq_array), GFP_KERNEL);
 346         if (!dev->cnq_array) {
 347                 rc = -ENOMEM;
 348                 goto err2;
 349         }
 350
 351         dev->sb_start = dev->ops->rdma_get_start_sb(dev->cdev);
 352
 353         /* Allocate CNQ PBLs */
 354         n_entries = min_t(u32, QED_RDMA_MAX_CNQ_SIZE, QEDR_ROCE_MAX_CNQ_SIZE);
 355         for (i = 0; i < dev->num_cnq; i++) {
 356                 cnq = &dev->cnq_array[i];
 357
 358                 rc = qedr_alloc_mem_sb(dev, &dev->sb_array[i],
 359                                        dev->sb_start + i);
 360                 if (rc)
 361                         goto err3;
 362
 363                 rc = dev->ops->common->chain_alloc(dev->cdev,
 364                                                    QED_CHAIN_USE_TO_CONSUME,
 365                                                    QED_CHAIN_MODE_PBL,
 366                                                    QED_CHAIN_CNT_TYPE_U16,
 367                                                    n_entries,
 368                                                    sizeof(struct regpair *),
 369                                                    &cnq->pbl, NULL);
 370                 if (rc)
 371                         goto err4;
 372
 373                 cnq->dev = dev;
 374                 cnq->sb = &dev->sb_array[i];
 375                 cons_pi = dev->sb_array[i].sb_virt->pi_array;
 376                 cnq->hw_cons_ptr = &cons_pi[QED_ROCE_PROTOCOL_INDEX];
 377                 cnq->index = i;
 378                 sprintf(cnq->name, "qedr%d@pci:%s", i, pci_name(dev->pdev));
 379
 380                 DP_DEBUG(dev, QEDR_MSG_INIT, "cnq[%d].cons=%d\n",
 381                          i, qed_chain_get_cons_idx(&cnq->pbl));
 382         }
 383
 384         return 0;
 385 err4:
 386         qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
 387 err3:
 388         for (--i; i >= 0; i--) {
 389                 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
 390                 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
 391         }
 392         kfree(dev->cnq_array);
 393 err2:
 394         kfree(dev->sb_array);
 395 err1:
 396         kfree(dev->sgid_tbl);
 397         return rc;
 398 }
 399
 400 /* QEDR sysfs interface */
 401 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
 402                         char *buf)
 403 {
 404         struct qedr_dev *dev = dev_get_drvdata(device);
 405
 406         return scnprintf(buf, PAGE_SIZE, "0x%x\n", dev->pdev->vendor);
 407 }
 408
 409 static ssize_t show_hca_type(struct device *device,
 410                              struct device_attribute *attr, char *buf)
 411 {
 412         return scnprintf(buf, PAGE_SIZE, "%s\n", "HCA_TYPE_TO_SET");
 413 }
 414
 415 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
 416 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca_type, NULL);
 417
 418 static struct device_attribute *qedr_attributes[] = {
 419         &dev_attr_hw_rev,
 420         &dev_attr_hca_type
 421 };
 422
 423 static void qedr_remove_sysfiles(struct qedr_dev *dev)
 424 {
 425         int i;
 426
 427         for (i = 0; i < ARRAY_SIZE(qedr_attributes); i++)
 428                 device_remove_file(&dev->ibdev.dev, qedr_attributes[i]);
 429 }
 430
 431 static void qedr_pci_set_atomic(struct qedr_dev *dev, struct pci_dev *pdev)
 432 {
 433         int rc = pci_enable_atomic_ops_to_root(pdev,
 434                                                PCI_EXP_DEVCAP2_ATOMIC_COMP64);
 435
 436         if (rc) {
 437                 dev->atomic_cap = IB_ATOMIC_NONE;
 438                 DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability disabled\n");
 439         } else {
 440                 dev->atomic_cap = IB_ATOMIC_GLOB;
 441                 DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability enabled\n");
 442         }
 443 }
 444
 445 static const struct qed_rdma_ops *qed_ops;
 446
 447 #define HILO_U64(hi, lo)                ((((u64)(hi)) << 32) + (lo))
 448
 449 static irqreturn_t qedr_irq_handler(int irq, void *handle)
 450 {
 451         u16 hw_comp_cons, sw_comp_cons;
 452         struct qedr_cnq *cnq = handle;
 453         struct regpair *cq_handle;
 454         struct qedr_cq *cq;
 455
 456         qed_sb_ack(cnq->sb, IGU_INT_DISABLE, 0);
 457
 458         qed_sb_update_sb_idx(cnq->sb);
 459
 460         hw_comp_cons = le16_to_cpu(*cnq->hw_cons_ptr);
 461         sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
 462
 463         /* Align protocol-index and chain reads */
 464         rmb();
 465
 466         while (sw_comp_cons != hw_comp_cons) {
 467                 cq_handle = (struct regpair *)qed_chain_consume(&cnq->pbl);
 468                 cq = (struct qedr_cq *)(uintptr_t)HILO_U64(cq_handle->hi,
 469                                 cq_handle->lo);
 470
 471                 if (cq == NULL) {
 472                         DP_ERR(cnq->dev,
 473                                "Received NULL CQ cq_handle->hi=%d cq_handle->lo=%d sw_comp_cons=%d hw_comp_cons=%d\n",
 474                                cq_handle->hi, cq_handle->lo, sw_comp_cons,
 475                                hw_comp_cons);
 476
 477                         break;
 478                 }
 479
 480                 if (cq->sig != QEDR_CQ_MAGIC_NUMBER) {
 481                         DP_ERR(cnq->dev,
 482                                "Problem with cq signature, cq_handle->hi=%d ch_handle->lo=%d cq=%p\n",
 483                                cq_handle->hi, cq_handle->lo, cq);
 484                         break;
 485                 }
 486
 487                 cq->arm_flags = 0;
 488
 489                 if (!cq->destroyed && cq->ibcq.comp_handler)
 490                         (*cq->ibcq.comp_handler)
 491                                 (&cq->ibcq, cq->ibcq.cq_context);
 492
 493                 /* The CQ's CNQ notification counter is checked before
 494                  * destroying the CQ in a busy-wait loop that waits for all of
 495                  * the CQ's CNQ interrupts to be processed. It is increased
 496                  * here, only after the completion handler, to ensure that the
 497                  * the handler is not running when the CQ is destroyed.
 498                  */
 499                 cq->cnq_notif++;
 500
 501                 sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
 502
 503                 cnq->n_comp++;
 504         }
 505
 506         qed_ops->rdma_cnq_prod_update(cnq->dev->rdma_ctx, cnq->index,
 507                                       sw_comp_cons);
 508
 509         qed_sb_ack(cnq->sb, IGU_INT_ENABLE, 1);
 510
 511         return IRQ_HANDLED;
 512 }
 513
 514 static void qedr_sync_free_irqs(struct qedr_dev *dev)
 515 {
 516         u32 vector;
 517         int i;
 518
 519         for (i = 0; i < dev->int_info.used_cnt; i++) {
 520                 if (dev->int_info.msix_cnt) {
 521                         vector = dev->int_info.msix[i * dev->num_hwfns].vector;
 522                         synchronize_irq(vector);
 523                         free_irq(vector, &dev->cnq_array[i]);
 524                 }
 525         }
 526
 527         dev->int_info.used_cnt = 0;
 528 }
 529
 530 static int qedr_req_msix_irqs(struct qedr_dev *dev)
 531 {
 532         int i, rc = 0;
 533
 534         if (dev->num_cnq > dev->int_info.msix_cnt) {
 535                 DP_ERR(dev,
 536                        "Interrupt mismatch: %d CNQ queues > %d MSI-x vectors\n",
 537                        dev->num_cnq, dev->int_info.msix_cnt);
 538                 return -EINVAL;
 539         }
 540
 541         for (i = 0; i < dev->num_cnq; i++) {
 542                 rc = request_irq(dev->int_info.msix[i * dev->num_hwfns].vector,
 543                                  qedr_irq_handler, 0, dev->cnq_array[i].name,
 544                                  &dev->cnq_array[i]);
 545                 if (rc) {
 546                         DP_ERR(dev, "Request cnq %d irq failed\n", i);
 547                         qedr_sync_free_irqs(dev);
 548                 } else {
 549                         DP_DEBUG(dev, QEDR_MSG_INIT,
 550                                  "Requested cnq irq for %s [entry %d]. Cookie is at %p\n",
 551                                  dev->cnq_array[i].name, i,
 552                                  &dev->cnq_array[i]);
 553                         dev->int_info.used_cnt++;
 554                 }
 555         }
 556
 557         return rc;
 558 }
 559
 560 static int qedr_setup_irqs(struct qedr_dev *dev)
 561 {
 562         int rc;
 563
 564         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs\n");
 565
 566         /* Learn Interrupt configuration */
 567         rc = dev->ops->rdma_set_rdma_int(dev->cdev, dev->num_cnq);
 568         if (rc < 0)
 569                 return rc;
 570
 571         rc = dev->ops->rdma_get_rdma_int(dev->cdev, &dev->int_info);
 572         if (rc) {
 573                 DP_DEBUG(dev, QEDR_MSG_INIT, "get_rdma_int failed\n");
 574                 return rc;
 575         }
 576
 577         if (dev->int_info.msix_cnt) {
 578                 DP_DEBUG(dev, QEDR_MSG_INIT, "rdma msix_cnt = %d\n",
 579                          dev->int_info.msix_cnt);
 580                 rc = qedr_req_msix_irqs(dev);
 581                 if (rc)
 582                         return rc;
 583         }
 584
 585         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs succeeded\n");
 586
 587         return 0;
 588 }
 589
 590 static int qedr_set_device_attr(struct qedr_dev *dev)
 591 {
 592         struct qed_rdma_device *qed_attr;
 593         struct qedr_device_attr *attr;
 594         u32 page_size;
 595
 596         /* Part 1 - query core capabilities */
 597         qed_attr = dev->ops->rdma_query_device(dev->rdma_ctx);
 598
 599         /* Part 2 - check capabilities */
 600         page_size = ~dev->attr.page_size_caps + 1;
 601         if (page_size > PAGE_SIZE) {
 602                 DP_ERR(dev,
 603                        "Kernel PAGE_SIZE is %ld which is smaller than minimum page size (%d) required by qedr\n",
 604                        PAGE_SIZE, page_size);
 605                 return -ENODEV;
 606         }
 607
 608         /* Part 3 - copy and update capabilities */
 609         attr = &dev->attr;
 610         attr->vendor_id = qed_attr->vendor_id;
 611         attr->vendor_part_id = qed_attr->vendor_part_id;
 612         attr->hw_ver = qed_attr->hw_ver;
 613         attr->fw_ver = qed_attr->fw_ver;
 614         attr->node_guid = qed_attr->node_guid;
 615         attr->sys_image_guid = qed_attr->sys_image_guid;
 616         attr->max_cnq = qed_attr->max_cnq;
 617         attr->max_sge = qed_attr->max_sge;
 618         attr->max_inline = qed_attr->max_inline;
 619         attr->max_sqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_SQE);
 620         attr->max_rqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_RQE);
 621         attr->max_qp_resp_rd_atomic_resc = qed_attr->max_qp_resp_rd_atomic_resc;
 622         attr->max_qp_req_rd_atomic_resc = qed_attr->max_qp_req_rd_atomic_resc;
 623         attr->max_dev_resp_rd_atomic_resc =
 624             qed_attr->max_dev_resp_rd_atomic_resc;
 625         attr->max_cq = qed_attr->max_cq;
 626         attr->max_qp = qed_attr->max_qp;
 627         attr->max_mr = qed_attr->max_mr;
 628         attr->max_mr_size = qed_attr->max_mr_size;
 629         attr->max_cqe = min_t(u64, qed_attr->max_cqe, QEDR_MAX_CQES);
 630         attr->max_mw = qed_attr->max_mw;
 631         attr->max_fmr = qed_attr->max_fmr;
 632         attr->max_mr_mw_fmr_pbl = qed_attr->max_mr_mw_fmr_pbl;
 633         attr->max_mr_mw_fmr_size = qed_attr->max_mr_mw_fmr_size;
 634         attr->max_pd = qed_attr->max_pd;
 635         attr->max_ah = qed_attr->max_ah;
 636         attr->max_pkey = qed_attr->max_pkey;
 637         attr->max_srq = qed_attr->max_srq;
 638         attr->max_srq_wr = qed_attr->max_srq_wr;
 639         attr->dev_caps = qed_attr->dev_caps;
 640         attr->page_size_caps = qed_attr->page_size_caps;
 641         attr->dev_ack_delay = qed_attr->dev_ack_delay;
 642         attr->reserved_lkey = qed_attr->reserved_lkey;
 643         attr->bad_pkey_counter = qed_attr->bad_pkey_counter;
 644         attr->max_stats_queues = qed_attr->max_stats_queues;
 645
 646         return 0;
 647 }
 648
 649 static void qedr_unaffiliated_event(void *context, u8 event_code)
 650 {
 651         pr_err("unaffiliated event not implemented yet\n");
 652 }
 653
 654 static void qedr_affiliated_event(void *context, u8 e_code, void *fw_handle)
 655 {
 656 #define EVENT_TYPE_NOT_DEFINED  0
 657 #define EVENT_TYPE_CQ           1
 658 #define EVENT_TYPE_QP           2
 659         struct qedr_dev *dev = (struct qedr_dev *)context;
 660         struct regpair *async_handle = (struct regpair *)fw_handle;
 661         u64 roce_handle64 = ((u64) async_handle->hi << 32) + async_handle->lo;
 662         u8 event_type = EVENT_TYPE_NOT_DEFINED;
 663         struct ib_event event;
 664         struct ib_cq *ibcq;
 665         struct ib_qp *ibqp;
 666         struct qedr_cq *cq;
 667         struct qedr_qp *qp;
 668
 669         switch (e_code) {
 670         case ROCE_ASYNC_EVENT_CQ_OVERFLOW_ERR:
 671                 event.event = IB_EVENT_CQ_ERR;
 672                 event_type = EVENT_TYPE_CQ;
 673                 break;
 674         case ROCE_ASYNC_EVENT_SQ_DRAINED:
 675                 event.event = IB_EVENT_SQ_DRAINED;
 676                 event_type = EVENT_TYPE_QP;
 677                 break;
 678         case ROCE_ASYNC_EVENT_QP_CATASTROPHIC_ERR:
 679                 event.event = IB_EVENT_QP_FATAL;
 680                 event_type = EVENT_TYPE_QP;
 681                 break;
 682         case ROCE_ASYNC_EVENT_LOCAL_INVALID_REQUEST_ERR:
 683                 event.event = IB_EVENT_QP_REQ_ERR;
 684                 event_type = EVENT_TYPE_QP;
 685                 break;
 686         case ROCE_ASYNC_EVENT_LOCAL_ACCESS_ERR:
 687                 event.event = IB_EVENT_QP_ACCESS_ERR;
 688                 event_type = EVENT_TYPE_QP;
 689                 break;
 690         default:
 691                 DP_ERR(dev, "unsupported event %d on handle=%llx\n", e_code,
 692                        roce_handle64);
 693         }
 694
 695         switch (event_type) {
 696         case EVENT_TYPE_CQ:
 697                 cq = (struct qedr_cq *)(uintptr_t)roce_handle64;
 698                 if (cq) {
 699                         ibcq = &cq->ibcq;
 700                         if (ibcq->event_handler) {
 701                                 event.device = ibcq->device;
 702                                 event.element.cq = ibcq;
 703                                 ibcq->event_handler(&event, ibcq->cq_context);
 704                         }
 705                 } else {
 706                         WARN(1,
 707                              "Error: CQ event with NULL pointer ibcq. Handle=%llx\n",
 708                              roce_handle64);
 709                 }
 710                 DP_ERR(dev, "CQ event %d on hanlde %p\n", e_code, cq);
 711                 break;
 712         case EVENT_TYPE_QP:
 713                 qp = (struct qedr_qp *)(uintptr_t)roce_handle64;
 714                 if (qp) {
 715                         ibqp = &qp->ibqp;
 716                         if (ibqp->event_handler) {
 717                                 event.device = ibqp->device;
 718                                 event.element.qp = ibqp;
 719                                 ibqp->event_handler(&event, ibqp->qp_context);
 720                         }
 721                 } else {
 722                         WARN(1,
 723                              "Error: QP event with NULL pointer ibqp. Handle=%llx\n",
 724                              roce_handle64);
 725                 }
 726                 DP_ERR(dev, "QP event %d on hanlde %p\n", e_code, qp);
 727                 break;
 728         default:
 729                 break;
 730         }
 731 }
 732
 733 static int qedr_init_hw(struct qedr_dev *dev)
 734 {
 735         struct qed_rdma_add_user_out_params out_params;
 736         struct qed_rdma_start_in_params *in_params;
 737         struct qed_rdma_cnq_params *cur_pbl;
 738         struct qed_rdma_events events;
 739         dma_addr_t p_phys_table;
 740         u32 page_cnt;
 741         int rc = 0;
 742         int i;
 743
 744         in_params =  kzalloc(sizeof(*in_params), GFP_KERNEL);
 745         if (!in_params) {
 746                 rc = -ENOMEM;
 747                 goto out;
 748         }
 749
 750         in_params->desired_cnq = dev->num_cnq;
 751         for (i = 0; i < dev->num_cnq; i++) {
 752                 cur_pbl = &in_params->cnq_pbl_list[i];
 753
 754                 page_cnt = qed_chain_get_page_cnt(&dev->cnq_array[i].pbl);
 755                 cur_pbl->num_pbl_pages = page_cnt;
 756
 757                 p_phys_table = qed_chain_get_pbl_phys(&dev->cnq_array[i].pbl);
 758                 cur_pbl->pbl_ptr = (u64)p_phys_table;
 759         }
 760
 761         events.affiliated_event = qedr_affiliated_event;
 762         events.unaffiliated_event = qedr_unaffiliated_event;
 763         events.context = dev;
 764
 765         in_params->events = &events;
 766         in_params->cq_mode = QED_RDMA_CQ_MODE_32_BITS;
 767         in_params->max_mtu = dev->ndev->mtu;
 768         dev->iwarp_max_mtu = dev->ndev->mtu;
 769         ether_addr_copy(&in_params->mac_addr[0], dev->ndev->dev_addr);
 770
 771         rc = dev->ops->rdma_init(dev->cdev, in_params);
 772         if (rc)
 773                 goto out;
 774
 775         rc = dev->ops->rdma_add_user(dev->rdma_ctx, &out_params);
 776         if (rc)
 777                 goto out;
 778
 779         dev->db_addr = (void __iomem *)(uintptr_t)out_params.dpi_addr;
 780         dev->db_phys_addr = out_params.dpi_phys_addr;
 781         dev->db_size = out_params.dpi_size;
 782         dev->dpi = out_params.dpi;
 783
 784         rc = qedr_set_device_attr(dev);
 785 out:
 786         kfree(in_params);
 787         if (rc)
 788                 DP_ERR(dev, "Init HW Failed rc = %d\n", rc);
 789
 790         return rc;
 791 }
 792
 793 static void qedr_stop_hw(struct qedr_dev *dev)
 794 {
 795         dev->ops->rdma_remove_user(dev->rdma_ctx, dev->dpi);
 796         dev->ops->rdma_stop(dev->rdma_ctx);
 797 }
 798
 799 static struct qedr_dev *qedr_add(struct qed_dev *cdev, struct pci_dev *pdev,
 800                                  struct net_device *ndev)
 801 {
 802         struct qed_dev_rdma_info dev_info;
 803         struct qedr_dev *dev;
 804         int rc = 0, i;
 805
 806         dev = (struct qedr_dev *)ib_alloc_device(sizeof(*dev));
 807         if (!dev) {
 808                 pr_err("Unable to allocate ib device\n");
 809                 return NULL;
 810         }
 811
 812         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr add device called\n");
 813
 814         dev->pdev = pdev;
 815         dev->ndev = ndev;
 816         dev->cdev = cdev;
 817
 818         qed_ops = qed_get_rdma_ops();
 819         if (!qed_ops) {
 820                 DP_ERR(dev, "Failed to get qed roce operations\n");
 821                 goto init_err;
 822         }
 823
 824         dev->ops = qed_ops;
 825         rc = qed_ops->fill_dev_info(cdev, &dev_info);
 826         if (rc)
 827                 goto init_err;
 828
 829         dev->user_dpm_enabled = dev_info.user_dpm_enabled;
 830         dev->rdma_type = dev_info.rdma_type;
 831         dev->num_hwfns = dev_info.common.num_hwfns;
 832         dev->rdma_ctx = dev->ops->rdma_get_rdma_ctx(cdev);
 833
 834         dev->num_cnq = dev->ops->rdma_get_min_cnq_msix(cdev);
 835         if (!dev->num_cnq) {
 836                 DP_ERR(dev, "not enough CNQ resources.\n");
 837                 goto init_err;
 838         }
 839
 840         dev->wq_multiplier = QEDR_WQ_MULTIPLIER_DFT;
 841
 842         qedr_pci_set_atomic(dev, pdev);
 843
 844         rc = qedr_alloc_resources(dev);
 845         if (rc)
 846                 goto init_err;
 847
 848         rc = qedr_init_hw(dev);
 849         if (rc)
 850                 goto alloc_err;
 851
 852         rc = qedr_setup_irqs(dev);
 853         if (rc)
 854                 goto irq_err;
 855
 856         rc = qedr_register_device(dev);
 857         if (rc) {
 858                 DP_ERR(dev, "Unable to allocate register device\n");
 859                 goto reg_err;
 860         }
 861
 862         for (i = 0; i < ARRAY_SIZE(qedr_attributes); i++)
 863                 if (device_create_file(&dev->ibdev.dev, qedr_attributes[i]))
 864                         goto sysfs_err;
 865
 866         if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
 867                 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE);
 868
 869         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr driver loaded successfully\n");
 870         return dev;
 871
 872 sysfs_err:
 873         ib_unregister_device(&dev->ibdev);
 874 reg_err:
 875         qedr_sync_free_irqs(dev);
 876 irq_err:
 877         qedr_stop_hw(dev);
 878 alloc_err:
 879         qedr_free_resources(dev);
 880 init_err:
 881         ib_dealloc_device(&dev->ibdev);
 882         DP_ERR(dev, "qedr driver load failed rc=%d\n", rc);
 883
 884         return NULL;
 885 }
 886
 887 static void qedr_remove(struct qedr_dev *dev)
 888 {
 889         /* First unregister with stack to stop all the active traffic
 890          * of the registered clients.
 891          */
 892         qedr_remove_sysfiles(dev);
 893         ib_unregister_device(&dev->ibdev);
 894
 895         qedr_stop_hw(dev);
 896         qedr_sync_free_irqs(dev);
 897         qedr_free_resources(dev);
 898         ib_dealloc_device(&dev->ibdev);
 899 }
 900
 901 static void qedr_close(struct qedr_dev *dev)
 902 {
 903         if (test_and_clear_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
 904                 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ERR);
 905 }
 906
 907 static void qedr_shutdown(struct qedr_dev *dev)
 908 {
 909         qedr_close(dev);
 910         qedr_remove(dev);
 911 }
 912
 913 static void qedr_open(struct qedr_dev *dev)
 914 {
 915         if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
 916                 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE);
 917 }
 918
 919 static void qedr_mac_address_change(struct qedr_dev *dev)
 920 {
 921         union ib_gid *sgid = &dev->sgid_tbl[0];
 922         u8 guid[8], mac_addr[6];
 923         int rc;
 924
 925         /* Update SGID */
 926         ether_addr_copy(&mac_addr[0], dev->ndev->dev_addr);
 927         guid[0] = mac_addr[0] ^ 2;
 928         guid[1] = mac_addr[1];
 929         guid[2] = mac_addr[2];
 930         guid[3] = 0xff;
 931         guid[4] = 0xfe;
 932         guid[5] = mac_addr[3];
 933         guid[6] = mac_addr[4];
 934         guid[7] = mac_addr[5];
 935         sgid->global.subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
 936         memcpy(&sgid->raw[8], guid, sizeof(guid));
 937
 938         /* Update LL2 */
 939         rc = dev->ops->ll2_set_mac_filter(dev->cdev,
 940                                           dev->gsi_ll2_mac_address,
 941                                           dev->ndev->dev_addr);
 942
 943         ether_addr_copy(dev->gsi_ll2_mac_address, dev->ndev->dev_addr);
 944
 945         qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_GID_CHANGE);
 946
 947         if (rc)
 948                 DP_ERR(dev, "Error updating mac filter\n");
 949 }
 950
 951 /* event handling via NIC driver ensures that all the NIC specific
 952  * initialization done before RoCE driver notifies
 953  * event to stack.
 954  */
 955 static void qedr_notify(struct qedr_dev *dev, enum qede_rdma_event event)
 956 {
 957         switch (event) {
 958         case QEDE_UP:
 959                 qedr_open(dev);
 960                 break;
 961         case QEDE_DOWN:
 962                 qedr_close(dev);
 963                 break;
 964         case QEDE_CLOSE:
 965                 qedr_shutdown(dev);
 966                 break;
 967         case QEDE_CHANGE_ADDR:
 968                 qedr_mac_address_change(dev);
 969                 break;
 970         default:
 971                 pr_err("Event not supported\n");
 972         }
 973 }
 974
 975 static struct qedr_driver qedr_drv = {
 976         .name = "qedr_driver",
 977         .add = qedr_add,
 978         .remove = qedr_remove,
 979         .notify = qedr_notify,
 980 };
 981
 982 static int __init qedr_init_module(void)
 983 {
 984         return qede_rdma_register_driver(&qedr_drv);
 985 }
 986
 987 static void __exit qedr_exit_module(void)
 988 {
 989         qede_rdma_unregister_driver(&qedr_drv);
 990 }
 991
 992 module_init(qedr_init_module);
 993 module_exit(qedr_exit_module);