2 * Copyright (c) 2000 Taku YAMAMOTO <taku@cent.saitama-u.ac.jp>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * $Id: maestro.c,v 1.12 2000/09/06 03:32:34 taku Exp $
27 * $FreeBSD: src/sys/dev/sound/pci/maestro.c,v 1.2.2.5 2002/04/22 15:49:32 cg Exp $
28 * $DragonFly: src/sys/dev/sound/pci/maestro.c,v 1.5 2005/06/10 23:06:59 dillon Exp $
34 * Part of this code (especially in many magic numbers) was heavily inspired
35 * by the Linux driver originally written by
36 * Alan Cox <alan.cox@linux.org>, modified heavily by
37 * Zach Brown <zab@zabbo.net>.
39 * busdma()-ize and buffer size reduction were suggested by
40 * Cameron Grant <gandalf@vilnya.demon.co.uk>.
41 * Also he showed me the way to use busdma() suite.
43 * Internal speaker problems on NEC VersaPro's and Dell Inspiron 7500
45 * Munehiro Matsuda <haro@tk.kubota.co.jp>,
46 * who brought patches based on the Linux driver with some simplification.
49 #include <dev/sound/pcm/sound.h>
50 #include <dev/sound/pcm/ac97.h>
51 #include <bus/pci/pcireg.h>
52 #include <bus/pci/pcivar.h>
54 #include <dev/sound/pci/maestro_reg.h>
56 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/maestro.c,v 1.5 2005/06/10 23:06:59 dillon Exp $");
58 #define inline __inline
61 * PCI IDs of supported chips:
63 * MAESTRO-1 0x01001285
64 * MAESTRO-2 0x1968125d
65 * MAESTRO-2E 0x1978125d
68 #define MAESTRO_1_PCI_ID 0x01001285
69 #define MAESTRO_2_PCI_ID 0x1968125d
70 #define MAESTRO_2E_PCI_ID 0x1978125d
72 #define NEC_SUBID1 0x80581033 /* Taken from Linux driver */
73 #define NEC_SUBID2 0x803c1033 /* NEC VersaProNX VA26D */
76 # define AGG_MAXPLAYCH 4
79 #define AGG_DEFAULT_BUFSZ 0x4000 /* 0x1000, but gets underflows */
82 /* -----------------------------
86 struct agg_info *parent;
87 struct pcm_channel *channel;
88 struct snd_dbuf *buffer;
100 struct resource *reg;
104 bus_space_handle_t sh;
105 bus_dma_tag_t parent_dmat;
107 struct resource *irq;
114 struct ac97_info *codec;
118 u_int playchns, active;
119 struct agg_chinfo pch[AGG_MAXPLAYCH];
120 struct agg_chinfo rch;
123 static inline void ringbus_setdest(struct agg_info*, int, int);
125 static inline u_int16_t wp_rdreg(struct agg_info*, u_int16_t);
126 static inline void wp_wrreg(struct agg_info*, u_int16_t, u_int16_t);
127 static inline u_int16_t wp_rdapu(struct agg_info*, int, u_int16_t);
128 static inline void wp_wrapu(struct agg_info*, int, u_int16_t, u_int16_t);
129 static inline void wp_settimer(struct agg_info*, u_int);
130 static inline void wp_starttimer(struct agg_info*);
131 static inline void wp_stoptimer(struct agg_info*);
133 static inline u_int16_t wc_rdreg(struct agg_info*, u_int16_t);
134 static inline void wc_wrreg(struct agg_info*, u_int16_t, u_int16_t);
135 static inline u_int16_t wc_rdchctl(struct agg_info*, int);
136 static inline void wc_wrchctl(struct agg_info*, int, u_int16_t);
138 static inline void agg_power(struct agg_info*, int);
140 static void agg_init(struct agg_info*);
142 static void aggch_start_dac(struct agg_chinfo*);
143 static void aggch_stop_dac(struct agg_chinfo*);
145 static inline void suppress_jitter(struct agg_chinfo*);
147 static inline u_int calc_timer_freq(struct agg_chinfo*);
148 static void set_timer(struct agg_info*);
150 static void agg_intr(void *);
151 static int agg_probe(device_t);
152 static int agg_attach(device_t);
153 static int agg_detach(device_t);
154 static int agg_suspend(device_t);
155 static int agg_resume(device_t);
156 static int agg_shutdown(device_t);
158 static void *dma_malloc(struct agg_info*, u_int32_t, bus_addr_t*);
159 static void dma_free(struct agg_info*, void *);
161 /* -----------------------------
167 /* -------------------------------------------------------------------- */
170 agg_ac97_init(kobj_t obj, void *sc)
172 struct agg_info *ess = sc;
174 return (bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT) & CODEC_STAT_MASK)? 0 : 1;
178 agg_rdcodec(kobj_t obj, void *sc, int regno)
180 struct agg_info *ess = sc;
183 /* We have to wait for a SAFE time to write addr/data */
184 for (t = 0; t < 20; t++) {
185 if ((bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
186 & CODEC_STAT_MASK) != CODEC_STAT_PROGLESS)
188 DELAY(2); /* 20.8us / 13 */
191 device_printf(ess->dev, "agg_rdcodec() PROGLESS timed out.\n");
193 bus_space_write_1(ess->st, ess->sh, PORT_CODEC_CMD,
194 CODEC_CMD_READ | regno);
195 DELAY(21); /* AC97 cycle = 20.8usec */
197 /* Wait for data retrieve */
198 for (t = 0; t < 20; t++) {
199 if ((bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
200 & CODEC_STAT_MASK) == CODEC_STAT_RW_DONE)
202 DELAY(2); /* 20.8us / 13 */
205 /* Timed out, but perform dummy read. */
206 device_printf(ess->dev, "agg_rdcodec() RW_DONE timed out.\n");
208 return bus_space_read_2(ess->st, ess->sh, PORT_CODEC_REG);
212 agg_wrcodec(kobj_t obj, void *sc, int regno, u_int32_t data)
215 struct agg_info *ess = sc;
217 /* We have to wait for a SAFE time to write addr/data */
218 for (t = 0; t < 20; t++) {
219 if ((bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
220 & CODEC_STAT_MASK) != CODEC_STAT_PROGLESS)
222 DELAY(2); /* 20.8us / 13 */
225 /* Timed out. Abort writing. */
226 device_printf(ess->dev, "agg_wrcodec() PROGLESS timed out.\n");
230 bus_space_write_2(ess->st, ess->sh, PORT_CODEC_REG, data);
231 bus_space_write_1(ess->st, ess->sh, PORT_CODEC_CMD,
232 CODEC_CMD_WRITE | regno);
237 static kobj_method_t agg_ac97_methods[] = {
238 KOBJMETHOD(ac97_init, agg_ac97_init),
239 KOBJMETHOD(ac97_read, agg_rdcodec),
240 KOBJMETHOD(ac97_write, agg_wrcodec),
243 AC97_DECLARE(agg_ac97);
245 /* -------------------------------------------------------------------- */
248 ringbus_setdest(struct agg_info *ess, int src, int dest)
252 data = bus_space_read_4(ess->st, ess->sh, PORT_RINGBUS_CTRL);
253 data &= ~(0xfU << src);
254 data |= (0xfU & dest) << src;
255 bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, data);
260 static inline u_int16_t
261 wp_rdreg(struct agg_info *ess, u_int16_t reg)
263 bus_space_write_2(ess->st, ess->sh, PORT_DSP_INDEX, reg);
264 return bus_space_read_2(ess->st, ess->sh, PORT_DSP_DATA);
268 wp_wrreg(struct agg_info *ess, u_int16_t reg, u_int16_t data)
270 bus_space_write_2(ess->st, ess->sh, PORT_DSP_INDEX, reg);
271 bus_space_write_2(ess->st, ess->sh, PORT_DSP_DATA, data);
275 apu_setindex(struct agg_info *ess, u_int16_t reg)
279 wp_wrreg(ess, WPREG_CRAM_PTR, reg);
280 /* Sometimes WP fails to set apu register index. */
281 for (t = 0; t < 1000; t++) {
282 if (bus_space_read_2(ess->st, ess->sh, PORT_DSP_DATA) == reg)
284 bus_space_write_2(ess->st, ess->sh, PORT_DSP_DATA, reg);
287 device_printf(ess->dev, "apu_setindex() timed out.\n");
290 static inline u_int16_t
291 wp_rdapu(struct agg_info *ess, int ch, u_int16_t reg)
295 apu_setindex(ess, ((unsigned)ch << 4) + reg);
296 ret = wp_rdreg(ess, WPREG_DATA_PORT);
301 wp_wrapu(struct agg_info *ess, int ch, u_int16_t reg, u_int16_t data)
305 apu_setindex(ess, ((unsigned)ch << 4) + reg);
306 wp_wrreg(ess, WPREG_DATA_PORT, data);
307 for (t = 0; t < 1000; t++) {
308 if (bus_space_read_2(ess->st, ess->sh, PORT_DSP_DATA) == data)
310 bus_space_write_2(ess->st, ess->sh, PORT_DSP_DATA, data);
313 device_printf(ess->dev, "wp_wrapu() timed out.\n");
317 wp_settimer(struct agg_info *ess, u_int freq)
319 u_int clock = 48000 << 2;
320 u_int prescale = 0, divide = (freq != 0) ? (clock / freq) : ~0;
322 RANGE(divide, 4, 32 << 8);
324 for (; divide > 32 << 1; divide >>= 1)
326 divide = (divide + 1) >> 1;
328 for (; prescale < 7 && divide > 2 && !(divide & 1); divide >>= 1)
331 wp_wrreg(ess, WPREG_TIMER_ENABLE, 0);
332 wp_wrreg(ess, WPREG_TIMER_FREQ,
333 (prescale << WP_TIMER_FREQ_PRESCALE_SHIFT) | (divide - 1));
334 wp_wrreg(ess, WPREG_TIMER_ENABLE, 1);
338 wp_starttimer(struct agg_info *ess)
340 wp_wrreg(ess, WPREG_TIMER_START, 1);
344 wp_stoptimer(struct agg_info *ess)
346 wp_wrreg(ess, WPREG_TIMER_START, 0);
347 bus_space_write_2(ess->st, ess->sh, PORT_INT_STAT, 1);
352 static inline u_int16_t
353 wc_rdreg(struct agg_info *ess, u_int16_t reg)
355 bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_INDEX, reg);
356 return bus_space_read_2(ess->st, ess->sh, PORT_WAVCACHE_DATA);
360 wc_wrreg(struct agg_info *ess, u_int16_t reg, u_int16_t data)
362 bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_INDEX, reg);
363 bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_DATA, data);
366 static inline u_int16_t
367 wc_rdchctl(struct agg_info *ess, int ch)
369 return wc_rdreg(ess, ch << 3);
373 wc_wrchctl(struct agg_info *ess, int ch, u_int16_t data)
375 wc_wrreg(ess, ch << 3, data);
378 /* Power management */
381 agg_power(struct agg_info *ess, int status)
385 data = pci_read_config(ess->dev, CONF_PM_PTR, 1);
386 if (pci_read_config(ess->dev, data, 1) == PPMI_CID)
387 pci_write_config(ess->dev, data + PM_CTRL, status, 1);
391 /* -----------------------------
396 agg_initcodec(struct agg_info* ess)
400 if (bus_space_read_4(ess->st, ess->sh, PORT_RINGBUS_CTRL)
401 & RINGBUS_CTRL_ACLINK_ENABLED) {
402 bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 0);
403 DELAY(104); /* 20.8us * (4 + 1) */
405 /* XXX - 2nd codec should be looked at. */
406 bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL,
407 RINGBUS_CTRL_AC97_SWRESET);
409 bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL,
410 RINGBUS_CTRL_ACLINK_ENABLED);
413 agg_rdcodec(NULL, ess, 0);
414 if (bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
416 bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 0);
419 /* Try cold reset. */
420 device_printf(ess->dev, "will perform cold reset.\n");
421 data = bus_space_read_2(ess->st, ess->sh, PORT_GPIO_DIR);
422 if (pci_read_config(ess->dev, 0x58, 2) & 1)
425 ~bus_space_read_2(ess->st, ess->sh, PORT_GPIO_DATA);
426 bus_space_write_2(ess->st, ess->sh, PORT_GPIO_MASK, 0xff6);
427 bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DIR,
429 bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA, 0x000);
431 bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA, 0x001);
433 bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA, 0x009);
435 bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DIR, data);
436 DELAY(84); /* 20.8us * 4 */
437 bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL,
438 RINGBUS_CTRL_ACLINK_ENABLED);
444 agg_init(struct agg_info* ess)
448 /* Setup PCI config registers. */
450 /* Disable all legacy emulations. */
451 data = pci_read_config(ess->dev, CONF_LEGACY, 2);
452 data |= LEGACY_DISABLED;
453 pci_write_config(ess->dev, CONF_LEGACY, data, 2);
455 /* Disconnect from CHI. (Makes Dell inspiron 7500 work?)
456 * Enable posted write.
457 * Prefer PCI timing rather than that of ISA.
459 data = pci_read_config(ess->dev, CONF_MAESTRO, 4);
460 data |= MAESTRO_CHIBUS | MAESTRO_POSTEDWRITE | MAESTRO_DMA_PCITIMING;
461 data &= ~MAESTRO_SWAP_LR;
462 pci_write_config(ess->dev, CONF_MAESTRO, data, 4);
464 /* Reset direct sound. */
465 bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL,
466 HOSTINT_CTRL_DSOUND_RESET);
467 DELAY(10000); /* XXX - too long? */
468 bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL, 0);
471 /* Enable direct sound interruption and hardware volume control. */
472 bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL,
473 HOSTINT_CTRL_DSOUND_INT_ENABLED | HOSTINT_CTRL_HWVOL_ENABLED);
475 /* Setup Wave Processor. */
477 /* Enable WaveCache, set DMA base address. */
478 wp_wrreg(ess, WPREG_WAVE_ROMRAM,
479 WP_WAVE_VIRTUAL_ENABLED | WP_WAVE_DRAM_ENABLED);
480 bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_CTRL,
481 WAVCACHE_ENABLED | WAVCACHE_WTSIZE_4MB);
483 for (data = WAVCACHE_PCMBAR; data < WAVCACHE_PCMBAR + 4; data++)
484 wc_wrreg(ess, data, ess->baseaddr >> WAVCACHE_BASEADDR_SHIFT);
486 /* Setup Codec/Ringbus. */
488 bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL,
489 RINGBUS_CTRL_RINGBUS_ENABLED | RINGBUS_CTRL_ACLINK_ENABLED);
491 wp_wrreg(ess, WPREG_BASE, 0x8500); /* Parallel I/O */
492 ringbus_setdest(ess, RINGBUS_SRC_ADC,
493 RINGBUS_DEST_STEREO | RINGBUS_DEST_DSOUND_IN);
494 ringbus_setdest(ess, RINGBUS_SRC_DSOUND,
495 RINGBUS_DEST_STEREO | RINGBUS_DEST_DAC);
497 /* Setup ASSP. Needed for Dell Inspiron 7500? */
498 bus_space_write_1(ess->st, ess->sh, PORT_ASSP_CTRL_B, 0x00);
499 bus_space_write_1(ess->st, ess->sh, PORT_ASSP_CTRL_A, 0x03);
500 bus_space_write_1(ess->st, ess->sh, PORT_ASSP_CTRL_C, 0x00);
504 * There seems to be speciality with NEC systems.
506 switch (pci_get_subvendor(ess->dev)
507 | (pci_get_subdevice(ess->dev) << 16)) {
510 /* Matthew Braithwaite <matt@braithwaite.net> reported that
511 * NEC Versa LX doesn't need GPIO operation. */
512 bus_space_write_2(ess->st, ess->sh, PORT_GPIO_MASK, 0x9ff);
513 bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DIR,
514 bus_space_read_2(ess->st, ess->sh, PORT_GPIO_DIR) | 0x600);
515 bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA, 0x200);
520 /* Channel controller. */
523 aggch_start_dac(struct agg_chinfo *ch)
525 bus_addr_t wpwa = APU_USE_SYSMEM | (ch->offset >> 9);
526 u_int size = ch->parent->bufsz >> 1;
527 u_int speed = ch->speed;
528 bus_addr_t offset = ch->offset >> 1;
530 u_int16_t apuch = ch->num << 1;
534 switch (ch->aputype) {
535 case APUTYPE_16BITSTEREO:
541 case APUTYPE_8BITSTEREO:
545 case APUTYPE_8BITLINEAR:
550 dv = (((speed % 48000) << 16) + 24000) / 48000
551 + ((speed / 48000) << 16);
554 wp_wrapu(ch->parent, apuch, APUREG_WAVESPACE, wpwa & 0xff00);
555 wp_wrapu(ch->parent, apuch, APUREG_CURPTR, offset + cp);
556 wp_wrapu(ch->parent, apuch, APUREG_ENDPTR, offset + size);
557 wp_wrapu(ch->parent, apuch, APUREG_LOOPLEN, size);
558 wp_wrapu(ch->parent, apuch, APUREG_AMPLITUDE, 0xe800);
559 wp_wrapu(ch->parent, apuch, APUREG_POSITION, 0x8f00
560 | (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT)
561 | ((PAN_FRONT + pan) << APU_PAN_SHIFT));
562 wp_wrapu(ch->parent, apuch, APUREG_FREQ_LOBYTE, APU_plus6dB
563 | ((dv & 0xff) << APU_FREQ_LOBYTE_SHIFT));
564 wp_wrapu(ch->parent, apuch, APUREG_FREQ_HIWORD, dv >> 8);
566 if (ch->aputype == APUTYPE_16BITSTEREO)
567 wpwa |= APU_STEREO >> 1;
569 } while (pan < 0 && apuch--);
571 wc_wrchctl(ch->parent, apuch, ch->wcreg_tpl);
572 wc_wrchctl(ch->parent, apuch + 1, ch->wcreg_tpl);
574 wp_wrapu(ch->parent, apuch, APUREG_APUTYPE,
575 (ch->aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
576 if (ch->wcreg_tpl & WAVCACHE_CHCTL_STEREO)
577 wp_wrapu(ch->parent, apuch + 1, APUREG_APUTYPE,
578 (ch->aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
582 aggch_stop_dac(struct agg_chinfo *ch)
584 wp_wrapu(ch->parent, (ch->num << 1), APUREG_APUTYPE,
585 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
586 wp_wrapu(ch->parent, (ch->num << 1) + 1, APUREG_APUTYPE,
587 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
591 * Stereo jitter suppressor.
592 * Sometimes playback pointers differ in stereo-paired channels.
593 * Calling this routine within intr fixes the problem.
596 suppress_jitter(struct agg_chinfo *ch)
598 if (ch->wcreg_tpl & WAVCACHE_CHCTL_STEREO) {
599 int cp, diff, halfsize = ch->parent->bufsz >> 2;
601 if (ch->aputype == APUTYPE_16BITSTEREO)
603 cp = wp_rdapu(ch->parent, (ch->num << 1), APUREG_CURPTR);
604 diff = wp_rdapu(ch->parent, (ch->num << 1) + 1, APUREG_CURPTR);
606 if (diff >> 1 && diff > -halfsize && diff < halfsize)
607 bus_space_write_2(ch->parent->st, ch->parent->sh,
613 calc_timer_freq(struct agg_chinfo *ch)
617 if (ch->aputype == APUTYPE_16BITSTEREO)
619 if (ch->aputype == APUTYPE_8BITLINEAR)
622 return (ch->speed * ss) / ch->blocksize;
626 set_timer(struct agg_info *ess)
631 for (i = 0; i < ess->playchns; i++)
632 if ((ess->active & (1 << i)) &&
633 (freq < calc_timer_freq(ess->pch + i)))
634 freq = calc_timer_freq(ess->pch + i);
636 wp_settimer(ess, freq);
640 /* -----------------------------
645 aggch_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
647 struct agg_info *ess = devinfo;
648 struct agg_chinfo *ch;
652 ch = (dir == PCMDIR_PLAY)? ess->pch + ess->playchns : &ess->rch;
657 ch->num = ess->playchns;
660 p = dma_malloc(ess, ess->bufsz, &physaddr);
663 sndbuf_setup(b, p, ess->bufsz);
665 ch->offset = physaddr - ess->baseaddr;
666 if (physaddr < ess->baseaddr || ch->offset > WPWA_MAXADDR) {
667 device_printf(ess->dev,
668 "offset %#llx exceeds limit. ", (long long)ch->offset);
669 dma_free(ess, sndbuf_getbuf(b));
673 ch->wcreg_tpl = (physaddr - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
675 if (dir == PCMDIR_PLAY) {
678 device_printf(ess->dev, "pch[%d].offset = %#llx\n", ch->num, (long long)ch->offset);
679 } else if (bootverbose)
680 device_printf(ess->dev, "rch.offset = %#llx\n", (long long)ch->offset);
686 aggch_free(kobj_t obj, void *data)
688 struct agg_chinfo *ch = data;
689 struct agg_info *ess = ch->parent;
691 /* free up buffer - called after channel stopped */
692 dma_free(ess, sndbuf_getbuf(ch->buffer));
699 aggch_setplayformat(kobj_t obj, void *data, u_int32_t format)
701 struct agg_chinfo *ch = data;
703 u_int16_t aputype = APUTYPE_16BITLINEAR;
705 wcreg_tpl = ch->wcreg_tpl & WAVCACHE_CHCTL_ADDRTAG_MASK;
707 if (format & AFMT_STEREO) {
708 wcreg_tpl |= WAVCACHE_CHCTL_STEREO;
711 if (format & AFMT_U8 || format & AFMT_S8) {
713 if (format & AFMT_U8)
714 wcreg_tpl |= WAVCACHE_CHCTL_U8;
716 if (format & AFMT_BIGENDIAN || format & AFMT_U16_LE) {
717 format &= ~AFMT_BIGENDIAN & ~AFMT_U16_LE;
718 format |= AFMT_S16_LE;
720 ch->wcreg_tpl = wcreg_tpl;
721 ch->aputype = aputype;
726 aggch_setspeed(kobj_t obj, void *data, u_int32_t speed)
728 struct agg_chinfo *ch = data;
735 aggch_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
737 return ((struct agg_chinfo*)data)->blocksize = blocksize;
741 aggch_trigger(kobj_t obj, void *data, int go)
743 struct agg_chinfo *ch = data;
746 case PCMTRIG_EMLDMAWR:
749 ch->parent->active |= (1 << ch->num);
750 if (ch->dir == PCMDIR_PLAY)
752 #if 0 /* XXX - RECORDING */
759 ch->parent->active &= ~(1 << ch->num);
760 if (ch->dir == PCMDIR_PLAY)
762 #if 0 /* XXX - RECORDING */
769 if (ch->parent->active) {
770 set_timer(ch->parent);
771 wp_starttimer(ch->parent);
773 wp_stoptimer(ch->parent);
779 aggch_getplayptr(kobj_t obj, void *data)
781 struct agg_chinfo *ch = data;
784 cp = wp_rdapu(ch->parent, (ch->num << 1), APUREG_CURPTR);
785 if (ch->aputype == APUTYPE_16BITSTEREO)
786 cp = (0xffff << 2) & ((cp << 2) - ch->offset);
788 cp = (0xffff << 1) & ((cp << 1) - ch->offset);
793 static struct pcmchan_caps *
794 aggch_getcaps(kobj_t obj, void *data)
796 static u_int32_t playfmt[] = {
798 AFMT_STEREO | AFMT_U8,
800 AFMT_STEREO | AFMT_S8,
802 AFMT_STEREO | AFMT_S16_LE,
805 static struct pcmchan_caps playcaps = {2000, 96000, playfmt, 0};
807 static u_int32_t recfmt[] = {
809 AFMT_STEREO | AFMT_S8,
811 AFMT_STEREO | AFMT_S16_LE,
814 static struct pcmchan_caps reccaps = {4000, 48000, recfmt, 0};
816 return (((struct agg_chinfo*)data)->dir == PCMDIR_PLAY)?
817 &playcaps : &reccaps;
820 static kobj_method_t aggch_methods[] = {
821 KOBJMETHOD(channel_init, aggch_init),
822 KOBJMETHOD(channel_free, aggch_free),
823 KOBJMETHOD(channel_setformat, aggch_setplayformat),
824 KOBJMETHOD(channel_setspeed, aggch_setspeed),
825 KOBJMETHOD(channel_setblocksize, aggch_setblocksize),
826 KOBJMETHOD(channel_trigger, aggch_trigger),
827 KOBJMETHOD(channel_getptr, aggch_getplayptr),
828 KOBJMETHOD(channel_getcaps, aggch_getcaps),
831 CHANNEL_DECLARE(aggch);
833 /* -----------------------------
840 struct agg_info* ess = sc;
844 status = bus_space_read_1(ess->st, ess->sh, PORT_HOSTINT_STAT);
848 /* Acknowledge all. */
849 bus_space_write_2(ess->st, ess->sh, PORT_INT_STAT, 1);
850 bus_space_write_1(ess->st, ess->sh, PORT_HOSTINT_STAT, 0xff);
852 if (status & HOSTINT_STAT_HWVOL) {
855 event = bus_space_read_1(ess->st, ess->sh, PORT_HWVOL_MASTER);
858 mixer_hwvol_mute(ess->dev);
861 mixer_hwvol_step(ess->dev, 1, 1);
864 mixer_hwvol_step(ess->dev, -1, -1);
869 device_printf(ess->dev, "%s: unknown HWVOL event 0x%x\n",
870 device_get_nameunit(ess->dev), event);
872 bus_space_write_1(ess->st, ess->sh, PORT_HWVOL_MASTER,
876 for (i = 0; i < ess->playchns; i++)
877 if (ess->active & (1 << i)) {
878 suppress_jitter(ess->pch + i);
879 chn_intr(ess->pch[i].channel);
881 #if 0 /* XXX - RECORDING */
882 if (ess->active & (1 << i))
883 chn_intr(ess->rch.channel);
888 setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error)
890 bus_addr_t *phys = arg;
892 *phys = error? 0 : segs->ds_addr;
895 printf("setmap (%lx, %lx), nseg=%d, error=%d\n",
896 (unsigned long)segs->ds_addr, (unsigned long)segs->ds_len,
902 dma_malloc(struct agg_info *sc, u_int32_t sz, bus_addr_t *phys)
907 if (bus_dmamem_alloc(sc->parent_dmat, &buf, BUS_DMA_NOWAIT, &map))
909 if (bus_dmamap_load(sc->parent_dmat, map, buf, sz, setmap, phys, 0)
911 bus_dmamem_free(sc->parent_dmat, buf, map);
918 dma_free(struct agg_info *sc, void *buf)
920 bus_dmamem_free(sc->parent_dmat, buf, NULL);
924 agg_probe(device_t dev)
928 switch (pci_get_devid(dev)) {
929 case MAESTRO_1_PCI_ID:
930 s = "ESS Technology Maestro-1";
933 case MAESTRO_2_PCI_ID:
934 s = "ESS Technology Maestro-2";
937 case MAESTRO_2E_PCI_ID:
938 s = "ESS Technology Maestro-2E";
942 if (s != NULL && pci_get_class(dev) == PCIC_MULTIMEDIA) {
943 device_set_desc(dev, s);
950 agg_attach(device_t dev)
952 struct agg_info *ess = NULL;
955 int regid = PCIR_MAPS;
956 struct resource *reg = NULL;
957 struct ac97_info *codec = NULL;
959 struct resource *irq = NULL;
961 char status[SND_STATUSLEN];
963 if ((ess = malloc(sizeof *ess, M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) {
964 device_printf(dev, "cannot allocate softc\n");
969 ess->bufsz = pcm_getbuffersize(dev, 4096, AGG_DEFAULT_BUFSZ, 65536);
971 if (bus_dma_tag_create(/*parent*/NULL,
972 /*alignment*/1 << WAVCACHE_BASEADDR_SHIFT,
973 /*boundary*/WPWA_MAXADDR + 1,
974 /*lowaddr*/MAESTRO_MAXADDR, /*highaddr*/BUS_SPACE_MAXADDR,
975 /*filter*/NULL, /*filterarg*/NULL,
976 /*maxsize*/ess->bufsz, /*nsegments*/1, /*maxsegz*/0x3ffff,
977 /*flags*/0, &ess->parent_dmat) != 0) {
978 device_printf(dev, "unable to create dma tag\n");
982 ess->stat = dma_malloc(ess, ess->bufsz, &ess->baseaddr);
983 if (ess->stat == NULL) {
984 device_printf(dev, "cannot allocate status buffer\n");
988 device_printf(dev, "Maestro DMA base: %#llx\n",
989 (long long)ess->baseaddr);
991 agg_power(ess, PPMI_D0);
994 data = pci_read_config(dev, PCIR_COMMAND, 2);
995 data |= (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN);
996 pci_write_config(dev, PCIR_COMMAND, data, 2);
997 data = pci_read_config(dev, PCIR_COMMAND, 2);
999 if (data & PCIM_CMD_PORTEN) {
1000 reg = bus_alloc_resource(dev, SYS_RES_IOPORT, ®id,
1001 0, BUS_SPACE_UNRESTRICTED, 256, RF_ACTIVE);
1005 ess->st = rman_get_bustag(reg);
1006 ess->sh = rman_get_bushandle(reg);
1011 device_printf(dev, "unable to map register space\n");
1016 if (agg_rdcodec(NULL, ess, 0) == 0x80) {
1017 device_printf(dev, "PT101 codec detected!\n");
1020 codec = AC97_CREATE(dev, ess, agg_ac97);
1023 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1)
1027 irq = bus_alloc_resource(dev, SYS_RES_IRQ, &irqid,
1028 0, BUS_SPACE_UNRESTRICTED, 1, RF_ACTIVE | RF_SHAREABLE);
1029 if (irq == NULL || snd_setup_intr(dev, irq, 0, agg_intr, ess, &ih, NULL)) {
1030 device_printf(dev, "unable to map interrupt\n");
1037 snprintf(status, SND_STATUSLEN, "at I/O port 0x%lx irq %ld",
1038 rman_get_start(reg), rman_get_start(irq));
1040 if (pcm_register(dev, ess, AGG_MAXPLAYCH, 1))
1043 mixer_hwvol_init(dev);
1044 for (data = 0; data < AGG_MAXPLAYCH; data++)
1045 pcm_addchan(dev, PCMDIR_PLAY, &aggch_class, ess);
1046 #if 0 /* XXX - RECORDING */
1047 pcm_addchan(dev, PCMDIR_REC, &aggrch_class, ess);
1049 pcm_setstatus(dev, status);
1055 ac97_destroy(codec);
1057 bus_teardown_intr(dev, irq, ih);
1059 bus_release_resource(dev, SYS_RES_IRQ, irqid, irq);
1061 bus_release_resource(dev, SYS_RES_IOPORT, regid, reg);
1063 agg_power(ess, PPMI_D3);
1064 if (ess->stat != NULL)
1065 dma_free(ess, ess->stat);
1066 if (ess->parent_dmat != NULL)
1067 bus_dma_tag_destroy(ess->parent_dmat);
1068 free(ess, M_DEVBUF);
1075 agg_detach(device_t dev)
1077 struct agg_info *ess = pcm_getdevinfo(dev);
1080 r = pcm_unregister(dev);
1084 ess = pcm_getdevinfo(dev);
1085 dma_free(ess, ess->stat);
1087 /* Power down everything except clock and vref. */
1088 agg_wrcodec(NULL, ess, AC97_REG_POWER, 0xd700);
1090 bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 0);
1091 agg_power(ess, PPMI_D3);
1093 bus_teardown_intr(dev, ess->irq, ess->ih);
1094 bus_release_resource(dev, SYS_RES_IRQ, ess->irqid, ess->irq);
1095 bus_release_resource(dev, SYS_RES_IOPORT, ess->regid, ess->reg);
1096 bus_dma_tag_destroy(ess->parent_dmat);
1097 free(ess, M_DEVBUF);
1102 agg_suspend(device_t dev)
1104 struct agg_info *ess = pcm_getdevinfo(dev);
1109 bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL, 0);
1111 for (i = 0; i < ess->playchns; i++)
1112 aggch_stop_dac(ess->pch + i);
1114 #if 0 /* XXX - RECORDING */
1115 aggch_stop_adc(&ess->rch);
1118 /* Power down everything except clock. */
1119 agg_wrcodec(NULL, ess, AC97_REG_POWER, 0xdf00);
1121 bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 0);
1123 agg_power(ess, PPMI_D3);
1129 agg_resume(device_t dev)
1132 struct agg_info *ess = pcm_getdevinfo(dev);
1134 agg_power(ess, PPMI_D0);
1137 if (mixer_reinit(dev)) {
1138 device_printf(dev, "unable to reinitialize the mixer\n");
1143 for (i = 0; i < ess->playchns; i++)
1144 if (ess->active & (1 << i))
1145 aggch_start_dac(ess->pch + i);
1146 #if 0 /* XXX - RECORDING */
1147 if (ess->active & (1 << i))
1148 aggch_start_adc(&ess->rch);
1159 agg_shutdown(device_t dev)
1161 struct agg_info *ess = pcm_getdevinfo(dev);
1165 bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL, 0);
1167 for (i = 0; i < ess->playchns; i++)
1168 aggch_stop_dac(ess->pch + i);
1170 #if 0 /* XXX - RECORDING */
1171 aggch_stop_adc(&ess->rch);
1177 static device_method_t agg_methods[] = {
1178 DEVMETHOD(device_probe, agg_probe),
1179 DEVMETHOD(device_attach, agg_attach),
1180 DEVMETHOD(device_detach, agg_detach),
1181 DEVMETHOD(device_suspend, agg_suspend),
1182 DEVMETHOD(device_resume, agg_resume),
1183 DEVMETHOD(device_shutdown, agg_shutdown),
1188 static driver_t agg_driver = {
1194 DRIVER_MODULE(snd_maestro, pci, agg_driver, pcm_devclass, 0, 0);
1195 MODULE_DEPEND(snd_maestro, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER);
1196 MODULE_VERSION(snd_maestro, 1);