2 * _NVRM_COPYRIGHT_BEGIN_
4 * Copyright 2006 by NVIDIA Corporation. All rights reserved. All
5 * information contained herein is proprietary and confidential to NVIDIA
6 * Corporation. Any use, reproduction, or disclosure without the written
7 * permission of NVIDIA Corporation is prohibited.
15 * These are defined here and used throughout resman.
16 * Any given registry name (windows registry leaf names) are mapped to
17 * variables with the following naming convention: NVreg_NAME, where NAME
18 * is the registry name with space converted to underscores.
23 * Steps to be followed for the addition of a new registry key
25 * Step 1: document and define registry key
32 * We've had problems with some Via chipsets in 4x mode, we need force
33 * them back down to 2x mode. If you'd like to experiment with retaining
34 * 4x mode, you may try setting this value to 1 If that hangs the system,
35 * you're stuck with 2x mode; there's nothing we can do about it.
39 * 0: disable AGP 4x on Via chipsets (default)
40 * 1: enable AGP 4x on Via chipsets
42 * #define __NV_ENABLE_VIA_4X EnableVia4x
43 * #define NV_REG_ENABLE_VIA_4X NV_REG_STRING(__NV_ENABLE_VIA_4X)
45 * Step 2: registry key parameter declarations
48 * NV_DEFINE_REG_ENTRY(__NV_ENABLE_VIA_4X, 0);
50 * Step 3: registry database definition
53 * nv_parm_t nv_parms[] = {
54 * NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_VIA_4X),
66 * use NV_REG_STRING to stringify a registry key when using that registry key
69 #define __NV_REG_STRING(regkey) #regkey
70 #define NV_REG_STRING(regkey) __NV_REG_STRING(regkey)
73 * use NV_DEFINE_REG_ENTRY and NV_DEFINE_PARAMS_TABLE_ENTRY to simplify definition
74 * of registry keys in the kernel module source code.
77 #define __NV_REG_VAR(regkey) NVreg_##regkey
79 #if defined(NV_MODULE_PARAMETER)
80 #define NV_DEFINE_REG_ENTRY(regkey, default_value) \
81 static NvU32 __NV_REG_VAR(regkey) = (default_value); \
82 NV_MODULE_PARAMETER(__NV_REG_VAR(regkey))
84 #define NV_DEFINE_REG_ENTRY(regkey, default_value) \
85 static NvU32 __NV_REG_VAR(regkey) = (default_value)
88 #if defined(NV_MODULE_STRING_PARAMETER)
89 #define NV_DEFINE_REG_STRING_ENTRY(regkey, default_value) \
90 char *__NV_REG_VAR(regkey) = (default_value); \
91 NV_MODULE_STRING_PARAMETER(__NV_REG_VAR(regkey))
93 #define NV_DEFINE_REG_STRING_ENTRY(regkey, default_value) \
94 char *__NV_REG_VAR(regkey) = (default_value)
97 #define NV_DEFINE_PARAMS_TABLE_ENTRY(regkey) \
98 { "NVreg", NV_REG_STRING(regkey), &__NV_REG_VAR(regkey) }
102 *----------------- registry key definitions--------------------------
106 * Option: EnableVia4x
110 * We've had problems with some Via chipsets in 4x mode, we need force
111 * them back down to 2x mode. If you'd like to experiment with retaining
112 * 4x mode, you may try setting this value to 1 If that hangs the system,
113 * you're stuck with 2x mode; there's nothing we can do about it.
117 * 0: disable AGP 4x on Via chipsets (default)
118 * 1: enable AGP 4x on Via chipsets
121 #define __NV_ENABLE_VIA_4X EnableVia4x
122 #define NV_REG_ENABLE_VIA_4X NV_REG_STRING(__NV_ENABLE_VIA_4X)
125 * Option: EnableALiAGP
129 * Some ALi chipsets (ALi1541, ALi1647) are known to cause severe system
130 * stability problems with AGP enabled. To avoid lockups, we disable AGP
131 * on systems with these chipsets by default. It appears that updating the
132 * system BIOS and using recent versions of the kernel AGP Gart driver can
133 * make such systems much more stable. If you own a system with one of the
134 * aforementioned chipsets and had it working reasonably well previously,
135 * or if you want to experiment with BIOS and AGPGART revisions, you can
136 * re-enable AGP support by setting this option to 1.
140 * 0: disable AGP on Ali1541 and ALi1647 (default)
141 * 1: enable AGP on Ali1541 and ALi1647
144 #define __NV_ENABLE_ALI_AGP EnableALiAGP
145 #define NV_REG_ENABLE_ALI_AGP NV_REG_STRING(__NV_ENABLE_ALI_AGP)
152 * Normally, the driver will compare speed modes of the chipset & card,
153 * picking the highest common rate. This key forces a maximum limit, to
154 * limit the driver to lower speeds. The driver will not attempt a speed
155 * beyond what the chipset and card claim they are capable of.
157 * Make sure you really know what you're doing before you enable this
158 * override. By default, AGP drivers will enable the fastest AGP rate
159 * your card and motherboard chipset are capable of. Then, in some cases,
160 * our driver will force this rate down to work around bugs in both our
161 * chipsets, and motherboard chipsets. Using this variable will override
162 * our bug fixes. This may be desirable in some cases, but not most.
164 * This is completely unsupported!
168 * This option expects a bitmask (15 = 8 | 4 | 2 | 1, etc.)
170 * Note that on AGP 3.x chipsets, the only supported AGP rates are
171 * AGP 8x and AGP 4x (if set in ReqAGPRate, AGP 2x and 1x are
172 * ignored by the driver).
174 * This option is disabled by default, see below for information on how
178 #define __NV_REQ_AGP_RATE ReqAGPRate
179 #define NV_REG_REQ_AGP_RATE NV_REG_STRING(__NV_REQ_AGP_RATE)
186 * This options controls which AGP GART driver is used when no explicit
187 * request is made to change the default (X server).
191 * 0 = disable AGP support
192 * 1 = use NVIDIA's builtin driver (if possible)
193 * 2 = use the kernel's AGPGART driver (if possible)
194 * 3 = use any available driver (try 1, then 2)
196 * Please note that NVIDIA's internal AGP GART driver will not be used
197 * if AGPGART was either statically linked into your kernel or built as
198 * a kernel module and loaded before the NVIDIA kernel module.
201 #define __NV_AGP NvAGP
202 #define NV_REG_NV_AGP NV_REG_STRING(__NV_AGP)
205 * Option: EnableAGPSBA
209 * For stability reasons, the driver will not Side Band Addressing even if
210 * both the host chipset and the AGP card support it. You may override this
211 * behaviour with the following registry key.
213 * This is completely unsupported!
217 * 0 = disable Side Band Addressing (default on x86, see below)
218 * 1 = enable Side Band Addressing (if supported)
222 * The default on x86 is to disable AGP side band addressing; if you want
223 * to turn it on, change the registry key below.
226 #define __NV_ENABLE_AGPSBA EnableAGPSBA
227 #define NV_REG_ENABLE_AGPSBA NV_REG_STRING(__NV_ENABLE_AGPSBA)
230 * Option: EnableAGPFW
234 * Similar to Side Band Addressing, Fast Writes are disabled by default. If
235 * you wish to enable them on systems that support them, you can do so with
236 * this registry key. Please note that this may render your system unstable
237 * with many AGP chipsets.
239 * This is completely unsupported!
243 * 0 = disable Fast Writes (default)
244 * 1 = enable Fast Writes (if supported)
246 * This option is disabled by default, see below for information on how
250 #define __NV_ENABLE_AGPFW EnableAGPFW
251 #define NV_REG_ENABLE_AGPFW NV_REG_STRING(__NV_ENABLE_AGPFW)
258 * The Mobile registry key should only be needed on mobile systems if
259 * SoftEDIDs is disabled (see above), in which case the mobile value
260 * will be used to lookup the correct EDID for the mobile LCD.
264 * ~0 = auto detect the correct value (default)
266 * 2 = non-Compal Toshiba
267 * 3 = all other notebooks
271 * Make sure to specify the correct value for your notebook.
274 #define __NV_MOBILE Mobile
275 #define NV_REG_MOBILE NV_REG_STRING(__NV_MOBILE)
278 * Option: ModifyDeviceFiles
282 * When this option is enabled, the NVIDIA driver will verify the validity
283 * of the NVIDIA device files in /dev and attempt to dynamically modify
284 * and/or (re-)create them, if necessary. If you don't wish for the NVIDIA
285 * driver to touch the device files, you can use this registry key.
288 * 0 = disable dynamic device file management
289 * 1 = enable dynamic device file management
292 #define __NV_MODIFY_DEVICE_FILES ModifyDeviceFiles
293 #define NV_REG_MODIFY_DEVICE_FILES NV_REG_STRING(__NV_MODIFY_DEVICE_FILES)
296 * Option: DeviceFileUID
300 * This registry key specifies the UID assigned to the NVIDIA device files
301 * created and/or modified by the NVIDIA driver when dynamic device file
302 * management is enabled.
304 * The default UID is 0 ('root').
307 #define __NV_DEVICE_FILE_UID DeviceFileUID
308 #define NV_REG_DEVICE_FILE_UID NV_REG_STRING(__NV_DEVICE_FILE_UID)
311 * Option: DeviceFileGID
315 * This registry key specifies the GID assigned to the NVIDIA device files
316 * created and/or modified by the NVIDIA driver when dynamic device file
317 * management is enabled.
319 * The default GID is 0 ('root').
322 #define __NV_DEVICE_FILE_GID DeviceFileGID
323 #define NV_REG_DEVICE_FILE_GID NV_REG_STRING(__NV_DEVICE_FILE_GID)
326 * Option: DeviceFileMode
330 * This registry key specifies the device file mode assigned to the NVIDIA
331 * device files created and/or modified by the NVIDIA driver when dynamic
332 * device file management is enabled.
334 * The default mode is 0666 (octal, rw-rw-rw-).
337 #define __NV_DEVICE_FILE_MODE DeviceFileMode
338 #define NV_REG_DEVICE_FILE_MODE NV_REG_STRING(__NV_DEVICE_FILE_MODE)
341 * Option: ResmanDebugLevel
346 #define __NV_RESMAN_DEBUG_LEVEL ResmanDebugLevel
347 #define NV_REG_RESMAN_DEBUG_LEVEL NV_REG_STRING(__NV_RESMAN_DEBUG_LEVEL)
355 #define __NV_RM_LOGON_RC RmLogonRC
356 #define NV_REG_RM_LOGON_RC NV_REG_STRING(__NV_RM_LOGON_RC)
363 * This registry key specifies the maximum amount of memory allowed to
364 * be remapped through the IOMMU/SWIOTLB. On 64-bit platforms, getting
365 * 32-bit physical addresses is difficult and requires remapping 64-bit
366 * physical addresses through either the IOMMU or SWIOTLB (depending on
367 * the CPU). These apertures are of limited size (usually default to 64
368 * MegaBytes). Exhausting these apertures can either immediately panic
369 * the kernel or lead to failures in other kernel subsystems, depending
370 * on the running kernel's behavior.
372 * The NVIDIA driver now attempts to avoid exhausting the these pools of
373 * memory to avoid these stability problems. Unfortunately, there is no
374 * way to determine the size of these pools at runtime, so the NVIDIA
375 * driver has to hard code this limit.
377 * This registry key allows the end user to manually tweak this value if
378 * necessary. Specifically, if the IOMMU or SWIOTLB aperture is larger
379 * than 64 MegaBytes, the end user can adjust this value to take advantage
380 * of the larger pool.
382 * Note that the default value of this limit is 60 MegaBytes, which leaves
383 * 4 MegaBytes available for the rest of the system. If the end user
384 * adjusts this value, it is recommended to leave 4 MegaBytes as well.
385 * For example, if the end user wants to adjust this value to account for
386 * a 128 MegaByte pool, it is suggested to set this value to 124 MegaBytes.
390 #define __NV_REMAP_LIMIT RemapLimit
391 #define NV_REG_REMAP_LIMIT NV_REG_STRING(__NV_REMAP_LIMIT)
394 * Option: UpdateMemoryTypes
398 * Many kernels have broken implementations of the change_page_attr()
399 * kernel interface that may cause cache aliasing problems. Linux/x86-64
400 * kernels between 2.6.0 and 2.6.10 may prompt kernel BUG()s due to
401 * improper accounting in the interface's large page management code, for
402 * example. For this reason, the NVIDIA Linux driver is very careful about
403 * not using the change_page_attr() kernel interface on these kernels.
405 * Due to the serious nature of the problems that can arise from bugs in
406 * the change_page_attr(), set_pages_{uc,wb}() and other kernel interfaces
407 * used to modify memory types, the NVIDIA driver implements a manual
408 * registry key override to allow forcibly enabling or disabling use of
413 * ~0 = use the NVIDIA driver's default logic (default)
414 * 0 = enable use of change_page_attr(), etc.
415 * 1 = disable use of change_page_attr(), etc.
417 * By default, the NVIDIA driver will attempt to auto-detect if it can
418 * safely use the change_page_attr() and other kernel interfaces to modify
419 * the memory types of kernel mappings.
422 #define __NV_UPDATE_MEMORY_TYPES UpdateMemoryTypes
423 #define NV_REG_UPDATE_MEMORY_TYPES NV_REG_STRING(__NV_UPDATE_MEMORY_TYPES)
426 * Option: RegistryDwords
430 * This option accepts a semicolon-separated list of key=value pairs. Each
431 * key name is checked agains the table of static options; if a match is
432 * found, the static option value is overridden, but invalid options remain
433 * invalid. Pairs that do not match an entry in the static option table
434 * are passed on to the RM directly.
438 * NVreg_RegistryDwords="<key=value>;<key=value>;..."
441 #define __NV_REGISTRY_DWORDS RegistryDwords
442 #define NV_REG_REGISTRY_DWORDS NV_REG_STRING(__NV_REGISTRY_DWORDS)
449 * Use Video BIOS int10 code
454 #define __NV_USE_VBIOS UseVBios
455 #define NV_REG_USE_VBIOS NV_REG_STRING(__NV_USE_VBIOS)
458 * Option: RMEdgeIntrCheck
462 * Enable/disable check for edge-triggered interrupts.
463 * Please see the common problems section of the readme for more
464 * details on edge-triggered interrupt problems.
467 * 1 - enable edge-triggered interrupt check (default)
468 * 0 - disable edge-triggered interrupt check
471 #define __NV_RM_EDGE_INTR_CHECK RMEdgeIntrCheck
472 #define NV_REG_RM_EDGE_INTR_CHECK NV_REG_STRING(__NV_RM_EDGE_INTR_CHECK)
475 * Option: UsePageAttributeTable
479 * Enable/disable use of the page attribute table (PAT) available in
480 * modern x86/x86-64 processors to set the effective memory type of memory
481 * mappings to write-combining (WC). If disabled, the driver will fall
482 * back to using MTRRs, if possible.
484 * If enabled, an x86 processor with PAT support is present and the host
485 * system's Linux kernel did not configure one of the PAT entries to
486 * indicate the WC memory type, the driver will change the second entry in
487 * the PAT from its default (write-through (WT)) to WC at module load
488 * time. If the kernel did update one of the PAT entries, the driver will
489 * not modify the PAT.
491 * In both cases, the driver will honor attempts to map memory with the WC
492 * memory type by selecting the appropriate PAT entry using the correct
497 * ~0 = use the NVIDIA driver's default logic (default)
498 * 1 = enable use of the PAT for WC mappings.
499 * 0 = disable use of the PAT for WC mappings.
502 #define __NV_USE_PAGE_ATTRIBUTE_TABLE UsePageAttributeTable
503 #define NV_USE_PAGE_ATTRIBUTE_TABLE NV_REG_STRING(__NV_USE_PAGE_ATTRIBUTE_TABLE)
510 * When this option is enabled and the host kernel supports the MSI feature,
511 * the NVIDIA driver will enable the PCI-E MSI capability of GPUs with the
512 * support for this feature instead of using PCI-E wired interrupt.
516 * 0 = disable MSI interrupt (default)
517 * 1 = enable MSI interrupt
521 #define __NV_ENABLE_MSI EnableMSI
522 #define NV_REG_ENABLE_MSI NV_REG_STRING(__NV_ENABLE_MSI)
525 * Option: MapRegistersEarly
529 * When this option is enabled, the NVIDIA kernel module will attempt to
530 * map the device registers of NVIDIA GPUs at probe(), rather than at
531 * open() time. This is useful for debugging purposes, only.
535 * 0 = do not map GPU registers early (default)
536 * 1 = map GPU registers early
539 #define __NV_MAP_REGISTERS_EARLY MapRegistersEarly
540 #define NV_REG_MAP_REGISTERS_EARLY NV_REG_STRING(__NV_MAP_REGISTERS_EARLY)
542 #if defined(NV_DEFINE_REGISTRY_KEY_TABLE)
545 *---------registry key parameter declarations--------------
548 NV_DEFINE_REG_ENTRY(__NV_ENABLE_VIA_4X, 0);
549 NV_DEFINE_REG_ENTRY(__NV_ENABLE_ALI_AGP, 0);
550 NV_DEFINE_REG_ENTRY(__NV_REQ_AGP_RATE, 15);
551 NV_DEFINE_REG_ENTRY(__NV_ENABLE_AGPSBA, 0);
552 NV_DEFINE_REG_ENTRY(__NV_ENABLE_AGPFW, 0);
553 NV_DEFINE_REG_ENTRY(__NV_MOBILE, ~0);
554 NV_DEFINE_REG_ENTRY(__NV_RESMAN_DEBUG_LEVEL, ~0);
555 NV_DEFINE_REG_ENTRY(__NV_RM_LOGON_RC, 1);
556 NV_DEFINE_REG_ENTRY(__NV_MODIFY_DEVICE_FILES, 1);
557 NV_DEFINE_REG_ENTRY(__NV_DEVICE_FILE_UID, 0);
558 NV_DEFINE_REG_ENTRY(__NV_DEVICE_FILE_GID, 0);
559 NV_DEFINE_REG_ENTRY(__NV_DEVICE_FILE_MODE, 0666);
560 NV_DEFINE_REG_ENTRY(__NV_REMAP_LIMIT, 0);
561 NV_DEFINE_REG_ENTRY(__NV_UPDATE_MEMORY_TYPES, ~0);
562 NV_DEFINE_REG_ENTRY(__NV_USE_VBIOS, 1);
563 NV_DEFINE_REG_ENTRY(__NV_RM_EDGE_INTR_CHECK, 1);
564 NV_DEFINE_REG_ENTRY(__NV_USE_PAGE_ATTRIBUTE_TABLE, ~0);
565 NV_DEFINE_REG_ENTRY(__NV_ENABLE_MSI, 0);
566 NV_DEFINE_REG_ENTRY(__NV_MAP_REGISTERS_EARLY, 0);
568 #if defined(NV_LINUX)
569 NV_DEFINE_REG_STRING_ENTRY(__NV_REGISTRY_DWORDS, NULL);
572 #if (defined(NV_BSD) && defined(NV_SUPPORT_OS_AGP)) || defined(NV_LINUX)
573 #define NV_DEFAULT_NV_AGP_VALUE 3
575 #define NV_DEFAULT_NV_AGP_VALUE 1
578 NV_DEFINE_REG_ENTRY(__NV_AGP, NV_DEFAULT_NV_AGP_VALUE);
582 *----------------registry database definition----------------------
586 * You can enable any of the registry options disabled by default by
587 * editing their respective entries in the table below. The last field
588 * determines if the option is considered valid - in order for the
589 * changes to take effect, you need to recompile and reload the NVIDIA
594 nv_parm_t nv_parms[] = {
595 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_VIA_4X),
596 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_ALI_AGP),
597 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_AGP),
598 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_REQ_AGP_RATE),
599 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_AGPSBA),
600 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_AGPFW),
601 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_MOBILE),
602 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_RESMAN_DEBUG_LEVEL),
603 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_RM_LOGON_RC),
604 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_MODIFY_DEVICE_FILES),
605 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DEVICE_FILE_UID),
606 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DEVICE_FILE_GID),
607 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DEVICE_FILE_MODE),
608 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_REMAP_LIMIT),
609 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_UPDATE_MEMORY_TYPES),
610 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_USE_VBIOS),
611 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_RM_EDGE_INTR_CHECK),
612 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_USE_PAGE_ATTRIBUTE_TABLE),
613 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_MSI),
614 NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_MAP_REGISTERS_EARLY),
619 #endif /* NV_DEFINE_REGISTRY_KEY_TABLE */
622 #endif /* _RM_REG_H_ */