2 * Copyright (c) 2003 Peter Wemm.
3 * Copyright (c) 1993 The Regents of the University of California.
4 * Copyright (c) 2008 The DragonFly Project.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by the University of
18 * California, Berkeley and its contributors.
19 * 4. Neither the name of the University nor the names of its contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * $FreeBSD: src/sys/amd64/include/cpufunc.h,v 1.139 2004/01/28 23:53:04 peter Exp $
36 * $DragonFly: src/sys/cpu/amd64/include/cpufunc.h,v 1.3 2008/08/29 17:07:06 dillon Exp $
40 * Functions to provide access to special i386 instructions.
41 * This in included in sys/systm.h, and that file should be
42 * used in preference to this.
45 #ifndef _CPU_CPUFUNC_H_
46 #define _CPU_CPUFUNC_H_
48 #include <sys/cdefs.h>
49 #include <machine/psl.h>
52 struct region_descriptor;
55 #define readb(va) (*(volatile u_int8_t *) (va))
56 #define readw(va) (*(volatile u_int16_t *) (va))
57 #define readl(va) (*(volatile u_int32_t *) (va))
58 #define readq(va) (*(volatile u_int64_t *) (va))
60 #define writeb(va, d) (*(volatile u_int8_t *) (va) = (d))
61 #define writew(va, d) (*(volatile u_int16_t *) (va) = (d))
62 #define writel(va, d) (*(volatile u_int32_t *) (va) = (d))
63 #define writeq(va, d) (*(volatile u_int64_t *) (va) = (d))
68 #include <machine/lock.h> /* XXX */
74 __asm __volatile("int $3");
80 __asm __volatile("pause");
88 __asm __volatile("bsfl %1,%0" : "=r" (result) : "rm" (mask));
92 static __inline u_long
97 __asm __volatile("bsfq %1,%0" : "=r" (result) : "rm" (mask));
101 static __inline u_int
106 __asm __volatile("bsrl %1,%0" : "=r" (result) : "rm" (mask));
110 static __inline u_long
115 __asm __volatile("bsrq %1,%0" : "=r" (result) : "rm" (mask));
120 cpu_disable_intr(void)
122 __asm __volatile("cli" : : : "memory");
126 do_cpuid(u_int ax, u_int *p)
128 __asm __volatile("cpuid"
129 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
134 cpuid_count(u_int ax, u_int cx, u_int *p)
136 __asm __volatile("cpuid"
137 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
138 : "0" (ax), "c" (cx));
142 cpu_enable_intr(void)
144 __asm __volatile("sti");
148 * Cpu and compiler memory ordering fence. mfence ensures strong read and
151 * A serializing or fence instruction is required here. A locked bus
152 * cycle on data for which we already own cache mastership is the most
159 __asm __volatile("lock; addl $0,(%%esp)" : : : "memory");
161 __asm __volatile("" : : : "memory");
166 * cpu_lfence() ensures strong read ordering for reads issued prior
167 * to the instruction verses reads issued afterwords.
169 * A serializing or fence instruction is required here. A locked bus
170 * cycle on data for which we already own cache mastership is the most
177 __asm __volatile("lock; addl $0,(%%esp)" : : : "memory");
179 __asm __volatile("" : : : "memory");
184 * cpu_sfence() ensures strong write ordering for writes issued prior
185 * to the instruction verses writes issued afterwords. Writes are
186 * ordered on intel cpus so we do not actually have to do anything.
191 __asm __volatile("" : : : "memory");
195 * cpu_ccfence() prevents the compiler from reordering instructions, in
196 * particular stores, relative to the current cpu. Use cpu_sfence() if
197 * you need to guarentee ordering by both the compiler and by the cpu.
199 * This also prevents the compiler from caching memory loads into local
200 * variables across the routine.
205 __asm __volatile("" : : : "memory");
210 #define HAVE_INLINE_FFS
217 * Note that gcc-2's builtin ffs would be used if we didn't declare
218 * this inline or turn off the builtin. The builtin is faster but
219 * broken in gcc-2.4.5 and slower but working in gcc-2.5 and later
222 return (mask == 0 ? mask : (int)bsfl((u_int)mask) + 1);
224 /* Actually, the above is way out of date. The builtins use cmov etc */
225 return (__builtin_ffs(mask));
229 #define HAVE_INLINE_FFSL
234 return (mask == 0 ? mask : (int)bsfq((u_long)mask) + 1);
237 #define HAVE_INLINE_FLS
242 return (mask == 0 ? mask : (int)bsrl((u_int)mask) + 1);
245 #define HAVE_INLINE_FLSL
250 return (mask == 0 ? mask : (int)bsrq((u_long)mask) + 1);
258 __asm __volatile("hlt");
262 * The following complications are to get around gcc not having a
263 * constraint letter for the range 0..255. We still put "d" in the
264 * constraint because "i" isn't a valid constraint when the port
265 * isn't constant. This only matters for -O0 because otherwise
266 * the non-working version gets optimized away.
268 * Use an expression-statement instead of a conditional expression
269 * because gcc-2.6.0 would promote the operands of the conditional
270 * and produce poor code for "if ((inb(var) & const1) == const2)".
272 * The unnecessary test `(port) < 0x10000' is to generate a warning if
273 * the `port' has type u_short or smaller. Such types are pessimal.
274 * This actually only works for signed types. The range check is
275 * careful to avoid generating warnings.
277 #define inb(port) __extension__ ({ \
279 if (__builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
280 && (port) < 0x10000) \
281 _data = inbc(port); \
283 _data = inbv(port); \
286 #define outb(port, data) ( \
287 __builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
288 && (port) < 0x10000 \
289 ? outbc(port, data) : outbv(port, data))
291 static __inline u_char
296 __asm __volatile("inb %1,%0" : "=a" (data) : "id" ((u_short)(port)));
301 outbc(u_int port, u_char data)
303 __asm __volatile("outb %0,%1" : : "a" (data), "id" ((u_short)(port)));
306 static __inline u_char
311 * We use %%dx and not %1 here because i/o is done at %dx and not at
312 * %edx, while gcc generates inferior code (movw instead of movl)
313 * if we tell it to load (u_short) port.
315 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
319 static __inline u_int
324 __asm __volatile("inl %%dx,%0" : "=a" (data) : "d" (port));
329 insb(u_int port, void *addr, size_t cnt)
331 __asm __volatile("cld; rep; insb"
332 : "+D" (addr), "+c" (cnt)
338 insw(u_int port, void *addr, size_t cnt)
340 __asm __volatile("cld; rep; insw"
341 : "+D" (addr), "+c" (cnt)
347 insl(u_int port, void *addr, size_t cnt)
349 __asm __volatile("cld; rep; insl"
350 : "+D" (addr), "+c" (cnt)
358 __asm __volatile("invd");
364 * If we are not a true-SMP box then smp_invltlb() is a NOP. Note that this
365 * will cause the invl*() functions to be equivalent to the cpu_invl*()
369 void smp_invltlb(void);
371 #define smp_invltlb()
374 #ifndef _CPU_INVLPG_DEFINED
377 * Invalidate a patricular VA on this cpu only
380 cpu_invlpg(void *addr)
382 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
389 static __inline u_short
394 __asm __volatile("inw %%dx,%0" : "=a" (data) : "d" (port));
398 static __inline u_int
399 loadandclear(volatile u_int *addr)
403 __asm __volatile("xorl %0,%0; xchgl %1,%0"
404 : "=&r" (result) : "m" (*addr));
409 outbv(u_int port, u_char data)
413 * Use an unnecessary assignment to help gcc's register allocator.
414 * This make a large difference for gcc-1.40 and a tiny difference
415 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
416 * best results. gcc-2.6.0 can't handle this.
419 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
423 outl(u_int port, u_int data)
426 * outl() and outw() aren't used much so we haven't looked at
427 * possible micro-optimizations such as the unnecessary
428 * assignment for them.
430 __asm __volatile("outl %0,%%dx" : : "a" (data), "d" (port));
434 outsb(u_int port, const void *addr, size_t cnt)
436 __asm __volatile("cld; rep; outsb"
437 : "+S" (addr), "+c" (cnt)
442 outsw(u_int port, const void *addr, size_t cnt)
444 __asm __volatile("cld; rep; outsw"
445 : "+S" (addr), "+c" (cnt)
450 outsl(u_int port, const void *addr, size_t cnt)
452 __asm __volatile("cld; rep; outsl"
453 : "+S" (addr), "+c" (cnt)
458 outw(u_int port, u_short data)
460 __asm __volatile("outw %0,%%dx" : : "a" (data), "d" (port));
466 __asm __volatile("pause");
469 static __inline u_long
474 __asm __volatile("pushfq; popq %0" : "=r" (rf));
478 static __inline u_int64_t
483 __asm __volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
484 return (low | ((u_int64_t)high << 32));
487 static __inline u_int64_t
492 __asm __volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (pmc));
493 return (low | ((u_int64_t)high << 32));
496 static __inline u_int64_t
501 __asm __volatile("rdtsc" : "=a" (low), "=d" (high));
502 return (low | ((u_int64_t)high << 32));
508 __asm __volatile("wbinvd");
512 write_rflags(u_long rf)
514 __asm __volatile("pushq %0; popfq" : : "r" (rf));
518 wrmsr(u_int msr, u_int64_t newval)
524 __asm __volatile("wrmsr" : : "a" (low), "d" (high), "c" (msr));
528 load_cr0(u_long data)
531 __asm __volatile("movq %0,%%cr0" : : "r" (data));
534 static __inline u_long
539 __asm __volatile("movq %%cr0,%0" : "=r" (data));
543 static __inline u_long
548 __asm __volatile("movq %%cr2,%0" : "=r" (data));
553 load_cr3(u_long data)
556 __asm __volatile("movq %0,%%cr3" : : "r" (data) : "memory");
559 static __inline u_long
564 __asm __volatile("movq %%cr3,%0" : "=r" (data));
569 load_cr4(u_long data)
571 __asm __volatile("movq %0,%%cr4" : : "r" (data));
574 static __inline u_long
579 __asm __volatile("movq %%cr4,%0" : "=r" (data));
584 * Global TLB flush (except for thise for pages marked PG_G)
594 * TLB flush for an individual page (even if it has PG_G).
595 * Only works on 486+ CPUs (i386 does not have PG_G).
601 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
604 static __inline u_int
608 __asm __volatile("movl %%fs,%0" : "=rm" (sel));
612 static __inline u_int
616 __asm __volatile("movl %%gs,%0" : "=rm" (sel));
623 __asm __volatile("movl %0,%%ds" : : "rm" (sel));
629 __asm __volatile("movl %0,%%es" : : "rm" (sel));
633 /* This is defined in <machine/specialreg.h> but is too painful to get to */
635 #define MSR_FSBASE 0xc0000100
640 /* Preserve the fsbase value across the selector load */
641 __asm __volatile("rdmsr; movl %0,%%fs; wrmsr"
642 : : "rm" (sel), "c" (MSR_FSBASE) : "eax", "edx");
646 #define MSR_GSBASE 0xc0000101
652 * Preserve the gsbase value across the selector load.
653 * Note that we have to disable interrupts because the gsbase
654 * being trashed happens to be the kernel gsbase at the time.
656 __asm __volatile("pushfq; cli; rdmsr; movw %0,%%gs; wrmsr; popfq"
657 : : "rm" (sel), "c" (MSR_GSBASE) : "eax", "edx");
660 /* Usable by userland */
664 __asm __volatile("movl %0,%%fs" : : "rm" (sel));
670 __asm __volatile("movl %0,%%gs" : : "rm" (sel));
674 /* void lidt(struct region_descriptor *addr); */
676 lidt(struct region_descriptor *addr)
678 __asm __volatile("lidt (%0)" : : "r" (addr));
681 /* void lldt(u_short sel); */
685 __asm __volatile("lldt %0" : : "r" (sel));
688 /* void ltr(u_short sel); */
692 __asm __volatile("ltr %0" : : "r" (sel));
695 static __inline u_int64_t
699 __asm __volatile("movq %%dr0,%0" : "=r" (data));
704 load_dr0(u_int64_t dr0)
706 __asm __volatile("movq %0,%%dr0" : : "r" (dr0));
709 static __inline u_int64_t
713 __asm __volatile("movq %%dr1,%0" : "=r" (data));
718 load_dr1(u_int64_t dr1)
720 __asm __volatile("movq %0,%%dr1" : : "r" (dr1));
723 static __inline u_int64_t
727 __asm __volatile("movq %%dr2,%0" : "=r" (data));
732 load_dr2(u_int64_t dr2)
734 __asm __volatile("movq %0,%%dr2" : : "r" (dr2));
737 static __inline u_int64_t
741 __asm __volatile("movq %%dr3,%0" : "=r" (data));
746 load_dr3(u_int64_t dr3)
748 __asm __volatile("movq %0,%%dr3" : : "r" (dr3));
751 static __inline u_int64_t
755 __asm __volatile("movq %%dr4,%0" : "=r" (data));
760 load_dr4(u_int64_t dr4)
762 __asm __volatile("movq %0,%%dr4" : : "r" (dr4));
765 static __inline u_int64_t
769 __asm __volatile("movq %%dr5,%0" : "=r" (data));
774 load_dr5(u_int64_t dr5)
776 __asm __volatile("movq %0,%%dr5" : : "r" (dr5));
779 static __inline u_int64_t
783 __asm __volatile("movq %%dr6,%0" : "=r" (data));
788 load_dr6(u_int64_t dr6)
790 __asm __volatile("movq %0,%%dr6" : : "r" (dr6));
793 static __inline u_int64_t
797 __asm __volatile("movq %%dr7,%0" : "=r" (data));
802 load_dr7(u_int64_t dr7)
804 __asm __volatile("movq %0,%%dr7" : : "r" (dr7));
807 static __inline register_t
812 rflags = read_rflags();
818 intr_restore(register_t rflags)
820 write_rflags(rflags);
823 #else /* !__GNUC__ */
825 int breakpoint(void);
826 void cpu_pause(void);
827 u_int bsfl(u_int mask);
828 u_int bsrl(u_int mask);
829 void cpu_disable_intr(void);
830 void cpu_enable_intr(void);
831 void cpu_invlpg(u_long addr);
832 void cpu_invlpg_range(u_long start, u_long end);
833 void do_cpuid(u_int ax, u_int *p);
835 u_char inb(u_int port);
836 u_int inl(u_int port);
837 void insb(u_int port, void *addr, size_t cnt);
838 void insl(u_int port, void *addr, size_t cnt);
839 void insw(u_int port, void *addr, size_t cnt);
841 void invlpg(u_int addr);
842 void invlpg_range(u_int start, u_int end);
843 void cpu_invltlb(void);
844 u_short inw(u_int port);
845 void load_cr0(u_int cr0);
846 void load_cr3(u_int cr3);
847 void load_cr4(u_int cr4);
848 void load_fs(u_int sel);
849 void load_gs(u_int sel);
850 struct region_descriptor;
851 void lidt(struct region_descriptor *addr);
852 void lldt(u_short sel);
853 void ltr(u_short sel);
854 void outb(u_int port, u_char data);
855 void outl(u_int port, u_int data);
856 void outsb(u_int port, void *addr, size_t cnt);
857 void outsl(u_int port, void *addr, size_t cnt);
858 void outsw(u_int port, void *addr, size_t cnt);
859 void outw(u_int port, u_short data);
860 void ia32_pause(void);
867 u_int64_t rdmsr(u_int msr);
868 u_int64_t rdpmc(u_int pmc);
869 u_int64_t rdtsc(void);
870 u_int read_rflags(void);
872 void write_rflags(u_int rf);
873 void wrmsr(u_int msr, u_int64_t newval);
874 u_int64_t rdr0(void);
875 void load_dr0(u_int64_t dr0);
876 u_int64_t rdr1(void);
877 void load_dr1(u_int64_t dr1);
878 u_int64_t rdr2(void);
879 void load_dr2(u_int64_t dr2);
880 u_int64_t rdr3(void);
881 void load_dr3(u_int64_t dr3);
882 u_int64_t rdr4(void);
883 void load_dr4(u_int64_t dr4);
884 u_int64_t rdr5(void);
885 void load_dr5(u_int64_t dr5);
886 u_int64_t rdr6(void);
887 void load_dr6(u_int64_t dr6);
888 u_int64_t rdr7(void);
889 void load_dr7(u_int64_t dr7);
890 register_t intr_disable(void);
891 void intr_restore(register_t rf);
893 #endif /* __GNUC__ */
895 void reset_dbregs(void);
899 #endif /* !_CPU_CPUFUNC_H_ */