2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_wb.c,v 1.26.2.6 2003/03/05 18:42:34 njl Exp $
33 * $DragonFly: src/sys/dev/netif/wb/if_wb.c,v 1.33 2005/11/28 17:13:44 dillon Exp $
37 * Winbond fast ethernet PCI NIC driver
39 * Supports various cheap network adapters based on the Winbond W89C840F
40 * fast ethernet controller chip. This includes adapters manufactured by
41 * Winbond itself and some made by Linksys.
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
49 * The Winbond W89C840F chip is a bus master; in some ways it resembles
50 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has
51 * one major difference which is that while the registers do many of
52 * the same things as a tulip adapter, the offsets are different: where
53 * tulip registers are typically spaced 8 bytes apart, the Winbond
54 * registers are spaced 4 bytes apart. The receiver filter is also
55 * programmed differently.
57 * Like the tulip, the Winbond chip uses small descriptors containing
58 * a status word, a control word and 32-bit areas that can either be used
59 * to point to two external data blocks, or to point to a single block
60 * and another descriptor in a linked list. Descriptors can be grouped
61 * together in blocks to form fixed length rings or can be chained
62 * together in linked lists. A single packet may be spread out over
63 * several descriptors if necessary.
65 * For the receive ring, this driver uses a linked list of descriptors,
66 * each pointing to a single mbuf cluster buffer, which us large enough
67 * to hold an entire packet. The link list is looped back to created a
70 * For transmission, the driver creates a linked list of 'super descriptors'
71 * which each contain several individual descriptors linked toghether.
72 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we
73 * abuse as fragment pointers. This allows us to use a buffer managment
74 * scheme very similar to that used in the ThunderLAN and Etherlink XL
77 * Autonegotiation is performed using the external PHY via the MII bus.
78 * The sample boards I have all use a Davicom PHY.
80 * Note: the author of the Linux driver for the Winbond chip alludes
81 * to some sort of flaw in the chip's design that seems to mandate some
82 * drastic workaround which signigicantly impairs transmit performance.
83 * I have no idea what he's on about: transmit performance with all
84 * three of my test boards seems fine.
89 #include <sys/param.h>
90 #include <sys/systm.h>
91 #include <sys/sockio.h>
93 #include <sys/malloc.h>
94 #include <sys/kernel.h>
95 #include <sys/socket.h>
96 #include <sys/queue.h>
97 #include <sys/serialize.h>
98 #include <sys/thread2.h>
101 #include <net/ifq_var.h>
102 #include <net/if_arp.h>
103 #include <net/ethernet.h>
104 #include <net/if_dl.h>
105 #include <net/if_media.h>
109 #include <vm/vm.h> /* for vtophys */
110 #include <vm/pmap.h> /* for vtophys */
111 #include <machine/bus.h>
112 #include <machine/resource.h>
114 #include <sys/rman.h>
116 #include <bus/pci/pcireg.h>
117 #include <bus/pci/pcivar.h>
119 #include <dev/netif/mii_layer/mii.h>
120 #include <dev/netif/mii_layer/miivar.h>
122 /* "controller miibus0" required. See GENERIC if you get errors here. */
123 #include "miibus_if.h"
125 #define WB_USEIOSPACE
127 #include "if_wbreg.h"
130 * Various supported device vendors/types and their names.
132 static struct wb_type wb_devs[] = {
133 { WB_VENDORID, WB_DEVICEID_840F,
134 "Winbond W89C840F 10/100BaseTX" },
135 { CP_VENDORID, CP_DEVICEID_RL100,
136 "Compex RL100-ATX 10/100baseTX" },
140 static int wb_probe(device_t);
141 static int wb_attach(device_t);
142 static int wb_detach(device_t);
144 static void wb_bfree(void *);
145 static int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *,
147 static int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *);
149 static void wb_rxeof(struct wb_softc *);
150 static void wb_rxeoc(struct wb_softc *);
151 static void wb_txeof(struct wb_softc *);
152 static void wb_txeoc(struct wb_softc *);
153 static void wb_intr(void *);
154 static void wb_tick(void *);
155 static void wb_start(struct ifnet *);
156 static int wb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
157 static void wb_init(void *);
158 static void wb_stop(struct wb_softc *);
159 static void wb_watchdog(struct ifnet *);
160 static void wb_shutdown(device_t);
161 static int wb_ifmedia_upd(struct ifnet *);
162 static void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *);
164 static void wb_eeprom_putbyte(struct wb_softc *, int);
165 static void wb_eeprom_getword(struct wb_softc *, int, uint16_t *);
166 static void wb_read_eeprom(struct wb_softc *, caddr_t, int, int);
167 static void wb_mii_sync(struct wb_softc *);
168 static void wb_mii_send(struct wb_softc *, uint32_t, int);
169 static int wb_mii_readreg(struct wb_softc *, struct wb_mii_frame *);
170 static int wb_mii_writereg(struct wb_softc *, struct wb_mii_frame *);
172 static void wb_setcfg(struct wb_softc *, uint32_t);
173 static void wb_setmulti(struct wb_softc *);
174 static void wb_reset(struct wb_softc *);
175 static void wb_fixmedia(struct wb_softc *);
176 static int wb_list_rx_init(struct wb_softc *);
177 static int wb_list_tx_init(struct wb_softc *);
179 static int wb_miibus_readreg(device_t, int, int);
180 static int wb_miibus_writereg(device_t, int, int, int);
181 static void wb_miibus_statchg(device_t);
184 #define WB_RES SYS_RES_IOPORT
185 #define WB_RID WB_PCI_LOIO
187 #define WB_RES SYS_RES_MEMORY
188 #define WB_RID WB_PCI_LOMEM
191 static device_method_t wb_methods[] = {
192 /* Device interface */
193 DEVMETHOD(device_probe, wb_probe),
194 DEVMETHOD(device_attach, wb_attach),
195 DEVMETHOD(device_detach, wb_detach),
196 DEVMETHOD(device_shutdown, wb_shutdown),
198 /* bus interface, for miibus */
199 DEVMETHOD(bus_print_child, bus_generic_print_child),
200 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
203 DEVMETHOD(miibus_readreg, wb_miibus_readreg),
204 DEVMETHOD(miibus_writereg, wb_miibus_writereg),
205 DEVMETHOD(miibus_statchg, wb_miibus_statchg),
209 static DEFINE_CLASS_0(wb, wb_driver, wb_methods, sizeof(struct wb_softc));
210 static devclass_t wb_devclass;
212 DECLARE_DUMMY_MODULE(if_wb);
213 DRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0);
214 DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0);
216 #define WB_SETBIT(sc, reg, x) \
217 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
219 #define WB_CLRBIT(sc, reg, x) \
220 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
223 CSR_WRITE_4(sc, WB_SIO, CSR_READ_4(sc, WB_SIO) | (x))
226 CSR_WRITE_4(sc, WB_SIO, CSR_READ_4(sc, WB_SIO) & ~(x))
229 * Send a read command and address to the EEPROM, check for ACK.
232 wb_eeprom_putbyte(struct wb_softc *sc, int addr)
236 d = addr | WB_EECMD_READ;
239 * Feed in each bit and stobe the clock.
241 for (i = 0x400; i; i >>= 1) {
243 SIO_SET(WB_SIO_EE_DATAIN);
245 SIO_CLR(WB_SIO_EE_DATAIN);
247 SIO_SET(WB_SIO_EE_CLK);
249 SIO_CLR(WB_SIO_EE_CLK);
255 * Read a word of data stored in the EEPROM at address 'addr.'
258 wb_eeprom_getword(struct wb_softc *sc, int addr, uint16_t *dest)
263 /* Enter EEPROM access mode. */
264 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
267 * Send address of word we want to read.
269 wb_eeprom_putbyte(sc, addr);
271 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
274 * Start reading bits from EEPROM.
276 for (i = 0x8000; i; i >>= 1) {
277 SIO_SET(WB_SIO_EE_CLK);
279 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)
281 SIO_CLR(WB_SIO_EE_CLK);
285 /* Turn off EEPROM access mode. */
286 CSR_WRITE_4(sc, WB_SIO, 0);
292 * Read a sequence of words from the EEPROM.
295 wb_read_eeprom(struct wb_softc *sc, caddr_t dest, int off, int cnt)
298 uint16_t word = 0, *ptr;
300 for (i = 0; i < cnt; i++) {
301 wb_eeprom_getword(sc, off + i, &word);
302 ptr = (uint16_t *)(dest + (i * 2));
308 * Sync the PHYs by setting data bit and strobing the clock 32 times.
311 wb_mii_sync(struct wb_softc *sc)
315 SIO_SET(WB_SIO_MII_DIR | WB_SIO_MII_DATAIN);
317 for (i = 0; i < 32; i++) {
318 SIO_SET(WB_SIO_MII_CLK);
320 SIO_CLR(WB_SIO_MII_CLK);
326 * Clock a series of bits through the MII.
329 wb_mii_send(struct wb_softc *sc, uint32_t bits, int cnt)
333 SIO_CLR(WB_SIO_MII_CLK);
335 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
337 SIO_SET(WB_SIO_MII_DATAIN);
339 SIO_CLR(WB_SIO_MII_DATAIN);
341 SIO_CLR(WB_SIO_MII_CLK);
343 SIO_SET(WB_SIO_MII_CLK);
348 * Read an PHY register through the MII.
351 wb_mii_readreg(struct wb_softc *sc, struct wb_mii_frame *frame)
358 * Set up frame for RX.
360 frame->mii_stdelim = WB_MII_STARTDELIM;
361 frame->mii_opcode = WB_MII_READOP;
362 frame->mii_turnaround = 0;
365 CSR_WRITE_4(sc, WB_SIO, 0);
370 SIO_SET(WB_SIO_MII_DIR);
375 * Send command/address info.
377 wb_mii_send(sc, frame->mii_stdelim, 2);
378 wb_mii_send(sc, frame->mii_opcode, 2);
379 wb_mii_send(sc, frame->mii_phyaddr, 5);
380 wb_mii_send(sc, frame->mii_regaddr, 5);
383 SIO_CLR((WB_SIO_MII_CLK | WB_SIO_MII_DATAIN));
385 SIO_SET(WB_SIO_MII_CLK);
389 SIO_CLR(WB_SIO_MII_DIR);
391 SIO_CLR(WB_SIO_MII_CLK);
393 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT;
394 SIO_SET(WB_SIO_MII_CLK);
396 SIO_CLR(WB_SIO_MII_CLK);
398 SIO_SET(WB_SIO_MII_CLK);
402 * Now try reading data bits. If the ack failed, we still
403 * need to clock through 16 cycles to keep the PHY(s) in sync.
406 for(i = 0; i < 16; i++) {
407 SIO_CLR(WB_SIO_MII_CLK);
409 SIO_SET(WB_SIO_MII_CLK);
415 for (i = 0x8000; i; i >>= 1) {
416 SIO_CLR(WB_SIO_MII_CLK);
419 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT)
420 frame->mii_data |= i;
423 SIO_SET(WB_SIO_MII_CLK);
429 SIO_CLR(WB_SIO_MII_CLK);
431 SIO_SET(WB_SIO_MII_CLK);
442 * Write to a PHY register through the MII.
445 wb_mii_writereg(struct wb_softc *sc, struct wb_mii_frame *frame)
450 * Set up frame for TX.
453 frame->mii_stdelim = WB_MII_STARTDELIM;
454 frame->mii_opcode = WB_MII_WRITEOP;
455 frame->mii_turnaround = WB_MII_TURNAROUND;
458 * Turn on data output.
460 SIO_SET(WB_SIO_MII_DIR);
464 wb_mii_send(sc, frame->mii_stdelim, 2);
465 wb_mii_send(sc, frame->mii_opcode, 2);
466 wb_mii_send(sc, frame->mii_phyaddr, 5);
467 wb_mii_send(sc, frame->mii_regaddr, 5);
468 wb_mii_send(sc, frame->mii_turnaround, 2);
469 wb_mii_send(sc, frame->mii_data, 16);
472 SIO_SET(WB_SIO_MII_CLK);
474 SIO_CLR(WB_SIO_MII_CLK);
480 SIO_CLR(WB_SIO_MII_DIR);
488 wb_miibus_readreg(device_t dev, int phy, int reg)
490 struct wb_softc *sc = device_get_softc(dev);
491 struct wb_mii_frame frame;
493 bzero(&frame, sizeof(frame));
495 frame.mii_phyaddr = phy;
496 frame.mii_regaddr = reg;
497 wb_mii_readreg(sc, &frame);
499 return(frame.mii_data);
503 wb_miibus_writereg(device_t dev, int phy, int reg, int data)
505 struct wb_softc *sc = device_get_softc(dev);
506 struct wb_mii_frame frame;
508 bzero(&frame, sizeof(frame));
510 frame.mii_phyaddr = phy;
511 frame.mii_regaddr = reg;
512 frame.mii_data = data;
514 wb_mii_writereg(sc, &frame);
520 wb_miibus_statchg(device_t dev)
522 struct wb_softc *sc = device_get_softc(dev);
523 struct mii_data *mii;
525 mii = device_get_softc(sc->wb_miibus);
526 wb_setcfg(sc, mii->mii_media_active);
530 * Program the 64-bit multicast hash filter.
533 wb_setmulti(struct wb_softc *sc)
535 struct ifnet *ifp = &sc->arpcom.ac_if;
537 uint32_t hashes[2] = { 0, 0 };
538 struct ifmultiaddr *ifma;
541 rxfilt = CSR_READ_4(sc, WB_NETCFG);
543 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
544 rxfilt |= WB_NETCFG_RX_MULTI;
545 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
546 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF);
547 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF);
551 /* first, zot all the existing hash bits */
552 CSR_WRITE_4(sc, WB_MAR0, 0);
553 CSR_WRITE_4(sc, WB_MAR1, 0);
555 /* now program new ones */
556 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
557 if (ifma->ifma_addr->sa_family != AF_LINK)
559 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *)
560 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
562 hashes[0] |= (1 << h);
564 hashes[1] |= (1 << (h - 32));
569 rxfilt |= WB_NETCFG_RX_MULTI;
571 rxfilt &= ~WB_NETCFG_RX_MULTI;
573 CSR_WRITE_4(sc, WB_MAR0, hashes[0]);
574 CSR_WRITE_4(sc, WB_MAR1, hashes[1]);
575 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
579 * The Winbond manual states that in order to fiddle with the
580 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
581 * first have to put the transmit and/or receive logic in the idle state.
584 wb_setcfg(struct wb_softc *sc, uint32_t media)
588 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON | WB_NETCFG_RX_ON)) {
590 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON | WB_NETCFG_RX_ON));
592 for (i = 0; i < WB_TIMEOUT; i++) {
594 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&
595 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE))
599 if (i == WB_TIMEOUT) {
600 if_printf(&sc->arpcom.ac_if, "failed to force tx and "
601 "rx to idle state\n");
605 if (IFM_SUBTYPE(media) == IFM_10_T)
606 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
608 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
610 if ((media & IFM_GMASK) == IFM_FDX)
611 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
613 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
616 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON | WB_NETCFG_RX_ON);
620 wb_reset(struct wb_softc *sc)
623 struct mii_data *mii;
625 CSR_WRITE_4(sc, WB_NETCFG, 0);
626 CSR_WRITE_4(sc, WB_BUSCTL, 0);
627 CSR_WRITE_4(sc, WB_TXADDR, 0);
628 CSR_WRITE_4(sc, WB_RXADDR, 0);
630 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
631 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
633 for (i = 0; i < WB_TIMEOUT; i++) {
635 if ((CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET) == 0)
639 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
641 /* Wait a little while for the chip to get its brains in order. */
644 if (sc->wb_miibus == NULL)
647 mii = device_get_softc(sc->wb_miibus);
651 if (mii->mii_instance) {
652 struct mii_softc *miisc;
653 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
654 mii_phy_reset(miisc);
659 wb_fixmedia(struct wb_softc *sc)
661 struct mii_data *mii;
664 if (sc->wb_miibus == NULL)
667 mii = device_get_softc(sc->wb_miibus);
670 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
671 media = mii->mii_media_active & ~IFM_10_T;
673 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
674 media = mii->mii_media_active & ~IFM_100_TX;
679 ifmedia_set(&mii->mii_media, media);
683 * Probe for a Winbond chip. Check the PCI vendor and device
684 * IDs against our list and return a device name if we find a match.
686 static int wb_probe(device_t dev)
689 uint16_t vendor, product;
691 vendor = pci_get_vendor(dev);
692 product = pci_get_device(dev);
694 for (t = wb_devs; t->wb_name != NULL; t++) {
695 if (vendor == t->wb_vid && product == t->wb_did) {
696 device_set_desc(dev, t->wb_name);
705 * Attach the interface. Allocate softc structures, do ifmedia
706 * setup and ethernet/BPF attach.
709 wb_attach(device_t dev)
711 u_char eaddr[ETHER_ADDR_LEN];
716 sc = device_get_softc(dev);
717 callout_init(&sc->wb_stat_timer);
720 * Handle power management nonsense.
722 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
723 uint32_t iobase, membase, irq;
725 /* Save important PCI config data. */
726 iobase = pci_read_config(dev, WB_PCI_LOIO, 4);
727 membase = pci_read_config(dev, WB_PCI_LOMEM, 4);
728 irq = pci_read_config(dev, WB_PCI_INTLINE, 4);
730 /* Reset the power state. */
731 device_printf(dev, "chip is in D%d power mode "
732 "-- setting to D0\n", pci_get_powerstate(dev));
733 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
735 /* Restore PCI config data. */
736 pci_write_config(dev, WB_PCI_LOIO, iobase, 4);
737 pci_write_config(dev, WB_PCI_LOMEM, membase, 4);
738 pci_write_config(dev, WB_PCI_INTLINE, irq, 4);
741 pci_enable_busmaster(dev);
744 sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE);
746 if (sc->wb_res == NULL) {
747 device_printf(dev, "couldn't map ports/memory\n");
752 sc->wb_btag = rman_get_bustag(sc->wb_res);
753 sc->wb_bhandle = rman_get_bushandle(sc->wb_res);
755 /* Allocate interrupt */
757 sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
758 RF_SHAREABLE | RF_ACTIVE);
760 if (sc->wb_irq == NULL) {
761 device_printf(dev, "couldn't map interrupt\n");
766 /* Save the cache line size. */
767 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF;
769 ifp = &sc->arpcom.ac_if;
770 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
772 /* Reset the adapter. */
776 * Get station address from the EEPROM.
778 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3);
780 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF,
781 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
783 if (sc->wb_ldata == NULL) {
784 device_printf(dev, "no memory for list buffers!\n");
789 bzero(sc->wb_ldata, sizeof(struct wb_list_data));
792 ifp->if_mtu = ETHERMTU;
793 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
794 ifp->if_ioctl = wb_ioctl;
795 ifp->if_start = wb_start;
796 ifp->if_watchdog = wb_watchdog;
797 ifp->if_init = wb_init;
798 ifp->if_baudrate = 10000000;
799 ifq_set_maxlen(&ifp->if_snd, WB_TX_LIST_CNT - 1);
800 ifq_set_ready(&ifp->if_snd);
805 if (mii_phy_probe(dev, &sc->wb_miibus,
806 wb_ifmedia_upd, wb_ifmedia_sts)) {
812 * Call MI attach routine.
814 ether_ifattach(ifp, eaddr, NULL);
816 error = bus_setup_intr(dev, sc->wb_irq, INTR_NETSAFE,
817 wb_intr, sc, &sc->wb_intrhand,
821 device_printf(dev, "couldn't set up irq\n");
834 wb_detach(device_t dev)
836 struct wb_softc *sc = device_get_softc(dev);
837 struct ifnet *ifp = &sc->arpcom.ac_if;
839 lwkt_serialize_enter(ifp->if_serializer);
841 if (device_is_attached(dev)) {
842 if (bus_child_present(dev))
848 device_delete_child(dev, sc->wb_miibus);
849 bus_generic_detach(dev);
852 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
855 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
857 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
858 if (sc->wb_ldata_ptr) {
859 contigfree(sc->wb_ldata_ptr, sizeof(struct wb_list_data) + 8,
862 lwkt_serialize_exit(ifp->if_serializer);
868 * Initialize the transmit descriptors.
871 wb_list_tx_init(struct wb_softc *sc)
873 struct wb_chain_data *cd;
874 struct wb_list_data *ld;
880 for (i = 0; i < WB_TX_LIST_CNT; i++) {
881 nexti = (i == WB_TX_LIST_CNT - 1) ? 0 : i + 1;
882 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i];
883 cd->wb_tx_chain[i].wb_nextdesc = &cd->wb_tx_chain[nexti];
886 cd->wb_tx_free = &cd->wb_tx_chain[0];
887 cd->wb_tx_tail = cd->wb_tx_head = NULL;
893 * Initialize the RX descriptors and allocate mbufs for them. Note that
894 * we arrange the descriptors in a closed ring, so that the last descriptor
895 * points back to the first.
898 wb_list_rx_init(struct wb_softc *sc)
900 struct wb_chain_data *cd;
901 struct wb_list_data *ld;
907 for (i = 0; i < WB_RX_LIST_CNT; i++) {
908 cd->wb_rx_chain[i].wb_ptr = &ld->wb_rx_list[i];
909 cd->wb_rx_chain[i].wb_buf = &ld->wb_rxbufs[i];
910 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS)
912 nexti = (WB_RX_LIST_CNT - 1) ? 0 : i + 1;
913 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[nexti];
914 ld->wb_rx_list[i].wb_next = vtophys(&ld->wb_rx_list[nexti]);
917 cd->wb_rx_head = &cd->wb_rx_chain[0];
928 * Initialize an RX descriptor and attach an MBUF cluster.
931 wb_newbuf(struct wb_softc *sc, struct wb_chain_onefrag *c, struct mbuf *m)
933 struct mbuf *m_new = NULL;
936 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
940 m_new->m_data = m_new->m_ext.ext_buf = c->wb_buf;
941 m_new->m_flags |= M_EXT;
942 m_new->m_ext.ext_size = m_new->m_pkthdr.len =
943 m_new->m_len = WB_BUFBYTES;
944 m_new->m_ext.ext_free = wb_bfree;
945 m_new->m_ext.ext_ref = wb_bfree;
948 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES;
949 m_new->m_data = m_new->m_ext.ext_buf;
952 m_adj(m_new, sizeof(uint64_t));
955 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t));
956 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536;
957 c->wb_ptr->wb_status = WB_RXSTAT;
963 * A frame has been uploaded: pass the resulting mbuf chain up to
964 * the higher level protocols.
967 wb_rxeof(struct wb_softc *sc)
969 struct ifnet *ifp = &sc->arpcom.ac_if;
971 struct wb_chain_onefrag *cur_rx;
976 rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status;
977 if ((rxstat & WB_RXSTAT_OWN) == 0)
980 cur_rx = sc->wb_cdata.wb_rx_head;
981 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc;
985 if ((rxstat & WB_RXSTAT_MIIERR) ||
986 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) ||
987 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) ||
988 (rxstat & WB_RXSTAT_LASTFRAG) == 0||
989 (rxstat & WB_RXSTAT_RXCMP) == 0) {
991 wb_newbuf(sc, cur_rx, m);
992 if_printf(ifp, "receiver babbling: possible chip "
993 "bug, forcing reset\n");
1000 if (rxstat & WB_RXSTAT_RXERR) {
1002 wb_newbuf(sc, cur_rx, m);
1006 /* No errors; receive the packet. */
1007 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status);
1010 * XXX The Winbond chip includes the CRC with every
1011 * received frame, and there's no way to turn this
1012 * behavior off (at least, I can't find anything in
1013 * the manual that explains how to do it) so we have
1014 * to trim off the CRC manually.
1016 total_len -= ETHER_CRC_LEN;
1018 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1019 total_len + ETHER_ALIGN, 0, ifp, NULL);
1020 wb_newbuf(sc, cur_rx, m);
1025 m_adj(m0, ETHER_ALIGN);
1029 ifp->if_input(ifp, m);
1034 wb_rxeoc(struct wb_softc *sc)
1038 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1039 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1040 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1041 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND)
1042 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1046 * A frame was downloaded to the chip. It's safe for us to clean up
1050 wb_txeof(struct wb_softc *sc)
1052 struct ifnet *ifp = &sc->arpcom.ac_if;
1053 struct wb_chain *cur_tx;
1055 /* Clear the timeout timer. */
1058 if (sc->wb_cdata.wb_tx_head == NULL)
1062 * Go through our tx list and free mbufs for those
1063 * frames that have been transmitted.
1065 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) {
1068 cur_tx = sc->wb_cdata.wb_tx_head;
1069 txstat = WB_TXSTATUS(cur_tx);
1071 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT)
1074 if (txstat & WB_TXSTAT_TXERR) {
1076 if (txstat & WB_TXSTAT_ABORT)
1077 ifp->if_collisions++;
1078 if (txstat & WB_TXSTAT_LATECOLL)
1079 ifp->if_collisions++;
1082 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3;
1085 m_freem(cur_tx->wb_mbuf);
1086 cur_tx->wb_mbuf = NULL;
1088 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) {
1089 sc->wb_cdata.wb_tx_head = NULL;
1090 sc->wb_cdata.wb_tx_tail = NULL;
1094 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc;
1099 * TX 'end of channel' interrupt handler.
1102 wb_txeoc(struct wb_softc *sc)
1104 struct ifnet *ifp = &sc->arpcom.ac_if;
1108 if (sc->wb_cdata.wb_tx_head == NULL) {
1109 ifp->if_flags &= ~IFF_OACTIVE;
1110 sc->wb_cdata.wb_tx_tail = NULL;
1111 } else if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) {
1112 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN;
1114 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1121 struct wb_softc *sc = arg;
1122 struct ifnet *ifp = &sc->arpcom.ac_if;
1125 if ((ifp->if_flags & IFF_UP) == 0)
1128 /* Disable interrupts. */
1129 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1132 status = CSR_READ_4(sc, WB_ISR);
1134 CSR_WRITE_4(sc, WB_ISR, status);
1136 if ((status & WB_INTRS) == 0)
1139 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) {
1142 if (status & WB_ISR_RX_ERR)
1148 if (status & WB_ISR_RX_OK)
1151 if (status & WB_ISR_RX_IDLE)
1154 if (status & WB_ISR_TX_OK)
1157 if (status & WB_ISR_TX_NOBUF)
1160 if (status & WB_ISR_TX_IDLE) {
1162 if (sc->wb_cdata.wb_tx_head != NULL) {
1163 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1164 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1168 if (status & WB_ISR_TX_UNDERRUN) {
1171 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1172 /* Jack up TX threshold */
1173 sc->wb_txthresh += WB_TXTHRESH_CHUNK;
1174 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1175 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1176 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1179 if (status & WB_ISR_BUS_ERR) {
1185 /* Re-enable interrupts. */
1186 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1188 if (!ifq_is_empty(&ifp->if_snd))
1195 struct wb_softc *sc = xsc;
1196 struct ifnet *ifp = &sc->arpcom.ac_if;
1197 struct mii_data *mii = device_get_softc(sc->wb_miibus);
1199 lwkt_serialize_enter(ifp->if_serializer);
1201 callout_reset(&sc->wb_stat_timer, hz, wb_tick, sc);
1202 lwkt_serialize_exit(ifp->if_serializer);
1206 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1207 * pointers to the fragment pointers.
1210 wb_encap(struct wb_softc *sc, struct wb_chain *c, struct mbuf *m_head)
1212 struct wb_desc *f = NULL;
1214 int frag, total_len;
1217 * Start packing the mbufs in this chain into
1218 * the fragment pointers. Stop when we run out
1219 * of fragments or hit the end of the mbuf chain.
1223 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1224 if (m->m_len != 0) {
1225 if (frag == WB_MAXFRAGS)
1227 total_len += m->m_len;
1228 f = &c->wb_ptr->wb_frag[frag];
1229 f->wb_ctl = WB_TXCTL_TLINK | m->m_len;
1231 f->wb_ctl |= WB_TXCTL_FIRSTFRAG;
1234 f->wb_status = WB_TXSTAT_OWN;
1236 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]);
1237 f->wb_data = vtophys(mtod(m, vm_offset_t));
1243 * Handle special case: we used up all 16 fragments,
1244 * but we have more mbufs left in the chain. Copy the
1245 * data into an mbuf cluster. Note that we don't
1246 * bother clearing the values in the other fragment
1247 * pointers/counters; it wouldn't gain us anything,
1248 * and would waste cycles.
1251 struct mbuf *m_new = NULL;
1253 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1256 if (m_head->m_pkthdr.len > MHLEN) {
1257 MCLGET(m_new, MB_DONTWAIT);
1258 if ((m_new->m_flags & M_EXT) == 0) {
1263 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1264 mtod(m_new, caddr_t));
1265 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1268 f = &c->wb_ptr->wb_frag[0];
1270 f->wb_data = vtophys(mtod(m_new, caddr_t));
1271 f->wb_ctl = total_len = m_new->m_len;
1272 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG;
1276 if (total_len < WB_MIN_FRAMELEN) {
1277 f = &c->wb_ptr->wb_frag[frag];
1278 f->wb_ctl = WB_MIN_FRAMELEN - total_len;
1279 f->wb_data = vtophys(&sc->wb_cdata.wb_pad);
1280 f->wb_ctl |= WB_TXCTL_TLINK;
1281 f->wb_status = WB_TXSTAT_OWN;
1285 c->wb_mbuf = m_head;
1286 c->wb_lastdesc = frag - 1;
1287 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG;
1288 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]);
1294 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1295 * to the mbuf data regions directly in the transmit lists. We also save a
1296 * copy of the pointers since the transmit list fragment pointers are
1297 * physical addresses.
1300 wb_start(struct ifnet *ifp)
1302 struct wb_softc *sc = ifp->if_softc;
1303 struct mbuf *m_head = NULL;
1304 struct wb_chain *cur_tx = NULL, *start_tx;
1307 * Check for an available queue slot. If there are none,
1310 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) {
1311 ifp->if_flags |= IFF_OACTIVE;
1315 start_tx = sc->wb_cdata.wb_tx_free;
1317 while (sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) {
1318 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1322 /* Pick a descriptor off the free list. */
1323 cur_tx = sc->wb_cdata.wb_tx_free;
1324 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc;
1326 /* Pack the data into the descriptor. */
1327 wb_encap(sc, cur_tx, m_head);
1329 if (cur_tx != start_tx)
1330 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN;
1332 BPF_MTAP(ifp, cur_tx->wb_mbuf);
1336 * If there are no packets queued, bail.
1342 * Place the request for the upload interrupt
1343 * in the last descriptor in the chain. This way, if
1344 * we're chaining several packets at once, we'll only
1345 * get an interupt once for the whole chain rather than
1346 * once for each packet.
1348 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT;
1349 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT;
1350 sc->wb_cdata.wb_tx_tail = cur_tx;
1352 if (sc->wb_cdata.wb_tx_head == NULL) {
1353 sc->wb_cdata.wb_tx_head = start_tx;
1354 WB_TXOWN(start_tx) = WB_TXSTAT_OWN;
1355 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1358 * We need to distinguish between the case where
1359 * the own bit is clear because the chip cleared it
1360 * and where the own bit is clear because we haven't
1361 * set it yet. The magic value WB_UNSET is just some
1362 * ramdomly chosen number which doesn't have the own
1363 * bit set. When we actually transmit the frame, the
1364 * status word will have _only_ the own bit set, so
1365 * the txeoc handler will be able to tell if it needs
1366 * to initiate another transmission to flush out pending
1369 WB_TXOWN(start_tx) = WB_UNSENT;
1373 * Set a timeout in case the chip goes out to lunch.
1381 struct wb_softc *sc = xsc;
1382 struct ifnet *ifp = &sc->arpcom.ac_if;
1384 struct mii_data *mii;
1388 mii = device_get_softc(sc->wb_miibus);
1391 * Cancel pending I/O and free all RX/TX buffers.
1396 sc->wb_txthresh = WB_TXTHRESH_INIT;
1399 * Set cache alignment and burst length.
1402 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG);
1403 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1404 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1407 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE | WB_BUSCTL_ARBITRATION);
1408 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG);
1409 switch(sc->wb_cachesize) {
1411 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG);
1414 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG);
1417 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG);
1421 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE);
1425 /* This doesn't tend to work too well at 100Mbps. */
1426 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON);
1428 /* Init our MAC address */
1429 for (i = 0; i < ETHER_ADDR_LEN; i++)
1430 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]);
1432 /* Init circular RX list. */
1433 if (wb_list_rx_init(sc) == ENOBUFS) {
1434 if_printf(ifp, "initialization failed: no "
1435 "memory for rx buffers\n");
1441 /* Init TX descriptors. */
1442 wb_list_tx_init(sc);
1444 /* If we want promiscuous mode, set the allframes bit. */
1445 if (ifp->if_flags & IFF_PROMISC)
1446 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1448 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1451 * Set capture broadcast bit to capture broadcast frames.
1453 if (ifp->if_flags & IFF_BROADCAST)
1454 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1456 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1459 * Program the multicast filter, if necessary.
1464 * Load the address of the RX list.
1466 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1467 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1470 * Enable interrupts.
1472 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1473 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF);
1475 /* Enable receiver and transmitter. */
1476 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1477 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1479 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1480 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0]));
1481 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1485 ifp->if_flags |= IFF_RUNNING;
1486 ifp->if_flags &= ~IFF_OACTIVE;
1490 callout_reset(&sc->wb_stat_timer, hz, wb_tick, sc);
1494 * Set media options.
1497 wb_ifmedia_upd(struct ifnet *ifp)
1499 struct wb_softc *sc = ifp->if_softc;
1501 if (ifp->if_flags & IFF_UP)
1508 * Report current media status.
1511 wb_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1513 struct wb_softc *sc = ifp->if_softc;
1514 struct mii_data *mii = device_get_softc(sc->wb_miibus);
1517 ifmr->ifm_active = mii->mii_media_active;
1518 ifmr->ifm_status = mii->mii_media_status;
1522 wb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1524 struct wb_softc *sc = ifp->if_softc;
1525 struct mii_data *mii;
1526 struct ifreq *ifr = (struct ifreq *) data;
1533 if (ifp->if_flags & IFF_UP)
1535 else if (ifp->if_flags & IFF_RUNNING)
1546 mii = device_get_softc(sc->wb_miibus);
1547 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1550 error = ether_ioctl(ifp, command, data);
1560 wb_watchdog(struct ifnet *ifp)
1562 struct wb_softc *sc = ifp->if_softc;
1565 if_printf(ifp, "watchdog timeout\n");
1567 if ((wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) == 0)
1568 if_printf(ifp, "no carrier - transceiver cable problem?\n");
1574 if (!ifq_is_empty(&ifp->if_snd))
1579 * Stop the adapter and free any mbufs allocated to the
1583 wb_stop(struct wb_softc *sc)
1585 struct ifnet *ifp = &sc->arpcom.ac_if;
1590 callout_stop(&sc->wb_stat_timer);
1592 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON | WB_NETCFG_TX_ON));
1593 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1594 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000);
1595 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000);
1598 * Free data in the RX lists.
1600 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1601 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) {
1602 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf);
1603 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL;
1606 bzero(&sc->wb_ldata->wb_rx_list, sizeof(sc->wb_ldata->wb_rx_list));
1609 * Free the TX list buffers.
1611 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1612 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) {
1613 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf);
1614 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL;
1618 bzero(&sc->wb_ldata->wb_tx_list, sizeof(sc->wb_ldata->wb_tx_list));
1620 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1624 * Stop all chip I/O so that the kernel's probe routines don't
1625 * get confused by errant DMAs when rebooting.
1628 wb_shutdown(device_t dev)
1630 struct wb_softc *sc = device_get_softc(dev);
1631 struct ifnet *ifp = &sc->arpcom.ac_if;
1633 lwkt_serialize_enter(ifp->if_serializer);
1635 lwkt_serialize_exit(ifp->if_serializer);