1 /* $OpenBSD: if_nfe.c,v 1.63 2006/06/17 18:00:43 brad Exp $ */
2 /* $DragonFly: src/sys/dev/netif/nfe/if_nfe.c,v 1.20 2008/05/14 11:59:21 sephe Exp $ */
5 * Copyright (c) 2006 The DragonFly Project. All rights reserved.
7 * This code is derived from software contributed to The DragonFly Project
8 * by Sepherosa Ziehau <sepherosa@gmail.com> and
9 * Matthew Dillon <dillon@apollo.backplane.com>
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
21 * 3. Neither the name of The DragonFly Project nor the names of its
22 * contributors may be used to endorse or promote products derived
23 * from this software without specific, prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
28 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
29 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
30 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
31 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
32 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
33 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
34 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
35 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * Copyright (c) 2006 Damien Bergamini <damien.bergamini@free.fr>
41 * Copyright (c) 2005, 2006 Jonathan Gray <jsg@openbsd.org>
43 * Permission to use, copy, modify, and distribute this software for any
44 * purpose with or without fee is hereby granted, provided that the above
45 * copyright notice and this permission notice appear in all copies.
47 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
48 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
49 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
50 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
51 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
52 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
53 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
56 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */
58 #include "opt_polling.h"
60 #include <sys/param.h>
61 #include <sys/endian.h>
62 #include <sys/kernel.h>
64 #include <sys/interrupt.h>
67 #include <sys/serialize.h>
68 #include <sys/socket.h>
69 #include <sys/sockio.h>
70 #include <sys/sysctl.h>
72 #include <net/ethernet.h>
75 #include <net/if_arp.h>
76 #include <net/if_dl.h>
77 #include <net/if_media.h>
78 #include <net/ifq_var.h>
79 #include <net/if_types.h>
80 #include <net/if_var.h>
81 #include <net/vlan/if_vlan_var.h>
82 #include <net/vlan/if_vlan_ether.h>
84 #include <bus/pci/pcireg.h>
85 #include <bus/pci/pcivar.h>
86 #include <bus/pci/pcidevs.h>
88 #include <dev/netif/mii_layer/mii.h>
89 #include <dev/netif/mii_layer/miivar.h>
91 #include "miibus_if.h"
93 #include <dev/netif/nfe/if_nfereg.h>
94 #include <dev/netif/nfe/if_nfevar.h>
97 #define NFE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
99 static int nfe_probe(device_t);
100 static int nfe_attach(device_t);
101 static int nfe_detach(device_t);
102 static void nfe_shutdown(device_t);
103 static int nfe_resume(device_t);
104 static int nfe_suspend(device_t);
106 static int nfe_miibus_readreg(device_t, int, int);
107 static void nfe_miibus_writereg(device_t, int, int, int);
108 static void nfe_miibus_statchg(device_t);
110 #ifdef DEVICE_POLLING
111 static void nfe_poll(struct ifnet *, enum poll_cmd, int);
113 static void nfe_intr(void *);
114 static int nfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
115 static void nfe_rxeof(struct nfe_softc *);
116 static void nfe_txeof(struct nfe_softc *);
117 static int nfe_encap(struct nfe_softc *, struct nfe_tx_ring *,
119 static void nfe_start(struct ifnet *);
120 static void nfe_watchdog(struct ifnet *);
121 static void nfe_init(void *);
122 static void nfe_stop(struct nfe_softc *);
123 static struct nfe_jbuf *nfe_jalloc(struct nfe_softc *);
124 static void nfe_jfree(void *);
125 static void nfe_jref(void *);
126 static int nfe_jpool_alloc(struct nfe_softc *, struct nfe_rx_ring *);
127 static void nfe_jpool_free(struct nfe_softc *, struct nfe_rx_ring *);
128 static int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
129 static void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
130 static int nfe_init_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
131 static void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
132 static int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
133 static void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
134 static int nfe_init_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
135 static void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
136 static int nfe_ifmedia_upd(struct ifnet *);
137 static void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
138 static void nfe_setmulti(struct nfe_softc *);
139 static void nfe_get_macaddr(struct nfe_softc *, uint8_t *);
140 static void nfe_set_macaddr(struct nfe_softc *, const uint8_t *);
141 static void nfe_tick(void *);
142 static void nfe_ring_dma_addr(void *, bus_dma_segment_t *, int, int);
143 static void nfe_buf_dma_addr(void *, bus_dma_segment_t *, int, bus_size_t,
145 static void nfe_set_paddr_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
147 static void nfe_set_ready_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
149 static int nfe_newbuf_std(struct nfe_softc *, struct nfe_rx_ring *, int,
151 static int nfe_newbuf_jumbo(struct nfe_softc *, struct nfe_rx_ring *, int,
154 static int nfe_sysctl_imtime(SYSCTL_HANDLER_ARGS);
159 static int nfe_debug = 0;
160 static int nfe_rx_ring_count = NFE_RX_RING_DEF_COUNT;
161 static int nfe_imtime = -1;
163 TUNABLE_INT("hw.nfe.rx_ring_count", &nfe_rx_ring_count);
164 TUNABLE_INT("hw.nfe.imtime", &nfe_imtime);
165 TUNABLE_INT("hw.nfe.debug", &nfe_debug);
167 #define DPRINTF(sc, fmt, ...) do { \
168 if ((sc)->sc_debug) { \
169 if_printf(&(sc)->arpcom.ac_if, \
174 #define DPRINTFN(sc, lv, fmt, ...) do { \
175 if ((sc)->sc_debug >= (lv)) { \
176 if_printf(&(sc)->arpcom.ac_if, \
181 #else /* !NFE_DEBUG */
183 #define DPRINTF(sc, fmt, ...)
184 #define DPRINTFN(sc, lv, fmt, ...)
186 #endif /* NFE_DEBUG */
190 bus_dma_segment_t *segs;
193 static const struct nfe_dev {
198 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN,
199 "NVIDIA nForce Fast Ethernet" },
201 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN,
202 "NVIDIA nForce2 Fast Ethernet" },
204 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1,
205 "NVIDIA nForce3 Gigabit Ethernet" },
207 /* XXX TGEN the next chip can also be found in the nForce2 Ultra 400Gb
208 chipset, and possibly also the 400R; it might be both nForce2- and
209 nForce3-based boards can use the same MCPs (= southbridges) */
210 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2,
211 "NVIDIA nForce3 Gigabit Ethernet" },
213 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3,
214 "NVIDIA nForce3 Gigabit Ethernet" },
216 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4,
217 "NVIDIA nForce3 Gigabit Ethernet" },
219 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5,
220 "NVIDIA nForce3 Gigabit Ethernet" },
222 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1,
223 "NVIDIA CK804 Gigabit Ethernet" },
225 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2,
226 "NVIDIA CK804 Gigabit Ethernet" },
228 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1,
229 "NVIDIA MCP04 Gigabit Ethernet" },
231 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2,
232 "NVIDIA MCP04 Gigabit Ethernet" },
234 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1,
235 "NVIDIA MCP51 Gigabit Ethernet" },
237 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2,
238 "NVIDIA MCP51 Gigabit Ethernet" },
240 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1,
241 "NVIDIA MCP55 Gigabit Ethernet" },
243 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2,
244 "NVIDIA MCP55 Gigabit Ethernet" },
246 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1,
247 "NVIDIA MCP61 Gigabit Ethernet" },
249 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2,
250 "NVIDIA MCP61 Gigabit Ethernet" },
252 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3,
253 "NVIDIA MCP61 Gigabit Ethernet" },
255 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4,
256 "NVIDIA MCP61 Gigabit Ethernet" },
258 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1,
259 "NVIDIA MCP65 Gigabit Ethernet" },
261 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2,
262 "NVIDIA MCP65 Gigabit Ethernet" },
264 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3,
265 "NVIDIA MCP65 Gigabit Ethernet" },
267 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4,
268 "NVIDIA MCP65 Gigabit Ethernet" },
270 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1,
271 "NVIDIA MCP67 Gigabit Ethernet" },
273 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2,
274 "NVIDIA MCP67 Gigabit Ethernet" },
276 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3,
277 "NVIDIA MCP67 Gigabit Ethernet" },
279 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4,
280 "NVIDIA MCP67 Gigabit Ethernet" }
283 static device_method_t nfe_methods[] = {
284 /* Device interface */
285 DEVMETHOD(device_probe, nfe_probe),
286 DEVMETHOD(device_attach, nfe_attach),
287 DEVMETHOD(device_detach, nfe_detach),
288 DEVMETHOD(device_suspend, nfe_suspend),
289 DEVMETHOD(device_resume, nfe_resume),
290 DEVMETHOD(device_shutdown, nfe_shutdown),
293 DEVMETHOD(bus_print_child, bus_generic_print_child),
294 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
297 DEVMETHOD(miibus_readreg, nfe_miibus_readreg),
298 DEVMETHOD(miibus_writereg, nfe_miibus_writereg),
299 DEVMETHOD(miibus_statchg, nfe_miibus_statchg),
304 static driver_t nfe_driver = {
307 sizeof(struct nfe_softc)
310 static devclass_t nfe_devclass;
312 DECLARE_DUMMY_MODULE(if_nfe);
313 MODULE_DEPEND(if_nfe, miibus, 1, 1, 1);
314 DRIVER_MODULE(if_nfe, pci, nfe_driver, nfe_devclass, 0, 0);
315 DRIVER_MODULE(miibus, nfe, miibus_driver, miibus_devclass, 0, 0);
318 nfe_probe(device_t dev)
320 const struct nfe_dev *n;
323 vid = pci_get_vendor(dev);
324 did = pci_get_device(dev);
325 for (n = nfe_devices; n->desc != NULL; ++n) {
326 if (vid == n->vid && did == n->did) {
327 struct nfe_softc *sc = device_get_softc(dev);
330 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2:
331 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3:
332 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4:
333 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5:
334 sc->sc_flags = NFE_JUMBO_SUP |
337 case PCI_PRODUCT_NVIDIA_MCP51_LAN1:
338 case PCI_PRODUCT_NVIDIA_MCP51_LAN2:
339 case PCI_PRODUCT_NVIDIA_MCP61_LAN1:
340 case PCI_PRODUCT_NVIDIA_MCP61_LAN2:
341 case PCI_PRODUCT_NVIDIA_MCP61_LAN3:
342 case PCI_PRODUCT_NVIDIA_MCP61_LAN4:
343 case PCI_PRODUCT_NVIDIA_MCP67_LAN1:
344 case PCI_PRODUCT_NVIDIA_MCP67_LAN2:
345 case PCI_PRODUCT_NVIDIA_MCP67_LAN3:
346 case PCI_PRODUCT_NVIDIA_MCP67_LAN4:
347 sc->sc_flags = NFE_40BIT_ADDR;
349 case PCI_PRODUCT_NVIDIA_CK804_LAN1:
350 case PCI_PRODUCT_NVIDIA_CK804_LAN2:
351 case PCI_PRODUCT_NVIDIA_MCP04_LAN1:
352 case PCI_PRODUCT_NVIDIA_MCP04_LAN2:
353 case PCI_PRODUCT_NVIDIA_MCP65_LAN1:
354 case PCI_PRODUCT_NVIDIA_MCP65_LAN2:
355 case PCI_PRODUCT_NVIDIA_MCP65_LAN3:
356 case PCI_PRODUCT_NVIDIA_MCP65_LAN4:
357 sc->sc_flags = NFE_JUMBO_SUP |
361 case PCI_PRODUCT_NVIDIA_MCP55_LAN1:
362 case PCI_PRODUCT_NVIDIA_MCP55_LAN2:
363 sc->sc_flags = NFE_JUMBO_SUP |
370 device_set_desc(dev, n->desc);
371 device_set_async_attach(dev, TRUE);
379 nfe_attach(device_t dev)
381 struct nfe_softc *sc = device_get_softc(dev);
382 struct ifnet *ifp = &sc->arpcom.ac_if;
383 uint8_t eaddr[ETHER_ADDR_LEN];
386 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
387 lwkt_serialize_init(&sc->sc_jbuf_serializer);
390 * Initialize sysctl variables
392 sc->sc_imtime = nfe_imtime;
393 sc->sc_irq_enable = NFE_IRQ_ENABLE(sc);
394 sc->sc_rx_ring_count = nfe_rx_ring_count;
395 sc->sc_debug = nfe_debug;
397 sc->sc_mem_rid = PCIR_BAR(0);
400 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
403 mem = pci_read_config(dev, sc->sc_mem_rid, 4);
404 irq = pci_read_config(dev, PCIR_INTLINE, 4);
406 device_printf(dev, "chip is in D%d power mode "
407 "-- setting to D0\n", pci_get_powerstate(dev));
409 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
411 pci_write_config(dev, sc->sc_mem_rid, mem, 4);
412 pci_write_config(dev, PCIR_INTLINE, irq, 4);
414 #endif /* !BURN_BRIDGE */
416 /* Enable bus mastering */
417 pci_enable_busmaster(dev);
419 /* Allocate IO memory */
420 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
421 &sc->sc_mem_rid, RF_ACTIVE);
422 if (sc->sc_mem_res == NULL) {
423 device_printf(dev, "cound not allocate io memory\n");
426 sc->sc_memh = rman_get_bushandle(sc->sc_mem_res);
427 sc->sc_memt = rman_get_bustag(sc->sc_mem_res);
431 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
433 RF_SHAREABLE | RF_ACTIVE);
434 if (sc->sc_irq_res == NULL) {
435 device_printf(dev, "could not allocate irq\n");
440 nfe_get_macaddr(sc, eaddr);
443 * Allocate Tx and Rx rings.
445 error = nfe_alloc_tx_ring(sc, &sc->txq);
447 device_printf(dev, "could not allocate Tx ring\n");
451 error = nfe_alloc_rx_ring(sc, &sc->rxq);
453 device_printf(dev, "could not allocate Rx ring\n");
460 sysctl_ctx_init(&sc->sc_sysctl_ctx);
461 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
462 SYSCTL_STATIC_CHILDREN(_hw),
464 device_get_nameunit(dev),
466 if (sc->sc_sysctl_tree == NULL) {
467 device_printf(dev, "can't add sysctl node\n");
471 SYSCTL_ADD_PROC(&sc->sc_sysctl_ctx,
472 SYSCTL_CHILDREN(sc->sc_sysctl_tree),
473 OID_AUTO, "imtimer", CTLTYPE_INT | CTLFLAG_RW,
474 sc, 0, nfe_sysctl_imtime, "I",
475 "Interrupt moderation time (usec). "
476 "-1 to disable interrupt moderation.");
477 SYSCTL_ADD_INT(NULL, SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
478 "rx_ring_count", CTLFLAG_RD, &sc->sc_rx_ring_count,
480 SYSCTL_ADD_INT(NULL, SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
481 "debug", CTLFLAG_RW, &sc->sc_debug,
482 0, "control debugging printfs");
484 error = mii_phy_probe(dev, &sc->sc_miibus, nfe_ifmedia_upd,
487 device_printf(dev, "MII without any phy\n");
492 ifp->if_mtu = ETHERMTU;
493 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
494 ifp->if_ioctl = nfe_ioctl;
495 ifp->if_start = nfe_start;
496 #ifdef DEVICE_POLLING
497 ifp->if_poll = nfe_poll;
499 ifp->if_watchdog = nfe_watchdog;
500 ifp->if_init = nfe_init;
501 ifq_set_maxlen(&ifp->if_snd, NFE_IFQ_MAXLEN);
502 ifq_set_ready(&ifp->if_snd);
504 ifp->if_capabilities = IFCAP_VLAN_MTU;
506 if (sc->sc_flags & NFE_HW_VLAN)
507 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
510 if (sc->sc_flags & NFE_HW_CSUM) {
511 ifp->if_capabilities |= IFCAP_HWCSUM;
512 ifp->if_hwassist = NFE_CSUM_FEATURES;
515 sc->sc_flags &= ~NFE_HW_CSUM;
517 ifp->if_capenable = ifp->if_capabilities;
519 callout_init(&sc->sc_tick_ch);
521 ether_ifattach(ifp, eaddr, NULL);
523 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, nfe_intr, sc,
524 &sc->sc_ih, ifp->if_serializer);
526 device_printf(dev, "could not setup intr\n");
531 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->sc_irq_res));
532 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
541 nfe_detach(device_t dev)
543 struct nfe_softc *sc = device_get_softc(dev);
545 if (device_is_attached(dev)) {
546 struct ifnet *ifp = &sc->arpcom.ac_if;
548 lwkt_serialize_enter(ifp->if_serializer);
550 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_ih);
551 lwkt_serialize_exit(ifp->if_serializer);
556 if (sc->sc_miibus != NULL)
557 device_delete_child(dev, sc->sc_miibus);
558 bus_generic_detach(dev);
560 if (sc->sc_sysctl_tree != NULL)
561 sysctl_ctx_free(&sc->sc_sysctl_ctx);
563 if (sc->sc_irq_res != NULL) {
564 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
568 if (sc->sc_mem_res != NULL) {
569 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
573 nfe_free_tx_ring(sc, &sc->txq);
574 nfe_free_rx_ring(sc, &sc->rxq);
580 nfe_shutdown(device_t dev)
582 struct nfe_softc *sc = device_get_softc(dev);
583 struct ifnet *ifp = &sc->arpcom.ac_if;
585 lwkt_serialize_enter(ifp->if_serializer);
587 lwkt_serialize_exit(ifp->if_serializer);
591 nfe_suspend(device_t dev)
593 struct nfe_softc *sc = device_get_softc(dev);
594 struct ifnet *ifp = &sc->arpcom.ac_if;
596 lwkt_serialize_enter(ifp->if_serializer);
598 lwkt_serialize_exit(ifp->if_serializer);
604 nfe_resume(device_t dev)
606 struct nfe_softc *sc = device_get_softc(dev);
607 struct ifnet *ifp = &sc->arpcom.ac_if;
609 lwkt_serialize_enter(ifp->if_serializer);
610 if (ifp->if_flags & IFF_UP)
612 lwkt_serialize_exit(ifp->if_serializer);
618 nfe_miibus_statchg(device_t dev)
620 struct nfe_softc *sc = device_get_softc(dev);
621 struct mii_data *mii = device_get_softc(sc->sc_miibus);
622 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET;
624 phy = NFE_READ(sc, NFE_PHY_IFACE);
625 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T);
627 seed = NFE_READ(sc, NFE_RNDSEED);
628 seed &= ~NFE_SEED_MASK;
630 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) {
631 phy |= NFE_PHY_HDX; /* half-duplex */
632 misc |= NFE_MISC1_HDX;
635 switch (IFM_SUBTYPE(mii->mii_media_active)) {
636 case IFM_1000_T: /* full-duplex only */
637 link |= NFE_MEDIA_1000T;
638 seed |= NFE_SEED_1000T;
639 phy |= NFE_PHY_1000T;
642 link |= NFE_MEDIA_100TX;
643 seed |= NFE_SEED_100TX;
644 phy |= NFE_PHY_100TX;
647 link |= NFE_MEDIA_10T;
648 seed |= NFE_SEED_10T;
652 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */
654 NFE_WRITE(sc, NFE_PHY_IFACE, phy);
655 NFE_WRITE(sc, NFE_MISC1, misc);
656 NFE_WRITE(sc, NFE_LINKSPEED, link);
660 nfe_miibus_readreg(device_t dev, int phy, int reg)
662 struct nfe_softc *sc = device_get_softc(dev);
666 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
668 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
669 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
673 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg);
675 for (ntries = 0; ntries < 1000; ntries++) {
677 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
680 if (ntries == 1000) {
681 DPRINTFN(sc, 2, "timeout waiting for PHY %s\n", "");
685 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) {
686 DPRINTFN(sc, 2, "could not read PHY %s\n", "");
690 val = NFE_READ(sc, NFE_PHY_DATA);
691 if (val != 0xffffffff && val != 0)
692 sc->mii_phyaddr = phy;
694 DPRINTFN(sc, 2, "mii read phy %d reg 0x%x ret 0x%x\n", phy, reg, val);
700 nfe_miibus_writereg(device_t dev, int phy, int reg, int val)
702 struct nfe_softc *sc = device_get_softc(dev);
706 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
708 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
709 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
713 NFE_WRITE(sc, NFE_PHY_DATA, val);
714 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg;
715 NFE_WRITE(sc, NFE_PHY_CTL, ctl);
717 for (ntries = 0; ntries < 1000; ntries++) {
719 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
725 DPRINTFN(sc, 2, "could not write to PHY %s\n", "");
729 #ifdef DEVICE_POLLING
732 nfe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
734 struct nfe_softc *sc = ifp->if_softc;
736 ASSERT_SERIALIZED(ifp->if_serializer);
740 /* Disable interrupts */
741 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
743 case POLL_DEREGISTER:
744 /* enable interrupts */
745 NFE_WRITE(sc, NFE_IRQ_MASK, sc->sc_irq_enable);
747 case POLL_AND_CHECK_STATUS:
750 if (ifp->if_flags & IFF_RUNNING) {
763 struct nfe_softc *sc = arg;
764 struct ifnet *ifp = &sc->arpcom.ac_if;
767 r = NFE_READ(sc, NFE_IRQ_STATUS);
769 return; /* not for us */
770 NFE_WRITE(sc, NFE_IRQ_STATUS, r);
772 DPRINTFN(sc, 5, "%s: interrupt register %x\n", __func__, r);
774 if (r & NFE_IRQ_LINK) {
775 NFE_READ(sc, NFE_PHY_STATUS);
776 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
777 DPRINTF(sc, "link state changed %s\n", "");
780 if (ifp->if_flags & IFF_RUNNING) {
790 nfe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
792 struct nfe_softc *sc = ifp->if_softc;
793 struct ifreq *ifr = (struct ifreq *)data;
794 struct mii_data *mii;
799 if (((sc->sc_flags & NFE_JUMBO_SUP) &&
800 ifr->ifr_mtu > NFE_JUMBO_MTU) ||
801 ((sc->sc_flags & NFE_JUMBO_SUP) == 0 &&
802 ifr->ifr_mtu > ETHERMTU)) {
804 } else if (ifp->if_mtu != ifr->ifr_mtu) {
805 ifp->if_mtu = ifr->ifr_mtu;
810 if (ifp->if_flags & IFF_UP) {
812 * If only the PROMISC or ALLMULTI flag changes, then
813 * don't do a full re-init of the chip, just update
816 if ((ifp->if_flags & IFF_RUNNING) &&
817 ((ifp->if_flags ^ sc->sc_if_flags) &
818 (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
821 if (!(ifp->if_flags & IFF_RUNNING))
825 if (ifp->if_flags & IFF_RUNNING)
828 sc->sc_if_flags = ifp->if_flags;
832 if (ifp->if_flags & IFF_RUNNING)
837 mii = device_get_softc(sc->sc_miibus);
838 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
841 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) & IFCAP_HWCSUM;
842 if (mask && (ifp->if_capabilities & IFCAP_HWCSUM)) {
843 ifp->if_capenable ^= mask;
844 if (IFCAP_TXCSUM & ifp->if_capenable)
845 ifp->if_hwassist = NFE_CSUM_FEATURES;
847 ifp->if_hwassist = 0;
849 if (ifp->if_flags & IFF_RUNNING)
854 error = ether_ioctl(ifp, cmd, data);
861 nfe_rxeof(struct nfe_softc *sc)
863 struct ifnet *ifp = &sc->arpcom.ac_if;
864 struct nfe_rx_ring *ring = &sc->rxq;
868 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_POSTREAD);
871 struct nfe_rx_data *data = &ring->data[ring->cur];
876 if (sc->sc_flags & NFE_40BIT_ADDR) {
877 struct nfe_desc64 *desc64 = &ring->desc64[ring->cur];
879 flags = le16toh(desc64->flags);
880 len = le16toh(desc64->length) & 0x3fff;
882 struct nfe_desc32 *desc32 = &ring->desc32[ring->cur];
884 flags = le16toh(desc32->flags);
885 len = le16toh(desc32->length) & 0x3fff;
888 if (flags & NFE_RX_READY)
893 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
894 if (!(flags & NFE_RX_VALID_V1))
897 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) {
898 flags &= ~NFE_RX_ERROR;
899 len--; /* fix buffer length */
902 if (!(flags & NFE_RX_VALID_V2))
905 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) {
906 flags &= ~NFE_RX_ERROR;
907 len--; /* fix buffer length */
911 if (flags & NFE_RX_ERROR) {
918 if (sc->sc_flags & NFE_USE_JUMBO)
919 error = nfe_newbuf_jumbo(sc, ring, ring->cur, 0);
921 error = nfe_newbuf_std(sc, ring, ring->cur, 0);
928 m->m_pkthdr.len = m->m_len = len;
929 m->m_pkthdr.rcvif = ifp;
931 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
932 (flags & NFE_RX_CSUMOK)) {
933 if (flags & NFE_RX_IP_CSUMOK_V2) {
934 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
939 (NFE_RX_UDP_CSUMOK_V2 | NFE_RX_TCP_CSUMOK_V2)) {
940 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
942 CSUM_FRAG_NOT_CHECKED;
943 m->m_pkthdr.csum_data = 0xffff;
948 ifp->if_input(ifp, m);
950 nfe_set_ready_rxdesc(sc, ring, ring->cur);
951 sc->rxq.cur = (sc->rxq.cur + 1) % sc->sc_rx_ring_count;
955 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
959 nfe_txeof(struct nfe_softc *sc)
961 struct ifnet *ifp = &sc->arpcom.ac_if;
962 struct nfe_tx_ring *ring = &sc->txq;
963 struct nfe_tx_data *data = NULL;
965 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_POSTREAD);
966 while (ring->next != ring->cur) {
969 if (sc->sc_flags & NFE_40BIT_ADDR)
970 flags = le16toh(ring->desc64[ring->next].flags);
972 flags = le16toh(ring->desc32[ring->next].flags);
974 if (flags & NFE_TX_VALID)
977 data = &ring->data[ring->next];
979 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
980 if (!(flags & NFE_TX_LASTFRAG_V1) && data->m == NULL)
983 if ((flags & NFE_TX_ERROR_V1) != 0) {
984 if_printf(ifp, "tx v1 error 0x%4b\n", flags,
991 if (!(flags & NFE_TX_LASTFRAG_V2) && data->m == NULL)
994 if ((flags & NFE_TX_ERROR_V2) != 0) {
995 if_printf(ifp, "tx v2 error 0x%4b\n", flags,
1003 if (data->m == NULL) { /* should not get there */
1005 "last fragment bit w/o associated mbuf!\n");
1009 /* last fragment of the mbuf chain transmitted */
1010 bus_dmamap_sync(ring->data_tag, data->map,
1011 BUS_DMASYNC_POSTWRITE);
1012 bus_dmamap_unload(ring->data_tag, data->map);
1019 KKASSERT(ring->queued >= 0);
1020 ring->next = (ring->next + 1) % NFE_TX_RING_COUNT;
1023 if (data != NULL) { /* at least one slot freed */
1024 ifp->if_flags &= ~IFF_OACTIVE;
1030 nfe_encap(struct nfe_softc *sc, struct nfe_tx_ring *ring, struct mbuf *m0)
1032 struct nfe_dma_ctx ctx;
1033 bus_dma_segment_t segs[NFE_MAX_SCATTER];
1034 struct nfe_tx_data *data, *data_map;
1036 struct nfe_desc64 *desc64 = NULL;
1037 struct nfe_desc32 *desc32 = NULL;
1042 data = &ring->data[ring->cur];
1044 data_map = data; /* Remember who owns the DMA map */
1046 ctx.nsegs = NFE_MAX_SCATTER;
1048 error = bus_dmamap_load_mbuf(ring->data_tag, map, m0,
1049 nfe_buf_dma_addr, &ctx, BUS_DMA_NOWAIT);
1050 if (error && error != EFBIG) {
1051 if_printf(&sc->arpcom.ac_if, "could not map TX mbuf\n");
1055 if (error) { /* error == EFBIG */
1058 m_new = m_defrag(m0, MB_DONTWAIT);
1059 if (m_new == NULL) {
1060 if_printf(&sc->arpcom.ac_if,
1061 "could not defrag TX mbuf\n");
1068 ctx.nsegs = NFE_MAX_SCATTER;
1070 error = bus_dmamap_load_mbuf(ring->data_tag, map, m0,
1071 nfe_buf_dma_addr, &ctx,
1074 if_printf(&sc->arpcom.ac_if,
1075 "could not map defraged TX mbuf\n");
1082 if (ring->queued + ctx.nsegs >= NFE_TX_RING_COUNT - 1) {
1083 bus_dmamap_unload(ring->data_tag, map);
1088 /* setup h/w VLAN tagging */
1089 if (m0->m_flags & M_VLANTAG)
1090 vtag = m0->m_pkthdr.ether_vlantag;
1092 if (sc->arpcom.ac_if.if_capenable & IFCAP_TXCSUM) {
1093 if (m0->m_pkthdr.csum_flags & CSUM_IP)
1094 flags |= NFE_TX_IP_CSUM;
1095 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
1096 flags |= NFE_TX_TCP_CSUM;
1100 * XXX urm. somebody is unaware of how hardware works. You
1101 * absolutely CANNOT set NFE_TX_VALID on the next descriptor in
1102 * the ring until the entire chain is actually *VALID*. Otherwise
1103 * the hardware may encounter a partially initialized chain that
1104 * is marked as being ready to go when it in fact is not ready to
1108 for (i = 0; i < ctx.nsegs; i++) {
1109 j = (ring->cur + i) % NFE_TX_RING_COUNT;
1110 data = &ring->data[j];
1112 if (sc->sc_flags & NFE_40BIT_ADDR) {
1113 desc64 = &ring->desc64[j];
1114 #if defined(__LP64__)
1115 desc64->physaddr[0] =
1116 htole32(segs[i].ds_addr >> 32);
1118 desc64->physaddr[1] =
1119 htole32(segs[i].ds_addr & 0xffffffff);
1120 desc64->length = htole16(segs[i].ds_len - 1);
1121 desc64->vtag = htole32(vtag);
1122 desc64->flags = htole16(flags);
1124 desc32 = &ring->desc32[j];
1125 desc32->physaddr = htole32(segs[i].ds_addr);
1126 desc32->length = htole16(segs[i].ds_len - 1);
1127 desc32->flags = htole16(flags);
1130 /* csum flags and vtag belong to the first fragment only */
1131 flags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_CSUM);
1135 KKASSERT(ring->queued <= NFE_TX_RING_COUNT);
1138 /* the whole mbuf chain has been DMA mapped, fix last descriptor */
1139 if (sc->sc_flags & NFE_40BIT_ADDR) {
1140 desc64->flags |= htole16(NFE_TX_LASTFRAG_V2);
1142 if (sc->sc_flags & NFE_JUMBO_SUP)
1143 flags = NFE_TX_LASTFRAG_V2;
1145 flags = NFE_TX_LASTFRAG_V1;
1146 desc32->flags |= htole16(flags);
1150 * Set NFE_TX_VALID backwards so the hardware doesn't see the
1151 * whole mess until the first descriptor in the map is flagged.
1153 for (i = ctx.nsegs - 1; i >= 0; --i) {
1154 j = (ring->cur + i) % NFE_TX_RING_COUNT;
1155 if (sc->sc_flags & NFE_40BIT_ADDR) {
1156 desc64 = &ring->desc64[j];
1157 desc64->flags |= htole16(NFE_TX_VALID);
1159 desc32 = &ring->desc32[j];
1160 desc32->flags |= htole16(NFE_TX_VALID);
1163 ring->cur = (ring->cur + ctx.nsegs) % NFE_TX_RING_COUNT;
1165 /* Exchange DMA map */
1166 data_map->map = data->map;
1170 bus_dmamap_sync(ring->data_tag, map, BUS_DMASYNC_PREWRITE);
1178 nfe_start(struct ifnet *ifp)
1180 struct nfe_softc *sc = ifp->if_softc;
1181 struct nfe_tx_ring *ring = &sc->txq;
1185 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
1189 m0 = ifq_dequeue(&ifp->if_snd, NULL);
1193 ETHER_BPF_MTAP(ifp, m0);
1195 if (nfe_encap(sc, ring, m0) != 0) {
1196 ifp->if_flags |= IFF_OACTIVE;
1203 * `m0' may be freed in nfe_encap(), so
1204 * it should not be touched any more.
1207 if (count == 0) /* nothing sent */
1210 /* Sync TX descriptor ring */
1211 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1214 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl);
1217 * Set a timeout in case the chip goes out to lunch.
1223 nfe_watchdog(struct ifnet *ifp)
1225 struct nfe_softc *sc = ifp->if_softc;
1227 if (ifp->if_flags & IFF_RUNNING) {
1228 if_printf(ifp, "watchdog timeout - lost interrupt recovered\n");
1233 if_printf(ifp, "watchdog timeout\n");
1235 nfe_init(ifp->if_softc);
1243 struct nfe_softc *sc = xsc;
1244 struct ifnet *ifp = &sc->arpcom.ac_if;
1252 * Switching between jumbo frames and normal frames should
1253 * be done _after_ nfe_stop() but _before_ nfe_init_rx_ring().
1255 if (ifp->if_mtu > ETHERMTU) {
1256 sc->sc_flags |= NFE_USE_JUMBO;
1257 sc->rxq.bufsz = NFE_JBYTES;
1259 if_printf(ifp, "use jumbo frames\n");
1261 sc->sc_flags &= ~NFE_USE_JUMBO;
1262 sc->rxq.bufsz = MCLBYTES;
1264 if_printf(ifp, "use non-jumbo frames\n");
1267 error = nfe_init_tx_ring(sc, &sc->txq);
1273 error = nfe_init_rx_ring(sc, &sc->rxq);
1279 NFE_WRITE(sc, NFE_TX_UNK, 0);
1280 NFE_WRITE(sc, NFE_STATUS, 0);
1282 sc->rxtxctl = NFE_RXTX_BIT2;
1283 if (sc->sc_flags & NFE_40BIT_ADDR)
1284 sc->rxtxctl |= NFE_RXTX_V3MAGIC;
1285 else if (sc->sc_flags & NFE_JUMBO_SUP)
1286 sc->rxtxctl |= NFE_RXTX_V2MAGIC;
1288 if (ifp->if_capenable & IFCAP_RXCSUM)
1289 sc->rxtxctl |= NFE_RXTX_RXCSUM;
1292 * Although the adapter is capable of stripping VLAN tags from received
1293 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on
1294 * purpose. This will be done in software by our network stack.
1296 if (sc->sc_flags & NFE_HW_VLAN)
1297 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT;
1299 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl);
1301 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1303 if (sc->sc_flags & NFE_HW_VLAN)
1304 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE);
1306 NFE_WRITE(sc, NFE_SETUP_R6, 0);
1308 /* set MAC address */
1309 nfe_set_macaddr(sc, sc->arpcom.ac_enaddr);
1311 /* tell MAC where rings are in memory */
1313 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32);
1315 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff);
1317 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32);
1319 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff);
1321 NFE_WRITE(sc, NFE_RING_SIZE,
1322 (sc->sc_rx_ring_count - 1) << 16 |
1323 (NFE_TX_RING_COUNT - 1));
1325 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz);
1327 /* force MAC to wakeup */
1328 tmp = NFE_READ(sc, NFE_PWR_STATE);
1329 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP);
1331 tmp = NFE_READ(sc, NFE_PWR_STATE);
1332 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID);
1335 * NFE_IMTIMER generates a periodic interrupt via NFE_IRQ_TIMER.
1336 * It is unclear how wide the timer is. Base programming does
1337 * not seem to effect NFE_IRQ_TX_DONE or NFE_IRQ_RX_DONE so
1338 * we don't get any interrupt moderation. TX moderation is
1339 * possible by using the timer interrupt instead of TX_DONE.
1341 * It is unclear whether there are other bits that can be
1342 * set to make the NFE device actually do interrupt moderation
1345 * For now set a 128uS interval as a placemark, but don't use
1348 if (sc->sc_imtime < 0)
1349 NFE_WRITE(sc, NFE_IMTIMER, NFE_IMTIME_DEFAULT);
1351 NFE_WRITE(sc, NFE_IMTIMER, NFE_IMTIME(sc->sc_imtime));
1353 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC);
1354 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC);
1355 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC);
1357 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */
1358 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC);
1360 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC);
1361 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_MAGIC);
1363 sc->rxtxctl &= ~NFE_RXTX_BIT2;
1364 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1366 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl);
1371 nfe_ifmedia_upd(ifp);
1374 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START);
1377 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START);
1379 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
1381 #ifdef DEVICE_POLLING
1382 if ((ifp->if_flags & IFF_POLLING) == 0)
1384 /* enable interrupts */
1385 NFE_WRITE(sc, NFE_IRQ_MASK, sc->sc_irq_enable);
1387 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
1389 ifp->if_flags |= IFF_RUNNING;
1390 ifp->if_flags &= ~IFF_OACTIVE;
1393 * If we had stuff in the tx ring before its all cleaned out now
1394 * so we are not going to get an interrupt, jump-start any pending
1401 nfe_stop(struct nfe_softc *sc)
1403 struct ifnet *ifp = &sc->arpcom.ac_if;
1405 callout_stop(&sc->sc_tick_ch);
1408 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1411 * Are NFE_TX_CTL and NFE_RX_CTL polled by the chip microcontroller
1412 * or do they directly reset/terminate the DMA hardware? Nobody
1417 * (1) Delay before zeroing out NFE_TX_CTL. This seems to help a
1418 * watchdog timeout that occurs after a stop/init sequence. I am
1419 * theorizing that a TX KICK occuring just prior to a reinit (e.g.
1420 * due to dhclient) is queueing an interrupt to the microcontroller
1421 * which gets delayed until after we clear the control registers
1422 * down below, resulting in mass confusion. TX KICK is clearly
1423 * hardware aided whereas the other bits in the control register
1424 * are more likely to be polled by the microcontroller.
1426 * (2) Delay after zeroing out TX and RX CTL registers, under the
1427 * assumption that primary DMA is initiated and terminated by
1428 * the microcontroller and not hardware (and anyway, one can hardly
1429 * expect the DMA engine to just instantly stop!). We don't want
1430 * to rip the rings out from under it before it has had a chance to
1436 NFE_WRITE(sc, NFE_TX_CTL, 0);
1439 NFE_WRITE(sc, NFE_RX_CTL, 0);
1441 /* Disable interrupts */
1442 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
1446 /* Reset Tx and Rx rings */
1447 nfe_reset_tx_ring(sc, &sc->txq);
1448 nfe_reset_rx_ring(sc, &sc->rxq);
1452 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1454 int i, j, error, descsize;
1457 if (sc->sc_flags & NFE_40BIT_ADDR) {
1458 desc = (void **)&ring->desc64;
1459 descsize = sizeof(struct nfe_desc64);
1461 desc = (void **)&ring->desc32;
1462 descsize = sizeof(struct nfe_desc32);
1465 ring->jbuf = kmalloc(sizeof(struct nfe_jbuf) * NFE_JPOOL_COUNT,
1466 M_DEVBUF, M_WAITOK | M_ZERO);
1467 ring->data = kmalloc(sizeof(struct nfe_rx_data) * sc->sc_rx_ring_count,
1468 M_DEVBUF, M_WAITOK | M_ZERO);
1470 ring->bufsz = MCLBYTES;
1471 ring->cur = ring->next = 0;
1473 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1474 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1476 sc->sc_rx_ring_count * descsize, 1,
1477 sc->sc_rx_ring_count * descsize,
1480 if_printf(&sc->arpcom.ac_if,
1481 "could not create desc RX DMA tag\n");
1485 error = bus_dmamem_alloc(ring->tag, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1488 if_printf(&sc->arpcom.ac_if,
1489 "could not allocate RX desc DMA memory\n");
1490 bus_dma_tag_destroy(ring->tag);
1495 error = bus_dmamap_load(ring->tag, ring->map, *desc,
1496 sc->sc_rx_ring_count * descsize,
1497 nfe_ring_dma_addr, &ring->physaddr,
1500 if_printf(&sc->arpcom.ac_if,
1501 "could not load RX desc DMA map\n");
1502 bus_dmamem_free(ring->tag, *desc, ring->map);
1503 bus_dma_tag_destroy(ring->tag);
1508 if (sc->sc_flags & NFE_JUMBO_SUP) {
1509 error = nfe_jpool_alloc(sc, ring);
1511 if_printf(&sc->arpcom.ac_if,
1512 "could not allocate jumbo frames\n");
1517 error = bus_dma_tag_create(NULL, 1, 0,
1518 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1520 MCLBYTES, 1, MCLBYTES,
1521 0, &ring->data_tag);
1523 if_printf(&sc->arpcom.ac_if,
1524 "could not create RX mbuf DMA tag\n");
1528 /* Create a spare RX mbuf DMA map */
1529 error = bus_dmamap_create(ring->data_tag, 0, &ring->data_tmpmap);
1531 if_printf(&sc->arpcom.ac_if,
1532 "could not create spare RX mbuf DMA map\n");
1533 bus_dma_tag_destroy(ring->data_tag);
1534 ring->data_tag = NULL;
1538 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1539 error = bus_dmamap_create(ring->data_tag, 0,
1540 &ring->data[i].map);
1542 if_printf(&sc->arpcom.ac_if,
1543 "could not create %dth RX mbuf DMA mapn", i);
1549 for (j = 0; j < i; ++j)
1550 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
1551 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1552 bus_dma_tag_destroy(ring->data_tag);
1553 ring->data_tag = NULL;
1558 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1562 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1563 struct nfe_rx_data *data = &ring->data[i];
1565 if (data->m != NULL) {
1566 if ((sc->sc_flags & NFE_USE_JUMBO) == 0)
1567 bus_dmamap_unload(ring->data_tag, data->map);
1572 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1574 ring->cur = ring->next = 0;
1578 nfe_init_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1582 for (i = 0; i < sc->sc_rx_ring_count; ++i) {
1585 /* XXX should use a function pointer */
1586 if (sc->sc_flags & NFE_USE_JUMBO)
1587 error = nfe_newbuf_jumbo(sc, ring, i, 1);
1589 error = nfe_newbuf_std(sc, ring, i, 1);
1591 if_printf(&sc->arpcom.ac_if,
1592 "could not allocate RX buffer\n");
1596 nfe_set_ready_rxdesc(sc, ring, i);
1598 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1604 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1606 if (ring->data_tag != NULL) {
1607 struct nfe_rx_data *data;
1610 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1611 data = &ring->data[i];
1613 if (data->m != NULL) {
1614 bus_dmamap_unload(ring->data_tag, data->map);
1617 bus_dmamap_destroy(ring->data_tag, data->map);
1619 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1620 bus_dma_tag_destroy(ring->data_tag);
1623 nfe_jpool_free(sc, ring);
1625 if (ring->jbuf != NULL)
1626 kfree(ring->jbuf, M_DEVBUF);
1627 if (ring->data != NULL)
1628 kfree(ring->data, M_DEVBUF);
1630 if (ring->tag != NULL) {
1633 if (sc->sc_flags & NFE_40BIT_ADDR)
1634 desc = ring->desc64;
1636 desc = ring->desc32;
1638 bus_dmamap_unload(ring->tag, ring->map);
1639 bus_dmamem_free(ring->tag, desc, ring->map);
1640 bus_dma_tag_destroy(ring->tag);
1644 static struct nfe_jbuf *
1645 nfe_jalloc(struct nfe_softc *sc)
1647 struct ifnet *ifp = &sc->arpcom.ac_if;
1648 struct nfe_jbuf *jbuf;
1650 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1652 jbuf = SLIST_FIRST(&sc->rxq.jfreelist);
1654 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext);
1657 if_printf(ifp, "no free jumbo buffer\n");
1660 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1666 nfe_jfree(void *arg)
1668 struct nfe_jbuf *jbuf = arg;
1669 struct nfe_softc *sc = jbuf->sc;
1670 struct nfe_rx_ring *ring = jbuf->ring;
1672 if (&ring->jbuf[jbuf->slot] != jbuf)
1673 panic("%s: free wrong jumbo buffer\n", __func__);
1674 else if (jbuf->inuse == 0)
1675 panic("%s: jumbo buffer already freed\n", __func__);
1677 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1678 atomic_subtract_int(&jbuf->inuse, 1);
1679 if (jbuf->inuse == 0)
1680 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1681 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1687 struct nfe_jbuf *jbuf = arg;
1688 struct nfe_rx_ring *ring = jbuf->ring;
1690 if (&ring->jbuf[jbuf->slot] != jbuf)
1691 panic("%s: ref wrong jumbo buffer\n", __func__);
1692 else if (jbuf->inuse == 0)
1693 panic("%s: jumbo buffer already freed\n", __func__);
1695 atomic_add_int(&jbuf->inuse, 1);
1699 nfe_jpool_alloc(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1701 struct nfe_jbuf *jbuf;
1702 bus_addr_t physaddr;
1707 * Allocate a big chunk of DMA'able memory.
1709 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1710 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1712 NFE_JPOOL_SIZE, 1, NFE_JPOOL_SIZE,
1715 if_printf(&sc->arpcom.ac_if,
1716 "could not create jumbo DMA tag\n");
1720 error = bus_dmamem_alloc(ring->jtag, (void **)&ring->jpool,
1721 BUS_DMA_WAITOK, &ring->jmap);
1723 if_printf(&sc->arpcom.ac_if,
1724 "could not allocate jumbo DMA memory\n");
1725 bus_dma_tag_destroy(ring->jtag);
1730 error = bus_dmamap_load(ring->jtag, ring->jmap, ring->jpool,
1731 NFE_JPOOL_SIZE, nfe_ring_dma_addr, &physaddr,
1734 if_printf(&sc->arpcom.ac_if,
1735 "could not load jumbo DMA map\n");
1736 bus_dmamem_free(ring->jtag, ring->jpool, ring->jmap);
1737 bus_dma_tag_destroy(ring->jtag);
1742 /* ..and split it into 9KB chunks */
1743 SLIST_INIT(&ring->jfreelist);
1746 for (i = 0; i < NFE_JPOOL_COUNT; i++) {
1747 jbuf = &ring->jbuf[i];
1754 jbuf->physaddr = physaddr;
1756 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1759 physaddr += NFE_JBYTES;
1766 nfe_jpool_free(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1768 if (ring->jtag != NULL) {
1769 bus_dmamap_unload(ring->jtag, ring->jmap);
1770 bus_dmamem_free(ring->jtag, ring->jpool, ring->jmap);
1771 bus_dma_tag_destroy(ring->jtag);
1776 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1778 int i, j, error, descsize;
1781 if (sc->sc_flags & NFE_40BIT_ADDR) {
1782 desc = (void **)&ring->desc64;
1783 descsize = sizeof(struct nfe_desc64);
1785 desc = (void **)&ring->desc32;
1786 descsize = sizeof(struct nfe_desc32);
1790 ring->cur = ring->next = 0;
1792 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1793 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1795 NFE_TX_RING_COUNT * descsize, 1,
1796 NFE_TX_RING_COUNT * descsize,
1799 if_printf(&sc->arpcom.ac_if,
1800 "could not create TX desc DMA map\n");
1804 error = bus_dmamem_alloc(ring->tag, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1807 if_printf(&sc->arpcom.ac_if,
1808 "could not allocate TX desc DMA memory\n");
1809 bus_dma_tag_destroy(ring->tag);
1814 error = bus_dmamap_load(ring->tag, ring->map, *desc,
1815 NFE_TX_RING_COUNT * descsize,
1816 nfe_ring_dma_addr, &ring->physaddr,
1819 if_printf(&sc->arpcom.ac_if,
1820 "could not load TX desc DMA map\n");
1821 bus_dmamem_free(ring->tag, *desc, ring->map);
1822 bus_dma_tag_destroy(ring->tag);
1827 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1828 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1830 NFE_JBYTES * NFE_MAX_SCATTER,
1831 NFE_MAX_SCATTER, NFE_JBYTES,
1832 0, &ring->data_tag);
1834 if_printf(&sc->arpcom.ac_if,
1835 "could not create TX buf DMA tag\n");
1839 for (i = 0; i < NFE_TX_RING_COUNT; i++) {
1840 error = bus_dmamap_create(ring->data_tag, 0,
1841 &ring->data[i].map);
1843 if_printf(&sc->arpcom.ac_if,
1844 "could not create %dth TX buf DMA map\n", i);
1851 for (j = 0; j < i; ++j)
1852 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
1853 bus_dma_tag_destroy(ring->data_tag);
1854 ring->data_tag = NULL;
1859 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1863 for (i = 0; i < NFE_TX_RING_COUNT; i++) {
1864 struct nfe_tx_data *data = &ring->data[i];
1866 if (sc->sc_flags & NFE_40BIT_ADDR)
1867 ring->desc64[i].flags = 0;
1869 ring->desc32[i].flags = 0;
1871 if (data->m != NULL) {
1872 bus_dmamap_sync(ring->data_tag, data->map,
1873 BUS_DMASYNC_POSTWRITE);
1874 bus_dmamap_unload(ring->data_tag, data->map);
1879 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1882 ring->cur = ring->next = 0;
1886 nfe_init_tx_ring(struct nfe_softc *sc __unused,
1887 struct nfe_tx_ring *ring __unused)
1893 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1895 if (ring->data_tag != NULL) {
1896 struct nfe_tx_data *data;
1899 for (i = 0; i < NFE_TX_RING_COUNT; ++i) {
1900 data = &ring->data[i];
1902 if (data->m != NULL) {
1903 bus_dmamap_unload(ring->data_tag, data->map);
1906 bus_dmamap_destroy(ring->data_tag, data->map);
1909 bus_dma_tag_destroy(ring->data_tag);
1912 if (ring->tag != NULL) {
1915 if (sc->sc_flags & NFE_40BIT_ADDR)
1916 desc = ring->desc64;
1918 desc = ring->desc32;
1920 bus_dmamap_unload(ring->tag, ring->map);
1921 bus_dmamem_free(ring->tag, desc, ring->map);
1922 bus_dma_tag_destroy(ring->tag);
1927 nfe_ifmedia_upd(struct ifnet *ifp)
1929 struct nfe_softc *sc = ifp->if_softc;
1930 struct mii_data *mii = device_get_softc(sc->sc_miibus);
1932 if (mii->mii_instance != 0) {
1933 struct mii_softc *miisc;
1935 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1936 mii_phy_reset(miisc);
1944 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1946 struct nfe_softc *sc = ifp->if_softc;
1947 struct mii_data *mii = device_get_softc(sc->sc_miibus);
1950 ifmr->ifm_status = mii->mii_media_status;
1951 ifmr->ifm_active = mii->mii_media_active;
1955 nfe_setmulti(struct nfe_softc *sc)
1957 struct ifnet *ifp = &sc->arpcom.ac_if;
1958 struct ifmultiaddr *ifma;
1959 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN];
1960 uint32_t filter = NFE_RXFILTER_MAGIC;
1963 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
1964 bzero(addr, ETHER_ADDR_LEN);
1965 bzero(mask, ETHER_ADDR_LEN);
1969 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN);
1970 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN);
1972 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1975 if (ifma->ifma_addr->sa_family != AF_LINK)
1978 maddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
1979 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1980 addr[i] &= maddr[i];
1981 mask[i] &= ~maddr[i];
1985 for (i = 0; i < ETHER_ADDR_LEN; i++)
1989 addr[0] |= 0x01; /* make sure multicast bit is set */
1991 NFE_WRITE(sc, NFE_MULTIADDR_HI,
1992 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
1993 NFE_WRITE(sc, NFE_MULTIADDR_LO,
1994 addr[5] << 8 | addr[4]);
1995 NFE_WRITE(sc, NFE_MULTIMASK_HI,
1996 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]);
1997 NFE_WRITE(sc, NFE_MULTIMASK_LO,
1998 mask[5] << 8 | mask[4]);
2000 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M;
2001 NFE_WRITE(sc, NFE_RXFILTER, filter);
2005 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr)
2009 tmp = NFE_READ(sc, NFE_MACADDR_LO);
2010 addr[0] = (tmp >> 8) & 0xff;
2011 addr[1] = (tmp & 0xff);
2013 tmp = NFE_READ(sc, NFE_MACADDR_HI);
2014 addr[2] = (tmp >> 24) & 0xff;
2015 addr[3] = (tmp >> 16) & 0xff;
2016 addr[4] = (tmp >> 8) & 0xff;
2017 addr[5] = (tmp & 0xff);
2021 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr)
2023 NFE_WRITE(sc, NFE_MACADDR_LO,
2024 addr[5] << 8 | addr[4]);
2025 NFE_WRITE(sc, NFE_MACADDR_HI,
2026 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
2032 struct nfe_softc *sc = arg;
2033 struct ifnet *ifp = &sc->arpcom.ac_if;
2034 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2036 lwkt_serialize_enter(ifp->if_serializer);
2039 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
2041 lwkt_serialize_exit(ifp->if_serializer);
2045 nfe_ring_dma_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
2050 KASSERT(nseg == 1, ("too many segments, should be 1\n"));
2052 *((uint32_t *)arg) = seg->ds_addr;
2056 nfe_buf_dma_addr(void *arg, bus_dma_segment_t *segs, int nsegs,
2057 bus_size_t mapsz __unused, int error)
2059 struct nfe_dma_ctx *ctx = arg;
2065 KASSERT(nsegs <= ctx->nsegs,
2066 ("too many segments(%d), should be <= %d\n",
2067 nsegs, ctx->nsegs));
2070 for (i = 0; i < nsegs; ++i)
2071 ctx->segs[i] = segs[i];
2075 nfe_newbuf_std(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2078 struct nfe_rx_data *data = &ring->data[idx];
2079 struct nfe_dma_ctx ctx;
2080 bus_dma_segment_t seg;
2085 m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2088 m->m_len = m->m_pkthdr.len = MCLBYTES;
2092 error = bus_dmamap_load_mbuf(ring->data_tag, ring->data_tmpmap,
2093 m, nfe_buf_dma_addr, &ctx,
2094 wait ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT);
2097 if_printf(&sc->arpcom.ac_if, "could map RX mbuf %d\n", error);
2101 /* Unload originally mapped mbuf */
2102 bus_dmamap_unload(ring->data_tag, data->map);
2104 /* Swap this DMA map with tmp DMA map */
2106 data->map = ring->data_tmpmap;
2107 ring->data_tmpmap = map;
2109 /* Caller is assumed to have collected the old mbuf */
2112 nfe_set_paddr_rxdesc(sc, ring, idx, seg.ds_addr);
2114 bus_dmamap_sync(ring->data_tag, data->map, BUS_DMASYNC_PREREAD);
2119 nfe_newbuf_jumbo(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2122 struct nfe_rx_data *data = &ring->data[idx];
2123 struct nfe_jbuf *jbuf;
2126 MGETHDR(m, wait ? MB_WAIT : MB_DONTWAIT, MT_DATA);
2130 jbuf = nfe_jalloc(sc);
2133 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
2134 "-- packet dropped!\n");
2138 m->m_ext.ext_arg = jbuf;
2139 m->m_ext.ext_buf = jbuf->buf;
2140 m->m_ext.ext_free = nfe_jfree;
2141 m->m_ext.ext_ref = nfe_jref;
2142 m->m_ext.ext_size = NFE_JBYTES;
2144 m->m_data = m->m_ext.ext_buf;
2145 m->m_flags |= M_EXT;
2146 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
2148 /* Caller is assumed to have collected the old mbuf */
2151 nfe_set_paddr_rxdesc(sc, ring, idx, jbuf->physaddr);
2153 bus_dmamap_sync(ring->jtag, ring->jmap, BUS_DMASYNC_PREREAD);
2158 nfe_set_paddr_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2159 bus_addr_t physaddr)
2161 if (sc->sc_flags & NFE_40BIT_ADDR) {
2162 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2164 #if defined(__LP64__)
2165 desc64->physaddr[0] = htole32(physaddr >> 32);
2167 desc64->physaddr[1] = htole32(physaddr & 0xffffffff);
2169 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2171 desc32->physaddr = htole32(physaddr);
2176 nfe_set_ready_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx)
2178 if (sc->sc_flags & NFE_40BIT_ADDR) {
2179 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2181 desc64->length = htole16(ring->bufsz);
2182 desc64->flags = htole16(NFE_RX_READY);
2184 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2186 desc32->length = htole16(ring->bufsz);
2187 desc32->flags = htole16(NFE_RX_READY);
2192 nfe_sysctl_imtime(SYSCTL_HANDLER_ARGS)
2194 struct nfe_softc *sc = arg1;
2195 struct ifnet *ifp = &sc->arpcom.ac_if;
2198 lwkt_serialize_enter(ifp->if_serializer);
2201 error = sysctl_handle_int(oidp, &v, 0, req);
2202 if (error || req->newptr == NULL)
2209 if (sc->sc_imtime != v) {
2210 int old_imtime = sc->sc_imtime;
2213 sc->sc_irq_enable = NFE_IRQ_ENABLE(sc);
2215 if ((ifp->if_flags & (IFF_POLLING | IFF_RUNNING))
2217 if (old_imtime > 0 && sc->sc_imtime > 0) {
2218 NFE_WRITE(sc, NFE_IMTIMER,
2219 NFE_IMTIME(sc->sc_imtime));
2220 } else if ((old_imtime * sc->sc_imtime) < 0) {
2226 lwkt_serialize_exit(ifp->if_serializer);