2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_wb.c,v 1.26.2.6 2003/03/05 18:42:34 njl Exp $
33 * $DragonFly: src/sys/dev/netif/wb/if_wb.c,v 1.42 2008/08/17 04:32:35 sephe Exp $
37 * Winbond fast ethernet PCI NIC driver
39 * Supports various cheap network adapters based on the Winbond W89C840F
40 * fast ethernet controller chip. This includes adapters manufactured by
41 * Winbond itself and some made by Linksys.
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
49 * The Winbond W89C840F chip is a bus master; in some ways it resembles
50 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has
51 * one major difference which is that while the registers do many of
52 * the same things as a tulip adapter, the offsets are different: where
53 * tulip registers are typically spaced 8 bytes apart, the Winbond
54 * registers are spaced 4 bytes apart. The receiver filter is also
55 * programmed differently.
57 * Like the tulip, the Winbond chip uses small descriptors containing
58 * a status word, a control word and 32-bit areas that can either be used
59 * to point to two external data blocks, or to point to a single block
60 * and another descriptor in a linked list. Descriptors can be grouped
61 * together in blocks to form fixed length rings or can be chained
62 * together in linked lists. A single packet may be spread out over
63 * several descriptors if necessary.
65 * For the receive ring, this driver uses a linked list of descriptors,
66 * each pointing to a single mbuf cluster buffer, which us large enough
67 * to hold an entire packet. The link list is looped back to created a
70 * For transmission, the driver creates a linked list of 'super descriptors'
71 * which each contain several individual descriptors linked toghether.
72 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we
73 * abuse as fragment pointers. This allows us to use a buffer managment
74 * scheme very similar to that used in the ThunderLAN and Etherlink XL
77 * Autonegotiation is performed using the external PHY via the MII bus.
78 * The sample boards I have all use a Davicom PHY.
80 * Note: the author of the Linux driver for the Winbond chip alludes
81 * to some sort of flaw in the chip's design that seems to mandate some
82 * drastic workaround which signigicantly impairs transmit performance.
83 * I have no idea what he's on about: transmit performance with all
84 * three of my test boards seems fine.
87 #include <sys/param.h>
88 #include <sys/systm.h>
89 #include <sys/sockio.h>
91 #include <sys/malloc.h>
92 #include <sys/kernel.h>
93 #include <sys/socket.h>
94 #include <sys/queue.h>
95 #include <sys/serialize.h>
98 #include <sys/thread2.h>
99 #include <sys/interrupt.h>
102 #include <net/ifq_var.h>
103 #include <net/if_arp.h>
104 #include <net/ethernet.h>
105 #include <net/if_dl.h>
106 #include <net/if_media.h>
110 #include <vm/vm.h> /* for vtophys */
111 #include <vm/pmap.h> /* for vtophys */
113 #include <bus/pci/pcidevs.h>
114 #include <bus/pci/pcireg.h>
115 #include <bus/pci/pcivar.h>
117 #include <dev/netif/mii_layer/mii.h>
118 #include <dev/netif/mii_layer/miivar.h>
120 /* "controller miibus0" required. See GENERIC if you get errors here. */
121 #include "miibus_if.h"
123 #define WB_USEIOSPACE
125 #include "if_wbreg.h"
128 * Various supported device vendors/types and their names.
130 static struct wb_type wb_devs[] = {
131 { PCI_VENDOR_WINBOND, PCI_PRODUCT_WINBOND_W89C840F,
132 "Winbond W89C840F 10/100BaseTX" },
133 { PCI_VENDOR_COMPEX, PCI_PRODUCT_COMPEX_RL100ATX,
134 "Compex RL100-ATX 10/100baseTX" },
138 static int wb_probe(device_t);
139 static int wb_attach(device_t);
140 static int wb_detach(device_t);
142 static void wb_bfree(void *);
143 static int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *,
145 static int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *);
147 static void wb_rxeof(struct wb_softc *);
148 static void wb_rxeoc(struct wb_softc *);
149 static void wb_txeof(struct wb_softc *);
150 static void wb_txeoc(struct wb_softc *);
151 static void wb_intr(void *);
152 static void wb_tick(void *);
153 static void wb_start(struct ifnet *);
154 static int wb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
155 static void wb_init(void *);
156 static void wb_stop(struct wb_softc *);
157 static void wb_watchdog(struct ifnet *);
158 static void wb_shutdown(device_t);
159 static int wb_ifmedia_upd(struct ifnet *);
160 static void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *);
162 static void wb_eeprom_putbyte(struct wb_softc *, int);
163 static void wb_eeprom_getword(struct wb_softc *, int, uint16_t *);
164 static void wb_read_eeprom(struct wb_softc *, caddr_t, int, int);
165 static void wb_mii_sync(struct wb_softc *);
166 static void wb_mii_send(struct wb_softc *, uint32_t, int);
167 static int wb_mii_readreg(struct wb_softc *, struct wb_mii_frame *);
168 static int wb_mii_writereg(struct wb_softc *, struct wb_mii_frame *);
170 static void wb_setcfg(struct wb_softc *, uint32_t);
171 static void wb_setmulti(struct wb_softc *);
172 static void wb_reset(struct wb_softc *);
173 static void wb_fixmedia(struct wb_softc *);
174 static int wb_list_rx_init(struct wb_softc *);
175 static int wb_list_tx_init(struct wb_softc *);
177 static int wb_miibus_readreg(device_t, int, int);
178 static int wb_miibus_writereg(device_t, int, int, int);
179 static void wb_miibus_statchg(device_t);
182 #define WB_RES SYS_RES_IOPORT
183 #define WB_RID WB_PCI_LOIO
185 #define WB_RES SYS_RES_MEMORY
186 #define WB_RID WB_PCI_LOMEM
189 static device_method_t wb_methods[] = {
190 /* Device interface */
191 DEVMETHOD(device_probe, wb_probe),
192 DEVMETHOD(device_attach, wb_attach),
193 DEVMETHOD(device_detach, wb_detach),
194 DEVMETHOD(device_shutdown, wb_shutdown),
196 /* bus interface, for miibus */
197 DEVMETHOD(bus_print_child, bus_generic_print_child),
198 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
201 DEVMETHOD(miibus_readreg, wb_miibus_readreg),
202 DEVMETHOD(miibus_writereg, wb_miibus_writereg),
203 DEVMETHOD(miibus_statchg, wb_miibus_statchg),
207 static DEFINE_CLASS_0(wb, wb_driver, wb_methods, sizeof(struct wb_softc));
208 static devclass_t wb_devclass;
210 DECLARE_DUMMY_MODULE(if_wb);
211 DRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0);
212 DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0);
214 #define WB_SETBIT(sc, reg, x) \
215 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
217 #define WB_CLRBIT(sc, reg, x) \
218 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
221 CSR_WRITE_4(sc, WB_SIO, CSR_READ_4(sc, WB_SIO) | (x))
224 CSR_WRITE_4(sc, WB_SIO, CSR_READ_4(sc, WB_SIO) & ~(x))
227 * Send a read command and address to the EEPROM, check for ACK.
230 wb_eeprom_putbyte(struct wb_softc *sc, int addr)
234 d = addr | WB_EECMD_READ;
237 * Feed in each bit and stobe the clock.
239 for (i = 0x400; i; i >>= 1) {
241 SIO_SET(WB_SIO_EE_DATAIN);
243 SIO_CLR(WB_SIO_EE_DATAIN);
245 SIO_SET(WB_SIO_EE_CLK);
247 SIO_CLR(WB_SIO_EE_CLK);
253 * Read a word of data stored in the EEPROM at address 'addr.'
256 wb_eeprom_getword(struct wb_softc *sc, int addr, uint16_t *dest)
261 /* Enter EEPROM access mode. */
262 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
265 * Send address of word we want to read.
267 wb_eeprom_putbyte(sc, addr);
269 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
272 * Start reading bits from EEPROM.
274 for (i = 0x8000; i; i >>= 1) {
275 SIO_SET(WB_SIO_EE_CLK);
277 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)
279 SIO_CLR(WB_SIO_EE_CLK);
283 /* Turn off EEPROM access mode. */
284 CSR_WRITE_4(sc, WB_SIO, 0);
290 * Read a sequence of words from the EEPROM.
293 wb_read_eeprom(struct wb_softc *sc, caddr_t dest, int off, int cnt)
296 uint16_t word = 0, *ptr;
298 for (i = 0; i < cnt; i++) {
299 wb_eeprom_getword(sc, off + i, &word);
300 ptr = (uint16_t *)(dest + (i * 2));
306 * Sync the PHYs by setting data bit and strobing the clock 32 times.
309 wb_mii_sync(struct wb_softc *sc)
313 SIO_SET(WB_SIO_MII_DIR | WB_SIO_MII_DATAIN);
315 for (i = 0; i < 32; i++) {
316 SIO_SET(WB_SIO_MII_CLK);
318 SIO_CLR(WB_SIO_MII_CLK);
324 * Clock a series of bits through the MII.
327 wb_mii_send(struct wb_softc *sc, uint32_t bits, int cnt)
331 SIO_CLR(WB_SIO_MII_CLK);
333 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
335 SIO_SET(WB_SIO_MII_DATAIN);
337 SIO_CLR(WB_SIO_MII_DATAIN);
339 SIO_CLR(WB_SIO_MII_CLK);
341 SIO_SET(WB_SIO_MII_CLK);
346 * Read an PHY register through the MII.
349 wb_mii_readreg(struct wb_softc *sc, struct wb_mii_frame *frame)
356 * Set up frame for RX.
358 frame->mii_stdelim = WB_MII_STARTDELIM;
359 frame->mii_opcode = WB_MII_READOP;
360 frame->mii_turnaround = 0;
363 CSR_WRITE_4(sc, WB_SIO, 0);
368 SIO_SET(WB_SIO_MII_DIR);
373 * Send command/address info.
375 wb_mii_send(sc, frame->mii_stdelim, 2);
376 wb_mii_send(sc, frame->mii_opcode, 2);
377 wb_mii_send(sc, frame->mii_phyaddr, 5);
378 wb_mii_send(sc, frame->mii_regaddr, 5);
381 SIO_CLR((WB_SIO_MII_CLK | WB_SIO_MII_DATAIN));
383 SIO_SET(WB_SIO_MII_CLK);
387 SIO_CLR(WB_SIO_MII_DIR);
389 SIO_CLR(WB_SIO_MII_CLK);
391 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT;
392 SIO_SET(WB_SIO_MII_CLK);
394 SIO_CLR(WB_SIO_MII_CLK);
396 SIO_SET(WB_SIO_MII_CLK);
400 * Now try reading data bits. If the ack failed, we still
401 * need to clock through 16 cycles to keep the PHY(s) in sync.
404 for(i = 0; i < 16; i++) {
405 SIO_CLR(WB_SIO_MII_CLK);
407 SIO_SET(WB_SIO_MII_CLK);
413 for (i = 0x8000; i; i >>= 1) {
414 SIO_CLR(WB_SIO_MII_CLK);
417 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT)
418 frame->mii_data |= i;
421 SIO_SET(WB_SIO_MII_CLK);
427 SIO_CLR(WB_SIO_MII_CLK);
429 SIO_SET(WB_SIO_MII_CLK);
440 * Write to a PHY register through the MII.
443 wb_mii_writereg(struct wb_softc *sc, struct wb_mii_frame *frame)
448 * Set up frame for TX.
451 frame->mii_stdelim = WB_MII_STARTDELIM;
452 frame->mii_opcode = WB_MII_WRITEOP;
453 frame->mii_turnaround = WB_MII_TURNAROUND;
456 * Turn on data output.
458 SIO_SET(WB_SIO_MII_DIR);
462 wb_mii_send(sc, frame->mii_stdelim, 2);
463 wb_mii_send(sc, frame->mii_opcode, 2);
464 wb_mii_send(sc, frame->mii_phyaddr, 5);
465 wb_mii_send(sc, frame->mii_regaddr, 5);
466 wb_mii_send(sc, frame->mii_turnaround, 2);
467 wb_mii_send(sc, frame->mii_data, 16);
470 SIO_SET(WB_SIO_MII_CLK);
472 SIO_CLR(WB_SIO_MII_CLK);
478 SIO_CLR(WB_SIO_MII_DIR);
486 wb_miibus_readreg(device_t dev, int phy, int reg)
488 struct wb_softc *sc = device_get_softc(dev);
489 struct wb_mii_frame frame;
491 bzero(&frame, sizeof(frame));
493 frame.mii_phyaddr = phy;
494 frame.mii_regaddr = reg;
495 wb_mii_readreg(sc, &frame);
497 return(frame.mii_data);
501 wb_miibus_writereg(device_t dev, int phy, int reg, int data)
503 struct wb_softc *sc = device_get_softc(dev);
504 struct wb_mii_frame frame;
506 bzero(&frame, sizeof(frame));
508 frame.mii_phyaddr = phy;
509 frame.mii_regaddr = reg;
510 frame.mii_data = data;
512 wb_mii_writereg(sc, &frame);
518 wb_miibus_statchg(device_t dev)
520 struct wb_softc *sc = device_get_softc(dev);
521 struct mii_data *mii;
523 mii = device_get_softc(sc->wb_miibus);
524 wb_setcfg(sc, mii->mii_media_active);
528 * Program the 64-bit multicast hash filter.
531 wb_setmulti(struct wb_softc *sc)
533 struct ifnet *ifp = &sc->arpcom.ac_if;
535 uint32_t hashes[2] = { 0, 0 };
536 struct ifmultiaddr *ifma;
539 rxfilt = CSR_READ_4(sc, WB_NETCFG);
541 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
542 rxfilt |= WB_NETCFG_RX_MULTI;
543 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
544 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF);
545 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF);
549 /* first, zot all the existing hash bits */
550 CSR_WRITE_4(sc, WB_MAR0, 0);
551 CSR_WRITE_4(sc, WB_MAR1, 0);
553 /* now program new ones */
554 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
555 if (ifma->ifma_addr->sa_family != AF_LINK)
557 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *)
558 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
560 hashes[0] |= (1 << h);
562 hashes[1] |= (1 << (h - 32));
567 rxfilt |= WB_NETCFG_RX_MULTI;
569 rxfilt &= ~WB_NETCFG_RX_MULTI;
571 CSR_WRITE_4(sc, WB_MAR0, hashes[0]);
572 CSR_WRITE_4(sc, WB_MAR1, hashes[1]);
573 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
577 * The Winbond manual states that in order to fiddle with the
578 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
579 * first have to put the transmit and/or receive logic in the idle state.
582 wb_setcfg(struct wb_softc *sc, uint32_t media)
586 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON | WB_NETCFG_RX_ON)) {
588 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON | WB_NETCFG_RX_ON));
590 for (i = 0; i < WB_TIMEOUT; i++) {
592 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&
593 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE))
597 if (i == WB_TIMEOUT) {
598 if_printf(&sc->arpcom.ac_if, "failed to force tx and "
599 "rx to idle state\n");
603 if (IFM_SUBTYPE(media) == IFM_10_T)
604 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
606 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
608 if ((media & IFM_GMASK) == IFM_FDX)
609 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
611 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
614 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON | WB_NETCFG_RX_ON);
618 wb_reset(struct wb_softc *sc)
621 struct mii_data *mii;
623 CSR_WRITE_4(sc, WB_NETCFG, 0);
624 CSR_WRITE_4(sc, WB_BUSCTL, 0);
625 CSR_WRITE_4(sc, WB_TXADDR, 0);
626 CSR_WRITE_4(sc, WB_RXADDR, 0);
628 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
629 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
631 for (i = 0; i < WB_TIMEOUT; i++) {
633 if ((CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET) == 0)
637 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
639 /* Wait a little while for the chip to get its brains in order. */
642 if (sc->wb_miibus == NULL)
645 mii = device_get_softc(sc->wb_miibus);
649 if (mii->mii_instance) {
650 struct mii_softc *miisc;
651 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
652 mii_phy_reset(miisc);
657 wb_fixmedia(struct wb_softc *sc)
659 struct mii_data *mii;
662 if (sc->wb_miibus == NULL)
665 mii = device_get_softc(sc->wb_miibus);
668 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
669 media = mii->mii_media_active & ~IFM_10_T;
671 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
672 media = mii->mii_media_active & ~IFM_100_TX;
677 ifmedia_set(&mii->mii_media, media);
681 * Probe for a Winbond chip. Check the PCI vendor and device
682 * IDs against our list and return a device name if we find a match.
685 wb_probe(device_t dev)
688 uint16_t vendor, product;
690 vendor = pci_get_vendor(dev);
691 product = pci_get_device(dev);
693 for (t = wb_devs; t->wb_name != NULL; t++) {
694 if (vendor == t->wb_vid && product == t->wb_did) {
695 device_set_desc(dev, t->wb_name);
704 * Attach the interface. Allocate softc structures, do ifmedia
705 * setup and ethernet/BPF attach.
708 wb_attach(device_t dev)
710 u_char eaddr[ETHER_ADDR_LEN];
715 sc = device_get_softc(dev);
716 callout_init(&sc->wb_stat_timer);
719 * Handle power management nonsense.
721 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
722 uint32_t iobase, membase, irq;
724 /* Save important PCI config data. */
725 iobase = pci_read_config(dev, WB_PCI_LOIO, 4);
726 membase = pci_read_config(dev, WB_PCI_LOMEM, 4);
727 irq = pci_read_config(dev, WB_PCI_INTLINE, 4);
729 /* Reset the power state. */
730 device_printf(dev, "chip is in D%d power mode "
731 "-- setting to D0\n", pci_get_powerstate(dev));
732 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
734 /* Restore PCI config data. */
735 pci_write_config(dev, WB_PCI_LOIO, iobase, 4);
736 pci_write_config(dev, WB_PCI_LOMEM, membase, 4);
737 pci_write_config(dev, WB_PCI_INTLINE, irq, 4);
740 pci_enable_busmaster(dev);
743 sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE);
745 if (sc->wb_res == NULL) {
746 device_printf(dev, "couldn't map ports/memory\n");
751 sc->wb_btag = rman_get_bustag(sc->wb_res);
752 sc->wb_bhandle = rman_get_bushandle(sc->wb_res);
754 /* Allocate interrupt */
756 sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
757 RF_SHAREABLE | RF_ACTIVE);
759 if (sc->wb_irq == NULL) {
760 device_printf(dev, "couldn't map interrupt\n");
765 /* Save the cache line size. */
766 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF;
768 ifp = &sc->arpcom.ac_if;
769 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
771 /* Reset the adapter. */
775 * Get station address from the EEPROM.
777 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3);
779 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF,
780 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
782 if (sc->wb_ldata == NULL) {
783 device_printf(dev, "no memory for list buffers!\n");
789 ifp->if_mtu = ETHERMTU;
790 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
791 ifp->if_ioctl = wb_ioctl;
792 ifp->if_start = wb_start;
793 ifp->if_watchdog = wb_watchdog;
794 ifp->if_init = wb_init;
795 ifp->if_baudrate = 10000000;
796 ifq_set_maxlen(&ifp->if_snd, WB_TX_LIST_CNT - 1);
797 ifq_set_ready(&ifp->if_snd);
802 if (mii_phy_probe(dev, &sc->wb_miibus,
803 wb_ifmedia_upd, wb_ifmedia_sts)) {
809 * Call MI attach routine.
811 ether_ifattach(ifp, eaddr, NULL);
813 error = bus_setup_intr(dev, sc->wb_irq, INTR_MPSAFE,
814 wb_intr, sc, &sc->wb_intrhand,
818 device_printf(dev, "couldn't set up irq\n");
823 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->wb_irq));
824 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
834 wb_detach(device_t dev)
836 struct wb_softc *sc = device_get_softc(dev);
837 struct ifnet *ifp = &sc->arpcom.ac_if;
840 if (device_is_attached(dev)) {
841 lwkt_serialize_enter(ifp->if_serializer);
843 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
844 lwkt_serialize_exit(ifp->if_serializer);
850 device_delete_child(dev, sc->wb_miibus);
851 bus_generic_detach(dev);
854 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
856 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
857 if (sc->wb_ldata_ptr) {
858 contigfree(sc->wb_ldata_ptr, sizeof(struct wb_list_data) + 8,
866 * Initialize the transmit descriptors.
869 wb_list_tx_init(struct wb_softc *sc)
871 struct wb_chain_data *cd;
872 struct wb_list_data *ld;
878 for (i = 0; i < WB_TX_LIST_CNT; i++) {
879 nexti = (i == WB_TX_LIST_CNT - 1) ? 0 : i + 1;
880 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i];
881 cd->wb_tx_chain[i].wb_nextdesc = &cd->wb_tx_chain[nexti];
884 cd->wb_tx_free = &cd->wb_tx_chain[0];
885 cd->wb_tx_tail = cd->wb_tx_head = NULL;
891 * Initialize the RX descriptors and allocate mbufs for them. Note that
892 * we arrange the descriptors in a closed ring, so that the last descriptor
893 * points back to the first.
896 wb_list_rx_init(struct wb_softc *sc)
898 struct wb_chain_data *cd;
899 struct wb_list_data *ld;
905 for (i = 0; i < WB_RX_LIST_CNT; i++) {
906 cd->wb_rx_chain[i].wb_ptr = &ld->wb_rx_list[i];
907 cd->wb_rx_chain[i].wb_buf = &ld->wb_rxbufs[i];
908 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS)
910 nexti = (WB_RX_LIST_CNT - 1) ? 0 : i + 1;
911 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[nexti];
912 ld->wb_rx_list[i].wb_next = vtophys(&ld->wb_rx_list[nexti]);
915 cd->wb_rx_head = &cd->wb_rx_chain[0];
926 * Initialize an RX descriptor and attach an MBUF cluster.
929 wb_newbuf(struct wb_softc *sc, struct wb_chain_onefrag *c, struct mbuf *m)
931 struct mbuf *m_new = NULL;
934 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
938 m_new->m_data = m_new->m_ext.ext_buf = c->wb_buf;
939 m_new->m_flags |= M_EXT;
940 m_new->m_ext.ext_size = m_new->m_pkthdr.len =
941 m_new->m_len = WB_BUFBYTES;
942 m_new->m_ext.ext_free = wb_bfree;
943 m_new->m_ext.ext_ref = wb_bfree;
946 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES;
947 m_new->m_data = m_new->m_ext.ext_buf;
950 m_adj(m_new, sizeof(uint64_t));
953 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t));
954 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536;
955 c->wb_ptr->wb_status = WB_RXSTAT;
961 * A frame has been uploaded: pass the resulting mbuf chain up to
962 * the higher level protocols.
965 wb_rxeof(struct wb_softc *sc)
967 struct ifnet *ifp = &sc->arpcom.ac_if;
969 struct wb_chain_onefrag *cur_rx;
974 rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status;
975 if ((rxstat & WB_RXSTAT_OWN) == 0)
978 cur_rx = sc->wb_cdata.wb_rx_head;
979 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc;
983 if ((rxstat & WB_RXSTAT_MIIERR) ||
984 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) ||
985 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) ||
986 (rxstat & WB_RXSTAT_LASTFRAG) == 0||
987 (rxstat & WB_RXSTAT_RXCMP) == 0) {
989 wb_newbuf(sc, cur_rx, m);
990 if_printf(ifp, "receiver babbling: possible chip "
991 "bug, forcing reset\n");
998 if (rxstat & WB_RXSTAT_RXERR) {
1000 wb_newbuf(sc, cur_rx, m);
1004 /* No errors; receive the packet. */
1005 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status);
1008 * XXX The Winbond chip includes the CRC with every
1009 * received frame, and there's no way to turn this
1010 * behavior off (at least, I can't find anything in
1011 * the manual that explains how to do it) so we have
1012 * to trim off the CRC manually.
1014 total_len -= ETHER_CRC_LEN;
1016 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1017 total_len + ETHER_ALIGN, 0, ifp, NULL);
1018 wb_newbuf(sc, cur_rx, m);
1023 m_adj(m0, ETHER_ALIGN);
1027 ifp->if_input(ifp, m);
1032 wb_rxeoc(struct wb_softc *sc)
1036 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1037 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1038 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1039 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND)
1040 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1044 * A frame was downloaded to the chip. It's safe for us to clean up
1048 wb_txeof(struct wb_softc *sc)
1050 struct ifnet *ifp = &sc->arpcom.ac_if;
1051 struct wb_chain *cur_tx;
1053 /* Clear the timeout timer. */
1056 if (sc->wb_cdata.wb_tx_head == NULL)
1060 * Go through our tx list and free mbufs for those
1061 * frames that have been transmitted.
1063 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) {
1066 cur_tx = sc->wb_cdata.wb_tx_head;
1067 txstat = WB_TXSTATUS(cur_tx);
1069 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT)
1072 if (txstat & WB_TXSTAT_TXERR) {
1074 if (txstat & WB_TXSTAT_ABORT)
1075 ifp->if_collisions++;
1076 if (txstat & WB_TXSTAT_LATECOLL)
1077 ifp->if_collisions++;
1080 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3;
1083 m_freem(cur_tx->wb_mbuf);
1084 cur_tx->wb_mbuf = NULL;
1086 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) {
1087 sc->wb_cdata.wb_tx_head = NULL;
1088 sc->wb_cdata.wb_tx_tail = NULL;
1092 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc;
1097 * TX 'end of channel' interrupt handler.
1100 wb_txeoc(struct wb_softc *sc)
1102 struct ifnet *ifp = &sc->arpcom.ac_if;
1106 if (sc->wb_cdata.wb_tx_head == NULL) {
1107 ifp->if_flags &= ~IFF_OACTIVE;
1108 sc->wb_cdata.wb_tx_tail = NULL;
1109 } else if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) {
1110 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN;
1112 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1119 struct wb_softc *sc = arg;
1120 struct ifnet *ifp = &sc->arpcom.ac_if;
1123 if ((ifp->if_flags & IFF_UP) == 0)
1126 /* Disable interrupts. */
1127 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1130 status = CSR_READ_4(sc, WB_ISR);
1132 CSR_WRITE_4(sc, WB_ISR, status);
1134 if ((status & WB_INTRS) == 0)
1137 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) {
1140 if (status & WB_ISR_RX_ERR)
1146 if (status & WB_ISR_RX_OK)
1149 if (status & WB_ISR_RX_IDLE)
1152 if (status & WB_ISR_TX_OK)
1155 if (status & WB_ISR_TX_NOBUF)
1158 if (status & WB_ISR_TX_IDLE) {
1160 if (sc->wb_cdata.wb_tx_head != NULL) {
1161 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1162 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1166 if (status & WB_ISR_TX_UNDERRUN) {
1169 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1170 /* Jack up TX threshold */
1171 sc->wb_txthresh += WB_TXTHRESH_CHUNK;
1172 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1173 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1174 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1177 if (status & WB_ISR_BUS_ERR) {
1183 /* Re-enable interrupts. */
1184 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1186 if (!ifq_is_empty(&ifp->if_snd))
1193 struct wb_softc *sc = xsc;
1194 struct ifnet *ifp = &sc->arpcom.ac_if;
1195 struct mii_data *mii = device_get_softc(sc->wb_miibus);
1197 lwkt_serialize_enter(ifp->if_serializer);
1199 callout_reset(&sc->wb_stat_timer, hz, wb_tick, sc);
1200 lwkt_serialize_exit(ifp->if_serializer);
1204 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1205 * pointers to the fragment pointers.
1208 wb_encap(struct wb_softc *sc, struct wb_chain *c, struct mbuf *m_head)
1210 struct wb_desc *f = NULL;
1212 int frag, total_len;
1215 * Start packing the mbufs in this chain into
1216 * the fragment pointers. Stop when we run out
1217 * of fragments or hit the end of the mbuf chain.
1221 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1222 if (m->m_len != 0) {
1223 if (frag == WB_MAXFRAGS)
1225 total_len += m->m_len;
1226 f = &c->wb_ptr->wb_frag[frag];
1227 f->wb_ctl = WB_TXCTL_TLINK | m->m_len;
1229 f->wb_ctl |= WB_TXCTL_FIRSTFRAG;
1232 f->wb_status = WB_TXSTAT_OWN;
1234 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]);
1235 f->wb_data = vtophys(mtod(m, vm_offset_t));
1241 * Handle special case: we used up all 16 fragments,
1242 * but we have more mbufs left in the chain. Copy the
1243 * data into an mbuf cluster. Note that we don't
1244 * bother clearing the values in the other fragment
1245 * pointers/counters; it wouldn't gain us anything,
1246 * and would waste cycles.
1249 struct mbuf *m_new = NULL;
1251 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1254 if (m_head->m_pkthdr.len > MHLEN) {
1255 MCLGET(m_new, MB_DONTWAIT);
1256 if ((m_new->m_flags & M_EXT) == 0) {
1261 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1262 mtod(m_new, caddr_t));
1263 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1266 f = &c->wb_ptr->wb_frag[0];
1268 f->wb_data = vtophys(mtod(m_new, caddr_t));
1269 f->wb_ctl = total_len = m_new->m_len;
1270 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG;
1274 if (total_len < WB_MIN_FRAMELEN) {
1275 f = &c->wb_ptr->wb_frag[frag];
1276 f->wb_ctl = WB_MIN_FRAMELEN - total_len;
1277 f->wb_data = vtophys(&sc->wb_cdata.wb_pad);
1278 f->wb_ctl |= WB_TXCTL_TLINK;
1279 f->wb_status = WB_TXSTAT_OWN;
1283 c->wb_mbuf = m_head;
1284 c->wb_lastdesc = frag - 1;
1285 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG;
1286 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]);
1292 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1293 * to the mbuf data regions directly in the transmit lists. We also save a
1294 * copy of the pointers since the transmit list fragment pointers are
1295 * physical addresses.
1298 wb_start(struct ifnet *ifp)
1300 struct wb_softc *sc = ifp->if_softc;
1301 struct mbuf *m_head = NULL;
1302 struct wb_chain *cur_tx = NULL, *start_tx;
1305 * Check for an available queue slot. If there are none,
1308 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) {
1309 ifp->if_flags |= IFF_OACTIVE;
1313 start_tx = sc->wb_cdata.wb_tx_free;
1315 while (sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) {
1316 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1320 /* Pick a descriptor off the free list. */
1321 cur_tx = sc->wb_cdata.wb_tx_free;
1322 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc;
1324 /* Pack the data into the descriptor. */
1325 wb_encap(sc, cur_tx, m_head);
1327 if (cur_tx != start_tx)
1328 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN;
1330 BPF_MTAP(ifp, cur_tx->wb_mbuf);
1334 * If there are no packets queued, bail.
1340 * Place the request for the upload interrupt
1341 * in the last descriptor in the chain. This way, if
1342 * we're chaining several packets at once, we'll only
1343 * get an interupt once for the whole chain rather than
1344 * once for each packet.
1346 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT;
1347 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT;
1348 sc->wb_cdata.wb_tx_tail = cur_tx;
1350 if (sc->wb_cdata.wb_tx_head == NULL) {
1351 sc->wb_cdata.wb_tx_head = start_tx;
1352 WB_TXOWN(start_tx) = WB_TXSTAT_OWN;
1353 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1356 * We need to distinguish between the case where
1357 * the own bit is clear because the chip cleared it
1358 * and where the own bit is clear because we haven't
1359 * set it yet. The magic value WB_UNSET is just some
1360 * ramdomly chosen number which doesn't have the own
1361 * bit set. When we actually transmit the frame, the
1362 * status word will have _only_ the own bit set, so
1363 * the txeoc handler will be able to tell if it needs
1364 * to initiate another transmission to flush out pending
1367 WB_TXOWN(start_tx) = WB_UNSENT;
1371 * Set a timeout in case the chip goes out to lunch.
1379 struct wb_softc *sc = xsc;
1380 struct ifnet *ifp = &sc->arpcom.ac_if;
1382 struct mii_data *mii;
1386 mii = device_get_softc(sc->wb_miibus);
1389 * Cancel pending I/O and free all RX/TX buffers.
1394 sc->wb_txthresh = WB_TXTHRESH_INIT;
1397 * Set cache alignment and burst length.
1400 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG);
1401 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1402 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1405 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE | WB_BUSCTL_ARBITRATION);
1406 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG);
1407 switch(sc->wb_cachesize) {
1409 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG);
1412 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG);
1415 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG);
1419 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE);
1423 /* This doesn't tend to work too well at 100Mbps. */
1424 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON);
1426 /* Init our MAC address */
1427 for (i = 0; i < ETHER_ADDR_LEN; i++)
1428 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]);
1430 /* Init circular RX list. */
1431 if (wb_list_rx_init(sc) == ENOBUFS) {
1432 if_printf(ifp, "initialization failed: no "
1433 "memory for rx buffers\n");
1439 /* Init TX descriptors. */
1440 wb_list_tx_init(sc);
1442 /* If we want promiscuous mode, set the allframes bit. */
1443 if (ifp->if_flags & IFF_PROMISC)
1444 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1446 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1449 * Set capture broadcast bit to capture broadcast frames.
1451 if (ifp->if_flags & IFF_BROADCAST)
1452 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1454 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1457 * Program the multicast filter, if necessary.
1462 * Load the address of the RX list.
1464 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1465 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1468 * Enable interrupts.
1470 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1471 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF);
1473 /* Enable receiver and transmitter. */
1474 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1475 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1477 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1478 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0]));
1479 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1483 ifp->if_flags |= IFF_RUNNING;
1484 ifp->if_flags &= ~IFF_OACTIVE;
1488 callout_reset(&sc->wb_stat_timer, hz, wb_tick, sc);
1492 * Set media options.
1495 wb_ifmedia_upd(struct ifnet *ifp)
1497 struct wb_softc *sc = ifp->if_softc;
1499 if (ifp->if_flags & IFF_UP)
1506 * Report current media status.
1509 wb_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1511 struct wb_softc *sc = ifp->if_softc;
1512 struct mii_data *mii = device_get_softc(sc->wb_miibus);
1515 ifmr->ifm_active = mii->mii_media_active;
1516 ifmr->ifm_status = mii->mii_media_status;
1520 wb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1522 struct wb_softc *sc = ifp->if_softc;
1523 struct mii_data *mii;
1524 struct ifreq *ifr = (struct ifreq *) data;
1531 if (ifp->if_flags & IFF_UP)
1533 else if (ifp->if_flags & IFF_RUNNING)
1544 mii = device_get_softc(sc->wb_miibus);
1545 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1548 error = ether_ioctl(ifp, command, data);
1558 wb_watchdog(struct ifnet *ifp)
1560 struct wb_softc *sc = ifp->if_softc;
1563 if_printf(ifp, "watchdog timeout\n");
1565 if ((wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) == 0)
1566 if_printf(ifp, "no carrier - transceiver cable problem?\n");
1572 if (!ifq_is_empty(&ifp->if_snd))
1577 * Stop the adapter and free any mbufs allocated to the
1581 wb_stop(struct wb_softc *sc)
1583 struct ifnet *ifp = &sc->arpcom.ac_if;
1588 callout_stop(&sc->wb_stat_timer);
1590 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON | WB_NETCFG_TX_ON));
1591 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1592 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000);
1593 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000);
1596 * Free data in the RX lists.
1598 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1599 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) {
1600 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf);
1601 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL;
1604 bzero(&sc->wb_ldata->wb_rx_list, sizeof(sc->wb_ldata->wb_rx_list));
1607 * Free the TX list buffers.
1609 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1610 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) {
1611 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf);
1612 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL;
1616 bzero(&sc->wb_ldata->wb_tx_list, sizeof(sc->wb_ldata->wb_tx_list));
1618 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1622 * Stop all chip I/O so that the kernel's probe routines don't
1623 * get confused by errant DMAs when rebooting.
1626 wb_shutdown(device_t dev)
1628 struct wb_softc *sc = device_get_softc(dev);
1629 struct ifnet *ifp = &sc->arpcom.ac_if;
1631 lwkt_serialize_enter(ifp->if_serializer);
1633 lwkt_serialize_exit(ifp->if_serializer);