2 * Copyright (c) 2001 Gary Jennejohn. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 * 4. Altered versions must be plainly marked as such, and must not be
17 * misrepresented as being the original software and/or documentation.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 *---------------------------------------------------------------------------
33 * i4b_ifpi2_pci.c: AVM Fritz!Card PCI hardware driver
34 * --------------------------------------------------
38 * $FreeBSD: src/sys/i4b/layer1/ifpi2/i4b_ifpi2_pci.c,v 1.6.2.2 2002/05/15 08:12:42 gj Exp $
40 * last edit-date: [Fri Jan 12 17:01:26 2001]
42 *---------------------------------------------------------------------------*/
44 #include "use_ifpi2.h"
48 #if (NIFPI2 > 0) && (NPCI > 0)
50 #include <sys/param.h>
51 #include <sys/kernel.h>
52 #include <sys/systm.h>
56 #include <sys/socket.h>
57 #include <sys/thread2.h>
59 #include <bus/pci/pcireg.h>
60 #include <bus/pci/pcivar.h>
63 #include <net/i4b/include/machine/i4b_debug.h>
64 #include <net/i4b/include/machine/i4b_ioctl.h>
65 #include <net/i4b/include/machine/i4b_trace.h>
67 #include "../../include/i4b_global.h"
68 #include "../../include/i4b_mbuf.h"
70 #include "../i4b_l1.h"
71 #include "../isic/i4b_isic.h"
72 /*#include "../isic/i4b_isac.h"*/
73 #include "../isic/i4b_hscx.h"
75 #include "i4b_ifpi2_ext.h"
76 #include "i4b_ifpi2_isacsx.h"
78 #define PCI_AVMA1_VID 0x1244
79 #define PCI_AVMA1_V2_DID 0x0e00
82 static void avma1pp2_disable(device_t);
84 static void avma1pp2_intr(void *);
85 static void hscx_write_reg(int, u_int, struct l1_softc *);
86 static u_char hscx_read_reg(int, struct l1_softc *);
87 static u_int hscx_read_reg_int(int, struct l1_softc *);
88 static void hscx_read_fifo(int, void *, size_t, struct l1_softc *);
89 static void hscx_write_fifo(int, void *, size_t, struct l1_softc *);
90 static void avma1pp2_hscx_int_handler(struct l1_softc *);
91 static void avma1pp2_hscx_intr(int, u_int, struct l1_softc *);
92 static void avma1pp2_init_linktab(struct l1_softc *);
93 static void avma1pp2_bchannel_setup(int, int, int, int);
94 static void avma1pp2_bchannel_start(int, int);
95 static void avma1pp2_hscx_init(struct l1_softc *, int, int);
96 static void avma1pp2_bchannel_stat(int, int, bchan_statistics_t *);
97 static void avma1pp2_set_linktab(int, int, drvr_link_t *);
98 static isdn_link_t * avma1pp2_ret_linktab(int, int);
99 static int avma1pp2_pci_probe(device_t);
100 static int avma1pp2_hscx_fifo(l1_bchan_state_t *, struct l1_softc *);
101 int avma1pp2_attach_avma1pp(device_t);
102 static void ifpi2_isacsx_intr(struct l1_softc *sc);
104 static device_method_t avma1pp2_pci_methods[] = {
105 /* Device interface */
106 DEVMETHOD(device_probe, avma1pp2_pci_probe),
107 DEVMETHOD(device_attach, avma1pp2_attach_avma1pp),
108 DEVMETHOD(device_shutdown, avma1pp2_disable),
111 DEVMETHOD(bus_print_child, bus_generic_print_child),
112 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
117 static driver_t avma1pp2_pci_driver = {
119 avma1pp2_pci_methods,
120 sizeof(struct l1_softc)
123 static devclass_t avma1pp2_pci_devclass;
125 DRIVER_MODULE(avma1pp2, pci, avma1pp2_pci_driver, avma1pp2_pci_devclass, NULL, NULL);
127 /* jump table for multiplex routines */
129 struct i4b_l1mux_func avma1pp2_l1mux_func = {
130 avma1pp2_ret_linktab,
131 avma1pp2_set_linktab,
132 ifpi2_mph_command_req,
134 ifpi2_ph_activate_req,
137 struct l1_softc *ifpi2_scp[IFPI2_MAXUNIT];
139 /*---------------------------------------------------------------------------*
140 * AVM PCI Fritz!Card V. 2 special registers
141 *---------------------------------------------------------------------------*/
144 * AVM PCI Status Latch 0 read only bits
146 #define ASL_IRQ_ISAC 0x01 /* ISAC interrupt, active high */
147 #define ASL_IRQ_HSCX 0x02 /* HSX interrupt, active high */
148 #define ASL_IRQ_TIMER 0x04 /* Timer interrupt, active high */
149 #define ASL_IRQ_BCHAN ASL_IRQ_HSCX
150 /* actually active high */
151 #define ASL_IRQ_Pending (ASL_IRQ_ISAC | ASL_IRQ_HSCX | ASL_IRQ_TIMER)
154 * AVM PCI Status Latch 0 read only bits
156 #define ASL_TIMERRESET 0x04
157 #define ASL_ENABLE_INT 0x08
162 #define HSCX_STAT_RME 0x01
163 #define HSCX_STAT_RDO 0x10
164 #define HSCX_STAT_CRCVFRRAB 0x0E
165 #define HSCX_STAT_CRCVFR 0x06
166 #define HSCX_STAT_RML_MASK 0x3f00
169 * "HSCX" interrupt bits
171 #define HSCX_INT_XPR 0x80
172 #define HSCX_INT_XDU 0x40
173 #define HSCX_INT_RPR 0x20
174 #define HSCX_INT_MASK 0xE0
177 * "HSCX" command bits
179 #define HSCX_CMD_XRS 0x80
180 #define HSCX_CMD_XME 0x01
181 #define HSCX_CMD_RRS 0x20
182 #define HSCX_CMD_XML_MASK 0x3f00
184 /* "HSCX" mode bits */
185 #define HSCX_MODE_ITF_FLG 0x01
186 #define HSCX_MODE_TRANS 0x02
188 /* offsets to various registers in the ASIC, evidently */
189 #define STAT0_OFFSET 0x02
191 #define HSCX_FIFO1 0x10
192 #define HSCX_FIFO2 0x18
194 #define HSCX_STAT1 0x14
195 #define HSCX_STAT2 0x1c
197 #define ISACSX_INDEX 0x04
198 #define ISACSX_DATA 0x08
201 * Commands and parameters are sent to the "HSCX" as a long, but the
202 * fields are handled as bytes.
205 * (prot << 16)|(txl << 8)|cmd
208 * prot = protocol to use
209 * txl = transmit length
210 * cmd = the command to be executed
212 * The fields are defined as u_char in struct l1_softc.
214 * Macro to coalesce the byte fields into a u_int
216 #define AVMA1PPSETCMDLONG(f) (f) = ((sc->avma1pp_cmd) | (sc->avma1pp_txl << 8) \
217 | (sc->avma1pp_prot << 16))
220 * to prevent deactivating the "HSCX" when both channels are active we
221 * define an HSCX_ACTIVE flag which is or'd into the channel's state
222 * flag in avma1pp2_bchannel_setup upon active and cleared upon deactivation.
223 * It is set high to allow room for new flags.
225 #define HSCX_AVMA1PP_ACTIVE 0x1000
227 /*---------------------------------------------------------------------------*
228 * AVM read fifo routines
229 *---------------------------------------------------------------------------*/
232 avma1pp2_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
234 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
235 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
240 bus_space_write_4(btag, bhandle, ISACSX_INDEX, 0);
241 /* evidently each byte must be read as a long */
242 for (i = 0; i < size; i++)
243 ((u_int8_t *)buf)[i] = (u_int8_t)bus_space_read_4(btag, bhandle, ISACSX_DATA);
245 case ISIC_WHAT_HSCXA:
246 hscx_read_fifo(0, buf, size, sc);
248 case ISIC_WHAT_HSCXB:
249 hscx_read_fifo(1, buf, size, sc);
255 hscx_read_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
260 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
261 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
263 dataoff = chan ? HSCX_FIFO2 : HSCX_FIFO1;
265 ip = (u_int32_t *)buf;
267 /* what if len isn't a multiple of sizeof(int) and buf is */
271 *ip++ = bus_space_read_4(btag, bhandle, dataoff);
276 /*---------------------------------------------------------------------------*
277 * AVM write fifo routines
278 *---------------------------------------------------------------------------*/
280 avma1pp2_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
282 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
283 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
288 bus_space_write_4(btag, bhandle, ISACSX_INDEX, 0);
289 /* evidently each byte must written as a long */
290 for (i = 0; i < size; i++)
291 bus_space_write_4(btag, bhandle, ISACSX_DATA, ((unsigned char *)buf)[i]);
293 case ISIC_WHAT_HSCXA:
294 hscx_write_fifo(0, buf, size, sc);
296 case ISIC_WHAT_HSCXB:
297 hscx_write_fifo(1, buf, size, sc);
303 hscx_write_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
308 l1_bchan_state_t *Bchan = &sc->sc_chan[chan];
309 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
310 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
312 dataoff = chan ? HSCX_FIFO2 : HSCX_FIFO1;
314 sc->avma1pp_cmd &= ~HSCX_CMD_XME;
316 if (Bchan->out_mbuf_cur == NULL)
318 if (Bchan->bprot != BPROT_NONE)
319 sc->avma1pp_cmd |= HSCX_CMD_XME;
321 if (len != sc->sc_bfifolen)
322 sc->avma1pp_txl = len;
324 cnt = 0; /* borrow cnt */
325 AVMA1PPSETCMDLONG(cnt);
326 hscx_write_reg(chan, cnt, sc);
328 ip = (u_int32_t *)buf;
332 bus_space_write_4(btag, bhandle, dataoff, *ip);
338 /*---------------------------------------------------------------------------*
339 * AVM write register routines
340 *---------------------------------------------------------------------------*/
343 avma1pp2_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
345 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
346 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
350 bus_space_write_4(btag, bhandle, ISACSX_INDEX, offs);
351 bus_space_write_4(btag, bhandle, ISACSX_DATA, data);
353 case ISIC_WHAT_HSCXA:
354 hscx_write_reg(0, data, sc);
356 case ISIC_WHAT_HSCXB:
357 hscx_write_reg(1, data, sc);
363 hscx_write_reg(int chan, u_int val, struct l1_softc *sc)
365 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
366 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
369 off = (chan == 0 ? HSCX_STAT1 : HSCX_STAT2);
371 bus_space_write_4(btag, bhandle, off, val);
374 /*---------------------------------------------------------------------------*
375 * AVM read register routines
376 *---------------------------------------------------------------------------*/
378 avma1pp2_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
380 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
381 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
386 bus_space_write_4(btag, bhandle, ISACSX_INDEX, offs);
387 val = (u_int8_t)bus_space_read_4(btag, bhandle, ISACSX_DATA);
389 case ISIC_WHAT_HSCXA:
390 return hscx_read_reg(0, sc);
391 case ISIC_WHAT_HSCXB:
392 return hscx_read_reg(1, sc);
398 hscx_read_reg(int chan, struct l1_softc *sc)
400 return(hscx_read_reg_int(chan, sc) & 0xff);
404 * need to be able to return an int because the RBCH is in the 2nd
408 hscx_read_reg_int(int chan, struct l1_softc *sc)
410 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
411 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
414 off = (chan == 0 ? HSCX_STAT1 : HSCX_STAT2);
415 return(bus_space_read_4(btag, bhandle, off));
418 /*---------------------------------------------------------------------------*
419 * avma1pp2_probe - probe for a card
420 *---------------------------------------------------------------------------*/
422 avma1pp2_pci_probe(device_t dev)
426 vid = pci_get_vendor(dev);
427 did = pci_get_device(dev);
429 if ((vid == PCI_AVMA1_VID) && (did == PCI_AVMA1_V2_DID)) {
430 device_set_desc(dev, "AVM Fritz!Card PCI Version 2");
437 /*---------------------------------------------------------------------------*
438 * avma1pp2_attach_avma1pp - attach Fritz!Card PCI
439 *---------------------------------------------------------------------------*/
441 avma1pp2_attach_avma1pp(device_t dev)
448 bus_space_handle_t bhandle;
449 bus_space_tag_t btag;
453 vid = pci_get_vendor(dev);
454 did = pci_get_device(dev);
455 sc = device_get_softc(dev);
456 unit = device_get_unit(dev);
457 bzero(sc, sizeof(struct l1_softc));
459 /* probably not really required */
460 if(unit > IFPI2_MAXUNIT) {
461 kprintf("ifpi2-%d: Error, unit > IFPI_MAXUNIT!\n", unit);
466 if ((vid != PCI_AVMA1_VID) && (did != PCI_AVMA1_V2_DID)) {
467 kprintf("ifpi2-%d: unknown device!?\n", unit);
471 ifpi2_scp[unit] = sc;
473 sc->sc_resources.io_rid[0] = PCIR_MAPS+4;
474 sc->sc_resources.io_base[0] = bus_alloc_resource(dev, SYS_RES_IOPORT,
475 &sc->sc_resources.io_rid[0],
476 0, ~0, 1, RF_ACTIVE);
478 if (sc->sc_resources.io_base[0] == NULL) {
479 kprintf("ifpi2-%d: couldn't map IO port\n", unit);
484 bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
485 btag = rman_get_bustag(sc->sc_resources.io_base[0]);
487 /* Allocate interrupt */
488 sc->sc_resources.irq_rid = 0;
489 sc->sc_resources.irq = bus_alloc_resource(dev, SYS_RES_IRQ,
490 &sc->sc_resources.irq_rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
492 if (sc->sc_resources.irq == NULL) {
493 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
494 kprintf("ifpi2-%d: couldn't map interrupt\n", unit);
499 error = bus_setup_intr(dev, sc->sc_resources.irq, 0,
500 avma1pp2_intr, sc, &ih, NULL);
503 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_resources.irq);
504 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
505 kprintf("ifpi2-%d: couldn't set up irq\n", unit);
511 /* end of new-bus stuff */
513 ISAC_BASE = (caddr_t)ISIC_WHAT_ISAC;
515 HSCX_A_BASE = (caddr_t)ISIC_WHAT_HSCXA;
516 HSCX_B_BASE = (caddr_t)ISIC_WHAT_HSCXB;
518 /* setup access routines */
521 sc->readreg = avma1pp2_read_reg;
522 sc->writereg = avma1pp2_write_reg;
524 sc->readfifo = avma1pp2_read_fifo;
525 sc->writefifo = avma1pp2_write_fifo;
527 /* setup card type */
529 sc->sc_cardtyp = CARD_TYPEP_AVMA1PCI_V2;
531 /* setup IOM bus type */
533 sc->sc_bustyp = BUS_TYPE_IOM2;
535 /* set up some other miscellaneous things */
537 sc->sc_bfifolen = HSCX_FIFO_LEN;
540 /* the Linux driver does this to clear any pending ISAC interrupts */
542 v = ISAC_READ(I_RMODED);
543 #ifdef AVMA1PCI_V2_DEBUG
544 kprintf("avma1pp2_attach: I_MODED %x...", v);
546 v = ISAC_READ(I_ISTAD);
547 #ifdef AVMA1PCI_V2_DEBUG
548 kprintf("avma1pp2_attach: I_ISTAD %x...", v);
550 v = ISAC_READ(I_ISTA);
551 #ifdef AVMA1PCI_V2_DEBUG
552 kprintf("avma1pp2_attach: I_ISTA %x...", v);
554 ISAC_WRITE(I_MASKD, 0xff);
555 ISAC_WRITE(I_MASK, 0xff);
556 /* the Linux driver does this to clear any pending HSCX interrupts */
557 v = hscx_read_reg_int(0, sc);
558 #ifdef AVMA1PCI_V2_DEBUG
559 kprintf("avma1pp2_attach: 0 HSCX_STAT %x...", v);
561 v = hscx_read_reg_int(1, sc);
562 #ifdef AVMA1PCI_V2_DEBUG
563 kprintf("avma1pp2_attach: 1 HSCX_STAT %x\n", v);
566 bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_TIMERRESET);
567 DELAY(SEC_DELAY/100); /* 10 ms */
568 bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_ENABLE_INT);
569 DELAY(SEC_DELAY/100); /* 10 ms */
571 /* from here to the end would normally be done in isic_pciattach */
573 kprintf("ifpi2-%d: ISACSX %s\n", unit, "PSB3186");
576 ifpi2_isacsx_init(sc);
578 /* init the "HSCX" */
579 avma1pp2_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
581 avma1pp2_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
583 /* can't use the normal B-Channel stuff */
584 avma1pp2_init_linktab(sc);
586 /* set trace level */
588 sc->sc_trace = TRACE_OFF;
590 sc->sc_state = ISAC_IDLE;
602 sc->sc_freeflag2 = 0;
604 callout_init(&sc->sc_T3_timeout);
605 callout_init(&sc->sc_T4_timeout);
607 /* init higher protocol layers */
609 i4b_l1_mph_status_ind(L0IFPI2UNIT(sc->sc_unit), STI_ATTACH, sc->sc_cardtyp, &avma1pp2_l1mux_func);
617 * this is the real interrupt routine
620 avma1pp2_hscx_intr(int h_chan, u_int stat, struct l1_softc *sc)
622 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
626 NDBGL1(L1_H_IRQ, "%#x", stat);
628 if((stat & HSCX_INT_XDU) && (chan->bprot != BPROT_NONE))/* xmit data underrun */
631 NDBGL1(L1_H_XFRERR, "xmit data underrun");
632 /* abort the transmission */
634 sc->avma1pp_cmd |= HSCX_CMD_XRS;
635 AVMA1PPSETCMDLONG(param);
636 hscx_write_reg(h_chan, param, sc);
637 sc->avma1pp_cmd &= ~HSCX_CMD_XRS;
638 AVMA1PPSETCMDLONG(param);
639 hscx_write_reg(h_chan, param, sc);
641 if (chan->out_mbuf_head != NULL) /* don't continue to transmit this buffer */
643 i4b_Bfreembuf(chan->out_mbuf_head);
644 chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
649 * The following is based on examination of the Linux driver.
651 * The logic here is different than with a "real" HSCX; all kinds
652 * of information (interrupt/status bits) are in stat.
653 * HSCX_INT_RPR indicates a receive interrupt
654 * HSCX_STAT_RDO indicates an overrun condition, abort -
655 * otherwise read the bytes ((stat & HSCX_STZT_RML_MASK) >> 8)
656 * HSCX_STAT_RME indicates end-of-frame and apparently any
657 * CRC/framing errors are only reported in this state.
658 * if ((stat & HSCX_STAT_CRCVFRRAB) != HSCX_STAT_CRCVFR)
662 if(stat & HSCX_INT_RPR)
666 /* always have to read the FIFO, so use a scratch buffer */
667 u_char scrbuf[HSCX_FIFO_LEN];
669 if(stat & HSCX_STAT_RDO)
672 NDBGL1(L1_H_XFRERR, "receive data overflow");
677 * check whether we're receiving data for an inactive B-channel
678 * and discard it. This appears to happen for telephony when
679 * both B-channels are active and one is deactivated. Since
680 * it is not really possible to deactivate the channel in that
681 * case (the ASIC seems to deactivate _both_ channels), the
682 * "deactivated" channel keeps receiving data which can lead
683 * to exhaustion of mbufs and a kernel panic.
685 * This is a hack, but it's the only solution I can think of
686 * without having the documentation for the ASIC.
689 if (chan->state == HSCX_IDLE)
691 NDBGL1(L1_H_XFRERR, "toss data from %d", h_chan);
695 fifo_data_len = ((stat & HSCX_STAT_RML_MASK) >> 8);
697 if(fifo_data_len == 0)
698 fifo_data_len = sc->sc_bfifolen;
700 /* ALWAYS read data from HSCX fifo */
702 HSCX_RDFIFO(h_chan, scrbuf, fifo_data_len);
703 chan->rxcount += fifo_data_len;
705 /* all error conditions checked, now decide and take action */
709 if(chan->in_mbuf == NULL)
711 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
712 panic("L1 avma1pp2_hscx_intr: RME, cannot allocate mbuf!\n");
713 chan->in_cbptr = chan->in_mbuf->m_data;
717 if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
719 /* OK to copy the data */
720 bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
721 chan->in_cbptr += fifo_data_len;
722 chan->in_len += fifo_data_len;
724 /* setup mbuf data length */
726 chan->in_mbuf->m_len = chan->in_len;
727 chan->in_mbuf->m_pkthdr.len = chan->in_len;
729 if(sc->sc_trace & TRACE_B_RX)
732 hdr.unit = L0IFPI2UNIT(sc->sc_unit);
733 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
735 hdr.count = ++sc->sc_trace_bcount;
737 i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
740 if (stat & HSCX_STAT_RME)
742 if((stat & HSCX_STAT_CRCVFRRAB) == HSCX_STAT_CRCVFR)
744 (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
747 /* mark buffer ptr as unused */
749 chan->in_mbuf = NULL;
750 chan->in_cbptr = NULL;
756 NDBGL1(L1_H_XFRERR, "CRC/RAB");
757 if (chan->in_mbuf != NULL)
759 i4b_Bfreembuf(chan->in_mbuf);
760 chan->in_mbuf = NULL;
761 chan->in_cbptr = NULL;
766 } /* END enough space in mbuf */
769 if(chan->bprot == BPROT_NONE)
771 /* setup mbuf data length */
773 chan->in_mbuf->m_len = chan->in_len;
774 chan->in_mbuf->m_pkthdr.len = chan->in_len;
776 if(sc->sc_trace & TRACE_B_RX)
779 hdr.unit = L0IFPI2UNIT(sc->sc_unit);
780 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
782 hdr.count = ++sc->sc_trace_bcount;
784 i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
787 if(!(i4b_l1_bchan_tel_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
790 /* move rx'd data to rx queue */
792 if(!(IF_QFULL(&chan->rx_queue)))
794 IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
798 i4b_Bfreembuf(chan->in_mbuf);
800 /* signal upper layer that data are available */
801 (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
803 /* alloc new buffer */
805 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
806 panic("L1 avma1pp2_hscx_intr: RPF, cannot allocate new mbuf!\n");
808 /* setup new data ptr */
810 chan->in_cbptr = chan->in_mbuf->m_data;
812 /* OK to copy the data */
813 bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
815 chan->in_cbptr += fifo_data_len;
816 chan->in_len = fifo_data_len;
818 chan->rxcount += fifo_data_len;
822 NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RPF, in_len=%d", chan->in_len);
823 chan->in_cbptr = chan->in_mbuf->m_data;
827 } /* if(error == 0) */
830 /* land here for RDO */
831 if (chan->in_mbuf != NULL)
833 i4b_Bfreembuf(chan->in_mbuf);
834 chan->in_mbuf = NULL;
835 chan->in_cbptr = NULL;
839 sc->avma1pp_cmd |= HSCX_CMD_RRS;
840 AVMA1PPSETCMDLONG(param);
841 hscx_write_reg(h_chan, param, sc);
842 sc->avma1pp_cmd &= ~HSCX_CMD_RRS;
843 AVMA1PPSETCMDLONG(param);
844 hscx_write_reg(h_chan, param, sc);
849 /* transmit fifo empty, new data can be written to fifo */
851 if(stat & HSCX_INT_XPR)
854 * for a description what is going on here, please have
855 * a look at isic_bchannel_start() in i4b_bchan.c !
858 NDBGL1(L1_H_IRQ, "unit %d, chan %d - XPR, Tx Fifo Empty!", sc->sc_unit, h_chan);
860 if(chan->out_mbuf_cur == NULL) /* last frame is transmitted */
862 IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
864 if(chan->out_mbuf_head == NULL)
866 chan->state &= ~HSCX_TX_ACTIVE;
867 (*chan->isic_drvr_linktab->bch_tx_queue_empty)(chan->isic_drvr_linktab->unit);
871 chan->state |= HSCX_TX_ACTIVE;
872 chan->out_mbuf_cur = chan->out_mbuf_head;
873 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
874 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
876 if(sc->sc_trace & TRACE_B_TX)
879 hdr.unit = L0IFPI2UNIT(sc->sc_unit);
880 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
882 hdr.count = ++sc->sc_trace_bcount;
884 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
887 if(chan->bprot == BPROT_NONE)
889 if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
899 avma1pp2_hscx_fifo(chan, sc);
902 /* call timeout handling routine */
904 if(activity == ACT_RX || activity == ACT_TX)
905 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
909 * this is the main routine which checks each channel and then calls
910 * the real interrupt routine as appropriate
913 avma1pp2_hscx_int_handler(struct l1_softc *sc)
917 /* has to be a u_int because the byte count is in the 2nd byte */
918 stat = hscx_read_reg_int(0, sc);
919 if (stat & HSCX_INT_MASK)
920 avma1pp2_hscx_intr(0, stat, sc);
921 stat = hscx_read_reg_int(1, sc);
922 if (stat & HSCX_INT_MASK)
923 avma1pp2_hscx_intr(1, stat, sc);
927 avma1pp2_disable(device_t dev)
929 struct l1_softc *sc = device_get_softc(dev);
930 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
931 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
933 /* could still be wrong, but it seems to help */
934 bus_space_write_1(btag, bhandle, STAT0_OFFSET, 0x00);
938 avma1pp2_intr(void *xsc)
942 bus_space_handle_t bhandle;
943 bus_space_tag_t btag;
946 bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
947 btag = rman_get_bustag(sc->sc_resources.io_base[0]);
949 stat = bus_space_read_1(btag, bhandle, STAT0_OFFSET);
950 NDBGL1(L1_H_IRQ, "stat %x", stat);
951 /* was there an interrupt from this card ? */
952 if ((stat & ASL_IRQ_Pending) == 0)
954 /* For slow machines loop as long as an interrupt is active */
955 for (; ((stat & ASL_IRQ_Pending) != 0) ;)
957 /* interrupts are high active */
958 if (stat & ASL_IRQ_TIMER)
959 NDBGL1(L1_H_IRQ, "timer interrupt ???");
960 if (stat & ASL_IRQ_HSCX)
962 NDBGL1(L1_H_IRQ, "HSCX");
963 avma1pp2_hscx_int_handler(sc);
965 if (stat & ASL_IRQ_ISAC)
967 NDBGL1(L1_H_IRQ, "ISAC");
968 ifpi2_isacsx_intr(sc);
970 stat = bus_space_read_1(btag, bhandle, STAT0_OFFSET);
971 NDBGL1(L1_H_IRQ, "stat %x", stat);
977 avma1pp2_hscx_init(struct l1_softc *sc, int h_chan, int activate)
979 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
982 NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
983 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
985 sc->avma1pp_cmd = sc->avma1pp_prot = sc->avma1pp_txl = 0;
989 /* only deactivate if both channels are idle */
990 if (sc->sc_chan[HSCX_CH_A].state != HSCX_IDLE ||
991 sc->sc_chan[HSCX_CH_B].state != HSCX_IDLE)
995 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
996 sc->avma1pp_prot = HSCX_MODE_TRANS;
997 AVMA1PPSETCMDLONG(param);
998 hscx_write_reg(h_chan, param, sc);
1001 if(chan->bprot == BPROT_RHDLC)
1003 NDBGL1(L1_BCHAN, "BPROT_RHDLC");
1005 /* HDLC Frames, transparent mode 0 */
1006 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1007 sc->avma1pp_prot = HSCX_MODE_ITF_FLG;
1008 AVMA1PPSETCMDLONG(param);
1009 hscx_write_reg(h_chan, param, sc);
1010 sc->avma1pp_cmd = HSCX_CMD_XRS;
1011 AVMA1PPSETCMDLONG(param);
1012 hscx_write_reg(h_chan, param, sc);
1013 sc->avma1pp_cmd = 0;
1017 NDBGL1(L1_BCHAN, "BPROT_NONE??");
1019 /* Raw Telephony, extended transparent mode 1 */
1020 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1021 sc->avma1pp_prot = HSCX_MODE_TRANS;
1022 AVMA1PPSETCMDLONG(param);
1023 hscx_write_reg(h_chan, param, sc);
1024 sc->avma1pp_cmd = HSCX_CMD_XRS;
1025 AVMA1PPSETCMDLONG(param);
1026 hscx_write_reg(h_chan, param, sc);
1027 sc->avma1pp_cmd = 0;
1032 avma1pp2_bchannel_setup(int unit, int h_chan, int bprot, int activate)
1034 struct l1_softc *sc = ifpi2_scp[unit];
1035 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1042 chan->state = HSCX_IDLE;
1043 avma1pp2_hscx_init(sc, h_chan, activate);
1046 NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1047 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1051 chan->unit = sc->sc_unit; /* unit number */
1052 chan->channel = h_chan; /* B channel */
1053 chan->bprot = bprot; /* B channel protocol */
1054 chan->state = HSCX_IDLE; /* B channel state */
1058 chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1060 i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1062 chan->rxcount = 0; /* reset rx counter */
1064 i4b_Bfreembuf(chan->in_mbuf); /* clean rx mbuf */
1066 chan->in_mbuf = NULL; /* reset mbuf ptr */
1067 chan->in_cbptr = NULL; /* reset mbuf curr ptr */
1068 chan->in_len = 0; /* reset mbuf data len */
1070 /* transmitter part */
1072 chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1074 i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1076 chan->txcount = 0; /* reset tx counter */
1078 i4b_Bfreembuf(chan->out_mbuf_head); /* clean tx mbuf */
1080 chan->out_mbuf_head = NULL; /* reset head mbuf ptr */
1081 chan->out_mbuf_cur = NULL; /* reset current mbuf ptr */
1082 chan->out_mbuf_cur_ptr = NULL; /* reset current mbuf data ptr */
1083 chan->out_mbuf_cur_len = 0; /* reset current mbuf data cnt */
1088 avma1pp2_hscx_init(sc, h_chan, activate);
1089 chan->state |= HSCX_AVMA1PP_ACTIVE;
1096 avma1pp2_bchannel_start(int unit, int h_chan)
1098 struct l1_softc *sc = ifpi2_scp[unit];
1099 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1103 if(chan->state & HSCX_TX_ACTIVE) /* already running ? */
1106 return; /* yes, leave */
1109 /* get next mbuf from queue */
1111 IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
1113 if(chan->out_mbuf_head == NULL) /* queue empty ? */
1116 return; /* yes, exit */
1119 /* init current mbuf values */
1121 chan->out_mbuf_cur = chan->out_mbuf_head;
1122 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1123 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1125 /* activity indicator for timeout handling */
1127 if(chan->bprot == BPROT_NONE)
1129 if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
1137 chan->state |= HSCX_TX_ACTIVE; /* we start transmitting */
1139 if(sc->sc_trace & TRACE_B_TX) /* if trace, send mbuf to trace dev */
1141 i4b_trace_hdr_t hdr;
1142 hdr.unit = L0IFPI2UNIT(sc->sc_unit);
1143 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1145 hdr.count = ++sc->sc_trace_bcount;
1146 MICROTIME(hdr.time);
1147 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1150 avma1pp2_hscx_fifo(chan, sc);
1152 /* call timeout handling routine */
1154 if(activity == ACT_RX || activity == ACT_TX)
1155 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
1160 /*---------------------------------------------------------------------------*
1161 * return the address of isic drivers linktab
1162 *---------------------------------------------------------------------------*/
1163 static isdn_link_t *
1164 avma1pp2_ret_linktab(int unit, int channel)
1166 struct l1_softc *sc = ifpi2_scp[unit];
1167 l1_bchan_state_t *chan = &sc->sc_chan[channel];
1169 return(&chan->isic_isdn_linktab);
1172 /*---------------------------------------------------------------------------*
1173 * set the driver linktab in the b channel softc
1174 *---------------------------------------------------------------------------*/
1176 avma1pp2_set_linktab(int unit, int channel, drvr_link_t *dlt)
1178 struct l1_softc *sc = ifpi2_scp[unit];
1179 l1_bchan_state_t *chan = &sc->sc_chan[channel];
1181 chan->isic_drvr_linktab = dlt;
1185 /*---------------------------------------------------------------------------*
1186 * initialize our local linktab
1187 *---------------------------------------------------------------------------*/
1189 avma1pp2_init_linktab(struct l1_softc *sc)
1191 l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
1192 isdn_link_t *lt = &chan->isic_isdn_linktab;
1194 /* make sure the hardware driver is known to layer 4 */
1195 /* avoid overwriting if already set */
1196 if (ctrl_types[CTRL_PASSIVE].set_linktab == NULL)
1198 ctrl_types[CTRL_PASSIVE].set_linktab = i4b_l1_set_linktab;
1199 ctrl_types[CTRL_PASSIVE].get_linktab = i4b_l1_ret_linktab;
1203 lt->unit = sc->sc_unit;
1204 lt->channel = HSCX_CH_A;
1205 lt->bch_config = avma1pp2_bchannel_setup;
1206 lt->bch_tx_start = avma1pp2_bchannel_start;
1207 lt->bch_stat = avma1pp2_bchannel_stat;
1208 lt->tx_queue = &chan->tx_queue;
1210 /* used by non-HDLC data transfers, i.e. telephony drivers */
1211 lt->rx_queue = &chan->rx_queue;
1213 /* used by HDLC data transfers, i.e. ipr and isp drivers */
1214 lt->rx_mbuf = &chan->in_mbuf;
1216 chan = &sc->sc_chan[HSCX_CH_B];
1217 lt = &chan->isic_isdn_linktab;
1219 lt->unit = sc->sc_unit;
1220 lt->channel = HSCX_CH_B;
1221 lt->bch_config = avma1pp2_bchannel_setup;
1222 lt->bch_tx_start = avma1pp2_bchannel_start;
1223 lt->bch_stat = avma1pp2_bchannel_stat;
1224 lt->tx_queue = &chan->tx_queue;
1226 /* used by non-HDLC data transfers, i.e. telephony drivers */
1227 lt->rx_queue = &chan->rx_queue;
1229 /* used by HDLC data transfers, i.e. ipr and isp drivers */
1230 lt->rx_mbuf = &chan->in_mbuf;
1234 * use this instead of isic_bchannel_stat in i4b_bchan.c because it's static
1237 avma1pp2_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp)
1239 struct l1_softc *sc = ifpi2_scp[unit];
1240 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1244 bsp->outbytes = chan->txcount;
1245 bsp->inbytes = chan->rxcount;
1253 /*---------------------------------------------------------------------------*
1254 * fill HSCX fifo with data from the current mbuf
1255 * Put this here until it can go into i4b_hscx.c
1256 *---------------------------------------------------------------------------*/
1258 avma1pp2_hscx_fifo(l1_bchan_state_t *chan, struct l1_softc *sc)
1264 /* using a scratch buffer simplifies writing to the FIFO */
1265 u_char scrbuf[HSCX_FIFO_LEN];
1270 * fill the HSCX tx fifo with data from the current mbuf. if
1271 * current mbuf holds less data than HSCX fifo length, try to
1272 * get the next mbuf from (a possible) mbuf chain. if there is
1273 * not enough data in a single mbuf or in a chain, then this
1274 * is the last mbuf and we tell the HSCX that it has to send
1275 * CRC and closing flag
1278 while(chan->out_mbuf_cur && len != sc->sc_bfifolen)
1280 nextlen = min(chan->out_mbuf_cur_len, sc->sc_bfifolen - len);
1283 kprintf("i:mh=%p, mc=%p, mcp=%p, mcl=%d l=%d nl=%d # ",
1284 chan->out_mbuf_head,
1286 chan->out_mbuf_cur_ptr,
1287 chan->out_mbuf_cur_len,
1292 cmd |= HSCX_CMDR_XTF;
1293 /* collect the data in the scratch buffer */
1294 for (i = 0; i < nextlen; i++)
1295 scrbuf[i + len] = chan->out_mbuf_cur_ptr[i];
1298 chan->txcount += nextlen;
1300 chan->out_mbuf_cur_ptr += nextlen;
1301 chan->out_mbuf_cur_len -= nextlen;
1303 if(chan->out_mbuf_cur_len == 0)
1305 if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
1307 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1308 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1310 if(sc->sc_trace & TRACE_B_TX)
1312 i4b_trace_hdr_t hdr;
1313 hdr.unit = L0IFPI2UNIT(sc->sc_unit);
1314 hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1316 hdr.count = ++sc->sc_trace_bcount;
1317 MICROTIME(hdr.time);
1318 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1323 if (chan->bprot != BPROT_NONE)
1324 cmd |= HSCX_CMDR_XME;
1325 i4b_Bfreembuf(chan->out_mbuf_head);
1326 chan->out_mbuf_head = NULL;
1330 /* write what we have from the scratch buf to the HSCX fifo */
1332 HSCX_WRFIFO(chan->channel, scrbuf, len);
1336 /*---------------------------------------------------------------------------*
1337 * ifpi2 - ISAC interrupt routine
1338 *---------------------------------------------------------------------------*/
1340 ifpi2_isacsx_intr(struct l1_softc *sc)
1342 u_char isacsx_irq_stat;
1346 /* get isac irq status */
1347 /* ISTA tells us whether it was a C/I or HDLC int. */
1348 isacsx_irq_stat = ISAC_READ(I_ISTA);
1351 ifpi2_isacsx_irq(sc, isacsx_irq_stat); /* isac handler */
1356 ISAC_WRITE(I_MASKD, 0xff);
1357 ISAC_WRITE(I_MASK, 0xff);
1361 ISAC_WRITE(I_MASKD, isacsx_imaskd);
1362 ISAC_WRITE(I_MASK, isacsx_imask);
1365 /*---------------------------------------------------------------------------*
1366 * ifpi2_recover - try to recover from irq lockup
1367 *---------------------------------------------------------------------------*/
1369 ifpi2_recover(struct l1_softc *sc)
1371 kprintf("ifpi2_recover %d\n", sc->sc_unit);
1372 #if 0 /* fix me later */
1375 /* get isac irq status */
1377 byte = ISAC_READ(I_ISTA);
1379 NDBGL1(L1_ERROR, " ISAC: ISTA = 0x%x", byte);
1381 if(byte & ISACSX_ISTA_EXI)
1382 NDBGL1(L1_ERROR, " ISAC: EXIR = 0x%x", (u_char)ISAC_READ(I_EXIR));
1384 if(byte & ISACSX_ISTA_CISQ)
1386 byte = ISAC_READ(I_CIRR);
1388 NDBGL1(L1_ERROR, " ISAC: CISQ = 0x%x", byte);
1390 if(byte & ISACSX_CIRR_SQC)
1391 NDBGL1(L1_ERROR, " ISAC: SQRR = 0x%x", (u_char)ISAC_READ(I_SQRR));
1394 NDBGL1(L1_ERROR, " ISAC: IMASK = 0x%x", ISACSX_IMASK);
1396 ISAC_WRITE(I_MASKD, 0xff);
1397 ISAC_WRITE(I_MASK, 0xff);
1399 ISAC_WRITE(I_MASKD, isacsx_imaskd);
1400 ISAC_WRITE(I_MASK, isacsx_imask);
1405 #endif /* NIFPI2 > 0 */