1 /******************************************************************************
3 Copyright (c) 2006-2009, Myricom Inc.
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Neither the name of the Myricom Inc, nor the names of its
13 contributors may be used to endorse or promote products derived from
14 this software without specific prior written permission.
16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 POSSIBILITY OF SUCH DAMAGE.
28 $FreeBSD: src/sys/dev/mxge/if_mxge.c,v 1.63 2009/06/26 11:45:06 rwatson Exp $
30 ***************************************************************************/
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/linker.h>
35 #include <sys/firmware.h>
36 #include <sys/endian.h>
37 #include <sys/in_cksum.h>
38 #include <sys/sockio.h>
40 #include <sys/malloc.h>
41 #include <sys/kernel.h>
42 #include <sys/module.h>
43 #include <sys/serialize.h>
44 #include <sys/socket.h>
45 #include <sys/sysctl.h>
47 /* count xmits ourselves, rather than via drbr */
50 #include <net/if_arp.h>
51 #include <net/ifq_var.h>
52 #include <net/ethernet.h>
53 #include <net/if_dl.h>
54 #include <net/if_media.h>
58 #include <net/if_types.h>
59 #include <net/vlan/if_vlan_var.h>
62 #include <netinet/in_systm.h>
63 #include <netinet/in.h>
64 #include <netinet/ip.h>
65 #include <netinet/tcp.h>
70 #include <bus/pci/pcireg.h>
71 #include <bus/pci/pcivar.h>
72 #include <bus/pci/pci_private.h> /* XXX for pci_cfg_restore */
74 #include <vm/vm.h> /* for pmap_mapdev() */
77 #if defined(__i386) || defined(__x86_64)
78 #include <machine/specialreg.h>
81 #include <dev/netif/mxge/mxge_mcp.h>
82 #include <dev/netif/mxge/mcp_gen_header.h>
83 /*#define MXGE_FAKE_IFP*/
84 #include <dev/netif/mxge/if_mxge_var.h>
86 #include <sys/buf_ring.h>
92 static int mxge_nvidia_ecrc_enable = 1;
93 static int mxge_force_firmware = 0;
94 static int mxge_intr_coal_delay = 30;
95 static int mxge_deassert_wait = 1;
96 static int mxge_flow_control = 1;
97 static int mxge_verbose = 0;
98 static int mxge_lro_cnt = 8;
99 static int mxge_ticks;
100 static int mxge_max_slices = 1;
101 static int mxge_rss_hash_type = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
102 static int mxge_always_promisc = 0;
104 /* static int mxge_initial_mtu = ETHERMTU_JUMBO; */
105 static int mxge_initial_mtu = ETHERMTU;
106 static char *mxge_fw_unaligned = "mxge_ethp_z8e";
107 static char *mxge_fw_aligned = "mxge_eth_z8e";
108 static char *mxge_fw_rss_aligned = "mxge_rss_eth_z8e";
109 static char *mxge_fw_rss_unaligned = "mxge_rss_ethp_z8e";
111 static int mxge_probe(device_t dev);
112 static int mxge_attach(device_t dev);
113 static int mxge_detach(device_t dev);
114 static int mxge_shutdown(device_t dev);
115 static void mxge_intr(void *arg);
117 static device_method_t mxge_methods[] =
119 /* Device interface */
120 DEVMETHOD(device_probe, mxge_probe),
121 DEVMETHOD(device_attach, mxge_attach),
122 DEVMETHOD(device_detach, mxge_detach),
123 DEVMETHOD(device_shutdown, mxge_shutdown),
127 static driver_t mxge_driver =
131 sizeof(mxge_softc_t),
134 static devclass_t mxge_devclass;
136 /* Declare ourselves to be a child of the PCI bus.*/
137 DRIVER_MODULE(mxge, pci, mxge_driver, mxge_devclass, NULL, NULL);
138 MODULE_DEPEND(mxge, firmware, 1, 1, 1);
139 MODULE_DEPEND(mxge, zlib, 1, 1, 1);
141 static int mxge_load_firmware(mxge_softc_t *sc, int adopt);
142 static int mxge_send_cmd(mxge_softc_t *sc, uint32_t cmd, mxge_cmd_t *data);
143 static int mxge_close(mxge_softc_t *sc);
144 static int mxge_open(mxge_softc_t *sc);
145 static void mxge_tick(void *arg);
147 /* XXX: we don't have Large Receive Offload support yet */
149 mxge_lro_rx(struct mxge_slice_state *ss, struct mbuf *m_head, uint32_t csum)
158 mxge_lro_flush(struct mxge_slice_state *ss, struct lro_entry *lro)
165 mxge_probe(device_t dev)
170 if ((pci_get_vendor(dev) == MXGE_PCI_VENDOR_MYRICOM) &&
171 ((pci_get_device(dev) == MXGE_PCI_DEVICE_Z8E) ||
172 (pci_get_device(dev) == MXGE_PCI_DEVICE_Z8E_9))) {
173 rev = pci_get_revid(dev);
175 case MXGE_PCI_REV_Z8E:
176 device_set_desc(dev, "Myri10G-PCIE-8A");
178 case MXGE_PCI_REV_Z8ES:
179 device_set_desc(dev, "Myri10G-PCIE-8B");
182 device_set_desc(dev, "Myri10G-PCIE-8??");
183 device_printf(dev, "Unrecognized rev %d NIC\n",
193 mxge_enable_wc(mxge_softc_t *sc)
196 #if defined(__i386) || defined(__x86_64)
201 len = rman_get_size(sc->mem_res);
202 err = pmap_change_attr((vm_offset_t) sc->sram,
203 len, PAT_WRITE_COMBINING);
205 device_printf(sc->dev, "pmap_change_attr failed, %d\n",
211 sc->wc = 0; /* TBD: PAT support */
216 /* callback to get our DMA address */
218 mxge_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nsegs,
222 *(bus_addr_t *) arg = segs->ds_addr;
227 mxge_dma_alloc(mxge_softc_t *sc, mxge_dma_t *dma, size_t bytes,
228 bus_size_t alignment)
231 device_t dev = sc->dev;
232 bus_size_t boundary, maxsegsize;
234 if (bytes > 4096 && alignment == 4096) {
242 /* allocate DMAable memory tags */
243 err = bus_dma_tag_create(sc->parent_dmat, /* parent */
244 alignment, /* alignment */
245 boundary, /* boundary */
246 BUS_SPACE_MAXADDR, /* low */
247 BUS_SPACE_MAXADDR, /* high */
248 NULL, NULL, /* filter */
251 maxsegsize, /* maxsegsize */
252 BUS_DMA_COHERENT, /* flags */
253 &dma->dmat); /* tag */
255 device_printf(dev, "couldn't alloc tag (err = %d)\n", err);
259 /* allocate DMAable memory & map */
260 err = bus_dmamem_alloc(dma->dmat, &dma->addr,
261 (BUS_DMA_WAITOK | BUS_DMA_COHERENT
262 | BUS_DMA_ZERO), &dma->map);
264 device_printf(dev, "couldn't alloc mem (err = %d)\n", err);
265 goto abort_with_dmat;
268 /* load the memory */
269 err = bus_dmamap_load(dma->dmat, dma->map, dma->addr, bytes,
270 mxge_dmamap_callback,
271 (void *)&dma->bus_addr, 0);
273 device_printf(dev, "couldn't load map (err = %d)\n", err);
279 bus_dmamem_free(dma->dmat, dma->addr, dma->map);
281 (void)bus_dma_tag_destroy(dma->dmat);
287 mxge_dma_free(mxge_dma_t *dma)
289 bus_dmamap_unload(dma->dmat, dma->map);
290 bus_dmamem_free(dma->dmat, dma->addr, dma->map);
291 (void)bus_dma_tag_destroy(dma->dmat);
295 * The eeprom strings on the lanaiX have the format
302 mxge_parse_strings(mxge_softc_t *sc)
304 #define MXGE_NEXT_STRING(p) while(ptr < limit && *ptr++)
309 ptr = sc->eeprom_strings;
310 limit = sc->eeprom_strings + MXGE_EEPROM_STRINGS_SIZE;
312 while (ptr < limit && *ptr != '\0') {
313 if (memcmp(ptr, "MAC=", 4) == 0) {
315 sc->mac_addr_string = ptr;
316 for (i = 0; i < 6; i++) {
318 if ((ptr + 2) > limit)
320 sc->mac_addr[i] = strtoul(ptr, NULL, 16);
323 } else if (memcmp(ptr, "PC=", 3) == 0) {
325 strncpy(sc->product_code_string, ptr,
326 sizeof (sc->product_code_string) - 1);
327 } else if (memcmp(ptr, "SN=", 3) == 0) {
329 strncpy(sc->serial_number_string, ptr,
330 sizeof (sc->serial_number_string) - 1);
332 MXGE_NEXT_STRING(ptr);
339 device_printf(sc->dev, "failed to parse eeprom_strings\n");
344 #if defined __i386 || defined i386 || defined __i386__ || defined __x86_64__
346 mxge_enable_nvidia_ecrc(mxge_softc_t *sc)
349 unsigned long base, off;
351 device_t pdev, mcp55;
352 uint16_t vendor_id, device_id, word;
353 uintptr_t bus, slot, func, ivend, idev;
357 if (!mxge_nvidia_ecrc_enable)
360 pdev = device_get_parent(device_get_parent(sc->dev));
362 device_printf(sc->dev, "could not find parent?\n");
365 vendor_id = pci_read_config(pdev, PCIR_VENDOR, 2);
366 device_id = pci_read_config(pdev, PCIR_DEVICE, 2);
368 if (vendor_id != 0x10de)
373 if (device_id == 0x005d) {
374 /* ck804, base address is magic */
376 } else if (device_id >= 0x0374 && device_id <= 0x378) {
377 /* mcp55, base address stored in chipset */
378 mcp55 = pci_find_bsf(0, 0, 0);
380 0x10de == pci_read_config(mcp55, PCIR_VENDOR, 2) &&
381 0x0369 == pci_read_config(mcp55, PCIR_DEVICE, 2)) {
382 word = pci_read_config(mcp55, 0x90, 2);
383 base = ((unsigned long)word & 0x7ffeU) << 25;
390 Test below is commented because it is believed that doing
391 config read/write beyond 0xff will access the config space
392 for the next larger function. Uncomment this and remove
393 the hacky pmap_mapdev() way of accessing config space when
394 FreeBSD grows support for extended pcie config space access
397 /* See if we can, by some miracle, access the extended
399 val = pci_read_config(pdev, 0x178, 4);
400 if (val != 0xffffffff) {
402 pci_write_config(pdev, 0x178, val, 4);
406 /* Rather than using normal pci config space writes, we must
407 * map the Nvidia config space ourselves. This is because on
408 * opteron/nvidia class machine the 0xe000000 mapping is
409 * handled by the nvidia chipset, that means the internal PCI
410 * device (the on-chip northbridge), or the amd-8131 bridge
411 * and things behind them are not visible by this method.
414 BUS_READ_IVAR(device_get_parent(pdev), pdev,
416 BUS_READ_IVAR(device_get_parent(pdev), pdev,
417 PCI_IVAR_SLOT, &slot);
418 BUS_READ_IVAR(device_get_parent(pdev), pdev,
419 PCI_IVAR_FUNCTION, &func);
420 BUS_READ_IVAR(device_get_parent(pdev), pdev,
421 PCI_IVAR_VENDOR, &ivend);
422 BUS_READ_IVAR(device_get_parent(pdev), pdev,
423 PCI_IVAR_DEVICE, &idev);
426 + 0x00100000UL * (unsigned long)bus
427 + 0x00001000UL * (unsigned long)(func
430 /* map it into the kernel */
431 va = pmap_mapdev(trunc_page((vm_paddr_t)off), PAGE_SIZE);
435 device_printf(sc->dev, "pmap_kenter_temporary didn't\n");
438 /* get a pointer to the config space mapped into the kernel */
439 cfgptr = va + (off & PAGE_MASK);
441 /* make sure that we can really access it */
442 vendor_id = *(uint16_t *)(cfgptr + PCIR_VENDOR);
443 device_id = *(uint16_t *)(cfgptr + PCIR_DEVICE);
444 if (! (vendor_id == ivend && device_id == idev)) {
445 device_printf(sc->dev, "mapping failed: 0x%x:0x%x\n",
446 vendor_id, device_id);
447 pmap_unmapdev((vm_offset_t)va, PAGE_SIZE);
451 ptr32 = (uint32_t*)(cfgptr + 0x178);
454 if (val == 0xffffffff) {
455 device_printf(sc->dev, "extended mapping failed\n");
456 pmap_unmapdev((vm_offset_t)va, PAGE_SIZE);
460 pmap_unmapdev((vm_offset_t)va, PAGE_SIZE);
462 device_printf(sc->dev,
463 "Enabled ECRC on upstream Nvidia bridge "
465 (int)bus, (int)slot, (int)func);
470 mxge_enable_nvidia_ecrc(mxge_softc_t *sc)
472 device_printf(sc->dev,
473 "Nforce 4 chipset on non-x86/x86_64!?!?!\n");
480 mxge_dma_test(mxge_softc_t *sc, int test_type)
483 bus_addr_t dmatest_bus = sc->dmabench_dma.bus_addr;
489 /* Run a small DMA test.
490 * The magic multipliers to the length tell the firmware
491 * to do DMA read, write, or read+write tests. The
492 * results are returned in cmd.data0. The upper 16
493 * bits of the return is the number of transfers completed.
494 * The lower 16 bits is the time in 0.5us ticks that the
495 * transfers took to complete.
498 len = sc->tx_boundary;
500 cmd.data0 = MXGE_LOWPART_TO_U32(dmatest_bus);
501 cmd.data1 = MXGE_HIGHPART_TO_U32(dmatest_bus);
502 cmd.data2 = len * 0x10000;
503 status = mxge_send_cmd(sc, test_type, &cmd);
508 sc->read_dma = ((cmd.data0>>16) * len * 2) /
509 (cmd.data0 & 0xffff);
510 cmd.data0 = MXGE_LOWPART_TO_U32(dmatest_bus);
511 cmd.data1 = MXGE_HIGHPART_TO_U32(dmatest_bus);
512 cmd.data2 = len * 0x1;
513 status = mxge_send_cmd(sc, test_type, &cmd);
518 sc->write_dma = ((cmd.data0>>16) * len * 2) /
519 (cmd.data0 & 0xffff);
521 cmd.data0 = MXGE_LOWPART_TO_U32(dmatest_bus);
522 cmd.data1 = MXGE_HIGHPART_TO_U32(dmatest_bus);
523 cmd.data2 = len * 0x10001;
524 status = mxge_send_cmd(sc, test_type, &cmd);
529 sc->read_write_dma = ((cmd.data0>>16) * len * 2 * 2) /
530 (cmd.data0 & 0xffff);
533 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
534 device_printf(sc->dev, "DMA %s benchmark failed: %d\n",
541 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
542 * when the PCI-E Completion packets are aligned on an 8-byte
543 * boundary. Some PCI-E chip sets always align Completion packets; on
544 * the ones that do not, the alignment can be enforced by enabling
545 * ECRC generation (if supported).
547 * When PCI-E Completion packets are not aligned, it is actually more
548 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
550 * If the driver can neither enable ECRC nor verify that it has
551 * already been enabled, then it must use a firmware image which works
552 * around unaligned completion packets (ethp_z8e.dat), and it should
553 * also ensure that it never gives the device a Read-DMA which is
554 * larger than 2KB by setting the tx_boundary to 2KB. If ECRC is
555 * enabled, then the driver should use the aligned (eth_z8e.dat)
556 * firmware image, and set tx_boundary to 4KB.
560 mxge_firmware_probe(mxge_softc_t *sc)
562 device_t dev = sc->dev;
566 sc->tx_boundary = 4096;
568 * Verify the max read request size was set to 4KB
569 * before trying the test with 4KB.
571 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) {
572 pectl = pci_read_config(dev, reg + 0x8, 2);
573 if ((pectl & (5 << 12)) != (5 << 12)) {
574 device_printf(dev, "Max Read Req. size != 4k (0x%x\n",
576 sc->tx_boundary = 2048;
581 * load the optimized firmware (which assumes aligned PCIe
582 * completions) in order to see if it works on this host.
584 sc->fw_name = mxge_fw_aligned;
585 status = mxge_load_firmware(sc, 1);
591 * Enable ECRC if possible
593 mxge_enable_nvidia_ecrc(sc);
596 * Run a DMA test which watches for unaligned completions and
597 * aborts on the first one seen.
600 status = mxge_dma_test(sc, MXGEFW_CMD_UNALIGNED_TEST);
602 return 0; /* keep the aligned firmware */
605 device_printf(dev, "DMA test failed: %d\n", status);
606 if (status == ENOSYS)
607 device_printf(dev, "Falling back to ethp! "
608 "Please install up to date fw\n");
613 mxge_select_firmware(mxge_softc_t *sc)
618 if (mxge_force_firmware != 0) {
619 if (mxge_force_firmware == 1)
624 device_printf(sc->dev,
625 "Assuming %s completions (forced)\n",
626 aligned ? "aligned" : "unaligned");
630 /* if the PCIe link width is 4 or less, we can use the aligned
631 firmware and skip any checks */
632 if (sc->link_width != 0 && sc->link_width <= 4) {
633 device_printf(sc->dev,
634 "PCIe x%d Link, expect reduced performance\n",
640 if (0 == mxge_firmware_probe(sc))
645 sc->fw_name = mxge_fw_aligned;
646 sc->tx_boundary = 4096;
648 sc->fw_name = mxge_fw_unaligned;
649 sc->tx_boundary = 2048;
651 return (mxge_load_firmware(sc, 0));
661 mxge_validate_firmware(mxge_softc_t *sc, const mcp_gen_header_t *hdr)
665 if (be32toh(hdr->mcp_type) != MCP_TYPE_ETH) {
666 device_printf(sc->dev, "Bad firmware type: 0x%x\n",
667 be32toh(hdr->mcp_type));
671 /* save firmware version for sysctl */
672 strncpy(sc->fw_version, hdr->version, sizeof (sc->fw_version));
674 device_printf(sc->dev, "firmware id: %s\n", hdr->version);
676 ksscanf(sc->fw_version, "%d.%d.%d", &sc->fw_ver_major,
677 &sc->fw_ver_minor, &sc->fw_ver_tiny);
679 if (!(sc->fw_ver_major == MXGEFW_VERSION_MAJOR
680 && sc->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
681 device_printf(sc->dev, "Found firmware version %s\n",
683 device_printf(sc->dev, "Driver needs %d.%d\n",
684 MXGEFW_VERSION_MAJOR, MXGEFW_VERSION_MINOR);
692 z_alloc(void *nil, u_int items, u_int size)
696 ptr = kmalloc(items * size, M_TEMP, M_NOWAIT);
701 z_free(void *nil, void *ptr)
708 mxge_load_firmware_helper(mxge_softc_t *sc, uint32_t *limit)
711 char *inflate_buffer;
712 const struct firmware *fw;
713 const mcp_gen_header_t *hdr;
719 fw = firmware_get(sc->fw_name);
721 device_printf(sc->dev, "Could not find firmware image %s\n",
728 /* setup zlib and decompress f/w */
729 bzero(&zs, sizeof (zs));
732 status = inflateInit(&zs);
733 if (status != Z_OK) {
738 /* the uncompressed size is stored as the firmware version,
739 which would otherwise go unused */
740 fw_len = (size_t) fw->version;
741 inflate_buffer = kmalloc(fw_len, M_TEMP, M_NOWAIT);
742 if (inflate_buffer == NULL)
744 zs.avail_in = fw->datasize;
745 zs.next_in = __DECONST(char *, fw->data);
746 zs.avail_out = fw_len;
747 zs.next_out = inflate_buffer;
748 status = inflate(&zs, Z_FINISH);
749 if (status != Z_STREAM_END) {
750 device_printf(sc->dev, "zlib %d\n", status);
752 goto abort_with_buffer;
756 hdr_offset = htobe32(*(const uint32_t *)
757 (inflate_buffer + MCP_HEADER_PTR_OFFSET));
758 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw_len) {
759 device_printf(sc->dev, "Bad firmware file");
761 goto abort_with_buffer;
763 hdr = (const void*)(inflate_buffer + hdr_offset);
765 status = mxge_validate_firmware(sc, hdr);
767 goto abort_with_buffer;
769 /* Copy the inflated firmware to NIC SRAM. */
770 for (i = 0; i < fw_len; i += 256) {
771 mxge_pio_copy(sc->sram + MXGE_FW_OFFSET + i,
773 min(256U, (unsigned)(fw_len - i)));
781 kfree(inflate_buffer, M_TEMP);
785 firmware_put(fw, FIRMWARE_UNLOAD);
790 * Enable or disable periodic RDMAs from the host to make certain
791 * chipsets resend dropped PCIe messages
795 mxge_dummy_rdma(mxge_softc_t *sc, int enable)
798 volatile uint32_t *confirm;
799 volatile char *submit;
800 uint32_t *buf, dma_low, dma_high;
803 buf = (uint32_t *)((unsigned long)(buf_bytes + 7) & ~7UL);
805 /* clear confirmation addr */
806 confirm = (volatile uint32_t *)sc->cmd;
810 /* send an rdma command to the PCIe engine, and wait for the
811 response in the confirmation address. The firmware should
812 write a -1 there to indicate it is alive and well
815 dma_low = MXGE_LOWPART_TO_U32(sc->cmd_dma.bus_addr);
816 dma_high = MXGE_HIGHPART_TO_U32(sc->cmd_dma.bus_addr);
817 buf[0] = htobe32(dma_high); /* confirm addr MSW */
818 buf[1] = htobe32(dma_low); /* confirm addr LSW */
819 buf[2] = htobe32(0xffffffff); /* confirm data */
820 dma_low = MXGE_LOWPART_TO_U32(sc->zeropad_dma.bus_addr);
821 dma_high = MXGE_HIGHPART_TO_U32(sc->zeropad_dma.bus_addr);
822 buf[3] = htobe32(dma_high); /* dummy addr MSW */
823 buf[4] = htobe32(dma_low); /* dummy addr LSW */
824 buf[5] = htobe32(enable); /* enable? */
827 submit = (volatile char *)(sc->sram + MXGEFW_BOOT_DUMMY_RDMA);
829 mxge_pio_copy(submit, buf, 64);
834 while (*confirm != 0xffffffff && i < 20) {
838 if (*confirm != 0xffffffff) {
839 device_printf(sc->dev, "dummy rdma %s failed (%p = 0x%x)",
840 (enable ? "enable" : "disable"), confirm,
847 mxge_send_cmd(mxge_softc_t *sc, uint32_t cmd, mxge_cmd_t *data)
850 char buf_bytes[sizeof(*buf) + 8];
851 volatile mcp_cmd_response_t *response = sc->cmd;
852 volatile char *cmd_addr = sc->sram + MXGEFW_ETH_CMD;
853 uint32_t dma_low, dma_high;
854 int err, sleep_total = 0;
857 * We may be called during attach, before if_serializer is available.
858 * This is not a fast path, just check for NULL
861 if (sc->ifp->if_serializer)
862 ASSERT_SERIALIZED(sc->ifp->if_serializer);
864 /* ensure buf is aligned to 8 bytes */
865 buf = (mcp_cmd_t *)((unsigned long)(buf_bytes + 7) & ~7UL);
867 buf->data0 = htobe32(data->data0);
868 buf->data1 = htobe32(data->data1);
869 buf->data2 = htobe32(data->data2);
870 buf->cmd = htobe32(cmd);
871 dma_low = MXGE_LOWPART_TO_U32(sc->cmd_dma.bus_addr);
872 dma_high = MXGE_HIGHPART_TO_U32(sc->cmd_dma.bus_addr);
874 buf->response_addr.low = htobe32(dma_low);
875 buf->response_addr.high = htobe32(dma_high);
878 response->result = 0xffffffff;
880 mxge_pio_copy((volatile void *)cmd_addr, buf, sizeof (*buf));
882 /* wait up to 20ms */
884 for (sleep_total = 0; sleep_total < 20; sleep_total++) {
885 bus_dmamap_sync(sc->cmd_dma.dmat,
886 sc->cmd_dma.map, BUS_DMASYNC_POSTREAD);
888 switch (be32toh(response->result)) {
890 data->data0 = be32toh(response->data);
896 case MXGEFW_CMD_UNKNOWN:
899 case MXGEFW_CMD_ERROR_UNALIGNED:
902 case MXGEFW_CMD_ERROR_BUSY:
906 device_printf(sc->dev,
908 "failed, result = %d\n",
909 cmd, be32toh(response->result));
917 device_printf(sc->dev, "mxge: command %d timed out"
919 cmd, be32toh(response->result));
924 mxge_adopt_running_firmware(mxge_softc_t *sc)
926 struct mcp_gen_header *hdr;
927 const size_t bytes = sizeof (struct mcp_gen_header);
931 /* find running firmware header */
932 hdr_offset = htobe32(*(volatile uint32_t *)
933 (sc->sram + MCP_HEADER_PTR_OFFSET));
935 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > sc->sram_size) {
936 device_printf(sc->dev,
937 "Running firmware has bad header offset (%d)\n",
942 /* copy header of running firmware from SRAM to host memory to
943 * validate firmware */
944 hdr = kmalloc(bytes, M_DEVBUF, M_NOWAIT);
946 device_printf(sc->dev, "could not kmalloc firmware hdr\n");
949 bus_space_read_region_1(rman_get_bustag(sc->mem_res),
950 rman_get_bushandle(sc->mem_res),
951 hdr_offset, (char *)hdr, bytes);
952 status = mxge_validate_firmware(sc, hdr);
953 kfree(hdr, M_DEVBUF);
956 * check to see if adopted firmware has bug where adopting
957 * it will cause broadcasts to be filtered unless the NIC
958 * is kept in ALLMULTI mode
960 if (sc->fw_ver_major == 1 && sc->fw_ver_minor == 4 &&
961 sc->fw_ver_tiny >= 4 && sc->fw_ver_tiny <= 11) {
962 sc->adopted_rx_filter_bug = 1;
963 device_printf(sc->dev, "Adopting fw %d.%d.%d: "
964 "working around rx filter bug\n",
965 sc->fw_ver_major, sc->fw_ver_minor,
974 mxge_load_firmware(mxge_softc_t *sc, int adopt)
976 volatile uint32_t *confirm;
977 volatile char *submit;
979 uint32_t *buf, size, dma_low, dma_high;
982 buf = (uint32_t *)((unsigned long)(buf_bytes + 7) & ~7UL);
984 size = sc->sram_size;
985 status = mxge_load_firmware_helper(sc, &size);
989 /* Try to use the currently running firmware, if
991 status = mxge_adopt_running_firmware(sc);
993 device_printf(sc->dev,
994 "failed to adopt running firmware\n");
997 device_printf(sc->dev,
998 "Successfully adopted running firmware\n");
999 if (sc->tx_boundary == 4096) {
1000 device_printf(sc->dev,
1001 "Using firmware currently running on NIC"
1003 device_printf(sc->dev,
1004 "performance consider loading optimized "
1007 sc->fw_name = mxge_fw_unaligned;
1008 sc->tx_boundary = 2048;
1011 /* clear confirmation addr */
1012 confirm = (volatile uint32_t *)sc->cmd;
1015 /* send a reload command to the bootstrap MCP, and wait for the
1016 response in the confirmation address. The firmware should
1017 write a -1 there to indicate it is alive and well
1020 dma_low = MXGE_LOWPART_TO_U32(sc->cmd_dma.bus_addr);
1021 dma_high = MXGE_HIGHPART_TO_U32(sc->cmd_dma.bus_addr);
1023 buf[0] = htobe32(dma_high); /* confirm addr MSW */
1024 buf[1] = htobe32(dma_low); /* confirm addr LSW */
1025 buf[2] = htobe32(0xffffffff); /* confirm data */
1027 /* FIX: All newest firmware should un-protect the bottom of
1028 the sram before handoff. However, the very first interfaces
1029 do not. Therefore the handoff copy must skip the first 8 bytes
1031 /* where the code starts*/
1032 buf[3] = htobe32(MXGE_FW_OFFSET + 8);
1033 buf[4] = htobe32(size - 8); /* length of code */
1034 buf[5] = htobe32(8); /* where to copy to */
1035 buf[6] = htobe32(0); /* where to jump to */
1037 submit = (volatile char *)(sc->sram + MXGEFW_BOOT_HANDOFF);
1038 mxge_pio_copy(submit, buf, 64);
1043 while (*confirm != 0xffffffff && i < 20) {
1046 bus_dmamap_sync(sc->cmd_dma.dmat,
1047 sc->cmd_dma.map, BUS_DMASYNC_POSTREAD);
1049 if (*confirm != 0xffffffff) {
1050 device_printf(sc->dev,"handoff failed (%p = 0x%x)",
1059 mxge_update_mac_address(mxge_softc_t *sc)
1062 uint8_t *addr = sc->mac_addr;
1066 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
1067 | (addr[2] << 8) | addr[3]);
1069 cmd.data1 = ((addr[4] << 8) | (addr[5]));
1071 status = mxge_send_cmd(sc, MXGEFW_SET_MAC_ADDRESS, &cmd);
1076 mxge_change_pause(mxge_softc_t *sc, int pause)
1082 status = mxge_send_cmd(sc, MXGEFW_ENABLE_FLOW_CONTROL,
1085 status = mxge_send_cmd(sc, MXGEFW_DISABLE_FLOW_CONTROL,
1089 device_printf(sc->dev, "Failed to set flow control mode\n");
1097 mxge_change_promisc(mxge_softc_t *sc, int promisc)
1102 if( sc->ifp->if_serializer)
1103 ASSERT_SERIALIZED(sc->ifp->if_serializer);
1104 if (mxge_always_promisc)
1108 status = mxge_send_cmd(sc, MXGEFW_ENABLE_PROMISC,
1111 status = mxge_send_cmd(sc, MXGEFW_DISABLE_PROMISC,
1115 device_printf(sc->dev, "Failed to set promisc mode\n");
1120 mxge_set_multicast_list(mxge_softc_t *sc)
1123 struct ifmultiaddr *ifma;
1124 struct ifnet *ifp = sc->ifp;
1127 if (ifp->if_serializer)
1128 ASSERT_SERIALIZED(ifp->if_serializer);
1130 /* This firmware is known to not support multicast */
1131 if (!sc->fw_multicast_support)
1134 /* Disable multicast filtering while we play with the lists*/
1135 err = mxge_send_cmd(sc, MXGEFW_ENABLE_ALLMULTI, &cmd);
1137 device_printf(sc->dev, "Failed MXGEFW_ENABLE_ALLMULTI,"
1138 " error status: %d\n", err);
1142 if (sc->adopted_rx_filter_bug)
1145 if (ifp->if_flags & IFF_ALLMULTI)
1146 /* request to disable multicast filtering, so quit here */
1149 /* Flush all the filters */
1151 err = mxge_send_cmd(sc, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS, &cmd);
1153 device_printf(sc->dev,
1154 "Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
1155 ", error status: %d\n", err);
1159 /* Walk the multicast list, and add each address */
1161 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1162 if (ifma->ifma_addr->sa_family != AF_LINK)
1164 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1166 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr) + 4,
1168 cmd.data0 = htonl(cmd.data0);
1169 cmd.data1 = htonl(cmd.data1);
1170 err = mxge_send_cmd(sc, MXGEFW_JOIN_MULTICAST_GROUP, &cmd);
1172 device_printf(sc->dev, "Failed "
1173 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
1175 /* abort, leaving multicast filtering off */
1179 /* Enable multicast filtering */
1180 err = mxge_send_cmd(sc, MXGEFW_DISABLE_ALLMULTI, &cmd);
1182 device_printf(sc->dev, "Failed MXGEFW_DISABLE_ALLMULTI"
1183 ", error status: %d\n", err);
1188 mxge_max_mtu(mxge_softc_t *sc)
1193 if (MJUMPAGESIZE - MXGEFW_PAD > MXGEFW_MAX_MTU)
1194 return MXGEFW_MAX_MTU - MXGEFW_PAD;
1196 /* try to set nbufs to see if it we can
1197 use virtually contiguous jumbos */
1199 status = mxge_send_cmd(sc, MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS,
1202 return MXGEFW_MAX_MTU - MXGEFW_PAD;
1204 /* otherwise, we're limited to MJUMPAGESIZE */
1205 return MJUMPAGESIZE - MXGEFW_PAD;
1209 mxge_reset(mxge_softc_t *sc, int interrupts_setup)
1211 struct mxge_slice_state *ss;
1212 mxge_rx_done_t *rx_done;
1213 volatile uint32_t *irq_claim;
1217 /* try to send a reset command to the card to see if it
1219 memset(&cmd, 0, sizeof (cmd));
1220 status = mxge_send_cmd(sc, MXGEFW_CMD_RESET, &cmd);
1222 device_printf(sc->dev, "failed reset\n");
1226 mxge_dummy_rdma(sc, 1);
1229 /* set the intrq size */
1230 cmd.data0 = sc->rx_ring_size;
1231 status = mxge_send_cmd(sc, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd);
1234 * Even though we already know how many slices are supported
1235 * via mxge_slice_probe(), MXGEFW_CMD_GET_MAX_RSS_QUEUES
1236 * has magic side effects, and must be called after a reset.
1237 * It must be called prior to calling any RSS related cmds,
1238 * including assigning an interrupt queue for anything but
1239 * slice 0. It must also be called *after*
1240 * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
1241 * the firmware to compute offsets.
1244 if (sc->num_slices > 1) {
1245 /* ask the maximum number of slices it supports */
1246 status = mxge_send_cmd(sc, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
1249 device_printf(sc->dev,
1250 "failed to get number of slices\n");
1254 * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
1255 * to setting up the interrupt queue DMA
1257 cmd.data0 = sc->num_slices;
1258 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
1259 #ifdef IFNET_BUF_RING
1260 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
1262 status = mxge_send_cmd(sc, MXGEFW_CMD_ENABLE_RSS_QUEUES,
1265 device_printf(sc->dev,
1266 "failed to set number of slices\n");
1272 if (interrupts_setup) {
1273 /* Now exchange information about interrupts */
1274 for (slice = 0; slice < sc->num_slices; slice++) {
1275 rx_done = &sc->ss[slice].rx_done;
1276 memset(rx_done->entry, 0, sc->rx_ring_size);
1277 cmd.data0 = MXGE_LOWPART_TO_U32(rx_done->dma.bus_addr);
1278 cmd.data1 = MXGE_HIGHPART_TO_U32(rx_done->dma.bus_addr);
1280 status |= mxge_send_cmd(sc,
1281 MXGEFW_CMD_SET_INTRQ_DMA,
1286 status |= mxge_send_cmd(sc,
1287 MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd);
1290 sc->intr_coal_delay_ptr = (volatile uint32_t *)(sc->sram + cmd.data0);
1292 status |= mxge_send_cmd(sc, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd);
1293 irq_claim = (volatile uint32_t *)(sc->sram + cmd.data0);
1296 status |= mxge_send_cmd(sc, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
1298 sc->irq_deassert = (volatile uint32_t *)(sc->sram + cmd.data0);
1300 device_printf(sc->dev, "failed set interrupt parameters\n");
1305 *sc->intr_coal_delay_ptr = htobe32(sc->intr_coal_delay);
1308 /* run a DMA benchmark */
1309 (void) mxge_dma_test(sc, MXGEFW_DMA_TEST);
1311 for (slice = 0; slice < sc->num_slices; slice++) {
1312 ss = &sc->ss[slice];
1314 ss->irq_claim = irq_claim + (2 * slice);
1315 /* reset mcp/driver shared state back to 0 */
1316 ss->rx_done.idx = 0;
1317 ss->rx_done.cnt = 0;
1320 ss->tx.pkt_done = 0;
1321 ss->tx.queue_active = 0;
1322 ss->tx.activate = 0;
1323 ss->tx.deactivate = 0;
1328 ss->rx_small.cnt = 0;
1329 ss->lro_bad_csum = 0;
1331 ss->lro_flushed = 0;
1332 if (ss->fw_stats != NULL) {
1333 ss->fw_stats->valid = 0;
1334 ss->fw_stats->send_done_count = 0;
1337 sc->rdma_tags_available = 15;
1338 status = mxge_update_mac_address(sc);
1339 mxge_change_promisc(sc, sc->ifp->if_flags & IFF_PROMISC);
1340 mxge_change_pause(sc, sc->pause);
1341 mxge_set_multicast_list(sc);
1346 mxge_change_intr_coal(SYSCTL_HANDLER_ARGS)
1349 unsigned int intr_coal_delay;
1353 intr_coal_delay = sc->intr_coal_delay;
1354 err = sysctl_handle_int(oidp, &intr_coal_delay, arg2, req);
1358 if (intr_coal_delay == sc->intr_coal_delay)
1361 if (intr_coal_delay == 0 || intr_coal_delay > 1000*1000)
1364 lwkt_serialize_enter(sc->ifp->if_serializer);
1365 *sc->intr_coal_delay_ptr = htobe32(intr_coal_delay);
1366 sc->intr_coal_delay = intr_coal_delay;
1368 lwkt_serialize_exit(sc->ifp->if_serializer);
1373 mxge_change_flow_control(SYSCTL_HANDLER_ARGS)
1376 unsigned int enabled;
1380 enabled = sc->pause;
1381 err = sysctl_handle_int(oidp, &enabled, arg2, req);
1385 if (enabled == sc->pause)
1388 lwkt_serialize_enter(sc->ifp->if_serializer);
1389 err = mxge_change_pause(sc, enabled);
1390 lwkt_serialize_exit(sc->ifp->if_serializer);
1395 mxge_change_lro_locked(mxge_softc_t *sc, int lro_cnt)
1402 ifp->if_capenable &= ~IFCAP_LRO;
1404 ifp->if_capenable |= IFCAP_LRO;
1405 sc->lro_cnt = lro_cnt;
1406 if (ifp->if_flags & IFF_RUNNING) {
1408 err = mxge_open(sc);
1414 mxge_change_lro(SYSCTL_HANDLER_ARGS)
1417 unsigned int lro_cnt;
1421 lro_cnt = sc->lro_cnt;
1422 err = sysctl_handle_int(oidp, &lro_cnt, arg2, req);
1426 if (lro_cnt == sc->lro_cnt)
1432 lwkt_serialize_enter(sc->ifp->if_serializer);
1433 err = mxge_change_lro_locked(sc, lro_cnt);
1434 lwkt_serialize_exit(sc->ifp->if_serializer);
1439 mxge_handle_be32(SYSCTL_HANDLER_ARGS)
1445 arg2 = be32toh(*(int *)arg1);
1447 err = sysctl_handle_int(oidp, arg1, arg2, req);
1453 mxge_rem_sysctls(mxge_softc_t *sc)
1455 struct mxge_slice_state *ss;
1458 if (sc->slice_sysctl_tree == NULL)
1461 for (slice = 0; slice < sc->num_slices; slice++) {
1462 ss = &sc->ss[slice];
1463 if (ss == NULL || ss->sysctl_tree == NULL)
1465 sysctl_ctx_free(&ss->sysctl_ctx);
1466 ss->sysctl_tree = NULL;
1468 sysctl_ctx_free(&sc->slice_sysctl_ctx);
1469 sc->slice_sysctl_tree = NULL;
1470 sysctl_ctx_free(&sc->sysctl_ctx);
1471 sc->sysctl_tree = NULL;
1476 mxge_add_sysctls(mxge_softc_t *sc)
1478 struct sysctl_ctx_list *ctx;
1479 struct sysctl_oid_list *children;
1481 struct mxge_slice_state *ss;
1485 ctx = &sc->sysctl_ctx;
1486 sysctl_ctx_init(ctx);
1487 sc->sysctl_tree = SYSCTL_ADD_NODE(ctx, SYSCTL_STATIC_CHILDREN(_hw),
1489 device_get_nameunit(sc->dev),
1491 if (sc->sysctl_tree == NULL) {
1492 device_printf(sc->dev, "can't add sysctl node\n");
1496 children = SYSCTL_CHILDREN(sc->sysctl_tree);
1497 fw = sc->ss[0].fw_stats;
1499 /* random information */
1500 SYSCTL_ADD_STRING(ctx, children, OID_AUTO,
1502 CTLFLAG_RD, &sc->fw_version,
1503 0, "firmware version");
1504 SYSCTL_ADD_STRING(ctx, children, OID_AUTO,
1506 CTLFLAG_RD, &sc->serial_number_string,
1507 0, "serial number");
1508 SYSCTL_ADD_STRING(ctx, children, OID_AUTO,
1510 CTLFLAG_RD, &sc->product_code_string,
1512 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1514 CTLFLAG_RD, &sc->link_width,
1516 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1518 CTLFLAG_RD, &sc->tx_boundary,
1520 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1522 CTLFLAG_RD, &sc->wc,
1523 0, "write combining PIO?");
1524 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1526 CTLFLAG_RD, &sc->read_dma,
1527 0, "DMA Read speed in MB/s");
1528 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1530 CTLFLAG_RD, &sc->write_dma,
1531 0, "DMA Write speed in MB/s");
1532 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1533 "read_write_dma_MBs",
1534 CTLFLAG_RD, &sc->read_write_dma,
1535 0, "DMA concurrent Read/Write speed in MB/s");
1538 /* performance related tunables */
1539 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1541 CTLTYPE_INT|CTLFLAG_RW, sc,
1542 0, mxge_change_intr_coal,
1543 "I", "interrupt coalescing delay in usecs");
1545 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1546 "flow_control_enabled",
1547 CTLTYPE_INT|CTLFLAG_RW, sc,
1548 0, mxge_change_flow_control,
1549 "I", "interrupt coalescing delay in usecs");
1551 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1553 CTLFLAG_RW, &mxge_deassert_wait,
1554 0, "Wait for IRQ line to go low in ihandler");
1556 /* stats block from firmware is in network byte order.
1558 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1560 CTLTYPE_INT|CTLFLAG_RD, &fw->link_up,
1561 0, mxge_handle_be32,
1563 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1564 "rdma_tags_available",
1565 CTLTYPE_INT|CTLFLAG_RD, &fw->rdma_tags_available,
1566 0, mxge_handle_be32,
1567 "I", "rdma_tags_available");
1568 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1569 "dropped_bad_crc32",
1570 CTLTYPE_INT|CTLFLAG_RD,
1571 &fw->dropped_bad_crc32,
1572 0, mxge_handle_be32,
1573 "I", "dropped_bad_crc32");
1574 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1576 CTLTYPE_INT|CTLFLAG_RD,
1577 &fw->dropped_bad_phy,
1578 0, mxge_handle_be32,
1579 "I", "dropped_bad_phy");
1580 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1581 "dropped_link_error_or_filtered",
1582 CTLTYPE_INT|CTLFLAG_RD,
1583 &fw->dropped_link_error_or_filtered,
1584 0, mxge_handle_be32,
1585 "I", "dropped_link_error_or_filtered");
1586 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1587 "dropped_link_overflow",
1588 CTLTYPE_INT|CTLFLAG_RD, &fw->dropped_link_overflow,
1589 0, mxge_handle_be32,
1590 "I", "dropped_link_overflow");
1591 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1592 "dropped_multicast_filtered",
1593 CTLTYPE_INT|CTLFLAG_RD,
1594 &fw->dropped_multicast_filtered,
1595 0, mxge_handle_be32,
1596 "I", "dropped_multicast_filtered");
1597 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1598 "dropped_no_big_buffer",
1599 CTLTYPE_INT|CTLFLAG_RD, &fw->dropped_no_big_buffer,
1600 0, mxge_handle_be32,
1601 "I", "dropped_no_big_buffer");
1602 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1603 "dropped_no_small_buffer",
1604 CTLTYPE_INT|CTLFLAG_RD,
1605 &fw->dropped_no_small_buffer,
1606 0, mxge_handle_be32,
1607 "I", "dropped_no_small_buffer");
1608 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1610 CTLTYPE_INT|CTLFLAG_RD, &fw->dropped_overrun,
1611 0, mxge_handle_be32,
1612 "I", "dropped_overrun");
1613 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1615 CTLTYPE_INT|CTLFLAG_RD,
1617 0, mxge_handle_be32,
1618 "I", "dropped_pause");
1619 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1621 CTLTYPE_INT|CTLFLAG_RD, &fw->dropped_runt,
1622 0, mxge_handle_be32,
1623 "I", "dropped_runt");
1625 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1626 "dropped_unicast_filtered",
1627 CTLTYPE_INT|CTLFLAG_RD, &fw->dropped_unicast_filtered,
1628 0, mxge_handle_be32,
1629 "I", "dropped_unicast_filtered");
1631 /* verbose printing? */
1632 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1634 CTLFLAG_RW, &mxge_verbose,
1635 0, "verbose printing");
1638 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1640 CTLTYPE_INT|CTLFLAG_RW, sc,
1642 "I", "number of lro merge queues");
1645 /* add counters exported for debugging from all slices */
1646 sysctl_ctx_init(&sc->slice_sysctl_ctx);
1647 sc->slice_sysctl_tree =
1648 SYSCTL_ADD_NODE(&sc->slice_sysctl_ctx, children, OID_AUTO,
1649 "slice", CTLFLAG_RD, 0, "");
1651 for (slice = 0; slice < sc->num_slices; slice++) {
1652 ss = &sc->ss[slice];
1653 sysctl_ctx_init(&ss->sysctl_ctx);
1654 ctx = &ss->sysctl_ctx;
1655 children = SYSCTL_CHILDREN(sc->slice_sysctl_tree);
1656 ksprintf(slice_num, "%d", slice);
1658 SYSCTL_ADD_NODE(ctx, children, OID_AUTO, slice_num,
1660 children = SYSCTL_CHILDREN(ss->sysctl_tree);
1661 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1663 CTLFLAG_RD, &ss->rx_small.cnt,
1665 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1667 CTLFLAG_RD, &ss->rx_big.cnt,
1669 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1670 "lro_flushed", CTLFLAG_RD, &ss->lro_flushed,
1671 0, "number of lro merge queues flushed");
1673 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1674 "lro_queued", CTLFLAG_RD, &ss->lro_queued,
1675 0, "number of frames appended to lro merge"
1678 #ifndef IFNET_BUF_RING
1679 /* only transmit from slice 0 for now */
1683 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1685 CTLFLAG_RD, &ss->tx.req,
1688 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1690 CTLFLAG_RD, &ss->tx.done,
1692 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1694 CTLFLAG_RD, &ss->tx.pkt_done,
1696 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1698 CTLFLAG_RD, &ss->tx.stall,
1700 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1702 CTLFLAG_RD, &ss->tx.wake,
1704 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1706 CTLFLAG_RD, &ss->tx.defrag,
1708 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1710 CTLFLAG_RD, &ss->tx.queue_active,
1711 0, "tx_queue_active");
1712 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1714 CTLFLAG_RD, &ss->tx.activate,
1716 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1718 CTLFLAG_RD, &ss->tx.deactivate,
1719 0, "tx_deactivate");
1723 /* copy an array of mcp_kreq_ether_send_t's to the mcp. Copy
1724 backwards one at a time and handle ring wraps */
1727 mxge_submit_req_backwards(mxge_tx_ring_t *tx,
1728 mcp_kreq_ether_send_t *src, int cnt)
1730 int idx, starting_slot;
1731 starting_slot = tx->req;
1734 idx = (starting_slot + cnt) & tx->mask;
1735 mxge_pio_copy(&tx->lanai[idx],
1736 &src[cnt], sizeof(*src));
1742 * copy an array of mcp_kreq_ether_send_t's to the mcp. Copy
1743 * at most 32 bytes at a time, so as to avoid involving the software
1744 * pio handler in the nic. We re-write the first segment's flags
1745 * to mark them valid only after writing the entire chain
1749 mxge_submit_req(mxge_tx_ring_t *tx, mcp_kreq_ether_send_t *src,
1754 volatile uint32_t *dst_ints;
1755 mcp_kreq_ether_send_t *srcp;
1756 volatile mcp_kreq_ether_send_t *dstp, *dst;
1759 idx = tx->req & tx->mask;
1761 last_flags = src->flags;
1764 dst = dstp = &tx->lanai[idx];
1767 if ((idx + cnt) < tx->mask) {
1768 for (i = 0; i < (cnt - 1); i += 2) {
1769 mxge_pio_copy(dstp, srcp, 2 * sizeof(*src));
1770 wmb(); /* force write every 32 bytes */
1775 /* submit all but the first request, and ensure
1776 that it is submitted below */
1777 mxge_submit_req_backwards(tx, src, cnt);
1781 /* submit the first request */
1782 mxge_pio_copy(dstp, srcp, sizeof(*src));
1783 wmb(); /* barrier before setting valid flag */
1786 /* re-write the last 32-bits with the valid flags */
1787 src->flags = last_flags;
1788 src_ints = (uint32_t *)src;
1790 dst_ints = (volatile uint32_t *)dst;
1792 *dst_ints = *src_ints;
1800 mxge_encap_tso(struct mxge_slice_state *ss, struct mbuf *m,
1801 int busdma_seg_cnt, int ip_off)
1804 mcp_kreq_ether_send_t *req;
1805 bus_dma_segment_t *seg;
1808 uint32_t low, high_swapped;
1809 int len, seglen, cum_len, cum_len_next;
1810 int next_is_first, chop, cnt, rdma_count, small;
1811 uint16_t pseudo_hdr_offset, cksum_offset, mss;
1812 uint8_t flags, flags_next;
1815 mss = m->m_pkthdr.tso_segsz;
1817 /* negative cum_len signifies to the
1818 * send loop that we are still in the
1819 * header portion of the TSO packet.
1822 /* ensure we have the ethernet, IP and TCP
1823 header together in the first mbuf, copy
1824 it to a scratch buffer if not */
1825 if (__predict_false(m->m_len < ip_off + sizeof (*ip))) {
1826 m_copydata(m, 0, ip_off + sizeof (*ip),
1828 ip = (struct ip *)(ss->scratch + ip_off);
1830 ip = (struct ip *)(mtod(m, char *) + ip_off);
1832 if (__predict_false(m->m_len < ip_off + (ip->ip_hl << 2)
1834 m_copydata(m, 0, ip_off + (ip->ip_hl << 2)
1835 + sizeof (*tcp), ss->scratch);
1836 ip = (struct ip *)(mtod(m, char *) + ip_off);
1839 tcp = (struct tcphdr *)((char *)ip + (ip->ip_hl << 2));
1840 cum_len = -(ip_off + ((ip->ip_hl + tcp->th_off) << 2));
1842 /* TSO implies checksum offload on this hardware */
1843 cksum_offset = ip_off + (ip->ip_hl << 2);
1844 flags = MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST;
1847 /* for TSO, pseudo_hdr_offset holds mss.
1848 * The firmware figures out where to put
1849 * the checksum by parsing the header. */
1850 pseudo_hdr_offset = htobe16(mss);
1857 /* "rdma_count" is the number of RDMAs belonging to the
1858 * current packet BEFORE the current send request. For
1859 * non-TSO packets, this is equal to "count".
1860 * For TSO packets, rdma_count needs to be reset
1861 * to 0 after a segment cut.
1863 * The rdma_count field of the send request is
1864 * the number of RDMAs of the packet starting at
1865 * that request. For TSO send requests with one ore more cuts
1866 * in the middle, this is the number of RDMAs starting
1867 * after the last cut in the request. All previous
1868 * segments before the last cut implicitly have 1 RDMA.
1870 * Since the number of RDMAs is not known beforehand,
1871 * it must be filled-in retroactively - after each
1872 * segmentation cut or at the end of the entire packet.
1875 while (busdma_seg_cnt) {
1876 /* Break the busdma segment up into pieces*/
1877 low = MXGE_LOWPART_TO_U32(seg->ds_addr);
1878 high_swapped = htobe32(MXGE_HIGHPART_TO_U32(seg->ds_addr));
1882 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
1884 cum_len_next = cum_len + seglen;
1885 (req-rdma_count)->rdma_count = rdma_count + 1;
1886 if (__predict_true(cum_len >= 0)) {
1888 chop = (cum_len_next > mss);
1889 cum_len_next = cum_len_next % mss;
1890 next_is_first = (cum_len_next == 0);
1891 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
1892 flags_next |= next_is_first *
1894 rdma_count |= -(chop | next_is_first);
1895 rdma_count += chop & !next_is_first;
1896 } else if (cum_len_next >= 0) {
1901 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
1902 flags_next = MXGEFW_FLAGS_TSO_PLD |
1903 MXGEFW_FLAGS_FIRST |
1904 (small * MXGEFW_FLAGS_SMALL);
1907 req->addr_high = high_swapped;
1908 req->addr_low = htobe32(low);
1909 req->pseudo_hdr_offset = pseudo_hdr_offset;
1911 req->rdma_count = 1;
1912 req->length = htobe16(seglen);
1913 req->cksum_offset = cksum_offset;
1914 req->flags = flags | ((cum_len & 1) *
1915 MXGEFW_FLAGS_ALIGN_ODD);
1918 cum_len = cum_len_next;
1923 if (__predict_false(cksum_offset > seglen))
1924 cksum_offset -= seglen;
1927 if (__predict_false(cnt > tx->max_desc))
1933 (req-rdma_count)->rdma_count = rdma_count;
1937 req->flags |= MXGEFW_FLAGS_TSO_LAST;
1938 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP | MXGEFW_FLAGS_FIRST)));
1940 tx->info[((cnt - 1) + tx->req) & tx->mask].flag = 1;
1941 mxge_submit_req(tx, tx->req_list, cnt);
1942 #ifdef IFNET_BUF_RING
1943 if ((ss->sc->num_slices > 1) && tx->queue_active == 0) {
1944 /* tell the NIC to start polling this slice */
1946 tx->queue_active = 1;
1954 bus_dmamap_unload(tx->dmat, tx->info[tx->req & tx->mask].map);
1958 kprintf("tx->max_desc exceeded via TSO!\n");
1959 kprintf("mss = %d, %ld, %d!\n", mss,
1960 (long)seg - (long)tx->seg_list, tx->max_desc);
1967 #endif /* IFCAP_TSO4 */
1969 #ifdef MXGE_NEW_VLAN_API
1971 * We reproduce the software vlan tag insertion from
1972 * net/if_vlan.c:vlan_start() here so that we can advertise "hardware"
1973 * vlan tag insertion. We need to advertise this in order to have the
1974 * vlan interface respect our csum offload flags.
1976 static struct mbuf *
1977 mxge_vlan_tag_insert(struct mbuf *m)
1979 struct ether_vlan_header *evl;
1981 M_PREPEND(m, EVL_ENCAPLEN, MB_DONTWAIT);
1982 if (__predict_false(m == NULL))
1984 if (m->m_len < sizeof(*evl)) {
1985 m = m_pullup(m, sizeof(*evl));
1986 if (__predict_false(m == NULL))
1990 * Transform the Ethernet header into an Ethernet header
1991 * with 802.1Q encapsulation.
1993 evl = mtod(m, struct ether_vlan_header *);
1994 bcopy((char *)evl + EVL_ENCAPLEN,
1995 (char *)evl, ETHER_HDR_LEN - ETHER_TYPE_LEN);
1996 evl->evl_encap_proto = htons(ETHERTYPE_VLAN);
1997 evl->evl_tag = htons(m->m_pkthdr.ether_vlantag);
1998 m->m_flags &= ~M_VLANTAG;
2001 #endif /* MXGE_NEW_VLAN_API */
2004 mxge_encap(struct mxge_slice_state *ss, struct mbuf *m)
2007 mcp_kreq_ether_send_t *req;
2008 bus_dma_segment_t *seg;
2012 int cnt, cum_len, err, i, idx, odd_flag, ip_off;
2013 uint16_t pseudo_hdr_offset;
2014 uint8_t flags, cksum_offset;
2020 ip_off = sizeof (struct ether_header);
2021 #ifdef MXGE_NEW_VLAN_API
2022 if (m->m_flags & M_VLANTAG) {
2023 m = mxge_vlan_tag_insert(m);
2024 if (__predict_false(m == NULL))
2026 ip_off += EVL_ENCAPLEN;
2029 /* (try to) map the frame for DMA */
2030 idx = tx->req & tx->mask;
2031 err = bus_dmamap_load_mbuf_segment(tx->dmat, tx->info[idx].map,
2032 m, tx->seg_list, 1, &cnt,
2034 if (__predict_false(err == EFBIG)) {
2035 /* Too many segments in the chain. Try
2037 m_tmp = m_defrag(m, MB_DONTWAIT);
2038 if (m_tmp == NULL) {
2043 err = bus_dmamap_load_mbuf_segment(tx->dmat,
2045 m, tx->seg_list, 1, &cnt,
2048 if (__predict_false(err != 0)) {
2049 device_printf(sc->dev, "bus_dmamap_load_mbuf_segment returned %d"
2050 " packet len = %d\n", err, m->m_pkthdr.len);
2053 bus_dmamap_sync(tx->dmat, tx->info[idx].map,
2054 BUS_DMASYNC_PREWRITE);
2055 tx->info[idx].m = m;
2058 /* TSO is different enough, we handle it in another routine */
2059 if (m->m_pkthdr.csum_flags & (CSUM_TSO)) {
2060 mxge_encap_tso(ss, m, cnt, ip_off);
2067 pseudo_hdr_offset = 0;
2068 flags = MXGEFW_FLAGS_NO_TSO;
2070 /* checksum offloading? */
2071 if (m->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2072 /* ensure ip header is in first mbuf, copy
2073 it to a scratch buffer if not */
2074 if (__predict_false(m->m_len < ip_off + sizeof (*ip))) {
2075 m_copydata(m, 0, ip_off + sizeof (*ip),
2077 ip = (struct ip *)(ss->scratch + ip_off);
2079 ip = (struct ip *)(mtod(m, char *) + ip_off);
2081 cksum_offset = ip_off + (ip->ip_hl << 2);
2082 pseudo_hdr_offset = cksum_offset + m->m_pkthdr.csum_data;
2083 pseudo_hdr_offset = htobe16(pseudo_hdr_offset);
2084 req->cksum_offset = cksum_offset;
2085 flags |= MXGEFW_FLAGS_CKSUM;
2086 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2090 if (m->m_pkthdr.len < MXGEFW_SEND_SMALL_SIZE)
2091 flags |= MXGEFW_FLAGS_SMALL;
2093 /* convert segments into a request list */
2096 req->flags = MXGEFW_FLAGS_FIRST;
2097 for (i = 0; i < cnt; i++) {
2099 htobe32(MXGE_LOWPART_TO_U32(seg->ds_addr));
2101 htobe32(MXGE_HIGHPART_TO_U32(seg->ds_addr));
2102 req->length = htobe16(seg->ds_len);
2103 req->cksum_offset = cksum_offset;
2104 if (cksum_offset > seg->ds_len)
2105 cksum_offset -= seg->ds_len;
2108 req->pseudo_hdr_offset = pseudo_hdr_offset;
2109 req->pad = 0; /* complete solid 16-byte block */
2110 req->rdma_count = 1;
2111 req->flags |= flags | ((cum_len & 1) * odd_flag);
2112 cum_len += seg->ds_len;
2118 /* pad runts to 60 bytes */
2122 htobe32(MXGE_LOWPART_TO_U32(sc->zeropad_dma.bus_addr));
2124 htobe32(MXGE_HIGHPART_TO_U32(sc->zeropad_dma.bus_addr));
2125 req->length = htobe16(60 - cum_len);
2126 req->cksum_offset = 0;
2127 req->pseudo_hdr_offset = pseudo_hdr_offset;
2128 req->pad = 0; /* complete solid 16-byte block */
2129 req->rdma_count = 1;
2130 req->flags |= flags | ((cum_len & 1) * odd_flag);
2134 tx->req_list[0].rdma_count = cnt;
2136 /* print what the firmware will see */
2137 for (i = 0; i < cnt; i++) {
2138 kprintf("%d: addr: 0x%x 0x%x len:%d pso%d,"
2139 "cso:%d, flags:0x%x, rdma:%d\n",
2140 i, (int)ntohl(tx->req_list[i].addr_high),
2141 (int)ntohl(tx->req_list[i].addr_low),
2142 (int)ntohs(tx->req_list[i].length),
2143 (int)ntohs(tx->req_list[i].pseudo_hdr_offset),
2144 tx->req_list[i].cksum_offset, tx->req_list[i].flags,
2145 tx->req_list[i].rdma_count);
2147 kprintf("--------------\n");
2149 tx->info[((cnt - 1) + tx->req) & tx->mask].flag = 1;
2150 mxge_submit_req(tx, tx->req_list, cnt);
2151 #ifdef IFNET_BUF_RING
2152 if ((ss->sc->num_slices > 1) && tx->queue_active == 0) {
2153 /* tell the NIC to start polling this slice */
2155 tx->queue_active = 1;
2169 mxge_start_locked(struct mxge_slice_state *ss)
2179 while ((tx->mask - (tx->req - tx->done)) > tx->max_desc) {
2180 m = ifq_dequeue(&ifp->if_snd, NULL);
2184 /* let BPF see it */
2187 /* give it to the nic */
2190 /* ran out of transmit slots */
2191 if (!ifq_is_oactive(&ifp->if_snd)) {
2192 ifq_set_oactive(&ifp->if_snd);
2198 mxge_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
2200 mxge_softc_t *sc = ifp->if_softc;
2201 struct mxge_slice_state *ss;
2203 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
2204 ASSERT_SERIALIZED(sc->ifp->if_serializer);
2205 /* only use the first slice for now */
2207 mxge_start_locked(ss);
2211 * copy an array of mcp_kreq_ether_recv_t's to the mcp. Copy
2212 * at most 32 bytes at a time, so as to avoid involving the software
2213 * pio handler in the nic. We re-write the first segment's low
2214 * DMA address to mark it valid only after we write the entire chunk
2218 mxge_submit_8rx(volatile mcp_kreq_ether_recv_t *dst,
2219 mcp_kreq_ether_recv_t *src)
2223 low = src->addr_low;
2224 src->addr_low = 0xffffffff;
2225 mxge_pio_copy(dst, src, 4 * sizeof (*src));
2227 mxge_pio_copy(dst + 4, src + 4, 4 * sizeof (*src));
2229 src->addr_low = low;
2230 dst->addr_low = low;
2235 mxge_get_buf_small(struct mxge_slice_state *ss, bus_dmamap_t map, int idx)
2237 bus_dma_segment_t seg;
2239 mxge_rx_ring_t *rx = &ss->rx_small;
2242 m = m_gethdr(MB_DONTWAIT, MT_DATA);
2248 m->m_len = m->m_pkthdr.len = MHLEN;
2249 err = bus_dmamap_load_mbuf_segment(rx->dmat, map, m,
2250 &seg, 1, &cnt, BUS_DMA_NOWAIT);
2252 kprintf("can't dmamap small (%d)\n", err);
2256 rx->info[idx].m = m;
2257 rx->shadow[idx].addr_low =
2258 htobe32(MXGE_LOWPART_TO_U32(seg.ds_addr));
2259 rx->shadow[idx].addr_high =
2260 htobe32(MXGE_HIGHPART_TO_U32(seg.ds_addr));
2264 mxge_submit_8rx(&rx->lanai[idx - 7], &rx->shadow[idx - 7]);
2270 mxge_get_buf_big(struct mxge_slice_state *ss, bus_dmamap_t map, int idx)
2272 bus_dma_segment_t seg[3];
2274 mxge_rx_ring_t *rx = &ss->rx_big;
2277 if (rx->cl_size == MCLBYTES)
2278 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
2281 m = m_getjcl(MB_DONTWAIT, MT_DATA, M_PKTHDR, rx->cl_size);
2284 * XXX: allocate normal sized buffers for big buffers.
2285 * We should be fine as long as we don't get any jumbo frames
2287 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
2295 m->m_pkthdr.len = 0;
2296 m->m_len = m->m_pkthdr.len = rx->mlen;
2297 err = bus_dmamap_load_mbuf_segment(rx->dmat, map, m,
2298 seg, 1, &cnt, BUS_DMA_NOWAIT);
2300 kprintf("can't dmamap big (%d)\n", err);
2304 rx->info[idx].m = m;
2305 rx->shadow[idx].addr_low =
2306 htobe32(MXGE_LOWPART_TO_U32(seg->ds_addr));
2307 rx->shadow[idx].addr_high =
2308 htobe32(MXGE_HIGHPART_TO_U32(seg->ds_addr));
2310 #if MXGE_VIRT_JUMBOS
2311 for (i = 1; i < cnt; i++) {
2312 rx->shadow[idx + i].addr_low =
2313 htobe32(MXGE_LOWPART_TO_U32(seg[i].ds_addr));
2314 rx->shadow[idx + i].addr_high =
2315 htobe32(MXGE_HIGHPART_TO_U32(seg[i].ds_addr));
2320 for (i = 0; i < rx->nbufs; i++) {
2321 if ((idx & 7) == 7) {
2322 mxge_submit_8rx(&rx->lanai[idx - 7],
2323 &rx->shadow[idx - 7]);
2331 * Myri10GE hardware checksums are not valid if the sender
2332 * padded the frame with non-zero padding. This is because
2333 * the firmware just does a simple 16-bit 1s complement
2334 * checksum across the entire frame, excluding the first 14
2335 * bytes. It is best to simply to check the checksum and
2336 * tell the stack about it only if the checksum is good
2339 static inline uint16_t
2340 mxge_rx_csum(struct mbuf *m, int csum)
2342 struct ether_header *eh;
2346 eh = mtod(m, struct ether_header *);
2348 /* only deal with IPv4 TCP & UDP for now */
2349 if (__predict_false(eh->ether_type != htons(ETHERTYPE_IP)))
2351 ip = (struct ip *)(eh + 1);
2352 if (__predict_false(ip->ip_p != IPPROTO_TCP &&
2353 ip->ip_p != IPPROTO_UDP))
2356 c = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr,
2357 htonl(ntohs(csum) + ntohs(ip->ip_len) +
2358 - (ip->ip_hl << 2) + ip->ip_p));
2367 mxge_vlan_tag_remove(struct mbuf *m, uint32_t *csum)
2369 struct ether_vlan_header *evl;
2372 evl = mtod(m, struct ether_vlan_header *);
2375 * fix checksum by subtracting EVL_ENCAPLEN bytes
2376 * after what the firmware thought was the end of the ethernet
2380 /* put checksum into host byte order */
2381 *csum = ntohs(*csum);
2382 partial = ntohl(*(uint32_t *)(mtod(m, char *) + ETHER_HDR_LEN));
2383 (*csum) += ~partial;
2384 (*csum) += ((*csum) < ~partial);
2385 (*csum) = ((*csum) >> 16) + ((*csum) & 0xFFFF);
2386 (*csum) = ((*csum) >> 16) + ((*csum) & 0xFFFF);
2388 /* restore checksum to network byte order;
2389 later consumers expect this */
2390 *csum = htons(*csum);
2393 #ifdef MXGE_NEW_VLAN_API
2394 m->m_pkthdr.ether_vlantag = ntohs(evl->evl_tag);
2398 mtag = m_tag_alloc(MTAG_VLAN, MTAG_VLAN_TAG, sizeof(u_int),
2402 VLAN_TAG_VALUE(mtag) = ntohs(evl->evl_tag);
2403 m_tag_prepend(m, mtag);
2407 m->m_flags |= M_VLANTAG;
2410 * Remove the 802.1q header by copying the Ethernet
2411 * addresses over it and adjusting the beginning of
2412 * the data in the mbuf. The encapsulated Ethernet
2413 * type field is already in place.
2415 bcopy((char *)evl, (char *)evl + EVL_ENCAPLEN,
2416 ETHER_HDR_LEN - ETHER_TYPE_LEN);
2417 m_adj(m, EVL_ENCAPLEN);
2422 mxge_rx_done_big(struct mxge_slice_state *ss, uint32_t len, uint32_t csum)
2427 struct ether_header *eh;
2429 bus_dmamap_t old_map;
2431 uint16_t tcpudp_csum;
2436 idx = rx->cnt & rx->mask;
2437 rx->cnt += rx->nbufs;
2438 /* save a pointer to the received mbuf */
2439 m = rx->info[idx].m;
2440 /* try to replace the received mbuf */
2441 if (mxge_get_buf_big(ss, rx->extra_map, idx)) {
2442 /* drop the frame -- the old mbuf is re-cycled */
2443 IFNET_STAT_INC(ifp, ierrors, 1);
2447 /* unmap the received buffer */
2448 old_map = rx->info[idx].map;
2449 bus_dmamap_sync(rx->dmat, old_map, BUS_DMASYNC_POSTREAD);
2450 bus_dmamap_unload(rx->dmat, old_map);
2452 /* swap the bus_dmamap_t's */
2453 rx->info[idx].map = rx->extra_map;
2454 rx->extra_map = old_map;
2456 /* mcp implicitly skips 1st 2 bytes so that packet is properly
2458 m->m_data += MXGEFW_PAD;
2460 m->m_pkthdr.rcvif = ifp;
2461 m->m_len = m->m_pkthdr.len = len;
2463 eh = mtod(m, struct ether_header *);
2464 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
2465 mxge_vlan_tag_remove(m, &csum);
2467 /* if the checksum is valid, mark it in the mbuf header */
2468 if (sc->csum_flag && (0 == (tcpudp_csum = mxge_rx_csum(m, csum)))) {
2469 if (sc->lro_cnt && (0 == mxge_lro_rx(ss, m, csum)))
2471 /* otherwise, it was a UDP frame, or a TCP frame which
2472 we could not do LRO on. Tell the stack that the
2474 m->m_pkthdr.csum_data = 0xffff;
2475 m->m_pkthdr.csum_flags = CSUM_PSEUDO_HDR | CSUM_DATA_VALID;
2478 /* flowid only valid if RSS hashing is enabled */
2479 if (sc->num_slices > 1) {
2480 m->m_pkthdr.flowid = (ss - sc->ss);
2481 m->m_flags |= M_FLOWID;
2484 ifp->if_input(ifp, m);
2488 mxge_rx_done_small(struct mxge_slice_state *ss, uint32_t len, uint32_t csum)
2492 struct ether_header *eh;
2495 bus_dmamap_t old_map;
2497 uint16_t tcpudp_csum;
2502 idx = rx->cnt & rx->mask;
2504 /* save a pointer to the received mbuf */
2505 m = rx->info[idx].m;
2506 /* try to replace the received mbuf */
2507 if (mxge_get_buf_small(ss, rx->extra_map, idx)) {
2508 /* drop the frame -- the old mbuf is re-cycled */
2509 IFNET_STAT_INC(ifp, ierrors, 1);
2513 /* unmap the received buffer */
2514 old_map = rx->info[idx].map;
2515 bus_dmamap_sync(rx->dmat, old_map, BUS_DMASYNC_POSTREAD);
2516 bus_dmamap_unload(rx->dmat, old_map);
2518 /* swap the bus_dmamap_t's */
2519 rx->info[idx].map = rx->extra_map;
2520 rx->extra_map = old_map;
2522 /* mcp implicitly skips 1st 2 bytes so that packet is properly
2524 m->m_data += MXGEFW_PAD;
2526 m->m_pkthdr.rcvif = ifp;
2527 m->m_len = m->m_pkthdr.len = len;
2529 eh = mtod(m, struct ether_header *);
2530 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
2531 mxge_vlan_tag_remove(m, &csum);
2533 /* if the checksum is valid, mark it in the mbuf header */
2534 if (sc->csum_flag && (0 == (tcpudp_csum = mxge_rx_csum(m, csum)))) {
2535 if (sc->lro_cnt && (0 == mxge_lro_rx(ss, m, csum)))
2537 /* otherwise, it was a UDP frame, or a TCP frame which
2538 we could not do LRO on. Tell the stack that the
2540 m->m_pkthdr.csum_data = 0xffff;
2541 m->m_pkthdr.csum_flags = CSUM_PSEUDO_HDR | CSUM_DATA_VALID;
2544 /* flowid only valid if RSS hashing is enabled */
2545 if (sc->num_slices > 1) {
2546 m->m_pkthdr.flowid = (ss - sc->ss);
2547 m->m_flags |= M_FLOWID;
2550 ifp->if_input(ifp, m);
2556 * Inlining the call to this function causes mxge_intr() to grow too large
2557 * for GCC's stack size limits (which shouldn't take into account inlining
2558 * of leaf functions at one call site anyway). Inlining is definitely a
2559 * good idea in this case though, so mark the function appropriately.
2561 static inline __always_inline void
2562 mxge_clean_rx_done(struct mxge_slice_state *ss)
2564 mxge_rx_done_t *rx_done = &ss->rx_done;
2569 while (rx_done->entry[rx_done->idx].length != 0) {
2570 length = ntohs(rx_done->entry[rx_done->idx].length);
2571 rx_done->entry[rx_done->idx].length = 0;
2572 checksum = rx_done->entry[rx_done->idx].checksum;
2573 if (length <= (MHLEN - MXGEFW_PAD))
2574 mxge_rx_done_small(ss, length, checksum);
2576 mxge_rx_done_big(ss, length, checksum);
2578 rx_done->idx = rx_done->cnt & rx_done->mask;
2580 /* limit potential for livelock */
2581 if (__predict_false(++limit > rx_done->mask / 2))
2585 while (!SLIST_EMPTY(&ss->lro_active)) {
2586 struct lro_entry *lro = SLIST_FIRST(&ss->lro_active);
2587 SLIST_REMOVE_HEAD(&ss->lro_active, next);
2588 mxge_lro_flush(ss, lro);
2595 mxge_tx_done(struct mxge_slice_state *ss, uint32_t mcp_idx)
2605 ASSERT_SERIALIZED(ifp->if_serializer);
2606 while (tx->pkt_done != mcp_idx) {
2607 idx = tx->done & tx->mask;
2609 m = tx->info[idx].m;
2610 /* mbuf and DMA map only attached to the first
2613 ss->obytes += m->m_pkthdr.len;
2614 if (m->m_flags & M_MCAST)
2617 tx->info[idx].m = NULL;
2618 map = tx->info[idx].map;
2619 bus_dmamap_unload(tx->dmat, map);
2622 if (tx->info[idx].flag) {
2623 tx->info[idx].flag = 0;
2628 /* If we have space, clear OACTIVE to tell the stack that
2629 its OK to send packets */
2630 if (ifq_is_oactive(&ifp->if_snd) &&
2631 tx->req - tx->done < (tx->mask + 1)/4) {
2632 ifq_clr_oactive(&ifp->if_snd);
2634 mxge_start_locked(ss);
2636 #ifdef IFNET_BUF_RING
2637 if ((ss->sc->num_slices > 1) && (tx->req == tx->done)) {
2638 /* let the NIC stop polling this queue, since there
2639 * are no more transmits pending */
2640 if (tx->req == tx->done) {
2642 tx->queue_active = 0;
2651 static struct mxge_media_type mxge_xfp_media_types[] =
2653 {IFM_10G_CX4, 0x7f, "10GBASE-CX4 (module)"},
2654 {IFM_10G_SR, (1 << 7), "10GBASE-SR"},
2655 {IFM_10G_LR, (1 << 6), "10GBASE-LR"},
2656 {0, (1 << 5), "10GBASE-ER"},
2657 {IFM_10G_LRM, (1 << 4), "10GBASE-LRM"},
2658 {0, (1 << 3), "10GBASE-SW"},
2659 {0, (1 << 2), "10GBASE-LW"},
2660 {0, (1 << 1), "10GBASE-EW"},
2661 {0, (1 << 0), "Reserved"}
2663 static struct mxge_media_type mxge_sfp_media_types[] =
2665 {0, (1 << 7), "Reserved"},
2666 {IFM_10G_LRM, (1 << 6), "10GBASE-LRM"},
2667 {IFM_10G_LR, (1 << 5), "10GBASE-LR"},
2668 {IFM_10G_SR, (1 << 4), "10GBASE-SR"}
2672 mxge_set_media(mxge_softc_t *sc, int type)
2674 sc->media_flags |= type;
2675 ifmedia_add(&sc->media, sc->media_flags, 0, NULL);
2676 ifmedia_set(&sc->media, sc->media_flags);
2681 * Determine the media type for a NIC. Some XFPs will identify
2682 * themselves only when their link is up, so this is initiated via a
2683 * link up interrupt. However, this can potentially take up to
2684 * several milliseconds, so it is run via the watchdog routine, rather
2685 * than in the interrupt handler itself. This need only be done
2686 * once, not each time the link is up.
2689 mxge_media_probe(mxge_softc_t *sc)
2694 struct mxge_media_type *mxge_media_types = NULL;
2695 int i, err, ms, mxge_media_type_entries;
2698 sc->need_media_probe = 0;
2700 /* if we've already set a media type, we're done */
2701 if (sc->media_flags != (IFM_ETHER | IFM_AUTO))
2705 * parse the product code to deterimine the interface type
2706 * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
2707 * after the 3rd dash in the driver's cached copy of the
2708 * EEPROM's product code string.
2710 ptr = sc->product_code_string;
2712 device_printf(sc->dev, "Missing product code\n");
2715 for (i = 0; i < 3; i++, ptr++) {
2716 ptr = index(ptr, '-');
2718 device_printf(sc->dev,
2719 "only %d dashes in PC?!?\n", i);
2725 mxge_set_media(sc, IFM_10G_CX4);
2728 else if (*ptr == 'Q') {
2729 /* -Q is Quad Ribbon Fiber */
2730 device_printf(sc->dev, "Quad Ribbon Fiber Media\n");
2731 /* FreeBSD has no media type for Quad ribbon fiber */
2737 mxge_media_types = mxge_xfp_media_types;
2738 mxge_media_type_entries = NELEM(mxge_xfp_media_types);
2739 byte = MXGE_XFP_COMPLIANCE_BYTE;
2743 if (*ptr == 'S' || *(ptr +1) == 'S') {
2744 /* -S or -2S is SFP+ */
2745 mxge_media_types = mxge_sfp_media_types;
2746 mxge_media_type_entries = NELEM(mxge_sfp_media_types);
2751 if (mxge_media_types == NULL) {
2752 device_printf(sc->dev, "Unknown media type: %c\n", *ptr);
2757 * At this point we know the NIC has an XFP cage, so now we
2758 * try to determine what is in the cage by using the
2759 * firmware's XFP I2C commands to read the XFP 10GbE compilance
2760 * register. We read just one byte, which may take over
2764 cmd.data0 = 0; /* just fetch 1 byte, not all 256 */
2766 err = mxge_send_cmd(sc, MXGEFW_CMD_I2C_READ, &cmd);
2767 if (err == MXGEFW_CMD_ERROR_I2C_FAILURE) {
2768 device_printf(sc->dev, "failed to read XFP\n");
2770 if (err == MXGEFW_CMD_ERROR_I2C_ABSENT) {
2771 device_printf(sc->dev, "Type R/S with no XFP!?!?\n");
2773 if (err != MXGEFW_CMD_OK) {
2777 /* now we wait for the data to be cached */
2779 err = mxge_send_cmd(sc, MXGEFW_CMD_I2C_BYTE, &cmd);
2780 for (ms = 0; (err == EBUSY) && (ms < 50); ms++) {
2783 err = mxge_send_cmd(sc, MXGEFW_CMD_I2C_BYTE, &cmd);
2785 if (err != MXGEFW_CMD_OK) {
2786 device_printf(sc->dev, "failed to read %s (%d, %dms)\n",
2787 cage_type, err, ms);
2791 if (cmd.data0 == mxge_media_types[0].bitmask) {
2793 device_printf(sc->dev, "%s:%s\n", cage_type,
2794 mxge_media_types[0].name);
2795 mxge_set_media(sc, IFM_10G_CX4);
2798 for (i = 1; i < mxge_media_type_entries; i++) {
2799 if (cmd.data0 & mxge_media_types[i].bitmask) {
2801 device_printf(sc->dev, "%s:%s\n",
2803 mxge_media_types[i].name);
2805 mxge_set_media(sc, mxge_media_types[i].flag);
2809 device_printf(sc->dev, "%s media 0x%x unknown\n", cage_type,
2816 mxge_intr(void *arg)
2818 struct mxge_slice_state *ss = arg;
2819 mxge_softc_t *sc = ss->sc;
2820 mcp_irq_data_t *stats = ss->fw_stats;
2821 mxge_tx_ring_t *tx = &ss->tx;
2822 mxge_rx_done_t *rx_done = &ss->rx_done;
2823 uint32_t send_done_count;
2827 #ifndef IFNET_BUF_RING
2828 /* an interrupt on a non-zero slice is implicitly valid
2829 since MSI-X irqs are not shared */
2831 mxge_clean_rx_done(ss);
2832 *ss->irq_claim = be32toh(3);
2837 /* make sure the DMA has finished */
2838 if (!stats->valid) {
2841 valid = stats->valid;
2843 if (sc->legacy_irq) {
2844 /* lower legacy IRQ */
2845 *sc->irq_deassert = 0;
2846 if (!mxge_deassert_wait)
2847 /* don't wait for conf. that irq is low */
2853 /* loop while waiting for legacy irq deassertion */
2855 /* check for transmit completes and receives */
2856 send_done_count = be32toh(stats->send_done_count);
2857 while ((send_done_count != tx->pkt_done) ||
2858 (rx_done->entry[rx_done->idx].length != 0)) {
2859 if (send_done_count != tx->pkt_done)
2860 mxge_tx_done(ss, (int)send_done_count);
2861 mxge_clean_rx_done(ss);
2862 send_done_count = be32toh(stats->send_done_count);
2864 if (sc->legacy_irq && mxge_deassert_wait)
2866 } while (*((volatile uint8_t *) &stats->valid));
2868 /* fw link & error stats meaningful only on the first slice */
2869 if (__predict_false((ss == sc->ss) && stats->stats_updated)) {
2870 if (sc->link_state != stats->link_up) {
2871 sc->link_state = stats->link_up;
2872 if (sc->link_state) {
2873 sc->ifp->if_link_state = LINK_STATE_UP;
2874 if_link_state_change(sc->ifp);
2876 device_printf(sc->dev, "link up\n");
2878 sc->ifp->if_link_state = LINK_STATE_DOWN;
2879 if_link_state_change(sc->ifp);
2881 device_printf(sc->dev, "link down\n");
2883 sc->need_media_probe = 1;
2885 if (sc->rdma_tags_available !=
2886 be32toh(stats->rdma_tags_available)) {
2887 sc->rdma_tags_available =
2888 be32toh(stats->rdma_tags_available);
2889 device_printf(sc->dev, "RDMA timed out! %d tags "
2890 "left\n", sc->rdma_tags_available);
2893 if (stats->link_down) {
2894 sc->down_cnt += stats->link_down;
2896 sc->ifp->if_link_state = LINK_STATE_DOWN;
2897 if_link_state_change(sc->ifp);
2901 /* check to see if we have rx token to pass back */
2903 *ss->irq_claim = be32toh(3);
2904 *(ss->irq_claim + 1) = be32toh(3);
2908 mxge_init(void *arg)
2915 mxge_free_slice_mbufs(struct mxge_slice_state *ss)
2917 struct lro_entry *lro_entry;
2920 while (!SLIST_EMPTY(&ss->lro_free)) {
2921 lro_entry = SLIST_FIRST(&ss->lro_free);
2922 SLIST_REMOVE_HEAD(&ss->lro_free, next);
2923 kfree(lro_entry, M_DEVBUF);
2926 for (i = 0; i <= ss->rx_big.mask; i++) {
2927 if (ss->rx_big.info[i].m == NULL)
2929 bus_dmamap_unload(ss->rx_big.dmat,
2930 ss->rx_big.info[i].map);
2931 m_freem(ss->rx_big.info[i].m);
2932 ss->rx_big.info[i].m = NULL;
2935 for (i = 0; i <= ss->rx_small.mask; i++) {
2936 if (ss->rx_small.info[i].m == NULL)
2938 bus_dmamap_unload(ss->rx_small.dmat,
2939 ss->rx_small.info[i].map);
2940 m_freem(ss->rx_small.info[i].m);
2941 ss->rx_small.info[i].m = NULL;
2944 /* transmit ring used only on the first slice */
2945 if (ss->tx.info == NULL)
2948 for (i = 0; i <= ss->tx.mask; i++) {
2949 ss->tx.info[i].flag = 0;
2950 if (ss->tx.info[i].m == NULL)
2952 bus_dmamap_unload(ss->tx.dmat,
2953 ss->tx.info[i].map);
2954 m_freem(ss->tx.info[i].m);
2955 ss->tx.info[i].m = NULL;
2960 mxge_free_mbufs(mxge_softc_t *sc)
2964 for (slice = 0; slice < sc->num_slices; slice++)
2965 mxge_free_slice_mbufs(&sc->ss[slice]);
2969 mxge_free_slice_rings(struct mxge_slice_state *ss)
2974 if (ss->rx_done.entry != NULL)
2975 mxge_dma_free(&ss->rx_done.dma);
2976 ss->rx_done.entry = NULL;
2978 if (ss->tx.req_bytes != NULL)
2979 kfree(ss->tx.req_bytes, M_DEVBUF);
2980 ss->tx.req_bytes = NULL;
2982 if (ss->tx.seg_list != NULL)
2983 kfree(ss->tx.seg_list, M_DEVBUF);
2984 ss->tx.seg_list = NULL;
2986 if (ss->rx_small.shadow != NULL)
2987 kfree(ss->rx_small.shadow, M_DEVBUF);
2988 ss->rx_small.shadow = NULL;
2990 if (ss->rx_big.shadow != NULL)
2991 kfree(ss->rx_big.shadow, M_DEVBUF);
2992 ss->rx_big.shadow = NULL;
2994 if (ss->tx.info != NULL) {
2995 if (ss->tx.dmat != NULL) {
2996 for (i = 0; i <= ss->tx.mask; i++) {
2997 bus_dmamap_destroy(ss->tx.dmat,
2998 ss->tx.info[i].map);
3000 bus_dma_tag_destroy(ss->tx.dmat);
3002 kfree(ss->tx.info, M_DEVBUF);
3006 if (ss->rx_small.info != NULL) {
3007 if (ss->rx_small.dmat != NULL) {
3008 for (i = 0; i <= ss->rx_small.mask; i++) {
3009 bus_dmamap_destroy(ss->rx_small.dmat,
3010 ss->rx_small.info[i].map);
3012 bus_dmamap_destroy(ss->rx_small.dmat,
3013 ss->rx_small.extra_map);
3014 bus_dma_tag_destroy(ss->rx_small.dmat);
3016 kfree(ss->rx_small.info, M_DEVBUF);
3018 ss->rx_small.info = NULL;
3020 if (ss->rx_big.info != NULL) {
3021 if (ss->rx_big.dmat != NULL) {
3022 for (i = 0; i <= ss->rx_big.mask; i++) {
3023 bus_dmamap_destroy(ss->rx_big.dmat,
3024 ss->rx_big.info[i].map);
3026 bus_dmamap_destroy(ss->rx_big.dmat,
3027 ss->rx_big.extra_map);
3028 bus_dma_tag_destroy(ss->rx_big.dmat);
3030 kfree(ss->rx_big.info, M_DEVBUF);
3032 ss->rx_big.info = NULL;
3036 mxge_free_rings(mxge_softc_t *sc)
3040 for (slice = 0; slice < sc->num_slices; slice++)
3041 mxge_free_slice_rings(&sc->ss[slice]);
3045 mxge_alloc_slice_rings(struct mxge_slice_state *ss, int rx_ring_entries,
3046 int tx_ring_entries)
3048 mxge_softc_t *sc = ss->sc;
3054 /* allocate per-slice receive resources */
3056 ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
3057 ss->rx_done.mask = (2 * rx_ring_entries) - 1;
3059 /* allocate the rx shadow rings */
3060 bytes = rx_ring_entries * sizeof (*ss->rx_small.shadow);
3061 ss->rx_small.shadow = kmalloc(bytes, M_DEVBUF, M_ZERO|M_WAITOK);
3063 bytes = rx_ring_entries * sizeof (*ss->rx_big.shadow);
3064 ss->rx_big.shadow = kmalloc(bytes, M_DEVBUF, M_ZERO|M_WAITOK);
3066 /* allocate the rx host info rings */
3067 bytes = rx_ring_entries * sizeof (*ss->rx_small.info);
3068 ss->rx_small.info = kmalloc(bytes, M_DEVBUF, M_ZERO|M_WAITOK);
3070 bytes = rx_ring_entries * sizeof (*ss->rx_big.info);
3071 ss->rx_big.info = kmalloc(bytes, M_DEVBUF, M_ZERO|M_WAITOK);
3073 /* allocate the rx busdma resources */
3074 err = bus_dma_tag_create(sc->parent_dmat, /* parent */
3076 4096, /* boundary */
3077 BUS_SPACE_MAXADDR, /* low */
3078 BUS_SPACE_MAXADDR, /* high */
3079 NULL, NULL, /* filter */
3080 MHLEN, /* maxsize */
3082 MHLEN, /* maxsegsize */
3083 BUS_DMA_ALLOCNOW, /* flags */
3084 &ss->rx_small.dmat); /* tag */
3086 device_printf(sc->dev, "Err %d allocating rx_small dmat\n",
3091 err = bus_dma_tag_create(sc->parent_dmat, /* parent */
3093 #if MXGE_VIRT_JUMBOS
3094 4096, /* boundary */
3098 BUS_SPACE_MAXADDR, /* low */
3099 BUS_SPACE_MAXADDR, /* high */
3100 NULL, NULL, /* filter */
3101 3*4096, /* maxsize */
3102 #if MXGE_VIRT_JUMBOS
3104 4096, /* maxsegsize*/
3107 MJUM9BYTES, /* maxsegsize*/
3109 BUS_DMA_ALLOCNOW, /* flags */
3110 &ss->rx_big.dmat); /* tag */
3112 device_printf(sc->dev, "Err %d allocating rx_big dmat\n",
3116 for (i = 0; i <= ss->rx_small.mask; i++) {
3117 err = bus_dmamap_create(ss->rx_small.dmat, 0,
3118 &ss->rx_small.info[i].map);
3120 device_printf(sc->dev, "Err %d rx_small dmamap\n",
3125 err = bus_dmamap_create(ss->rx_small.dmat, 0,
3126 &ss->rx_small.extra_map);
3128 device_printf(sc->dev, "Err %d extra rx_small dmamap\n",
3133 for (i = 0; i <= ss->rx_big.mask; i++) {
3134 err = bus_dmamap_create(ss->rx_big.dmat, 0,
3135 &ss->rx_big.info[i].map);
3137 device_printf(sc->dev, "Err %d rx_big dmamap\n",
3142 err = bus_dmamap_create(ss->rx_big.dmat, 0,
3143 &ss->rx_big.extra_map);
3145 device_printf(sc->dev, "Err %d extra rx_big dmamap\n",
3150 /* now allocate TX resouces */
3152 #ifndef IFNET_BUF_RING
3153 /* only use a single TX ring for now */
3154 if (ss != ss->sc->ss)
3158 ss->tx.mask = tx_ring_entries - 1;
3159 ss->tx.max_desc = MIN(MXGE_MAX_SEND_DESC, tx_ring_entries / 4);
3162 /* allocate the tx request copy block */
3164 sizeof (*ss->tx.req_list) * (ss->tx.max_desc + 4);
3165 ss->tx.req_bytes = kmalloc(bytes, M_DEVBUF, M_WAITOK);
3166 /* ensure req_list entries are aligned to 8 bytes */
3167 ss->tx.req_list = (mcp_kreq_ether_send_t *)
3168 ((unsigned long)(ss->tx.req_bytes + 7) & ~7UL);
3170 /* allocate the tx busdma segment list */
3171 bytes = sizeof (*ss->tx.seg_list) * ss->tx.max_desc;
3172 ss->tx.seg_list = (bus_dma_segment_t *)
3173 kmalloc(bytes, M_DEVBUF, M_WAITOK);
3174 if (ss->tx.seg_list == NULL)
3177 /* allocate the tx host info ring */
3178 bytes = tx_ring_entries * sizeof (*ss->tx.info);
3179 ss->tx.info = kmalloc(bytes, M_DEVBUF, M_ZERO|M_WAITOK);
3181 /* allocate the tx busdma resources */
3182 err = bus_dma_tag_create(sc->parent_dmat, /* parent */
3184 sc->tx_boundary, /* boundary */
3185 BUS_SPACE_MAXADDR, /* low */
3186 BUS_SPACE_MAXADDR, /* high */
3187 NULL, NULL, /* filter */
3188 65536 + 256, /* maxsize */
3189 ss->tx.max_desc - 2, /* num segs */
3190 sc->tx_boundary, /* maxsegsz */
3191 BUS_DMA_ALLOCNOW, /* flags */
3192 &ss->tx.dmat); /* tag */
3195 device_printf(sc->dev, "Err %d allocating tx dmat\n",
3200 /* now use these tags to setup dmamaps for each slot
3202 for (i = 0; i <= ss->tx.mask; i++) {
3203 err = bus_dmamap_create(ss->tx.dmat, 0,
3204 &ss->tx.info[i].map);
3206 device_printf(sc->dev, "Err %d tx dmamap\n",
3216 mxge_alloc_rings(mxge_softc_t *sc)
3220 int tx_ring_entries, rx_ring_entries;
3223 /* get ring sizes */
3224 err = mxge_send_cmd(sc, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd);
3225 tx_ring_size = cmd.data0;
3227 device_printf(sc->dev, "Cannot determine tx ring sizes\n");
3231 tx_ring_entries = tx_ring_size / sizeof (mcp_kreq_ether_send_t);
3232 rx_ring_entries = sc->rx_ring_size / sizeof (mcp_dma_addr_t);
3233 ifq_set_maxlen(&sc->ifp->if_snd, tx_ring_entries - 1);
3234 ifq_set_ready(&sc->ifp->if_snd);
3236 for (slice = 0; slice < sc->num_slices; slice++) {
3237 err = mxge_alloc_slice_rings(&sc->ss[slice],
3246 mxge_free_rings(sc);
3253 mxge_choose_params(int mtu, int *big_buf_size, int *cl_size, int *nbufs)
3255 int bufsize = mtu + ETHER_HDR_LEN + EVL_ENCAPLEN + MXGEFW_PAD;
3257 if (bufsize < MCLBYTES) {
3258 /* easy, everything fits in a single buffer */
3259 *big_buf_size = MCLBYTES;
3260 *cl_size = MCLBYTES;
3265 if (bufsize < MJUMPAGESIZE) {
3266 /* still easy, everything still fits in a single buffer */
3267 *big_buf_size = MJUMPAGESIZE;
3268 *cl_size = MJUMPAGESIZE;
3272 #if MXGE_VIRT_JUMBOS
3273 /* now we need to use virtually contiguous buffers */
3274 *cl_size = MJUM9BYTES;
3275 *big_buf_size = 4096;
3276 *nbufs = mtu / 4096 + 1;
3277 /* needs to be a power of two, so round up */
3281 *cl_size = MJUM9BYTES;
3282 *big_buf_size = MJUM9BYTES;
3288 mxge_slice_open(struct mxge_slice_state *ss, int nbufs, int cl_size)
3293 struct lro_entry *lro_entry;
3298 slice = ss - sc->ss;
3300 SLIST_INIT(&ss->lro_free);
3301 SLIST_INIT(&ss->lro_active);
3303 for (i = 0; i < sc->lro_cnt; i++) {
3304 lro_entry = (struct lro_entry *)
3305 kmalloc(sizeof (*lro_entry), M_DEVBUF,
3307 if (lro_entry == NULL) {
3311 SLIST_INSERT_HEAD(&ss->lro_free, lro_entry, next);
3313 /* get the lanai pointers to the send and receive rings */
3316 #ifndef IFNET_BUF_RING
3317 /* We currently only send from the first slice */
3321 err = mxge_send_cmd(sc, MXGEFW_CMD_GET_SEND_OFFSET, &cmd);
3323 (volatile mcp_kreq_ether_send_t *)(sc->sram + cmd.data0);
3324 ss->tx.send_go = (volatile uint32_t *)
3325 (sc->sram + MXGEFW_ETH_SEND_GO + 64 * slice);
3326 ss->tx.send_stop = (volatile uint32_t *)
3327 (sc->sram + MXGEFW_ETH_SEND_STOP + 64 * slice);
3328 #ifndef IFNET_BUF_RING
3332 err |= mxge_send_cmd(sc,
3333 MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd);
3334 ss->rx_small.lanai =
3335 (volatile mcp_kreq_ether_recv_t *)(sc->sram + cmd.data0);
3337 err |= mxge_send_cmd(sc, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd);
3339 (volatile mcp_kreq_ether_recv_t *)(sc->sram + cmd.data0);
3342 device_printf(sc->dev,
3343 "failed to get ring sizes or locations\n");
3347 /* stock receive rings */
3348 for (i = 0; i <= ss->rx_small.mask; i++) {
3349 map = ss->rx_small.info[i].map;
3350 err = mxge_get_buf_small(ss, map, i);
3352 device_printf(sc->dev, "alloced %d/%d smalls\n",
3353 i, ss->rx_small.mask + 1);
3357 for (i = 0; i <= ss->rx_big.mask; i++) {
3358 ss->rx_big.shadow[i].addr_low = 0xffffffff;
3359 ss->rx_big.shadow[i].addr_high = 0xffffffff;
3361 ss->rx_big.nbufs = nbufs;
3362 ss->rx_big.cl_size = cl_size;
3363 ss->rx_big.mlen = ss->sc->ifp->if_mtu + ETHER_HDR_LEN +
3364 EVL_ENCAPLEN + MXGEFW_PAD;
3365 for (i = 0; i <= ss->rx_big.mask; i += ss->rx_big.nbufs) {
3366 map = ss->rx_big.info[i].map;
3367 err = mxge_get_buf_big(ss, map, i);
3369 device_printf(sc->dev, "alloced %d/%d bigs\n",
3370 i, ss->rx_big.mask + 1);
3378 mxge_open(mxge_softc_t *sc)
3381 int err, big_bytes, nbufs, slice, cl_size, i;
3383 volatile uint8_t *itable;
3384 struct mxge_slice_state *ss;
3386 ASSERT_SERIALIZED(sc->ifp->if_serializer);
3387 /* Copy the MAC address in case it was overridden */
3388 bcopy(IF_LLADDR(sc->ifp), sc->mac_addr, ETHER_ADDR_LEN);
3390 err = mxge_reset(sc, 1);
3392 device_printf(sc->dev, "failed to reset\n");
3396 if (sc->num_slices > 1) {
3397 /* setup the indirection table */
3398 cmd.data0 = sc->num_slices;
3399 err = mxge_send_cmd(sc, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
3402 err |= mxge_send_cmd(sc, MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
3405 device_printf(sc->dev,
3406 "failed to setup rss tables\n");
3410 /* just enable an identity mapping */
3411 itable = sc->sram + cmd.data0;
3412 for (i = 0; i < sc->num_slices; i++)
3413 itable[i] = (uint8_t)i;
3416 cmd.data1 = mxge_rss_hash_type;
3417 err = mxge_send_cmd(sc, MXGEFW_CMD_SET_RSS_ENABLE, &cmd);
3419 device_printf(sc->dev, "failed to enable slices\n");
3425 mxge_choose_params(sc->ifp->if_mtu, &big_bytes, &cl_size, &nbufs);
3428 err = mxge_send_cmd(sc, MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS,
3430 /* error is only meaningful if we're trying to set
3431 MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS > 1 */
3432 if (err && nbufs > 1) {
3433 device_printf(sc->dev,
3434 "Failed to set alway-use-n to %d\n",
3438 /* Give the firmware the mtu and the big and small buffer
3439 sizes. The firmware wants the big buf size to be a power
3440 of two. Luckily, FreeBSD's clusters are powers of two */
3441 cmd.data0 = sc->ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN;
3442 err = mxge_send_cmd(sc, MXGEFW_CMD_SET_MTU, &cmd);
3443 cmd.data0 = MHLEN - MXGEFW_PAD;
3444 err |= mxge_send_cmd(sc, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE,
3446 cmd.data0 = big_bytes;
3447 err |= mxge_send_cmd(sc, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd);
3450 device_printf(sc->dev, "failed to setup params\n");
3454 /* Now give him the pointer to the stats block */
3456 #ifdef IFNET_BUF_RING
3457 slice < sc->num_slices;
3462 ss = &sc->ss[slice];
3464 MXGE_LOWPART_TO_U32(ss->fw_stats_dma.bus_addr);
3466 MXGE_HIGHPART_TO_U32(ss->fw_stats_dma.bus_addr);
3467 cmd.data2 = sizeof(struct mcp_irq_data);
3468 cmd.data2 |= (slice << 16);
3469 err |= mxge_send_cmd(sc, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd);
3473 bus = sc->ss->fw_stats_dma.bus_addr;
3474 bus += offsetof(struct mcp_irq_data, send_done_count);
3475 cmd.data0 = MXGE_LOWPART_TO_U32(bus);
3476 cmd.data1 = MXGE_HIGHPART_TO_U32(bus);
3477 err = mxge_send_cmd(sc,
3478 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
3480 /* Firmware cannot support multicast without STATS_DMA_V2 */
3481 sc->fw_multicast_support = 0;
3483 sc->fw_multicast_support = 1;
3487 device_printf(sc->dev, "failed to setup params\n");
3491 for (slice = 0; slice < sc->num_slices; slice++) {
3492 err = mxge_slice_open(&sc->ss[slice], nbufs, cl_size);
3494 device_printf(sc->dev, "couldn't open slice %d\n",
3500 /* Finally, start the firmware running */
3501 err = mxge_send_cmd(sc, MXGEFW_CMD_ETHERNET_UP, &cmd);
3503 device_printf(sc->dev, "Couldn't bring up link\n");
3506 sc->ifp->if_flags |= IFF_RUNNING;
3507 ifq_clr_oactive(&sc->ifp->if_snd);
3508 callout_reset(&sc->co_hdl, mxge_ticks, mxge_tick, sc);
3514 mxge_free_mbufs(sc);
3520 mxge_close(mxge_softc_t *sc)
3523 int err, old_down_cnt;
3524 #ifdef IFNET_BUF_RING
3525 struct mxge_slice_state *ss;
3529 ASSERT_SERIALIZED(sc->ifp->if_serializer);
3530 callout_stop(&sc->co_hdl);
3531 #ifdef IFNET_BUF_RING
3532 for (slice = 0; slice < sc->num_slices; slice++) {
3533 ss = &sc->ss[slice];
3534 ss->if_flags &= ~IFF_RUNNING;
3537 sc->ifp->if_flags &= ~IFF_RUNNING;
3538 old_down_cnt = sc->down_cnt;
3540 err = mxge_send_cmd(sc, MXGEFW_CMD_ETHERNET_DOWN, &cmd);
3542 device_printf(sc->dev, "Couldn't bring down link\n");
3544 if (old_down_cnt == sc->down_cnt) {
3545 /* wait for down irq */
3546 DELAY(10 * sc->intr_coal_delay);
3549 if (old_down_cnt == sc->down_cnt) {
3550 device_printf(sc->dev, "never got down irq\n");
3553 mxge_free_mbufs(sc);
3559 mxge_setup_cfg_space(mxge_softc_t *sc)
3561 device_t dev = sc->dev;
3563 uint16_t cmd, lnk, pectl;
3565 /* find the PCIe link width and set max read request to 4KB*/
3566 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) {
3567 lnk = pci_read_config(dev, reg + 0x12, 2);
3568 sc->link_width = (lnk >> 4) & 0x3f;
3570 pectl = pci_read_config(dev, reg + 0x8, 2);
3571 pectl = (pectl & ~0x7000) | (5 << 12);
3572 pci_write_config(dev, reg + 0x8, pectl, 2);
3575 /* Enable DMA and Memory space access */
3576 pci_enable_busmaster(dev);
3577 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
3578 cmd |= PCIM_CMD_MEMEN;
3579 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
3583 mxge_read_reboot(mxge_softc_t *sc)
3585 device_t dev = sc->dev;
3588 /* find the vendor specific offset */
3589 if (pci_find_extcap(dev, PCIY_VENDOR, &vs) != 0) {
3590 device_printf(sc->dev,
3591 "could not find vendor specific offset\n");
3592 return (uint32_t)-1;
3594 /* enable read32 mode */
3595 pci_write_config(dev, vs + 0x10, 0x3, 1);
3596 /* tell NIC which register to read */
3597 pci_write_config(dev, vs + 0x18, 0xfffffff0, 4);
3598 return (pci_read_config(dev, vs + 0x14, 4));
3602 mxge_watchdog_reset(mxge_softc_t *sc, int slice)
3604 struct pci_devinfo *dinfo;
3612 device_printf(sc->dev, "Watchdog reset!\n");
3615 * check to see if the NIC rebooted. If it did, then all of
3616 * PCI config space has been reset, and things like the
3617 * busmaster bit will be zero. If this is the case, then we
3618 * must restore PCI config space before the NIC can be used
3621 cmd = pci_read_config(sc->dev, PCIR_COMMAND, 2);
3622 if (cmd == 0xffff) {
3624 * maybe the watchdog caught the NIC rebooting; wait
3625 * up to 100ms for it to finish. If it does not come
3626 * back, then give up
3629 cmd = pci_read_config(sc->dev, PCIR_COMMAND, 2);
3630 if (cmd == 0xffff) {
3631 device_printf(sc->dev, "NIC disappeared!\n");
3635 if ((cmd & PCIM_CMD_BUSMASTEREN) == 0) {
3636 /* print the reboot status */
3637 reboot = mxge_read_reboot(sc);
3638 device_printf(sc->dev, "NIC rebooted, status = 0x%x\n",
3640 /* restore PCI configuration space */
3641 dinfo = device_get_ivars(sc->dev);
3642 pci_cfg_restore(sc->dev, dinfo);
3644 /* and redo any changes we made to our config space */
3645 mxge_setup_cfg_space(sc);
3647 if (sc->ifp->if_flags & IFF_RUNNING) {
3649 err = mxge_open(sc);
3652 tx = &sc->ss[slice].tx;
3653 device_printf(sc->dev,
3654 "NIC did not reboot, slice %d ring state:\n",
3656 device_printf(sc->dev,
3657 "tx.req=%d tx.done=%d, tx.queue_active=%d\n",
3658 tx->req, tx->done, tx->queue_active);
3659 device_printf(sc->dev, "tx.activate=%d tx.deactivate=%d\n",
3660 tx->activate, tx->deactivate);
3661 device_printf(sc->dev, "pkt_done=%d fw=%d\n",
3663 be32toh(sc->ss->fw_stats->send_done_count));
3664 device_printf(sc->dev, "not resetting\n");
3670 mxge_watchdog(mxge_softc_t *sc)
3673 uint32_t rx_pause = be32toh(sc->ss->fw_stats->dropped_pause);
3676 /* see if we have outstanding transmits, which
3677 have been pending for more than mxge_ticks */
3679 #ifdef IFNET_BUF_RING
3680 (i < sc->num_slices) && (err == 0);
3682 (i < 1) && (err == 0);
3686 if (tx->req != tx->done &&
3687 tx->watchdog_req != tx->watchdog_done &&
3688 tx->done == tx->watchdog_done) {
3689 /* check for pause blocking before resetting */
3690 if (tx->watchdog_rx_pause == rx_pause)
3691 err = mxge_watchdog_reset(sc, i);
3693 device_printf(sc->dev, "Flow control blocking "
3694 "xmits, check link partner\n");
3697 tx->watchdog_req = tx->req;
3698 tx->watchdog_done = tx->done;
3699 tx->watchdog_rx_pause = rx_pause;
3702 if (sc->need_media_probe)
3703 mxge_media_probe(sc);
3708 mxge_update_stats(mxge_softc_t *sc)
3710 struct mxge_slice_state *ss;
3711 u_long ipackets = 0;
3712 u_long opackets = 0;
3713 #ifdef IFNET_BUF_RING
3721 for (slice = 0; slice < sc->num_slices; slice++) {
3722 ss = &sc->ss[slice];
3723 ipackets += ss->ipackets;
3724 opackets += ss->opackets;
3725 #ifdef IFNET_BUF_RING
3726 obytes += ss->obytes;
3727 omcasts += ss->omcasts;
3728 odrops += ss->tx.br->br_drops;
3730 oerrors += ss->oerrors;
3732 IFNET_STAT_SET(sc->ifp, ipackets, ipackets);
3733 IFNET_STAT_SET(sc->ifp, opackets, opackets);
3734 #ifdef IFNET_BUF_RING
3735 sc->ifp->if_obytes = obytes;
3736 sc->ifp->if_omcasts = omcasts;
3737 sc->ifp->if_snd.ifq_drops = odrops;
3739 IFNET_STAT_SET(sc->ifp, oerrors, oerrors);
3743 mxge_tick(void *arg)
3745 mxge_softc_t *sc = arg;
3748 lwkt_serialize_enter(sc->ifp->if_serializer);
3749 /* aggregate stats from different slices */
3750 mxge_update_stats(sc);
3751 if (!sc->watchdog_countdown) {
3752 err = mxge_watchdog(sc);
3753 sc->watchdog_countdown = 4;
3755 sc->watchdog_countdown--;
3757 callout_reset(&sc->co_hdl, mxge_ticks, mxge_tick, sc);
3758 lwkt_serialize_exit(sc->ifp->if_serializer);
3762 mxge_media_change(struct ifnet *ifp)
3768 mxge_change_mtu(mxge_softc_t *sc, int mtu)
3770 struct ifnet *ifp = sc->ifp;
3771 int real_mtu, old_mtu;
3774 if (ifp->if_serializer)
3775 ASSERT_SERIALIZED(ifp->if_serializer);
3777 real_mtu = mtu + ETHER_HDR_LEN + EVL_ENCAPLEN;
3778 if ((real_mtu > sc->max_mtu) || real_mtu < 60)
3780 old_mtu = ifp->if_mtu;
3782 if (ifp->if_flags & IFF_RUNNING) {
3784 err = mxge_open(sc);
3786 ifp->if_mtu = old_mtu;
3788 (void) mxge_open(sc);
3795 mxge_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
3797 mxge_softc_t *sc = ifp->if_softc;
3802 ifmr->ifm_status = IFM_AVALID;
3803 ifmr->ifm_status |= sc->link_state ? IFM_ACTIVE : 0;
3804 ifmr->ifm_active = IFM_AUTO | IFM_ETHER;
3805 ifmr->ifm_active |= sc->link_state ? IFM_FDX : 0;
3809 mxge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3811 mxge_softc_t *sc = ifp->if_softc;
3812 struct ifreq *ifr = (struct ifreq *)data;
3817 ASSERT_SERIALIZED(ifp->if_serializer);
3821 err = ether_ioctl(ifp, command, data);
3825 err = mxge_change_mtu(sc, ifr->ifr_mtu);
3832 if (ifp->if_flags & IFF_UP) {
3833 if (!(ifp->if_flags & IFF_RUNNING)) {
3834 err = mxge_open(sc);
3836 /* take care of promis can allmulti
3838 mxge_change_promisc(sc,
3839 ifp->if_flags & IFF_PROMISC);
3840 mxge_set_multicast_list(sc);
3843 if (ifp->if_flags & IFF_RUNNING) {
3851 mxge_set_multicast_list(sc);
3855 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3856 if (mask & IFCAP_TXCSUM) {
3857 if (IFCAP_TXCSUM & ifp->if_capenable) {
3858 ifp->if_capenable &= ~(IFCAP_TXCSUM|IFCAP_TSO4);
3859 ifp->if_hwassist &= ~(CSUM_TCP | CSUM_UDP
3862 ifp->if_capenable |= IFCAP_TXCSUM;
3863 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP);
3865 } else if (mask & IFCAP_RXCSUM) {
3866 if (IFCAP_RXCSUM & ifp->if_capenable) {
3867 ifp->if_capenable &= ~IFCAP_RXCSUM;
3870 ifp->if_capenable |= IFCAP_RXCSUM;
3874 if (mask & IFCAP_TSO4) {
3875 if (IFCAP_TSO4 & ifp->if_capenable) {
3876 ifp->if_capenable &= ~IFCAP_TSO4;
3877 ifp->if_hwassist &= ~CSUM_TSO;
3878 } else if (IFCAP_TXCSUM & ifp->if_capenable) {
3879 ifp->if_capenable |= IFCAP_TSO4;
3880 ifp->if_hwassist |= CSUM_TSO;
3882 kprintf("mxge requires tx checksum offload"
3883 " be enabled to use TSO\n");
3887 if (mask & IFCAP_LRO) {
3888 if (IFCAP_LRO & ifp->if_capenable)
3889 err = mxge_change_lro_locked(sc, 0);
3891 err = mxge_change_lro_locked(sc, mxge_lro_cnt);
3893 if (mask & IFCAP_VLAN_HWTAGGING)
3894 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3895 VLAN_CAPABILITIES(ifp);
3900 err = ifmedia_ioctl(ifp, (struct ifreq *)data,
3901 &sc->media, command);
3911 mxge_fetch_tunables(mxge_softc_t *sc)
3914 TUNABLE_INT_FETCH("hw.mxge.max_slices", &mxge_max_slices);
3915 TUNABLE_INT_FETCH("hw.mxge.flow_control_enabled",
3916 &mxge_flow_control);
3917 TUNABLE_INT_FETCH("hw.mxge.intr_coal_delay",
3918 &mxge_intr_coal_delay);
3919 TUNABLE_INT_FETCH("hw.mxge.nvidia_ecrc_enable",
3920 &mxge_nvidia_ecrc_enable);
3921 TUNABLE_INT_FETCH("hw.mxge.force_firmware",
3922 &mxge_force_firmware);
3923 TUNABLE_INT_FETCH("hw.mxge.deassert_wait",
3924 &mxge_deassert_wait);
3925 TUNABLE_INT_FETCH("hw.mxge.verbose",
3927 TUNABLE_INT_FETCH("hw.mxge.ticks", &mxge_ticks);
3928 TUNABLE_INT_FETCH("hw.mxge.lro_cnt", &sc->lro_cnt);
3929 TUNABLE_INT_FETCH("hw.mxge.always_promisc", &mxge_always_promisc);
3930 TUNABLE_INT_FETCH("hw.mxge.rss_hash_type", &mxge_rss_hash_type);
3931 TUNABLE_INT_FETCH("hw.mxge.initial_mtu", &mxge_initial_mtu);
3932 if (sc->lro_cnt != 0)
3933 mxge_lro_cnt = sc->lro_cnt;
3937 if (mxge_intr_coal_delay < 0 || mxge_intr_coal_delay > 10*1000)
3938 mxge_intr_coal_delay = 30;
3939 if (mxge_ticks == 0)
3940 mxge_ticks = hz / 2;
3941 sc->pause = mxge_flow_control;
3942 if (mxge_rss_hash_type < MXGEFW_RSS_HASH_TYPE_IPV4
3943 || mxge_rss_hash_type > MXGEFW_RSS_HASH_TYPE_MAX) {
3944 mxge_rss_hash_type = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
3946 if (mxge_initial_mtu > ETHERMTU_JUMBO ||
3947 mxge_initial_mtu < ETHER_MIN_LEN)
3948 mxge_initial_mtu = ETHERMTU_JUMBO;
3953 mxge_free_slices(mxge_softc_t *sc)
3955 struct mxge_slice_state *ss;
3962 for (i = 0; i < sc->num_slices; i++) {
3964 if (ss->fw_stats != NULL) {
3965 mxge_dma_free(&ss->fw_stats_dma);
3966 ss->fw_stats = NULL;
3967 #ifdef IFNET_BUF_RING
3968 if (ss->tx.br != NULL) {
3969 drbr_free(ss->tx.br, M_DEVBUF);
3974 if (ss->rx_done.entry != NULL) {
3975 mxge_dma_free(&ss->rx_done.dma);
3976 ss->rx_done.entry = NULL;
3979 kfree(sc->ss, M_DEVBUF);
3984 mxge_alloc_slices(mxge_softc_t *sc)
3987 struct mxge_slice_state *ss;
3989 int err, i, max_intr_slots;
3991 err = mxge_send_cmd(sc, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd);
3993 device_printf(sc->dev, "Cannot determine rx ring size\n");
3996 sc->rx_ring_size = cmd.data0;
3997 max_intr_slots = 2 * (sc->rx_ring_size / sizeof (mcp_dma_addr_t));
3999 bytes = sizeof (*sc->ss) * sc->num_slices;
4000 sc->ss = kmalloc(bytes, M_DEVBUF, M_NOWAIT | M_ZERO);
4003 for (i = 0; i < sc->num_slices; i++) {
4008 /* allocate per-slice rx interrupt queues */
4010 bytes = max_intr_slots * sizeof (*ss->rx_done.entry);
4011 err = mxge_dma_alloc(sc, &ss->rx_done.dma, bytes, 4096);
4014 ss->rx_done.entry = ss->rx_done.dma.addr;
4015 bzero(ss->rx_done.entry, bytes);
4018 * allocate the per-slice firmware stats; stats
4019 * (including tx) are used used only on the first
4022 #ifndef IFNET_BUF_RING
4027 bytes = sizeof (*ss->fw_stats);
4028 err = mxge_dma_alloc(sc, &ss->fw_stats_dma,
4029 sizeof (*ss->fw_stats), 64);
4032 ss->fw_stats = (mcp_irq_data_t *)ss->fw_stats_dma.addr;
4033 #ifdef IFNET_BUF_RING
4034 ss->tx.br = buf_ring_alloc(2048, M_DEVBUF, M_WAITOK,
4042 mxge_free_slices(sc);
4047 mxge_slice_probe(mxge_softc_t *sc)
4051 int msix_cnt, status, max_intr_slots;
4055 * don't enable multiple slices if they are not enabled,
4056 * or if this is not an SMP system
4059 if (mxge_max_slices == 0 || mxge_max_slices == 1 || ncpus < 2)
4062 /* see how many MSI-X interrupts are available */
4063 msix_cnt = pci_msix_count(sc->dev);
4067 /* now load the slice aware firmware see what it supports */
4068 old_fw = sc->fw_name;
4069 if (old_fw == mxge_fw_aligned)
4070 sc->fw_name = mxge_fw_rss_aligned;
4072 sc->fw_name = mxge_fw_rss_unaligned;
4073 status = mxge_load_firmware(sc, 0);
4075 device_printf(sc->dev, "Falling back to a single slice\n");
4079 /* try to send a reset command to the card to see if it
4081 memset(&cmd, 0, sizeof (cmd));
4082 status = mxge_send_cmd(sc, MXGEFW_CMD_RESET, &cmd);
4084 device_printf(sc->dev, "failed reset\n");
4088 /* get rx ring size */
4089 status = mxge_send_cmd(sc, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd);
4091 device_printf(sc->dev, "Cannot determine rx ring size\n");
4094 max_intr_slots = 2 * (cmd.data0 / sizeof (mcp_dma_addr_t));
4096 /* tell it the size of the interrupt queues */
4097 cmd.data0 = max_intr_slots * sizeof (struct mcp_slot);
4098 status = mxge_send_cmd(sc, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd);
4100 device_printf(sc->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
4104 /* ask the maximum number of slices it supports */
4105 status = mxge_send_cmd(sc, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd);
4107 device_printf(sc->dev,
4108 "failed MXGEFW_CMD_GET_MAX_RSS_QUEUES\n");
4111 sc->num_slices = cmd.data0;
4112 if (sc->num_slices > msix_cnt)
4113 sc->num_slices = msix_cnt;
4115 if (mxge_max_slices == -1) {
4116 /* cap to number of CPUs in system */
4117 if (sc->num_slices > ncpus)
4118 sc->num_slices = ncpus;
4120 if (sc->num_slices > mxge_max_slices)
4121 sc->num_slices = mxge_max_slices;
4123 /* make sure it is a power of two */
4124 while (sc->num_slices & (sc->num_slices - 1))
4128 device_printf(sc->dev, "using %d slices\n",
4134 sc->fw_name = old_fw;
4135 (void) mxge_load_firmware(sc, 0);
4140 mxge_add_msix_irqs(mxge_softc_t *sc)
4143 int count, err, i, rid;
4146 sc->msix_table_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
4149 if (sc->msix_table_res == NULL) {
4150 device_printf(sc->dev, "couldn't alloc MSIX table res\n");
4154 count = sc->num_slices;
4155 err = pci_alloc_msix(sc->dev, &count);
4157 device_printf(sc->dev, "pci_alloc_msix: failed, wanted %d"
4158 "err = %d \n", sc->num_slices, err);
4159 goto abort_with_msix_table;
4161 if (count < sc->num_slices) {
4162 device_printf(sc->dev, "pci_alloc_msix: need %d, got %d\n",
4163 count, sc->num_slices);
4164 device_printf(sc->dev,
4165 "Try setting hw.mxge.max_slices to %d\n",
4168 goto abort_with_msix;
4170 bytes = sizeof (*sc->msix_irq_res) * sc->num_slices;
4171 sc->msix_irq_res = kmalloc(bytes, M_DEVBUF, M_NOWAIT|M_ZERO);
4172 if (sc->msix_irq_res == NULL) {
4174 goto abort_with_msix;
4177 for (i = 0; i < sc->num_slices; i++) {
4179 sc->msix_irq_res[i] = bus_alloc_resource_any(sc->dev,
4182 if (sc->msix_irq_res[i] == NULL) {
4183 device_printf(sc->dev, "couldn't allocate IRQ res"
4184 " for message %d\n", i);
4186 goto abort_with_res;
4190 bytes = sizeof (*sc->msix_ih) * sc->num_slices;
4191 sc->msix_ih = kmalloc(bytes, M_DEVBUF, M_NOWAIT|M_ZERO);
4193 for (i = 0; i < sc->num_slices; i++) {
4194 err = bus_setup_intr(sc->dev, sc->msix_irq_res[i],
4196 mxge_intr, &sc->ss[i], &sc->msix_ih[i],
4197 sc->ifp->if_serializer);
4199 device_printf(sc->dev, "couldn't setup intr for "
4201 goto abort_with_intr;
4206 device_printf(sc->dev, "using %d msix IRQs:",
4208 for (i = 0; i < sc->num_slices; i++)
4209 kprintf(" %ld", rman_get_start(sc->msix_irq_res[i]));
4215 for (i = 0; i < sc->num_slices; i++) {
4216 if (sc->msix_ih[i] != NULL) {
4217 bus_teardown_intr(sc->dev, sc->msix_irq_res[i],
4219 sc->msix_ih[i] = NULL;
4222 kfree(sc->msix_ih, M_DEVBUF);
4226 for (i = 0; i < sc->num_slices; i++) {
4228 if (sc->msix_irq_res[i] != NULL)
4229 bus_release_resource(sc->dev, SYS_RES_IRQ, rid,
4230 sc->msix_irq_res[i]);
4231 sc->msix_irq_res[i] = NULL;
4233 kfree(sc->msix_irq_res, M_DEVBUF);
4237 pci_release_msi(sc->dev);
4239 abort_with_msix_table:
4240 bus_release_resource(sc->dev, SYS_RES_MEMORY, PCIR_BAR(2),
4241 sc->msix_table_res);
4248 mxge_add_single_irq(mxge_softc_t *sc)
4254 count = pci_msi_count(sc->dev);
4255 if (count == 1 && pci_alloc_msi(sc->dev, &count) == 0) {
4265 sc->irq_res = bus_alloc_resource(sc->dev, SYS_RES_IRQ, &rid, 0, ~0,
4266 1, RF_SHAREABLE | RF_ACTIVE);
4267 if (sc->irq_res == NULL) {
4268 device_printf(sc->dev, "could not alloc interrupt\n");
4272 device_printf(sc->dev, "using %s irq %ld\n",
4273 sc->legacy_irq ? "INTx" : "MSI",
4274 rman_get_start(sc->irq_res));
4275 err = bus_setup_intr(sc->dev, sc->irq_res,
4277 mxge_intr, &sc->ss[0], &sc->ih,
4278 sc->ifp->if_serializer);
4280 bus_release_resource(sc->dev, SYS_RES_IRQ,
4281 sc->legacy_irq ? 0 : 1, sc->irq_res);
4282 if (!sc->legacy_irq)
4283 pci_release_msi(sc->dev);
4290 mxge_rem_msix_irqs(mxge_softc_t *sc)
4294 for (i = 0; i < sc->num_slices; i++) {
4295 if (sc->msix_ih[i] != NULL) {
4296 bus_teardown_intr(sc->dev, sc->msix_irq_res[i],
4298 sc->msix_ih[i] = NULL;
4301 kfree(sc->msix_ih, M_DEVBUF);
4303 for (i = 0; i < sc->num_slices; i++) {
4305 if (sc->msix_irq_res[i] != NULL)
4306 bus_release_resource(sc->dev, SYS_RES_IRQ, rid,
4307 sc->msix_irq_res[i]);
4308 sc->msix_irq_res[i] = NULL;
4310 kfree(sc->msix_irq_res, M_DEVBUF);
4312 bus_release_resource(sc->dev, SYS_RES_MEMORY, PCIR_BAR(2),
4313 sc->msix_table_res);
4315 pci_release_msi(sc->dev);
4321 mxge_rem_single_irq(mxge_softc_t *sc)
4323 bus_teardown_intr(sc->dev, sc->irq_res, sc->ih);
4324 bus_release_resource(sc->dev, SYS_RES_IRQ,
4325 sc->legacy_irq ? 0 : 1, sc->irq_res);
4326 if (!sc->legacy_irq)
4327 pci_release_msi(sc->dev);
4331 mxge_rem_irq(mxge_softc_t *sc)
4334 if (sc->num_slices > 1)
4335 mxge_rem_msix_irqs(sc);
4338 mxge_rem_single_irq(sc);
4342 mxge_add_irq(mxge_softc_t *sc)
4347 if (sc->num_slices > 1)
4348 err = mxge_add_msix_irqs(sc);
4350 err = mxge_add_single_irq(sc);
4352 if (0 && err == 0 && sc->num_slices > 1) {
4353 mxge_rem_msix_irqs(sc);
4354 err = mxge_add_msix_irqs(sc);
4358 return mxge_add_single_irq(sc);
4364 mxge_attach(device_t dev)
4366 mxge_softc_t *sc = device_get_softc(dev);
4367 struct ifnet *ifp = &sc->arpcom.ac_if;
4371 * avoid rewriting half the lines in this file to use
4372 * &sc->arpcom.ac_if instead
4376 mxge_fetch_tunables(sc);
4378 err = bus_dma_tag_create(NULL, /* parent */
4381 BUS_SPACE_MAXADDR, /* low */
4382 BUS_SPACE_MAXADDR, /* high */
4383 NULL, NULL, /* filter */
4384 65536 + 256, /* maxsize */
4385 MXGE_MAX_SEND_DESC, /* num segs */
4386 65536, /* maxsegsize */
4388 &sc->parent_dmat); /* tag */
4391 device_printf(sc->dev, "Err %d allocating parent dmat\n",
4393 goto abort_with_nothing;
4397 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
4399 callout_init_mp(&sc->co_hdl);
4401 mxge_setup_cfg_space(sc);
4403 /* Map the board into the kernel */
4405 sc->mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0,
4407 if (sc->mem_res == NULL) {
4408 device_printf(dev, "could not map memory\n");
4410 goto abort_with_nothing;
4412 sc->sram = rman_get_virtual(sc->mem_res);
4413 sc->sram_size = 2*1024*1024 - (2*(48*1024)+(32*1024)) - 0x100;
4414 if (sc->sram_size > rman_get_size(sc->mem_res)) {
4415 device_printf(dev, "impossible memory region size %ld\n",
4416 rman_get_size(sc->mem_res));
4418 goto abort_with_mem_res;
4421 /* make NULL terminated copy of the EEPROM strings section of
4423 bzero(sc->eeprom_strings, MXGE_EEPROM_STRINGS_SIZE);
4424 bus_space_read_region_1(rman_get_bustag(sc->mem_res),
4425 rman_get_bushandle(sc->mem_res),
4426 sc->sram_size - MXGE_EEPROM_STRINGS_SIZE,
4428 MXGE_EEPROM_STRINGS_SIZE - 2);
4429 err = mxge_parse_strings(sc);
4431 goto abort_with_mem_res;
4433 /* Enable write combining for efficient use of PCIe bus */
4436 /* Allocate the out of band dma memory */
4437 err = mxge_dma_alloc(sc, &sc->cmd_dma,
4438 sizeof (mxge_cmd_t), 64);
4440 goto abort_with_mem_res;
4441 sc->cmd = (mcp_cmd_response_t *) sc->cmd_dma.addr;
4442 err = mxge_dma_alloc(sc, &sc->zeropad_dma, 64, 64);
4444 goto abort_with_cmd_dma;
4446 err = mxge_dma_alloc(sc, &sc->dmabench_dma, 4096, 4096);
4448 goto abort_with_zeropad_dma;
4450 /* select & load the firmware */
4451 err = mxge_select_firmware(sc);
4453 goto abort_with_dmabench;
4454 sc->intr_coal_delay = mxge_intr_coal_delay;
4456 mxge_slice_probe(sc);
4457 err = mxge_alloc_slices(sc);
4459 goto abort_with_dmabench;
4461 err = mxge_reset(sc, 0);
4463 goto abort_with_slices;
4465 err = mxge_alloc_rings(sc);
4467 device_printf(sc->dev, "failed to allocate rings\n");
4468 goto abort_with_dmabench;
4471 ifp->if_baudrate = IF_Gbps(10UL);
4472 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4 |
4475 ifp->if_capabilities |= IFCAP_LRO;
4478 #ifdef MXGE_NEW_VLAN_API
4479 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM;
4482 sc->max_mtu = mxge_max_mtu(sc);
4483 if (sc->max_mtu >= 9000)
4484 ifp->if_capabilities |= IFCAP_JUMBO_MTU;
4486 device_printf(dev, "MTU limited to %d. Install "
4487 "latest firmware for 9000 byte jumbo support\n",
4488 sc->max_mtu - ETHER_HDR_LEN);
4489 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_TSO;
4490 ifp->if_capenable = ifp->if_capabilities;
4491 if (sc->lro_cnt == 0)
4492 ifp->if_capenable &= ~IFCAP_LRO;
4494 ifp->if_init = mxge_init;
4496 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
4497 ifp->if_ioctl = mxge_ioctl;
4498 ifp->if_start = mxge_start;
4499 /* Initialise the ifmedia structure */
4500 ifmedia_init(&sc->media, 0, mxge_media_change,
4502 mxge_set_media(sc, IFM_ETHER | IFM_AUTO);
4503 mxge_media_probe(sc);
4505 ether_ifattach(ifp, sc->mac_addr, NULL);
4506 /* ether_ifattach sets mtu to ETHERMTU */
4507 if (mxge_initial_mtu != ETHERMTU) {
4508 lwkt_serialize_enter(ifp->if_serializer);
4509 mxge_change_mtu(sc, mxge_initial_mtu);
4510 lwkt_serialize_exit(ifp->if_serializer);
4512 /* must come after ether_ifattach() */
4513 err = mxge_add_irq(sc);
4515 device_printf(sc->dev, "failed to add irq\n");
4516 goto abort_with_rings;
4519 mxge_add_sysctls(sc);
4520 #ifdef IFNET_BUF_RING
4521 ifp->if_transmit = mxge_transmit;
4522 ifp->if_qflush = mxge_qflush;
4527 mxge_free_rings(sc);
4529 mxge_free_slices(sc);
4530 abort_with_dmabench:
4531 mxge_dma_free(&sc->dmabench_dma);
4532 abort_with_zeropad_dma:
4533 mxge_dma_free(&sc->zeropad_dma);
4535 mxge_dma_free(&sc->cmd_dma);
4537 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BARS, sc->mem_res);
4538 pci_disable_busmaster(dev);
4539 bus_dma_tag_destroy(sc->parent_dmat);
4545 mxge_detach(device_t dev)
4547 mxge_softc_t *sc = device_get_softc(dev);
4549 lwkt_serialize_enter(sc->ifp->if_serializer);
4551 if (sc->ifp->if_flags & IFF_RUNNING)
4554 * XXX: race: the callout callback could be spinning on
4555 * the serializer and run anyway
4557 callout_stop(&sc->co_hdl);
4558 lwkt_serialize_exit(sc->ifp->if_serializer);
4560 ether_ifdetach(sc->ifp);
4561 ifmedia_removeall(&sc->media);
4562 mxge_dummy_rdma(sc, 0);
4563 mxge_rem_sysctls(sc);
4565 mxge_free_rings(sc);
4566 mxge_free_slices(sc);
4567 mxge_dma_free(&sc->dmabench_dma);
4568 mxge_dma_free(&sc->zeropad_dma);
4569 mxge_dma_free(&sc->cmd_dma);
4570 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BARS, sc->mem_res);
4571 pci_disable_busmaster(dev);
4572 bus_dma_tag_destroy(sc->parent_dmat);
4577 mxge_shutdown(device_t dev)