2 * Copyright (c) 2006 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Matthew Dillon <dillon@backplane.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * $DragonFly: src/sys/platform/vkernel/platform/machintr.c,v 1.17 2008/04/30 16:59:45 dillon Exp $
37 #include <sys/types.h>
38 #include <sys/systm.h>
39 #include <sys/kernel.h>
40 #include <sys/machintr.h>
41 #include <sys/errno.h>
43 #include <sys/globaldata.h>
44 #include <sys/interrupt.h>
47 #include <machine/globaldata.h>
48 #include <machine/md_var.h>
49 #include <sys/thread2.h>
52 * Interrupt Subsystem ABI
55 static void dummy_intr_disable(int);
56 static void dummy_intr_enable(int);
57 static void dummy_intr_setup(int, int);
58 static void dummy_intr_teardown(int);
59 static int dummy_legacy_intr_cpuid(int);
60 static void dummy_finalize(void);
61 static void dummy_intrcleanup(void);
62 static void dummy_stabilize(void);
64 struct machintr_abi MachIntrABI = {
66 .intr_disable = dummy_intr_disable,
67 .intr_enable = dummy_intr_enable,
68 .intr_setup = dummy_intr_setup,
69 .intr_teardown = dummy_intr_teardown,
70 .legacy_intr_cpuid = dummy_legacy_intr_cpuid,
72 .finalize = dummy_finalize,
73 .cleanup = dummy_intrcleanup,
74 .stabilize = dummy_stabilize
78 dummy_intr_disable(int intr)
83 dummy_intr_enable(int intr)
88 dummy_intr_setup(int intr, int flags)
93 dummy_intr_teardown(int intr)
103 dummy_intrcleanup(void)
108 dummy_stabilize(void)
113 dummy_legacy_intr_cpuid(int irq __unused)
119 * Process pending interrupts
124 struct mdglobaldata *gd = mdcpu;
125 thread_t td = gd->mi.gd_curthread;
128 while (gd->mi.gd_reqflags & (RQF_IPIQ|RQF_INTPEND)) {
129 crit_enter_quick(td);
131 if (gd->mi.gd_reqflags & RQF_IPIQ) {
132 atomic_clear_int(&gd->mi.gd_reqflags, RQF_IPIQ);
136 if (gd->mi.gd_reqflags & RQF_INTPEND) {
137 atomic_clear_int(&gd->mi.gd_reqflags, RQF_INTPEND);
138 while ((irq = ffs(gd->gd_spending)) != 0) {
140 atomic_clear_int(&gd->gd_spending, 1 << irq);
141 irq += FIRST_SOFTINT;
142 sched_ithd_soft(irq);
144 while ((irq = ffs(gd->gd_fpending)) != 0) {
146 atomic_clear_int(&gd->gd_fpending, 1 << irq);
147 sched_ithd_hard_virtual(irq);
150 crit_exit_noyield(td);
155 * Allows an unprotected signal handler or mailbox to signal an interrupt
157 * For sched_ithd_hard_virtaul() to properly preempt via lwkt_schedule() we
158 * cannot enter a critical section here. We use td_nest_count instead.
163 struct mdglobaldata *gd = mdcpu;
164 thread_t td = gd->mi.gd_curthread;
166 if (td->td_critcount || td->td_nest_count) {
167 atomic_set_int_nonlocked(&gd->gd_fpending, 1 << intr);
168 atomic_set_int(&gd->mi.gd_reqflags, RQF_INTPEND);
171 atomic_clear_int(&gd->gd_fpending, 1 << intr);
172 sched_ithd_hard_virtual(intr);
178 cpu_disable_intr(void)
180 sigblock(sigmask(SIGALRM)|sigmask(SIGIO)|sigmask(SIGUSR1));
184 cpu_enable_intr(void)
190 cpu_mask_all_signals(void)
192 sigblock(sigmask(SIGALRM)|sigmask(SIGIO)|sigmask(SIGQUIT)|
193 sigmask(SIGUSR1)|sigmask(SIGTERM)|sigmask(SIGWINCH)|
198 cpu_unmask_all_signals(void)
204 cpu_invlpg(void *addr)
206 madvise(addr, PAGE_SIZE, MADV_INVAL);
212 madvise((void *)KvaStart, KvaEnd - KvaStart, MADV_INVAL);