2 * Copyright (c) 1997, Stefan Esser <se@kfreebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@kfreebsd.org>
4 * Copyright (c) 2000, BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/pci/pci.c,v 1.355.2.9.2.1 2009/04/15 03:14:26 kensmith Exp $
33 #include "opt_compat_oldpci.h"
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/malloc.h>
38 #include <sys/module.h>
39 #include <sys/linker.h>
40 #include <sys/fcntl.h>
42 #include <sys/kernel.h>
43 #include <sys/queue.h>
44 #include <sys/sysctl.h>
45 #include <sys/endian.h>
49 #include <vm/vm_extern.h>
53 #include <sys/device.h>
55 #include <sys/pciio.h>
56 #include <bus/pci/pcireg.h>
57 #include <bus/pci/pcivar.h>
58 #include <bus/pci/pci_private.h>
64 #include <contrib/dev/acpica/acpi.h>
67 #define ACPI_PWR_FOR_SLEEP(x, y, z)
70 extern struct dev_ops pcic_ops; /* XXX */
72 typedef void (*pci_read_cap_t)(device_t, int, int, pcicfgregs *);
74 static uint32_t pci_mapbase(unsigned mapreg);
75 static const char *pci_maptype(unsigned mapreg);
76 static int pci_mapsize(unsigned testval);
77 static int pci_maprange(unsigned mapreg);
78 static void pci_fixancient(pcicfgregs *cfg);
80 static int pci_porten(device_t pcib, int b, int s, int f);
81 static int pci_memen(device_t pcib, int b, int s, int f);
82 static void pci_assign_interrupt(device_t bus, device_t dev,
84 static int pci_add_map(device_t pcib, device_t bus, device_t dev,
85 int b, int s, int f, int reg,
86 struct resource_list *rl, int force, int prefetch);
87 static int pci_probe(device_t dev);
88 static int pci_attach(device_t dev);
89 static void pci_child_detached(device_t, device_t);
90 static void pci_load_vendor_data(void);
91 static int pci_describe_parse_line(char **ptr, int *vendor,
92 int *device, char **desc);
93 static char *pci_describe_device(device_t dev);
94 static int pci_modevent(module_t mod, int what, void *arg);
95 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
97 static void pci_read_capabilities(device_t pcib, pcicfgregs *cfg);
98 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
99 int reg, uint32_t *data);
101 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
102 int reg, uint32_t data);
104 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
105 static void pci_disable_msi(device_t dev);
106 static void pci_enable_msi(device_t dev, uint64_t address,
108 static void pci_enable_msix(device_t dev, u_int index,
109 uint64_t address, uint32_t data);
110 static void pci_mask_msix(device_t dev, u_int index);
111 static void pci_unmask_msix(device_t dev, u_int index);
112 static int pci_msi_blacklisted(void);
113 static void pci_resume_msi(device_t dev);
114 static void pci_resume_msix(device_t dev);
115 static int pcie_slotimpl(const pcicfgregs *);
116 static void pci_print_verbose_expr(const pcicfgregs *);
118 static void pci_read_cap_pmgt(device_t, int, int, pcicfgregs *);
119 static void pci_read_cap_ht(device_t, int, int, pcicfgregs *);
120 static void pci_read_cap_msi(device_t, int, int, pcicfgregs *);
121 static void pci_read_cap_msix(device_t, int, int, pcicfgregs *);
122 static void pci_read_cap_vpd(device_t, int, int, pcicfgregs *);
123 static void pci_read_cap_subvendor(device_t, int, int,
125 static void pci_read_cap_pcix(device_t, int, int, pcicfgregs *);
126 static void pci_read_cap_express(device_t, int, int, pcicfgregs *);
128 static device_method_t pci_methods[] = {
129 /* Device interface */
130 DEVMETHOD(device_probe, pci_probe),
131 DEVMETHOD(device_attach, pci_attach),
132 DEVMETHOD(device_detach, bus_generic_detach),
133 DEVMETHOD(device_shutdown, bus_generic_shutdown),
134 DEVMETHOD(device_suspend, pci_suspend),
135 DEVMETHOD(device_resume, pci_resume),
138 DEVMETHOD(bus_print_child, pci_print_child),
139 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
140 DEVMETHOD(bus_read_ivar, pci_read_ivar),
141 DEVMETHOD(bus_write_ivar, pci_write_ivar),
142 DEVMETHOD(bus_driver_added, pci_driver_added),
143 DEVMETHOD(bus_child_detached, pci_child_detached),
144 DEVMETHOD(bus_setup_intr, pci_setup_intr),
145 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
147 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
148 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
149 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
150 DEVMETHOD(bus_delete_resource, pci_delete_resource),
151 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
152 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
153 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
154 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
155 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
156 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
159 DEVMETHOD(pci_read_config, pci_read_config_method),
160 DEVMETHOD(pci_write_config, pci_write_config_method),
161 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
162 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
163 DEVMETHOD(pci_enable_io, pci_enable_io_method),
164 DEVMETHOD(pci_disable_io, pci_disable_io_method),
165 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
166 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
167 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
168 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
169 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
170 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
171 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
172 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method),
173 DEVMETHOD(pci_remap_msix, pci_remap_msix_method),
174 DEVMETHOD(pci_release_msi, pci_release_msi_method),
175 DEVMETHOD(pci_msi_count, pci_msi_count_method),
176 DEVMETHOD(pci_msix_count, pci_msix_count_method),
181 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0);
183 static devclass_t pci_devclass;
184 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, NULL);
185 MODULE_VERSION(pci, 1);
187 static char *pci_vendordata;
188 static size_t pci_vendordata_size;
191 static const struct pci_read_cap {
193 pci_read_cap_t read_cap;
194 } pci_read_caps[] = {
195 { PCIY_PMG, pci_read_cap_pmgt },
196 { PCIY_HT, pci_read_cap_ht },
197 { PCIY_MSI, pci_read_cap_msi },
198 { PCIY_MSIX, pci_read_cap_msix },
199 { PCIY_VPD, pci_read_cap_vpd },
200 { PCIY_SUBVENDOR, pci_read_cap_subvendor },
201 { PCIY_PCIX, pci_read_cap_pcix },
202 { PCIY_EXPRESS, pci_read_cap_express },
203 { 0, NULL } /* required last entry */
207 uint32_t devid; /* Vendor/device of the card */
209 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
210 #define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */
215 struct pci_quirk pci_quirks[] = {
216 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
217 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
218 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
219 /* As does the Serverworks OSB4 (the SMBus mapping register) */
220 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
223 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
224 * or the CMIC-SL (AKA ServerWorks GC_LE).
226 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
227 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
230 * MSI doesn't work on earlier Intel chipsets including
231 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
233 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
234 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
235 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
236 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
237 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
238 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
239 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
242 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
245 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
250 /* map register information */
251 #define PCI_MAPMEM 0x01 /* memory map */
252 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
253 #define PCI_MAPPORT 0x04 /* port map */
255 struct devlist pci_devq;
256 uint32_t pci_generation;
257 uint32_t pci_numdevs = 0;
258 static int pcie_chipset, pcix_chipset;
261 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
263 static int pci_enable_io_modes = 1;
264 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
265 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
266 &pci_enable_io_modes, 1,
267 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
268 enable these bits correctly. We'd like to do this all the time, but there\n\
269 are some peripherals that this causes problems with.");
271 static int pci_do_power_nodriver = 0;
272 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
273 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
274 &pci_do_power_nodriver, 0,
275 "Place a function into D3 state when no driver attaches to it. 0 means\n\
276 disable. 1 means conservatively place devices into D3 state. 2 means\n\
277 aggressively place devices into D3 state. 3 means put absolutely everything\n\
280 static int pci_do_power_resume = 1;
281 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
282 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
283 &pci_do_power_resume, 1,
284 "Transition from D3 -> D0 on resume.");
286 static int pci_do_msi = 1;
287 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
288 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
289 "Enable support for MSI interrupts");
291 static int pci_do_msix = 1;
292 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
293 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
294 "Enable support for MSI-X interrupts");
296 static int pci_honor_msi_blacklist = 1;
297 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
298 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
299 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI");
301 /* Find a device_t by bus/slot/function in domain 0 */
304 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
307 return (pci_find_dbsf(0, bus, slot, func));
310 /* Find a device_t by domain/bus/slot/function */
313 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
315 struct pci_devinfo *dinfo;
317 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
318 if ((dinfo->cfg.domain == domain) &&
319 (dinfo->cfg.bus == bus) &&
320 (dinfo->cfg.slot == slot) &&
321 (dinfo->cfg.func == func)) {
322 return (dinfo->cfg.dev);
329 /* Find a device_t by vendor/device ID */
332 pci_find_device(uint16_t vendor, uint16_t device)
334 struct pci_devinfo *dinfo;
336 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
337 if ((dinfo->cfg.vendor == vendor) &&
338 (dinfo->cfg.device == device)) {
339 return (dinfo->cfg.dev);
346 /* return base address of memory or port map */
349 pci_mapbase(uint32_t mapreg)
352 if (PCI_BAR_MEM(mapreg))
353 return (mapreg & PCIM_BAR_MEM_BASE);
355 return (mapreg & PCIM_BAR_IO_BASE);
358 /* return map type of memory or port map */
361 pci_maptype(unsigned mapreg)
364 if (PCI_BAR_IO(mapreg))
366 if (mapreg & PCIM_BAR_MEM_PREFETCH)
367 return ("Prefetchable Memory");
371 /* return log2 of map size decoded for memory or port map */
374 pci_mapsize(uint32_t testval)
378 testval = pci_mapbase(testval);
381 while ((testval & 1) == 0)
390 /* return log2 of address range supported by map register */
393 pci_maprange(unsigned mapreg)
397 if (PCI_BAR_IO(mapreg))
400 switch (mapreg & PCIM_BAR_MEM_TYPE) {
401 case PCIM_BAR_MEM_32:
404 case PCIM_BAR_MEM_1MB:
407 case PCIM_BAR_MEM_64:
414 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
417 pci_fixancient(pcicfgregs *cfg)
419 if (cfg->hdrtype != 0)
422 /* PCI to PCI bridges use header type 1 */
423 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
427 /* extract header type specific config data */
430 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
432 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
433 switch (cfg->hdrtype) {
435 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
436 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
437 cfg->nummaps = PCI_MAXMAPS_0;
440 cfg->nummaps = PCI_MAXMAPS_1;
442 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
446 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
447 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
448 cfg->nummaps = PCI_MAXMAPS_2;
450 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
457 /* read configuration header into pcicfgregs structure */
459 pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
461 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
462 pcicfgregs *cfg = NULL;
463 struct pci_devinfo *devlist_entry;
464 struct devlist *devlist_head;
466 devlist_head = &pci_devq;
468 devlist_entry = NULL;
470 if (REG(PCIR_DEVVENDOR, 4) != -1) {
471 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
473 cfg = &devlist_entry->cfg;
479 cfg->vendor = REG(PCIR_VENDOR, 2);
480 cfg->device = REG(PCIR_DEVICE, 2);
481 cfg->cmdreg = REG(PCIR_COMMAND, 2);
482 cfg->statreg = REG(PCIR_STATUS, 2);
483 cfg->baseclass = REG(PCIR_CLASS, 1);
484 cfg->subclass = REG(PCIR_SUBCLASS, 1);
485 cfg->progif = REG(PCIR_PROGIF, 1);
486 cfg->revid = REG(PCIR_REVID, 1);
487 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
488 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
489 cfg->lattimer = REG(PCIR_LATTIMER, 1);
490 cfg->intpin = REG(PCIR_INTPIN, 1);
491 cfg->intline = REG(PCIR_INTLINE, 1);
493 cfg->mingnt = REG(PCIR_MINGNT, 1);
494 cfg->maxlat = REG(PCIR_MAXLAT, 1);
496 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
497 cfg->hdrtype &= ~PCIM_MFDEV;
500 pci_hdrtypedata(pcib, b, s, f, cfg);
502 pci_read_capabilities(pcib, cfg);
504 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
506 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
507 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
508 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
509 devlist_entry->conf.pc_sel.pc_func = cfg->func;
510 devlist_entry->conf.pc_hdr = cfg->hdrtype;
512 devlist_entry->conf.pc_subvendor = cfg->subvendor;
513 devlist_entry->conf.pc_subdevice = cfg->subdevice;
514 devlist_entry->conf.pc_vendor = cfg->vendor;
515 devlist_entry->conf.pc_device = cfg->device;
517 devlist_entry->conf.pc_class = cfg->baseclass;
518 devlist_entry->conf.pc_subclass = cfg->subclass;
519 devlist_entry->conf.pc_progif = cfg->progif;
520 devlist_entry->conf.pc_revid = cfg->revid;
525 return (devlist_entry);
530 pci_fixup_nextptr(int *nextptr0)
532 int nextptr = *nextptr0;
534 /* "Next pointer" is only one byte */
535 KASSERT(nextptr <= 0xff, ("Illegal next pointer %d\n", nextptr));
539 * PCI local bus spec 3.0:
541 * "... The bottom two bits of all pointers are reserved
542 * and must be implemented as 00b although software must
543 * mask them to allow for future uses of these bits ..."
546 kprintf("Illegal PCI extended capability "
547 "offset, fixup 0x%02x -> 0x%02x\n",
548 nextptr, nextptr & ~0x3);
554 if (nextptr < 0x40) {
556 kprintf("Illegal PCI extended capability "
557 "offset 0x%02x", nextptr);
565 pci_read_cap_pmgt(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
568 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
570 struct pcicfg_pp *pp = &cfg->pp;
575 pp->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
576 pp->pp_status = ptr + PCIR_POWER_STATUS;
577 pp->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
579 if ((nextptr - ptr) > PCIR_POWER_DATA) {
582 * We should write to data_select and read back from
583 * data_scale to determine whether data register is
587 pp->pp_data = ptr + PCIR_POWER_DATA;
597 pci_read_cap_ht(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
600 #if defined(__i386__) || defined(__x86_64__)
603 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
605 struct pcicfg_ht *ht = &cfg->ht;
609 /* Determine HT-specific capability type. */
610 val = REG(ptr + PCIR_HT_COMMAND, 2);
612 if ((val & PCIM_HTCMD_CAP_MASK) != PCIM_HTCAP_MSI_MAPPING)
615 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
616 /* Sanity check the mapping window. */
617 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 4);
619 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 4);
620 if (addr != MSI_INTEL_ADDR_BASE) {
621 device_printf(pcib, "HT Bridge at pci%d:%d:%d:%d "
622 "has non-default MSI window 0x%llx\n",
623 cfg->domain, cfg->bus, cfg->slot, cfg->func,
627 addr = MSI_INTEL_ADDR_BASE;
631 ht->ht_msictrl = val;
632 ht->ht_msiaddr = addr;
636 #endif /* __i386__ || __x86_64__ */
641 pci_read_cap_msi(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
644 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
646 struct pcicfg_msi *msi = &cfg->msi;
648 msi->msi_location = ptr;
649 msi->msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
650 msi->msi_msgnum = 1 << ((msi->msi_ctrl & PCIM_MSICTRL_MMC_MASK) >> 1);
656 pci_read_cap_msix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
659 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
661 struct pcicfg_msix *msix = &cfg->msix;
664 msix->msix_location = ptr;
665 msix->msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
666 msix->msix_msgnum = (msix->msix_ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
668 val = REG(ptr + PCIR_MSIX_TABLE, 4);
669 msix->msix_table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
670 msix->msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
672 val = REG(ptr + PCIR_MSIX_PBA, 4);
673 msix->msix_pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
674 msix->msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
680 pci_read_cap_vpd(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
682 cfg->vpd.vpd_reg = ptr;
686 pci_read_cap_subvendor(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
689 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
691 /* Should always be true. */
692 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) {
695 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
696 cfg->subvendor = val & 0xffff;
697 cfg->subdevice = val >> 16;
704 pci_read_cap_pcix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
707 * Assume we have a PCI-X chipset if we have
708 * at least one PCI-PCI bridge with a PCI-X
709 * capability. Note that some systems with
710 * PCI-express or HT chipsets might match on
711 * this check as well.
713 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1)
716 cfg->pcix.pcix_ptr = ptr;
720 pcie_slotimpl(const pcicfgregs *cfg)
722 const struct pcicfg_expr *expr = &cfg->expr;
726 * Only version 1 can be parsed currently
728 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
732 * - Slot implemented bit is meaningful iff current port is
733 * root port or down stream port.
734 * - Testing for root port or down stream port is meanningful
735 * iff PCI configure has type 1 header.
738 if (cfg->hdrtype != 1)
741 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
742 if (port_type != PCIE_ROOT_PORT && port_type != PCIE_DOWN_STREAM_PORT)
745 if (!(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
752 pci_read_cap_express(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
755 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
757 struct pcicfg_expr *expr = &cfg->expr;
760 * Assume we have a PCI-express chipset if we have
761 * at least one PCI-express device.
765 expr->expr_ptr = ptr;
766 expr->expr_cap = REG(ptr + PCIER_CAPABILITY, 2);
769 * Only version 1 can be parsed currently
771 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
775 * Read slot capabilities. Slot capabilities exists iff
776 * current port's slot is implemented
778 if (pcie_slotimpl(cfg))
779 expr->expr_slotcap = REG(ptr + PCIER_SLOTCAP, 4);
785 pci_read_capabilities(device_t pcib, pcicfgregs *cfg)
787 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
788 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
793 if ((REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) == 0) {
794 /* No capabilities */
798 switch (cfg->hdrtype & PCIM_HDRTYPE) {
801 ptrptr = PCIR_CAP_PTR;
804 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
807 return; /* no capabilities support */
809 nextptr = REG(ptrptr, 1); /* sanity check? */
812 * Read capability entries.
814 while (pci_fixup_nextptr(&nextptr)) {
815 const struct pci_read_cap *rc;
818 /* Find the next entry */
819 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
821 /* Process this entry */
822 val = REG(ptr + PCICAP_ID, 1);
823 for (rc = pci_read_caps; rc->read_cap != NULL; ++rc) {
824 if (rc->cap == val) {
825 rc->read_cap(pcib, ptr, nextptr, cfg);
830 /* REG and WREG use carry through to next functions */
834 * PCI Vital Product Data
837 #define PCI_VPD_TIMEOUT 1000000
840 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
842 int count = PCI_VPD_TIMEOUT;
844 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
846 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
848 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
851 DELAY(1); /* limit looping */
853 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
860 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
862 int count = PCI_VPD_TIMEOUT;
864 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
866 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
867 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
868 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
871 DELAY(1); /* limit looping */
878 #undef PCI_VPD_TIMEOUT
880 struct vpd_readstate {
890 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
895 if (vrs->bytesinval == 0) {
896 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
898 vrs->val = le32toh(reg);
900 byte = vrs->val & 0xff;
903 vrs->val = vrs->val >> 8;
904 byte = vrs->val & 0xff;
914 pcie_slot_implemented(device_t dev)
916 struct pci_devinfo *dinfo = device_get_ivars(dev);
918 return pcie_slotimpl(&dinfo->cfg);
922 pcie_set_max_readrq(device_t dev, uint16_t rqsize)
927 rqsize &= PCIEM_DEVCTL_MAX_READRQ_MASK;
928 if (rqsize > PCIEM_DEVCTL_MAX_READRQ_4096) {
929 panic("%s: invalid max read request size 0x%02x\n",
930 device_get_nameunit(dev), rqsize);
933 expr_ptr = pci_get_pciecap_ptr(dev);
935 panic("%s: not PCIe device\n", device_get_nameunit(dev));
937 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
938 if ((val & PCIEM_DEVCTL_MAX_READRQ_MASK) != rqsize) {
940 device_printf(dev, "adjust device control 0x%04x", val);
942 val &= ~PCIEM_DEVCTL_MAX_READRQ_MASK;
944 pci_write_config(dev, expr_ptr + PCIER_DEVCTRL, val, 2);
947 kprintf(" -> 0x%04x\n", val);
952 pcie_get_max_readrq(device_t dev)
957 expr_ptr = pci_get_pciecap_ptr(dev);
959 panic("%s: not PCIe device\n", device_get_nameunit(dev));
961 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
962 return (val & PCIEM_DEVCTL_MAX_READRQ_MASK);
966 pci_read_vpd(device_t pcib, pcicfgregs *cfg)
968 struct vpd_readstate vrs;
973 int alloc, off; /* alloc/off for RO/W arrays */
979 /* init vpd reader */
987 name = remain = i = 0; /* shut up stupid gcc */
988 alloc = off = 0; /* shut up stupid gcc */
989 dflen = 0; /* shut up stupid gcc */
992 if (vpd_nextbyte(&vrs, &byte)) {
997 kprintf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
998 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
999 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
1002 case 0: /* item name */
1004 if (vpd_nextbyte(&vrs, &byte2)) {
1009 if (vpd_nextbyte(&vrs, &byte2)) {
1013 remain |= byte2 << 8;
1014 if (remain > (0x7f*4 - vrs.off)) {
1017 "pci%d:%d:%d:%d: invalid VPD data, remain %#x\n",
1018 cfg->domain, cfg->bus, cfg->slot,
1023 remain = byte & 0x7;
1024 name = (byte >> 3) & 0xf;
1027 case 0x2: /* String */
1028 cfg->vpd.vpd_ident = kmalloc(remain + 1,
1029 M_DEVBUF, M_WAITOK);
1036 case 0x10: /* VPD-R */
1039 cfg->vpd.vpd_ros = kmalloc(alloc *
1040 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
1044 case 0x11: /* VPD-W */
1047 cfg->vpd.vpd_w = kmalloc(alloc *
1048 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
1052 default: /* Invalid data, abort */
1058 case 1: /* Identifier String */
1059 cfg->vpd.vpd_ident[i++] = byte;
1062 cfg->vpd.vpd_ident[i] = '\0';
1067 case 2: /* VPD-R Keyword Header */
1069 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
1070 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
1071 M_DEVBUF, M_WAITOK | M_ZERO);
1073 cfg->vpd.vpd_ros[off].keyword[0] = byte;
1074 if (vpd_nextbyte(&vrs, &byte2)) {
1078 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
1079 if (vpd_nextbyte(&vrs, &byte2)) {
1085 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
1088 * if this happens, we can't trust the rest
1092 "pci%d:%d:%d:%d: bad keyword length: %d\n",
1093 cfg->domain, cfg->bus, cfg->slot,
1098 } else if (dflen == 0) {
1099 cfg->vpd.vpd_ros[off].value = kmalloc(1 *
1100 sizeof(*cfg->vpd.vpd_ros[off].value),
1101 M_DEVBUF, M_WAITOK);
1102 cfg->vpd.vpd_ros[off].value[0] = '\x00';
1104 cfg->vpd.vpd_ros[off].value = kmalloc(
1106 sizeof(*cfg->vpd.vpd_ros[off].value),
1107 M_DEVBUF, M_WAITOK);
1110 /* keep in sync w/ state 3's transistions */
1111 if (dflen == 0 && remain == 0)
1113 else if (dflen == 0)
1119 case 3: /* VPD-R Keyword Value */
1120 cfg->vpd.vpd_ros[off].value[i++] = byte;
1121 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
1122 "RV", 2) == 0 && cksumvalid == -1) {
1128 "pci%d:%d:%d:%d: bad VPD cksum, remain %hhu\n",
1129 cfg->domain, cfg->bus,
1130 cfg->slot, cfg->func,
1139 /* keep in sync w/ state 2's transistions */
1141 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
1142 if (dflen == 0 && remain == 0) {
1143 cfg->vpd.vpd_rocnt = off;
1144 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
1145 off * sizeof(*cfg->vpd.vpd_ros),
1146 M_DEVBUF, M_WAITOK | M_ZERO);
1148 } else if (dflen == 0)
1158 case 5: /* VPD-W Keyword Header */
1160 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
1161 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
1162 M_DEVBUF, M_WAITOK | M_ZERO);
1164 cfg->vpd.vpd_w[off].keyword[0] = byte;
1165 if (vpd_nextbyte(&vrs, &byte2)) {
1169 cfg->vpd.vpd_w[off].keyword[1] = byte2;
1170 if (vpd_nextbyte(&vrs, &byte2)) {
1174 cfg->vpd.vpd_w[off].len = dflen = byte2;
1175 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
1176 cfg->vpd.vpd_w[off].value = kmalloc((dflen + 1) *
1177 sizeof(*cfg->vpd.vpd_w[off].value),
1178 M_DEVBUF, M_WAITOK);
1181 /* keep in sync w/ state 6's transistions */
1182 if (dflen == 0 && remain == 0)
1184 else if (dflen == 0)
1190 case 6: /* VPD-W Keyword Value */
1191 cfg->vpd.vpd_w[off].value[i++] = byte;
1194 /* keep in sync w/ state 5's transistions */
1196 cfg->vpd.vpd_w[off++].value[i++] = '\0';
1197 if (dflen == 0 && remain == 0) {
1198 cfg->vpd.vpd_wcnt = off;
1199 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
1200 off * sizeof(*cfg->vpd.vpd_w),
1201 M_DEVBUF, M_WAITOK | M_ZERO);
1203 } else if (dflen == 0)
1208 kprintf("pci%d:%d:%d:%d: invalid state: %d\n",
1209 cfg->domain, cfg->bus, cfg->slot, cfg->func,
1216 if (cksumvalid == 0 || state < -1) {
1217 /* read-only data bad, clean up */
1218 if (cfg->vpd.vpd_ros != NULL) {
1219 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
1220 kfree(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
1221 kfree(cfg->vpd.vpd_ros, M_DEVBUF);
1222 cfg->vpd.vpd_ros = NULL;
1226 /* I/O error, clean up */
1227 kprintf("pci%d:%d:%d:%d: failed to read VPD data.\n",
1228 cfg->domain, cfg->bus, cfg->slot, cfg->func);
1229 if (cfg->vpd.vpd_ident != NULL) {
1230 kfree(cfg->vpd.vpd_ident, M_DEVBUF);
1231 cfg->vpd.vpd_ident = NULL;
1233 if (cfg->vpd.vpd_w != NULL) {
1234 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1235 kfree(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1236 kfree(cfg->vpd.vpd_w, M_DEVBUF);
1237 cfg->vpd.vpd_w = NULL;
1240 cfg->vpd.vpd_cached = 1;
1246 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1248 struct pci_devinfo *dinfo = device_get_ivars(child);
1249 pcicfgregs *cfg = &dinfo->cfg;
1251 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1252 pci_read_vpd(device_get_parent(dev), cfg);
1254 *identptr = cfg->vpd.vpd_ident;
1256 if (*identptr == NULL)
1263 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1266 struct pci_devinfo *dinfo = device_get_ivars(child);
1267 pcicfgregs *cfg = &dinfo->cfg;
1270 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1271 pci_read_vpd(device_get_parent(dev), cfg);
1273 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1274 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1275 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1276 *vptr = cfg->vpd.vpd_ros[i].value;
1279 if (i != cfg->vpd.vpd_rocnt)
1287 * Return the offset in configuration space of the requested extended
1288 * capability entry or 0 if the specified capability was not found.
1291 pci_find_extcap_method(device_t dev, device_t child, int capability,
1294 struct pci_devinfo *dinfo = device_get_ivars(child);
1295 pcicfgregs *cfg = &dinfo->cfg;
1300 * Check the CAP_LIST bit of the PCI status register first.
1302 status = pci_read_config(child, PCIR_STATUS, 2);
1303 if (!(status & PCIM_STATUS_CAPPRESENT))
1307 * Determine the start pointer of the capabilities list.
1309 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1315 ptr = PCIR_CAP_PTR_2;
1319 return (ENXIO); /* no extended capabilities support */
1321 ptr = pci_read_config(child, ptr, 1);
1324 * Traverse the capabilities list.
1327 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1332 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1339 * Support for MSI-X message interrupts.
1342 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
1344 struct pci_devinfo *dinfo = device_get_ivars(dev);
1345 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1348 KASSERT(msix->msix_table_len > index, ("bogus index"));
1349 offset = msix->msix_table_offset + index * 16;
1350 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1351 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1352 bus_write_4(msix->msix_table_res, offset + 8, data);
1354 /* Enable MSI -> HT mapping. */
1355 pci_ht_map_msi(dev, address);
1359 pci_mask_msix(device_t dev, u_int index)
1361 struct pci_devinfo *dinfo = device_get_ivars(dev);
1362 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1363 uint32_t offset, val;
1365 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1366 offset = msix->msix_table_offset + index * 16 + 12;
1367 val = bus_read_4(msix->msix_table_res, offset);
1368 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1369 val |= PCIM_MSIX_VCTRL_MASK;
1370 bus_write_4(msix->msix_table_res, offset, val);
1375 pci_unmask_msix(device_t dev, u_int index)
1377 struct pci_devinfo *dinfo = device_get_ivars(dev);
1378 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1379 uint32_t offset, val;
1381 KASSERT(msix->msix_table_len > index, ("bogus index"));
1382 offset = msix->msix_table_offset + index * 16 + 12;
1383 val = bus_read_4(msix->msix_table_res, offset);
1384 if (val & PCIM_MSIX_VCTRL_MASK) {
1385 val &= ~PCIM_MSIX_VCTRL_MASK;
1386 bus_write_4(msix->msix_table_res, offset, val);
1391 pci_pending_msix(device_t dev, u_int index)
1393 struct pci_devinfo *dinfo = device_get_ivars(dev);
1394 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1395 uint32_t offset, bit;
1397 KASSERT(msix->msix_table_len > index, ("bogus index"));
1398 offset = msix->msix_pba_offset + (index / 32) * 4;
1399 bit = 1 << index % 32;
1400 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1404 * Restore MSI-X registers and table during resume. If MSI-X is
1405 * enabled then walk the virtual table to restore the actual MSI-X
1409 pci_resume_msix(device_t dev)
1411 struct pci_devinfo *dinfo = device_get_ivars(dev);
1412 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1413 struct msix_table_entry *mte;
1414 struct msix_vector *mv;
1417 if (msix->msix_alloc > 0) {
1418 /* First, mask all vectors. */
1419 for (i = 0; i < msix->msix_msgnum; i++)
1420 pci_mask_msix(dev, i);
1422 /* Second, program any messages with at least one handler. */
1423 for (i = 0; i < msix->msix_table_len; i++) {
1424 mte = &msix->msix_table[i];
1425 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1427 mv = &msix->msix_vectors[mte->mte_vector - 1];
1428 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data);
1429 pci_unmask_msix(dev, i);
1432 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1433 msix->msix_ctrl, 2);
1437 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1438 * returned in *count. After this function returns, each message will be
1439 * available to the driver as SYS_RES_IRQ resources starting at rid 1.
1442 pci_alloc_msix_method(device_t dev, device_t child, int *count)
1444 struct pci_devinfo *dinfo = device_get_ivars(child);
1445 pcicfgregs *cfg = &dinfo->cfg;
1446 struct resource_list_entry *rle;
1447 int actual, error, i, irq, max;
1449 /* Don't let count == 0 get us into trouble. */
1453 /* If rid 0 is allocated, then fail. */
1454 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1455 if (rle != NULL && rle->res != NULL)
1458 /* Already have allocated messages? */
1459 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1462 /* If MSI is blacklisted for this system, fail. */
1463 if (pci_msi_blacklisted())
1466 /* MSI-X capability present? */
1467 if (cfg->msix.msix_location == 0 || !pci_do_msix)
1470 /* Make sure the appropriate BARs are mapped. */
1471 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1472 cfg->msix.msix_table_bar);
1473 if (rle == NULL || rle->res == NULL ||
1474 !(rman_get_flags(rle->res) & RF_ACTIVE))
1476 cfg->msix.msix_table_res = rle->res;
1477 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1478 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1479 cfg->msix.msix_pba_bar);
1480 if (rle == NULL || rle->res == NULL ||
1481 !(rman_get_flags(rle->res) & RF_ACTIVE))
1484 cfg->msix.msix_pba_res = rle->res;
1487 device_printf(child,
1488 "attempting to allocate %d MSI-X vectors (%d supported)\n",
1489 *count, cfg->msix.msix_msgnum);
1490 max = min(*count, cfg->msix.msix_msgnum);
1491 for (i = 0; i < max; i++) {
1492 /* Allocate a message. */
1493 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq);
1496 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1503 device_printf(child,
1504 "could not allocate any MSI-X vectors\n");
1510 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
1512 device_printf(child, "using IRQ %lu for MSI-X\n",
1518 * Be fancy and try to print contiguous runs of
1519 * IRQ values as ranges. 'irq' is the previous IRQ.
1520 * 'run' is true if we are in a range.
1522 device_printf(child, "using IRQs %lu", rle->start);
1525 for (i = 1; i < actual; i++) {
1526 rle = resource_list_find(&dinfo->resources,
1527 SYS_RES_IRQ, i + 1);
1529 /* Still in a run? */
1530 if (rle->start == irq + 1) {
1536 /* Finish previous range. */
1538 kprintf("-%d", irq);
1542 /* Start new range. */
1543 kprintf(",%lu", rle->start);
1547 /* Unfinished range? */
1549 kprintf("-%d", irq);
1550 kprintf(" for MSI-X\n");
1554 /* Mask all vectors. */
1555 for (i = 0; i < cfg->msix.msix_msgnum; i++)
1556 pci_mask_msix(child, i);
1558 /* Allocate and initialize vector data and virtual table. */
1559 cfg->msix.msix_vectors = kmalloc(sizeof(struct msix_vector) * actual,
1560 M_DEVBUF, M_WAITOK | M_ZERO);
1561 cfg->msix.msix_table = kmalloc(sizeof(struct msix_table_entry) * actual,
1562 M_DEVBUF, M_WAITOK | M_ZERO);
1563 for (i = 0; i < actual; i++) {
1564 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1565 cfg->msix.msix_vectors[i].mv_irq = rle->start;
1566 cfg->msix.msix_table[i].mte_vector = i + 1;
1569 /* Update control register to enable MSI-X. */
1570 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1571 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
1572 cfg->msix.msix_ctrl, 2);
1574 /* Update counts of alloc'd messages. */
1575 cfg->msix.msix_alloc = actual;
1576 cfg->msix.msix_table_len = actual;
1582 * By default, pci_alloc_msix() will assign the allocated IRQ
1583 * resources consecutively to the first N messages in the MSI-X table.
1584 * However, device drivers may want to use different layouts if they
1585 * either receive fewer messages than they asked for, or they wish to
1586 * populate the MSI-X table sparsely. This method allows the driver
1587 * to specify what layout it wants. It must be called after a
1588 * successful pci_alloc_msix() but before any of the associated
1589 * SYS_RES_IRQ resources are allocated via bus_alloc_resource().
1591 * The 'vectors' array contains 'count' message vectors. The array
1592 * maps directly to the MSI-X table in that index 0 in the array
1593 * specifies the vector for the first message in the MSI-X table, etc.
1594 * The vector value in each array index can either be 0 to indicate
1595 * that no vector should be assigned to a message slot, or it can be a
1596 * number from 1 to N (where N is the count returned from a
1597 * succcessful call to pci_alloc_msix()) to indicate which message
1598 * vector (IRQ) to be used for the corresponding message.
1600 * On successful return, each message with a non-zero vector will have
1601 * an associated SYS_RES_IRQ whose rid is equal to the array index +
1602 * 1. Additionally, if any of the IRQs allocated via the previous
1603 * call to pci_alloc_msix() are not used in the mapping, those IRQs
1604 * will be kfreed back to the system automatically.
1606 * For example, suppose a driver has a MSI-X table with 6 messages and
1607 * asks for 6 messages, but pci_alloc_msix() only returns a count of
1608 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and
1609 * C. After the call to pci_alloc_msix(), the device will be setup to
1610 * have an MSI-X table of ABC--- (where - means no vector assigned).
1611 * If the driver ten passes a vector array of { 1, 0, 1, 2, 0, 2 },
1612 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
1613 * be kfreed back to the system. This device will also have valid
1614 * SYS_RES_IRQ rids of 1, 3, 4, and 6.
1616 * In any case, the SYS_RES_IRQ rid X will always map to the message
1617 * at MSI-X table index X - 1 and will only be valid if a vector is
1618 * assigned to that table entry.
1621 pci_remap_msix_method(device_t dev, device_t child, int count,
1622 const u_int *vectors)
1624 struct pci_devinfo *dinfo = device_get_ivars(child);
1625 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1626 struct resource_list_entry *rle;
1627 int i, irq, j, *used;
1630 * Have to have at least one message in the table but the
1631 * table can't be bigger than the actual MSI-X table in the
1634 if (count == 0 || count > msix->msix_msgnum)
1637 /* Sanity check the vectors. */
1638 for (i = 0; i < count; i++)
1639 if (vectors[i] > msix->msix_alloc)
1643 * Make sure there aren't any holes in the vectors to be used.
1644 * It's a big pain to support it, and it doesn't really make
1645 * sense anyway. Also, at least one vector must be used.
1647 used = kmalloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK |
1649 for (i = 0; i < count; i++)
1650 if (vectors[i] != 0)
1651 used[vectors[i] - 1] = 1;
1652 for (i = 0; i < msix->msix_alloc - 1; i++)
1653 if (used[i] == 0 && used[i + 1] == 1) {
1654 kfree(used, M_DEVBUF);
1658 kfree(used, M_DEVBUF);
1662 /* Make sure none of the resources are allocated. */
1663 for (i = 0; i < msix->msix_table_len; i++) {
1664 if (msix->msix_table[i].mte_vector == 0)
1666 if (msix->msix_table[i].mte_handlers > 0)
1668 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1669 KASSERT(rle != NULL, ("missing resource"));
1670 if (rle->res != NULL)
1674 /* Free the existing resource list entries. */
1675 for (i = 0; i < msix->msix_table_len; i++) {
1676 if (msix->msix_table[i].mte_vector == 0)
1678 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1682 * Build the new virtual table keeping track of which vectors are
1685 kfree(msix->msix_table, M_DEVBUF);
1686 msix->msix_table = kmalloc(sizeof(struct msix_table_entry) * count,
1687 M_DEVBUF, M_WAITOK | M_ZERO);
1688 for (i = 0; i < count; i++)
1689 msix->msix_table[i].mte_vector = vectors[i];
1690 msix->msix_table_len = count;
1692 /* Free any unused IRQs and resize the vectors array if necessary. */
1693 j = msix->msix_alloc - 1;
1695 struct msix_vector *vec;
1697 while (used[j] == 0) {
1698 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1699 msix->msix_vectors[j].mv_irq);
1702 vec = kmalloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF,
1704 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) *
1706 kfree(msix->msix_vectors, M_DEVBUF);
1707 msix->msix_vectors = vec;
1708 msix->msix_alloc = j + 1;
1710 kfree(used, M_DEVBUF);
1712 /* Map the IRQs onto the rids. */
1713 for (i = 0; i < count; i++) {
1714 if (vectors[i] == 0)
1716 irq = msix->msix_vectors[vectors[i]].mv_irq;
1717 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1722 device_printf(child, "Remapped MSI-X IRQs as: ");
1723 for (i = 0; i < count; i++) {
1726 if (vectors[i] == 0)
1730 msix->msix_vectors[vectors[i]].mv_irq);
1739 pci_release_msix(device_t dev, device_t child)
1741 struct pci_devinfo *dinfo = device_get_ivars(child);
1742 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1743 struct resource_list_entry *rle;
1746 /* Do we have any messages to release? */
1747 if (msix->msix_alloc == 0)
1750 /* Make sure none of the resources are allocated. */
1751 for (i = 0; i < msix->msix_table_len; i++) {
1752 if (msix->msix_table[i].mte_vector == 0)
1754 if (msix->msix_table[i].mte_handlers > 0)
1756 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1757 KASSERT(rle != NULL, ("missing resource"));
1758 if (rle->res != NULL)
1762 /* Update control register to disable MSI-X. */
1763 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1764 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
1765 msix->msix_ctrl, 2);
1767 /* Free the resource list entries. */
1768 for (i = 0; i < msix->msix_table_len; i++) {
1769 if (msix->msix_table[i].mte_vector == 0)
1771 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1773 kfree(msix->msix_table, M_DEVBUF);
1774 msix->msix_table_len = 0;
1776 /* Release the IRQs. */
1777 for (i = 0; i < msix->msix_alloc; i++)
1778 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1779 msix->msix_vectors[i].mv_irq);
1780 kfree(msix->msix_vectors, M_DEVBUF);
1781 msix->msix_alloc = 0;
1786 * Return the max supported MSI-X messages this device supports.
1787 * Basically, assuming the MD code can alloc messages, this function
1788 * should return the maximum value that pci_alloc_msix() can return.
1789 * Thus, it is subject to the tunables, etc.
1792 pci_msix_count_method(device_t dev, device_t child)
1794 struct pci_devinfo *dinfo = device_get_ivars(child);
1795 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1797 if (pci_do_msix && msix->msix_location != 0)
1798 return (msix->msix_msgnum);
1803 * HyperTransport MSI mapping control
1806 pci_ht_map_msi(device_t dev, uint64_t addr)
1808 struct pci_devinfo *dinfo = device_get_ivars(dev);
1809 struct pcicfg_ht *ht = &dinfo->cfg.ht;
1814 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
1815 ht->ht_msiaddr >> 20 == addr >> 20) {
1816 /* Enable MSI -> HT mapping. */
1817 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1818 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1822 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) {
1823 /* Disable MSI -> HT mapping. */
1824 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
1825 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1831 * Support for MSI message signalled interrupts.
1834 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
1836 struct pci_devinfo *dinfo = device_get_ivars(dev);
1837 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1839 /* Write data and address values. */
1840 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1841 address & 0xffffffff, 4);
1842 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1843 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
1845 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
1848 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
1851 /* Enable MSI in the control register. */
1852 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
1853 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1856 /* Enable MSI -> HT mapping. */
1857 pci_ht_map_msi(dev, address);
1861 pci_disable_msi(device_t dev)
1863 struct pci_devinfo *dinfo = device_get_ivars(dev);
1864 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1866 /* Disable MSI -> HT mapping. */
1867 pci_ht_map_msi(dev, 0);
1869 /* Disable MSI in the control register. */
1870 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
1871 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1876 * Restore MSI registers during resume. If MSI is enabled then
1877 * restore the data and address registers in addition to the control
1881 pci_resume_msi(device_t dev)
1883 struct pci_devinfo *dinfo = device_get_ivars(dev);
1884 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1888 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
1889 address = msi->msi_addr;
1890 data = msi->msi_data;
1891 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1892 address & 0xffffffff, 4);
1893 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1894 pci_write_config(dev, msi->msi_location +
1895 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
1896 pci_write_config(dev, msi->msi_location +
1897 PCIR_MSI_DATA_64BIT, data, 2);
1899 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
1902 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1907 pci_remap_msi_irq(device_t dev, u_int irq)
1909 struct pci_devinfo *dinfo = device_get_ivars(dev);
1910 pcicfgregs *cfg = &dinfo->cfg;
1911 struct resource_list_entry *rle;
1912 struct msix_table_entry *mte;
1913 struct msix_vector *mv;
1919 bus = device_get_parent(dev);
1922 * Handle MSI first. We try to find this IRQ among our list
1923 * of MSI IRQs. If we find it, we request updated address and
1924 * data registers and apply the results.
1926 if (cfg->msi.msi_alloc > 0) {
1928 /* If we don't have any active handlers, nothing to do. */
1929 if (cfg->msi.msi_handlers == 0)
1931 for (i = 0; i < cfg->msi.msi_alloc; i++) {
1932 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
1934 if (rle->start == irq) {
1935 error = PCIB_MAP_MSI(device_get_parent(bus),
1936 dev, irq, &addr, &data);
1939 pci_disable_msi(dev);
1940 dinfo->cfg.msi.msi_addr = addr;
1941 dinfo->cfg.msi.msi_data = data;
1942 pci_enable_msi(dev, addr, data);
1950 * For MSI-X, we check to see if we have this IRQ. If we do,
1951 * we request the updated mapping info. If that works, we go
1952 * through all the slots that use this IRQ and update them.
1954 if (cfg->msix.msix_alloc > 0) {
1955 for (i = 0; i < cfg->msix.msix_alloc; i++) {
1956 mv = &cfg->msix.msix_vectors[i];
1957 if (mv->mv_irq == irq) {
1958 error = PCIB_MAP_MSI(device_get_parent(bus),
1959 dev, irq, &addr, &data);
1962 mv->mv_address = addr;
1964 for (j = 0; j < cfg->msix.msix_table_len; j++) {
1965 mte = &cfg->msix.msix_table[j];
1966 if (mte->mte_vector != i + 1)
1968 if (mte->mte_handlers == 0)
1970 pci_mask_msix(dev, j);
1971 pci_enable_msix(dev, j, addr, data);
1972 pci_unmask_msix(dev, j);
1983 * Returns true if the specified device is blacklisted because MSI
1987 pci_msi_device_blacklisted(device_t dev)
1989 struct pci_quirk *q;
1991 if (!pci_honor_msi_blacklist)
1994 for (q = &pci_quirks[0]; q->devid; q++) {
1995 if (q->devid == pci_get_devid(dev) &&
1996 q->type == PCI_QUIRK_DISABLE_MSI)
2003 * Determine if MSI is blacklisted globally on this sytem. Currently,
2004 * we just check for blacklisted chipsets as represented by the
2005 * host-PCI bridge at device 0:0:0. In the future, it may become
2006 * necessary to check other system attributes, such as the kenv values
2007 * that give the motherboard manufacturer and model number.
2010 pci_msi_blacklisted(void)
2014 if (!pci_honor_msi_blacklist)
2017 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
2018 if (!(pcie_chipset || pcix_chipset))
2021 dev = pci_find_bsf(0, 0, 0);
2023 return (pci_msi_device_blacklisted(dev));
2028 * Attempt to allocate *count MSI messages. The actual number allocated is
2029 * returned in *count. After this function returns, each message will be
2030 * available to the driver as SYS_RES_IRQ resources starting at a rid 1.
2033 pci_alloc_msi_method(device_t dev, device_t child, int *count)
2035 struct pci_devinfo *dinfo = device_get_ivars(child);
2036 pcicfgregs *cfg = &dinfo->cfg;
2037 struct resource_list_entry *rle;
2038 int actual, error, i, irqs[32];
2041 /* Don't let count == 0 get us into trouble. */
2045 /* If rid 0 is allocated, then fail. */
2046 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
2047 if (rle != NULL && rle->res != NULL)
2050 /* Already have allocated messages? */
2051 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
2054 /* If MSI is blacklisted for this system, fail. */
2055 if (pci_msi_blacklisted())
2058 /* MSI capability present? */
2059 if (cfg->msi.msi_location == 0 || !pci_do_msi)
2063 device_printf(child,
2064 "attempting to allocate %d MSI vectors (%d supported)\n",
2065 *count, cfg->msi.msi_msgnum);
2067 /* Don't ask for more than the device supports. */
2068 actual = min(*count, cfg->msi.msi_msgnum);
2070 /* Don't ask for more than 32 messages. */
2071 actual = min(actual, 32);
2073 /* MSI requires power of 2 number of messages. */
2074 if (!powerof2(actual))
2078 /* Try to allocate N messages. */
2079 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
2080 cfg->msi.msi_msgnum, irqs);
2091 * We now have N actual messages mapped onto SYS_RES_IRQ
2092 * resources in the irqs[] array, so add new resources
2093 * starting at rid 1.
2095 for (i = 0; i < actual; i++)
2096 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
2097 irqs[i], irqs[i], 1, -1);
2101 device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
2106 * Be fancy and try to print contiguous runs
2107 * of IRQ values as ranges. 'run' is true if
2108 * we are in a range.
2110 device_printf(child, "using IRQs %d", irqs[0]);
2112 for (i = 1; i < actual; i++) {
2114 /* Still in a run? */
2115 if (irqs[i] == irqs[i - 1] + 1) {
2120 /* Finish previous range. */
2122 kprintf("-%d", irqs[i - 1]);
2126 /* Start new range. */
2127 kprintf(",%d", irqs[i]);
2130 /* Unfinished range? */
2132 kprintf("-%d", irqs[actual - 1]);
2133 kprintf(" for MSI\n");
2137 /* Update control register with actual count. */
2138 ctrl = cfg->msi.msi_ctrl;
2139 ctrl &= ~PCIM_MSICTRL_MME_MASK;
2140 ctrl |= (ffs(actual) - 1) << 4;
2141 cfg->msi.msi_ctrl = ctrl;
2142 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
2144 /* Update counts of alloc'd messages. */
2145 cfg->msi.msi_alloc = actual;
2146 cfg->msi.msi_handlers = 0;
2151 /* Release the MSI messages associated with this device. */
2153 pci_release_msi_method(device_t dev, device_t child)
2155 struct pci_devinfo *dinfo = device_get_ivars(child);
2156 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2157 struct resource_list_entry *rle;
2158 int error, i, irqs[32];
2160 /* Try MSI-X first. */
2161 error = pci_release_msix(dev, child);
2162 if (error != ENODEV)
2165 /* Do we have any messages to release? */
2166 if (msi->msi_alloc == 0)
2168 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
2170 /* Make sure none of the resources are allocated. */
2171 if (msi->msi_handlers > 0)
2173 for (i = 0; i < msi->msi_alloc; i++) {
2174 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2175 KASSERT(rle != NULL, ("missing MSI resource"));
2176 if (rle->res != NULL)
2178 irqs[i] = rle->start;
2181 /* Update control register with 0 count. */
2182 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
2183 ("%s: MSI still enabled", __func__));
2184 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
2185 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2188 /* Release the messages. */
2189 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
2190 for (i = 0; i < msi->msi_alloc; i++)
2191 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2193 /* Update alloc count. */
2201 * Return the max supported MSI messages this device supports.
2202 * Basically, assuming the MD code can alloc messages, this function
2203 * should return the maximum value that pci_alloc_msi() can return.
2204 * Thus, it is subject to the tunables, etc.
2207 pci_msi_count_method(device_t dev, device_t child)
2209 struct pci_devinfo *dinfo = device_get_ivars(child);
2210 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2212 if (pci_do_msi && msi->msi_location != 0)
2213 return (msi->msi_msgnum);
2217 /* kfree pcicfgregs structure and all depending data structures */
2220 pci_freecfg(struct pci_devinfo *dinfo)
2222 struct devlist *devlist_head;
2225 devlist_head = &pci_devq;
2227 if (dinfo->cfg.vpd.vpd_reg) {
2228 kfree(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2229 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2230 kfree(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2231 kfree(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2232 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2233 kfree(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2234 kfree(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2236 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2237 kfree(dinfo, M_DEVBUF);
2239 /* increment the generation count */
2242 /* we're losing one device */
2248 * PCI power manangement
2251 pci_set_powerstate_method(device_t dev, device_t child, int state)
2253 struct pci_devinfo *dinfo = device_get_ivars(child);
2254 pcicfgregs *cfg = &dinfo->cfg;
2256 int result, oldstate, highest, delay;
2258 if (cfg->pp.pp_cap == 0)
2259 return (EOPNOTSUPP);
2262 * Optimize a no state change request away. While it would be OK to
2263 * write to the hardware in theory, some devices have shown odd
2264 * behavior when going from D3 -> D3.
2266 oldstate = pci_get_powerstate(child);
2267 if (oldstate == state)
2271 * The PCI power management specification states that after a state
2272 * transition between PCI power states, system software must
2273 * guarantee a minimal delay before the function accesses the device.
2274 * Compute the worst case delay that we need to guarantee before we
2275 * access the device. Many devices will be responsive much more
2276 * quickly than this delay, but there are some that don't respond
2277 * instantly to state changes. Transitions to/from D3 state require
2278 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2279 * is done below with DELAY rather than a sleeper function because
2280 * this function can be called from contexts where we cannot sleep.
2282 highest = (oldstate > state) ? oldstate : state;
2283 if (highest == PCI_POWERSTATE_D3)
2285 else if (highest == PCI_POWERSTATE_D2)
2289 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2290 & ~PCIM_PSTAT_DMASK;
2293 case PCI_POWERSTATE_D0:
2294 status |= PCIM_PSTAT_D0;
2296 case PCI_POWERSTATE_D1:
2297 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2298 return (EOPNOTSUPP);
2299 status |= PCIM_PSTAT_D1;
2301 case PCI_POWERSTATE_D2:
2302 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2303 return (EOPNOTSUPP);
2304 status |= PCIM_PSTAT_D2;
2306 case PCI_POWERSTATE_D3:
2307 status |= PCIM_PSTAT_D3;
2315 "pci%d:%d:%d:%d: Transition from D%d to D%d\n",
2316 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2317 dinfo->cfg.func, oldstate, state);
2319 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2326 pci_get_powerstate_method(device_t dev, device_t child)
2328 struct pci_devinfo *dinfo = device_get_ivars(child);
2329 pcicfgregs *cfg = &dinfo->cfg;
2333 if (cfg->pp.pp_cap != 0) {
2334 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2335 switch (status & PCIM_PSTAT_DMASK) {
2337 result = PCI_POWERSTATE_D0;
2340 result = PCI_POWERSTATE_D1;
2343 result = PCI_POWERSTATE_D2;
2346 result = PCI_POWERSTATE_D3;
2349 result = PCI_POWERSTATE_UNKNOWN;
2353 /* No support, device is always at D0 */
2354 result = PCI_POWERSTATE_D0;
2360 * Some convenience functions for PCI device drivers.
2363 static __inline void
2364 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2368 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2370 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2373 static __inline void
2374 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2378 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2380 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2384 pci_enable_busmaster_method(device_t dev, device_t child)
2386 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2391 pci_disable_busmaster_method(device_t dev, device_t child)
2393 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2398 pci_enable_io_method(device_t dev, device_t child, int space)
2408 case SYS_RES_IOPORT:
2409 bit = PCIM_CMD_PORTEN;
2412 case SYS_RES_MEMORY:
2413 bit = PCIM_CMD_MEMEN;
2419 pci_set_command_bit(dev, child, bit);
2420 /* Some devices seem to need a brief stall here, what do to? */
2421 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2424 device_printf(child, "failed to enable %s mapping!\n", error);
2429 pci_disable_io_method(device_t dev, device_t child, int space)
2439 case SYS_RES_IOPORT:
2440 bit = PCIM_CMD_PORTEN;
2443 case SYS_RES_MEMORY:
2444 bit = PCIM_CMD_MEMEN;
2450 pci_clear_command_bit(dev, child, bit);
2451 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2452 if (command & bit) {
2453 device_printf(child, "failed to disable %s mapping!\n", error);
2460 * New style pci driver. Parent device is either a pci-host-bridge or a
2461 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2465 pci_print_verbose(struct pci_devinfo *dinfo)
2469 pcicfgregs *cfg = &dinfo->cfg;
2471 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2472 cfg->vendor, cfg->device, cfg->revid);
2473 kprintf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2474 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2475 kprintf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2476 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2478 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2479 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2480 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
2481 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2482 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
2483 if (cfg->intpin > 0)
2484 kprintf("\tintpin=%c, irq=%d\n",
2485 cfg->intpin +'a' -1, cfg->intline);
2486 if (cfg->pp.pp_cap) {
2489 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2490 kprintf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2491 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2492 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2493 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2494 status & PCIM_PSTAT_DMASK);
2496 if (cfg->msi.msi_location) {
2499 ctrl = cfg->msi.msi_ctrl;
2500 kprintf("\tMSI supports %d message%s%s%s\n",
2501 cfg->msi.msi_msgnum,
2502 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2503 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2504 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2506 if (cfg->msix.msix_location) {
2507 kprintf("\tMSI-X supports %d message%s ",
2508 cfg->msix.msix_msgnum,
2509 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2510 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2511 kprintf("in map 0x%x\n",
2512 cfg->msix.msix_table_bar);
2514 kprintf("in maps 0x%x and 0x%x\n",
2515 cfg->msix.msix_table_bar,
2516 cfg->msix.msix_pba_bar);
2518 pci_print_verbose_expr(cfg);
2523 pci_print_verbose_expr(const pcicfgregs *cfg)
2525 const struct pcicfg_expr *expr = &cfg->expr;
2526 const char *port_name;
2532 if (expr->expr_ptr == 0) /* No PCI Express capability */
2535 kprintf("\tPCI Express ver.%d cap=0x%04x",
2536 expr->expr_cap & PCIEM_CAP_VER_MASK, expr->expr_cap);
2537 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
2540 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
2542 switch (port_type) {
2543 case PCIE_END_POINT:
2544 port_name = "DEVICE";
2546 case PCIE_LEG_END_POINT:
2547 port_name = "LEGDEV";
2549 case PCIE_ROOT_PORT:
2552 case PCIE_UP_STREAM_PORT:
2553 port_name = "UPSTREAM";
2555 case PCIE_DOWN_STREAM_PORT:
2556 port_name = "DOWNSTRM";
2558 case PCIE_PCIE2PCI_BRIDGE:
2559 port_name = "PCIE2PCI";
2561 case PCIE_PCI2PCIE_BRIDGE:
2562 port_name = "PCI2PCIE";
2568 if ((port_type == PCIE_ROOT_PORT ||
2569 port_type == PCIE_DOWN_STREAM_PORT) &&
2570 !(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
2572 if (port_name != NULL)
2573 kprintf("[%s]", port_name);
2575 if (pcie_slotimpl(cfg)) {
2576 kprintf(", slotcap=0x%08x", expr->expr_slotcap);
2577 if (expr->expr_slotcap & PCIEM_SLTCAP_HP_CAP)
2578 kprintf("[HOTPLUG]");
2585 pci_porten(device_t pcib, int b, int s, int f)
2587 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2588 & PCIM_CMD_PORTEN) != 0;
2592 pci_memen(device_t pcib, int b, int s, int f)
2594 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2595 & PCIM_CMD_MEMEN) != 0;
2599 * Add a resource based on a pci map register. Return 1 if the map
2600 * register is a 32bit map register or 2 if it is a 64bit register.
2603 pci_add_map(device_t pcib, device_t bus, device_t dev,
2604 int b, int s, int f, int reg, struct resource_list *rl, int force,
2609 pci_addr_t start, end, count;
2616 struct resource *res;
2618 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2619 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
2620 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2621 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
2623 if (PCI_BAR_MEM(map)) {
2624 type = SYS_RES_MEMORY;
2625 if (map & PCIM_BAR_MEM_PREFETCH)
2628 type = SYS_RES_IOPORT;
2629 ln2size = pci_mapsize(testval);
2630 ln2range = pci_maprange(testval);
2631 base = pci_mapbase(map);
2632 barlen = ln2range == 64 ? 2 : 1;
2635 * For I/O registers, if bottom bit is set, and the next bit up
2636 * isn't clear, we know we have a BAR that doesn't conform to the
2637 * spec, so ignore it. Also, sanity check the size of the data
2638 * areas to the type of memory involved. Memory must be at least
2639 * 16 bytes in size, while I/O ranges must be at least 4.
2641 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2643 if ((type == SYS_RES_MEMORY && ln2size < 4) ||
2644 (type == SYS_RES_IOPORT && ln2size < 2))
2648 /* Read the other half of a 64bit map register */
2649 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
2651 kprintf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2652 reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size);
2653 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2654 kprintf(", port disabled\n");
2655 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2656 kprintf(", memory disabled\n");
2658 kprintf(", enabled\n");
2662 * If base is 0, then we have problems. It is best to ignore
2663 * such entries for the moment. These will be allocated later if
2664 * the driver specifically requests them. However, some
2665 * removable busses look better when all resources are allocated,
2666 * so allow '0' to be overriden.
2668 * Similarly treat maps whose values is the same as the test value
2669 * read back. These maps have had all f's written to them by the
2670 * BIOS in an attempt to disable the resources.
2672 if (!force && (base == 0 || map == testval))
2674 if ((u_long)base != base) {
2676 "pci%d:%d:%d:%d bar %#x too many address bits",
2677 pci_get_domain(dev), b, s, f, reg);
2682 * This code theoretically does the right thing, but has
2683 * undesirable side effects in some cases where peripherals
2684 * respond oddly to having these bits enabled. Let the user
2685 * be able to turn them off (since pci_enable_io_modes is 1 by
2688 if (pci_enable_io_modes) {
2689 /* Turn on resources that have been left off by a lazy BIOS */
2690 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
2691 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2692 cmd |= PCIM_CMD_PORTEN;
2693 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2695 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
2696 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2697 cmd |= PCIM_CMD_MEMEN;
2698 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2701 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2703 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2707 count = 1 << ln2size;
2708 if (base == 0 || base == pci_mapbase(testval)) {
2709 start = 0; /* Let the parent decide. */
2713 end = base + (1 << ln2size) - 1;
2715 resource_list_add(rl, type, reg, start, end, count, -1);
2718 * Try to allocate the resource for this BAR from our parent
2719 * so that this resource range is already reserved. The
2720 * driver for this device will later inherit this resource in
2721 * pci_alloc_resource().
2723 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count,
2724 prefetch ? RF_PREFETCHABLE : 0);
2727 * If the allocation fails, delete the resource list
2728 * entry to force pci_alloc_resource() to allocate
2729 * resources from the parent.
2731 resource_list_delete(rl, type, reg);
2732 #ifdef PCI_BAR_CLEAR
2735 #else /* !PCI_BAR_CLEAR */
2737 * Don't clear BAR here. Some BIOS lists HPET as a
2738 * PCI function, clearing the BAR causes HPET timer
2742 kprintf("pci:%d:%d:%d: resource reservation failed "
2743 "%#jx - %#jx\n", b, s, f,
2744 (intmax_t)start, (intmax_t)end);
2747 #endif /* PCI_BAR_CLEAR */
2749 start = rman_get_start(res);
2751 pci_write_config(dev, reg, start, 4);
2753 pci_write_config(dev, reg + 4, start >> 32, 4);
2758 * For ATA devices we need to decide early what addressing mode to use.
2759 * Legacy demands that the primary and secondary ATA ports sits on the
2760 * same addresses that old ISA hardware did. This dictates that we use
2761 * those addresses and ignore the BAR's if we cannot set PCI native
2765 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b,
2766 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask)
2768 int rid, type, progif;
2770 /* if this device supports PCI native addressing use it */
2771 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2772 if ((progif & 0x8a) == 0x8a) {
2773 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2774 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
2775 kprintf("Trying ATA native PCI addressing mode\n");
2776 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2780 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2781 type = SYS_RES_IOPORT;
2782 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
2783 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force,
2784 prefetchmask & (1 << 0));
2785 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force,
2786 prefetchmask & (1 << 1));
2789 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8, -1);
2790 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
2793 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1, -1);
2794 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
2797 if (progif & PCIP_STORAGE_IDE_MODESEC) {
2798 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force,
2799 prefetchmask & (1 << 2));
2800 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force,
2801 prefetchmask & (1 << 3));
2804 resource_list_add(rl, type, rid, 0x170, 0x177, 8, -1);
2805 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
2808 resource_list_add(rl, type, rid, 0x376, 0x376, 1, -1);
2809 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
2812 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force,
2813 prefetchmask & (1 << 4));
2814 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force,
2815 prefetchmask & (1 << 5));
2819 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
2821 struct pci_devinfo *dinfo = device_get_ivars(dev);
2822 pcicfgregs *cfg = &dinfo->cfg;
2823 char tunable_name[64];
2826 /* Has to have an intpin to have an interrupt. */
2827 if (cfg->intpin == 0)
2830 /* Let the user override the IRQ with a tunable. */
2831 irq = PCI_INVALID_IRQ;
2832 ksnprintf(tunable_name, sizeof(tunable_name),
2833 "hw.pci%d.%d.%d.INT%c.irq",
2834 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
2835 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
2836 irq = PCI_INVALID_IRQ;
2839 * If we didn't get an IRQ via the tunable, then we either use the
2840 * IRQ value in the intline register or we ask the bus to route an
2841 * interrupt for us. If force_route is true, then we only use the
2842 * value in the intline register if the bus was unable to assign an
2845 if (!PCI_INTERRUPT_VALID(irq)) {
2846 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
2847 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
2848 if (!PCI_INTERRUPT_VALID(irq))
2852 /* If after all that we don't have an IRQ, just bail. */
2853 if (!PCI_INTERRUPT_VALID(irq))
2856 /* Update the config register if it changed. */
2857 if (irq != cfg->intline) {
2859 pci_write_config(dev, PCIR_INTLINE, irq, 1);
2862 /* Add this IRQ as rid 0 interrupt resource. */
2863 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1, -1);
2867 pci_add_resources(device_t pcib, device_t bus, device_t dev, int force, uint32_t prefetchmask)
2869 struct pci_devinfo *dinfo = device_get_ivars(dev);
2870 pcicfgregs *cfg = &dinfo->cfg;
2871 struct resource_list *rl = &dinfo->resources;
2872 struct pci_quirk *q;
2879 /* ATA devices needs special map treatment */
2880 if ((pci_get_class(dev) == PCIC_STORAGE) &&
2881 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
2882 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
2883 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
2884 !pci_read_config(dev, PCIR_BAR(2), 4))) )
2885 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask);
2887 for (i = 0; i < cfg->nummaps;)
2888 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i),
2889 rl, force, prefetchmask & (1 << i));
2892 * Add additional, quirked resources.
2894 for (q = &pci_quirks[0]; q->devid; q++) {
2895 if (q->devid == ((cfg->device << 16) | cfg->vendor)
2896 && q->type == PCI_QUIRK_MAP_REG)
2897 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl,
2901 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2903 * Try to re-route interrupts. Sometimes the BIOS or
2904 * firmware may leave bogus values in these registers.
2905 * If the re-route fails, then just stick with what we
2908 pci_assign_interrupt(bus, dev, 1);
2913 pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
2915 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
2916 device_t pcib = device_get_parent(dev);
2917 struct pci_devinfo *dinfo;
2919 int s, f, pcifunchigh;
2922 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
2923 ("dinfo_size too small"));
2924 maxslots = PCIB_MAXSLOTS(pcib);
2925 for (s = 0; s <= maxslots; s++) {
2929 hdrtype = REG(PCIR_HDRTYPE, 1);
2930 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
2932 if (hdrtype & PCIM_MFDEV)
2933 pcifunchigh = PCI_FUNCMAX;
2934 for (f = 0; f <= pcifunchigh; f++) {
2935 dinfo = pci_read_device(pcib, domain, busno, s, f,
2937 if (dinfo != NULL) {
2938 pci_add_child(dev, dinfo);
2946 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
2950 pcib = device_get_parent(bus);
2951 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
2952 device_set_ivars(dinfo->cfg.dev, dinfo);
2953 resource_list_init(&dinfo->resources);
2954 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
2955 pci_cfg_restore(dinfo->cfg.dev, dinfo);
2956 pci_print_verbose(dinfo);
2957 pci_add_resources(pcib, bus, dinfo->cfg.dev, 0, 0);
2961 pci_probe(device_t dev)
2963 device_set_desc(dev, "PCI bus");
2965 /* Allow other subclasses to override this driver. */
2970 pci_attach(device_t dev)
2975 * Since there can be multiple independantly numbered PCI
2976 * busses on systems with multiple PCI domains, we can't use
2977 * the unit number to decide which bus we are probing. We ask
2978 * the parent pcib what our domain and bus numbers are.
2980 domain = pcib_get_domain(dev);
2981 busno = pcib_get_bus(dev);
2983 device_printf(dev, "domain=%d, physical bus=%d\n",
2986 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
2988 return (bus_generic_attach(dev));
2992 pci_suspend(device_t dev)
2994 int dstate, error, i, numdevs;
2995 device_t acpi_dev, child, *devlist;
2996 struct pci_devinfo *dinfo;
2999 * Save the PCI configuration space for each child and set the
3000 * device in the appropriate power state for this sleep state.
3003 if (pci_do_power_resume)
3004 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
3005 device_get_children(dev, &devlist, &numdevs);
3006 for (i = 0; i < numdevs; i++) {
3008 dinfo = (struct pci_devinfo *) device_get_ivars(child);
3009 pci_cfg_save(child, dinfo, 0);
3012 /* Suspend devices before potentially powering them down. */
3013 error = bus_generic_suspend(dev);
3015 kfree(devlist, M_TEMP);
3020 * Always set the device to D3. If ACPI suggests a different
3021 * power state, use it instead. If ACPI is not present, the
3022 * firmware is responsible for managing device power. Skip
3023 * children who aren't attached since they are powered down
3024 * separately. Only manage type 0 devices for now.
3026 for (i = 0; acpi_dev && i < numdevs; i++) {
3028 dinfo = (struct pci_devinfo *) device_get_ivars(child);
3029 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) {
3030 dstate = PCI_POWERSTATE_D3;
3031 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate);
3032 pci_set_powerstate(child, dstate);
3035 kfree(devlist, M_TEMP);
3040 pci_resume(device_t dev)
3043 device_t acpi_dev, child, *devlist;
3044 struct pci_devinfo *dinfo;
3047 * Set each child to D0 and restore its PCI configuration space.
3050 if (pci_do_power_resume)
3051 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
3052 device_get_children(dev, &devlist, &numdevs);
3053 for (i = 0; i < numdevs; i++) {
3055 * Notify ACPI we're going to D0 but ignore the result. If
3056 * ACPI is not present, the firmware is responsible for
3057 * managing device power. Only manage type 0 devices for now.
3060 dinfo = (struct pci_devinfo *) device_get_ivars(child);
3061 if (acpi_dev && device_is_attached(child) &&
3062 dinfo->cfg.hdrtype == 0) {
3063 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL);
3064 pci_set_powerstate(child, PCI_POWERSTATE_D0);
3067 /* Now the device is powered up, restore its config space. */
3068 pci_cfg_restore(child, dinfo);
3070 kfree(devlist, M_TEMP);
3071 return (bus_generic_resume(dev));
3075 pci_load_vendor_data(void)
3077 caddr_t vendordata, info;
3079 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
3080 info = preload_search_info(vendordata, MODINFO_ADDR);
3081 pci_vendordata = *(char **)info;
3082 info = preload_search_info(vendordata, MODINFO_SIZE);
3083 pci_vendordata_size = *(size_t *)info;
3084 /* terminate the database */
3085 pci_vendordata[pci_vendordata_size] = '\n';
3090 pci_driver_added(device_t dev, driver_t *driver)
3095 struct pci_devinfo *dinfo;
3099 device_printf(dev, "driver added\n");
3100 DEVICE_IDENTIFY(driver, dev);
3101 device_get_children(dev, &devlist, &numdevs);
3102 for (i = 0; i < numdevs; i++) {
3104 if (device_get_state(child) != DS_NOTPRESENT)
3106 dinfo = device_get_ivars(child);
3107 pci_print_verbose(dinfo);
3109 kprintf("pci%d:%d:%d:%d: reprobing on driver added\n",
3110 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
3112 pci_cfg_restore(child, dinfo);
3113 if (device_probe_and_attach(child) != 0)
3114 pci_cfg_save(child, dinfo, 1);
3116 kfree(devlist, M_TEMP);
3120 pci_child_detached(device_t parent __unused, device_t child)
3122 /* Turn child's power off */
3123 pci_cfg_save(child, device_get_ivars(child), 1);
3127 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
3128 driver_intr_t *intr, void *arg, void **cookiep, lwkt_serialize_t serializer)
3131 struct pci_devinfo *dinfo;
3132 struct msix_table_entry *mte;
3133 struct msix_vector *mv;
3140 error = bus_generic_setup_intr(dev, child, irq, flags, intr,
3141 arg, &cookie, serializer);
3145 /* If this is not a direct child, just bail out. */
3146 if (device_get_parent(child) != dev) {
3151 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3153 rid = rman_get_rid(irq);
3155 /* Make sure that INTx is enabled */
3156 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3159 * Check to see if the interrupt is MSI or MSI-X.
3160 * Ask our parent to map the MSI and give
3161 * us the address and data register values.
3162 * If we fail for some reason, teardown the
3163 * interrupt handler.
3165 dinfo = device_get_ivars(child);
3166 if (dinfo->cfg.msi.msi_alloc > 0) {
3167 if (dinfo->cfg.msi.msi_addr == 0) {
3168 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
3169 ("MSI has handlers, but vectors not mapped"));
3170 error = PCIB_MAP_MSI(device_get_parent(dev),
3171 child, rman_get_start(irq), &addr, &data);
3174 dinfo->cfg.msi.msi_addr = addr;
3175 dinfo->cfg.msi.msi_data = data;
3176 pci_enable_msi(child, addr, data);
3178 dinfo->cfg.msi.msi_handlers++;
3180 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3181 ("No MSI or MSI-X interrupts allocated"));
3182 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3183 ("MSI-X index too high"));
3184 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3185 KASSERT(mte->mte_vector != 0, ("no message vector"));
3186 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
3187 KASSERT(mv->mv_irq == rman_get_start(irq),
3189 if (mv->mv_address == 0) {
3190 KASSERT(mte->mte_handlers == 0,
3191 ("MSI-X table entry has handlers, but vector not mapped"));
3192 error = PCIB_MAP_MSI(device_get_parent(dev),
3193 child, rman_get_start(irq), &addr, &data);
3196 mv->mv_address = addr;
3199 if (mte->mte_handlers == 0) {
3200 pci_enable_msix(child, rid - 1, mv->mv_address,
3202 pci_unmask_msix(child, rid - 1);
3204 mte->mte_handlers++;
3207 /* Make sure that INTx is disabled if we are using MSI/MSIX */
3208 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3211 (void)bus_generic_teardown_intr(dev, child, irq,
3222 pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
3226 struct msix_table_entry *mte;
3227 struct resource_list_entry *rle;
3228 struct pci_devinfo *dinfo;
3233 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
3236 /* If this isn't a direct child, just bail out */
3237 if (device_get_parent(child) != dev)
3238 return(bus_generic_teardown_intr(dev, child, irq, cookie));
3240 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3242 rid = rman_get_rid(irq);
3245 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3248 * Check to see if the interrupt is MSI or MSI-X. If so,
3249 * decrement the appropriate handlers count and mask the
3250 * MSI-X message, or disable MSI messages if the count
3253 dinfo = device_get_ivars(child);
3254 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
3255 if (rle->res != irq)
3257 if (dinfo->cfg.msi.msi_alloc > 0) {
3258 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
3259 ("MSI-X index too high"));
3260 if (dinfo->cfg.msi.msi_handlers == 0)
3262 dinfo->cfg.msi.msi_handlers--;
3263 if (dinfo->cfg.msi.msi_handlers == 0)
3264 pci_disable_msi(child);
3266 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3267 ("No MSI or MSI-X interrupts allocated"));
3268 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3269 ("MSI-X index too high"));
3270 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3271 if (mte->mte_handlers == 0)
3273 mte->mte_handlers--;
3274 if (mte->mte_handlers == 0)
3275 pci_mask_msix(child, rid - 1);
3278 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3281 ("%s: generic teardown failed for MSI/MSI-X", __func__));
3283 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3288 pci_print_child(device_t dev, device_t child)
3290 struct pci_devinfo *dinfo;
3291 struct resource_list *rl;
3294 dinfo = device_get_ivars(child);
3295 rl = &dinfo->resources;
3297 retval += bus_print_child_header(dev, child);
3299 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
3300 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
3301 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
3302 if (device_get_flags(dev))
3303 retval += kprintf(" flags %#x", device_get_flags(dev));
3305 retval += kprintf(" at device %d.%d", pci_get_slot(child),
3306 pci_get_function(child));
3308 retval += bus_print_child_footer(dev, child);
3318 } pci_nomatch_tab[] = {
3319 {PCIC_OLD, -1, "old"},
3320 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
3321 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
3322 {PCIC_STORAGE, -1, "mass storage"},
3323 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
3324 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
3325 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
3326 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
3327 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
3328 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"},
3329 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"},
3330 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"},
3331 {PCIC_NETWORK, -1, "network"},
3332 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
3333 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
3334 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
3335 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
3336 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
3337 {PCIC_DISPLAY, -1, "display"},
3338 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
3339 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
3340 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
3341 {PCIC_MULTIMEDIA, -1, "multimedia"},
3342 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
3343 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
3344 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
3345 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"},
3346 {PCIC_MEMORY, -1, "memory"},
3347 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
3348 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
3349 {PCIC_BRIDGE, -1, "bridge"},
3350 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
3351 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
3352 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
3353 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
3354 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
3355 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
3356 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
3357 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
3358 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
3359 {PCIC_SIMPLECOMM, -1, "simple comms"},
3360 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
3361 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
3362 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
3363 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
3364 {PCIC_BASEPERIPH, -1, "base peripheral"},
3365 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
3366 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
3367 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
3368 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
3369 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
3370 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"},
3371 {PCIC_INPUTDEV, -1, "input device"},
3372 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
3373 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
3374 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
3375 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
3376 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
3377 {PCIC_DOCKING, -1, "docking station"},
3378 {PCIC_PROCESSOR, -1, "processor"},
3379 {PCIC_SERIALBUS, -1, "serial bus"},
3380 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
3381 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
3382 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
3383 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
3384 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
3385 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
3386 {PCIC_WIRELESS, -1, "wireless controller"},
3387 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
3388 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
3389 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
3390 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
3391 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
3392 {PCIC_SATCOM, -1, "satellite communication"},
3393 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
3394 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
3395 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
3396 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
3397 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
3398 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
3399 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
3400 {PCIC_DASP, -1, "dasp"},
3401 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
3406 pci_probe_nomatch(device_t dev, device_t child)
3409 char *cp, *scp, *device;
3412 * Look for a listing for this device in a loaded device database.
3414 if ((device = pci_describe_device(child)) != NULL) {
3415 device_printf(dev, "<%s>", device);
3416 kfree(device, M_DEVBUF);
3419 * Scan the class/subclass descriptions for a general
3424 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
3425 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
3426 if (pci_nomatch_tab[i].subclass == -1) {
3427 cp = pci_nomatch_tab[i].desc;
3428 } else if (pci_nomatch_tab[i].subclass ==
3429 pci_get_subclass(child)) {
3430 scp = pci_nomatch_tab[i].desc;
3434 device_printf(dev, "<%s%s%s>",
3436 ((cp != NULL) && (scp != NULL)) ? ", " : "",
3439 kprintf(" (vendor 0x%04x, dev 0x%04x) at device %d.%d",
3440 pci_get_vendor(child), pci_get_device(child),
3441 pci_get_slot(child), pci_get_function(child));
3442 if (pci_get_intpin(child) > 0) {
3445 irq = pci_get_irq(child);
3446 if (PCI_INTERRUPT_VALID(irq))
3447 kprintf(" irq %d", irq);
3451 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1);
3455 * Parse the PCI device database, if loaded, and return a pointer to a
3456 * description of the device.
3458 * The database is flat text formatted as follows:
3460 * Any line not in a valid format is ignored.
3461 * Lines are terminated with newline '\n' characters.
3463 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
3466 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
3467 * - devices cannot be listed without a corresponding VENDOR line.
3468 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
3469 * another TAB, then the device name.
3473 * Assuming (ptr) points to the beginning of a line in the database,
3474 * return the vendor or device and description of the next entry.
3475 * The value of (vendor) or (device) inappropriate for the entry type
3476 * is set to -1. Returns nonzero at the end of the database.
3478 * Note that this is slightly unrobust in the face of corrupt data;
3479 * we attempt to safeguard against this by spamming the end of the
3480 * database with a newline when we initialise.
3483 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
3492 left = pci_vendordata_size - (cp - pci_vendordata);
3500 ksscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
3504 ksscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
3507 /* skip to next line */
3508 while (*cp != '\n' && left > 0) {
3517 /* skip to next line */
3518 while (*cp != '\n' && left > 0) {
3522 if (*cp == '\n' && left > 0)
3529 pci_describe_device(device_t dev)
3532 char *desc, *vp, *dp, *line;
3534 desc = vp = dp = NULL;
3537 * If we have no vendor data, we can't do anything.
3539 if (pci_vendordata == NULL)
3543 * Scan the vendor data looking for this device
3545 line = pci_vendordata;
3546 if ((vp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3549 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
3551 if (vendor == pci_get_vendor(dev))
3554 if ((dp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3557 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
3565 if (device == pci_get_device(dev))
3569 ksnprintf(dp, 80, "0x%x", pci_get_device(dev));
3570 if ((desc = kmalloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
3572 ksprintf(desc, "%s, %s", vp, dp);
3575 kfree(vp, M_DEVBUF);
3577 kfree(dp, M_DEVBUF);
3582 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
3584 struct pci_devinfo *dinfo;
3587 dinfo = device_get_ivars(child);
3591 case PCI_IVAR_ETHADDR:
3593 * The generic accessor doesn't deal with failure, so
3594 * we set the return value, then return an error.
3596 *((uint8_t **) result) = NULL;
3598 case PCI_IVAR_SUBVENDOR:
3599 *result = cfg->subvendor;
3601 case PCI_IVAR_SUBDEVICE:
3602 *result = cfg->subdevice;
3604 case PCI_IVAR_VENDOR:
3605 *result = cfg->vendor;
3607 case PCI_IVAR_DEVICE:
3608 *result = cfg->device;
3610 case PCI_IVAR_DEVID:
3611 *result = (cfg->device << 16) | cfg->vendor;
3613 case PCI_IVAR_CLASS:
3614 *result = cfg->baseclass;
3616 case PCI_IVAR_SUBCLASS:
3617 *result = cfg->subclass;
3619 case PCI_IVAR_PROGIF:
3620 *result = cfg->progif;
3622 case PCI_IVAR_REVID:
3623 *result = cfg->revid;
3625 case PCI_IVAR_INTPIN:
3626 *result = cfg->intpin;
3629 *result = cfg->intline;
3631 case PCI_IVAR_DOMAIN:
3632 *result = cfg->domain;
3638 *result = cfg->slot;
3640 case PCI_IVAR_FUNCTION:
3641 *result = cfg->func;
3643 case PCI_IVAR_CMDREG:
3644 *result = cfg->cmdreg;
3646 case PCI_IVAR_CACHELNSZ:
3647 *result = cfg->cachelnsz;
3649 case PCI_IVAR_MINGNT:
3650 *result = cfg->mingnt;
3652 case PCI_IVAR_MAXLAT:
3653 *result = cfg->maxlat;
3655 case PCI_IVAR_LATTIMER:
3656 *result = cfg->lattimer;
3658 case PCI_IVAR_PCIXCAP_PTR:
3659 *result = cfg->pcix.pcix_ptr;
3661 case PCI_IVAR_PCIECAP_PTR:
3662 *result = cfg->expr.expr_ptr;
3664 case PCI_IVAR_VPDCAP_PTR:
3665 *result = cfg->vpd.vpd_reg;
3674 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
3676 struct pci_devinfo *dinfo;
3678 dinfo = device_get_ivars(child);
3681 case PCI_IVAR_INTPIN:
3682 dinfo->cfg.intpin = value;
3684 case PCI_IVAR_ETHADDR:
3685 case PCI_IVAR_SUBVENDOR:
3686 case PCI_IVAR_SUBDEVICE:
3687 case PCI_IVAR_VENDOR:
3688 case PCI_IVAR_DEVICE:
3689 case PCI_IVAR_DEVID:
3690 case PCI_IVAR_CLASS:
3691 case PCI_IVAR_SUBCLASS:
3692 case PCI_IVAR_PROGIF:
3693 case PCI_IVAR_REVID:
3695 case PCI_IVAR_DOMAIN:
3698 case PCI_IVAR_FUNCTION:
3699 return (EINVAL); /* disallow for now */
3706 #include "opt_ddb.h"
3708 #include <ddb/ddb.h>
3709 #include <sys/cons.h>
3712 * List resources based on pci map registers, used for within ddb
3715 DB_SHOW_COMMAND(pciregs, db_pci_dump)
3717 struct pci_devinfo *dinfo;
3718 struct devlist *devlist_head;
3721 int i, error, none_count;
3724 /* get the head of the device queue */
3725 devlist_head = &pci_devq;
3728 * Go through the list of devices and print out devices
3730 for (error = 0, i = 0,
3731 dinfo = STAILQ_FIRST(devlist_head);
3732 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
3733 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
3735 /* Populate pd_name and pd_unit */
3738 name = device_get_name(dinfo->cfg.dev);
3741 db_kprintf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
3742 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
3743 (name && *name) ? name : "none",
3744 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
3746 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
3747 p->pc_sel.pc_func, (p->pc_class << 16) |
3748 (p->pc_subclass << 8) | p->pc_progif,
3749 (p->pc_subdevice << 16) | p->pc_subvendor,
3750 (p->pc_device << 16) | p->pc_vendor,
3751 p->pc_revid, p->pc_hdr);
3757 static struct resource *
3758 pci_alloc_map(device_t dev, device_t child, int type, int *rid,
3759 u_long start, u_long end, u_long count, u_int flags)
3761 struct pci_devinfo *dinfo = device_get_ivars(child);
3762 struct resource_list *rl = &dinfo->resources;
3763 struct resource_list_entry *rle;
3764 struct resource *res;
3765 pci_addr_t map, testval;
3769 * Weed out the bogons, and figure out how large the BAR/map
3770 * is. Bars that read back 0 here are bogus and unimplemented.
3771 * Note: atapci in legacy mode are special and handled elsewhere
3772 * in the code. If you have a atapci device in legacy mode and
3773 * it fails here, that other code is broken.
3776 map = pci_read_config(child, *rid, 4);
3777 pci_write_config(child, *rid, 0xffffffff, 4);
3778 testval = pci_read_config(child, *rid, 4);
3779 if (pci_maprange(testval) == 64)
3780 map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32;
3781 if (pci_mapbase(testval) == 0)
3785 * Restore the original value of the BAR. We may have reprogrammed
3786 * the BAR of the low-level console device and when booting verbose,
3787 * we need the console device addressable.
3789 pci_write_config(child, *rid, map, 4);
3791 if (PCI_BAR_MEM(testval)) {
3792 if (type != SYS_RES_MEMORY) {
3795 "child %s requested type %d for rid %#x,"
3796 " but the BAR says it is an memio\n",
3797 device_get_nameunit(child), type, *rid);
3801 if (type != SYS_RES_IOPORT) {
3804 "child %s requested type %d for rid %#x,"
3805 " but the BAR says it is an ioport\n",
3806 device_get_nameunit(child), type, *rid);
3811 * For real BARs, we need to override the size that
3812 * the driver requests, because that's what the BAR
3813 * actually uses and we would otherwise have a
3814 * situation where we might allocate the excess to
3815 * another driver, which won't work.
3817 mapsize = pci_mapsize(testval);
3818 count = 1UL << mapsize;
3819 if (RF_ALIGNMENT(flags) < mapsize)
3820 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
3821 if (PCI_BAR_MEM(testval) && (testval & PCIM_BAR_MEM_PREFETCH))
3822 flags |= RF_PREFETCHABLE;
3825 * Allocate enough resource, and then write back the
3826 * appropriate bar for that resource.
3828 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
3829 start, end, count, flags);
3831 device_printf(child,
3832 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
3833 count, *rid, type, start, end);
3836 resource_list_add(rl, type, *rid, start, end, count, -1);
3837 rle = resource_list_find(rl, type, *rid);
3839 panic("pci_alloc_map: unexpectedly can't find resource.");
3841 rle->start = rman_get_start(res);
3842 rle->end = rman_get_end(res);
3845 device_printf(child,
3846 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
3847 count, *rid, type, rman_get_start(res));
3848 map = rman_get_start(res);
3850 pci_write_config(child, *rid, map, 4);
3851 if (pci_maprange(testval) == 64)
3852 pci_write_config(child, *rid + 4, map >> 32, 4);
3858 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
3859 u_long start, u_long end, u_long count, u_int flags)
3861 struct pci_devinfo *dinfo = device_get_ivars(child);
3862 struct resource_list *rl = &dinfo->resources;
3863 struct resource_list_entry *rle;
3864 pcicfgregs *cfg = &dinfo->cfg;
3867 * Perform lazy resource allocation
3869 if (device_get_parent(child) == dev) {
3873 * Can't alloc legacy interrupt once MSI messages
3874 * have been allocated.
3877 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
3878 cfg->msix.msix_alloc > 0))
3882 * If the child device doesn't have an
3883 * interrupt routed and is deserving of an
3884 * interrupt, try to assign it one.
3886 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
3888 pci_assign_interrupt(dev, child, 0);
3890 case SYS_RES_IOPORT:
3891 case SYS_RES_MEMORY:
3892 if (*rid < PCIR_BAR(cfg->nummaps)) {
3894 * Enable the I/O mode. We should
3895 * also be assigning resources too
3896 * when none are present. The
3897 * resource_list_alloc kind of sorta does
3900 if (PCI_ENABLE_IO(dev, child, type))
3903 rle = resource_list_find(rl, type, *rid);
3905 return (pci_alloc_map(dev, child, type, rid,
3906 start, end, count, flags));
3910 * If we've already allocated the resource, then
3911 * return it now. But first we may need to activate
3912 * it, since we don't allocate the resource as active
3913 * above. Normally this would be done down in the
3914 * nexus, but since we short-circuit that path we have
3915 * to do its job here. Not sure if we should kfree the
3916 * resource if it fails to activate.
3918 rle = resource_list_find(rl, type, *rid);
3919 if (rle != NULL && rle->res != NULL) {
3921 device_printf(child,
3922 "Reserved %#lx bytes for rid %#x type %d at %#lx\n",
3923 rman_get_size(rle->res), *rid, type,
3924 rman_get_start(rle->res));
3925 if ((flags & RF_ACTIVE) &&
3926 bus_generic_activate_resource(dev, child, type,
3927 *rid, rle->res) != 0)
3932 return (resource_list_alloc(rl, dev, child, type, rid,
3933 start, end, count, flags));
3937 pci_delete_resource(device_t dev, device_t child, int type, int rid)
3939 struct pci_devinfo *dinfo;
3940 struct resource_list *rl;
3941 struct resource_list_entry *rle;
3943 if (device_get_parent(child) != dev)
3946 dinfo = device_get_ivars(child);
3947 rl = &dinfo->resources;
3948 rle = resource_list_find(rl, type, rid);
3951 if (rman_get_device(rle->res) != dev ||
3952 rman_get_flags(rle->res) & RF_ACTIVE) {
3953 device_printf(dev, "delete_resource: "
3954 "Resource still owned by child, oops. "
3955 "(type=%d, rid=%d, addr=%lx)\n",
3956 rle->type, rle->rid,
3957 rman_get_start(rle->res));
3960 bus_release_resource(dev, type, rid, rle->res);
3962 resource_list_delete(rl, type, rid);
3965 * Why do we turn off the PCI configuration BAR when we delete a
3968 pci_write_config(child, rid, 0, 4);
3969 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid);
3972 struct resource_list *
3973 pci_get_resource_list (device_t dev, device_t child)
3975 struct pci_devinfo *dinfo = device_get_ivars(child);
3980 return (&dinfo->resources);
3984 pci_read_config_method(device_t dev, device_t child, int reg, int width)
3986 struct pci_devinfo *dinfo = device_get_ivars(child);
3987 pcicfgregs *cfg = &dinfo->cfg;
3989 return (PCIB_READ_CONFIG(device_get_parent(dev),
3990 cfg->bus, cfg->slot, cfg->func, reg, width));
3994 pci_write_config_method(device_t dev, device_t child, int reg,
3995 uint32_t val, int width)
3997 struct pci_devinfo *dinfo = device_get_ivars(child);
3998 pcicfgregs *cfg = &dinfo->cfg;
4000 PCIB_WRITE_CONFIG(device_get_parent(dev),
4001 cfg->bus, cfg->slot, cfg->func, reg, val, width);
4005 pci_child_location_str_method(device_t dev, device_t child, char *buf,
4009 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
4010 pci_get_function(child));
4015 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
4018 struct pci_devinfo *dinfo;
4021 dinfo = device_get_ivars(child);
4023 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
4024 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
4025 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
4031 pci_assign_interrupt_method(device_t dev, device_t child)
4033 struct pci_devinfo *dinfo = device_get_ivars(child);
4034 pcicfgregs *cfg = &dinfo->cfg;
4036 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
4041 pci_modevent(module_t mod, int what, void *arg)
4043 static struct cdev *pci_cdev;
4047 STAILQ_INIT(&pci_devq);
4049 pci_cdev = make_dev(&pcic_ops, 0, UID_ROOT, GID_WHEEL, 0644,
4051 pci_load_vendor_data();
4055 destroy_dev(pci_cdev);
4063 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
4068 * Only do header type 0 devices. Type 1 devices are bridges,
4069 * which we know need special treatment. Type 2 devices are
4070 * cardbus bridges which also require special treatment.
4071 * Other types are unknown, and we err on the side of safety
4074 if (dinfo->cfg.hdrtype != 0)
4078 * Restore the device to full power mode. We must do this
4079 * before we restore the registers because moving from D3 to
4080 * D0 will cause the chip's BARs and some other registers to
4081 * be reset to some unknown power on reset values. Cut down
4082 * the noise on boot by doing nothing if we are already in
4085 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
4086 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4088 for (i = 0; i < dinfo->cfg.nummaps; i++)
4089 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4);
4090 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
4091 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
4092 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
4093 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
4094 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
4095 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
4096 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
4097 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
4098 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
4099 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
4101 /* Restore MSI and MSI-X configurations if they are present. */
4102 if (dinfo->cfg.msi.msi_location != 0)
4103 pci_resume_msi(dev);
4104 if (dinfo->cfg.msix.msix_location != 0)
4105 pci_resume_msix(dev);
4109 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
4116 * Only do header type 0 devices. Type 1 devices are bridges, which
4117 * we know need special treatment. Type 2 devices are cardbus bridges
4118 * which also require special treatment. Other types are unknown, and
4119 * we err on the side of safety by ignoring them. Powering down
4120 * bridges should not be undertaken lightly.
4122 if (dinfo->cfg.hdrtype != 0)
4124 for (i = 0; i < dinfo->cfg.nummaps; i++)
4125 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4);
4126 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
4129 * Some drivers apparently write to these registers w/o updating our
4130 * cached copy. No harm happens if we update the copy, so do so here
4131 * so we can restore them. The COMMAND register is modified by the
4132 * bus w/o updating the cache. This should represent the normally
4133 * writable portion of the 'defined' part of type 0 headers. In
4134 * theory we also need to save/restore the PCI capability structures
4135 * we know about, but apart from power we don't know any that are
4138 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
4139 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4140 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
4141 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
4142 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
4143 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
4144 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
4145 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
4146 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
4147 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
4148 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
4149 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
4150 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
4151 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
4152 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
4155 * don't set the state for display devices, base peripherals and
4156 * memory devices since bad things happen when they are powered down.
4157 * We should (a) have drivers that can easily detach and (b) use
4158 * generic drivers for these devices so that some device actually
4159 * attaches. We need to make sure that when we implement (a) we don't
4160 * power the device down on a reattach.
4162 cls = pci_get_class(dev);
4165 switch (pci_do_power_nodriver)
4167 case 0: /* NO powerdown at all */
4169 case 1: /* Conservative about what to power down */
4170 if (cls == PCIC_STORAGE)
4173 case 2: /* Agressive about what to power down */
4174 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
4175 cls == PCIC_BASEPERIPH)
4178 case 3: /* Power down everything */
4182 * PCI spec says we can only go into D3 state from D0 state.
4183 * Transition from D[12] into D0 before going to D3 state.
4185 ps = pci_get_powerstate(dev);
4186 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
4187 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4188 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
4189 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
4192 #ifdef COMPAT_OLDPCI
4195 * Locate the parent of a PCI device by scanning the PCI devlist
4196 * and return the entry for the parent.
4197 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
4198 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
4201 pci_devlist_get_parent(pcicfgregs *cfg)
4203 struct devlist *devlist_head;
4204 struct pci_devinfo *dinfo;
4205 pcicfgregs *bridge_cfg;
4208 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
4210 /* If the device is on PCI bus 0, look for the host */
4211 if (cfg->bus == 0) {
4212 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
4213 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
4214 bridge_cfg = &dinfo->cfg;
4215 if (bridge_cfg->baseclass == PCIC_BRIDGE
4216 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
4217 && bridge_cfg->bus == cfg->bus) {
4223 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
4225 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
4226 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
4227 bridge_cfg = &dinfo->cfg;
4228 if (bridge_cfg->baseclass == PCIC_BRIDGE
4229 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
4230 && bridge_cfg->secondarybus == cfg->bus) {
4239 #endif /* COMPAT_OLDPCI */