2 * Copyright 2008 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Jerome Glisse <glisse@freedesktop.org>
27 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_cs.c 254885 2013-08-25 19:37:15Z dumbbell $
31 #include <uapi_drm/radeon_drm.h>
32 #include "radeon_reg.h"
35 static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
37 struct drm_device *ddev = p->rdev->ddev;
38 struct radeon_cs_chunk *chunk;
42 if (p->chunk_relocs_idx == -1) {
45 chunk = &p->chunks[p->chunk_relocs_idx];
47 /* FIXME: we assume that each relocs use 4 dwords */
48 p->nrelocs = chunk->length_dw / 4;
49 p->relocs_ptr = kmalloc(p->nrelocs * sizeof(void *), M_DRM,
51 if (p->relocs_ptr == NULL) {
54 p->relocs = kmalloc(p->nrelocs * sizeof(struct radeon_cs_reloc),
55 M_DRM, M_ZERO | M_WAITOK);
56 if (p->relocs == NULL) {
59 for (i = 0; i < p->nrelocs; i++) {
60 struct drm_radeon_cs_reloc *r;
63 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
64 for (j = 0; j < i; j++) {
65 if (r->handle == p->relocs[j].handle) {
66 p->relocs_ptr[i] = &p->relocs[j];
72 p->relocs[i].gobj = drm_gem_object_lookup(ddev,
75 if (p->relocs[i].gobj == NULL) {
76 DRM_ERROR("gem object lookup failed 0x%x\n",
80 p->relocs_ptr[i] = &p->relocs[i];
81 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
82 p->relocs[i].lobj.bo = p->relocs[i].robj;
83 p->relocs[i].lobj.wdomain = r->write_domain;
84 p->relocs[i].lobj.rdomain = r->read_domains;
85 p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
86 p->relocs[i].handle = r->handle;
87 p->relocs[i].flags = r->flags;
88 radeon_bo_list_add_object(&p->relocs[i].lobj,
92 p->relocs[i].handle = 0;
94 return radeon_bo_list_validate(&p->validated);
97 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
99 p->priority = priority;
103 DRM_ERROR("unknown ring id: %d\n", ring);
105 case RADEON_CS_RING_GFX:
106 p->ring = RADEON_RING_TYPE_GFX_INDEX;
108 case RADEON_CS_RING_COMPUTE:
109 if (p->rdev->family >= CHIP_TAHITI) {
111 p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
113 p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
115 p->ring = RADEON_RING_TYPE_GFX_INDEX;
117 case RADEON_CS_RING_DMA:
118 if (p->rdev->family >= CHIP_CAYMAN) {
120 p->ring = R600_RING_TYPE_DMA_INDEX;
122 p->ring = CAYMAN_RING_TYPE_DMA1_INDEX;
123 } else if (p->rdev->family >= CHIP_R600) {
124 p->ring = R600_RING_TYPE_DMA_INDEX;
133 static void radeon_cs_sync_rings(struct radeon_cs_parser *p)
137 for (i = 0; i < p->nrelocs; i++) {
138 if (!p->relocs[i].robj)
141 radeon_ib_sync_to(&p->ib, p->relocs[i].robj->tbo.sync_obj);
145 /* XXX: note that this is called from the legacy UMS CS ioctl as well */
146 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
148 struct drm_radeon_cs *cs = data;
149 uint64_t *chunk_array_ptr;
151 u32 ring = RADEON_CS_RING_GFX;
154 if (!cs->num_chunks) {
158 INIT_LIST_HEAD(&p->validated);
161 p->ib.semaphore = NULL;
162 p->const_ib.sa_bo = NULL;
163 p->const_ib.semaphore = NULL;
164 p->chunk_ib_idx = -1;
165 p->chunk_relocs_idx = -1;
166 p->chunk_flags_idx = -1;
167 p->chunk_const_ib_idx = -1;
168 p->chunks_array = kmalloc(cs->num_chunks * sizeof(uint64_t),
169 M_DRM, M_ZERO | M_WAITOK);
170 if (p->chunks_array == NULL) {
173 chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
174 if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
175 sizeof(uint64_t)*cs->num_chunks)) {
179 p->nchunks = cs->num_chunks;
180 p->chunks = kmalloc(p->nchunks * sizeof(struct radeon_cs_chunk),
181 M_DRM, M_ZERO | M_WAITOK);
182 if (p->chunks == NULL) {
185 for (i = 0; i < p->nchunks; i++) {
186 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
187 struct drm_radeon_cs_chunk user_chunk;
188 uint32_t __user *cdata;
190 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
191 if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
192 sizeof(struct drm_radeon_cs_chunk))) {
195 p->chunks[i].length_dw = user_chunk.length_dw;
196 p->chunks[i].kdata = NULL;
197 p->chunks[i].chunk_id = user_chunk.chunk_id;
198 p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;
199 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
200 p->chunk_relocs_idx = i;
202 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
204 /* zero length IB isn't useful */
205 if (p->chunks[i].length_dw == 0)
208 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
209 p->chunk_const_ib_idx = i;
210 /* zero length CONST IB isn't useful */
211 if (p->chunks[i].length_dw == 0)
214 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
215 p->chunk_flags_idx = i;
216 /* zero length flags aren't useful */
217 if (p->chunks[i].length_dw == 0)
221 cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
222 if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) ||
223 (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
224 size = p->chunks[i].length_dw * sizeof(uint32_t);
225 p->chunks[i].kdata = kmalloc(size, M_DRM,
227 if (p->chunks[i].kdata == NULL) {
230 if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
231 p->chunks[i].user_ptr, size)) {
234 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
235 p->cs_flags = p->chunks[i].kdata[0];
236 if (p->chunks[i].length_dw > 1)
237 ring = p->chunks[i].kdata[1];
238 if (p->chunks[i].length_dw > 2)
239 priority = (s32)p->chunks[i].kdata[2];
244 /* these are KMS only */
246 if ((p->cs_flags & RADEON_CS_USE_VM) &&
247 !p->rdev->vm_manager.enabled) {
248 DRM_ERROR("VM not active on asic!\n");
252 /* we only support VM on SI+ */
253 if ((p->rdev->family >= CHIP_TAHITI) &&
254 ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
255 DRM_ERROR("VM required on SI+!\n");
259 if (radeon_cs_get_ring(p, ring, priority))
263 /* deal with non-vm */
264 if ((p->chunk_ib_idx != -1) &&
265 ((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
266 (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
267 if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
268 DRM_ERROR("cs IB too big: %d\n",
269 p->chunks[p->chunk_ib_idx].length_dw);
272 if (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) {
273 p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE,
276 p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE,
279 if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL ||
280 p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
281 drm_free(p->chunks[p->chunk_ib_idx].kpage[0],
283 drm_free(p->chunks[p->chunk_ib_idx].kpage[1],
285 p->chunks[p->chunk_ib_idx].kpage[0] = NULL;
286 p->chunks[p->chunk_ib_idx].kpage[1] = NULL;
290 p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
291 p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
292 p->chunks[p->chunk_ib_idx].last_copied_page = -1;
293 p->chunks[p->chunk_ib_idx].last_page_index =
294 ((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
301 * cs_parser_fini() - clean parser states
302 * @parser: parser structure holding parsing context.
303 * @error: error number
305 * If error is set than unvalidate buffer, otherwise just free memory
306 * used by parsing context.
308 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
313 ttm_eu_fence_buffer_objects(&parser->validated,
316 ttm_eu_backoff_reservation(&parser->validated);
319 if (parser->relocs != NULL) {
320 for (i = 0; i < parser->nrelocs; i++) {
321 if (parser->relocs[i].gobj)
322 drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
325 drm_free(parser->track, M_DRM);
326 drm_free(parser->relocs, M_DRM);
327 drm_free(parser->relocs_ptr, M_DRM);
328 for (i = 0; i < parser->nchunks; i++) {
329 drm_free(parser->chunks[i].kdata, M_DRM);
330 if ((parser->rdev->flags & RADEON_IS_AGP)) {
331 drm_free(parser->chunks[i].kpage[0], M_DRM);
332 drm_free(parser->chunks[i].kpage[1], M_DRM);
335 drm_free(parser->chunks, M_DRM);
336 drm_free(parser->chunks_array, M_DRM);
337 radeon_ib_free(parser->rdev, &parser->ib);
338 radeon_ib_free(parser->rdev, &parser->const_ib);
341 static int radeon_cs_ib_chunk(struct radeon_device *rdev,
342 struct radeon_cs_parser *parser)
344 struct radeon_cs_chunk *ib_chunk;
347 if (parser->chunk_ib_idx == -1)
350 if (parser->cs_flags & RADEON_CS_USE_VM)
353 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
354 /* Copy the packet into the IB, the parser will read from the
355 * input memory (cached) and write to the IB (which can be
358 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
359 NULL, ib_chunk->length_dw * 4);
361 DRM_ERROR("Failed to get ib !\n");
364 parser->ib.length_dw = ib_chunk->length_dw;
365 r = radeon_cs_parse(rdev, parser->ring, parser);
366 if (r || parser->parser_error) {
367 DRM_ERROR("Invalid command stream !\n");
370 r = radeon_cs_finish_pages(parser);
372 DRM_ERROR("Invalid command stream !\n");
375 radeon_cs_sync_rings(parser);
376 r = radeon_ib_schedule(rdev, &parser->ib, NULL);
378 DRM_ERROR("Failed to schedule IB !\n");
383 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
384 struct radeon_vm *vm)
386 struct radeon_device *rdev = parser->rdev;
387 struct radeon_bo_list *lobj;
388 struct radeon_bo *bo;
391 r = radeon_vm_bo_update_pte(rdev, vm, rdev->ring_tmp_bo.bo, &rdev->ring_tmp_bo.bo->tbo.mem);
395 list_for_each_entry(lobj, &parser->validated, tv.head) {
397 r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
405 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
406 struct radeon_cs_parser *parser)
408 struct radeon_cs_chunk *ib_chunk;
409 struct radeon_fpriv *fpriv = parser->filp->driver_priv;
410 struct radeon_vm *vm = &fpriv->vm;
413 if (parser->chunk_ib_idx == -1)
415 if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
418 if ((rdev->family >= CHIP_TAHITI) &&
419 (parser->chunk_const_ib_idx != -1)) {
420 ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
421 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
422 DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
425 r = radeon_ib_get(rdev, parser->ring, &parser->const_ib,
426 vm, ib_chunk->length_dw * 4);
428 DRM_ERROR("Failed to get const ib !\n");
431 parser->const_ib.is_const_ib = true;
432 parser->const_ib.length_dw = ib_chunk->length_dw;
433 /* Copy the packet into the IB */
434 if (DRM_COPY_FROM_USER(parser->const_ib.ptr, ib_chunk->user_ptr,
435 ib_chunk->length_dw * 4)) {
438 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib);
444 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
445 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
446 DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
449 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
450 vm, ib_chunk->length_dw * 4);
452 DRM_ERROR("Failed to get ib !\n");
455 parser->ib.length_dw = ib_chunk->length_dw;
456 /* Copy the packet into the IB */
457 if (DRM_COPY_FROM_USER(parser->ib.ptr, ib_chunk->user_ptr,
458 ib_chunk->length_dw * 4)) {
461 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib);
466 lockmgr(&rdev->vm_manager.lock, LK_EXCLUSIVE);
467 lockmgr(&vm->mutex, LK_EXCLUSIVE);
468 r = radeon_vm_alloc_pt(rdev, vm);
472 r = radeon_bo_vm_update_pte(parser, vm);
476 radeon_cs_sync_rings(parser);
477 radeon_ib_sync_to(&parser->ib, vm->fence);
478 radeon_ib_sync_to(&parser->ib, radeon_vm_grab_id(
479 rdev, vm, parser->ring));
481 if ((rdev->family >= CHIP_TAHITI) &&
482 (parser->chunk_const_ib_idx != -1)) {
483 r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib);
485 r = radeon_ib_schedule(rdev, &parser->ib, NULL);
489 radeon_vm_fence(rdev, vm, parser->ib.fence);
493 radeon_vm_add_to_lru(rdev, vm);
494 lockmgr(&vm->mutex, LK_RELEASE);
495 lockmgr(&rdev->vm_manager.lock, LK_RELEASE);
499 static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r)
502 r = radeon_gpu_reset(rdev);
509 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
511 struct radeon_device *rdev = dev->dev_private;
512 struct radeon_cs_parser parser;
515 lockmgr(&rdev->exclusive_lock, LK_EXCLUSIVE);
516 if (!rdev->accel_working) {
517 lockmgr(&rdev->exclusive_lock, LK_RELEASE);
520 /* initialize parser */
521 memset(&parser, 0, sizeof(struct radeon_cs_parser));
524 parser.dev = rdev->dev;
525 parser.family = rdev->family;
526 r = radeon_cs_parser_init(&parser, data);
528 DRM_ERROR("Failed to initialize parser !\n");
529 radeon_cs_parser_fini(&parser, r);
530 lockmgr(&rdev->exclusive_lock, LK_RELEASE);
531 r = radeon_cs_handle_lockup(rdev, r);
534 r = radeon_cs_parser_relocs(&parser);
536 if (r != -ERESTARTSYS)
537 DRM_ERROR("Failed to parse relocation %d!\n", r);
538 radeon_cs_parser_fini(&parser, r);
539 lockmgr(&rdev->exclusive_lock, LK_RELEASE);
540 r = radeon_cs_handle_lockup(rdev, r);
543 r = radeon_cs_ib_chunk(rdev, &parser);
547 r = radeon_cs_ib_vm_chunk(rdev, &parser);
552 radeon_cs_parser_fini(&parser, r);
553 lockmgr(&rdev->exclusive_lock, LK_RELEASE);
554 r = radeon_cs_handle_lockup(rdev, r);
558 int radeon_cs_finish_pages(struct radeon_cs_parser *p)
560 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
562 int size = PAGE_SIZE;
564 for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
565 if (i == ibc->last_page_index) {
566 size = (ibc->length_dw * 4) % PAGE_SIZE;
571 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
572 (char *)ibc->user_ptr + (i * PAGE_SIZE),
579 static int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
582 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
584 int size = PAGE_SIZE;
585 bool copy1 = (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) ?
588 for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
589 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
590 (char *)ibc->user_ptr + (i * PAGE_SIZE),
592 p->parser_error = -EFAULT;
597 if (pg_idx == ibc->last_page_index) {
598 size = (ibc->length_dw * 4) % PAGE_SIZE;
603 new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
605 ibc->kpage[new_page] = p->ib.ptr + (pg_idx * (PAGE_SIZE / 4));
607 if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
608 (char *)ibc->user_ptr + (pg_idx * PAGE_SIZE),
610 p->parser_error = -EFAULT;
614 /* copy to IB for non single case */
616 memcpy((void *)(p->ib.ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size);
618 ibc->last_copied_page = pg_idx;
619 ibc->kpage_idx[new_page] = pg_idx;
624 u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
626 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
627 u32 pg_idx, pg_offset;
631 pg_idx = (idx * 4) / PAGE_SIZE;
632 pg_offset = (idx * 4) % PAGE_SIZE;
634 if (ibc->kpage_idx[0] == pg_idx)
635 return ibc->kpage[0][pg_offset/4];
636 if (ibc->kpage_idx[1] == pg_idx)
637 return ibc->kpage[1][pg_offset/4];
639 new_page = radeon_cs_update_pages(p, pg_idx);
641 p->parser_error = new_page;
645 idx_value = ibc->kpage[new_page][pg_offset/4];
650 * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet
651 * @parser: parser structure holding parsing context.
652 * @pkt: where to store packet information
654 * Assume that chunk_ib_index is properly set. Will return -EINVAL
655 * if packet is bigger than remaining ib size. or if packets is unknown.
657 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
658 struct radeon_cs_packet *pkt,
661 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
662 struct radeon_device *rdev = p->rdev;
665 if (idx >= ib_chunk->length_dw) {
666 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
667 idx, ib_chunk->length_dw);
670 header = radeon_get_ib_value(p, idx);
672 pkt->type = RADEON_CP_PACKET_GET_TYPE(header);
673 pkt->count = RADEON_CP_PACKET_GET_COUNT(header);
676 case RADEON_PACKET_TYPE0:
677 if (rdev->family < CHIP_R600) {
678 pkt->reg = R100_CP_PACKET0_GET_REG(header);
680 RADEON_CP_PACKET0_GET_ONE_REG_WR(header);
682 pkt->reg = R600_CP_PACKET0_GET_REG(header);
684 case RADEON_PACKET_TYPE3:
685 pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header);
687 case RADEON_PACKET_TYPE2:
691 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
694 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
695 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
696 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
703 * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP
704 * @p: structure holding the parser context.
706 * Check if the next packet is NOP relocation packet3.
708 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
710 struct radeon_cs_packet p3reloc;
713 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
716 if (p3reloc.type != RADEON_PACKET_TYPE3)
718 if (p3reloc.opcode != RADEON_PACKET3_NOP)
724 * radeon_cs_dump_packet() - dump raw packet context
725 * @p: structure holding the parser context.
726 * @pkt: structure holding the packet.
728 * Used mostly for debugging and error reporting.
730 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
731 struct radeon_cs_packet *pkt)
733 volatile uint32_t *ib;
739 for (i = 0; i <= (pkt->count + 1); i++, idx++)
740 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
744 * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet
745 * @parser: parser structure holding parsing context.
746 * @data: pointer to relocation data
747 * @offset_start: starting offset
748 * @offset_mask: offset mask (to align start offset on)
749 * @reloc: reloc informations
751 * Check if next packet is relocation packet3, do bo validation and compute
752 * GPU offset using the provided start.
754 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
755 struct radeon_cs_reloc **cs_reloc,
758 struct radeon_cs_chunk *relocs_chunk;
759 struct radeon_cs_packet p3reloc;
763 if (p->chunk_relocs_idx == -1) {
764 DRM_ERROR("No relocation chunk !\n");
768 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
769 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
772 p->idx += p3reloc.count + 2;
773 if (p3reloc.type != RADEON_PACKET_TYPE3 ||
774 p3reloc.opcode != RADEON_PACKET3_NOP) {
775 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
777 radeon_cs_dump_packet(p, &p3reloc);
780 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
781 if (idx >= relocs_chunk->length_dw) {
782 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
783 idx, relocs_chunk->length_dw);
784 radeon_cs_dump_packet(p, &p3reloc);
787 /* FIXME: we assume reloc size is 4 dwords */
789 *cs_reloc = p->relocs;
790 (*cs_reloc)->lobj.gpu_offset =
791 (u64)relocs_chunk->kdata[idx + 3] << 32;
792 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
794 *cs_reloc = p->relocs_ptr[(idx / 4)];