2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
26 * $DragonFly: src/sys/platform/pc32/apic/mpapic.c,v 1.22 2008/04/20 13:44:26 swildner Exp $
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/kernel.h>
32 #include <machine/globaldata.h>
33 #include <machine/smp.h>
34 #include <machine/cputypes.h>
35 #include <machine/md_var.h>
36 #include <machine/pmap.h>
37 #include <machine_base/apic/mpapic.h>
38 #include <machine/segments.h>
39 #include <sys/thread2.h>
41 #include <machine_base/isa/intr_machdep.h> /* Xspuriousint() */
44 extern pt_entry_t *SMPpt;
46 /* EISA Edge/Level trigger control registers */
47 #define ELCR0 0x4d0 /* eisa irq 0-7 */
48 #define ELCR1 0x4d1 /* eisa irq 8-15 */
50 static void lapic_timer_calibrate(void);
51 static void lapic_timer_set_divisor(int);
52 static void lapic_timer_fixup_handler(void *);
53 static void lapic_timer_restart_handler(void *);
55 void lapic_timer_process(void);
56 void lapic_timer_process_frame(struct intrframe *);
58 static int lapic_timer_enable = 1;
59 TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
61 static void lapic_timer_intr_reload(struct cputimer_intr *, sysclock_t);
62 static void lapic_timer_intr_enable(struct cputimer_intr *);
63 static void lapic_timer_intr_restart(struct cputimer_intr *);
64 static void lapic_timer_intr_pmfixup(struct cputimer_intr *);
66 static struct cputimer_intr lapic_cputimer_intr = {
68 .reload = lapic_timer_intr_reload,
69 .enable = lapic_timer_intr_enable,
70 .config = cputimer_intr_default_config,
71 .restart = lapic_timer_intr_restart,
72 .pmfixup = lapic_timer_intr_pmfixup,
73 .initclock = cputimer_intr_default_initclock,
74 .next = SLIST_ENTRY_INITIALIZER,
76 .type = CPUTIMER_INTR_LAPIC,
77 .prio = CPUTIMER_INTR_PRIO_LAPIC,
78 .caps = CPUTIMER_INTR_CAP_NONE
82 * pointers to pmapped apic hardware.
85 volatile ioapic_t **ioapic;
87 static int lapic_timer_divisor_idx = -1;
88 static const uint32_t lapic_timer_divisors[] = {
89 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
90 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
92 #define APIC_TIMER_NDIVISORS \
93 (int)(sizeof(lapic_timer_divisors) / sizeof(lapic_timer_divisors[0]))
97 * Enable APIC, configure interrupts.
100 apic_initialize(boolean_t bsp)
106 * setup LVT1 as ExtINT on the BSP. This is theoretically an
107 * aggregate interrupt input from the 8259. The INTA cycle
108 * will be routed to the external controller (the 8259) which
109 * is expected to supply the vector.
111 * Must be setup edge triggered, active high.
113 * Disable LVT1 on the APs. It doesn't matter what delivery
114 * mode we use because we leave it masked.
116 temp = lapic.lvt_lint0;
117 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
118 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
119 if (mycpu->gd_cpuid == 0)
120 temp |= APIC_LVT_DM_EXTINT;
122 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
123 lapic.lvt_lint0 = temp;
126 * setup LVT2 as NMI, masked till later. Edge trigger, active high.
128 temp = lapic.lvt_lint1;
129 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
130 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
131 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
132 lapic.lvt_lint1 = temp;
135 * Mask the apic error interrupt, apic performance counter
138 lapic.lvt_error = lapic.lvt_error | APIC_LVT_MASKED;
139 lapic.lvt_pcint = lapic.lvt_pcint | APIC_LVT_MASKED;
141 /* Set apic timer vector and mask the apic timer interrupt. */
142 timer = lapic.lvt_timer;
143 timer &= ~APIC_LVTT_VECTOR;
144 timer |= XTIMER_OFFSET;
145 timer |= APIC_LVTT_MASKED;
146 lapic.lvt_timer = timer;
149 * Set the Task Priority Register as needed. At the moment allow
150 * interrupts on all cpus (the APs will remain CLId until they are
151 * ready to deal). We could disable all but IPIs by setting
152 * temp |= TPR_IPI_ONLY for cpu != 0.
155 temp &= ~APIC_TPR_PRIO; /* clear priority field */
158 * If we are NOT running the IO APICs, the LAPIC will only be used
159 * for IPIs. Set the TPR to prevent any unintentional interrupts.
161 temp |= TPR_IPI_ONLY;
167 * enable the local APIC
170 temp |= APIC_SVR_ENABLE; /* enable the APIC */
171 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
174 * Set the spurious interrupt vector. The low 4 bits of the vector
177 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
178 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
179 temp &= ~APIC_SVR_VECTOR;
180 temp |= XSPURIOUSINT_OFFSET;
185 * Pump out a few EOIs to clean out interrupts that got through
186 * before we were able to set the TPR.
193 lapic_timer_calibrate();
194 if (lapic_timer_enable) {
195 cputimer_intr_register(&lapic_cputimer_intr);
196 cputimer_intr_select(&lapic_cputimer_intr, 0);
199 lapic_timer_set_divisor(lapic_timer_divisor_idx);
203 apic_dump("apic_initialize()");
208 lapic_timer_set_divisor(int divisor_idx)
210 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
211 lapic.dcr_timer = lapic_timer_divisors[divisor_idx];
215 lapic_timer_oneshot(u_int count)
219 value = lapic.lvt_timer;
220 value &= ~APIC_LVTT_PERIODIC;
221 lapic.lvt_timer = value;
222 lapic.icr_timer = count;
226 lapic_timer_oneshot_quick(u_int count)
228 lapic.icr_timer = count;
232 lapic_timer_calibrate(void)
236 /* Try to calibrate the local APIC timer. */
237 for (lapic_timer_divisor_idx = 0;
238 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
239 lapic_timer_divisor_idx++) {
240 lapic_timer_set_divisor(lapic_timer_divisor_idx);
241 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
243 value = APIC_TIMER_MAX_COUNT - lapic.ccr_timer;
244 if (value != APIC_TIMER_MAX_COUNT)
247 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
248 panic("lapic: no proper timer divisor?!\n");
249 lapic_cputimer_intr.freq = value / 2;
251 kprintf("lapic: divisor index %d, frequency %u Hz\n",
252 lapic_timer_divisor_idx, lapic_cputimer_intr.freq);
256 lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
260 gd->gd_timer_running = 0;
262 count = sys_cputimer->count();
263 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
264 systimer_intr(&count, 0, frame);
268 lapic_timer_process(void)
270 lapic_timer_process_oncpu(mycpu, NULL);
274 lapic_timer_process_frame(struct intrframe *frame)
276 lapic_timer_process_oncpu(mycpu, frame);
280 lapic_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
282 struct globaldata *gd = mycpu;
284 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
288 if (gd->gd_timer_running) {
289 if (reload < lapic.ccr_timer)
290 lapic_timer_oneshot_quick(reload);
292 gd->gd_timer_running = 1;
293 lapic_timer_oneshot_quick(reload);
298 lapic_timer_intr_enable(struct cputimer_intr *cti __unused)
302 timer = lapic.lvt_timer;
303 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
304 lapic.lvt_timer = timer;
306 lapic_timer_fixup_handler(NULL);
310 lapic_timer_fixup_handler(void *arg)
317 if (cpu_vendor_id == CPU_VENDOR_AMD) {
319 * Detect the presence of C1E capability mostly on latest
320 * dual-cores (or future) k8 family. This feature renders
321 * the local APIC timer dead, so we disable it by reading
322 * the Interrupt Pending Message register and clearing both
323 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
326 * "BIOS and Kernel Developer's Guide for AMD NPT
327 * Family 0Fh Processors"
328 * #32559 revision 3.00
330 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
331 (cpu_id & 0x0fff0000) >= 0x00040000) {
334 msr = rdmsr(0xc0010055);
335 if (msr & 0x18000000) {
336 struct globaldata *gd = mycpu;
338 kprintf("cpu%d: AMD C1E detected\n",
340 wrmsr(0xc0010055, msr & ~0x18000000ULL);
343 * We are kinda stalled;
346 gd->gd_timer_running = 1;
347 lapic_timer_oneshot_quick(2);
357 lapic_timer_restart_handler(void *dummy __unused)
361 lapic_timer_fixup_handler(&started);
363 struct globaldata *gd = mycpu;
365 gd->gd_timer_running = 1;
366 lapic_timer_oneshot_quick(2);
371 * This function is called only by ACPI-CA code currently:
372 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
373 * module controls PM. So once ACPI-CA is attached, we try
374 * to apply the fixup to prevent LAPIC timer from hanging.
377 lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused)
379 lwkt_send_ipiq_mask(smp_active_mask,
380 lapic_timer_fixup_handler, NULL);
384 lapic_timer_intr_restart(struct cputimer_intr *cti __unused)
386 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL);
391 * dump contents of local APIC registers
396 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
397 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
398 lapic.lvt_lint0, lapic.lvt_lint1, lapic.tpr, lapic.svr);
408 #define IOAPIC_ISA_INTS 16
409 #define REDIRCNT_IOAPIC(A) \
410 ((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1)
412 static int trigger (int apic, int pin, u_int32_t * flags);
413 static void polarity (int apic, int pin, u_int32_t * flags, int level);
415 #define DEFAULT_FLAGS \
421 #define DEFAULT_ISA_FLAGS \
430 io_apic_set_id(int apic, int id)
434 ux = io_apic_read(apic, IOAPIC_ID); /* get current contents */
435 if (((ux & APIC_ID_MASK) >> 24) != id) {
436 kprintf("Changing APIC ID for IO APIC #%d"
437 " from %d to %d on chip\n",
438 apic, ((ux & APIC_ID_MASK) >> 24), id);
439 ux &= ~APIC_ID_MASK; /* clear the ID field */
441 io_apic_write(apic, IOAPIC_ID, ux); /* write new value */
442 ux = io_apic_read(apic, IOAPIC_ID); /* re-read && test */
443 if (((ux & APIC_ID_MASK) >> 24) != id)
444 panic("can't control IO APIC #%d ID, reg: 0x%08x",
451 io_apic_get_id(int apic)
453 return (io_apic_read(apic, IOAPIC_ID) & APIC_ID_MASK) >> 24;
462 io_apic_setup_intpin(int apic, int pin)
464 int bus, bustype, irq;
465 u_char select; /* the select register is 8 bits */
466 u_int32_t flags; /* the window register is 32 bits */
467 u_int32_t target; /* the window register is 32 bits */
468 u_int32_t vector; /* the window register is 32 bits */
473 select = pin * 2 + IOAPIC_REDTBL0; /* register */
476 * Always clear an IO APIC pin before [re]programming it. This is
477 * particularly important if the pin is set up for a level interrupt
478 * as the IOART_REM_IRR bit might be set. When we reprogram the
479 * vector any EOI from pending ints on this pin could be lost and
480 * IRR might never get reset.
482 * To fix this problem, clear the vector and make sure it is
483 * programmed as an edge interrupt. This should theoretically
484 * clear IRR so we can later, safely program it as a level
489 flags = io_apic_read(apic, select) & IOART_RESV;
490 flags |= IOART_INTMSET | IOART_TRGREDG | IOART_INTAHI;
491 flags |= IOART_DESTPHY | IOART_DELFIXED;
493 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
494 target |= 0; /* fixed mode cpu mask of 0 - don't deliver anywhere */
498 io_apic_write(apic, select, flags | vector);
499 io_apic_write(apic, select + 1, target);
504 * We only deal with vectored interrupts here. ? documentation is
505 * lacking, I'm guessing an interrupt type of 0 is the 'INT' type,
508 * This test also catches unconfigured pins.
510 if (apic_int_type(apic, pin) != 0)
514 * Leave the pin unprogrammed if it does not correspond to
517 irq = apic_irq(apic, pin);
521 /* determine the bus type for this pin */
522 bus = apic_src_bus_id(apic, pin);
525 bustype = apic_bus_type(bus);
527 if ((bustype == ISA) &&
528 (pin < IOAPIC_ISA_INTS) &&
530 (apic_polarity(apic, pin) == 0x1) &&
531 (apic_trigger(apic, pin) == 0x3)) {
533 * A broken BIOS might describe some ISA
534 * interrupts as active-high level-triggered.
535 * Use default ISA flags for those interrupts.
537 flags = DEFAULT_ISA_FLAGS;
540 * Program polarity and trigger mode according to
543 flags = DEFAULT_FLAGS;
544 level = trigger(apic, pin, &flags);
546 int_to_apicintpin[irq].flags |= IOAPIC_IM_FLAG_LEVEL;
547 polarity(apic, pin, &flags, level);
551 ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", irq);
552 kgetenv_int(envpath, &cpuid);
554 /* ncpus may not be available yet */
559 kprintf("IOAPIC #%d intpin %d -> irq %d (CPU%d)\n",
560 apic, pin, irq, cpuid);
564 * Program the appropriate registers. This routing may be
565 * overridden when an interrupt handler for a device is
566 * actually added (see register_int(), which calls through
567 * the MACHINTR ABI to set up an interrupt handler/vector).
569 * The order in which we must program the two registers for
570 * safety is unclear! XXX
574 vector = IDT_OFFSET + irq; /* IDT vec */
575 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
576 /* Deliver all interrupts to CPU0 (BSP) */
577 target |= (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
579 flags |= io_apic_read(apic, select) & IOART_RESV;
580 io_apic_write(apic, select, flags | vector);
581 io_apic_write(apic, select + 1, target);
587 io_apic_setup(int apic)
592 maxpin = REDIRCNT_IOAPIC(apic); /* pins in APIC */
593 kprintf("Programming %d pins in IOAPIC #%d\n", maxpin, apic);
595 for (pin = 0; pin < maxpin; ++pin) {
596 io_apic_setup_intpin(apic, pin);
599 if (apic_int_type(apic, pin) >= 0) {
600 kprintf("Warning: IOAPIC #%d pin %d does not exist,"
601 " cannot program!\n", apic, pin);
606 /* return GOOD status */
609 #undef DEFAULT_ISA_FLAGS
613 #define DEFAULT_EXTINT_FLAGS \
622 * XXX this function is only used by 8254 setup
623 * Setup the source of External INTerrupts.
626 ext_int_setup(int apic, int intr)
628 u_char select; /* the select register is 8 bits */
629 u_int32_t flags; /* the window register is 32 bits */
630 u_int32_t target; /* the window register is 32 bits */
631 u_int32_t vector; /* the window register is 32 bits */
635 if (apic_int_type(apic, intr) != 3)
639 ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", intr);
640 kgetenv_int(envpath, &cpuid);
642 /* ncpus may not be available yet */
646 /* Deliver interrupts to CPU0 (BSP) */
647 target = (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
649 select = IOAPIC_REDTBL0 + (2 * intr);
650 vector = IDT_OFFSET + intr;
651 flags = DEFAULT_EXTINT_FLAGS;
653 io_apic_write(apic, select, flags | vector);
654 io_apic_write(apic, select + 1, target);
658 #undef DEFAULT_EXTINT_FLAGS
662 * Set the trigger level for an IO APIC pin.
665 trigger(int apic, int pin, u_int32_t * flags)
670 static int intcontrol = -1;
672 switch (apic_trigger(apic, pin)) {
678 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG */
682 *flags |= IOART_TRGRLVL;
690 if ((id = apic_src_bus_id(apic, pin)) == -1)
693 switch (apic_bus_type(id)) {
695 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG; */
699 eirq = apic_src_bus_irq(apic, pin);
701 if (eirq < 0 || eirq > 15) {
702 kprintf("EISA IRQ %d?!?!\n", eirq);
706 if (intcontrol == -1) {
707 intcontrol = inb(ELCR1) << 8;
708 intcontrol |= inb(ELCR0);
709 kprintf("EISA INTCONTROL = %08x\n", intcontrol);
712 /* Use ELCR settings to determine level or edge mode */
713 level = (intcontrol >> eirq) & 1;
716 * Note that on older Neptune chipset based systems, any
717 * pci interrupts often show up here and in the ELCR as well
718 * as level sensitive interrupts attributed to the EISA bus.
722 *flags |= IOART_TRGRLVL;
724 *flags &= ~IOART_TRGRLVL;
729 *flags |= IOART_TRGRLVL;
738 panic("bad APIC IO INT flags");
743 * Set the polarity value for an IO APIC pin.
746 polarity(int apic, int pin, u_int32_t * flags, int level)
750 switch (apic_polarity(apic, pin)) {
756 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
760 *flags |= IOART_INTALO;
768 if ((id = apic_src_bus_id(apic, pin)) == -1)
771 switch (apic_bus_type(id)) {
773 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
777 /* polarity converter always gives active high */
778 *flags &= ~IOART_INTALO;
782 *flags |= IOART_INTALO;
791 panic("bad APIC IO INT flags");
796 * Print contents of unmasked IRQs.
803 kprintf("SMP: enabled INTs: ");
804 for (x = 0; x < APIC_INTMAPSIZE; ++x) {
805 if ((int_to_apicintpin[x].flags & IOAPIC_IM_FLAG_MASKED) == 0)
813 * Inter Processor Interrupt functions.
819 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
821 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
822 * vector is any valid SYSTEM INT vector
823 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
825 * A backlog of requests can create a deadlock between cpus. To avoid this
826 * we have to be able to accept IPIs at the same time we are trying to send
827 * them. The critical section prevents us from attempting to send additional
828 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
829 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
830 * to occur but fortunately it does not happen too often.
833 apic_ipi(int dest_type, int vector, int delivery_mode)
838 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
839 unsigned int eflags = read_eflags();
841 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
844 write_eflags(eflags);
847 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
848 delivery_mode | vector;
849 lapic.icr_lo = icr_lo;
855 single_apic_ipi(int cpu, int vector, int delivery_mode)
861 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
862 unsigned int eflags = read_eflags();
864 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
867 write_eflags(eflags);
869 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
870 icr_hi |= (CPU_TO_ID(cpu) << 24);
871 lapic.icr_hi = icr_hi;
874 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK)
875 | APIC_DEST_DESTFLD | delivery_mode | vector;
878 lapic.icr_lo = icr_lo;
885 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
887 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
888 * to the target, and the scheduler does not 'poll' for IPI messages.
891 single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
897 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
901 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
902 icr_hi |= (CPU_TO_ID(cpu) << 24);
903 lapic.icr_hi = icr_hi;
906 icr_lo = (lapic.icr_lo & APIC_RESV2_MASK)
907 | APIC_DEST_DESTFLD | delivery_mode | vector;
910 lapic.icr_lo = icr_lo;
918 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
920 * target is a bitmask of destination cpus. Vector is any
921 * valid system INT vector. Delivery mode may be either
922 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
925 selected_apic_ipi(u_int target, int vector, int delivery_mode)
929 int n = bsfl(target);
931 single_apic_ipi(n, vector, delivery_mode);
937 * Timer code, in development...
938 * - suggested by rgrimes@gndrsh.aac.dev.com
941 get_apic_timer_frequency(void)
943 return(lapic_cputimer_intr.freq);
947 * Load a 'downcount time' in uSeconds.
950 set_apic_timer(int us)
955 * When we reach here, lapic timer's frequency
956 * must have been calculated as well as the
957 * divisor (lapic.dcr_timer is setup during the
958 * divisor calculation).
960 KKASSERT(lapic_cputimer_intr.freq != 0 &&
961 lapic_timer_divisor_idx >= 0);
963 count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000;
964 lapic_timer_oneshot(count);
969 * Read remaining time in timer.
972 read_apic_timer(void)
975 /** XXX FIXME: we need to return the actual remaining time,
976 * for now we just return the remaining count.
979 return lapic.ccr_timer;
985 * Spin-style delay, set delay time in uS, spin till it drains.
990 set_apic_timer(count);
991 while (read_apic_timer())
996 lapic_map(vm_offset_t lapic_addr)
998 /* Local apic is mapped on last page */
999 SMPpt[NPTEPG - 1] = (pt_entry_t)(PG_V | PG_RW | PG_N |
1000 pmap_get_pgeflag() | (lapic_addr & PG_FRAME));
1002 kprintf("lapic: at %p\n", (void *)lapic_addr);
1005 static TAILQ_HEAD(, lapic_enumerator) lapic_enumerators =
1006 TAILQ_HEAD_INITIALIZER(lapic_enumerators);
1011 struct lapic_enumerator *e;
1014 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
1015 error = e->lapic_probe(e);
1020 panic("can't config lapic\n");
1022 e->lapic_enumerate(e);
1026 lapic_enumerator_register(struct lapic_enumerator *ne)
1028 struct lapic_enumerator *e;
1030 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
1031 if (e->lapic_prio < ne->lapic_prio) {
1032 TAILQ_INSERT_BEFORE(e, ne, lapic_link);
1036 TAILQ_INSERT_TAIL(&lapic_enumerators, ne, lapic_link);