2 * Copyright (c) 1997, Stefan Esser <se@kfreebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@kfreebsd.org>
4 * Copyright (c) 2000, BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/pci/pci.c,v 1.355.2.9.2.1 2009/04/15 03:14:26 kensmith Exp $
32 #include "opt_compat_oldpci.h"
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/linker.h>
39 #include <sys/fcntl.h>
41 #include <sys/kernel.h>
42 #include <sys/queue.h>
43 #include <sys/sysctl.h>
44 #include <sys/endian.h>
47 #include <machine/smp.h>
52 #include <vm/vm_extern.h>
56 #include <sys/device.h>
58 #include <sys/pciio.h>
59 #include <bus/pci/pcireg.h>
60 #include <bus/pci/pcivar.h>
61 #include <bus/pci/pci_private.h>
67 #include <contrib/dev/acpica/acpi.h>
70 #define ACPI_PWR_FOR_SLEEP(x, y, z)
73 extern struct dev_ops pcic_ops; /* XXX */
75 typedef void (*pci_read_cap_t)(device_t, int, int, pcicfgregs *);
77 static uint32_t pci_mapbase(unsigned mapreg);
78 static const char *pci_maptype(unsigned mapreg);
79 static int pci_mapsize(unsigned testval);
80 static int pci_maprange(unsigned mapreg);
81 static void pci_fixancient(pcicfgregs *cfg);
83 static int pci_porten(device_t pcib, int b, int s, int f);
84 static int pci_memen(device_t pcib, int b, int s, int f);
85 static void pci_assign_interrupt(device_t bus, device_t dev,
87 static int pci_add_map(device_t pcib, device_t bus, device_t dev,
88 int b, int s, int f, int reg,
89 struct resource_list *rl, int force, int prefetch);
90 static int pci_probe(device_t dev);
91 static int pci_attach(device_t dev);
92 static void pci_child_detached(device_t, device_t);
93 static void pci_load_vendor_data(void);
94 static int pci_describe_parse_line(char **ptr, int *vendor,
95 int *device, char **desc);
96 static char *pci_describe_device(device_t dev);
97 static int pci_modevent(module_t mod, int what, void *arg);
98 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
100 static void pci_read_capabilities(device_t pcib, pcicfgregs *cfg);
101 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
102 int reg, uint32_t *data);
104 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
105 int reg, uint32_t data);
107 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
108 static void pci_disable_msi(device_t dev);
109 static void pci_enable_msi(device_t dev, uint64_t address,
111 static void pci_enable_msix(device_t dev, u_int index,
112 uint64_t address, uint32_t data);
113 static void pci_mask_msix(device_t dev, u_int index);
114 static void pci_unmask_msix(device_t dev, u_int index);
115 static int pci_msi_blacklisted(void);
116 static void pci_resume_msi(device_t dev);
117 static void pci_resume_msix(device_t dev);
118 static int pcie_slotimpl(const pcicfgregs *);
119 static void pci_print_verbose_expr(const pcicfgregs *);
121 static void pci_read_cap_pmgt(device_t, int, int, pcicfgregs *);
122 static void pci_read_cap_ht(device_t, int, int, pcicfgregs *);
123 static void pci_read_cap_msi(device_t, int, int, pcicfgregs *);
124 static void pci_read_cap_msix(device_t, int, int, pcicfgregs *);
125 static void pci_read_cap_vpd(device_t, int, int, pcicfgregs *);
126 static void pci_read_cap_subvendor(device_t, int, int,
128 static void pci_read_cap_pcix(device_t, int, int, pcicfgregs *);
129 static void pci_read_cap_express(device_t, int, int, pcicfgregs *);
131 static device_method_t pci_methods[] = {
132 /* Device interface */
133 DEVMETHOD(device_probe, pci_probe),
134 DEVMETHOD(device_attach, pci_attach),
135 DEVMETHOD(device_detach, bus_generic_detach),
136 DEVMETHOD(device_shutdown, bus_generic_shutdown),
137 DEVMETHOD(device_suspend, pci_suspend),
138 DEVMETHOD(device_resume, pci_resume),
141 DEVMETHOD(bus_print_child, pci_print_child),
142 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
143 DEVMETHOD(bus_read_ivar, pci_read_ivar),
144 DEVMETHOD(bus_write_ivar, pci_write_ivar),
145 DEVMETHOD(bus_driver_added, pci_driver_added),
146 DEVMETHOD(bus_child_detached, pci_child_detached),
147 DEVMETHOD(bus_setup_intr, pci_setup_intr),
148 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
150 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
151 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
152 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
153 DEVMETHOD(bus_delete_resource, pci_delete_resource),
154 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
155 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
156 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
157 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
158 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
159 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
162 DEVMETHOD(pci_read_config, pci_read_config_method),
163 DEVMETHOD(pci_write_config, pci_write_config_method),
164 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
165 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
166 DEVMETHOD(pci_enable_io, pci_enable_io_method),
167 DEVMETHOD(pci_disable_io, pci_disable_io_method),
168 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
169 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
170 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
171 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
172 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
173 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
174 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
175 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method),
176 DEVMETHOD(pci_remap_msix, pci_remap_msix_method),
177 DEVMETHOD(pci_release_msi, pci_release_msi_method),
178 DEVMETHOD(pci_msi_count, pci_msi_count_method),
179 DEVMETHOD(pci_msix_count, pci_msix_count_method),
184 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0);
186 static devclass_t pci_devclass;
187 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
188 MODULE_VERSION(pci, 1);
190 static char *pci_vendordata;
191 static size_t pci_vendordata_size;
194 static const struct pci_read_cap {
196 pci_read_cap_t read_cap;
197 } pci_read_caps[] = {
198 { PCIY_PMG, pci_read_cap_pmgt },
199 { PCIY_HT, pci_read_cap_ht },
200 { PCIY_MSI, pci_read_cap_msi },
201 { PCIY_MSIX, pci_read_cap_msix },
202 { PCIY_VPD, pci_read_cap_vpd },
203 { PCIY_SUBVENDOR, pci_read_cap_subvendor },
204 { PCIY_PCIX, pci_read_cap_pcix },
205 { PCIY_EXPRESS, pci_read_cap_express },
206 { 0, NULL } /* required last entry */
210 uint32_t devid; /* Vendor/device of the card */
212 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
213 #define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */
218 struct pci_quirk pci_quirks[] = {
219 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
220 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
221 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
222 /* As does the Serverworks OSB4 (the SMBus mapping register) */
223 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
226 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
227 * or the CMIC-SL (AKA ServerWorks GC_LE).
229 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
230 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
233 * MSI doesn't work on earlier Intel chipsets including
234 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
236 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
237 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
238 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
239 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
240 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
241 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
242 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
245 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
248 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
253 /* map register information */
254 #define PCI_MAPMEM 0x01 /* memory map */
255 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
256 #define PCI_MAPPORT 0x04 /* port map */
258 struct devlist pci_devq;
259 uint32_t pci_generation;
260 uint32_t pci_numdevs = 0;
261 static int pcie_chipset, pcix_chipset;
264 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
266 static int pci_enable_io_modes = 1;
267 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
268 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
269 &pci_enable_io_modes, 1,
270 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
271 enable these bits correctly. We'd like to do this all the time, but there\n\
272 are some peripherals that this causes problems with.");
274 static int pci_do_power_nodriver = 0;
275 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
276 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
277 &pci_do_power_nodriver, 0,
278 "Place a function into D3 state when no driver attaches to it. 0 means\n\
279 disable. 1 means conservatively place devices into D3 state. 2 means\n\
280 aggressively place devices into D3 state. 3 means put absolutely everything\n\
283 static int pci_do_power_resume = 1;
284 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
285 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
286 &pci_do_power_resume, 1,
287 "Transition from D3 -> D0 on resume.");
289 static int pci_do_msi = 1;
290 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
291 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
292 "Enable support for MSI interrupts");
294 static int pci_do_msix = 1;
295 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
296 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
297 "Enable support for MSI-X interrupts");
299 static int pci_honor_msi_blacklist = 1;
300 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
301 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
302 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI");
304 /* Find a device_t by bus/slot/function in domain 0 */
307 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
310 return (pci_find_dbsf(0, bus, slot, func));
313 /* Find a device_t by domain/bus/slot/function */
316 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
318 struct pci_devinfo *dinfo;
320 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
321 if ((dinfo->cfg.domain == domain) &&
322 (dinfo->cfg.bus == bus) &&
323 (dinfo->cfg.slot == slot) &&
324 (dinfo->cfg.func == func)) {
325 return (dinfo->cfg.dev);
332 /* Find a device_t by vendor/device ID */
335 pci_find_device(uint16_t vendor, uint16_t device)
337 struct pci_devinfo *dinfo;
339 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
340 if ((dinfo->cfg.vendor == vendor) &&
341 (dinfo->cfg.device == device)) {
342 return (dinfo->cfg.dev);
349 /* return base address of memory or port map */
352 pci_mapbase(uint32_t mapreg)
355 if (PCI_BAR_MEM(mapreg))
356 return (mapreg & PCIM_BAR_MEM_BASE);
358 return (mapreg & PCIM_BAR_IO_BASE);
361 /* return map type of memory or port map */
364 pci_maptype(unsigned mapreg)
367 if (PCI_BAR_IO(mapreg))
369 if (mapreg & PCIM_BAR_MEM_PREFETCH)
370 return ("Prefetchable Memory");
374 /* return log2 of map size decoded for memory or port map */
377 pci_mapsize(uint32_t testval)
381 testval = pci_mapbase(testval);
384 while ((testval & 1) == 0)
393 /* return log2 of address range supported by map register */
396 pci_maprange(unsigned mapreg)
400 if (PCI_BAR_IO(mapreg))
403 switch (mapreg & PCIM_BAR_MEM_TYPE) {
404 case PCIM_BAR_MEM_32:
407 case PCIM_BAR_MEM_1MB:
410 case PCIM_BAR_MEM_64:
417 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
420 pci_fixancient(pcicfgregs *cfg)
422 if (cfg->hdrtype != 0)
425 /* PCI to PCI bridges use header type 1 */
426 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
430 /* extract header type specific config data */
433 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
435 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
436 switch (cfg->hdrtype) {
438 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
439 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
440 cfg->nummaps = PCI_MAXMAPS_0;
443 cfg->nummaps = PCI_MAXMAPS_1;
445 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
449 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
450 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
451 cfg->nummaps = PCI_MAXMAPS_2;
453 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
460 /* read configuration header into pcicfgregs structure */
462 pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
464 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
465 pcicfgregs *cfg = NULL;
466 struct pci_devinfo *devlist_entry;
467 struct devlist *devlist_head;
469 devlist_head = &pci_devq;
471 devlist_entry = NULL;
473 if (REG(PCIR_DEVVENDOR, 4) != -1) {
474 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
476 cfg = &devlist_entry->cfg;
482 cfg->vendor = REG(PCIR_VENDOR, 2);
483 cfg->device = REG(PCIR_DEVICE, 2);
484 cfg->cmdreg = REG(PCIR_COMMAND, 2);
485 cfg->statreg = REG(PCIR_STATUS, 2);
486 cfg->baseclass = REG(PCIR_CLASS, 1);
487 cfg->subclass = REG(PCIR_SUBCLASS, 1);
488 cfg->progif = REG(PCIR_PROGIF, 1);
489 cfg->revid = REG(PCIR_REVID, 1);
490 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
491 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
492 cfg->lattimer = REG(PCIR_LATTIMER, 1);
493 cfg->intpin = REG(PCIR_INTPIN, 1);
494 cfg->intline = REG(PCIR_INTLINE, 1);
498 * If using the APIC the intpin is probably wrong, since it
499 * is often setup by the BIOS with the PIC in mind.
501 if (cfg->intpin != 0) {
504 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
506 /* PCI specific entry found in MP table */
507 if (airq != cfg->intline) {
508 undirect_pci_irq(cfg->intline);
513 * PCI interrupts might be redirected to the
514 * ISA bus according to some MP tables. Use the
515 * same methods as used by the ISA devices
516 * devices to find the proper IOAPIC int pin.
518 airq = isa_apic_irq(cfg->intline);
519 if ((airq >= 0) && (airq != cfg->intline)) {
520 /* XXX: undirect_pci_irq() ? */
521 undirect_isa_irq(cfg->intline);
528 cfg->mingnt = REG(PCIR_MINGNT, 1);
529 cfg->maxlat = REG(PCIR_MAXLAT, 1);
531 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
532 cfg->hdrtype &= ~PCIM_MFDEV;
535 pci_hdrtypedata(pcib, b, s, f, cfg);
537 pci_read_capabilities(pcib, cfg);
539 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
541 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
542 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
543 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
544 devlist_entry->conf.pc_sel.pc_func = cfg->func;
545 devlist_entry->conf.pc_hdr = cfg->hdrtype;
547 devlist_entry->conf.pc_subvendor = cfg->subvendor;
548 devlist_entry->conf.pc_subdevice = cfg->subdevice;
549 devlist_entry->conf.pc_vendor = cfg->vendor;
550 devlist_entry->conf.pc_device = cfg->device;
552 devlist_entry->conf.pc_class = cfg->baseclass;
553 devlist_entry->conf.pc_subclass = cfg->subclass;
554 devlist_entry->conf.pc_progif = cfg->progif;
555 devlist_entry->conf.pc_revid = cfg->revid;
560 return (devlist_entry);
565 pci_fixup_nextptr(int *nextptr0)
567 int nextptr = *nextptr0;
569 /* "Next pointer" is only one byte */
570 KASSERT(nextptr <= 0xff, ("Illegal next pointer %d\n", nextptr));
574 * PCI local bus spec 3.0:
576 * "... The bottom two bits of all pointers are reserved
577 * and must be implemented as 00b although software must
578 * mask them to allow for future uses of these bits ..."
581 kprintf("Illegal PCI extended capability "
582 "offset, fixup 0x%02x -> 0x%02x\n",
583 nextptr, nextptr & ~0x3);
589 if (nextptr < 0x40) {
591 kprintf("Illegal PCI extended capability "
592 "offset 0x%02x", nextptr);
600 pci_read_cap_pmgt(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
603 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
605 struct pcicfg_pp *pp = &cfg->pp;
610 pp->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
611 pp->pp_status = ptr + PCIR_POWER_STATUS;
612 pp->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
614 if ((nextptr - ptr) > PCIR_POWER_DATA) {
617 * We should write to data_select and read back from
618 * data_scale to determine whether data register is
622 pp->pp_data = ptr + PCIR_POWER_DATA;
632 pci_read_cap_ht(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
635 #if defined(__i386__) || defined(__amd64__)
638 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
640 struct pcicfg_ht *ht = &cfg->ht;
644 /* Determine HT-specific capability type. */
645 val = REG(ptr + PCIR_HT_COMMAND, 2);
647 if ((val & PCIM_HTCMD_CAP_MASK) != PCIM_HTCAP_MSI_MAPPING)
650 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
651 /* Sanity check the mapping window. */
652 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 4);
654 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 4);
655 if (addr != MSI_INTEL_ADDR_BASE) {
656 device_printf(pcib, "HT Bridge at pci%d:%d:%d:%d "
657 "has non-default MSI window 0x%llx\n",
658 cfg->domain, cfg->bus, cfg->slot, cfg->func,
662 addr = MSI_INTEL_ADDR_BASE;
666 ht->ht_msictrl = val;
667 ht->ht_msiaddr = addr;
671 #endif /* __i386__ || __amd64__ */
676 pci_read_cap_msi(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
679 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
681 struct pcicfg_msi *msi = &cfg->msi;
683 msi->msi_location = ptr;
684 msi->msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
685 msi->msi_msgnum = 1 << ((msi->msi_ctrl & PCIM_MSICTRL_MMC_MASK) >> 1);
691 pci_read_cap_msix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
694 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
696 struct pcicfg_msix *msix = &cfg->msix;
699 msix->msix_location = ptr;
700 msix->msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
701 msix->msix_msgnum = (msix->msix_ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
703 val = REG(ptr + PCIR_MSIX_TABLE, 4);
704 msix->msix_table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
705 msix->msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
707 val = REG(ptr + PCIR_MSIX_PBA, 4);
708 msix->msix_pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
709 msix->msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
715 pci_read_cap_vpd(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
717 cfg->vpd.vpd_reg = ptr;
721 pci_read_cap_subvendor(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
724 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
726 /* Should always be true. */
727 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) {
730 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
731 cfg->subvendor = val & 0xffff;
732 cfg->subdevice = val >> 16;
739 pci_read_cap_pcix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
742 * Assume we have a PCI-X chipset if we have
743 * at least one PCI-PCI bridge with a PCI-X
744 * capability. Note that some systems with
745 * PCI-express or HT chipsets might match on
746 * this check as well.
748 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1)
751 cfg->pcix.pcix_ptr = ptr;
755 pcie_slotimpl(const pcicfgregs *cfg)
757 const struct pcicfg_expr *expr = &cfg->expr;
761 * Only version 1 can be parsed currently
763 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
767 * - Slot implemented bit is meaningful iff current port is
768 * root port or down stream port.
769 * - Testing for root port or down stream port is meanningful
770 * iff PCI configure has type 1 header.
773 if (cfg->hdrtype != 1)
776 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
777 if (port_type != PCIE_ROOT_PORT && port_type != PCIE_DOWN_STREAM_PORT)
780 if (!(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
787 pci_read_cap_express(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
790 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
792 struct pcicfg_expr *expr = &cfg->expr;
795 * Assume we have a PCI-express chipset if we have
796 * at least one PCI-express device.
800 expr->expr_ptr = ptr;
801 expr->expr_cap = REG(ptr + PCIER_CAPABILITY, 2);
804 * Only version 1 can be parsed currently
806 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
810 * Read slot capabilities. Slot capabilities exists iff
811 * current port's slot is implemented
813 if (pcie_slotimpl(cfg))
814 expr->expr_slotcap = REG(ptr + PCIER_SLOTCAP, 4);
820 pci_read_capabilities(device_t pcib, pcicfgregs *cfg)
822 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
823 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
828 if ((REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) == 0) {
829 /* No capabilities */
833 switch (cfg->hdrtype & PCIM_HDRTYPE) {
836 ptrptr = PCIR_CAP_PTR;
839 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
842 return; /* no capabilities support */
844 nextptr = REG(ptrptr, 1); /* sanity check? */
847 * Read capability entries.
849 while (pci_fixup_nextptr(&nextptr)) {
850 const struct pci_read_cap *rc;
853 /* Find the next entry */
854 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
856 /* Process this entry */
857 val = REG(ptr + PCICAP_ID, 1);
858 for (rc = pci_read_caps; rc->read_cap != NULL; ++rc) {
859 if (rc->cap == val) {
860 rc->read_cap(pcib, ptr, nextptr, cfg);
865 /* REG and WREG use carry through to next functions */
869 * PCI Vital Product Data
872 #define PCI_VPD_TIMEOUT 1000000
875 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
877 int count = PCI_VPD_TIMEOUT;
879 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
881 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
883 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
886 DELAY(1); /* limit looping */
888 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
895 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
897 int count = PCI_VPD_TIMEOUT;
899 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
901 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
902 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
903 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
906 DELAY(1); /* limit looping */
913 #undef PCI_VPD_TIMEOUT
915 struct vpd_readstate {
925 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
930 if (vrs->bytesinval == 0) {
931 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
933 vrs->val = le32toh(reg);
935 byte = vrs->val & 0xff;
938 vrs->val = vrs->val >> 8;
939 byte = vrs->val & 0xff;
949 pcie_slot_implemented(device_t dev)
951 struct pci_devinfo *dinfo = device_get_ivars(dev);
953 return pcie_slotimpl(&dinfo->cfg);
957 pcie_set_max_readrq(device_t dev, uint16_t rqsize)
962 rqsize &= PCIEM_DEVCTL_MAX_READRQ_MASK;
963 if (rqsize > PCIEM_DEVCTL_MAX_READRQ_4096) {
964 panic("%s: invalid max read request size 0x%02x\n",
965 device_get_nameunit(dev), rqsize);
968 expr_ptr = pci_get_pciecap_ptr(dev);
970 panic("%s: not PCIe device\n", device_get_nameunit(dev));
972 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
973 if ((val & PCIEM_DEVCTL_MAX_READRQ_MASK) != rqsize) {
975 device_printf(dev, "adjust device control 0x%04x", val);
977 val &= ~PCIEM_DEVCTL_MAX_READRQ_MASK;
979 pci_write_config(dev, expr_ptr + PCIER_DEVCTRL, val, 2);
982 kprintf(" -> 0x%04x\n", val);
987 pci_read_vpd(device_t pcib, pcicfgregs *cfg)
989 struct vpd_readstate vrs;
994 int alloc, off; /* alloc/off for RO/W arrays */
1000 /* init vpd reader */
1008 name = remain = i = 0; /* shut up stupid gcc */
1009 alloc = off = 0; /* shut up stupid gcc */
1010 dflen = 0; /* shut up stupid gcc */
1012 while (state >= 0) {
1013 if (vpd_nextbyte(&vrs, &byte)) {
1018 kprintf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
1019 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
1020 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
1023 case 0: /* item name */
1025 if (vpd_nextbyte(&vrs, &byte2)) {
1030 if (vpd_nextbyte(&vrs, &byte2)) {
1034 remain |= byte2 << 8;
1035 if (remain > (0x7f*4 - vrs.off)) {
1038 "pci%d:%d:%d:%d: invalid VPD data, remain %#x\n",
1039 cfg->domain, cfg->bus, cfg->slot,
1044 remain = byte & 0x7;
1045 name = (byte >> 3) & 0xf;
1048 case 0x2: /* String */
1049 cfg->vpd.vpd_ident = kmalloc(remain + 1,
1050 M_DEVBUF, M_WAITOK);
1057 case 0x10: /* VPD-R */
1060 cfg->vpd.vpd_ros = kmalloc(alloc *
1061 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
1065 case 0x11: /* VPD-W */
1068 cfg->vpd.vpd_w = kmalloc(alloc *
1069 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
1073 default: /* Invalid data, abort */
1079 case 1: /* Identifier String */
1080 cfg->vpd.vpd_ident[i++] = byte;
1083 cfg->vpd.vpd_ident[i] = '\0';
1088 case 2: /* VPD-R Keyword Header */
1090 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
1091 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
1092 M_DEVBUF, M_WAITOK | M_ZERO);
1094 cfg->vpd.vpd_ros[off].keyword[0] = byte;
1095 if (vpd_nextbyte(&vrs, &byte2)) {
1099 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
1100 if (vpd_nextbyte(&vrs, &byte2)) {
1106 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
1109 * if this happens, we can't trust the rest
1113 "pci%d:%d:%d:%d: bad keyword length: %d\n",
1114 cfg->domain, cfg->bus, cfg->slot,
1119 } else if (dflen == 0) {
1120 cfg->vpd.vpd_ros[off].value = kmalloc(1 *
1121 sizeof(*cfg->vpd.vpd_ros[off].value),
1122 M_DEVBUF, M_WAITOK);
1123 cfg->vpd.vpd_ros[off].value[0] = '\x00';
1125 cfg->vpd.vpd_ros[off].value = kmalloc(
1127 sizeof(*cfg->vpd.vpd_ros[off].value),
1128 M_DEVBUF, M_WAITOK);
1131 /* keep in sync w/ state 3's transistions */
1132 if (dflen == 0 && remain == 0)
1134 else if (dflen == 0)
1140 case 3: /* VPD-R Keyword Value */
1141 cfg->vpd.vpd_ros[off].value[i++] = byte;
1142 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
1143 "RV", 2) == 0 && cksumvalid == -1) {
1149 "pci%d:%d:%d:%d: bad VPD cksum, remain %hhu\n",
1150 cfg->domain, cfg->bus,
1151 cfg->slot, cfg->func,
1160 /* keep in sync w/ state 2's transistions */
1162 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
1163 if (dflen == 0 && remain == 0) {
1164 cfg->vpd.vpd_rocnt = off;
1165 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
1166 off * sizeof(*cfg->vpd.vpd_ros),
1167 M_DEVBUF, M_WAITOK | M_ZERO);
1169 } else if (dflen == 0)
1179 case 5: /* VPD-W Keyword Header */
1181 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
1182 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
1183 M_DEVBUF, M_WAITOK | M_ZERO);
1185 cfg->vpd.vpd_w[off].keyword[0] = byte;
1186 if (vpd_nextbyte(&vrs, &byte2)) {
1190 cfg->vpd.vpd_w[off].keyword[1] = byte2;
1191 if (vpd_nextbyte(&vrs, &byte2)) {
1195 cfg->vpd.vpd_w[off].len = dflen = byte2;
1196 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
1197 cfg->vpd.vpd_w[off].value = kmalloc((dflen + 1) *
1198 sizeof(*cfg->vpd.vpd_w[off].value),
1199 M_DEVBUF, M_WAITOK);
1202 /* keep in sync w/ state 6's transistions */
1203 if (dflen == 0 && remain == 0)
1205 else if (dflen == 0)
1211 case 6: /* VPD-W Keyword Value */
1212 cfg->vpd.vpd_w[off].value[i++] = byte;
1215 /* keep in sync w/ state 5's transistions */
1217 cfg->vpd.vpd_w[off++].value[i++] = '\0';
1218 if (dflen == 0 && remain == 0) {
1219 cfg->vpd.vpd_wcnt = off;
1220 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
1221 off * sizeof(*cfg->vpd.vpd_w),
1222 M_DEVBUF, M_WAITOK | M_ZERO);
1224 } else if (dflen == 0)
1229 kprintf("pci%d:%d:%d:%d: invalid state: %d\n",
1230 cfg->domain, cfg->bus, cfg->slot, cfg->func,
1237 if (cksumvalid == 0 || state < -1) {
1238 /* read-only data bad, clean up */
1239 if (cfg->vpd.vpd_ros != NULL) {
1240 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
1241 kfree(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
1242 kfree(cfg->vpd.vpd_ros, M_DEVBUF);
1243 cfg->vpd.vpd_ros = NULL;
1247 /* I/O error, clean up */
1248 kprintf("pci%d:%d:%d:%d: failed to read VPD data.\n",
1249 cfg->domain, cfg->bus, cfg->slot, cfg->func);
1250 if (cfg->vpd.vpd_ident != NULL) {
1251 kfree(cfg->vpd.vpd_ident, M_DEVBUF);
1252 cfg->vpd.vpd_ident = NULL;
1254 if (cfg->vpd.vpd_w != NULL) {
1255 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1256 kfree(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1257 kfree(cfg->vpd.vpd_w, M_DEVBUF);
1258 cfg->vpd.vpd_w = NULL;
1261 cfg->vpd.vpd_cached = 1;
1267 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1269 struct pci_devinfo *dinfo = device_get_ivars(child);
1270 pcicfgregs *cfg = &dinfo->cfg;
1272 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1273 pci_read_vpd(device_get_parent(dev), cfg);
1275 *identptr = cfg->vpd.vpd_ident;
1277 if (*identptr == NULL)
1284 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1287 struct pci_devinfo *dinfo = device_get_ivars(child);
1288 pcicfgregs *cfg = &dinfo->cfg;
1291 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1292 pci_read_vpd(device_get_parent(dev), cfg);
1294 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1295 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1296 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1297 *vptr = cfg->vpd.vpd_ros[i].value;
1300 if (i != cfg->vpd.vpd_rocnt)
1308 * Return the offset in configuration space of the requested extended
1309 * capability entry or 0 if the specified capability was not found.
1312 pci_find_extcap_method(device_t dev, device_t child, int capability,
1315 struct pci_devinfo *dinfo = device_get_ivars(child);
1316 pcicfgregs *cfg = &dinfo->cfg;
1321 * Check the CAP_LIST bit of the PCI status register first.
1323 status = pci_read_config(child, PCIR_STATUS, 2);
1324 if (!(status & PCIM_STATUS_CAPPRESENT))
1328 * Determine the start pointer of the capabilities list.
1330 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1336 ptr = PCIR_CAP_PTR_2;
1340 return (ENXIO); /* no extended capabilities support */
1342 ptr = pci_read_config(child, ptr, 1);
1345 * Traverse the capabilities list.
1348 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1353 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1360 * Support for MSI-X message interrupts.
1363 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
1365 struct pci_devinfo *dinfo = device_get_ivars(dev);
1366 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1369 KASSERT(msix->msix_table_len > index, ("bogus index"));
1370 offset = msix->msix_table_offset + index * 16;
1371 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1372 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1373 bus_write_4(msix->msix_table_res, offset + 8, data);
1375 /* Enable MSI -> HT mapping. */
1376 pci_ht_map_msi(dev, address);
1380 pci_mask_msix(device_t dev, u_int index)
1382 struct pci_devinfo *dinfo = device_get_ivars(dev);
1383 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1384 uint32_t offset, val;
1386 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1387 offset = msix->msix_table_offset + index * 16 + 12;
1388 val = bus_read_4(msix->msix_table_res, offset);
1389 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1390 val |= PCIM_MSIX_VCTRL_MASK;
1391 bus_write_4(msix->msix_table_res, offset, val);
1396 pci_unmask_msix(device_t dev, u_int index)
1398 struct pci_devinfo *dinfo = device_get_ivars(dev);
1399 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1400 uint32_t offset, val;
1402 KASSERT(msix->msix_table_len > index, ("bogus index"));
1403 offset = msix->msix_table_offset + index * 16 + 12;
1404 val = bus_read_4(msix->msix_table_res, offset);
1405 if (val & PCIM_MSIX_VCTRL_MASK) {
1406 val &= ~PCIM_MSIX_VCTRL_MASK;
1407 bus_write_4(msix->msix_table_res, offset, val);
1412 pci_pending_msix(device_t dev, u_int index)
1414 struct pci_devinfo *dinfo = device_get_ivars(dev);
1415 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1416 uint32_t offset, bit;
1418 KASSERT(msix->msix_table_len > index, ("bogus index"));
1419 offset = msix->msix_pba_offset + (index / 32) * 4;
1420 bit = 1 << index % 32;
1421 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1425 * Restore MSI-X registers and table during resume. If MSI-X is
1426 * enabled then walk the virtual table to restore the actual MSI-X
1430 pci_resume_msix(device_t dev)
1432 struct pci_devinfo *dinfo = device_get_ivars(dev);
1433 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1434 struct msix_table_entry *mte;
1435 struct msix_vector *mv;
1438 if (msix->msix_alloc > 0) {
1439 /* First, mask all vectors. */
1440 for (i = 0; i < msix->msix_msgnum; i++)
1441 pci_mask_msix(dev, i);
1443 /* Second, program any messages with at least one handler. */
1444 for (i = 0; i < msix->msix_table_len; i++) {
1445 mte = &msix->msix_table[i];
1446 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1448 mv = &msix->msix_vectors[mte->mte_vector - 1];
1449 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data);
1450 pci_unmask_msix(dev, i);
1453 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1454 msix->msix_ctrl, 2);
1458 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1459 * returned in *count. After this function returns, each message will be
1460 * available to the driver as SYS_RES_IRQ resources starting at rid 1.
1463 pci_alloc_msix_method(device_t dev, device_t child, int *count)
1465 struct pci_devinfo *dinfo = device_get_ivars(child);
1466 pcicfgregs *cfg = &dinfo->cfg;
1467 struct resource_list_entry *rle;
1468 int actual, error, i, irq, max;
1470 /* Don't let count == 0 get us into trouble. */
1474 /* If rid 0 is allocated, then fail. */
1475 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1476 if (rle != NULL && rle->res != NULL)
1479 /* Already have allocated messages? */
1480 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1483 /* If MSI is blacklisted for this system, fail. */
1484 if (pci_msi_blacklisted())
1487 /* MSI-X capability present? */
1488 if (cfg->msix.msix_location == 0 || !pci_do_msix)
1491 /* Make sure the appropriate BARs are mapped. */
1492 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1493 cfg->msix.msix_table_bar);
1494 if (rle == NULL || rle->res == NULL ||
1495 !(rman_get_flags(rle->res) & RF_ACTIVE))
1497 cfg->msix.msix_table_res = rle->res;
1498 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1499 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1500 cfg->msix.msix_pba_bar);
1501 if (rle == NULL || rle->res == NULL ||
1502 !(rman_get_flags(rle->res) & RF_ACTIVE))
1505 cfg->msix.msix_pba_res = rle->res;
1508 device_printf(child,
1509 "attempting to allocate %d MSI-X vectors (%d supported)\n",
1510 *count, cfg->msix.msix_msgnum);
1511 max = min(*count, cfg->msix.msix_msgnum);
1512 for (i = 0; i < max; i++) {
1513 /* Allocate a message. */
1514 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq);
1517 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1523 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
1525 device_printf(child, "using IRQ %lu for MSI-X\n",
1531 * Be fancy and try to print contiguous runs of
1532 * IRQ values as ranges. 'irq' is the previous IRQ.
1533 * 'run' is true if we are in a range.
1535 device_printf(child, "using IRQs %lu", rle->start);
1538 for (i = 1; i < actual; i++) {
1539 rle = resource_list_find(&dinfo->resources,
1540 SYS_RES_IRQ, i + 1);
1542 /* Still in a run? */
1543 if (rle->start == irq + 1) {
1549 /* Finish previous range. */
1551 kprintf("-%d", irq);
1555 /* Start new range. */
1556 kprintf(",%lu", rle->start);
1560 /* Unfinished range? */
1562 kprintf("-%d", irq);
1563 kprintf(" for MSI-X\n");
1567 /* Mask all vectors. */
1568 for (i = 0; i < cfg->msix.msix_msgnum; i++)
1569 pci_mask_msix(child, i);
1571 /* Allocate and initialize vector data and virtual table. */
1572 cfg->msix.msix_vectors = kmalloc(sizeof(struct msix_vector) * actual,
1573 M_DEVBUF, M_WAITOK | M_ZERO);
1574 cfg->msix.msix_table = kmalloc(sizeof(struct msix_table_entry) * actual,
1575 M_DEVBUF, M_WAITOK | M_ZERO);
1576 for (i = 0; i < actual; i++) {
1577 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1578 cfg->msix.msix_vectors[i].mv_irq = rle->start;
1579 cfg->msix.msix_table[i].mte_vector = i + 1;
1582 /* Update control register to enable MSI-X. */
1583 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1584 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
1585 cfg->msix.msix_ctrl, 2);
1587 /* Update counts of alloc'd messages. */
1588 cfg->msix.msix_alloc = actual;
1589 cfg->msix.msix_table_len = actual;
1595 * By default, pci_alloc_msix() will assign the allocated IRQ
1596 * resources consecutively to the first N messages in the MSI-X table.
1597 * However, device drivers may want to use different layouts if they
1598 * either receive fewer messages than they asked for, or they wish to
1599 * populate the MSI-X table sparsely. This method allows the driver
1600 * to specify what layout it wants. It must be called after a
1601 * successful pci_alloc_msix() but before any of the associated
1602 * SYS_RES_IRQ resources are allocated via bus_alloc_resource().
1604 * The 'vectors' array contains 'count' message vectors. The array
1605 * maps directly to the MSI-X table in that index 0 in the array
1606 * specifies the vector for the first message in the MSI-X table, etc.
1607 * The vector value in each array index can either be 0 to indicate
1608 * that no vector should be assigned to a message slot, or it can be a
1609 * number from 1 to N (where N is the count returned from a
1610 * succcessful call to pci_alloc_msix()) to indicate which message
1611 * vector (IRQ) to be used for the corresponding message.
1613 * On successful return, each message with a non-zero vector will have
1614 * an associated SYS_RES_IRQ whose rid is equal to the array index +
1615 * 1. Additionally, if any of the IRQs allocated via the previous
1616 * call to pci_alloc_msix() are not used in the mapping, those IRQs
1617 * will be kfreed back to the system automatically.
1619 * For example, suppose a driver has a MSI-X table with 6 messages and
1620 * asks for 6 messages, but pci_alloc_msix() only returns a count of
1621 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and
1622 * C. After the call to pci_alloc_msix(), the device will be setup to
1623 * have an MSI-X table of ABC--- (where - means no vector assigned).
1624 * If the driver ten passes a vector array of { 1, 0, 1, 2, 0, 2 },
1625 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
1626 * be kfreed back to the system. This device will also have valid
1627 * SYS_RES_IRQ rids of 1, 3, 4, and 6.
1629 * In any case, the SYS_RES_IRQ rid X will always map to the message
1630 * at MSI-X table index X - 1 and will only be valid if a vector is
1631 * assigned to that table entry.
1634 pci_remap_msix_method(device_t dev, device_t child, int count,
1635 const u_int *vectors)
1637 struct pci_devinfo *dinfo = device_get_ivars(child);
1638 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1639 struct resource_list_entry *rle;
1640 int i, irq, j, *used;
1643 * Have to have at least one message in the table but the
1644 * table can't be bigger than the actual MSI-X table in the
1647 if (count == 0 || count > msix->msix_msgnum)
1650 /* Sanity check the vectors. */
1651 for (i = 0; i < count; i++)
1652 if (vectors[i] > msix->msix_alloc)
1656 * Make sure there aren't any holes in the vectors to be used.
1657 * It's a big pain to support it, and it doesn't really make
1658 * sense anyway. Also, at least one vector must be used.
1660 used = kmalloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK |
1662 for (i = 0; i < count; i++)
1663 if (vectors[i] != 0)
1664 used[vectors[i] - 1] = 1;
1665 for (i = 0; i < msix->msix_alloc - 1; i++)
1666 if (used[i] == 0 && used[i + 1] == 1) {
1667 kfree(used, M_DEVBUF);
1671 kfree(used, M_DEVBUF);
1675 /* Make sure none of the resources are allocated. */
1676 for (i = 0; i < msix->msix_table_len; i++) {
1677 if (msix->msix_table[i].mte_vector == 0)
1679 if (msix->msix_table[i].mte_handlers > 0)
1681 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1682 KASSERT(rle != NULL, ("missing resource"));
1683 if (rle->res != NULL)
1687 /* Free the existing resource list entries. */
1688 for (i = 0; i < msix->msix_table_len; i++) {
1689 if (msix->msix_table[i].mte_vector == 0)
1691 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1695 * Build the new virtual table keeping track of which vectors are
1698 kfree(msix->msix_table, M_DEVBUF);
1699 msix->msix_table = kmalloc(sizeof(struct msix_table_entry) * count,
1700 M_DEVBUF, M_WAITOK | M_ZERO);
1701 for (i = 0; i < count; i++)
1702 msix->msix_table[i].mte_vector = vectors[i];
1703 msix->msix_table_len = count;
1705 /* Free any unused IRQs and resize the vectors array if necessary. */
1706 j = msix->msix_alloc - 1;
1708 struct msix_vector *vec;
1710 while (used[j] == 0) {
1711 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1712 msix->msix_vectors[j].mv_irq);
1715 vec = kmalloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF,
1717 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) *
1719 kfree(msix->msix_vectors, M_DEVBUF);
1720 msix->msix_vectors = vec;
1721 msix->msix_alloc = j + 1;
1723 kfree(used, M_DEVBUF);
1725 /* Map the IRQs onto the rids. */
1726 for (i = 0; i < count; i++) {
1727 if (vectors[i] == 0)
1729 irq = msix->msix_vectors[vectors[i]].mv_irq;
1730 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1735 device_printf(child, "Remapped MSI-X IRQs as: ");
1736 for (i = 0; i < count; i++) {
1739 if (vectors[i] == 0)
1743 msix->msix_vectors[vectors[i]].mv_irq);
1752 pci_release_msix(device_t dev, device_t child)
1754 struct pci_devinfo *dinfo = device_get_ivars(child);
1755 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1756 struct resource_list_entry *rle;
1759 /* Do we have any messages to release? */
1760 if (msix->msix_alloc == 0)
1763 /* Make sure none of the resources are allocated. */
1764 for (i = 0; i < msix->msix_table_len; i++) {
1765 if (msix->msix_table[i].mte_vector == 0)
1767 if (msix->msix_table[i].mte_handlers > 0)
1769 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1770 KASSERT(rle != NULL, ("missing resource"));
1771 if (rle->res != NULL)
1775 /* Update control register to disable MSI-X. */
1776 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1777 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
1778 msix->msix_ctrl, 2);
1780 /* Free the resource list entries. */
1781 for (i = 0; i < msix->msix_table_len; i++) {
1782 if (msix->msix_table[i].mte_vector == 0)
1784 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1786 kfree(msix->msix_table, M_DEVBUF);
1787 msix->msix_table_len = 0;
1789 /* Release the IRQs. */
1790 for (i = 0; i < msix->msix_alloc; i++)
1791 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1792 msix->msix_vectors[i].mv_irq);
1793 kfree(msix->msix_vectors, M_DEVBUF);
1794 msix->msix_alloc = 0;
1799 * Return the max supported MSI-X messages this device supports.
1800 * Basically, assuming the MD code can alloc messages, this function
1801 * should return the maximum value that pci_alloc_msix() can return.
1802 * Thus, it is subject to the tunables, etc.
1805 pci_msix_count_method(device_t dev, device_t child)
1807 struct pci_devinfo *dinfo = device_get_ivars(child);
1808 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1810 if (pci_do_msix && msix->msix_location != 0)
1811 return (msix->msix_msgnum);
1816 * HyperTransport MSI mapping control
1819 pci_ht_map_msi(device_t dev, uint64_t addr)
1821 struct pci_devinfo *dinfo = device_get_ivars(dev);
1822 struct pcicfg_ht *ht = &dinfo->cfg.ht;
1827 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
1828 ht->ht_msiaddr >> 20 == addr >> 20) {
1829 /* Enable MSI -> HT mapping. */
1830 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1831 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1835 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) {
1836 /* Disable MSI -> HT mapping. */
1837 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
1838 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1844 * Support for MSI message signalled interrupts.
1847 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
1849 struct pci_devinfo *dinfo = device_get_ivars(dev);
1850 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1852 /* Write data and address values. */
1853 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1854 address & 0xffffffff, 4);
1855 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1856 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
1858 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
1861 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
1864 /* Enable MSI in the control register. */
1865 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
1866 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1869 /* Enable MSI -> HT mapping. */
1870 pci_ht_map_msi(dev, address);
1874 pci_disable_msi(device_t dev)
1876 struct pci_devinfo *dinfo = device_get_ivars(dev);
1877 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1879 /* Disable MSI -> HT mapping. */
1880 pci_ht_map_msi(dev, 0);
1882 /* Disable MSI in the control register. */
1883 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
1884 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1889 * Restore MSI registers during resume. If MSI is enabled then
1890 * restore the data and address registers in addition to the control
1894 pci_resume_msi(device_t dev)
1896 struct pci_devinfo *dinfo = device_get_ivars(dev);
1897 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1901 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
1902 address = msi->msi_addr;
1903 data = msi->msi_data;
1904 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1905 address & 0xffffffff, 4);
1906 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1907 pci_write_config(dev, msi->msi_location +
1908 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
1909 pci_write_config(dev, msi->msi_location +
1910 PCIR_MSI_DATA_64BIT, data, 2);
1912 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
1915 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1920 pci_remap_msi_irq(device_t dev, u_int irq)
1922 struct pci_devinfo *dinfo = device_get_ivars(dev);
1923 pcicfgregs *cfg = &dinfo->cfg;
1924 struct resource_list_entry *rle;
1925 struct msix_table_entry *mte;
1926 struct msix_vector *mv;
1932 bus = device_get_parent(dev);
1935 * Handle MSI first. We try to find this IRQ among our list
1936 * of MSI IRQs. If we find it, we request updated address and
1937 * data registers and apply the results.
1939 if (cfg->msi.msi_alloc > 0) {
1941 /* If we don't have any active handlers, nothing to do. */
1942 if (cfg->msi.msi_handlers == 0)
1944 for (i = 0; i < cfg->msi.msi_alloc; i++) {
1945 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
1947 if (rle->start == irq) {
1948 error = PCIB_MAP_MSI(device_get_parent(bus),
1949 dev, irq, &addr, &data);
1952 pci_disable_msi(dev);
1953 dinfo->cfg.msi.msi_addr = addr;
1954 dinfo->cfg.msi.msi_data = data;
1955 pci_enable_msi(dev, addr, data);
1963 * For MSI-X, we check to see if we have this IRQ. If we do,
1964 * we request the updated mapping info. If that works, we go
1965 * through all the slots that use this IRQ and update them.
1967 if (cfg->msix.msix_alloc > 0) {
1968 for (i = 0; i < cfg->msix.msix_alloc; i++) {
1969 mv = &cfg->msix.msix_vectors[i];
1970 if (mv->mv_irq == irq) {
1971 error = PCIB_MAP_MSI(device_get_parent(bus),
1972 dev, irq, &addr, &data);
1975 mv->mv_address = addr;
1977 for (j = 0; j < cfg->msix.msix_table_len; j++) {
1978 mte = &cfg->msix.msix_table[j];
1979 if (mte->mte_vector != i + 1)
1981 if (mte->mte_handlers == 0)
1983 pci_mask_msix(dev, j);
1984 pci_enable_msix(dev, j, addr, data);
1985 pci_unmask_msix(dev, j);
1996 * Returns true if the specified device is blacklisted because MSI
2000 pci_msi_device_blacklisted(device_t dev)
2002 struct pci_quirk *q;
2004 if (!pci_honor_msi_blacklist)
2007 for (q = &pci_quirks[0]; q->devid; q++) {
2008 if (q->devid == pci_get_devid(dev) &&
2009 q->type == PCI_QUIRK_DISABLE_MSI)
2016 * Determine if MSI is blacklisted globally on this sytem. Currently,
2017 * we just check for blacklisted chipsets as represented by the
2018 * host-PCI bridge at device 0:0:0. In the future, it may become
2019 * necessary to check other system attributes, such as the kenv values
2020 * that give the motherboard manufacturer and model number.
2023 pci_msi_blacklisted(void)
2027 if (!pci_honor_msi_blacklist)
2030 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
2031 if (!(pcie_chipset || pcix_chipset))
2034 dev = pci_find_bsf(0, 0, 0);
2036 return (pci_msi_device_blacklisted(dev));
2041 * Attempt to allocate *count MSI messages. The actual number allocated is
2042 * returned in *count. After this function returns, each message will be
2043 * available to the driver as SYS_RES_IRQ resources starting at a rid 1.
2046 pci_alloc_msi_method(device_t dev, device_t child, int *count)
2048 struct pci_devinfo *dinfo = device_get_ivars(child);
2049 pcicfgregs *cfg = &dinfo->cfg;
2050 struct resource_list_entry *rle;
2051 int actual, error, i, irqs[32];
2054 /* Don't let count == 0 get us into trouble. */
2058 /* If rid 0 is allocated, then fail. */
2059 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
2060 if (rle != NULL && rle->res != NULL)
2063 /* Already have allocated messages? */
2064 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
2067 /* If MSI is blacklisted for this system, fail. */
2068 if (pci_msi_blacklisted())
2071 /* MSI capability present? */
2072 if (cfg->msi.msi_location == 0 || !pci_do_msi)
2076 device_printf(child,
2077 "attempting to allocate %d MSI vectors (%d supported)\n",
2078 *count, cfg->msi.msi_msgnum);
2080 /* Don't ask for more than the device supports. */
2081 actual = min(*count, cfg->msi.msi_msgnum);
2083 /* Don't ask for more than 32 messages. */
2084 actual = min(actual, 32);
2086 /* MSI requires power of 2 number of messages. */
2087 if (!powerof2(actual))
2091 /* Try to allocate N messages. */
2092 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
2093 cfg->msi.msi_msgnum, irqs);
2104 * We now have N actual messages mapped onto SYS_RES_IRQ
2105 * resources in the irqs[] array, so add new resources
2106 * starting at rid 1.
2108 for (i = 0; i < actual; i++)
2109 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
2110 irqs[i], irqs[i], 1);
2114 device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
2119 * Be fancy and try to print contiguous runs
2120 * of IRQ values as ranges. 'run' is true if
2121 * we are in a range.
2123 device_printf(child, "using IRQs %d", irqs[0]);
2125 for (i = 1; i < actual; i++) {
2127 /* Still in a run? */
2128 if (irqs[i] == irqs[i - 1] + 1) {
2133 /* Finish previous range. */
2135 kprintf("-%d", irqs[i - 1]);
2139 /* Start new range. */
2140 kprintf(",%d", irqs[i]);
2143 /* Unfinished range? */
2145 kprintf("-%d", irqs[actual - 1]);
2146 kprintf(" for MSI\n");
2150 /* Update control register with actual count. */
2151 ctrl = cfg->msi.msi_ctrl;
2152 ctrl &= ~PCIM_MSICTRL_MME_MASK;
2153 ctrl |= (ffs(actual) - 1) << 4;
2154 cfg->msi.msi_ctrl = ctrl;
2155 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
2157 /* Update counts of alloc'd messages. */
2158 cfg->msi.msi_alloc = actual;
2159 cfg->msi.msi_handlers = 0;
2164 /* Release the MSI messages associated with this device. */
2166 pci_release_msi_method(device_t dev, device_t child)
2168 struct pci_devinfo *dinfo = device_get_ivars(child);
2169 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2170 struct resource_list_entry *rle;
2171 int error, i, irqs[32];
2173 /* Try MSI-X first. */
2174 error = pci_release_msix(dev, child);
2175 if (error != ENODEV)
2178 /* Do we have any messages to release? */
2179 if (msi->msi_alloc == 0)
2181 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
2183 /* Make sure none of the resources are allocated. */
2184 if (msi->msi_handlers > 0)
2186 for (i = 0; i < msi->msi_alloc; i++) {
2187 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2188 KASSERT(rle != NULL, ("missing MSI resource"));
2189 if (rle->res != NULL)
2191 irqs[i] = rle->start;
2194 /* Update control register with 0 count. */
2195 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
2196 ("%s: MSI still enabled", __func__));
2197 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
2198 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2201 /* Release the messages. */
2202 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
2203 for (i = 0; i < msi->msi_alloc; i++)
2204 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2206 /* Update alloc count. */
2214 * Return the max supported MSI messages this device supports.
2215 * Basically, assuming the MD code can alloc messages, this function
2216 * should return the maximum value that pci_alloc_msi() can return.
2217 * Thus, it is subject to the tunables, etc.
2220 pci_msi_count_method(device_t dev, device_t child)
2222 struct pci_devinfo *dinfo = device_get_ivars(child);
2223 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2225 if (pci_do_msi && msi->msi_location != 0)
2226 return (msi->msi_msgnum);
2230 /* kfree pcicfgregs structure and all depending data structures */
2233 pci_freecfg(struct pci_devinfo *dinfo)
2235 struct devlist *devlist_head;
2238 devlist_head = &pci_devq;
2240 if (dinfo->cfg.vpd.vpd_reg) {
2241 kfree(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2242 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2243 kfree(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2244 kfree(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2245 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2246 kfree(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2247 kfree(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2249 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2250 kfree(dinfo, M_DEVBUF);
2252 /* increment the generation count */
2255 /* we're losing one device */
2261 * PCI power manangement
2264 pci_set_powerstate_method(device_t dev, device_t child, int state)
2266 struct pci_devinfo *dinfo = device_get_ivars(child);
2267 pcicfgregs *cfg = &dinfo->cfg;
2269 int result, oldstate, highest, delay;
2271 if (cfg->pp.pp_cap == 0)
2272 return (EOPNOTSUPP);
2275 * Optimize a no state change request away. While it would be OK to
2276 * write to the hardware in theory, some devices have shown odd
2277 * behavior when going from D3 -> D3.
2279 oldstate = pci_get_powerstate(child);
2280 if (oldstate == state)
2284 * The PCI power management specification states that after a state
2285 * transition between PCI power states, system software must
2286 * guarantee a minimal delay before the function accesses the device.
2287 * Compute the worst case delay that we need to guarantee before we
2288 * access the device. Many devices will be responsive much more
2289 * quickly than this delay, but there are some that don't respond
2290 * instantly to state changes. Transitions to/from D3 state require
2291 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2292 * is done below with DELAY rather than a sleeper function because
2293 * this function can be called from contexts where we cannot sleep.
2295 highest = (oldstate > state) ? oldstate : state;
2296 if (highest == PCI_POWERSTATE_D3)
2298 else if (highest == PCI_POWERSTATE_D2)
2302 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2303 & ~PCIM_PSTAT_DMASK;
2306 case PCI_POWERSTATE_D0:
2307 status |= PCIM_PSTAT_D0;
2309 case PCI_POWERSTATE_D1:
2310 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2311 return (EOPNOTSUPP);
2312 status |= PCIM_PSTAT_D1;
2314 case PCI_POWERSTATE_D2:
2315 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2316 return (EOPNOTSUPP);
2317 status |= PCIM_PSTAT_D2;
2319 case PCI_POWERSTATE_D3:
2320 status |= PCIM_PSTAT_D3;
2328 "pci%d:%d:%d:%d: Transition from D%d to D%d\n",
2329 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2330 dinfo->cfg.func, oldstate, state);
2332 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2339 pci_get_powerstate_method(device_t dev, device_t child)
2341 struct pci_devinfo *dinfo = device_get_ivars(child);
2342 pcicfgregs *cfg = &dinfo->cfg;
2346 if (cfg->pp.pp_cap != 0) {
2347 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2348 switch (status & PCIM_PSTAT_DMASK) {
2350 result = PCI_POWERSTATE_D0;
2353 result = PCI_POWERSTATE_D1;
2356 result = PCI_POWERSTATE_D2;
2359 result = PCI_POWERSTATE_D3;
2362 result = PCI_POWERSTATE_UNKNOWN;
2366 /* No support, device is always at D0 */
2367 result = PCI_POWERSTATE_D0;
2373 * Some convenience functions for PCI device drivers.
2376 static __inline void
2377 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2381 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2383 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2386 static __inline void
2387 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2391 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2393 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2397 pci_enable_busmaster_method(device_t dev, device_t child)
2399 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2404 pci_disable_busmaster_method(device_t dev, device_t child)
2406 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2411 pci_enable_io_method(device_t dev, device_t child, int space)
2421 case SYS_RES_IOPORT:
2422 bit = PCIM_CMD_PORTEN;
2425 case SYS_RES_MEMORY:
2426 bit = PCIM_CMD_MEMEN;
2432 pci_set_command_bit(dev, child, bit);
2433 /* Some devices seem to need a brief stall here, what do to? */
2434 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2437 device_printf(child, "failed to enable %s mapping!\n", error);
2442 pci_disable_io_method(device_t dev, device_t child, int space)
2452 case SYS_RES_IOPORT:
2453 bit = PCIM_CMD_PORTEN;
2456 case SYS_RES_MEMORY:
2457 bit = PCIM_CMD_MEMEN;
2463 pci_clear_command_bit(dev, child, bit);
2464 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2465 if (command & bit) {
2466 device_printf(child, "failed to disable %s mapping!\n", error);
2473 * New style pci driver. Parent device is either a pci-host-bridge or a
2474 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2478 pci_print_verbose(struct pci_devinfo *dinfo)
2482 pcicfgregs *cfg = &dinfo->cfg;
2484 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2485 cfg->vendor, cfg->device, cfg->revid);
2486 kprintf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2487 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2488 kprintf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2489 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2491 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2492 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2493 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
2494 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2495 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
2496 if (cfg->intpin > 0)
2497 kprintf("\tintpin=%c, irq=%d\n",
2498 cfg->intpin +'a' -1, cfg->intline);
2499 if (cfg->pp.pp_cap) {
2502 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2503 kprintf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2504 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2505 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2506 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2507 status & PCIM_PSTAT_DMASK);
2509 if (cfg->msi.msi_location) {
2512 ctrl = cfg->msi.msi_ctrl;
2513 kprintf("\tMSI supports %d message%s%s%s\n",
2514 cfg->msi.msi_msgnum,
2515 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2516 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2517 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2519 if (cfg->msix.msix_location) {
2520 kprintf("\tMSI-X supports %d message%s ",
2521 cfg->msix.msix_msgnum,
2522 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2523 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2524 kprintf("in map 0x%x\n",
2525 cfg->msix.msix_table_bar);
2527 kprintf("in maps 0x%x and 0x%x\n",
2528 cfg->msix.msix_table_bar,
2529 cfg->msix.msix_pba_bar);
2531 pci_print_verbose_expr(cfg);
2536 pci_print_verbose_expr(const pcicfgregs *cfg)
2538 const struct pcicfg_expr *expr = &cfg->expr;
2539 const char *port_name;
2545 if (expr->expr_ptr == 0) /* No PCI Express capability */
2548 kprintf("\tPCI Express ver.%d cap=0x%04x",
2549 expr->expr_cap & PCIEM_CAP_VER_MASK, expr->expr_cap);
2550 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
2553 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
2555 switch (port_type) {
2556 case PCIE_END_POINT:
2557 port_name = "DEVICE";
2559 case PCIE_LEG_END_POINT:
2560 port_name = "LEGDEV";
2562 case PCIE_ROOT_PORT:
2565 case PCIE_UP_STREAM_PORT:
2566 port_name = "UPSTREAM";
2568 case PCIE_DOWN_STREAM_PORT:
2569 port_name = "DOWNSTRM";
2571 case PCIE_PCIE2PCI_BRIDGE:
2572 port_name = "PCIE2PCI";
2574 case PCIE_PCI2PCIE_BRIDGE:
2575 port_name = "PCI2PCIE";
2581 if ((port_type == PCIE_ROOT_PORT ||
2582 port_type == PCIE_DOWN_STREAM_PORT) &&
2583 !(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
2585 if (port_name != NULL)
2586 kprintf("[%s]", port_name);
2588 if (pcie_slotimpl(cfg)) {
2589 kprintf(", slotcap=0x%08x", expr->expr_slotcap);
2590 if (expr->expr_slotcap & PCIEM_SLTCAP_HP_CAP)
2591 kprintf("[HOTPLUG]");
2598 pci_porten(device_t pcib, int b, int s, int f)
2600 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2601 & PCIM_CMD_PORTEN) != 0;
2605 pci_memen(device_t pcib, int b, int s, int f)
2607 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2608 & PCIM_CMD_MEMEN) != 0;
2612 * Add a resource based on a pci map register. Return 1 if the map
2613 * register is a 32bit map register or 2 if it is a 64bit register.
2616 pci_add_map(device_t pcib, device_t bus, device_t dev,
2617 int b, int s, int f, int reg, struct resource_list *rl, int force,
2622 pci_addr_t start, end, count;
2629 struct resource *res;
2631 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2632 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
2633 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2634 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
2636 if (PCI_BAR_MEM(map)) {
2637 type = SYS_RES_MEMORY;
2638 if (map & PCIM_BAR_MEM_PREFETCH)
2641 type = SYS_RES_IOPORT;
2642 ln2size = pci_mapsize(testval);
2643 ln2range = pci_maprange(testval);
2644 base = pci_mapbase(map);
2645 barlen = ln2range == 64 ? 2 : 1;
2648 * For I/O registers, if bottom bit is set, and the next bit up
2649 * isn't clear, we know we have a BAR that doesn't conform to the
2650 * spec, so ignore it. Also, sanity check the size of the data
2651 * areas to the type of memory involved. Memory must be at least
2652 * 16 bytes in size, while I/O ranges must be at least 4.
2654 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2656 if ((type == SYS_RES_MEMORY && ln2size < 4) ||
2657 (type == SYS_RES_IOPORT && ln2size < 2))
2661 /* Read the other half of a 64bit map register */
2662 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
2664 kprintf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2665 reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size);
2666 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2667 kprintf(", port disabled\n");
2668 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2669 kprintf(", memory disabled\n");
2671 kprintf(", enabled\n");
2675 * If base is 0, then we have problems. It is best to ignore
2676 * such entries for the moment. These will be allocated later if
2677 * the driver specifically requests them. However, some
2678 * removable busses look better when all resources are allocated,
2679 * so allow '0' to be overriden.
2681 * Similarly treat maps whose values is the same as the test value
2682 * read back. These maps have had all f's written to them by the
2683 * BIOS in an attempt to disable the resources.
2685 if (!force && (base == 0 || map == testval))
2687 if ((u_long)base != base) {
2689 "pci%d:%d:%d:%d bar %#x too many address bits",
2690 pci_get_domain(dev), b, s, f, reg);
2695 * This code theoretically does the right thing, but has
2696 * undesirable side effects in some cases where peripherals
2697 * respond oddly to having these bits enabled. Let the user
2698 * be able to turn them off (since pci_enable_io_modes is 1 by
2701 if (pci_enable_io_modes) {
2702 /* Turn on resources that have been left off by a lazy BIOS */
2703 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
2704 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2705 cmd |= PCIM_CMD_PORTEN;
2706 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2708 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
2709 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2710 cmd |= PCIM_CMD_MEMEN;
2711 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2714 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2716 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2720 count = 1 << ln2size;
2721 if (base == 0 || base == pci_mapbase(testval)) {
2722 start = 0; /* Let the parent decide. */
2726 end = base + (1 << ln2size) - 1;
2728 resource_list_add(rl, type, reg, start, end, count);
2731 * Try to allocate the resource for this BAR from our parent
2732 * so that this resource range is already reserved. The
2733 * driver for this device will later inherit this resource in
2734 * pci_alloc_resource().
2736 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count,
2737 prefetch ? RF_PREFETCHABLE : 0);
2740 * If the allocation fails, delete the resource list
2741 * entry to force pci_alloc_resource() to allocate
2742 * resources from the parent.
2744 resource_list_delete(rl, type, reg);
2745 #ifdef PCI_BAR_CLEAR
2748 #else /* !PCI_BAR_CLEAR */
2750 * Don't clear BAR here. Some BIOS lists HPET as a
2751 * PCI function, clearing the BAR causes HPET timer
2755 kprintf("pci:%d:%d:%d: resource reservation failed "
2756 "%#llx - %#llx\n", b, s, f, start, end);
2759 #endif /* PCI_BAR_CLEAR */
2761 start = rman_get_start(res);
2763 pci_write_config(dev, reg, start, 4);
2765 pci_write_config(dev, reg + 4, start >> 32, 4);
2770 * For ATA devices we need to decide early what addressing mode to use.
2771 * Legacy demands that the primary and secondary ATA ports sits on the
2772 * same addresses that old ISA hardware did. This dictates that we use
2773 * those addresses and ignore the BAR's if we cannot set PCI native
2777 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b,
2778 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask)
2780 int rid, type, progif;
2782 /* if this device supports PCI native addressing use it */
2783 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2784 if ((progif & 0x8a) == 0x8a) {
2785 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2786 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
2787 kprintf("Trying ATA native PCI addressing mode\n");
2788 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2792 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2793 type = SYS_RES_IOPORT;
2794 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
2795 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force,
2796 prefetchmask & (1 << 0));
2797 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force,
2798 prefetchmask & (1 << 1));
2801 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
2802 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
2805 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
2806 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
2809 if (progif & PCIP_STORAGE_IDE_MODESEC) {
2810 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force,
2811 prefetchmask & (1 << 2));
2812 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force,
2813 prefetchmask & (1 << 3));
2816 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
2817 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
2820 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
2821 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
2824 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force,
2825 prefetchmask & (1 << 4));
2826 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force,
2827 prefetchmask & (1 << 5));
2831 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
2833 struct pci_devinfo *dinfo = device_get_ivars(dev);
2834 pcicfgregs *cfg = &dinfo->cfg;
2835 char tunable_name[64];
2838 /* Has to have an intpin to have an interrupt. */
2839 if (cfg->intpin == 0)
2842 /* Let the user override the IRQ with a tunable. */
2843 irq = PCI_INVALID_IRQ;
2844 ksnprintf(tunable_name, sizeof(tunable_name),
2845 "hw.pci%d.%d.%d.INT%c.irq",
2846 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
2847 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
2848 irq = PCI_INVALID_IRQ;
2851 * If we didn't get an IRQ via the tunable, then we either use the
2852 * IRQ value in the intline register or we ask the bus to route an
2853 * interrupt for us. If force_route is true, then we only use the
2854 * value in the intline register if the bus was unable to assign an
2857 if (!PCI_INTERRUPT_VALID(irq)) {
2858 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
2859 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
2860 if (!PCI_INTERRUPT_VALID(irq))
2864 /* If after all that we don't have an IRQ, just bail. */
2865 if (!PCI_INTERRUPT_VALID(irq))
2868 /* Update the config register if it changed. */
2869 if (irq != cfg->intline) {
2871 pci_write_config(dev, PCIR_INTLINE, irq, 1);
2874 /* Add this IRQ as rid 0 interrupt resource. */
2875 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
2879 pci_add_resources(device_t pcib, device_t bus, device_t dev, int force, uint32_t prefetchmask)
2881 struct pci_devinfo *dinfo = device_get_ivars(dev);
2882 pcicfgregs *cfg = &dinfo->cfg;
2883 struct resource_list *rl = &dinfo->resources;
2884 struct pci_quirk *q;
2891 /* ATA devices needs special map treatment */
2892 if ((pci_get_class(dev) == PCIC_STORAGE) &&
2893 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
2894 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
2895 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
2896 !pci_read_config(dev, PCIR_BAR(2), 4))) )
2897 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask);
2899 for (i = 0; i < cfg->nummaps;)
2900 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i),
2901 rl, force, prefetchmask & (1 << i));
2904 * Add additional, quirked resources.
2906 for (q = &pci_quirks[0]; q->devid; q++) {
2907 if (q->devid == ((cfg->device << 16) | cfg->vendor)
2908 && q->type == PCI_QUIRK_MAP_REG)
2909 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl,
2913 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2914 #ifdef __PCI_REROUTE_INTERRUPT
2916 * Try to re-route interrupts. Sometimes the BIOS or
2917 * firmware may leave bogus values in these registers.
2918 * If the re-route fails, then just stick with what we
2921 pci_assign_interrupt(bus, dev, 1);
2923 pci_assign_interrupt(bus, dev, 0);
2929 pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
2931 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
2932 device_t pcib = device_get_parent(dev);
2933 struct pci_devinfo *dinfo;
2935 int s, f, pcifunchigh;
2938 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
2939 ("dinfo_size too small"));
2940 maxslots = PCIB_MAXSLOTS(pcib);
2941 for (s = 0; s <= maxslots; s++) {
2945 hdrtype = REG(PCIR_HDRTYPE, 1);
2946 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
2948 if (hdrtype & PCIM_MFDEV)
2949 pcifunchigh = PCI_FUNCMAX;
2950 for (f = 0; f <= pcifunchigh; f++) {
2951 dinfo = pci_read_device(pcib, domain, busno, s, f,
2953 if (dinfo != NULL) {
2954 pci_add_child(dev, dinfo);
2962 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
2966 pcib = device_get_parent(bus);
2967 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
2968 device_set_ivars(dinfo->cfg.dev, dinfo);
2969 resource_list_init(&dinfo->resources);
2970 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
2971 pci_cfg_restore(dinfo->cfg.dev, dinfo);
2972 pci_print_verbose(dinfo);
2973 pci_add_resources(pcib, bus, dinfo->cfg.dev, 0, 0);
2977 pci_probe(device_t dev)
2979 device_set_desc(dev, "PCI bus");
2981 /* Allow other subclasses to override this driver. */
2986 pci_attach(device_t dev)
2991 * Since there can be multiple independantly numbered PCI
2992 * busses on systems with multiple PCI domains, we can't use
2993 * the unit number to decide which bus we are probing. We ask
2994 * the parent pcib what our domain and bus numbers are.
2996 domain = pcib_get_domain(dev);
2997 busno = pcib_get_bus(dev);
2999 device_printf(dev, "domain=%d, physical bus=%d\n",
3002 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
3004 return (bus_generic_attach(dev));
3008 pci_suspend(device_t dev)
3010 int dstate, error, i, numdevs;
3011 device_t acpi_dev, child, *devlist;
3012 struct pci_devinfo *dinfo;
3015 * Save the PCI configuration space for each child and set the
3016 * device in the appropriate power state for this sleep state.
3019 if (pci_do_power_resume)
3020 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
3021 device_get_children(dev, &devlist, &numdevs);
3022 for (i = 0; i < numdevs; i++) {
3024 dinfo = (struct pci_devinfo *) device_get_ivars(child);
3025 pci_cfg_save(child, dinfo, 0);
3028 /* Suspend devices before potentially powering them down. */
3029 error = bus_generic_suspend(dev);
3031 kfree(devlist, M_TEMP);
3036 * Always set the device to D3. If ACPI suggests a different
3037 * power state, use it instead. If ACPI is not present, the
3038 * firmware is responsible for managing device power. Skip
3039 * children who aren't attached since they are powered down
3040 * separately. Only manage type 0 devices for now.
3042 for (i = 0; acpi_dev && i < numdevs; i++) {
3044 dinfo = (struct pci_devinfo *) device_get_ivars(child);
3045 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) {
3046 dstate = PCI_POWERSTATE_D3;
3047 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate);
3048 pci_set_powerstate(child, dstate);
3051 kfree(devlist, M_TEMP);
3056 pci_resume(device_t dev)
3059 device_t acpi_dev, child, *devlist;
3060 struct pci_devinfo *dinfo;
3063 * Set each child to D0 and restore its PCI configuration space.
3066 if (pci_do_power_resume)
3067 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
3068 device_get_children(dev, &devlist, &numdevs);
3069 for (i = 0; i < numdevs; i++) {
3071 * Notify ACPI we're going to D0 but ignore the result. If
3072 * ACPI is not present, the firmware is responsible for
3073 * managing device power. Only manage type 0 devices for now.
3076 dinfo = (struct pci_devinfo *) device_get_ivars(child);
3077 if (acpi_dev && device_is_attached(child) &&
3078 dinfo->cfg.hdrtype == 0) {
3079 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL);
3080 pci_set_powerstate(child, PCI_POWERSTATE_D0);
3083 /* Now the device is powered up, restore its config space. */
3084 pci_cfg_restore(child, dinfo);
3086 kfree(devlist, M_TEMP);
3087 return (bus_generic_resume(dev));
3091 pci_load_vendor_data(void)
3093 caddr_t vendordata, info;
3095 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
3096 info = preload_search_info(vendordata, MODINFO_ADDR);
3097 pci_vendordata = *(char **)info;
3098 info = preload_search_info(vendordata, MODINFO_SIZE);
3099 pci_vendordata_size = *(size_t *)info;
3100 /* terminate the database */
3101 pci_vendordata[pci_vendordata_size] = '\n';
3106 pci_driver_added(device_t dev, driver_t *driver)
3111 struct pci_devinfo *dinfo;
3115 device_printf(dev, "driver added\n");
3116 DEVICE_IDENTIFY(driver, dev);
3117 device_get_children(dev, &devlist, &numdevs);
3118 for (i = 0; i < numdevs; i++) {
3120 if (device_get_state(child) != DS_NOTPRESENT)
3122 dinfo = device_get_ivars(child);
3123 pci_print_verbose(dinfo);
3125 kprintf("pci%d:%d:%d:%d: reprobing on driver added\n",
3126 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
3128 pci_cfg_restore(child, dinfo);
3129 if (device_probe_and_attach(child) != 0)
3130 pci_cfg_save(child, dinfo, 1);
3132 kfree(devlist, M_TEMP);
3136 pci_child_detached(device_t parent __unused, device_t child)
3138 /* Turn child's power off */
3139 pci_cfg_save(child, device_get_ivars(child), 1);
3143 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
3144 driver_intr_t *intr, void *arg, void **cookiep, lwkt_serialize_t serializer)
3147 struct pci_devinfo *dinfo;
3148 struct msix_table_entry *mte;
3149 struct msix_vector *mv;
3156 error = bus_generic_setup_intr(dev, child, irq, flags, intr,
3157 arg, &cookie, serializer);
3161 /* If this is not a direct child, just bail out. */
3162 if (device_get_parent(child) != dev) {
3167 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3169 rid = rman_get_rid(irq);
3171 /* Make sure that INTx is enabled */
3172 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3175 * Check to see if the interrupt is MSI or MSI-X.
3176 * Ask our parent to map the MSI and give
3177 * us the address and data register values.
3178 * If we fail for some reason, teardown the
3179 * interrupt handler.
3181 dinfo = device_get_ivars(child);
3182 if (dinfo->cfg.msi.msi_alloc > 0) {
3183 if (dinfo->cfg.msi.msi_addr == 0) {
3184 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
3185 ("MSI has handlers, but vectors not mapped"));
3186 error = PCIB_MAP_MSI(device_get_parent(dev),
3187 child, rman_get_start(irq), &addr, &data);
3190 dinfo->cfg.msi.msi_addr = addr;
3191 dinfo->cfg.msi.msi_data = data;
3192 pci_enable_msi(child, addr, data);
3194 dinfo->cfg.msi.msi_handlers++;
3196 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3197 ("No MSI or MSI-X interrupts allocated"));
3198 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3199 ("MSI-X index too high"));
3200 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3201 KASSERT(mte->mte_vector != 0, ("no message vector"));
3202 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
3203 KASSERT(mv->mv_irq == rman_get_start(irq),
3205 if (mv->mv_address == 0) {
3206 KASSERT(mte->mte_handlers == 0,
3207 ("MSI-X table entry has handlers, but vector not mapped"));
3208 error = PCIB_MAP_MSI(device_get_parent(dev),
3209 child, rman_get_start(irq), &addr, &data);
3212 mv->mv_address = addr;
3215 if (mte->mte_handlers == 0) {
3216 pci_enable_msix(child, rid - 1, mv->mv_address,
3218 pci_unmask_msix(child, rid - 1);
3220 mte->mte_handlers++;
3223 /* Make sure that INTx is disabled if we are using MSI/MSIX */
3224 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3227 (void)bus_generic_teardown_intr(dev, child, irq,
3238 pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
3242 struct msix_table_entry *mte;
3243 struct resource_list_entry *rle;
3244 struct pci_devinfo *dinfo;
3249 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
3252 /* If this isn't a direct child, just bail out */
3253 if (device_get_parent(child) != dev)
3254 return(bus_generic_teardown_intr(dev, child, irq, cookie));
3256 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3258 rid = rman_get_rid(irq);
3261 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3264 * Check to see if the interrupt is MSI or MSI-X. If so,
3265 * decrement the appropriate handlers count and mask the
3266 * MSI-X message, or disable MSI messages if the count
3269 dinfo = device_get_ivars(child);
3270 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
3271 if (rle->res != irq)
3273 if (dinfo->cfg.msi.msi_alloc > 0) {
3274 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
3275 ("MSI-X index too high"));
3276 if (dinfo->cfg.msi.msi_handlers == 0)
3278 dinfo->cfg.msi.msi_handlers--;
3279 if (dinfo->cfg.msi.msi_handlers == 0)
3280 pci_disable_msi(child);
3282 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3283 ("No MSI or MSI-X interrupts allocated"));
3284 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3285 ("MSI-X index too high"));
3286 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3287 if (mte->mte_handlers == 0)
3289 mte->mte_handlers--;
3290 if (mte->mte_handlers == 0)
3291 pci_mask_msix(child, rid - 1);
3294 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3297 ("%s: generic teardown failed for MSI/MSI-X", __func__));
3299 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3304 pci_print_child(device_t dev, device_t child)
3306 struct pci_devinfo *dinfo;
3307 struct resource_list *rl;
3310 dinfo = device_get_ivars(child);
3311 rl = &dinfo->resources;
3313 retval += bus_print_child_header(dev, child);
3315 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
3316 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
3317 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
3318 if (device_get_flags(dev))
3319 retval += kprintf(" flags %#x", device_get_flags(dev));
3321 retval += kprintf(" at device %d.%d", pci_get_slot(child),
3322 pci_get_function(child));
3324 retval += bus_print_child_footer(dev, child);
3334 } pci_nomatch_tab[] = {
3335 {PCIC_OLD, -1, "old"},
3336 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
3337 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
3338 {PCIC_STORAGE, -1, "mass storage"},
3339 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
3340 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
3341 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
3342 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
3343 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
3344 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"},
3345 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"},
3346 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"},
3347 {PCIC_NETWORK, -1, "network"},
3348 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
3349 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
3350 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
3351 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
3352 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
3353 {PCIC_DISPLAY, -1, "display"},
3354 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
3355 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
3356 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
3357 {PCIC_MULTIMEDIA, -1, "multimedia"},
3358 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
3359 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
3360 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
3361 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"},
3362 {PCIC_MEMORY, -1, "memory"},
3363 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
3364 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
3365 {PCIC_BRIDGE, -1, "bridge"},
3366 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
3367 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
3368 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
3369 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
3370 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
3371 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
3372 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
3373 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
3374 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
3375 {PCIC_SIMPLECOMM, -1, "simple comms"},
3376 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
3377 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
3378 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
3379 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
3380 {PCIC_BASEPERIPH, -1, "base peripheral"},
3381 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
3382 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
3383 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
3384 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
3385 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
3386 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"},
3387 {PCIC_INPUTDEV, -1, "input device"},
3388 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
3389 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
3390 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
3391 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
3392 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
3393 {PCIC_DOCKING, -1, "docking station"},
3394 {PCIC_PROCESSOR, -1, "processor"},
3395 {PCIC_SERIALBUS, -1, "serial bus"},
3396 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
3397 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
3398 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
3399 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
3400 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
3401 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
3402 {PCIC_WIRELESS, -1, "wireless controller"},
3403 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
3404 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
3405 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
3406 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
3407 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
3408 {PCIC_SATCOM, -1, "satellite communication"},
3409 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
3410 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
3411 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
3412 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
3413 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
3414 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
3415 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
3416 {PCIC_DASP, -1, "dasp"},
3417 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
3422 pci_probe_nomatch(device_t dev, device_t child)
3425 char *cp, *scp, *device;
3428 * Look for a listing for this device in a loaded device database.
3430 if ((device = pci_describe_device(child)) != NULL) {
3431 device_printf(dev, "<%s>", device);
3432 kfree(device, M_DEVBUF);
3435 * Scan the class/subclass descriptions for a general
3440 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
3441 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
3442 if (pci_nomatch_tab[i].subclass == -1) {
3443 cp = pci_nomatch_tab[i].desc;
3444 } else if (pci_nomatch_tab[i].subclass ==
3445 pci_get_subclass(child)) {
3446 scp = pci_nomatch_tab[i].desc;
3450 device_printf(dev, "<%s%s%s>",
3452 ((cp != NULL) && (scp != NULL)) ? ", " : "",
3455 kprintf(" at device %d.%d (no driver attached)\n",
3456 pci_get_slot(child), pci_get_function(child));
3457 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1);
3462 * Parse the PCI device database, if loaded, and return a pointer to a
3463 * description of the device.
3465 * The database is flat text formatted as follows:
3467 * Any line not in a valid format is ignored.
3468 * Lines are terminated with newline '\n' characters.
3470 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
3473 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
3474 * - devices cannot be listed without a corresponding VENDOR line.
3475 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
3476 * another TAB, then the device name.
3480 * Assuming (ptr) points to the beginning of a line in the database,
3481 * return the vendor or device and description of the next entry.
3482 * The value of (vendor) or (device) inappropriate for the entry type
3483 * is set to -1. Returns nonzero at the end of the database.
3485 * Note that this is slightly unrobust in the face of corrupt data;
3486 * we attempt to safeguard against this by spamming the end of the
3487 * database with a newline when we initialise.
3490 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
3499 left = pci_vendordata_size - (cp - pci_vendordata);
3507 ksscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
3511 ksscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
3514 /* skip to next line */
3515 while (*cp != '\n' && left > 0) {
3524 /* skip to next line */
3525 while (*cp != '\n' && left > 0) {
3529 if (*cp == '\n' && left > 0)
3536 pci_describe_device(device_t dev)
3539 char *desc, *vp, *dp, *line;
3541 desc = vp = dp = NULL;
3544 * If we have no vendor data, we can't do anything.
3546 if (pci_vendordata == NULL)
3550 * Scan the vendor data looking for this device
3552 line = pci_vendordata;
3553 if ((vp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3556 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
3558 if (vendor == pci_get_vendor(dev))
3561 if ((dp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3564 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
3572 if (device == pci_get_device(dev))
3576 ksnprintf(dp, 80, "0x%x", pci_get_device(dev));
3577 if ((desc = kmalloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
3579 ksprintf(desc, "%s, %s", vp, dp);
3582 kfree(vp, M_DEVBUF);
3584 kfree(dp, M_DEVBUF);
3589 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
3591 struct pci_devinfo *dinfo;
3594 dinfo = device_get_ivars(child);
3598 case PCI_IVAR_ETHADDR:
3600 * The generic accessor doesn't deal with failure, so
3601 * we set the return value, then return an error.
3603 *((uint8_t **) result) = NULL;
3605 case PCI_IVAR_SUBVENDOR:
3606 *result = cfg->subvendor;
3608 case PCI_IVAR_SUBDEVICE:
3609 *result = cfg->subdevice;
3611 case PCI_IVAR_VENDOR:
3612 *result = cfg->vendor;
3614 case PCI_IVAR_DEVICE:
3615 *result = cfg->device;
3617 case PCI_IVAR_DEVID:
3618 *result = (cfg->device << 16) | cfg->vendor;
3620 case PCI_IVAR_CLASS:
3621 *result = cfg->baseclass;
3623 case PCI_IVAR_SUBCLASS:
3624 *result = cfg->subclass;
3626 case PCI_IVAR_PROGIF:
3627 *result = cfg->progif;
3629 case PCI_IVAR_REVID:
3630 *result = cfg->revid;
3632 case PCI_IVAR_INTPIN:
3633 *result = cfg->intpin;
3636 *result = cfg->intline;
3638 case PCI_IVAR_DOMAIN:
3639 *result = cfg->domain;
3645 *result = cfg->slot;
3647 case PCI_IVAR_FUNCTION:
3648 *result = cfg->func;
3650 case PCI_IVAR_CMDREG:
3651 *result = cfg->cmdreg;
3653 case PCI_IVAR_CACHELNSZ:
3654 *result = cfg->cachelnsz;
3656 case PCI_IVAR_MINGNT:
3657 *result = cfg->mingnt;
3659 case PCI_IVAR_MAXLAT:
3660 *result = cfg->maxlat;
3662 case PCI_IVAR_LATTIMER:
3663 *result = cfg->lattimer;
3665 case PCI_IVAR_PCIXCAP_PTR:
3666 *result = cfg->pcix.pcix_ptr;
3668 case PCI_IVAR_PCIECAP_PTR:
3669 *result = cfg->expr.expr_ptr;
3671 case PCI_IVAR_VPDCAP_PTR:
3672 *result = cfg->vpd.vpd_reg;
3681 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
3683 struct pci_devinfo *dinfo;
3685 dinfo = device_get_ivars(child);
3688 case PCI_IVAR_INTPIN:
3689 dinfo->cfg.intpin = value;
3691 case PCI_IVAR_ETHADDR:
3692 case PCI_IVAR_SUBVENDOR:
3693 case PCI_IVAR_SUBDEVICE:
3694 case PCI_IVAR_VENDOR:
3695 case PCI_IVAR_DEVICE:
3696 case PCI_IVAR_DEVID:
3697 case PCI_IVAR_CLASS:
3698 case PCI_IVAR_SUBCLASS:
3699 case PCI_IVAR_PROGIF:
3700 case PCI_IVAR_REVID:
3702 case PCI_IVAR_DOMAIN:
3705 case PCI_IVAR_FUNCTION:
3706 return (EINVAL); /* disallow for now */
3713 #include "opt_ddb.h"
3715 #include <ddb/ddb.h>
3716 #include <sys/cons.h>
3719 * List resources based on pci map registers, used for within ddb
3722 DB_SHOW_COMMAND(pciregs, db_pci_dump)
3724 struct pci_devinfo *dinfo;
3725 struct devlist *devlist_head;
3728 int i, error, none_count;
3731 /* get the head of the device queue */
3732 devlist_head = &pci_devq;
3735 * Go through the list of devices and print out devices
3737 for (error = 0, i = 0,
3738 dinfo = STAILQ_FIRST(devlist_head);
3739 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
3740 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
3742 /* Populate pd_name and pd_unit */
3745 name = device_get_name(dinfo->cfg.dev);
3748 db_kprintf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
3749 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
3750 (name && *name) ? name : "none",
3751 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
3753 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
3754 p->pc_sel.pc_func, (p->pc_class << 16) |
3755 (p->pc_subclass << 8) | p->pc_progif,
3756 (p->pc_subdevice << 16) | p->pc_subvendor,
3757 (p->pc_device << 16) | p->pc_vendor,
3758 p->pc_revid, p->pc_hdr);
3764 static struct resource *
3765 pci_alloc_map(device_t dev, device_t child, int type, int *rid,
3766 u_long start, u_long end, u_long count, u_int flags)
3768 struct pci_devinfo *dinfo = device_get_ivars(child);
3769 struct resource_list *rl = &dinfo->resources;
3770 struct resource_list_entry *rle;
3771 struct resource *res;
3772 pci_addr_t map, testval;
3776 * Weed out the bogons, and figure out how large the BAR/map
3777 * is. Bars that read back 0 here are bogus and unimplemented.
3778 * Note: atapci in legacy mode are special and handled elsewhere
3779 * in the code. If you have a atapci device in legacy mode and
3780 * it fails here, that other code is broken.
3783 map = pci_read_config(child, *rid, 4);
3784 pci_write_config(child, *rid, 0xffffffff, 4);
3785 testval = pci_read_config(child, *rid, 4);
3786 if (pci_maprange(testval) == 64)
3787 map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32;
3788 if (pci_mapbase(testval) == 0)
3792 * Restore the original value of the BAR. We may have reprogrammed
3793 * the BAR of the low-level console device and when booting verbose,
3794 * we need the console device addressable.
3796 pci_write_config(child, *rid, map, 4);
3798 if (PCI_BAR_MEM(testval)) {
3799 if (type != SYS_RES_MEMORY) {
3802 "child %s requested type %d for rid %#x,"
3803 " but the BAR says it is an memio\n",
3804 device_get_nameunit(child), type, *rid);
3808 if (type != SYS_RES_IOPORT) {
3811 "child %s requested type %d for rid %#x,"
3812 " but the BAR says it is an ioport\n",
3813 device_get_nameunit(child), type, *rid);
3818 * For real BARs, we need to override the size that
3819 * the driver requests, because that's what the BAR
3820 * actually uses and we would otherwise have a
3821 * situation where we might allocate the excess to
3822 * another driver, which won't work.
3824 mapsize = pci_mapsize(testval);
3825 count = 1UL << mapsize;
3826 if (RF_ALIGNMENT(flags) < mapsize)
3827 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
3828 if (PCI_BAR_MEM(testval) && (testval & PCIM_BAR_MEM_PREFETCH))
3829 flags |= RF_PREFETCHABLE;
3832 * Allocate enough resource, and then write back the
3833 * appropriate bar for that resource.
3835 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
3836 start, end, count, flags);
3838 device_printf(child,
3839 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
3840 count, *rid, type, start, end);
3843 resource_list_add(rl, type, *rid, start, end, count);
3844 rle = resource_list_find(rl, type, *rid);
3846 panic("pci_alloc_map: unexpectedly can't find resource.");
3848 rle->start = rman_get_start(res);
3849 rle->end = rman_get_end(res);
3852 device_printf(child,
3853 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
3854 count, *rid, type, rman_get_start(res));
3855 map = rman_get_start(res);
3857 pci_write_config(child, *rid, map, 4);
3858 if (pci_maprange(testval) == 64)
3859 pci_write_config(child, *rid + 4, map >> 32, 4);
3865 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
3866 u_long start, u_long end, u_long count, u_int flags)
3868 struct pci_devinfo *dinfo = device_get_ivars(child);
3869 struct resource_list *rl = &dinfo->resources;
3870 struct resource_list_entry *rle;
3871 pcicfgregs *cfg = &dinfo->cfg;
3874 * Perform lazy resource allocation
3876 if (device_get_parent(child) == dev) {
3880 * Can't alloc legacy interrupt once MSI messages
3881 * have been allocated.
3884 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
3885 cfg->msix.msix_alloc > 0))
3889 * If the child device doesn't have an
3890 * interrupt routed and is deserving of an
3891 * interrupt, try to assign it one.
3893 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
3895 pci_assign_interrupt(dev, child, 0);
3897 case SYS_RES_IOPORT:
3898 case SYS_RES_MEMORY:
3899 if (*rid < PCIR_BAR(cfg->nummaps)) {
3901 * Enable the I/O mode. We should
3902 * also be assigning resources too
3903 * when none are present. The
3904 * resource_list_alloc kind of sorta does
3907 if (PCI_ENABLE_IO(dev, child, type))
3910 rle = resource_list_find(rl, type, *rid);
3912 return (pci_alloc_map(dev, child, type, rid,
3913 start, end, count, flags));
3917 * If we've already allocated the resource, then
3918 * return it now. But first we may need to activate
3919 * it, since we don't allocate the resource as active
3920 * above. Normally this would be done down in the
3921 * nexus, but since we short-circuit that path we have
3922 * to do its job here. Not sure if we should kfree the
3923 * resource if it fails to activate.
3925 rle = resource_list_find(rl, type, *rid);
3926 if (rle != NULL && rle->res != NULL) {
3928 device_printf(child,
3929 "Reserved %#lx bytes for rid %#x type %d at %#lx\n",
3930 rman_get_size(rle->res), *rid, type,
3931 rman_get_start(rle->res));
3932 if ((flags & RF_ACTIVE) &&
3933 bus_generic_activate_resource(dev, child, type,
3934 *rid, rle->res) != 0)
3939 return (resource_list_alloc(rl, dev, child, type, rid,
3940 start, end, count, flags));
3944 pci_delete_resource(device_t dev, device_t child, int type, int rid)
3946 struct pci_devinfo *dinfo;
3947 struct resource_list *rl;
3948 struct resource_list_entry *rle;
3950 if (device_get_parent(child) != dev)
3953 dinfo = device_get_ivars(child);
3954 rl = &dinfo->resources;
3955 rle = resource_list_find(rl, type, rid);
3958 if (rman_get_device(rle->res) != dev ||
3959 rman_get_flags(rle->res) & RF_ACTIVE) {
3960 device_printf(dev, "delete_resource: "
3961 "Resource still owned by child, oops. "
3962 "(type=%d, rid=%d, addr=%lx)\n",
3963 rle->type, rle->rid,
3964 rman_get_start(rle->res));
3967 bus_release_resource(dev, type, rid, rle->res);
3969 resource_list_delete(rl, type, rid);
3972 * Why do we turn off the PCI configuration BAR when we delete a
3975 pci_write_config(child, rid, 0, 4);
3976 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid);
3979 struct resource_list *
3980 pci_get_resource_list (device_t dev, device_t child)
3982 struct pci_devinfo *dinfo = device_get_ivars(child);
3987 return (&dinfo->resources);
3991 pci_read_config_method(device_t dev, device_t child, int reg, int width)
3993 struct pci_devinfo *dinfo = device_get_ivars(child);
3994 pcicfgregs *cfg = &dinfo->cfg;
3996 return (PCIB_READ_CONFIG(device_get_parent(dev),
3997 cfg->bus, cfg->slot, cfg->func, reg, width));
4001 pci_write_config_method(device_t dev, device_t child, int reg,
4002 uint32_t val, int width)
4004 struct pci_devinfo *dinfo = device_get_ivars(child);
4005 pcicfgregs *cfg = &dinfo->cfg;
4007 PCIB_WRITE_CONFIG(device_get_parent(dev),
4008 cfg->bus, cfg->slot, cfg->func, reg, val, width);
4012 pci_child_location_str_method(device_t dev, device_t child, char *buf,
4016 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
4017 pci_get_function(child));
4022 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
4025 struct pci_devinfo *dinfo;
4028 dinfo = device_get_ivars(child);
4030 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
4031 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
4032 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
4038 pci_assign_interrupt_method(device_t dev, device_t child)
4040 struct pci_devinfo *dinfo = device_get_ivars(child);
4041 pcicfgregs *cfg = &dinfo->cfg;
4043 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
4048 pci_modevent(module_t mod, int what, void *arg)
4050 static struct cdev *pci_cdev;
4054 STAILQ_INIT(&pci_devq);
4056 dev_ops_add(&pcic_ops, -1, 0);
4057 pci_cdev = make_dev(&pcic_ops, 0, UID_ROOT, GID_WHEEL, 0644,
4059 pci_load_vendor_data();
4063 destroy_dev(pci_cdev);
4071 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
4076 * Only do header type 0 devices. Type 1 devices are bridges,
4077 * which we know need special treatment. Type 2 devices are
4078 * cardbus bridges which also require special treatment.
4079 * Other types are unknown, and we err on the side of safety
4082 if (dinfo->cfg.hdrtype != 0)
4086 * Restore the device to full power mode. We must do this
4087 * before we restore the registers because moving from D3 to
4088 * D0 will cause the chip's BARs and some other registers to
4089 * be reset to some unknown power on reset values. Cut down
4090 * the noise on boot by doing nothing if we are already in
4093 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
4094 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4096 for (i = 0; i < dinfo->cfg.nummaps; i++)
4097 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4);
4098 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
4099 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
4100 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
4101 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
4102 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
4103 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
4104 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
4105 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
4106 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
4107 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
4109 /* Restore MSI and MSI-X configurations if they are present. */
4110 if (dinfo->cfg.msi.msi_location != 0)
4111 pci_resume_msi(dev);
4112 if (dinfo->cfg.msix.msix_location != 0)
4113 pci_resume_msix(dev);
4117 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
4124 * Only do header type 0 devices. Type 1 devices are bridges, which
4125 * we know need special treatment. Type 2 devices are cardbus bridges
4126 * which also require special treatment. Other types are unknown, and
4127 * we err on the side of safety by ignoring them. Powering down
4128 * bridges should not be undertaken lightly.
4130 if (dinfo->cfg.hdrtype != 0)
4132 for (i = 0; i < dinfo->cfg.nummaps; i++)
4133 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4);
4134 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
4137 * Some drivers apparently write to these registers w/o updating our
4138 * cached copy. No harm happens if we update the copy, so do so here
4139 * so we can restore them. The COMMAND register is modified by the
4140 * bus w/o updating the cache. This should represent the normally
4141 * writable portion of the 'defined' part of type 0 headers. In
4142 * theory we also need to save/restore the PCI capability structures
4143 * we know about, but apart from power we don't know any that are
4146 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
4147 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4148 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
4149 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
4150 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
4151 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
4152 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
4153 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
4154 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
4155 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
4156 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
4157 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
4158 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
4159 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
4160 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
4163 * don't set the state for display devices, base peripherals and
4164 * memory devices since bad things happen when they are powered down.
4165 * We should (a) have drivers that can easily detach and (b) use
4166 * generic drivers for these devices so that some device actually
4167 * attaches. We need to make sure that when we implement (a) we don't
4168 * power the device down on a reattach.
4170 cls = pci_get_class(dev);
4173 switch (pci_do_power_nodriver)
4175 case 0: /* NO powerdown at all */
4177 case 1: /* Conservative about what to power down */
4178 if (cls == PCIC_STORAGE)
4181 case 2: /* Agressive about what to power down */
4182 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
4183 cls == PCIC_BASEPERIPH)
4186 case 3: /* Power down everything */
4190 * PCI spec says we can only go into D3 state from D0 state.
4191 * Transition from D[12] into D0 before going to D3 state.
4193 ps = pci_get_powerstate(dev);
4194 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
4195 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4196 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
4197 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
4200 #ifdef COMPAT_OLDPCI
4203 * Locate the parent of a PCI device by scanning the PCI devlist
4204 * and return the entry for the parent.
4205 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
4206 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
4209 pci_devlist_get_parent(pcicfgregs *cfg)
4211 struct devlist *devlist_head;
4212 struct pci_devinfo *dinfo;
4213 pcicfgregs *bridge_cfg;
4216 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
4218 /* If the device is on PCI bus 0, look for the host */
4219 if (cfg->bus == 0) {
4220 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
4221 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
4222 bridge_cfg = &dinfo->cfg;
4223 if (bridge_cfg->baseclass == PCIC_BRIDGE
4224 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
4225 && bridge_cfg->bus == cfg->bus) {
4231 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
4233 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
4234 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
4235 bridge_cfg = &dinfo->cfg;
4236 if (bridge_cfg->baseclass == PCIC_BRIDGE
4237 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
4238 && bridge_cfg->secondarybus == cfg->bus) {
4247 #endif /* COMPAT_OLDPCI */