2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
40 #include <sys/mplock2.h>
43 #include <vm/vm_param.h>
45 #include <vm/vm_kern.h>
46 #include <vm/vm_extern.h>
48 #include <vm/vm_map.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine_base/apic/mpapic.h>
59 #include <machine/psl.h>
60 #include <machine/segments.h>
61 #include <machine/tss.h>
62 #include <machine/specialreg.h>
63 #include <machine/globaldata.h>
65 #include <machine/md_var.h> /* setidt() */
66 #include <machine_base/icu/icu.h> /* IPIs */
67 #include <machine_base/isa/intr_machdep.h> /* IPIs */
69 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
71 #define WARMBOOT_TARGET 0
72 #define WARMBOOT_OFF (KERNBASE + 0x0467)
73 #define WARMBOOT_SEG (KERNBASE + 0x0469)
75 #define BIOS_BASE (0xf0000)
76 #define BIOS_SIZE (0x10000)
77 #define BIOS_COUNT (BIOS_SIZE/4)
79 #define CMOS_REG (0x70)
80 #define CMOS_DATA (0x71)
81 #define BIOS_RESET (0x0f)
82 #define BIOS_WARM (0x0a)
84 #define PROCENTRY_FLAG_EN 0x01
85 #define PROCENTRY_FLAG_BP 0x02
86 #define IOAPICENTRY_FLAG_EN 0x01
89 /* MP Floating Pointer Structure */
90 typedef struct MPFPS {
103 /* MP Configuration Table Header */
104 typedef struct MPCTH {
106 u_short base_table_length;
110 u_char product_id[12];
111 u_int32_t oem_table_pointer;
112 u_short oem_table_size;
114 u_int32_t apic_address;
115 u_short extended_table_length;
116 u_char extended_table_checksum;
121 typedef struct PROCENTRY {
126 u_int32_t cpu_signature;
127 u_int32_t feature_flags;
132 typedef struct BUSENTRY {
138 typedef struct IOAPICENTRY {
143 u_int32_t apic_address;
144 } *io_apic_entry_ptr;
146 typedef struct INTENTRY {
156 /* descriptions of MP basetable entries */
157 typedef struct BASETABLE_ENTRY {
166 vm_size_t mp_cth_mapsz;
169 typedef int (*mptable_iter_func)(void *, const void *, int);
172 * this code MUST be enabled here and in mpboot.s.
173 * it follows the very early stages of AP boot by placing values in CMOS ram.
174 * it NORMALLY will never be needed and thus the primitive method for enabling.
177 #if defined(CHECK_POINTS)
178 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
179 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
181 #define CHECK_INIT(D); \
182 CHECK_WRITE(0x34, (D)); \
183 CHECK_WRITE(0x35, (D)); \
184 CHECK_WRITE(0x36, (D)); \
185 CHECK_WRITE(0x37, (D)); \
186 CHECK_WRITE(0x38, (D)); \
187 CHECK_WRITE(0x39, (D));
189 #define CHECK_PRINT(S); \
190 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
199 #else /* CHECK_POINTS */
201 #define CHECK_INIT(D)
202 #define CHECK_PRINT(S)
204 #endif /* CHECK_POINTS */
207 * Values to send to the POST hardware.
209 #define MP_BOOTADDRESS_POST 0x10
210 #define MP_PROBE_POST 0x11
211 #define MPTABLE_PASS1_POST 0x12
213 #define MP_START_POST 0x13
214 #define MP_ENABLE_POST 0x14
215 #define MPTABLE_PASS2_POST 0x15
217 #define START_ALL_APS_POST 0x16
218 #define INSTALL_AP_TRAMP_POST 0x17
219 #define START_AP_POST 0x18
221 #define MP_ANNOUNCE_POST 0x19
223 static int madt_probe_test;
224 TUNABLE_INT("hw.madt_probe_test", &madt_probe_test);
226 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
227 int current_postcode;
229 /** XXX FIXME: what system files declare these??? */
230 extern struct region_descriptor r_gdt, r_idt;
232 int mp_naps; /* # of Applications processors */
234 static int mp_nbusses; /* # of busses */
235 int mp_napics; /* # of IO APICs */
238 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
239 u_int32_t *io_apic_versions;
243 u_int32_t cpu_apic_versions[MAXCPU];
245 extern int64_t tsc_offsets[];
247 extern u_long ebda_addr;
250 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
254 * APIC ID logical/physical mapping structures.
255 * We oversize these to simplify boot-time config.
257 int cpu_num_to_apic_id[NAPICID];
259 int io_num_to_apic_id[NAPICID];
261 int apic_id_to_logical[NAPICID];
263 /* AP uses this during bootstrap. Do not staticize. */
268 * SMP page table page. Setup by locore to point to a page table
269 * page from which we allocate per-cpu privatespace areas io_apics,
273 #define IO_MAPPING_START_INDEX \
274 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
276 extern pt_entry_t *SMPpt;
278 struct pcb stoppcbs[MAXCPU];
280 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
282 static basetable_entry basetable_entry_types[] =
284 {0, 20, "Processor"},
292 * Local data and functions.
295 static u_int boot_address;
296 static u_int base_memory;
297 static int mp_finish;
299 static void mp_enable(u_int boot_addr);
301 static int mptable_iterate_entries(const mpcth_t,
302 mptable_iter_func, void *);
303 static int mptable_probe(void);
304 static int mptable_search(void);
305 static int mptable_check(vm_paddr_t);
306 static long mptable_search_sig(u_int32_t target, int count);
307 static int mptable_hyperthread_fixup(u_int, int);
309 static void mptable_pass1(struct mptable_pos *);
310 static void mptable_pass2(struct mptable_pos *);
311 static void mptable_default(int type);
312 static void mptable_fix(void);
314 static int mptable_map(struct mptable_pos *, vm_paddr_t);
315 static void mptable_unmap(struct mptable_pos *);
316 static void mptable_lapic_enumerate(struct mptable_pos *);
317 static void mptable_lapic_default(void);
318 static void mptable_imcr(struct mptable_pos *);
321 static void setup_apic_irq_mapping(void);
322 static int apic_int_is_bus_type(int intr, int bus_type);
324 static int start_all_aps(u_int boot_addr);
326 static void install_ap_tramp(u_int boot_addr);
328 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
329 static int smitest(void);
331 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
332 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
333 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
334 static u_int bootMP_size;
337 * Calculate usable address in base memory for AP trampoline code.
340 mp_bootaddress(u_int basemem)
342 POSTCODE(MP_BOOTADDRESS_POST);
344 base_memory = basemem;
346 bootMP_size = mptramp_end - mptramp_start;
347 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
348 if (((basemem * 1024) - boot_address) < bootMP_size)
349 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
350 /* 3 levels of page table pages */
351 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
353 return mptramp_pagetables;
362 mpfps_paddr = mptable_search();
363 if (mptable_check(mpfps_paddr))
370 * Look for an Intel MP spec table (ie, SMP capable hardware).
379 * Make sure our SMPpt[] page table is big enough to hold all the
382 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
384 POSTCODE(MP_PROBE_POST);
386 /* see if EBDA exists */
387 if (ebda_addr != 0) {
388 /* search first 1K of EBDA */
389 target = (u_int32_t)ebda_addr;
390 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
393 /* last 1K of base memory, effective 'top of base' passed in */
394 target = (u_int32_t)(base_memory - 0x400);
395 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
399 /* search the BIOS */
400 target = (u_int32_t)BIOS_BASE;
401 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
408 struct mptable_check_cbarg {
414 mptable_check_callback(void *xarg, const void *pos, int type)
416 const struct PROCENTRY *ent;
417 struct mptable_check_cbarg *arg = xarg;
423 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
427 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
428 if (arg->found_bsp) {
429 kprintf("more than one BSP in base MP table\n");
438 mptable_check(vm_paddr_t mpfps_paddr)
440 struct mptable_pos mpt;
441 struct mptable_check_cbarg arg;
445 if (mpfps_paddr == 0)
448 error = mptable_map(&mpt, mpfps_paddr);
452 if (mpt.mp_fps->mpfb1 != 0)
460 if (cth->apic_address == 0)
463 bzero(&arg, sizeof(arg));
464 error = mptable_iterate_entries(cth, mptable_check_callback, &arg);
466 if (arg.cpu_count == 0) {
467 kprintf("MP table contains no processor entries\n");
469 } else if (!arg.found_bsp) {
470 kprintf("MP table does not contains BSP entry\n");
480 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
482 int count, total_size;
483 const void *position;
485 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
486 total_size = cth->base_table_length - sizeof(struct MPCTH);
487 position = (const uint8_t *)cth + sizeof(struct MPCTH);
488 count = cth->entry_count;
493 KKASSERT(total_size >= 0);
494 if (total_size == 0) {
495 kprintf("invalid base MP table, "
496 "entry count and length mismatch\n");
500 type = *(const uint8_t *)position;
502 case 0: /* processor_entry */
503 case 1: /* bus_entry */
504 case 2: /* io_apic_entry */
505 case 3: /* int_entry */
506 case 4: /* int_entry */
509 kprintf("unknown base MP table entry type %d\n", type);
513 if (total_size < basetable_entry_types[type].length) {
514 kprintf("invalid base MP table length, "
515 "does not contain all entries\n");
518 total_size -= basetable_entry_types[type].length;
520 error = func(arg, position, type);
524 position = (const uint8_t *)position +
525 basetable_entry_types[type].length;
532 * Startup the SMP processors.
537 POSTCODE(MP_START_POST);
538 mp_enable(boot_address);
543 * Print various information about the SMP system hardware and setup.
550 POSTCODE(MP_ANNOUNCE_POST);
552 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
553 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
554 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
555 for (x = 1; x <= mp_naps; ++x) {
556 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
557 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
561 for (x = 0; x < mp_napics; ++x) {
562 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
563 kprintf(", version: 0x%08x", io_apic_versions[x]);
564 kprintf(", at 0x%08lx\n", io_apic_address[x]);
567 kprintf(" Warning: APIC I/O disabled\n");
572 * AP cpu's call this to sync up protected mode.
574 * WARNING! %gs is not set up on entry. This routine sets up %gs.
580 int x, myid = bootAP;
582 struct mdglobaldata *md;
583 struct privatespace *ps;
585 ps = &CPU_prvspace[myid];
587 gdt_segs[GPROC0_SEL].ssd_base =
588 (long) &ps->mdglobaldata.gd_common_tss;
589 ps->mdglobaldata.mi.gd_prvspace = ps;
591 /* We fill the 32-bit segment descriptors */
592 for (x = 0; x < NGDT; x++) {
593 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
594 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
596 /* And now a 64-bit one */
597 ssdtosyssd(&gdt_segs[GPROC0_SEL],
598 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
600 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
601 r_gdt.rd_base = (long) &gdt[myid * NGDT];
602 lgdt(&r_gdt); /* does magic intra-segment return */
604 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
605 wrmsr(MSR_FSBASE, 0); /* User value */
606 wrmsr(MSR_GSBASE, (u_int64_t)ps);
607 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
613 mdcpu->gd_currentldt = _default_ldt;
616 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
617 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
619 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
621 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
623 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
625 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
626 md->gd_common_tssd = *md->gd_tss_gdt;
628 md->gd_common_tss.tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
633 * Set to a known state:
634 * Set by mpboot.s: CR0_PG, CR0_PE
635 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
638 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
641 /* Set up the fast syscall stuff */
642 msr = rdmsr(MSR_EFER) | EFER_SCE;
643 wrmsr(MSR_EFER, msr);
644 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
645 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
646 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
647 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
648 wrmsr(MSR_STAR, msr);
649 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
651 pmap_set_opt(); /* PSE/4MB pages, etc */
653 /* Initialize the PAT MSR. */
657 /* set up CPU registers and state */
660 /* set up SSE/NX registers */
663 /* set up FPU state on the AP */
664 npxinit(__INITIAL_NPXCW__);
666 /* disable the APIC, just to be SURE */
667 lapic->svr &= ~APIC_SVR_ENABLE;
669 /* data returned to BSP */
670 cpu_apic_versions[0] = lapic->version;
673 /*******************************************************************
674 * local functions and data
678 * start the SMP system
681 mp_enable(u_int boot_addr)
687 vm_paddr_t mpfps_paddr;
688 struct mptable_pos mpt;
690 POSTCODE(MP_ENABLE_POST);
693 * Enumerate Local APIC
698 mpfps_paddr = mptable_probe();
700 mptable_map(&mpt, mpfps_paddr);
701 mptable_lapic_enumerate(&mpt);
705 vm_paddr_t madt_paddr;
706 vm_offset_t lapic_addr;
709 madt_paddr = madt_probe();
711 panic("mp_enable: madt_probe failed\n");
713 lapic_addr = madt_pass1(madt_paddr);
715 panic("mp_enable: no local apic (madt)!\n");
717 lapic_init(lapic_addr);
719 bsp_apic_id = APIC_ID(lapic->id);
720 if (madt_pass2(madt_paddr, bsp_apic_id))
721 panic("mp_enable: madt_pass2 failed\n");
724 mpfps_paddr = mptable_probe();
726 mptable_map(&mpt, mpfps_paddr);
733 panic("no MP table, disable APIC_IO!\n");
735 mptable_map(&mpt, mpfps_paddr);
738 * Examine the MP table for needed info
745 /* Post scan cleanup */
748 setup_apic_irq_mapping();
750 /* fill the LOGICAL io_apic_versions table */
751 for (apic = 0; apic < mp_napics; ++apic) {
752 ux = io_apic_read(apic, IOAPIC_VER);
753 io_apic_versions[apic] = ux;
754 io_apic_set_id(apic, IO_TO_ID(apic));
757 /* program each IO APIC in the system */
758 for (apic = 0; apic < mp_napics; ++apic)
759 if (io_apic_setup(apic) < 0)
760 panic("IO APIC setup failure");
765 * These are required for SMP operation
768 /* install a 'Spurious INTerrupt' vector */
769 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
770 SDT_SYSIGT, SEL_KPL, 0);
772 /* install an inter-CPU IPI for TLB invalidation */
773 setidt(XINVLTLB_OFFSET, Xinvltlb,
774 SDT_SYSIGT, SEL_KPL, 0);
776 /* install an inter-CPU IPI for IPIQ messaging */
777 setidt(XIPIQ_OFFSET, Xipiq,
778 SDT_SYSIGT, SEL_KPL, 0);
780 /* install a timer vector */
781 setidt(XTIMER_OFFSET, Xtimer,
782 SDT_SYSIGT, SEL_KPL, 0);
784 /* install an inter-CPU IPI for CPU stop/restart */
785 setidt(XCPUSTOP_OFFSET, Xcpustop,
786 SDT_SYSIGT, SEL_KPL, 0);
788 /* start each Application Processor */
789 start_all_aps(boot_addr);
794 * look for the MP spec signature
797 /* string defined by the Intel MP Spec as identifying the MP table */
798 #define MP_SIG 0x5f504d5f /* _MP_ */
799 #define NEXT(X) ((X) += 4)
801 mptable_search_sig(u_int32_t target, int count)
807 KKASSERT(target != 0);
809 map_size = count * sizeof(u_int32_t);
810 addr = pmap_mapdev((vm_paddr_t)target, map_size);
813 for (x = 0; x < count; NEXT(x)) {
814 if (addr[x] == MP_SIG) {
815 /* make array index a byte index */
816 ret = target + (x * sizeof(u_int32_t));
821 pmap_unmapdev((vm_offset_t)addr, map_size);
826 typedef struct BUSDATA {
828 enum busTypes bus_type;
831 typedef struct INTDATA {
841 typedef struct BUSTYPENAME {
848 static bus_type_name bus_type_table[] =
854 {UNKNOWN_BUSTYPE, "---"},
857 {UNKNOWN_BUSTYPE, "---"},
858 {UNKNOWN_BUSTYPE, "---"},
859 {UNKNOWN_BUSTYPE, "---"},
860 {UNKNOWN_BUSTYPE, "---"},
861 {UNKNOWN_BUSTYPE, "---"},
863 {UNKNOWN_BUSTYPE, "---"},
864 {UNKNOWN_BUSTYPE, "---"},
865 {UNKNOWN_BUSTYPE, "---"},
866 {UNKNOWN_BUSTYPE, "---"},
868 {UNKNOWN_BUSTYPE, "---"}
871 /* from MP spec v1.4, table 5-1 */
872 static int default_data[7][5] =
874 /* nbus, id0, type0, id1, type1 */
875 {1, 0, ISA, 255, 255},
876 {1, 0, EISA, 255, 255},
877 {1, 0, EISA, 255, 255},
878 {1, 0, MCA, 255, 255},
880 {2, 0, EISA, 1, PCI},
885 static bus_datum *bus_data;
887 /* the IO INT data, one entry per possible APIC INTerrupt */
888 static io_int *io_apic_ints;
893 static int processor_entry (const struct PROCENTRY *entry, int cpu);
895 static int bus_entry (const struct BUSENTRY *entry, int bus);
896 static int io_apic_entry (const struct IOAPICENTRY *entry, int apic);
897 static int int_entry (const struct INTENTRY *entry, int intr);
898 static int lookup_bus_type (char *name);
904 mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
906 const struct IOAPICENTRY *ioapic_ent;
909 case 1: /* bus_entry */
913 case 2: /* io_apic_entry */
915 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
916 io_apic_address[mp_napics++] =
917 (vm_offset_t)ioapic_ent->apic_address;
921 case 3: /* int_entry */
929 * 1st pass on motherboard's Intel MP specification table.
938 mptable_pass1(struct mptable_pos *mpt)
943 POSTCODE(MPTABLE_PASS1_POST);
946 KKASSERT(fps != NULL);
948 /* clear various tables */
949 for (x = 0; x < NAPICID; ++x)
950 io_apic_address[x] = ~0; /* IO APIC address table */
956 /* check for use of 'default' configuration */
957 if (fps->mpfb1 != 0) {
958 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
959 mp_nbusses = default_data[fps->mpfb1 - 1][0];
965 error = mptable_iterate_entries(mpt->mp_cth,
966 mptable_ioapic_pass1_callback, NULL);
968 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
972 struct mptable_ioapic2_cbarg {
979 mptable_ioapic_pass2_callback(void *xarg, const void *pos, int type)
981 struct mptable_ioapic2_cbarg *arg = xarg;
985 if (bus_entry(pos, arg->bus))
990 if (io_apic_entry(pos, arg->apic))
995 if (int_entry(pos, arg->intr))
1003 * 2nd pass on motherboard's Intel MP specification table.
1006 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
1007 * IO_TO_ID(N), logical IO to APIC ID table
1012 mptable_pass2(struct mptable_pos *mpt)
1014 struct mptable_ioapic2_cbarg arg;
1018 POSTCODE(MPTABLE_PASS2_POST);
1021 KKASSERT(fps != NULL);
1023 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
1024 M_DEVBUF, M_WAITOK);
1025 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
1026 M_DEVBUF, M_WAITOK | M_ZERO);
1027 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
1028 M_DEVBUF, M_WAITOK);
1029 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
1030 M_DEVBUF, M_WAITOK);
1032 for (x = 0; x < mp_napics; x++)
1033 ioapic[x] = permanent_io_mapping(io_apic_address[x]);
1035 /* clear various tables */
1036 for (x = 0; x < NAPICID; ++x) {
1037 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
1038 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
1041 /* clear bus data table */
1042 for (x = 0; x < mp_nbusses; ++x)
1043 bus_data[x].bus_id = 0xff;
1045 /* clear IO APIC INT table */
1046 for (x = 0; x < (nintrs + 1); ++x) {
1047 io_apic_ints[x].int_type = 0xff;
1048 io_apic_ints[x].int_vector = 0xff;
1051 /* check for use of 'default' configuration */
1052 if (fps->mpfb1 != 0) {
1053 mptable_default(fps->mpfb1);
1057 bzero(&arg, sizeof(arg));
1058 error = mptable_iterate_entries(mpt->mp_cth,
1059 mptable_ioapic_pass2_callback, &arg);
1061 panic("mptable_iterate_entries(ioapic_pass2) failed\n");
1067 * Check if we should perform a hyperthreading "fix-up" to
1068 * enumerate any logical CPU's that aren't already listed
1071 * XXX: We assume that all of the physical CPUs in the
1072 * system have the same number of logical CPUs.
1074 * XXX: We assume that APIC ID's are allocated such that
1075 * the APIC ID's for a physical processor are aligned
1076 * with the number of logical CPU's in the processor.
1079 mptable_hyperthread_fixup(u_int id_mask, int cpu_count)
1081 int i, id, lcpus_max, logical_cpus;
1083 if ((cpu_feature & CPUID_HTT) == 0)
1086 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1090 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
1092 * INSTRUCTION SET REFERENCE, A-M (#253666)
1093 * Page 3-181, Table 3-20
1094 * "The nearest power-of-2 integer that is not smaller
1095 * than EBX[23:16] is the number of unique initial APIC
1096 * IDs reserved for addressing different logical
1097 * processors in a physical package."
1099 for (i = 0; ; ++i) {
1100 if ((1 << i) >= lcpus_max) {
1107 KKASSERT(cpu_count != 0);
1108 if (cpu_count == lcpus_max) {
1109 /* We have nothing to fix */
1111 } else if (cpu_count == 1) {
1112 /* XXX this may be incorrect */
1113 logical_cpus = lcpus_max;
1115 int cur, prev, dist;
1118 * Calculate the distances between two nearest
1119 * APIC IDs. If all such distances are same,
1120 * then it is the number of missing cpus that
1121 * we are going to fill later.
1123 dist = cur = prev = -1;
1124 for (id = 0; id < MAXCPU; ++id) {
1125 if ((id_mask & 1 << id) == 0)
1130 int new_dist = cur - prev;
1136 * Make sure that all distances
1137 * between two nearest APIC IDs
1140 if (dist != new_dist)
1148 /* Must be power of 2 */
1149 if (dist & (dist - 1))
1152 /* Can't exceed CPU package capacity */
1153 if (dist > lcpus_max)
1154 logical_cpus = lcpus_max;
1156 logical_cpus = dist;
1160 * For each APIC ID of a CPU that is set in the mask,
1161 * scan the other candidate APIC ID's for this
1162 * physical processor. If any of those ID's are
1163 * already in the table, then kill the fixup.
1165 for (id = 0; id < MAXCPU; id++) {
1166 if ((id_mask & 1 << id) == 0)
1168 /* First, make sure we are on a logical_cpus boundary. */
1169 if (id % logical_cpus != 0)
1171 for (i = id + 1; i < id + logical_cpus; i++)
1172 if ((id_mask & 1 << i) != 0)
1175 return logical_cpus;
1179 mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1183 vm_size_t cth_mapsz = 0;
1185 bzero(mpt, sizeof(*mpt));
1187 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1188 if (fps->pap != 0) {
1190 * Map configuration table header to get
1191 * the base table size
1193 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1194 cth_mapsz = cth->base_table_length;
1195 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1197 if (cth_mapsz < sizeof(*cth)) {
1198 kprintf("invalid base MP table length %d\n",
1200 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1205 * Map the base table
1207 cth = pmap_mapdev(fps->pap, cth_mapsz);
1212 mpt->mp_cth_mapsz = cth_mapsz;
1218 mptable_unmap(struct mptable_pos *mpt)
1220 if (mpt->mp_cth != NULL) {
1221 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1223 mpt->mp_cth_mapsz = 0;
1225 if (mpt->mp_fps != NULL) {
1226 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1234 assign_apic_irq(int apic, int intpin, int irq)
1238 if (int_to_apicintpin[irq].ioapic != -1)
1239 panic("assign_apic_irq: inconsistent table");
1241 int_to_apicintpin[irq].ioapic = apic;
1242 int_to_apicintpin[irq].int_pin = intpin;
1243 int_to_apicintpin[irq].apic_address = ioapic[apic];
1244 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1246 for (x = 0; x < nintrs; x++) {
1247 if ((io_apic_ints[x].int_type == 0 ||
1248 io_apic_ints[x].int_type == 3) &&
1249 io_apic_ints[x].int_vector == 0xff &&
1250 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1251 io_apic_ints[x].dst_apic_int == intpin)
1252 io_apic_ints[x].int_vector = irq;
1257 revoke_apic_irq(int irq)
1263 if (int_to_apicintpin[irq].ioapic == -1)
1264 panic("revoke_apic_irq: inconsistent table");
1266 oldapic = int_to_apicintpin[irq].ioapic;
1267 oldintpin = int_to_apicintpin[irq].int_pin;
1269 int_to_apicintpin[irq].ioapic = -1;
1270 int_to_apicintpin[irq].int_pin = 0;
1271 int_to_apicintpin[irq].apic_address = NULL;
1272 int_to_apicintpin[irq].redirindex = 0;
1274 for (x = 0; x < nintrs; x++) {
1275 if ((io_apic_ints[x].int_type == 0 ||
1276 io_apic_ints[x].int_type == 3) &&
1277 io_apic_ints[x].int_vector != 0xff &&
1278 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1279 io_apic_ints[x].dst_apic_int == oldintpin)
1280 io_apic_ints[x].int_vector = 0xff;
1288 allocate_apic_irq(int intr)
1294 if (io_apic_ints[intr].int_vector != 0xff)
1295 return; /* Interrupt handler already assigned */
1297 if (io_apic_ints[intr].int_type != 0 &&
1298 (io_apic_ints[intr].int_type != 3 ||
1299 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1300 io_apic_ints[intr].dst_apic_int == 0)))
1301 return; /* Not INT or ExtInt on != (0, 0) */
1304 while (irq < APIC_INTMAPSIZE &&
1305 int_to_apicintpin[irq].ioapic != -1)
1308 if (irq >= APIC_INTMAPSIZE)
1309 return; /* No free interrupt handlers */
1311 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1312 intpin = io_apic_ints[intr].dst_apic_int;
1314 assign_apic_irq(apic, intpin, irq);
1319 swap_apic_id(int apic, int oldid, int newid)
1326 return; /* Nothing to do */
1328 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1329 apic, oldid, newid);
1331 /* Swap physical APIC IDs in interrupt entries */
1332 for (x = 0; x < nintrs; x++) {
1333 if (io_apic_ints[x].dst_apic_id == oldid)
1334 io_apic_ints[x].dst_apic_id = newid;
1335 else if (io_apic_ints[x].dst_apic_id == newid)
1336 io_apic_ints[x].dst_apic_id = oldid;
1339 /* Swap physical APIC IDs in IO_TO_ID mappings */
1340 for (oapic = 0; oapic < mp_napics; oapic++)
1341 if (IO_TO_ID(oapic) == newid)
1344 if (oapic < mp_napics) {
1345 kprintf("Changing APIC ID for IO APIC #%d from "
1346 "%d to %d in MP table\n",
1347 oapic, newid, oldid);
1348 IO_TO_ID(oapic) = oldid;
1350 IO_TO_ID(apic) = newid;
1355 fix_id_to_io_mapping(void)
1359 for (x = 0; x < NAPICID; x++)
1362 for (x = 0; x <= mp_naps; x++)
1363 if (CPU_TO_ID(x) < NAPICID)
1364 ID_TO_IO(CPU_TO_ID(x)) = x;
1366 for (x = 0; x < mp_napics; x++)
1367 if (IO_TO_ID(x) < NAPICID)
1368 ID_TO_IO(IO_TO_ID(x)) = x;
1373 first_free_apic_id(void)
1377 for (freeid = 0; freeid < NAPICID; freeid++) {
1378 for (x = 0; x <= mp_naps; x++)
1379 if (CPU_TO_ID(x) == freeid)
1383 for (x = 0; x < mp_napics; x++)
1384 if (IO_TO_ID(x) == freeid)
1395 io_apic_id_acceptable(int apic, int id)
1397 int cpu; /* Logical CPU number */
1398 int oapic; /* Logical IO APIC number for other IO APIC */
1401 return 0; /* Out of range */
1403 for (cpu = 0; cpu <= mp_naps; cpu++)
1404 if (CPU_TO_ID(cpu) == id)
1405 return 0; /* Conflict with CPU */
1407 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1408 if (IO_TO_ID(oapic) == id)
1409 return 0; /* Conflict with other APIC */
1411 return 1; /* ID is acceptable for IO APIC */
1416 io_apic_find_int_entry(int apic, int pin)
1420 /* search each of the possible INTerrupt sources */
1421 for (x = 0; x < nintrs; ++x) {
1422 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1423 (pin == io_apic_ints[x].dst_apic_int))
1424 return (&io_apic_ints[x]);
1430 * parse an Intel MP specification table
1437 int apic; /* IO APIC unit number */
1438 int freeid; /* Free physical APIC ID */
1439 int physid; /* Current physical IO APIC ID */
1441 int bus_0 = 0; /* Stop GCC warning */
1442 int bus_pci = 0; /* Stop GCC warning */
1446 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1447 * did it wrong. The MP spec says that when more than 1 PCI bus
1448 * exists the BIOS must begin with bus entries for the PCI bus and use
1449 * actual PCI bus numbering. This implies that when only 1 PCI bus
1450 * exists the BIOS can choose to ignore this ordering, and indeed many
1451 * MP motherboards do ignore it. This causes a problem when the PCI
1452 * sub-system makes requests of the MP sub-system based on PCI bus
1453 * numbers. So here we look for the situation and renumber the
1454 * busses and associated INTs in an effort to "make it right".
1457 /* find bus 0, PCI bus, count the number of PCI busses */
1458 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1459 if (bus_data[x].bus_id == 0) {
1462 if (bus_data[x].bus_type == PCI) {
1468 * bus_0 == slot of bus with ID of 0
1469 * bus_pci == slot of last PCI bus encountered
1472 /* check the 1 PCI bus case for sanity */
1473 /* if it is number 0 all is well */
1474 if (num_pci_bus == 1 &&
1475 bus_data[bus_pci].bus_id != 0) {
1477 /* mis-numbered, swap with whichever bus uses slot 0 */
1479 /* swap the bus entry types */
1480 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1481 bus_data[bus_0].bus_type = PCI;
1483 /* swap each relavant INTerrupt entry */
1484 id = bus_data[bus_pci].bus_id;
1485 for (x = 0; x < nintrs; ++x) {
1486 if (io_apic_ints[x].src_bus_id == id) {
1487 io_apic_ints[x].src_bus_id = 0;
1489 else if (io_apic_ints[x].src_bus_id == 0) {
1490 io_apic_ints[x].src_bus_id = id;
1495 /* Assign IO APIC IDs.
1497 * First try the existing ID. If a conflict is detected, try
1498 * the ID in the MP table. If a conflict is still detected, find
1501 * We cannot use the ID_TO_IO table before all conflicts has been
1502 * resolved and the table has been corrected.
1504 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1506 /* First try to use the value set by the BIOS */
1507 physid = io_apic_get_id(apic);
1508 if (io_apic_id_acceptable(apic, physid)) {
1509 if (IO_TO_ID(apic) != physid)
1510 swap_apic_id(apic, IO_TO_ID(apic), physid);
1514 /* Then check if the value in the MP table is acceptable */
1515 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1518 /* Last resort, find a free APIC ID and use it */
1519 freeid = first_free_apic_id();
1520 if (freeid >= NAPICID)
1521 panic("No free physical APIC IDs found");
1523 if (io_apic_id_acceptable(apic, freeid)) {
1524 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1527 panic("Free physical APIC ID not usable");
1529 fix_id_to_io_mapping();
1531 /* detect and fix broken Compaq MP table */
1532 if (apic_int_type(0, 0) == -1) {
1533 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1534 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1535 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1536 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1537 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1538 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1540 } else if (apic_int_type(0, 0) == 0) {
1541 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1542 for (x = 0; x < nintrs; ++x)
1543 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1544 (0 == io_apic_ints[x].dst_apic_int)) {
1545 io_apic_ints[x].int_type = 3;
1546 io_apic_ints[x].int_vector = 0xff;
1552 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1553 * controllers universally come in pairs. If IRQ 14 is specified
1554 * as an ISA interrupt, then IRQ 15 had better be too.
1556 * [ Shuttle XPC / AMD Athlon X2 ]
1557 * The MPTable is missing an entry for IRQ 15. Note that the
1558 * ACPI table has an entry for both 14 and 15.
1560 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1561 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1562 io14 = io_apic_find_int_entry(0, 14);
1563 io_apic_ints[nintrs] = *io14;
1564 io_apic_ints[nintrs].src_bus_irq = 15;
1565 io_apic_ints[nintrs].dst_apic_int = 15;
1570 /* Assign low level interrupt handlers */
1572 setup_apic_irq_mapping(void)
1578 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1579 int_to_apicintpin[x].ioapic = -1;
1580 int_to_apicintpin[x].int_pin = 0;
1581 int_to_apicintpin[x].apic_address = NULL;
1582 int_to_apicintpin[x].redirindex = 0;
1585 /* First assign ISA/EISA interrupts */
1586 for (x = 0; x < nintrs; x++) {
1587 int_vector = io_apic_ints[x].src_bus_irq;
1588 if (int_vector < APIC_INTMAPSIZE &&
1589 io_apic_ints[x].int_vector == 0xff &&
1590 int_to_apicintpin[int_vector].ioapic == -1 &&
1591 (apic_int_is_bus_type(x, ISA) ||
1592 apic_int_is_bus_type(x, EISA)) &&
1593 io_apic_ints[x].int_type == 0) {
1594 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1595 io_apic_ints[x].dst_apic_int,
1600 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1601 for (x = 0; x < nintrs; x++) {
1602 if (io_apic_ints[x].dst_apic_int == 0 &&
1603 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1604 io_apic_ints[x].int_vector == 0xff &&
1605 int_to_apicintpin[0].ioapic == -1 &&
1606 io_apic_ints[x].int_type == 3) {
1607 assign_apic_irq(0, 0, 0);
1612 /* Assign PCI interrupts */
1613 for (x = 0; x < nintrs; ++x) {
1614 if (io_apic_ints[x].int_type == 0 &&
1615 io_apic_ints[x].int_vector == 0xff &&
1616 apic_int_is_bus_type(x, PCI))
1617 allocate_apic_irq(x);
1624 mp_set_cpuids(int cpu_id, int apic_id)
1626 CPU_TO_ID(cpu_id) = apic_id;
1627 ID_TO_CPU(apic_id) = cpu_id;
1631 processor_entry(const struct PROCENTRY *entry, int cpu)
1635 /* check for usability */
1636 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1639 /* check for BSP flag */
1640 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1641 mp_set_cpuids(0, entry->apic_id);
1642 return 0; /* its already been counted */
1645 /* add another AP to list, if less than max number of CPUs */
1646 else if (cpu < MAXCPU) {
1647 mp_set_cpuids(cpu, entry->apic_id);
1657 bus_entry(const struct BUSENTRY *entry, int bus)
1662 /* encode the name into an index */
1663 for (x = 0; x < 6; ++x) {
1664 if ((c = entry->bus_type[x]) == ' ')
1670 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1671 panic("unknown bus type: '%s'", name);
1673 bus_data[bus].bus_id = entry->bus_id;
1674 bus_data[bus].bus_type = x;
1680 io_apic_entry(const struct IOAPICENTRY *entry, int apic)
1682 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1685 IO_TO_ID(apic) = entry->apic_id;
1686 ID_TO_IO(entry->apic_id) = apic;
1692 lookup_bus_type(char *name)
1696 for (x = 0; x < MAX_BUSTYPE; ++x)
1697 if (strcmp(bus_type_table[x].name, name) == 0)
1698 return bus_type_table[x].type;
1700 return UNKNOWN_BUSTYPE;
1704 int_entry(const struct INTENTRY *entry, int intr)
1708 io_apic_ints[intr].int_type = entry->int_type;
1709 io_apic_ints[intr].int_flags = entry->int_flags;
1710 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1711 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1712 if (entry->dst_apic_id == 255) {
1713 /* This signal goes to all IO APICS. Select an IO APIC
1714 with sufficient number of interrupt pins */
1715 for (apic = 0; apic < mp_napics; apic++)
1716 if (((io_apic_read(apic, IOAPIC_VER) &
1717 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1718 entry->dst_apic_int)
1720 if (apic < mp_napics)
1721 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1723 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1725 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1726 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1732 apic_int_is_bus_type(int intr, int bus_type)
1736 for (bus = 0; bus < mp_nbusses; ++bus)
1737 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1738 && ((int) bus_data[bus].bus_type == bus_type))
1745 * Given a traditional ISA INT mask, return an APIC mask.
1748 isa_apic_mask(u_int isa_mask)
1753 #if defined(SKIP_IRQ15_REDIRECT)
1754 if (isa_mask == (1 << 15)) {
1755 kprintf("skipping ISA IRQ15 redirect\n");
1758 #endif /* SKIP_IRQ15_REDIRECT */
1760 isa_irq = ffs(isa_mask); /* find its bit position */
1761 if (isa_irq == 0) /* doesn't exist */
1763 --isa_irq; /* make it zero based */
1765 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1769 return (1 << apic_pin); /* convert pin# to a mask */
1773 * Determine which APIC pin an ISA/EISA INT is attached to.
1775 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1776 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1777 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1778 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1780 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1782 isa_apic_irq(int isa_irq)
1786 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1787 if (INTTYPE(intr) == 0) { /* standard INT */
1788 if (SRCBUSIRQ(intr) == isa_irq) {
1789 if (apic_int_is_bus_type(intr, ISA) ||
1790 apic_int_is_bus_type(intr, EISA)) {
1791 if (INTIRQ(intr) == 0xff)
1792 return -1; /* unassigned */
1793 return INTIRQ(intr); /* found */
1798 return -1; /* NOT found */
1803 * Determine which APIC pin a PCI INT is attached to.
1805 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1806 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1807 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1809 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1813 --pciInt; /* zero based */
1815 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1816 if ((INTTYPE(intr) == 0) /* standard INT */
1817 && (SRCBUSID(intr) == pciBus)
1818 && (SRCBUSDEVICE(intr) == pciDevice)
1819 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1820 if (apic_int_is_bus_type(intr, PCI)) {
1821 if (INTIRQ(intr) == 0xff) {
1822 kprintf("IOAPIC: pci_apic_irq() "
1824 return -1; /* unassigned */
1826 return INTIRQ(intr); /* exact match */
1831 return -1; /* NOT found */
1835 next_apic_irq(int irq)
1842 for (intr = 0; intr < nintrs; intr++) {
1843 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1845 bus = SRCBUSID(intr);
1846 bustype = apic_bus_type(bus);
1847 if (bustype != ISA &&
1853 if (intr >= nintrs) {
1856 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1857 if (INTTYPE(ointr) != 0)
1859 if (bus != SRCBUSID(ointr))
1861 if (bustype == PCI) {
1862 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1864 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1867 if (bustype == ISA || bustype == EISA) {
1868 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1871 if (INTPIN(intr) == INTPIN(ointr))
1875 if (ointr >= nintrs) {
1878 return INTIRQ(ointr);
1893 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1896 * Exactly what this means is unclear at this point. It is a solution
1897 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1898 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1899 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1903 undirect_isa_irq(int rirq)
1907 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1908 /** FIXME: tickle the MB redirector chip */
1912 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1919 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1922 undirect_pci_irq(int rirq)
1926 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1928 /** FIXME: tickle the MB redirector chip */
1932 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1942 * given a bus ID, return:
1943 * the bus type if found
1947 apic_bus_type(int id)
1951 for (x = 0; x < mp_nbusses; ++x)
1952 if (bus_data[x].bus_id == id)
1953 return bus_data[x].bus_type;
1959 * given a LOGICAL APIC# and pin#, return:
1960 * the associated src bus ID if found
1964 apic_src_bus_id(int apic, int pin)
1968 /* search each of the possible INTerrupt sources */
1969 for (x = 0; x < nintrs; ++x)
1970 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1971 (pin == io_apic_ints[x].dst_apic_int))
1972 return (io_apic_ints[x].src_bus_id);
1974 return -1; /* NOT found */
1978 * given a LOGICAL APIC# and pin#, return:
1979 * the associated src bus IRQ if found
1983 apic_src_bus_irq(int apic, int pin)
1987 for (x = 0; x < nintrs; x++)
1988 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1989 (pin == io_apic_ints[x].dst_apic_int))
1990 return (io_apic_ints[x].src_bus_irq);
1992 return -1; /* NOT found */
1997 * given a LOGICAL APIC# and pin#, return:
1998 * the associated INTerrupt type if found
2002 apic_int_type(int apic, int pin)
2006 /* search each of the possible INTerrupt sources */
2007 for (x = 0; x < nintrs; ++x) {
2008 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2009 (pin == io_apic_ints[x].dst_apic_int))
2010 return (io_apic_ints[x].int_type);
2012 return -1; /* NOT found */
2016 * Return the IRQ associated with an APIC pin
2019 apic_irq(int apic, int pin)
2024 for (x = 0; x < nintrs; ++x) {
2025 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2026 (pin == io_apic_ints[x].dst_apic_int)) {
2027 res = io_apic_ints[x].int_vector;
2030 if (apic != int_to_apicintpin[res].ioapic)
2031 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
2032 if (pin != int_to_apicintpin[res].int_pin)
2033 panic("apic_irq inconsistent table (2)");
2042 * given a LOGICAL APIC# and pin#, return:
2043 * the associated trigger mode if found
2047 apic_trigger(int apic, int pin)
2051 /* search each of the possible INTerrupt sources */
2052 for (x = 0; x < nintrs; ++x)
2053 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2054 (pin == io_apic_ints[x].dst_apic_int))
2055 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
2057 return -1; /* NOT found */
2062 * given a LOGICAL APIC# and pin#, return:
2063 * the associated 'active' level if found
2067 apic_polarity(int apic, int pin)
2071 /* search each of the possible INTerrupt sources */
2072 for (x = 0; x < nintrs; ++x)
2073 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2074 (pin == io_apic_ints[x].dst_apic_int))
2075 return (io_apic_ints[x].int_flags & 0x03);
2077 return -1; /* NOT found */
2081 * set data according to MP defaults
2082 * FIXME: probably not complete yet...
2085 mptable_default(int type)
2091 kprintf(" MP default config type: %d\n", type);
2094 kprintf(" bus: ISA, APIC: 82489DX\n");
2097 kprintf(" bus: EISA, APIC: 82489DX\n");
2100 kprintf(" bus: EISA, APIC: 82489DX\n");
2103 kprintf(" bus: MCA, APIC: 82489DX\n");
2106 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2109 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2112 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2115 kprintf(" future type\n");
2121 /* one and only IO APIC */
2122 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2125 * sanity check, refer to MP spec section 3.6.6, last paragraph
2126 * necessary as some hardware isn't properly setting up the IO APIC
2128 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2129 if (io_apic_id != 2) {
2131 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2132 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2133 io_apic_set_id(0, 2);
2136 IO_TO_ID(0) = io_apic_id;
2137 ID_TO_IO(io_apic_id) = 0;
2139 /* fill out bus entries */
2148 bus_data[0].bus_id = default_data[type - 1][1];
2149 bus_data[0].bus_type = default_data[type - 1][2];
2150 bus_data[1].bus_id = default_data[type - 1][3];
2151 bus_data[1].bus_type = default_data[type - 1][4];
2154 /* case 4: case 7: MCA NOT supported */
2155 default: /* illegal/reserved */
2156 panic("BAD default MP config: %d", type);
2160 /* general cases from MP v1.4, table 5-2 */
2161 for (pin = 0; pin < 16; ++pin) {
2162 io_apic_ints[pin].int_type = 0;
2163 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2164 io_apic_ints[pin].src_bus_id = 0;
2165 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2166 io_apic_ints[pin].dst_apic_id = io_apic_id;
2167 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2170 /* special cases from MP v1.4, table 5-2 */
2172 io_apic_ints[2].int_type = 0xff; /* N/C */
2173 io_apic_ints[13].int_type = 0xff; /* N/C */
2174 #if !defined(APIC_MIXED_MODE)
2176 panic("sorry, can't support type 2 default yet");
2177 #endif /* APIC_MIXED_MODE */
2180 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2183 io_apic_ints[0].int_type = 0xff; /* N/C */
2185 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2188 #endif /* APIC_IO */
2191 * Map a physical memory address representing I/O into KVA. The I/O
2192 * block is assumed not to cross a page boundary.
2195 permanent_io_mapping(vm_paddr_t pa)
2197 KKASSERT(pa < 0x100000000LL);
2199 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
2203 * start each AP in our list
2206 start_all_aps(u_int boot_addr)
2208 vm_offset_t va = boot_address + KERNBASE;
2209 u_int64_t *pt4, *pt3, *pt2;
2215 u_char mpbiosreason;
2216 u_long mpbioswarmvec;
2217 struct mdglobaldata *gd;
2218 struct privatespace *ps;
2220 POSTCODE(START_ALL_APS_POST);
2222 /* Initialize BSP's local APIC */
2223 apic_initialize(TRUE);
2225 /* install the AP 1st level boot code */
2226 pmap_kenter(va, boot_address);
2227 cpu_invlpg((void *)va); /* JG XXX */
2228 bcopy(mptramp_start, (void *)va, bootMP_size);
2230 /* Locate the page tables, they'll be below the trampoline */
2231 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
2232 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
2233 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
2235 /* Create the initial 1GB replicated page tables */
2236 for (i = 0; i < 512; i++) {
2237 /* Each slot of the level 4 pages points to the same level 3 page */
2238 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
2239 pt4[i] |= PG_V | PG_RW | PG_U;
2241 /* Each slot of the level 3 pages points to the same level 2 page */
2242 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
2243 pt3[i] |= PG_V | PG_RW | PG_U;
2245 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
2246 pt2[i] = i * (2 * 1024 * 1024);
2247 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
2250 /* save the current value of the warm-start vector */
2251 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
2252 outb(CMOS_REG, BIOS_RESET);
2253 mpbiosreason = inb(CMOS_DATA);
2255 /* setup a vector to our boot code */
2256 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2257 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
2258 outb(CMOS_REG, BIOS_RESET);
2259 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2262 * If we have a TSC we can figure out the SMI interrupt rate.
2263 * The SMI does not necessarily use a constant rate. Spend
2264 * up to 250ms trying to figure it out.
2267 if (cpu_feature & CPUID_TSC) {
2268 set_apic_timer(275000);
2269 smilast = read_apic_timer();
2270 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2271 smicount = smitest();
2272 if (smibest == 0 || smilast - smicount < smibest)
2273 smibest = smilast - smicount;
2276 if (smibest > 250000)
2279 smibest = smibest * (int64_t)1000000 /
2280 get_apic_timer_frequency();
2284 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2285 1000000 / smibest, smibest);
2288 for (x = 1; x <= mp_naps; ++x) {
2290 /* This is a bit verbose, it will go away soon. */
2292 /* first page of AP's private space */
2293 pg = x * x86_64_btop(sizeof(struct privatespace));
2295 /* allocate new private data page(s) */
2296 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2297 MDGLOBALDATA_BASEALLOC_SIZE);
2299 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2300 bzero(gd, sizeof(*gd));
2301 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2303 /* prime data page for it to use */
2304 mi_gdinit(&gd->mi, x);
2306 gd->gd_CMAP1 = &SMPpt[pg + 0];
2307 gd->gd_CMAP2 = &SMPpt[pg + 1];
2308 gd->gd_CMAP3 = &SMPpt[pg + 2];
2309 gd->gd_PMAP1 = &SMPpt[pg + 3];
2310 gd->gd_CADDR1 = ps->CPAGE1;
2311 gd->gd_CADDR2 = ps->CPAGE2;
2312 gd->gd_CADDR3 = ps->CPAGE3;
2313 gd->gd_PADDR1 = (pt_entry_t *)ps->PPAGE1;
2314 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2315 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2317 /* setup a vector to our boot code */
2318 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2319 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2320 outb(CMOS_REG, BIOS_RESET);
2321 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2324 * Setup the AP boot stack
2326 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2329 /* attempt to start the Application Processor */
2330 CHECK_INIT(99); /* setup checkpoints */
2331 if (!start_ap(gd, boot_addr, smibest)) {
2332 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2333 CHECK_PRINT("trace"); /* show checkpoints */
2334 /* better panic as the AP may be running loose */
2335 kprintf("panic y/n? [y] ");
2336 if (cngetc() != 'n')
2339 CHECK_PRINT("trace"); /* show checkpoints */
2341 /* record its version info */
2342 cpu_apic_versions[x] = cpu_apic_versions[0];
2345 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2348 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2349 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2352 ncpus2_shift = shift;
2353 ncpus2 = 1 << shift;
2354 ncpus2_mask = ncpus2 - 1;
2356 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2357 if ((1 << shift) < ncpus)
2359 ncpus_fit = 1 << shift;
2360 ncpus_fit_mask = ncpus_fit - 1;
2362 /* build our map of 'other' CPUs */
2363 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2364 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2365 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2367 /* fill in our (BSP) APIC version */
2368 cpu_apic_versions[0] = lapic->version;
2370 /* restore the warmstart vector */
2371 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2372 outb(CMOS_REG, BIOS_RESET);
2373 outb(CMOS_DATA, mpbiosreason);
2376 * NOTE! The idlestack for the BSP was setup by locore. Finish
2377 * up, clean out the P==V mapping we did earlier.
2381 /* number of APs actually started */
2387 * load the 1st level AP boot code into base memory.
2390 /* targets for relocation */
2391 extern void bigJump(void);
2392 extern void bootCodeSeg(void);
2393 extern void bootDataSeg(void);
2394 extern void MPentry(void);
2395 extern u_int MP_GDT;
2396 extern u_int mp_gdtbase;
2401 install_ap_tramp(u_int boot_addr)
2404 int size = *(int *) ((u_long) & bootMP_size);
2405 u_char *src = (u_char *) ((u_long) bootMP);
2406 u_char *dst = (u_char *) boot_addr + KERNBASE;
2407 u_int boot_base = (u_int) bootMP;
2412 POSTCODE(INSTALL_AP_TRAMP_POST);
2414 for (x = 0; x < size; ++x)
2418 * modify addresses in code we just moved to basemem. unfortunately we
2419 * need fairly detailed info about mpboot.s for this to work. changes
2420 * to mpboot.s might require changes here.
2423 /* boot code is located in KERNEL space */
2424 dst = (u_char *) boot_addr + KERNBASE;
2426 /* modify the lgdt arg */
2427 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2428 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2430 /* modify the ljmp target for MPentry() */
2431 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2432 *dst32 = ((u_int) MPentry - KERNBASE);
2434 /* modify the target for boot code segment */
2435 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2436 dst8 = (u_int8_t *) (dst16 + 1);
2437 *dst16 = (u_int) boot_addr & 0xffff;
2438 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2440 /* modify the target for boot data segment */
2441 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2442 dst8 = (u_int8_t *) (dst16 + 1);
2443 *dst16 = (u_int) boot_addr & 0xffff;
2444 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2450 * This function starts the AP (application processor) identified
2451 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2452 * to accomplish this. This is necessary because of the nuances
2453 * of the different hardware we might encounter. It ain't pretty,
2454 * but it seems to work.
2456 * NOTE: eventually an AP gets to ap_init(), which is called just
2457 * before the AP goes into the LWKT scheduler's idle loop.
2460 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2464 u_long icr_lo, icr_hi;
2466 POSTCODE(START_AP_POST);
2468 /* get the PHYSICAL APIC ID# */
2469 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2471 /* calculate the vector */
2472 vector = (boot_addr >> 12) & 0xff;
2474 /* We don't want anything interfering */
2477 /* Make sure the target cpu sees everything */
2481 * Try to detect when a SMI has occurred, wait up to 200ms.
2483 * If a SMI occurs during an AP reset but before we issue
2484 * the STARTUP command, the AP may brick. To work around
2485 * this problem we hold off doing the AP startup until
2486 * after we have detected the SMI. Hopefully another SMI
2487 * will not occur before we finish the AP startup.
2489 * Retries don't seem to help. SMIs have a window of opportunity
2490 * and if USB->legacy keyboard emulation is enabled in the BIOS
2491 * the interrupt rate can be quite high.
2493 * NOTE: Don't worry about the L1 cache load, it might bloat
2494 * ldelta a little but ndelta will be so huge when the SMI
2495 * occurs the detection logic will still work fine.
2498 set_apic_timer(200000);
2503 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2504 * and running the target CPU. OR this INIT IPI might be latched (P5
2505 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2508 * see apic/apicreg.h for icr bit definitions.
2510 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2514 * Setup the address for the target AP. We can setup
2515 * icr_hi once and then just trigger operations with
2518 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2519 icr_hi |= (physical_cpu << 24);
2520 icr_lo = lapic->icr_lo & 0xfff00000;
2521 lapic->icr_hi = icr_hi;
2524 * Do an INIT IPI: assert RESET
2526 * Use edge triggered mode to assert INIT
2528 lapic->icr_lo = icr_lo | 0x00004500;
2529 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2533 * The spec calls for a 10ms delay but we may have to use a
2534 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2535 * interrupt. We have other loops here too and dividing by 2
2536 * doesn't seem to be enough even after subtracting 350us,
2537 * so we divide by 4.
2539 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2540 * interrupt was detected we use the full 10ms.
2544 else if (smibest < 150 * 4 + 350)
2546 else if ((smibest - 350) / 4 < 10000)
2547 u_sleep((smibest - 350) / 4);
2552 * Do an INIT IPI: deassert RESET
2554 * Use level triggered mode to deassert. It is unclear
2555 * why we need to do this.
2557 lapic->icr_lo = icr_lo | 0x00008500;
2558 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2560 u_sleep(150); /* wait 150us */
2563 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2564 * latched, (P5 bug) this 1st STARTUP would then terminate
2565 * immediately, and the previously started INIT IPI would continue. OR
2566 * the previous INIT IPI has already run. and this STARTUP IPI will
2567 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2570 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2571 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2573 u_sleep(200); /* wait ~200uS */
2576 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2577 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2578 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2579 * recognized after hardware RESET or INIT IPI.
2581 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2582 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2585 /* Resume normal operation */
2588 /* wait for it to start, see ap_init() */
2589 set_apic_timer(5000000);/* == 5 seconds */
2590 while (read_apic_timer()) {
2591 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2592 return 1; /* return SUCCESS */
2595 return 0; /* return FAILURE */
2610 while (read_apic_timer()) {
2612 for (count = 0; count < 100; ++count)
2613 ntsc = rdtsc(); /* force loop to occur */
2615 ndelta = ntsc - ltsc;
2616 if (ldelta > ndelta)
2618 if (ndelta > ldelta * 2)
2621 ldelta = ntsc - ltsc;
2624 return(read_apic_timer());
2628 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2630 * If for some reason we were unable to start all cpus we cannot safely
2631 * use broadcast IPIs.
2637 if (smp_startup_mask == smp_active_mask) {
2638 all_but_self_ipi(XINVLTLB_OFFSET);
2640 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2641 APIC_DELMODE_FIXED);
2647 * When called the executing CPU will send an IPI to all other CPUs
2648 * requesting that they halt execution.
2650 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2652 * - Signals all CPUs in map to stop.
2653 * - Waits for each to stop.
2660 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2661 * from executing at same time.
2664 stop_cpus(u_int map)
2666 map &= smp_active_mask;
2668 /* send the Xcpustop IPI to all CPUs in map */
2669 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2671 while ((stopped_cpus & map) != map)
2679 * Called by a CPU to restart stopped CPUs.
2681 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2683 * - Signals all CPUs in map to restart.
2684 * - Waits for each to restart.
2692 restart_cpus(u_int map)
2694 /* signal other cpus to restart */
2695 started_cpus = map & smp_active_mask;
2697 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2704 * This is called once the mpboot code has gotten us properly relocated
2705 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2706 * and when it returns the scheduler will call the real cpu_idle() main
2707 * loop for the idlethread. Interrupts are disabled on entry and should
2708 * remain disabled at return.
2716 * Adjust smp_startup_mask to signal the BSP that we have started
2717 * up successfully. Note that we do not yet hold the BGL. The BSP
2718 * is waiting for our signal.
2720 * We can't set our bit in smp_active_mask yet because we are holding
2721 * interrupts physically disabled and remote cpus could deadlock
2722 * trying to send us an IPI.
2724 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2728 * Interlock for finalization. Wait until mp_finish is non-zero,
2729 * then get the MP lock.
2731 * Note: We are in a critical section.
2733 * Note: We have to synchronize td_mpcount to our desired MP state
2734 * before calling cpu_try_mplock().
2736 * Note: we are the idle thread, we can only spin.
2738 * Note: The load fence is memory volatile and prevents the compiler
2739 * from improperly caching mp_finish, and the cpu from improperly
2742 while (mp_finish == 0)
2744 ++curthread->td_mpcount;
2745 while (cpu_try_mplock() == 0)
2748 if (cpu_feature & CPUID_TSC) {
2750 * The BSP is constantly updating tsc0_offset, figure out the
2751 * relative difference to synchronize ktrdump.
2753 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2756 /* BSP may have changed PTD while we're waiting for the lock */
2759 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2763 /* Build our map of 'other' CPUs. */
2764 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2766 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2768 /* A quick check from sanity claus */
2769 apic_id = (apic_id_to_logical[(lapic->id & 0x0f000000) >> 24]);
2770 if (mycpu->gd_cpuid != apic_id) {
2771 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2772 kprintf("SMP: apic_id = %d\n", apic_id);
2774 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2776 panic("cpuid mismatch! boom!!");
2779 /* Initialize AP's local APIC for irq's */
2780 apic_initialize(FALSE);
2782 /* Set memory range attributes for this CPU to match the BSP */
2783 mem_range_AP_init();
2786 * Once we go active we must process any IPIQ messages that may
2787 * have been queued, because no actual IPI will occur until we
2788 * set our bit in the smp_active_mask. If we don't the IPI
2789 * message interlock could be left set which would also prevent
2792 * The idle loop doesn't expect the BGL to be held and while
2793 * lwkt_switch() normally cleans things up this is a special case
2794 * because we returning almost directly into the idle loop.
2796 * The idle thread is never placed on the runq, make sure
2797 * nothing we've done put it there.
2799 KKASSERT(curthread->td_mpcount == 1);
2800 smp_active_mask |= 1 << mycpu->gd_cpuid;
2803 * Enable interrupts here. idle_restore will also do it, but
2804 * doing it here lets us clean up any strays that got posted to
2805 * the CPU during the AP boot while we are still in a critical
2808 __asm __volatile("sti; pause; pause"::);
2809 mdcpu->gd_fpending = 0;
2811 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2812 lwkt_process_ipiq();
2815 * Releasing the mp lock lets the BSP finish up the SMP init
2818 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2822 * Get SMP fully working before we start initializing devices.
2830 kprintf("Finish MP startup\n");
2831 if (cpu_feature & CPUID_TSC)
2832 tsc0_offset = rdtsc();
2835 while (smp_active_mask != smp_startup_mask) {
2837 if (cpu_feature & CPUID_TSC)
2838 tsc0_offset = rdtsc();
2840 while (try_mplock() == 0)
2843 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2846 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2849 cpu_send_ipiq(int dcpu)
2851 if ((1 << dcpu) & smp_active_mask)
2852 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2855 #if 0 /* single_apic_ipi_passive() not working yet */
2857 * Returns 0 on failure, 1 on success
2860 cpu_send_ipiq_passive(int dcpu)
2863 if ((1 << dcpu) & smp_active_mask) {
2864 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2865 APIC_DELMODE_FIXED);
2871 struct mptable_lapic_cbarg1 {
2874 u_int ht_apicid_mask;
2878 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2880 const struct PROCENTRY *ent;
2881 struct mptable_lapic_cbarg1 *arg = xarg;
2887 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2891 if (ent->apic_id < 32) {
2892 arg->ht_apicid_mask |= 1 << ent->apic_id;
2893 } else if (arg->ht_fixup) {
2894 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2900 struct mptable_lapic_cbarg2 {
2907 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2909 const struct PROCENTRY *ent;
2910 struct mptable_lapic_cbarg2 *arg = xarg;
2916 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2917 KKASSERT(!arg->found_bsp);
2921 if (processor_entry(ent, arg->cpu))
2924 if (arg->logical_cpus) {
2925 struct PROCENTRY proc;
2929 * Create fake mptable processor entries
2930 * and feed them to processor_entry() to
2931 * enumerate the logical CPUs.
2933 bzero(&proc, sizeof(proc));
2935 proc.cpu_flags = PROCENTRY_FLAG_EN;
2936 proc.apic_id = ent->apic_id;
2938 for (i = 1; i < arg->logical_cpus; i++) {
2940 processor_entry(&proc, arg->cpu);
2948 mptable_lapic_default(void)
2950 int ap_apicid, bsp_apicid;
2952 mp_naps = 1; /* exclude BSP */
2954 /* Map local apic before the id field is accessed */
2955 lapic_init(DEFAULT_APIC_BASE);
2957 bsp_apicid = APIC_ID(lapic->id);
2958 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
2961 mp_set_cpuids(0, bsp_apicid);
2962 /* one and only AP */
2963 mp_set_cpuids(1, ap_apicid);
2969 * ID_TO_CPU(N), APIC ID to logical CPU table
2970 * CPU_TO_ID(N), logical CPU to APIC ID table
2973 mptable_lapic_enumerate(struct mptable_pos *mpt)
2975 struct mptable_lapic_cbarg1 arg1;
2976 struct mptable_lapic_cbarg2 arg2;
2978 int error, logical_cpus = 0;
2979 vm_offset_t lapic_addr;
2981 KKASSERT(mpt->mp_fps != NULL);
2984 * Check for use of 'default' configuration
2986 if (mpt->mp_fps->mpfb1 != 0) {
2987 mptable_lapic_default();
2992 KKASSERT(cth != NULL);
2994 /* Save local apic address */
2995 lapic_addr = (vm_offset_t)cth->apic_address;
2996 KKASSERT(lapic_addr != 0);
2999 * Find out how many CPUs do we have
3001 bzero(&arg1, sizeof(arg1));
3002 arg1.ht_fixup = 1; /* Apply ht fixup by default */
3004 error = mptable_iterate_entries(cth,
3005 mptable_lapic_pass1_callback, &arg1);
3007 panic("mptable_iterate_entries(lapic_pass1) failed\n");
3008 KKASSERT(arg1.cpu_count != 0);
3010 /* See if we need to fixup HT logical CPUs. */
3011 if (arg1.ht_fixup) {
3012 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
3014 if (logical_cpus != 0)
3015 arg1.cpu_count *= logical_cpus;
3017 mp_naps = arg1.cpu_count;
3019 /* Qualify the numbers again, after possible HT fixup */
3020 if (mp_naps > MAXCPU) {
3021 kprintf("Warning: only using %d of %d available CPUs!\n",
3026 --mp_naps; /* subtract the BSP */
3029 * Link logical CPU id to local apic id
3031 bzero(&arg2, sizeof(arg2));
3033 arg2.logical_cpus = logical_cpus;
3035 error = mptable_iterate_entries(cth,
3036 mptable_lapic_pass2_callback, &arg2);
3038 panic("mptable_iterate_entries(lapic_pass2) failed\n");
3039 KKASSERT(arg2.found_bsp);
3041 /* Map local apic */
3042 lapic_init(lapic_addr);
3046 mptable_imcr(struct mptable_pos *mpt)
3048 /* record whether PIC or virtual-wire mode */
3049 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT,
3050 mpt->mp_fps->mpfb2 & 0x80);