sys/dev/drm/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  *
  26  * $FreeBSD: head/sys/dev/drm2/radeon/radeon_atombios.c 254885 2013-08-25 19:37:15Z dumbbell $
  27  */
  28
  29 #include <drm/drmP.h>
  30 #include <uapi_drm/radeon_drm.h>
  31 #include "radeon.h"
  32 #include "radeon_asic.h" /* Declares several prototypes; clang is pleased. */
  33
  34 #include "atom.h"
  35 #include "atom-bits.h"
  36
  37 /* local */
  38 static int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
  39                                     u16 voltage_id, u16 *voltage);
  40
  41 union atom_supported_devices {
  42         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  43         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  44         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  45 };
  46
  47 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
  48                                           ATOM_GPIO_I2C_ASSIGMENT *gpio,
  49                                           u8 index)
  50 {
  51         /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
  52         if ((rdev->family == CHIP_R420) ||
  53             (rdev->family == CHIP_R423) ||
  54             (rdev->family == CHIP_RV410)) {
  55                 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
  56                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
  57                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
  58                         gpio->ucClkMaskShift = 0x19;
  59                         gpio->ucDataMaskShift = 0x18;
  60                 }
  61         }
  62
  63         /* some evergreen boards have bad data for this entry */
  64         if (ASIC_IS_DCE4(rdev)) {
  65                 if ((index == 7) &&
  66                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
  67                     (gpio->sucI2cId.ucAccess == 0)) {
  68                         gpio->sucI2cId.ucAccess = 0x97;
  69                         gpio->ucDataMaskShift = 8;
  70                         gpio->ucDataEnShift = 8;
  71                         gpio->ucDataY_Shift = 8;
  72                         gpio->ucDataA_Shift = 8;
  73                 }
  74         }
  75
  76         /* some DCE3 boards have bad data for this entry */
  77         if (ASIC_IS_DCE3(rdev)) {
  78                 if ((index == 4) &&
  79                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
  80                     (gpio->sucI2cId.ucAccess == 0x94))
  81                         gpio->sucI2cId.ucAccess = 0x14;
  82         }
  83 }
  84
  85 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
  86 {
  87         struct radeon_i2c_bus_rec i2c;
  88
  89         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
  90
  91         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
  92         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
  93         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
  94         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
  95         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
  96         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
  97         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
  98         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
  99         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
 100         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
 101         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
 102         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
 103         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 104         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 105         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 106         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 107
 108         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 109                 i2c.hw_capable = true;
 110         else
 111                 i2c.hw_capable = false;
 112
 113         if (gpio->sucI2cId.ucAccess == 0xa0)
 114                 i2c.mm_i2c = true;
 115         else
 116                 i2c.mm_i2c = false;
 117
 118         i2c.i2c_id = gpio->sucI2cId.ucAccess;
 119
 120         if (i2c.mask_clk_reg)
 121                 i2c.valid = true;
 122         else
 123                 i2c.valid = false;
 124
 125         return i2c;
 126 }
 127
 128 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
 129                                                                uint8_t id)
 130 {
 131         struct atom_context *ctx = rdev->mode_info.atom_context;
 132         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 133         struct radeon_i2c_bus_rec i2c;
 134         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 135         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 136         uint16_t data_offset, size;
 137         int i, num_indices;
 138
 139         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
 140         i2c.valid = false;
 141
 142         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 143                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)((char *)ctx->bios + data_offset);
 144
 145                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 146                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 147
 148                 for (i = 0; i < num_indices; i++) {
 149                         gpio = &i2c_info->asGPIO_Info[i];
 150
 151                         radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
 152
 153                         if (gpio->sucI2cId.ucAccess == id) {
 154                                 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
 155                                 break;
 156                         }
 157                 }
 158         }
 159
 160         return i2c;
 161 }
 162
 163 void radeon_atombios_i2c_init(struct radeon_device *rdev)
 164 {
 165         struct atom_context *ctx = rdev->mode_info.atom_context;
 166         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 167         struct radeon_i2c_bus_rec i2c;
 168         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 169         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 170         uint16_t data_offset, size;
 171         int i, num_indices;
 172         char stmp[32];
 173
 174         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 175                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)((char *)ctx->bios + data_offset);
 176
 177                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 178                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 179
 180                 for (i = 0; i < num_indices; i++) {
 181                         gpio = &i2c_info->asGPIO_Info[i];
 182
 183                         radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
 184
 185                         i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
 186
 187                         if (i2c.valid) {
 188                                 ksprintf(stmp, "0x%x", i2c.i2c_id);
 189                                 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
 190                         }
 191                 }
 192         }
 193 }
 194
 195 static struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
 196                                                         u8 id)
 197 {
 198         struct atom_context *ctx = rdev->mode_info.atom_context;
 199         struct radeon_gpio_rec gpio;
 200         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 201         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 202         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 203         u16 data_offset, size;
 204         int i, num_indices;
 205
 206         memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
 207         gpio.valid = false;
 208
 209         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 210                 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)((char *)ctx->bios + data_offset);
 211
 212                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 213                         sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 214
 215                 for (i = 0; i < num_indices; i++) {
 216                         pin = &gpio_info->asGPIO_Pin[i];
 217                         if (id == pin->ucGPIO_ID) {
 218                                 gpio.id = pin->ucGPIO_ID;
 219                                 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
 220                                 gpio.mask = (1 << pin->ucGpioPinBitShift);
 221                                 gpio.valid = true;
 222                                 break;
 223                         }
 224                 }
 225         }
 226
 227         return gpio;
 228 }
 229
 230 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
 231                                                             struct radeon_gpio_rec *gpio)
 232 {
 233         struct radeon_hpd hpd;
 234         u32 reg;
 235
 236         memset(&hpd, 0, sizeof(struct radeon_hpd));
 237
 238         if (ASIC_IS_DCE6(rdev))
 239                 reg = SI_DC_GPIO_HPD_A;
 240         else if (ASIC_IS_DCE4(rdev))
 241                 reg = EVERGREEN_DC_GPIO_HPD_A;
 242         else
 243                 reg = AVIVO_DC_GPIO_HPD_A;
 244
 245         hpd.gpio = *gpio;
 246         if (gpio->reg == reg) {
 247                 switch(gpio->mask) {
 248                 case (1 << 0):
 249                         hpd.hpd = RADEON_HPD_1;
 250                         break;
 251                 case (1 << 8):
 252                         hpd.hpd = RADEON_HPD_2;
 253                         break;
 254                 case (1 << 16):
 255                         hpd.hpd = RADEON_HPD_3;
 256                         break;
 257                 case (1 << 24):
 258                         hpd.hpd = RADEON_HPD_4;
 259                         break;
 260                 case (1 << 26):
 261                         hpd.hpd = RADEON_HPD_5;
 262                         break;
 263                 case (1 << 28):
 264                         hpd.hpd = RADEON_HPD_6;
 265                         break;
 266                 default:
 267                         hpd.hpd = RADEON_HPD_NONE;
 268                         break;
 269                 }
 270         } else
 271                 hpd.hpd = RADEON_HPD_NONE;
 272         return hpd;
 273 }
 274
 275 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 276                                      uint32_t supported_device,
 277                                      int *connector_type,
 278                                      struct radeon_i2c_bus_rec *i2c_bus,
 279                                      uint16_t *line_mux,
 280                                      struct radeon_hpd *hpd)
 281 {
 282
 283         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 284         if ((dev->pci_device == 0x791e) &&
 285             (dev->pci_subvendor == 0x1043) &&
 286             (dev->pci_subdevice == 0x826d)) {
 287                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 288                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 289                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 290         }
 291
 292         /* Asrock RS600 board lists the DVI port as HDMI */
 293         if ((dev->pci_device == 0x7941) &&
 294             (dev->pci_subvendor == 0x1849) &&
 295             (dev->pci_subdevice == 0x7941)) {
 296                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 297                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 298                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 299         }
 300
 301         /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
 302         if ((dev->pci_device == 0x796e) &&
 303             (dev->pci_subvendor == 0x1462) &&
 304             (dev->pci_subdevice == 0x7302)) {
 305                 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
 306                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 307                         return false;
 308         }
 309
 310         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 311         if ((dev->pci_device == 0x7941) &&
 312             (dev->pci_subvendor == 0x147b) &&
 313             (dev->pci_subdevice == 0x2412)) {
 314                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 315                         return false;
 316         }
 317
 318         /* Falcon NW laptop lists vga ddc line for LVDS */
 319         if ((dev->pci_device == 0x5653) &&
 320             (dev->pci_subvendor == 0x1462) &&
 321             (dev->pci_subdevice == 0x0291)) {
 322                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 323                         i2c_bus->valid = false;
 324                         *line_mux = 53;
 325                 }
 326         }
 327
 328         /* HIS X1300 is DVI+VGA, not DVI+DVI */
 329         if ((dev->pci_device == 0x7146) &&
 330             (dev->pci_subvendor == 0x17af) &&
 331             (dev->pci_subdevice == 0x2058)) {
 332                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 333                         return false;
 334         }
 335
 336         /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
 337         if ((dev->pci_device == 0x7142) &&
 338             (dev->pci_subvendor == 0x1458) &&
 339             (dev->pci_subdevice == 0x2134)) {
 340                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 341                         return false;
 342         }
 343
 344
 345         /* Funky macbooks */
 346         if ((dev->pci_device == 0x71C5) &&
 347             (dev->pci_subvendor == 0x106b) &&
 348             (dev->pci_subdevice == 0x0080)) {
 349                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 350                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 351                         return false;
 352                 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
 353                         *line_mux = 0x90;
 354         }
 355
 356         /* mac rv630, rv730, others */
 357         if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
 358             (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
 359                 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
 360                 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
 361         }
 362
 363         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 364         if ((dev->pci_device == 0x9598) &&
 365             (dev->pci_subvendor == 0x1043) &&
 366             (dev->pci_subdevice == 0x01da)) {
 367                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 368                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 369                 }
 370         }
 371
 372         /* ASUS HD 3600 board lists the DVI port as HDMI */
 373         if ((dev->pci_device == 0x9598) &&
 374             (dev->pci_subvendor == 0x1043) &&
 375             (dev->pci_subdevice == 0x01e4)) {
 376                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 377                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 378                 }
 379         }
 380
 381         /* ASUS HD 3450 board lists the DVI port as HDMI */
 382         if ((dev->pci_device == 0x95C5) &&
 383             (dev->pci_subvendor == 0x1043) &&
 384             (dev->pci_subdevice == 0x01e2)) {
 385                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 386                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 387                 }
 388         }
 389
 390         /* some BIOSes seem to report DAC on HDMI - usually this is a board with
 391          * HDMI + VGA reporting as HDMI
 392          */
 393         if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 394                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 395                         *connector_type = DRM_MODE_CONNECTOR_VGA;
 396                         *line_mux = 0;
 397                 }
 398         }
 399
 400         /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
 401          * on the laptop and a DVI port on the docking station and
 402          * both share the same encoder, hpd pin, and ddc line.
 403          * So while the bios table is technically correct,
 404          * we drop the DVI port here since xrandr has no concept of
 405          * encoders and will try and drive both connectors
 406          * with different crtcs which isn't possible on the hardware
 407          * side and leaves no crtcs for LVDS or VGA.
 408          */
 409         if (((dev->pci_device == 0x95c4) || (dev->pci_device == 0x9591)) &&
 410             (dev->pci_subvendor == 0x1025) &&
 411             (dev->pci_subdevice == 0x013c)) {
 412                 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
 413                     (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
 414                         /* actually it's a DVI-D port not DVI-I */
 415                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 416                         return false;
 417                 }
 418         }
 419
 420         /* XFX Pine Group device rv730 reports no VGA DDC lines
 421          * even though they are wired up to record 0x93
 422          */
 423         if ((dev->pci_device == 0x9498) &&
 424             (dev->pci_subvendor == 0x1682) &&
 425             (dev->pci_subdevice == 0x2452) &&
 426             (i2c_bus->valid == false) &&
 427             !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
 428                 struct radeon_device *rdev = dev->dev_private;
 429                 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
 430         }
 431
 432         /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
 433         if (((dev->pci_device == 0x9802) || (dev->pci_device == 0x9806)) &&
 434             (dev->pci_subvendor == 0x1734) &&
 435             (dev->pci_subdevice == 0x11bd)) {
 436                 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
 437                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 438                         *line_mux = 0x3103;
 439                 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
 440                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 441                 }
 442         }
 443
 444
 445         return true;
 446 }
 447
 448 const int supported_devices_connector_convert[] = {
 449         DRM_MODE_CONNECTOR_Unknown,
 450         DRM_MODE_CONNECTOR_VGA,
 451         DRM_MODE_CONNECTOR_DVII,
 452         DRM_MODE_CONNECTOR_DVID,
 453         DRM_MODE_CONNECTOR_DVIA,
 454         DRM_MODE_CONNECTOR_SVIDEO,
 455         DRM_MODE_CONNECTOR_Composite,
 456         DRM_MODE_CONNECTOR_LVDS,
 457         DRM_MODE_CONNECTOR_Unknown,
 458         DRM_MODE_CONNECTOR_Unknown,
 459         DRM_MODE_CONNECTOR_HDMIA,
 460         DRM_MODE_CONNECTOR_HDMIB,
 461         DRM_MODE_CONNECTOR_Unknown,
 462         DRM_MODE_CONNECTOR_Unknown,
 463         DRM_MODE_CONNECTOR_9PinDIN,
 464         DRM_MODE_CONNECTOR_DisplayPort
 465 };
 466
 467 const uint16_t supported_devices_connector_object_id_convert[] = {
 468         CONNECTOR_OBJECT_ID_NONE,
 469         CONNECTOR_OBJECT_ID_VGA,
 470         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
 471         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
 472         CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
 473         CONNECTOR_OBJECT_ID_COMPOSITE,
 474         CONNECTOR_OBJECT_ID_SVIDEO,
 475         CONNECTOR_OBJECT_ID_LVDS,
 476         CONNECTOR_OBJECT_ID_9PIN_DIN,
 477         CONNECTOR_OBJECT_ID_9PIN_DIN,
 478         CONNECTOR_OBJECT_ID_DISPLAYPORT,
 479         CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
 480         CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
 481         CONNECTOR_OBJECT_ID_SVIDEO
 482 };
 483
 484 const int object_connector_convert[] = {
 485         DRM_MODE_CONNECTOR_Unknown,
 486         DRM_MODE_CONNECTOR_DVII,
 487         DRM_MODE_CONNECTOR_DVII,
 488         DRM_MODE_CONNECTOR_DVID,
 489         DRM_MODE_CONNECTOR_DVID,
 490         DRM_MODE_CONNECTOR_VGA,
 491         DRM_MODE_CONNECTOR_Composite,
 492         DRM_MODE_CONNECTOR_SVIDEO,
 493         DRM_MODE_CONNECTOR_Unknown,
 494         DRM_MODE_CONNECTOR_Unknown,
 495         DRM_MODE_CONNECTOR_9PinDIN,
 496         DRM_MODE_CONNECTOR_Unknown,
 497         DRM_MODE_CONNECTOR_HDMIA,
 498         DRM_MODE_CONNECTOR_HDMIB,
 499         DRM_MODE_CONNECTOR_LVDS,
 500         DRM_MODE_CONNECTOR_9PinDIN,
 501         DRM_MODE_CONNECTOR_Unknown,
 502         DRM_MODE_CONNECTOR_Unknown,
 503         DRM_MODE_CONNECTOR_Unknown,
 504         DRM_MODE_CONNECTOR_DisplayPort,
 505         DRM_MODE_CONNECTOR_eDP,
 506         DRM_MODE_CONNECTOR_Unknown
 507 };
 508
 509 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 510 {
 511         struct radeon_device *rdev = dev->dev_private;
 512         struct radeon_mode_info *mode_info = &rdev->mode_info;
 513         struct atom_context *ctx = mode_info->atom_context;
 514         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 515         u16 size, data_offset;
 516         u8 frev, crev;
 517         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 518         ATOM_ENCODER_OBJECT_TABLE *enc_obj;
 519         ATOM_OBJECT_TABLE *router_obj;
 520         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 521         ATOM_OBJECT_HEADER *obj_header;
 522         int i, j, k, path_size, device_support;
 523         int connector_type;
 524         u16 igp_lane_info, conn_id, connector_object_id;
 525         struct radeon_i2c_bus_rec ddc_bus;
 526         struct radeon_router router;
 527         struct radeon_gpio_rec gpio;
 528         struct radeon_hpd hpd;
 529
 530         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 531                 return false;
 532
 533         if (crev < 2)
 534                 return false;
 535
 536         obj_header = (ATOM_OBJECT_HEADER *) ((char *)ctx->bios + data_offset);
 537         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 538             ((char *)ctx->bios + data_offset +
 539              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 540         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 541             ((char *)ctx->bios + data_offset +
 542              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 543         enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
 544             ((char *)ctx->bios + data_offset +
 545              le16_to_cpu(obj_header->usEncoderObjectTableOffset));
 546         router_obj = (ATOM_OBJECT_TABLE *)
 547                 ((char *)ctx->bios + data_offset +
 548                  le16_to_cpu(obj_header->usRouterObjectTableOffset));
 549         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 550
 551         path_size = 0;
 552         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 553                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 554                 ATOM_DISPLAY_OBJECT_PATH *path;
 555                 addr += path_size;
 556                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 557                 path_size += le16_to_cpu(path->usSize);
 558
 559                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 560                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 561
 562                         con_obj_id =
 563                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 564                             >> OBJECT_ID_SHIFT;
 565                         con_obj_num =
 566                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 567                             >> ENUM_ID_SHIFT;
 568                         con_obj_type =
 569                             (le16_to_cpu(path->usConnObjectId) &
 570                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 571
 572                         /* TODO CV support */
 573                         if (le16_to_cpu(path->usDeviceTag) ==
 574                                 ATOM_DEVICE_CV_SUPPORT)
 575                                 continue;
 576
 577                         /* IGP chips */
 578                         if ((rdev->flags & RADEON_IS_IGP) &&
 579                             (con_obj_id ==
 580                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 581                                 uint16_t igp_offset = 0;
 582                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 583
 584                                 index =
 585                                     GetIndexIntoMasterTable(DATA,
 586                                                             IntegratedSystemInfo);
 587
 588                                 if (atom_parse_data_header(ctx, index, &size, &frev,
 589                                                            &crev, &igp_offset)) {
 590
 591                                         if (crev >= 2) {
 592                                                 igp_obj =
 593                                                         (ATOM_INTEGRATED_SYSTEM_INFO_V2
 594                                                          *) ((char *)ctx->bios + igp_offset);
 595
 596                                                 if (igp_obj) {
 597                                                         uint32_t slot_config, ct;
 598
 599                                                         if (con_obj_num == 1)
 600                                                                 slot_config =
 601                                                                         igp_obj->
 602                                                                         ulDDISlot1Config;
 603                                                         else
 604                                                                 slot_config =
 605                                                                         igp_obj->
 606                                                                         ulDDISlot2Config;
 607
 608                                                         ct = (slot_config >> 16) & 0xff;
 609                                                         connector_type =
 610                                                                 object_connector_convert
 611                                                                 [ct];
 612                                                         connector_object_id = ct;
 613                                                         igp_lane_info =
 614                                                                 slot_config & 0xffff;
 615                                                 } else
 616                                                         continue;
 617                                         } else
 618                                                 continue;
 619                                 } else {
 620                                         igp_lane_info = 0;
 621                                         connector_type =
 622                                                 object_connector_convert[con_obj_id];
 623                                         connector_object_id = con_obj_id;
 624                                 }
 625                         } else {
 626                                 igp_lane_info = 0;
 627                                 connector_type =
 628                                     object_connector_convert[con_obj_id];
 629                                 connector_object_id = con_obj_id;
 630                         }
 631
 632                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 633                                 continue;
 634
 635                         router.ddc_valid = false;
 636                         router.cd_valid = false;
 637                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
 638                                 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
 639
 640                                 grph_obj_id =
 641                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 642                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 643                                 grph_obj_num =
 644                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 645                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 646                                 grph_obj_type =
 647                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 648                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 649
 650                                 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 651                                         for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
 652                                                 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
 653                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
 654                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 655                                                                 ((char *)ctx->bios + data_offset +
 656                                                                  le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
 657                                                         ATOM_ENCODER_CAP_RECORD *cap_record;
 658                                                         u16 caps = 0;
 659
 660                                                         while (record->ucRecordSize > 0 &&
 661                                                                record->ucRecordType > 0 &&
 662                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 663                                                                 switch (record->ucRecordType) {
 664                                                                 case ATOM_ENCODER_CAP_RECORD_TYPE:
 665                                                                         cap_record =(ATOM_ENCODER_CAP_RECORD *)
 666                                                                                 record;
 667                                                                         caps = le16_to_cpu(cap_record->usEncoderCap);
 668                                                                         break;
 669                                                                 }
 670                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 671                                                                         ((char *)record + record->ucRecordSize);
 672                                                         }
 673                                                         radeon_add_atom_encoder(dev,
 674                                                                                 encoder_obj,
 675                                                                                 le16_to_cpu
 676                                                                                 (path->
 677                                                                                  usDeviceTag),
 678                                                                                 caps);
 679                                                 }
 680                                         }
 681                                 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
 682                                         for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
 683                                                 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
 684                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
 685                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 686                                                                 ((char *)ctx->bios + data_offset +
 687                                                                  le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
 688                                                         ATOM_I2C_RECORD *i2c_record;
 689                                                         ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 690                                                         ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
 691                                                         ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
 692                                                         ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
 693                                                                 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
 694                                                                 ((char *)ctx->bios + data_offset +
 695                                                                  le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
 696                                                         int enum_id;
 697
 698                                                         router.router_id = router_obj_id;
 699                                                         for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
 700                                                              enum_id++) {
 701                                                                 if (le16_to_cpu(path->usConnObjectId) ==
 702                                                                     le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
 703                                                                         break;
 704                                                         }
 705
 706                                                         while (record->ucRecordSize > 0 &&
 707                                                                record->ucRecordType > 0 &&
 708                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 709                                                                 switch (record->ucRecordType) {
 710                                                                 case ATOM_I2C_RECORD_TYPE:
 711                                                                         i2c_record =
 712                                                                                 (ATOM_I2C_RECORD *)
 713                                                                                 record;
 714                                                                         i2c_config =
 715                                                                                 (ATOM_I2C_ID_CONFIG_ACCESS *)
 716                                                                                 &i2c_record->sucI2cId;
 717                                                                         router.i2c_info =
 718                                                                                 radeon_lookup_i2c_gpio(rdev,
 719                                                                                                        i2c_config->
 720                                                                                                        ucAccess);
 721                                                                         router.i2c_addr = i2c_record->ucI2CAddr >> 1;
 722                                                                         break;
 723                                                                 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
 724                                                                         ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
 725                                                                                 record;
 726                                                                         router.ddc_valid = true;
 727                                                                         router.ddc_mux_type = ddc_path->ucMuxType;
 728                                                                         router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
 729                                                                         router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
 730                                                                         break;
 731                                                                 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
 732                                                                         cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
 733                                                                                 record;
 734                                                                         router.cd_valid = true;
 735                                                                         router.cd_mux_type = cd_path->ucMuxType;
 736                                                                         router.cd_mux_control_pin = cd_path->ucMuxControlPin;
 737                                                                         router.cd_mux_state = cd_path->ucMuxState[enum_id];
 738                                                                         break;
 739                                                                 }
 740                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 741                                                                         ((char *)record + record->ucRecordSize);
 742                                                         }
 743                                                 }
 744                                         }
 745                                 }
 746                         }
 747
 748                         /* look up gpio for ddc, hpd */
 749                         ddc_bus.valid = false;
 750                         hpd.hpd = RADEON_HPD_NONE;
 751                         if ((le16_to_cpu(path->usDeviceTag) &
 752                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 753                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 754                                         if (le16_to_cpu(path->usConnObjectId) ==
 755                                             le16_to_cpu(con_obj->asObjects[j].
 756                                                         usObjectID)) {
 757                                                 ATOM_COMMON_RECORD_HEADER
 758                                                     *record =
 759                                                     (ATOM_COMMON_RECORD_HEADER
 760                                                      *)
 761                                                     ((char *)ctx->bios + data_offset +
 762                                                      le16_to_cpu(con_obj->
 763                                                                  asObjects[j].
 764                                                                  usRecordOffset));
 765                                                 ATOM_I2C_RECORD *i2c_record;
 766                                                 ATOM_HPD_INT_RECORD *hpd_record;
 767                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 768
 769                                                 while (record->ucRecordSize > 0 &&
 770                                                        record->ucRecordType > 0 &&
 771                                                        record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 772                                                         switch (record->ucRecordType) {
 773                                                         case ATOM_I2C_RECORD_TYPE:
 774                                                                 i2c_record =
 775                                                                     (ATOM_I2C_RECORD *)
 776                                                                         record;
 777                                                                 i2c_config =
 778                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 779                                                                         &i2c_record->sucI2cId;
 780                                                                 ddc_bus = radeon_lookup_i2c_gpio(rdev,
 781                                                                                                  i2c_config->
 782                                                                                                  ucAccess);
 783                                                                 break;
 784                                                         case ATOM_HPD_INT_RECORD_TYPE:
 785                                                                 hpd_record =
 786                                                                         (ATOM_HPD_INT_RECORD *)
 787                                                                         record;
 788                                                                 gpio = radeon_lookup_gpio(rdev,
 789                                                                                           hpd_record->ucHPDIntGPIOID);
 790                                                                 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 791                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 792                                                                 break;
 793                                                         }
 794                                                         record =
 795                                                             (ATOM_COMMON_RECORD_HEADER
 796                                                              *) ((char *)record
 797                                                                  +
 798                                                                  record->
 799                                                                  ucRecordSize);
 800                                                 }
 801                                                 break;
 802                                         }
 803                                 }
 804                         }
 805
 806                         /* needed for aux chan transactions */
 807                         ddc_bus.hpd = hpd.hpd;
 808
 809                         conn_id = le16_to_cpu(path->usConnObjectId);
 810
 811                         if (!radeon_atom_apply_quirks
 812                             (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
 813                              &ddc_bus, &conn_id, &hpd))
 814                                 continue;
 815
 816                         radeon_add_atom_connector(dev,
 817                                                   conn_id,
 818                                                   le16_to_cpu(path->
 819                                                               usDeviceTag),
 820                                                   connector_type, &ddc_bus,
 821                                                   igp_lane_info,
 822                                                   connector_object_id,
 823                                                   &hpd,
 824                                                   &router);
 825
 826                 }
 827         }
 828
 829         radeon_link_encoder_connector(dev);
 830
 831         return true;
 832 }
 833
 834 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
 835                                                  int connector_type,
 836                                                  uint16_t devices)
 837 {
 838         struct radeon_device *rdev = dev->dev_private;
 839
 840         if (rdev->flags & RADEON_IS_IGP) {
 841                 return supported_devices_connector_object_id_convert
 842                         [connector_type];
 843         } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
 844                     (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
 845                    (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
 846                 struct radeon_mode_info *mode_info = &rdev->mode_info;
 847                 struct atom_context *ctx = mode_info->atom_context;
 848                 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
 849                 uint16_t size, data_offset;
 850                 uint8_t frev, crev;
 851                 ATOM_XTMDS_INFO *xtmds;
 852
 853                 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
 854                         xtmds = (ATOM_XTMDS_INFO *)((char *)ctx->bios + data_offset);
 855
 856                         if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
 857                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 858                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
 859                                 else
 860                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
 861                         } else {
 862                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 863                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
 864                                 else
 865                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
 866                         }
 867                 } else
 868                         return supported_devices_connector_object_id_convert
 869                                 [connector_type];
 870         } else {
 871                 return supported_devices_connector_object_id_convert
 872                         [connector_type];
 873         }
 874 }
 875
 876 struct bios_connector {
 877         bool valid;
 878         uint16_t line_mux;
 879         uint16_t devices;
 880         int connector_type;
 881         struct radeon_i2c_bus_rec ddc_bus;
 882         struct radeon_hpd hpd;
 883 };
 884
 885 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 886                                                                  drm_device
 887                                                                  *dev)
 888 {
 889         struct radeon_device *rdev = dev->dev_private;
 890         struct radeon_mode_info *mode_info = &rdev->mode_info;
 891         struct atom_context *ctx = mode_info->atom_context;
 892         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 893         uint16_t size, data_offset;
 894         uint8_t frev, crev;
 895         uint16_t device_support;
 896         uint8_t dac;
 897         union atom_supported_devices *supported_devices;
 898         int i, j, max_device;
 899         struct bios_connector *bios_connectors;
 900         size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
 901         struct radeon_router router;
 902
 903         router.ddc_valid = false;
 904         router.cd_valid = false;
 905
 906         bios_connectors = kmalloc(bc_size, M_DRM, M_WAITOK | M_ZERO);
 907         if (!bios_connectors)
 908                 return false;
 909
 910         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
 911                                     &data_offset)) {
 912                 drm_free(bios_connectors, M_DRM);
 913                 return false;
 914         }
 915
 916         supported_devices =
 917             (union atom_supported_devices *)((char *)ctx->bios + data_offset);
 918
 919         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 920
 921         if (frev > 1)
 922                 max_device = ATOM_MAX_SUPPORTED_DEVICE;
 923         else
 924                 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
 925
 926         for (i = 0; i < max_device; i++) {
 927                 ATOM_CONNECTOR_INFO_I2C ci =
 928                     supported_devices->info.asConnInfo[i];
 929
 930                 bios_connectors[i].valid = false;
 931
 932                 if (!(device_support & (1 << i))) {
 933                         continue;
 934                 }
 935
 936                 if (i == ATOM_DEVICE_CV_INDEX) {
 937                         DRM_DEBUG_KMS("Skipping Component Video\n");
 938                         continue;
 939                 }
 940
 941                 bios_connectors[i].connector_type =
 942                     supported_devices_connector_convert[ci.sucConnectorInfo.
 943                                                         sbfAccess.
 944                                                         bfConnectorType];
 945
 946                 if (bios_connectors[i].connector_type ==
 947                     DRM_MODE_CONNECTOR_Unknown)
 948                         continue;
 949
 950                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 951
 952                 bios_connectors[i].line_mux =
 953                         ci.sucI2cId.ucAccess;
 954
 955                 /* give tv unique connector ids */
 956                 if (i == ATOM_DEVICE_TV1_INDEX) {
 957                         bios_connectors[i].ddc_bus.valid = false;
 958                         bios_connectors[i].line_mux = 50;
 959                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
 960                         bios_connectors[i].ddc_bus.valid = false;
 961                         bios_connectors[i].line_mux = 51;
 962                 } else if (i == ATOM_DEVICE_CV_INDEX) {
 963                         bios_connectors[i].ddc_bus.valid = false;
 964                         bios_connectors[i].line_mux = 52;
 965                 } else
 966                         bios_connectors[i].ddc_bus =
 967                             radeon_lookup_i2c_gpio(rdev,
 968                                                    bios_connectors[i].line_mux);
 969
 970                 if ((crev > 1) && (frev > 1)) {
 971                         u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
 972                         switch (isb) {
 973                         case 0x4:
 974                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 975                                 break;
 976                         case 0xa:
 977                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 978                                 break;
 979                         default:
 980                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 981                                 break;
 982                         }
 983                 } else {
 984                         if (i == ATOM_DEVICE_DFP1_INDEX)
 985                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 986                         else if (i == ATOM_DEVICE_DFP2_INDEX)
 987                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 988                         else
 989                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 990                 }
 991
 992                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
 993                  * shared with a DVI port, we'll pick up the DVI connector when we
 994                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
 995                  */
 996                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
 997                         bios_connectors[i].connector_type =
 998                             DRM_MODE_CONNECTOR_VGA;
 999
1000                 if (!radeon_atom_apply_quirks
1001                     (dev, (1 << i), &bios_connectors[i].connector_type,
1002                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1003                      &bios_connectors[i].hpd))
1004                         continue;
1005
1006                 bios_connectors[i].valid = true;
1007                 bios_connectors[i].devices = (1 << i);
1008
1009                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1010                         radeon_add_atom_encoder(dev,
1011                                                 radeon_get_encoder_enum(dev,
1012                                                                       (1 << i),
1013                                                                       dac),
1014                                                 (1 << i),
1015                                                 0);
1016                 else
1017                         radeon_add_legacy_encoder(dev,
1018                                                   radeon_get_encoder_enum(dev,
1019                                                                         (1 << i),
1020                                                                         dac),
1021                                                   (1 << i));
1022         }
1023
1024         /* combine shared connectors */
1025         for (i = 0; i < max_device; i++) {
1026                 if (bios_connectors[i].valid) {
1027                         for (j = 0; j < max_device; j++) {
1028                                 if (bios_connectors[j].valid && (i != j)) {
1029                                         if (bios_connectors[i].line_mux ==
1030                                             bios_connectors[j].line_mux) {
1031                                                 /* make sure not to combine LVDS */
1032                                                 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1033                                                         bios_connectors[i].line_mux = 53;
1034                                                         bios_connectors[i].ddc_bus.valid = false;
1035                                                         continue;
1036                                                 }
1037                                                 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1038                                                         bios_connectors[j].line_mux = 53;
1039                                                         bios_connectors[j].ddc_bus.valid = false;
1040                                                         continue;
1041                                                 }
1042                                                 /* combine analog and digital for DVI-I */
1043                                                 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1044                                                      (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1045                                                     ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1046                                                      (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1047                                                         bios_connectors[i].devices |=
1048                                                                 bios_connectors[j].devices;
1049                                                         bios_connectors[i].connector_type =
1050                                                                 DRM_MODE_CONNECTOR_DVII;
1051                                                         if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1052                                                                 bios_connectors[i].hpd =
1053                                                                         bios_connectors[j].hpd;
1054                                                         bios_connectors[j].valid = false;
1055                                                 }
1056                                         }
1057                                 }
1058                         }
1059                 }
1060         }
1061
1062         /* add the connectors */
1063         for (i = 0; i < max_device; i++) {
1064                 if (bios_connectors[i].valid) {
1065                         uint16_t connector_object_id =
1066                                 atombios_get_connector_object_id(dev,
1067                                                       bios_connectors[i].connector_type,
1068                                                       bios_connectors[i].devices);
1069                         radeon_add_atom_connector(dev,
1070                                                   bios_connectors[i].line_mux,
1071                                                   bios_connectors[i].devices,
1072                                                   bios_connectors[i].
1073                                                   connector_type,
1074                                                   &bios_connectors[i].ddc_bus,
1075                                                   0,
1076                                                   connector_object_id,
1077                                                   &bios_connectors[i].hpd,
1078                                                   &router);
1079                 }
1080         }
1081
1082         radeon_link_encoder_connector(dev);
1083
1084         drm_free(bios_connectors, M_DRM);
1085         return true;
1086 }
1087
1088 union firmware_info {
1089         ATOM_FIRMWARE_INFO info;
1090         ATOM_FIRMWARE_INFO_V1_2 info_12;
1091         ATOM_FIRMWARE_INFO_V1_3 info_13;
1092         ATOM_FIRMWARE_INFO_V1_4 info_14;
1093         ATOM_FIRMWARE_INFO_V2_1 info_21;
1094         ATOM_FIRMWARE_INFO_V2_2 info_22;
1095 };
1096
1097 bool radeon_atom_get_clock_info(struct drm_device *dev)
1098 {
1099         struct radeon_device *rdev = dev->dev_private;
1100         struct radeon_mode_info *mode_info = &rdev->mode_info;
1101         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1102         union firmware_info *firmware_info;
1103         uint8_t frev, crev;
1104         struct radeon_pll *p1pll = &rdev->clock.p1pll;
1105         struct radeon_pll *p2pll = &rdev->clock.p2pll;
1106         struct radeon_pll *dcpll = &rdev->clock.dcpll;
1107         struct radeon_pll *spll = &rdev->clock.spll;
1108         struct radeon_pll *mpll = &rdev->clock.mpll;
1109         uint16_t data_offset;
1110
1111         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1112                                    &frev, &crev, &data_offset)) {
1113                 firmware_info =
1114                         (union firmware_info *)((char *)mode_info->atom_context->bios +
1115                                                 data_offset);
1116                 /* pixel clocks */
1117                 p1pll->reference_freq =
1118                     le16_to_cpu(firmware_info->info.usReferenceClock);
1119                 p1pll->reference_div = 0;
1120
1121                 if (crev < 2)
1122                         p1pll->pll_out_min =
1123                                 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1124                 else
1125                         p1pll->pll_out_min =
1126                                 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1127                 p1pll->pll_out_max =
1128                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1129
1130                 if (crev >= 4) {
1131                         p1pll->lcd_pll_out_min =
1132                                 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1133                         if (p1pll->lcd_pll_out_min == 0)
1134                                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1135                         p1pll->lcd_pll_out_max =
1136                                 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1137                         if (p1pll->lcd_pll_out_max == 0)
1138                                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1139                 } else {
1140                         p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1141                         p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1142                 }
1143
1144                 if (p1pll->pll_out_min == 0) {
1145                         if (ASIC_IS_AVIVO(rdev))
1146                                 p1pll->pll_out_min = 64800;
1147                         else
1148                                 p1pll->pll_out_min = 20000;
1149                 }
1150
1151                 p1pll->pll_in_min =
1152                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1153                 p1pll->pll_in_max =
1154                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1155
1156                 *p2pll = *p1pll;
1157
1158                 /* system clock */
1159                 if (ASIC_IS_DCE4(rdev))
1160                         spll->reference_freq =
1161                                 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1162                 else
1163                         spll->reference_freq =
1164                                 le16_to_cpu(firmware_info->info.usReferenceClock);
1165                 spll->reference_div = 0;
1166
1167                 spll->pll_out_min =
1168                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1169                 spll->pll_out_max =
1170                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1171
1172                 /* ??? */
1173                 if (spll->pll_out_min == 0) {
1174                         if (ASIC_IS_AVIVO(rdev))
1175                                 spll->pll_out_min = 64800;
1176                         else
1177                                 spll->pll_out_min = 20000;
1178                 }
1179
1180                 spll->pll_in_min =
1181                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1182                 spll->pll_in_max =
1183                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1184
1185                 /* memory clock */
1186                 if (ASIC_IS_DCE4(rdev))
1187                         mpll->reference_freq =
1188                                 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1189                 else
1190                         mpll->reference_freq =
1191                                 le16_to_cpu(firmware_info->info.usReferenceClock);
1192                 mpll->reference_div = 0;
1193
1194                 mpll->pll_out_min =
1195                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1196                 mpll->pll_out_max =
1197                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1198
1199                 /* ??? */
1200                 if (mpll->pll_out_min == 0) {
1201                         if (ASIC_IS_AVIVO(rdev))
1202                                 mpll->pll_out_min = 64800;
1203                         else
1204                                 mpll->pll_out_min = 20000;
1205                 }
1206
1207                 mpll->pll_in_min =
1208                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1209                 mpll->pll_in_max =
1210                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1211
1212                 rdev->clock.default_sclk =
1213                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1214                 rdev->clock.default_mclk =
1215                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1216
1217                 if (ASIC_IS_DCE4(rdev)) {
1218                         rdev->clock.default_dispclk =
1219                                 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1220                         if (rdev->clock.default_dispclk == 0) {
1221                                 if (ASIC_IS_DCE5(rdev))
1222                                         rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1223                                 else
1224                                         rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1225                         }
1226                         rdev->clock.dp_extclk =
1227                                 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1228                 }
1229                 *dcpll = *p1pll;
1230
1231                 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1232                 if (rdev->clock.max_pixel_clock == 0)
1233                         rdev->clock.max_pixel_clock = 40000;
1234
1235                 /* not technically a clock, but... */
1236                 rdev->mode_info.firmware_flags =
1237                         le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
1238
1239                 return true;
1240         }
1241
1242         return false;
1243 }
1244
1245 union igp_info {
1246         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1247         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1248         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1249         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1250 };
1251
1252 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1253 {
1254         struct radeon_mode_info *mode_info = &rdev->mode_info;
1255         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1256         union igp_info *igp_info;
1257         u8 frev, crev;
1258         u16 data_offset;
1259
1260         /* sideport is AMD only */
1261         if (rdev->family == CHIP_RS600)
1262                 return false;
1263
1264         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1265                                    &frev, &crev, &data_offset)) {
1266                 igp_info = (union igp_info *)((char *)mode_info->atom_context->bios +
1267                                       data_offset);
1268                 switch (crev) {
1269                 case 1:
1270                         if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1271                                 return true;
1272                         break;
1273                 case 2:
1274                         if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1275                                 return true;
1276                         break;
1277                 default:
1278                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1279                         break;
1280                 }
1281         }
1282         return false;
1283 }
1284
1285 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1286                                    struct radeon_encoder_int_tmds *tmds)
1287 {
1288         struct drm_device *dev = encoder->base.dev;
1289         struct radeon_device *rdev = dev->dev_private;
1290         struct radeon_mode_info *mode_info = &rdev->mode_info;
1291         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1292         uint16_t data_offset;
1293         struct _ATOM_TMDS_INFO *tmds_info;
1294         uint8_t frev, crev;
1295         uint16_t maxfreq;
1296         int i;
1297
1298         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1299                                    &frev, &crev, &data_offset)) {
1300                 tmds_info =
1301                         (struct _ATOM_TMDS_INFO *)((char *)mode_info->atom_context->bios +
1302                                                    data_offset);
1303
1304                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1305                 for (i = 0; i < 4; i++) {
1306                         tmds->tmds_pll[i].freq =
1307                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1308                         tmds->tmds_pll[i].value =
1309                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1310                         tmds->tmds_pll[i].value |=
1311                             (tmds_info->asMiscInfo[i].
1312                              ucPLL_VCO_Gain & 0x3f) << 6;
1313                         tmds->tmds_pll[i].value |=
1314                             (tmds_info->asMiscInfo[i].
1315                              ucPLL_DutyCycle & 0xf) << 12;
1316                         tmds->tmds_pll[i].value |=
1317                             (tmds_info->asMiscInfo[i].
1318                              ucPLL_VoltageSwing & 0xf) << 16;
1319
1320                         DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1321                                   tmds->tmds_pll[i].freq,
1322                                   tmds->tmds_pll[i].value);
1323
1324                         if (maxfreq == tmds->tmds_pll[i].freq) {
1325                                 tmds->tmds_pll[i].freq = 0xffffffff;
1326                                 break;
1327                         }
1328                 }
1329                 return true;
1330         }
1331         return false;
1332 }
1333
1334 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1335                                       struct radeon_atom_ss *ss,
1336                                       int id)
1337 {
1338         struct radeon_mode_info *mode_info = &rdev->mode_info;
1339         int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1340         uint16_t data_offset, size;
1341         struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1342         uint8_t frev, crev;
1343         int i, num_indices;
1344
1345         memset(ss, 0, sizeof(struct radeon_atom_ss));
1346         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1347                                    &frev, &crev, &data_offset)) {
1348                 ss_info =
1349                         (struct _ATOM_SPREAD_SPECTRUM_INFO *)((char *)mode_info->atom_context->bios + data_offset);
1350
1351                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1352                         sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1353
1354                 for (i = 0; i < num_indices; i++) {
1355                         if (ss_info->asSS_Info[i].ucSS_Id == id) {
1356                                 ss->percentage =
1357                                         le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1358                                 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1359                                 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1360                                 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1361                                 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1362                                 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1363                                 return true;
1364                         }
1365                 }
1366         }
1367         return false;
1368 }
1369
1370 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1371                                                  struct radeon_atom_ss *ss,
1372                                                  int id)
1373 {
1374         struct radeon_mode_info *mode_info = &rdev->mode_info;
1375         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1376         u16 data_offset, size;
1377         union igp_info *igp_info;
1378         u8 frev, crev;
1379         u16 percentage = 0, rate = 0;
1380
1381         /* get any igp specific overrides */
1382         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1383                                    &frev, &crev, &data_offset)) {
1384                 igp_info = (union igp_info *)
1385                         ((char *)mode_info->atom_context->bios + data_offset);
1386                 switch (crev) {
1387                 case 6:
1388                         switch (id) {
1389                         case ASIC_INTERNAL_SS_ON_TMDS:
1390                                 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1391                                 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1392                                 break;
1393                         case ASIC_INTERNAL_SS_ON_HDMI:
1394                                 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1395                                 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1396                                 break;
1397                         case ASIC_INTERNAL_SS_ON_LVDS:
1398                                 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1399                                 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1400                                 break;
1401                         }
1402                         break;
1403                 case 7:
1404                         switch (id) {
1405                         case ASIC_INTERNAL_SS_ON_TMDS:
1406                                 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1407                                 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1408                                 break;
1409                         case ASIC_INTERNAL_SS_ON_HDMI:
1410                                 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1411                                 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1412                                 break;
1413                         case ASIC_INTERNAL_SS_ON_LVDS:
1414                                 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1415                                 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1416                                 break;
1417                         }
1418                         break;
1419                 default:
1420                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1421                         break;
1422                 }
1423                 if (percentage)
1424                         ss->percentage = percentage;
1425                 if (rate)
1426                         ss->rate = rate;
1427         }
1428 }
1429
1430 union asic_ss_info {
1431         struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1432         struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1433         struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1434 };
1435
1436 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1437                                       struct radeon_atom_ss *ss,
1438                                       int id, u32 clock)
1439 {
1440         struct radeon_mode_info *mode_info = &rdev->mode_info;
1441         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1442         uint16_t data_offset, size;
1443         union asic_ss_info *ss_info;
1444         uint8_t frev, crev;
1445         int i, num_indices;
1446
1447         memset(ss, 0, sizeof(struct radeon_atom_ss));
1448         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1449                                    &frev, &crev, &data_offset)) {
1450
1451                 ss_info =
1452                         (union asic_ss_info *)((char *)mode_info->atom_context->bios + data_offset);
1453
1454                 switch (frev) {
1455                 case 1:
1456                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1457                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1458
1459                         for (i = 0; i < num_indices; i++) {
1460                                 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1461                                     (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) {
1462                                         ss->percentage =
1463                                                 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1464                                         ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1465                                         ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1466                                         return true;
1467                                 }
1468                         }
1469                         break;
1470                 case 2:
1471                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1472                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1473                         for (i = 0; i < num_indices; i++) {
1474                                 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1475                                     (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) {
1476                                         ss->percentage =
1477                                                 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1478                                         ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1479                                         ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1480                                         return true;
1481                                 }
1482                         }
1483                         break;
1484                 case 3:
1485                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1486                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1487                         for (i = 0; i < num_indices; i++) {
1488                                 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1489                                     (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) {
1490                                         ss->percentage =
1491                                                 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1492                                         ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1493                                         ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1494                                         if (rdev->flags & RADEON_IS_IGP)
1495                                                 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1496                                         return true;
1497                                 }
1498                         }
1499                         break;
1500                 default:
1501                         DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1502                         break;
1503                 }
1504
1505         }
1506         return false;
1507 }
1508
1509 union lvds_info {
1510         struct _ATOM_LVDS_INFO info;
1511         struct _ATOM_LVDS_INFO_V12 info_12;
1512 };
1513
1514 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1515                                                               radeon_encoder
1516                                                               *encoder)
1517 {
1518         struct drm_device *dev = encoder->base.dev;
1519         struct radeon_device *rdev = dev->dev_private;
1520         struct radeon_mode_info *mode_info = &rdev->mode_info;
1521         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1522         uint16_t data_offset, misc;
1523         union lvds_info *lvds_info;
1524         uint8_t frev, crev;
1525         struct radeon_encoder_atom_dig *lvds = NULL;
1526         int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1527
1528         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1529                                    &frev, &crev, &data_offset)) {
1530                 lvds_info =
1531                         (union lvds_info *)((char *)mode_info->atom_context->bios + data_offset);
1532                 lvds =
1533                     kmalloc(sizeof(struct radeon_encoder_atom_dig),
1534                         M_DRM, M_WAITOK | M_ZERO);
1535
1536                 if (!lvds)
1537                         return NULL;
1538
1539                 lvds->native_mode.clock =
1540                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1541                 lvds->native_mode.hdisplay =
1542                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1543                 lvds->native_mode.vdisplay =
1544                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1545                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1546                         le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1547                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1548                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1549                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1550                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1551                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1552                         le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1553                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1554                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1555                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1556                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1557                 lvds->panel_pwr_delay =
1558                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
1559                 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1560
1561                 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1562                 if (misc & ATOM_VSYNC_POLARITY)
1563                         lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1564                 if (misc & ATOM_HSYNC_POLARITY)
1565                         lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1566                 if (misc & ATOM_COMPOSITESYNC)
1567                         lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1568                 if (misc & ATOM_INTERLACE)
1569                         lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1570                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1571                         lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1572
1573                 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1574                 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1575
1576                 /* set crtc values */
1577                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1578
1579                 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1580
1581                 encoder->native_mode = lvds->native_mode;
1582
1583                 if (encoder_enum == 2)
1584                         lvds->linkb = true;
1585                 else
1586                         lvds->linkb = false;
1587
1588                 /* parse the lcd record table */
1589                 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1590                         ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1591                         ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1592                         bool bad_record = false;
1593                         u8 *record;
1594
1595                         if ((frev == 1) && (crev < 2))
1596                                 /* absolute */
1597                                 record = (u8 *)((char *)mode_info->atom_context->bios +
1598                                                 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1599                         else
1600                                 /* relative */
1601                                 record = (u8 *)((char *)mode_info->atom_context->bios +
1602                                                 data_offset +
1603                                                 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1604                         while (*record != ATOM_RECORD_END_TYPE) {
1605                                 switch (*record) {
1606                                 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1607                                         record += sizeof(ATOM_PATCH_RECORD_MODE);
1608                                         break;
1609                                 case LCD_RTS_RECORD_TYPE:
1610                                         record += sizeof(ATOM_LCD_RTS_RECORD);
1611                                         break;
1612                                 case LCD_CAP_RECORD_TYPE:
1613                                         record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1614                                         break;
1615                                 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1616                                         fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1617                                         if (fake_edid_record->ucFakeEDIDLength) {
1618                                                 struct edid *edid;
1619                                                 int edid_size =
1620                                                         max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1621                                                 edid = kmalloc(edid_size, M_DRM, M_WAITOK);
1622                                                 if (edid) {
1623                                                         memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1624                                                                fake_edid_record->ucFakeEDIDLength);
1625
1626                                                         if (drm_edid_is_valid(edid)) {
1627                                                                 rdev->mode_info.bios_hardcoded_edid = edid;
1628                                                                 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1629                                                         } else
1630                                                                 drm_free(edid,
1631                                                                          M_DRM);
1632                                                 }
1633                                         }
1634                                         record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1635                                         break;
1636                                 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1637                                         panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1638                                         lvds->native_mode.width_mm = panel_res_record->usHSize;
1639                                         lvds->native_mode.height_mm = panel_res_record->usVSize;
1640                                         record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1641                                         break;
1642                                 default:
1643                                         DRM_ERROR("Bad LCD record %d\n", *record);
1644                                         bad_record = true;
1645                                         break;
1646                                 }
1647                                 if (bad_record)
1648                                         break;
1649                         }
1650                 }
1651         }
1652         return lvds;
1653 }
1654
1655 struct radeon_encoder_primary_dac *
1656 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1657 {
1658         struct drm_device *dev = encoder->base.dev;
1659         struct radeon_device *rdev = dev->dev_private;
1660         struct radeon_mode_info *mode_info = &rdev->mode_info;
1661         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1662         uint16_t data_offset;
1663         struct _COMPASSIONATE_DATA *dac_info;
1664         uint8_t frev, crev;
1665         uint8_t bg, dac;
1666         struct radeon_encoder_primary_dac *p_dac = NULL;
1667
1668         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1669                                    &frev, &crev, &data_offset)) {
1670                 dac_info = (struct _COMPASSIONATE_DATA *)
1671                         ((char *)mode_info->atom_context->bios + data_offset);
1672
1673                 p_dac = kmalloc(sizeof(struct radeon_encoder_primary_dac),
1674                     M_DRM, M_WAITOK | M_ZERO);
1675
1676                 if (!p_dac)
1677                         return NULL;
1678
1679                 bg = dac_info->ucDAC1_BG_Adjustment;
1680                 dac = dac_info->ucDAC1_DAC_Adjustment;
1681                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1682
1683         }
1684         return p_dac;
1685 }
1686
1687 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1688                                 struct drm_display_mode *mode)
1689 {
1690         struct radeon_mode_info *mode_info = &rdev->mode_info;
1691         ATOM_ANALOG_TV_INFO *tv_info;
1692         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1693         ATOM_DTD_FORMAT *dtd_timings;
1694         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1695         u8 frev, crev;
1696         u16 data_offset, misc;
1697
1698         if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1699                                     &frev, &crev, &data_offset))
1700                 return false;
1701
1702         switch (crev) {
1703         case 1:
1704                 tv_info = (ATOM_ANALOG_TV_INFO *)((char *)mode_info->atom_context->bios + data_offset);
1705                 if (index >= MAX_SUPPORTED_TV_TIMING)
1706                         return false;
1707
1708                 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1709                 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1710                 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1711                 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1712                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1713
1714                 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1715                 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1716                 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1717                 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1718                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1719
1720                 mode->flags = 0;
1721                 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1722                 if (misc & ATOM_VSYNC_POLARITY)
1723                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1724                 if (misc & ATOM_HSYNC_POLARITY)
1725                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1726                 if (misc & ATOM_COMPOSITESYNC)
1727                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1728                 if (misc & ATOM_INTERLACE)
1729                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1730                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1731                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1732
1733                 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1734
1735                 if (index == 1) {
1736                         /* PAL timings appear to have wrong values for totals */
1737                         mode->crtc_htotal -= 1;
1738                         mode->crtc_vtotal -= 1;
1739                 }
1740                 break;
1741         case 2:
1742                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)((char *)mode_info->atom_context->bios + data_offset);
1743                 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1744                         return false;
1745
1746                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1747                 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1748                         le16_to_cpu(dtd_timings->usHBlanking_Time);
1749                 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1750                 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1751                         le16_to_cpu(dtd_timings->usHSyncOffset);
1752                 mode->crtc_hsync_end = mode->crtc_hsync_start +
1753                         le16_to_cpu(dtd_timings->usHSyncWidth);
1754
1755                 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1756                         le16_to_cpu(dtd_timings->usVBlanking_Time);
1757                 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1758                 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1759                         le16_to_cpu(dtd_timings->usVSyncOffset);
1760                 mode->crtc_vsync_end = mode->crtc_vsync_start +
1761                         le16_to_cpu(dtd_timings->usVSyncWidth);
1762
1763                 mode->flags = 0;
1764                 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1765                 if (misc & ATOM_VSYNC_POLARITY)
1766                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1767                 if (misc & ATOM_HSYNC_POLARITY)
1768                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1769                 if (misc & ATOM_COMPOSITESYNC)
1770                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1771                 if (misc & ATOM_INTERLACE)
1772                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1773                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1774                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1775
1776                 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1777                 break;
1778         }
1779         return true;
1780 }
1781
1782 enum radeon_tv_std
1783 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1784 {
1785         struct radeon_mode_info *mode_info = &rdev->mode_info;
1786         int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1787         uint16_t data_offset;
1788         uint8_t frev, crev;
1789         struct _ATOM_ANALOG_TV_INFO *tv_info;
1790         enum radeon_tv_std tv_std = TV_STD_NTSC;
1791
1792         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1793                                    &frev, &crev, &data_offset)) {
1794
1795                 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1796                         ((char *)mode_info->atom_context->bios + data_offset);
1797
1798                 switch (tv_info->ucTV_BootUpDefaultStandard) {
1799                 case ATOM_TV_NTSC:
1800                         tv_std = TV_STD_NTSC;
1801                         DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1802                         break;
1803                 case ATOM_TV_NTSCJ:
1804                         tv_std = TV_STD_NTSC_J;
1805                         DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1806                         break;
1807                 case ATOM_TV_PAL:
1808                         tv_std = TV_STD_PAL;
1809                         DRM_DEBUG_KMS("Default TV standard: PAL\n");
1810                         break;
1811                 case ATOM_TV_PALM:
1812                         tv_std = TV_STD_PAL_M;
1813                         DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1814                         break;
1815                 case ATOM_TV_PALN:
1816                         tv_std = TV_STD_PAL_N;
1817                         DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1818                         break;
1819                 case ATOM_TV_PALCN:
1820                         tv_std = TV_STD_PAL_CN;
1821                         DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1822                         break;
1823                 case ATOM_TV_PAL60:
1824                         tv_std = TV_STD_PAL_60;
1825                         DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1826                         break;
1827                 case ATOM_TV_SECAM:
1828                         tv_std = TV_STD_SECAM;
1829                         DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1830                         break;
1831                 default:
1832                         tv_std = TV_STD_NTSC;
1833                         DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1834                         break;
1835                 }
1836         }
1837         return tv_std;
1838 }
1839
1840 struct radeon_encoder_tv_dac *
1841 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1842 {
1843         struct drm_device *dev = encoder->base.dev;
1844         struct radeon_device *rdev = dev->dev_private;
1845         struct radeon_mode_info *mode_info = &rdev->mode_info;
1846         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1847         uint16_t data_offset;
1848         struct _COMPASSIONATE_DATA *dac_info;
1849         uint8_t frev, crev;
1850         uint8_t bg, dac;
1851         struct radeon_encoder_tv_dac *tv_dac = NULL;
1852
1853         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1854                                    &frev, &crev, &data_offset)) {
1855
1856                 dac_info = (struct _COMPASSIONATE_DATA *)
1857                         ((char *)mode_info->atom_context->bios + data_offset);
1858
1859                 tv_dac = kmalloc(sizeof(struct radeon_encoder_tv_dac),
1860                     M_DRM, M_WAITOK | M_ZERO);
1861
1862                 if (!tv_dac)
1863                         return NULL;
1864
1865                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1866                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1867                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1868
1869                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1870                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1871                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1872
1873                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1874                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1875                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1876
1877                 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1878         }
1879         return tv_dac;
1880 }
1881
1882 static const char *thermal_controller_names[] = {
1883         "NONE",
1884         "lm63",
1885         "adm1032",
1886         "adm1030",
1887         "max6649",
1888         "lm64",
1889         "f75375",
1890         "asc7xxx",
1891 };
1892
1893 static const char *pp_lib_thermal_controller_names[] = {
1894         "NONE",
1895         "lm63",
1896         "adm1032",
1897         "adm1030",
1898         "max6649",
1899         "lm64",
1900         "f75375",
1901         "RV6xx",
1902         "RV770",
1903         "adt7473",
1904         "NONE",
1905         "External GPIO",
1906         "Evergreen",
1907         "emc2103",
1908         "Sumo",
1909         "Northern Islands",
1910         "Southern Islands",
1911         "lm96163",
1912 };
1913
1914 union power_info {
1915         struct _ATOM_POWERPLAY_INFO info;
1916         struct _ATOM_POWERPLAY_INFO_V2 info_2;
1917         struct _ATOM_POWERPLAY_INFO_V3 info_3;
1918         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1919         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1920         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1921 };
1922
1923 union pplib_clock_info {
1924         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1925         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1926         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1927         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1928         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
1929 };
1930
1931 union pplib_power_state {
1932         struct _ATOM_PPLIB_STATE v1;
1933         struct _ATOM_PPLIB_STATE_V2 v2;
1934 };
1935
1936 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1937                                                  int state_index,
1938                                                  u32 misc, u32 misc2)
1939 {
1940         rdev->pm.power_state[state_index].misc = misc;
1941         rdev->pm.power_state[state_index].misc2 = misc2;
1942         /* order matters! */
1943         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1944                 rdev->pm.power_state[state_index].type =
1945                         POWER_STATE_TYPE_POWERSAVE;
1946         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1947                 rdev->pm.power_state[state_index].type =
1948                         POWER_STATE_TYPE_BATTERY;
1949         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1950                 rdev->pm.power_state[state_index].type =
1951                         POWER_STATE_TYPE_BATTERY;
1952         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1953                 rdev->pm.power_state[state_index].type =
1954                         POWER_STATE_TYPE_BALANCED;
1955         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1956                 rdev->pm.power_state[state_index].type =
1957                         POWER_STATE_TYPE_PERFORMANCE;
1958                 rdev->pm.power_state[state_index].flags &=
1959                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1960         }
1961         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1962                 rdev->pm.power_state[state_index].type =
1963                         POWER_STATE_TYPE_BALANCED;
1964         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1965                 rdev->pm.power_state[state_index].type =
1966                         POWER_STATE_TYPE_DEFAULT;
1967                 rdev->pm.default_power_state_index = state_index;
1968                 rdev->pm.power_state[state_index].default_clock_mode =
1969                         &rdev->pm.power_state[state_index].clock_info[0];
1970         } else if (state_index == 0) {
1971                 rdev->pm.power_state[state_index].clock_info[0].flags |=
1972                         RADEON_PM_MODE_NO_DISPLAY;
1973         }
1974 }
1975
1976 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
1977 {
1978         struct radeon_mode_info *mode_info = &rdev->mode_info;
1979         u32 misc, misc2 = 0;
1980         int num_modes = 0, i;
1981         int state_index = 0;
1982         struct radeon_i2c_bus_rec i2c_bus;
1983         union power_info *power_info;
1984         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1985         u16 data_offset;
1986         u8 frev, crev;
1987
1988         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1989                                    &frev, &crev, &data_offset))
1990                 return state_index;
1991         power_info = (union power_info *)((char *)mode_info->atom_context->bios + data_offset);
1992
1993         /* add the i2c bus for thermal/fan chip */
1994         if ((power_info->info.ucOverdriveThermalController > 0) &&
1995             (power_info->info.ucOverdriveThermalController < DRM_ARRAY_SIZE(thermal_controller_names))) {
1996                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1997                          thermal_controller_names[power_info->info.ucOverdriveThermalController],
1998                          power_info->info.ucOverdriveControllerAddress >> 1);
1999                 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2000                 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2001 #ifdef DUMBBELL_WIP
2002                 if (rdev->pm.i2c_bus) {
2003                         struct i2c_board_info info = { };
2004                         const char *name = thermal_controller_names[power_info->info.
2005                                                                     ucOverdriveThermalController];
2006                         info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2007                         strlcpy(info.type, name, sizeof(info.type));
2008                         i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2009                 }
2010 #endif /* DUMBBELL_WIP */
2011         }
2012         num_modes = power_info->info.ucNumOfPowerModeEntries;
2013         if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2014                 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2015         if (num_modes == 0)
2016                 return state_index;
2017         rdev->pm.power_state = kmalloc(sizeof(struct radeon_power_state) * num_modes,
2018             M_DRM, M_WAITOK | M_ZERO);
2019         if (!rdev->pm.power_state)
2020                 return state_index;
2021         /* last mode is usually default, array is low to high */
2022         for (i = 0; i < num_modes; i++) {
2023                 rdev->pm.power_state[state_index].clock_info =
2024                         kmalloc(sizeof(struct radeon_pm_clock_info) * 1,
2025                             M_DRM, M_WAITOK | M_ZERO);
2026                 if (!rdev->pm.power_state[state_index].clock_info)
2027                         return state_index;
2028                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2029                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2030                 switch (frev) {
2031                 case 1:
2032                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2033                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2034                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2035                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2036                         /* skip invalid modes */
2037                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2038                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2039                                 continue;
2040                         rdev->pm.power_state[state_index].pcie_lanes =
2041                                 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2042                         misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2043                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2044                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2045                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2046                                         VOLTAGE_GPIO;
2047                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2048                                         radeon_lookup_gpio(rdev,
2049                                                            power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2050                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2051                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2052                                                 true;
2053                                 else
2054                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2055                                                 false;
2056                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2057                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2058                                         VOLTAGE_VDDC;
2059                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2060                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2061                         }
2062                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2063                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2064                         state_index++;
2065                         break;
2066                 case 2:
2067                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2068                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2069                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2070                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2071                         /* skip invalid modes */
2072                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2073                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2074                                 continue;
2075                         rdev->pm.power_state[state_index].pcie_lanes =
2076                                 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2077                         misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2078                         misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2079                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2080                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2081                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2082                                         VOLTAGE_GPIO;
2083                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2084                                         radeon_lookup_gpio(rdev,
2085                                                            power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2086                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2087                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2088                                                 true;
2089                                 else
2090                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2091                                                 false;
2092                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2093                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2094                                         VOLTAGE_VDDC;
2095                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2096                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2097                         }
2098                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2099                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2100                         state_index++;
2101                         break;
2102                 case 3:
2103                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2104                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2105                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2106                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2107                         /* skip invalid modes */
2108                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2109                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2110                                 continue;
2111                         rdev->pm.power_state[state_index].pcie_lanes =
2112                                 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2113                         misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2114                         misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2115                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2116                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2117                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2118                                         VOLTAGE_GPIO;
2119                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2120                                         radeon_lookup_gpio(rdev,
2121                                                            power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2122                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2123                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2124                                                 true;
2125                                 else
2126                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2127                                                 false;
2128                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2129                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2130                                         VOLTAGE_VDDC;
2131                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2132                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2133                                 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2134                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2135                                                 true;
2136                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2137                                                 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2138                                 }
2139                         }
2140                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2141                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2142                         state_index++;
2143                         break;
2144                 }
2145         }
2146         /* last mode is usually default */
2147         if (rdev->pm.default_power_state_index == -1) {
2148                 rdev->pm.power_state[state_index - 1].type =
2149                         POWER_STATE_TYPE_DEFAULT;
2150                 rdev->pm.default_power_state_index = state_index - 1;
2151                 rdev->pm.power_state[state_index - 1].default_clock_mode =
2152                         &rdev->pm.power_state[state_index - 1].clock_info[0];
2153                 rdev->pm.power_state[state_index].flags &=
2154                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2155                 rdev->pm.power_state[state_index].misc = 0;
2156                 rdev->pm.power_state[state_index].misc2 = 0;
2157         }
2158         return state_index;
2159 }
2160
2161 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2162                                                          ATOM_PPLIB_THERMALCONTROLLER *controller)
2163 {
2164         struct radeon_i2c_bus_rec i2c_bus;
2165
2166         /* add the i2c bus for thermal/fan chip */
2167         if (controller->ucType > 0) {
2168                 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2169                         DRM_INFO("Internal thermal controller %s fan control\n",
2170                                  (controller->ucFanParameters &
2171                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2172                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2173                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2174                         DRM_INFO("Internal thermal controller %s fan control\n",
2175                                  (controller->ucFanParameters &
2176                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2177                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2178                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2179                         DRM_INFO("Internal thermal controller %s fan control\n",
2180                                  (controller->ucFanParameters &
2181                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2182                         rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2183                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2184                         DRM_INFO("Internal thermal controller %s fan control\n",
2185                                  (controller->ucFanParameters &
2186                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2187                         rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2188                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2189                         DRM_INFO("Internal thermal controller %s fan control\n",
2190                                  (controller->ucFanParameters &
2191                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2192                         rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2193                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2194                         DRM_INFO("Internal thermal controller %s fan control\n",
2195                                  (controller->ucFanParameters &
2196                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2197                         rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2198                 } else if ((controller->ucType ==
2199                             ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2200                            (controller->ucType ==
2201                             ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2202                            (controller->ucType ==
2203                             ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
2204                         DRM_INFO("Special thermal controller config\n");
2205                 } else if (controller->ucType < DRM_ARRAY_SIZE(pp_lib_thermal_controller_names)) {
2206                         DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2207                                  pp_lib_thermal_controller_names[controller->ucType],
2208                                  controller->ucI2cAddress >> 1,
2209                                  (controller->ucFanParameters &
2210                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2211                         i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2212                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2213 #ifdef DUMBBELL_WIP
2214                         if (rdev->pm.i2c_bus) {
2215                                 struct i2c_board_info info = { };
2216                                 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2217                                 info.addr = controller->ucI2cAddress >> 1;
2218                                 strlcpy(info.type, name, sizeof(info.type));
2219                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2220                         }
2221 #endif /* DUMBBELL_WIP */
2222                 } else {
2223                         DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2224                                  controller->ucType,
2225                                  controller->ucI2cAddress >> 1,
2226                                  (controller->ucFanParameters &
2227                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2228                 }
2229         }
2230 }
2231
2232 static void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2233                                                  u16 *vddc, u16 *vddci)
2234 {
2235         struct radeon_mode_info *mode_info = &rdev->mode_info;
2236         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2237         u8 frev, crev;
2238         u16 data_offset;
2239         union firmware_info *firmware_info;
2240
2241         *vddc = 0;
2242         *vddci = 0;
2243
2244         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2245                                    &frev, &crev, &data_offset)) {
2246                 firmware_info =
2247                         (union firmware_info *)((char *)mode_info->atom_context->bios +
2248                                                 data_offset);
2249                 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2250                 if ((frev == 2) && (crev >= 2))
2251                         *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2252         }
2253 }
2254
2255 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2256                                                        int state_index, int mode_index,
2257                                                        struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2258 {
2259         int j;
2260         u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2261         u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2262         u16 vddc, vddci;
2263
2264         radeon_atombios_get_default_voltages(rdev, &vddc, &vddci);
2265
2266         rdev->pm.power_state[state_index].misc = misc;
2267         rdev->pm.power_state[state_index].misc2 = misc2;
2268         rdev->pm.power_state[state_index].pcie_lanes =
2269                 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2270                  ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2271         switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2272         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2273                 rdev->pm.power_state[state_index].type =
2274                         POWER_STATE_TYPE_BATTERY;
2275                 break;
2276         case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2277                 rdev->pm.power_state[state_index].type =
2278                         POWER_STATE_TYPE_BALANCED;
2279                 break;
2280         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2281                 rdev->pm.power_state[state_index].type =
2282                         POWER_STATE_TYPE_PERFORMANCE;
2283                 break;
2284         case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2285                 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2286                         rdev->pm.power_state[state_index].type =
2287                                 POWER_STATE_TYPE_PERFORMANCE;
2288                 break;
2289         }
2290         rdev->pm.power_state[state_index].flags = 0;
2291         if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2292                 rdev->pm.power_state[state_index].flags |=
2293                         RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2294         if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2295                 rdev->pm.power_state[state_index].type =
2296                         POWER_STATE_TYPE_DEFAULT;
2297                 rdev->pm.default_power_state_index = state_index;
2298                 rdev->pm.power_state[state_index].default_clock_mode =
2299                         &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2300                 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
2301                         /* NI chips post without MC ucode, so default clocks are strobe mode only */
2302                         rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2303                         rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2304                         rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2305                         rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2306                 } else {
2307                         /* patch the table values with the default slck/mclk from firmware info */
2308                         for (j = 0; j < mode_index; j++) {
2309                                 rdev->pm.power_state[state_index].clock_info[j].mclk =
2310                                         rdev->clock.default_mclk;
2311                                 rdev->pm.power_state[state_index].clock_info[j].sclk =
2312                                         rdev->clock.default_sclk;
2313                                 if (vddc)
2314                                         rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2315                                                 vddc;
2316                         }
2317                 }
2318         }
2319 }
2320
2321 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2322                                                    int state_index, int mode_index,
2323                                                    union pplib_clock_info *clock_info)
2324 {
2325         u32 sclk, mclk;
2326         u16 vddc;
2327
2328         if (rdev->flags & RADEON_IS_IGP) {
2329                 if (rdev->family >= CHIP_PALM) {
2330                         sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2331                         sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2332                         rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2333                 } else {
2334                         sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2335                         sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2336                         rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2337                 }
2338         } else if (rdev->family >= CHIP_TAHITI) {
2339                 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2340                 sclk |= clock_info->si.ucEngineClockHigh << 16;
2341                 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2342                 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2343                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2344                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2345                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2346                         VOLTAGE_SW;
2347                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2348                         le16_to_cpu(clock_info->si.usVDDC);
2349                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2350                         le16_to_cpu(clock_info->si.usVDDCI);
2351         } else if (rdev->family >= CHIP_CEDAR) {
2352                 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2353                 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2354                 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2355                 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2356                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2357                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2358                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2359                         VOLTAGE_SW;
2360                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2361                         le16_to_cpu(clock_info->evergreen.usVDDC);
2362                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2363                         le16_to_cpu(clock_info->evergreen.usVDDCI);
2364         } else {
2365                 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2366                 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2367                 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2368                 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2369                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2370                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2371                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2372                         VOLTAGE_SW;
2373                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2374                         le16_to_cpu(clock_info->r600.usVDDC);
2375         }
2376
2377         /* patch up vddc if necessary */
2378         switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2379         case ATOM_VIRTUAL_VOLTAGE_ID0:
2380         case ATOM_VIRTUAL_VOLTAGE_ID1:
2381         case ATOM_VIRTUAL_VOLTAGE_ID2:
2382         case ATOM_VIRTUAL_VOLTAGE_ID3:
2383                 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2384                                              rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2385                                              &vddc) == 0)
2386                         rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2387                 break;
2388         default:
2389                 break;
2390         }
2391
2392         if (rdev->flags & RADEON_IS_IGP) {
2393                 /* skip invalid modes */
2394                 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2395                         return false;
2396         } else {
2397                 /* skip invalid modes */
2398                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2399                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2400                         return false;
2401         }
2402         return true;
2403 }
2404
2405 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2406 {
2407         struct radeon_mode_info *mode_info = &rdev->mode_info;
2408         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2409         union pplib_power_state *power_state;
2410         int i, j;
2411         int state_index = 0, mode_index = 0;
2412         union pplib_clock_info *clock_info;
2413         bool valid;
2414         union power_info *power_info;
2415         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2416         u16 data_offset;
2417         u8 frev, crev;
2418
2419         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2420                                    &frev, &crev, &data_offset))
2421                 return state_index;
2422         power_info = (union power_info *)((char *)mode_info->atom_context->bios + data_offset);
2423
2424         radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2425         if (power_info->pplib.ucNumStates == 0)
2426                 return state_index;
2427         rdev->pm.power_state = kmalloc(sizeof(struct radeon_power_state) *
2428                                        power_info->pplib.ucNumStates,
2429                                        M_DRM, M_WAITOK | M_ZERO);
2430         if (!rdev->pm.power_state)
2431                 return state_index;
2432         /* first mode is usually default, followed by low to high */
2433         for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2434                 mode_index = 0;
2435                 power_state = (union pplib_power_state *)
2436                         ((char *)mode_info->atom_context->bios + data_offset +
2437                          le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2438                          i * power_info->pplib.ucStateEntrySize);
2439                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2440                         ((char *)mode_info->atom_context->bios + data_offset +
2441                          le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2442                          (power_state->v1.ucNonClockStateIndex *
2443                           power_info->pplib.ucNonClockSize));
2444                 rdev->pm.power_state[i].clock_info = kmalloc(sizeof(struct radeon_pm_clock_info) *
2445                                                              ((power_info->pplib.ucStateEntrySize - 1) ?
2446                                                               (power_info->pplib.ucStateEntrySize - 1) : 1),
2447                                                              M_DRM, M_WAITOK | M_ZERO);
2448                 if (!rdev->pm.power_state[i].clock_info)
2449                         return state_index;
2450                 if (power_info->pplib.ucStateEntrySize - 1) {
2451                         for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2452                                 clock_info = (union pplib_clock_info *)
2453                                         ((char *)mode_info->atom_context->bios + data_offset +
2454                                          le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2455                                          (power_state->v1.ucClockStateIndices[j] *
2456                                           power_info->pplib.ucClockInfoSize));
2457                                 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2458                                                                                state_index, mode_index,
2459                                                                                clock_info);
2460                                 if (valid)
2461                                         mode_index++;
2462                         }
2463                 } else {
2464                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2465                                 rdev->clock.default_mclk;
2466                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2467                                 rdev->clock.default_sclk;
2468                         mode_index++;
2469                 }
2470                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2471                 if (mode_index) {
2472                         radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2473                                                                    non_clock_info);
2474                         state_index++;
2475                 }
2476         }
2477         /* if multiple clock modes, mark the lowest as no display */
2478         for (i = 0; i < state_index; i++) {
2479                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2480                         rdev->pm.power_state[i].clock_info[0].flags |=
2481                                 RADEON_PM_MODE_NO_DISPLAY;
2482         }
2483         /* first mode is usually default */
2484         if (rdev->pm.default_power_state_index == -1) {
2485                 rdev->pm.power_state[0].type =
2486                         POWER_STATE_TYPE_DEFAULT;
2487                 rdev->pm.default_power_state_index = 0;
2488                 rdev->pm.power_state[0].default_clock_mode =
2489                         &rdev->pm.power_state[0].clock_info[0];
2490         }
2491         return state_index;
2492 }
2493
2494 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2495 {
2496         struct radeon_mode_info *mode_info = &rdev->mode_info;
2497         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2498         union pplib_power_state *power_state;
2499         int i, j, non_clock_array_index, clock_array_index;
2500         int state_index = 0, mode_index = 0;
2501         union pplib_clock_info *clock_info;
2502         struct _StateArray *state_array;
2503         struct _ClockInfoArray *clock_info_array;
2504         struct _NonClockInfoArray *non_clock_info_array;
2505         bool valid;
2506         union power_info *power_info;
2507         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2508         u16 data_offset;
2509         u8 frev, crev;
2510         u8 *power_state_offset;
2511
2512         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2513                                    &frev, &crev, &data_offset))
2514                 return state_index;
2515         power_info = (union power_info *)((char *)mode_info->atom_context->bios + data_offset);
2516
2517         radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2518         state_array = (struct _StateArray *)
2519                 ((char *)mode_info->atom_context->bios + data_offset +
2520                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
2521         clock_info_array = (struct _ClockInfoArray *)
2522                 ((char *)mode_info->atom_context->bios + data_offset +
2523                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2524         non_clock_info_array = (struct _NonClockInfoArray *)
2525                 ((char *)mode_info->atom_context->bios + data_offset +
2526                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2527         if (state_array->ucNumEntries == 0)
2528                 return state_index;
2529         rdev->pm.power_state = kmalloc(sizeof(struct radeon_power_state) *
2530                                        state_array->ucNumEntries,
2531                                        M_DRM, M_WAITOK | M_ZERO);
2532         if (!rdev->pm.power_state)
2533                 return state_index;
2534         power_state_offset = (u8 *)state_array->states;
2535         for (i = 0; i < state_array->ucNumEntries; i++) {
2536                 mode_index = 0;
2537                 power_state = (union pplib_power_state *)power_state_offset;
2538                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2539                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2540                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
2541                 rdev->pm.power_state[i].clock_info = kmalloc(sizeof(struct radeon_pm_clock_info) *
2542                                                              (power_state->v2.ucNumDPMLevels ?
2543                                                               power_state->v2.ucNumDPMLevels : 1),
2544                                                              M_DRM, M_WAITOK | M_ZERO);
2545                 if (!rdev->pm.power_state[i].clock_info)
2546                         return state_index;
2547                 if (power_state->v2.ucNumDPMLevels) {
2548                         for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2549                                 clock_array_index = power_state->v2.clockInfoIndex[j];
2550                                 clock_info = (union pplib_clock_info *)
2551                                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2552                                 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2553                                                                                state_index, mode_index,
2554                                                                                clock_info);
2555                                 if (valid)
2556                                         mode_index++;
2557                         }
2558                 } else {
2559                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2560                                 rdev->clock.default_mclk;
2561                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2562                                 rdev->clock.default_sclk;
2563                         mode_index++;
2564                 }
2565                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2566                 if (mode_index) {
2567                         radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2568                                                                    non_clock_info);
2569                         state_index++;
2570                 }
2571                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2572         }
2573         /* if multiple clock modes, mark the lowest as no display */
2574         for (i = 0; i < state_index; i++) {
2575                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2576                         rdev->pm.power_state[i].clock_info[0].flags |=
2577                                 RADEON_PM_MODE_NO_DISPLAY;
2578         }
2579         /* first mode is usually default */
2580         if (rdev->pm.default_power_state_index == -1) {
2581                 rdev->pm.power_state[0].type =
2582                         POWER_STATE_TYPE_DEFAULT;
2583                 rdev->pm.default_power_state_index = 0;
2584                 rdev->pm.power_state[0].default_clock_mode =
2585                         &rdev->pm.power_state[0].clock_info[0];
2586         }
2587         return state_index;
2588 }
2589
2590 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2591 {
2592         struct radeon_mode_info *mode_info = &rdev->mode_info;
2593         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2594         u16 data_offset;
2595         u8 frev, crev;
2596         int state_index = 0;
2597
2598         rdev->pm.default_power_state_index = -1;
2599
2600         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2601                                    &frev, &crev, &data_offset)) {
2602                 switch (frev) {
2603                 case 1:
2604                 case 2:
2605                 case 3:
2606                         state_index = radeon_atombios_parse_power_table_1_3(rdev);
2607                         break;
2608                 case 4:
2609                 case 5:
2610                         state_index = radeon_atombios_parse_power_table_4_5(rdev);
2611                         break;
2612                 case 6:
2613                         state_index = radeon_atombios_parse_power_table_6(rdev);
2614                         break;
2615                 default:
2616                         break;
2617                 }
2618         }
2619
2620         if (state_index == 0) {
2621                 rdev->pm.power_state = kmalloc(sizeof(struct radeon_power_state),
2622                     M_DRM, M_WAITOK | M_ZERO);
2623                 if (rdev->pm.power_state) {
2624                         rdev->pm.power_state[0].clock_info =
2625                                 kmalloc(sizeof(struct radeon_pm_clock_info) * 1,
2626                                     M_DRM, M_WAITOK | M_ZERO);
2627                         if (rdev->pm.power_state[0].clock_info) {
2628                                 /* add the default mode */
2629                                 rdev->pm.power_state[state_index].type =
2630                                         POWER_STATE_TYPE_DEFAULT;
2631                                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2632                                 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2633                                 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2634                                 rdev->pm.power_state[state_index].default_clock_mode =
2635                                         &rdev->pm.power_state[state_index].clock_info[0];
2636                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2637                                 rdev->pm.power_state[state_index].pcie_lanes = 16;
2638                                 rdev->pm.default_power_state_index = state_index;
2639                                 rdev->pm.power_state[state_index].flags = 0;
2640                                 state_index++;
2641                         }
2642                 }
2643         }
2644
2645         rdev->pm.num_power_states = state_index;
2646
2647         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2648         rdev->pm.current_clock_mode_index = 0;
2649         if (rdev->pm.default_power_state_index >= 0)
2650                 rdev->pm.current_vddc =
2651                         rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2652         else
2653                 rdev->pm.current_vddc = 0;
2654 }
2655
2656 union get_clock_dividers {
2657         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
2658         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
2659         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
2660         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
2661         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
2662 };
2663
2664 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2665                                    u8 clock_type,
2666                                    u32 clock,
2667                                    bool strobe_mode,
2668                                    struct atom_clock_dividers *dividers)
2669 {
2670         union get_clock_dividers args;
2671         int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
2672         u8 frev, crev;
2673
2674         memset(&args, 0, sizeof(args));
2675         memset(dividers, 0, sizeof(struct atom_clock_dividers));
2676
2677         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2678                 return -EINVAL;
2679
2680         switch (crev) {
2681         case 1:
2682                 /* r4xx, r5xx */
2683                 args.v1.ucAction = clock_type;
2684                 args.v1.ulClock = cpu_to_le32(clock);   /* 10 khz */
2685
2686                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2687
2688                 dividers->post_div = args.v1.ucPostDiv;
2689                 dividers->fb_div = args.v1.ucFbDiv;
2690                 dividers->enable_post_div = true;
2691                 break;
2692         case 2:
2693         case 3:
2694                 /* r6xx, r7xx, evergreen, ni */
2695                 if (rdev->family <= CHIP_RV770) {
2696                         args.v2.ucAction = clock_type;
2697                         args.v2.ulClock = cpu_to_le32(clock);   /* 10 khz */
2698
2699                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2700
2701                         dividers->post_div = args.v2.ucPostDiv;
2702                         dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
2703                         dividers->ref_div = args.v2.ucAction;
2704                         if (rdev->family == CHIP_RV770) {
2705                                 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
2706                                         true : false;
2707                                 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;
2708                         } else
2709                                 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
2710                 } else {
2711                         if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
2712                                 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2713
2714                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2715
2716                                 dividers->post_div = args.v3.ucPostDiv;
2717                                 dividers->enable_post_div = (args.v3.ucCntlFlag &
2718                                                              ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2719                                 dividers->enable_dithen = (args.v3.ucCntlFlag &
2720                                                            ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2721                                 dividers->fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
2722                                 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
2723                                 dividers->ref_div = args.v3.ucRefDiv;
2724                                 dividers->vco_mode = (args.v3.ucCntlFlag &
2725                                                       ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2726                         } else {
2727                                 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2728                                 if (strobe_mode)
2729                                         args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
2730
2731                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2732
2733                                 dividers->post_div = args.v5.ucPostDiv;
2734                                 dividers->enable_post_div = (args.v5.ucCntlFlag &
2735                                                              ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2736                                 dividers->enable_dithen = (args.v5.ucCntlFlag &
2737                                                            ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2738                                 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
2739                                 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
2740                                 dividers->ref_div = args.v5.ucRefDiv;
2741                                 dividers->vco_mode = (args.v5.ucCntlFlag &
2742                                                       ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2743                         }
2744                 }
2745                 break;
2746         case 4:
2747                 /* fusion */
2748                 args.v4.ulClock = cpu_to_le32(clock);   /* 10 khz */
2749
2750                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2751
2752                 dividers->post_div = args.v4.ucPostDiv;
2753                 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
2754                 break;
2755         default:
2756                 return -EINVAL;
2757         }
2758         return 0;
2759 }
2760
2761 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2762 {
2763         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2764         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2765
2766         args.ucEnable = enable;
2767
2768         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2769 }
2770
2771 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2772 {
2773         GET_ENGINE_CLOCK_PS_ALLOCATION args;
2774         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2775
2776         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2777         return le32_to_cpu(args.ulReturnEngineClock);
2778 }
2779
2780 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2781 {
2782         GET_MEMORY_CLOCK_PS_ALLOCATION args;
2783         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2784
2785         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2786         return le32_to_cpu(args.ulReturnMemoryClock);
2787 }
2788
2789 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2790                                   uint32_t eng_clock)
2791 {
2792         SET_ENGINE_CLOCK_PS_ALLOCATION args;
2793         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2794
2795         args.ulTargetEngineClock = cpu_to_le32(eng_clock);      /* 10 khz */
2796
2797         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2798 }
2799
2800 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2801                                   uint32_t mem_clock)
2802 {
2803         SET_MEMORY_CLOCK_PS_ALLOCATION args;
2804         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2805
2806         if (rdev->flags & RADEON_IS_IGP)
2807                 return;
2808
2809         args.ulTargetMemoryClock = cpu_to_le32(mem_clock);      /* 10 khz */
2810
2811         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2812 }
2813
2814 union set_voltage {
2815         struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2816         struct _SET_VOLTAGE_PARAMETERS v1;
2817         struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2818         struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
2819 };
2820
2821 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
2822 {
2823         union set_voltage args;
2824         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2825         u8 frev, crev, volt_index = voltage_level;
2826
2827         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2828                 return;
2829
2830         /* 0xff01 is a flag rather then an actual voltage */
2831         if (voltage_level == 0xff01)
2832                 return;
2833
2834         switch (crev) {
2835         case 1:
2836                 args.v1.ucVoltageType = voltage_type;
2837                 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2838                 args.v1.ucVoltageIndex = volt_index;
2839                 break;
2840         case 2:
2841                 args.v2.ucVoltageType = voltage_type;
2842                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2843                 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
2844                 break;
2845         case 3:
2846                 args.v3.ucVoltageType = voltage_type;
2847                 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
2848                 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
2849                 break;
2850         default:
2851                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2852                 return;
2853         }
2854
2855         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2856 }
2857
2858 static int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
2859                                     u16 voltage_id, u16 *voltage)
2860 {
2861         union set_voltage args;
2862         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2863         u8 frev, crev;
2864
2865         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2866                 return -EINVAL;
2867
2868         switch (crev) {
2869         case 1:
2870                 return -EINVAL;
2871         case 2:
2872                 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
2873                 args.v2.ucVoltageMode = 0;
2874                 args.v2.usVoltageLevel = 0;
2875
2876                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2877
2878                 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
2879                 break;
2880         case 3:
2881                 args.v3.ucVoltageType = voltage_type;
2882                 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
2883                 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
2884
2885                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2886
2887                 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
2888                 break;
2889         default:
2890                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2891                 return -EINVAL;
2892         }
2893
2894         return 0;
2895 }
2896
2897 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2898 {
2899         struct radeon_device *rdev = dev->dev_private;
2900         uint32_t bios_2_scratch, bios_6_scratch;
2901
2902         if (rdev->family >= CHIP_R600) {
2903                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2904                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2905         } else {
2906                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2907                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2908         }
2909
2910         /* let the bios control the backlight */
2911         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2912
2913         /* tell the bios not to handle mode switching */
2914         bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
2915
2916         if (rdev->family >= CHIP_R600) {
2917                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2918                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2919         } else {
2920                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2921                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2922         }
2923
2924 }
2925
2926 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2927 {
2928         uint32_t scratch_reg;
2929         int i;
2930
2931         if (rdev->family >= CHIP_R600)
2932                 scratch_reg = R600_BIOS_0_SCRATCH;
2933         else
2934                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2935
2936         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2937                 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2938 }
2939
2940 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2941 {
2942         uint32_t scratch_reg;
2943         int i;
2944
2945         if (rdev->family >= CHIP_R600)
2946                 scratch_reg = R600_BIOS_0_SCRATCH;
2947         else
2948                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2949
2950         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2951                 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2952 }
2953
2954 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2955 {
2956         struct drm_device *dev = encoder->dev;
2957         struct radeon_device *rdev = dev->dev_private;
2958         uint32_t bios_6_scratch;
2959
2960         if (rdev->family >= CHIP_R600)
2961                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2962         else
2963                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2964
2965         if (lock) {
2966                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2967                 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
2968         } else {
2969                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2970                 bios_6_scratch |= ATOM_S6_ACC_MODE;
2971         }
2972
2973         if (rdev->family >= CHIP_R600)
2974                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2975         else
2976                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2977 }
2978
2979 /* at some point we may want to break this out into individual functions */
2980 void
2981 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2982                                        struct drm_encoder *encoder,
2983                                        bool connected)
2984 {
2985         struct drm_device *dev = connector->dev;
2986         struct radeon_device *rdev = dev->dev_private;
2987         struct radeon_connector *radeon_connector =
2988             to_radeon_connector(connector);
2989         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2990         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2991
2992         if (rdev->family >= CHIP_R600) {
2993                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2994                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2995                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2996         } else {
2997                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2998                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2999                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3000         }
3001
3002         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3003             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3004                 if (connected) {
3005                         DRM_DEBUG_KMS("TV1 connected\n");
3006                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
3007                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
3008                 } else {
3009                         DRM_DEBUG_KMS("TV1 disconnected\n");
3010                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
3011                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
3012                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
3013                 }
3014         }
3015         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
3016             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
3017                 if (connected) {
3018                         DRM_DEBUG_KMS("CV connected\n");
3019                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
3020                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
3021                 } else {
3022                         DRM_DEBUG_KMS("CV disconnected\n");
3023                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
3024                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
3025                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
3026                 }
3027         }
3028         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3029             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3030                 if (connected) {
3031                         DRM_DEBUG_KMS("LCD1 connected\n");
3032                         bios_0_scratch |= ATOM_S0_LCD1;
3033                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
3034                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
3035                 } else {
3036                         DRM_DEBUG_KMS("LCD1 disconnected\n");
3037                         bios_0_scratch &= ~ATOM_S0_LCD1;
3038                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
3039                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
3040                 }
3041         }
3042         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3043             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3044                 if (connected) {
3045                         DRM_DEBUG_KMS("CRT1 connected\n");
3046                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
3047                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
3048                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
3049                 } else {
3050                         DRM_DEBUG_KMS("CRT1 disconnected\n");
3051                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
3052                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
3053                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
3054                 }
3055         }
3056         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3057             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3058                 if (connected) {
3059                         DRM_DEBUG_KMS("CRT2 connected\n");
3060                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
3061                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
3062                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
3063                 } else {
3064                         DRM_DEBUG_KMS("CRT2 disconnected\n");
3065                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
3066                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
3067                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
3068                 }
3069         }
3070         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3071             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3072                 if (connected) {
3073                         DRM_DEBUG_KMS("DFP1 connected\n");
3074                         bios_0_scratch |= ATOM_S0_DFP1;
3075                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
3076                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
3077                 } else {
3078                         DRM_DEBUG_KMS("DFP1 disconnected\n");
3079                         bios_0_scratch &= ~ATOM_S0_DFP1;
3080                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
3081                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
3082                 }
3083         }
3084         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3085             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3086                 if (connected) {
3087                         DRM_DEBUG_KMS("DFP2 connected\n");
3088                         bios_0_scratch |= ATOM_S0_DFP2;
3089                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
3090                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
3091                 } else {
3092                         DRM_DEBUG_KMS("DFP2 disconnected\n");
3093                         bios_0_scratch &= ~ATOM_S0_DFP2;
3094                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
3095                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
3096                 }
3097         }
3098         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
3099             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
3100                 if (connected) {
3101                         DRM_DEBUG_KMS("DFP3 connected\n");
3102                         bios_0_scratch |= ATOM_S0_DFP3;
3103                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
3104                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
3105                 } else {
3106                         DRM_DEBUG_KMS("DFP3 disconnected\n");
3107                         bios_0_scratch &= ~ATOM_S0_DFP3;
3108                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
3109                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
3110                 }
3111         }
3112         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
3113             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
3114                 if (connected) {
3115                         DRM_DEBUG_KMS("DFP4 connected\n");
3116                         bios_0_scratch |= ATOM_S0_DFP4;
3117                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
3118                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
3119                 } else {
3120                         DRM_DEBUG_KMS("DFP4 disconnected\n");
3121                         bios_0_scratch &= ~ATOM_S0_DFP4;
3122                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
3123                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
3124                 }
3125         }
3126         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
3127             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
3128                 if (connected) {
3129                         DRM_DEBUG_KMS("DFP5 connected\n");
3130                         bios_0_scratch |= ATOM_S0_DFP5;
3131                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
3132                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
3133                 } else {
3134                         DRM_DEBUG_KMS("DFP5 disconnected\n");
3135                         bios_0_scratch &= ~ATOM_S0_DFP5;
3136                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
3137                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
3138                 }
3139         }
3140         if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
3141             (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
3142                 if (connected) {
3143                         DRM_DEBUG_KMS("DFP6 connected\n");
3144                         bios_0_scratch |= ATOM_S0_DFP6;
3145                         bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
3146                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
3147                 } else {
3148                         DRM_DEBUG_KMS("DFP6 disconnected\n");
3149                         bios_0_scratch &= ~ATOM_S0_DFP6;
3150                         bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
3151                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
3152                 }
3153         }
3154
3155         if (rdev->family >= CHIP_R600) {
3156                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
3157                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
3158                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
3159         } else {
3160                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3161                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
3162                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3163         }
3164 }
3165
3166 void
3167 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3168 {
3169         struct drm_device *dev = encoder->dev;
3170         struct radeon_device *rdev = dev->dev_private;
3171         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3172         uint32_t bios_3_scratch;
3173
3174         if (ASIC_IS_DCE4(rdev))
3175                 return;
3176
3177         if (rdev->family >= CHIP_R600)
3178                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
3179         else
3180                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
3181
3182         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3183                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
3184                 bios_3_scratch |= (crtc << 18);
3185         }
3186         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
3187                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
3188                 bios_3_scratch |= (crtc << 24);
3189         }
3190         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3191                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
3192                 bios_3_scratch |= (crtc << 16);
3193         }
3194         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3195                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
3196                 bios_3_scratch |= (crtc << 20);
3197         }
3198         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3199                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
3200                 bios_3_scratch |= (crtc << 17);
3201         }
3202         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3203                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
3204                 bios_3_scratch |= (crtc << 19);
3205         }
3206         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3207                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
3208                 bios_3_scratch |= (crtc << 23);
3209         }
3210         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3211                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
3212                 bios_3_scratch |= (crtc << 25);
3213         }
3214
3215         if (rdev->family >= CHIP_R600)
3216                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
3217         else
3218                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
3219 }
3220
3221 void
3222 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3223 {
3224         struct drm_device *dev = encoder->dev;
3225         struct radeon_device *rdev = dev->dev_private;
3226         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3227         uint32_t bios_2_scratch;
3228
3229         if (ASIC_IS_DCE4(rdev))
3230                 return;
3231
3232         if (rdev->family >= CHIP_R600)
3233                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
3234         else
3235                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
3236
3237         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3238                 if (on)
3239                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
3240                 else
3241                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
3242         }
3243         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
3244                 if (on)
3245                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
3246                 else
3247                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
3248         }
3249         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3250                 if (on)
3251                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
3252                 else
3253                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
3254         }
3255         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3256                 if (on)
3257                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
3258                 else
3259                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
3260         }
3261         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3262                 if (on)
3263                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
3264                 else
3265                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
3266         }
3267         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3268                 if (on)
3269                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
3270                 else
3271                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
3272         }
3273         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3274                 if (on)
3275                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
3276                 else
3277                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
3278         }
3279         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3280                 if (on)
3281                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
3282                 else
3283                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
3284         }
3285         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
3286                 if (on)
3287                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
3288                 else
3289                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
3290         }
3291         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
3292                 if (on)
3293                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
3294                 else
3295                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
3296         }
3297
3298         if (rdev->family >= CHIP_R600)
3299                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
3300         else
3301                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
3302 }