sys/dev/drm/radeon/radeon_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  *
  26  * $FreeBSD: head/sys/dev/drm2/radeon/radeon_display.c 254885 2013-08-25 19:37:15Z dumbbell $
  27  */
  28
  29 #include <drm/drmP.h>
  30 #include <uapi_drm/radeon_drm.h>
  31 #include "radeon.h"
  32
  33 #include "atom.h"
  34
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_edid.h>
  37 #include <linux/err.h>
  38
  39 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
  40 {
  41         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  42         struct drm_device *dev = crtc->dev;
  43         struct radeon_device *rdev = dev->dev_private;
  44         int i;
  45
  46         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  47         WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
  48
  49         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  50         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  51         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  52
  53         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  54         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  55         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  56
  57         WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
  58         WREG32(AVIVO_DC_LUT_RW_MODE, 0);
  59         WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
  60
  61         WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
  62         for (i = 0; i < 256; i++) {
  63                 WREG32(AVIVO_DC_LUT_30_COLOR,
  64                              (radeon_crtc->lut_r[i] << 20) |
  65                              (radeon_crtc->lut_g[i] << 10) |
  66                              (radeon_crtc->lut_b[i] << 0));
  67         }
  68
  69         WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
  70 }
  71
  72 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
  73 {
  74         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  75         struct drm_device *dev = crtc->dev;
  76         struct radeon_device *rdev = dev->dev_private;
  77         int i;
  78
  79         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  80         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
  81
  82         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  83         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  84         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  85
  86         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  87         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  88         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  89
  90         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
  91         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
  92
  93         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
  94         for (i = 0; i < 256; i++) {
  95                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
  96                        (radeon_crtc->lut_r[i] << 20) |
  97                        (radeon_crtc->lut_g[i] << 10) |
  98                        (radeon_crtc->lut_b[i] << 0));
  99         }
 100 }
 101
 102 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
 103 {
 104         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 105         struct drm_device *dev = crtc->dev;
 106         struct radeon_device *rdev = dev->dev_private;
 107         int i;
 108
 109         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
 110
 111         WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 112                (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
 113                 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
 114         WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
 115                NI_GRPH_PRESCALE_BYPASS);
 116         WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
 117                NI_OVL_PRESCALE_BYPASS);
 118         WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
 119                (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
 120                 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
 121
 122         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
 123
 124         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
 125         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
 126         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
 127
 128         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
 129         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
 130         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
 131
 132         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
 133         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
 134
 135         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
 136         for (i = 0; i < 256; i++) {
 137                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
 138                        (radeon_crtc->lut_r[i] << 20) |
 139                        (radeon_crtc->lut_g[i] << 10) |
 140                        (radeon_crtc->lut_b[i] << 0));
 141         }
 142
 143         WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
 144                (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 145                 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 146                 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 147                 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
 148         WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
 149                (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
 150                 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
 151         WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
 152                (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
 153                 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
 154         WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 155                (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
 156                 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
 157         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
 158         WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
 159
 160 }
 161
 162 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
 163 {
 164         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 165         struct drm_device *dev = crtc->dev;
 166         struct radeon_device *rdev = dev->dev_private;
 167         int i;
 168         uint32_t dac2_cntl;
 169
 170         dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 171         if (radeon_crtc->crtc_id == 0)
 172                 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
 173         else
 174                 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
 175         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 176
 177         WREG8(RADEON_PALETTE_INDEX, 0);
 178         for (i = 0; i < 256; i++) {
 179                 WREG32(RADEON_PALETTE_30_DATA,
 180                              (radeon_crtc->lut_r[i] << 20) |
 181                              (radeon_crtc->lut_g[i] << 10) |
 182                              (radeon_crtc->lut_b[i] << 0));
 183         }
 184 }
 185
 186 void radeon_crtc_load_lut(struct drm_crtc *crtc)
 187 {
 188         struct drm_device *dev = crtc->dev;
 189         struct radeon_device *rdev = dev->dev_private;
 190
 191         if (!crtc->enabled)
 192                 return;
 193
 194         if (ASIC_IS_DCE5(rdev))
 195                 dce5_crtc_load_lut(crtc);
 196         else if (ASIC_IS_DCE4(rdev))
 197                 dce4_crtc_load_lut(crtc);
 198         else if (ASIC_IS_AVIVO(rdev))
 199                 avivo_crtc_load_lut(crtc);
 200         else
 201                 legacy_crtc_load_lut(crtc);
 202 }
 203
 204 /** Sets the color ramps on behalf of fbcon */
 205 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 206                               u16 blue, int regno)
 207 {
 208         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 209
 210         radeon_crtc->lut_r[regno] = red >> 6;
 211         radeon_crtc->lut_g[regno] = green >> 6;
 212         radeon_crtc->lut_b[regno] = blue >> 6;
 213 }
 214
 215 /** Gets the color ramps on behalf of fbcon */
 216 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 217                               u16 *blue, int regno)
 218 {
 219         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 220
 221         *red = radeon_crtc->lut_r[regno] << 6;
 222         *green = radeon_crtc->lut_g[regno] << 6;
 223         *blue = radeon_crtc->lut_b[regno] << 6;
 224 }
 225
 226 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 227                                   u16 *blue, uint32_t start, uint32_t size)
 228 {
 229         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 230         int end = (start + size > 256) ? 256 : start + size, i;
 231
 232         /* userspace palettes are always correct as is */
 233         for (i = start; i < end; i++) {
 234                 radeon_crtc->lut_r[i] = red[i] >> 6;
 235                 radeon_crtc->lut_g[i] = green[i] >> 6;
 236                 radeon_crtc->lut_b[i] = blue[i] >> 6;
 237         }
 238         radeon_crtc_load_lut(crtc);
 239 }
 240
 241 static void radeon_crtc_destroy(struct drm_crtc *crtc)
 242 {
 243         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 244
 245         drm_crtc_cleanup(crtc);
 246         drm_free(radeon_crtc, M_DRM);
 247 }
 248
 249 /*
 250  * Handle unpin events outside the interrupt handler proper.
 251  */
 252 static void radeon_unpin_work_func(void *arg, int pending)
 253 {
 254         struct radeon_unpin_work *work = arg;
 255         int r;
 256
 257         /* unpin of the old buffer */
 258         r = radeon_bo_reserve(work->old_rbo, false);
 259         if (likely(r == 0)) {
 260                 r = radeon_bo_unpin(work->old_rbo);
 261                 if (unlikely(r != 0)) {
 262                         DRM_ERROR("failed to unpin buffer after flip\n");
 263                 }
 264                 radeon_bo_unreserve(work->old_rbo);
 265         } else
 266                 DRM_ERROR("failed to reserve buffer after flip\n");
 267
 268         drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
 269         drm_free(work, M_DRM);
 270 }
 271
 272 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
 273 {
 274         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 275         struct radeon_unpin_work *work;
 276         u32 update_pending;
 277         int vpos, hpos;
 278
 279         lockmgr(&rdev->ddev->event_lock, LK_EXCLUSIVE);
 280         work = radeon_crtc->unpin_work;
 281         if (work == NULL ||
 282             (work->fence && !radeon_fence_signaled(work->fence))) {
 283                 lockmgr(&rdev->ddev->event_lock, LK_RELEASE);
 284                 return;
 285         }
 286         /* New pageflip, or just completion of a previous one? */
 287         if (!radeon_crtc->deferred_flip_completion) {
 288                 /* do the flip (mmio) */
 289                 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
 290         } else {
 291                 /* This is just a completion of a flip queued in crtc
 292                  * at last invocation. Make sure we go directly to
 293                  * completion routine.
 294                  */
 295                 update_pending = 0;
 296                 radeon_crtc->deferred_flip_completion = 0;
 297         }
 298
 299         /* Has the pageflip already completed in crtc, or is it certain
 300          * to complete in this vblank?
 301          */
 302         if (update_pending &&
 303             (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
 304                                                                &vpos, &hpos)) &&
 305             ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
 306              (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
 307                 /* crtc didn't flip in this target vblank interval,
 308                  * but flip is pending in crtc. Based on the current
 309                  * scanout position we know that the current frame is
 310                  * (nearly) complete and the flip will (likely)
 311                  * complete before the start of the next frame.
 312                  */
 313                 update_pending = 0;
 314         }
 315         if (update_pending) {
 316                 /* crtc didn't flip in this target vblank interval,
 317                  * but flip is pending in crtc. It will complete it
 318                  * in next vblank interval, so complete the flip at
 319                  * next vblank irq.
 320                  */
 321                 radeon_crtc->deferred_flip_completion = 1;
 322                 lockmgr(&rdev->ddev->event_lock, LK_RELEASE);
 323                 return;
 324         }
 325
 326         /* Pageflip (will be) certainly completed in this vblank. Clean up. */
 327         radeon_crtc->unpin_work = NULL;
 328
 329         /* wakeup userspace */
 330         if (work->event)
 331                 drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
 332
 333         lockmgr(&rdev->ddev->event_lock, LK_RELEASE);
 334
 335         drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
 336         radeon_fence_unref(&work->fence);
 337         radeon_post_page_flip(work->rdev, work->crtc_id);
 338         taskqueue_enqueue(rdev->tq, &work->work);
 339 }
 340
 341 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
 342                                  struct drm_framebuffer *fb,
 343                                  struct drm_pending_vblank_event *event,
 344                                  uint32_t page_flip_flags)
 345 {
 346         struct drm_device *dev = crtc->dev;
 347         struct radeon_device *rdev = dev->dev_private;
 348         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 349         struct radeon_framebuffer *old_radeon_fb;
 350         struct radeon_framebuffer *new_radeon_fb;
 351         struct drm_gem_object *obj;
 352         struct radeon_bo *rbo;
 353         struct radeon_unpin_work *work;
 354         u32 tiling_flags, pitch_pixels;
 355         u64 base;
 356         int r;
 357
 358         work = kmalloc(sizeof *work, M_DRM, M_WAITOK | M_ZERO);
 359         if (work == NULL)
 360                 return -ENOMEM;
 361
 362         work->event = event;
 363         work->rdev = rdev;
 364         work->crtc_id = radeon_crtc->crtc_id;
 365         old_radeon_fb = to_radeon_framebuffer(crtc->fb);
 366         new_radeon_fb = to_radeon_framebuffer(fb);
 367         /* schedule unpin of the old buffer */
 368         obj = old_radeon_fb->obj;
 369         /* take a reference to the old object */
 370         drm_gem_object_reference(obj);
 371         rbo = gem_to_radeon_bo(obj);
 372         work->old_rbo = rbo;
 373         obj = new_radeon_fb->obj;
 374         rbo = gem_to_radeon_bo(obj);
 375
 376         lockmgr(&rbo->tbo.bdev->fence_lock, LK_EXCLUSIVE);
 377         if (rbo->tbo.sync_obj)
 378                 work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
 379         lockmgr(&rbo->tbo.bdev->fence_lock, LK_RELEASE);
 380
 381         TASK_INIT(&work->work, 0, radeon_unpin_work_func, work);
 382
 383         /* We borrow the event spin lock for protecting unpin_work */
 384         lockmgr(&dev->event_lock, LK_EXCLUSIVE);
 385         if (radeon_crtc->unpin_work) {
 386                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 387                 r = -EBUSY;
 388                 goto unlock_free;
 389         }
 390         radeon_crtc->unpin_work = work;
 391         radeon_crtc->deferred_flip_completion = 0;
 392         lockmgr(&dev->event_lock, LK_RELEASE);
 393
 394         /* pin the new buffer */
 395         DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
 396                          work->old_rbo, rbo);
 397
 398         r = radeon_bo_reserve(rbo, false);
 399         if (unlikely(r != 0)) {
 400                 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
 401                 goto pflip_cleanup;
 402         }
 403         /* Only 27 bit offset for legacy CRTC */
 404         r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
 405                                      ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
 406         if (unlikely(r != 0)) {
 407                 radeon_bo_unreserve(rbo);
 408                 r = -EINVAL;
 409                 DRM_ERROR("failed to pin new rbo buffer before flip\n");
 410                 goto pflip_cleanup;
 411         }
 412         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 413         radeon_bo_unreserve(rbo);
 414
 415         if (!ASIC_IS_AVIVO(rdev)) {
 416                 /* crtc offset is from display base addr not FB location */
 417                 base -= radeon_crtc->legacy_display_base_addr;
 418                 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
 419
 420                 if (tiling_flags & RADEON_TILING_MACRO) {
 421                         if (ASIC_IS_R300(rdev)) {
 422                                 base &= ~0x7ff;
 423                         } else {
 424                                 int byteshift = fb->bits_per_pixel >> 4;
 425                                 int tile_addr = (((crtc->y >> 3) * pitch_pixels +  crtc->x) >> (8 - byteshift)) << 11;
 426                                 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
 427                         }
 428                 } else {
 429                         int offset = crtc->y * pitch_pixels + crtc->x;
 430                         switch (fb->bits_per_pixel) {
 431                         case 8:
 432                         default:
 433                                 offset *= 1;
 434                                 break;
 435                         case 15:
 436                         case 16:
 437                                 offset *= 2;
 438                                 break;
 439                         case 24:
 440                                 offset *= 3;
 441                                 break;
 442                         case 32:
 443                                 offset *= 4;
 444                                 break;
 445                         }
 446                         base += offset;
 447                 }
 448                 base &= ~7;
 449         }
 450
 451         lockmgr(&dev->event_lock, LK_EXCLUSIVE);
 452         work->new_crtc_base = base;
 453         lockmgr(&dev->event_lock, LK_RELEASE);
 454
 455         /* update crtc fb */
 456         crtc->fb = fb;
 457
 458         r = drm_vblank_get(dev, radeon_crtc->crtc_id);
 459         if (r) {
 460                 DRM_ERROR("failed to get vblank before flip\n");
 461                 goto pflip_cleanup1;
 462         }
 463
 464         /* set the proper interrupt */
 465         radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
 466
 467         return 0;
 468
 469 pflip_cleanup1:
 470         if (unlikely(radeon_bo_reserve(rbo, false) != 0)) {
 471                 DRM_ERROR("failed to reserve new rbo in error path\n");
 472                 goto pflip_cleanup;
 473         }
 474         if (unlikely(radeon_bo_unpin(rbo) != 0)) {
 475                 DRM_ERROR("failed to unpin new rbo in error path\n");
 476         }
 477         radeon_bo_unreserve(rbo);
 478
 479 pflip_cleanup:
 480         lockmgr(&dev->event_lock, LK_EXCLUSIVE);
 481         radeon_crtc->unpin_work = NULL;
 482 unlock_free:
 483         lockmgr(&dev->event_lock, LK_RELEASE);
 484         drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
 485         radeon_fence_unref(&work->fence);
 486         drm_free(work, M_DRM);
 487
 488         return r;
 489 }
 490
 491 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 492         .cursor_set = radeon_crtc_cursor_set,
 493         .cursor_move = radeon_crtc_cursor_move,
 494         .gamma_set = radeon_crtc_gamma_set,
 495         .set_config = drm_crtc_helper_set_config,
 496         .destroy = radeon_crtc_destroy,
 497         .page_flip = radeon_crtc_page_flip,
 498 };
 499
 500 static void radeon_crtc_init(struct drm_device *dev, int index)
 501 {
 502         struct radeon_device *rdev = dev->dev_private;
 503         struct radeon_crtc *radeon_crtc;
 504         int i;
 505
 506         radeon_crtc = kmalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)),
 507                               M_DRM, M_WAITOK | M_ZERO);
 508         if (radeon_crtc == NULL)
 509                 return;
 510
 511         drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
 512
 513         drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
 514         radeon_crtc->crtc_id = index;
 515         rdev->mode_info.crtcs[index] = radeon_crtc;
 516
 517 #if 0
 518         radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 519         radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 520         radeon_crtc->mode_set.num_connectors = 0;
 521 #endif
 522
 523         for (i = 0; i < 256; i++) {
 524                 radeon_crtc->lut_r[i] = i << 2;
 525                 radeon_crtc->lut_g[i] = i << 2;
 526                 radeon_crtc->lut_b[i] = i << 2;
 527         }
 528
 529         if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
 530                 radeon_atombios_init_crtc(dev, radeon_crtc);
 531         else
 532                 radeon_legacy_init_crtc(dev, radeon_crtc);
 533 }
 534
 535 static const char *encoder_names[37] = {
 536         "NONE",
 537         "INTERNAL_LVDS",
 538         "INTERNAL_TMDS1",
 539         "INTERNAL_TMDS2",
 540         "INTERNAL_DAC1",
 541         "INTERNAL_DAC2",
 542         "INTERNAL_SDVOA",
 543         "INTERNAL_SDVOB",
 544         "SI170B",
 545         "CH7303",
 546         "CH7301",
 547         "INTERNAL_DVO1",
 548         "EXTERNAL_SDVOA",
 549         "EXTERNAL_SDVOB",
 550         "TITFP513",
 551         "INTERNAL_LVTM1",
 552         "VT1623",
 553         "HDMI_SI1930",
 554         "HDMI_INTERNAL",
 555         "INTERNAL_KLDSCP_TMDS1",
 556         "INTERNAL_KLDSCP_DVO1",
 557         "INTERNAL_KLDSCP_DAC1",
 558         "INTERNAL_KLDSCP_DAC2",
 559         "SI178",
 560         "MVPU_FPGA",
 561         "INTERNAL_DDI",
 562         "VT1625",
 563         "HDMI_SI1932",
 564         "DP_AN9801",
 565         "DP_DP501",
 566         "INTERNAL_UNIPHY",
 567         "INTERNAL_KLDSCP_LVTMA",
 568         "INTERNAL_UNIPHY1",
 569         "INTERNAL_UNIPHY2",
 570         "NUTMEG",
 571         "TRAVIS",
 572         "INTERNAL_VCE"
 573 };
 574
 575 static const char *hpd_names[6] = {
 576         "HPD1",
 577         "HPD2",
 578         "HPD3",
 579         "HPD4",
 580         "HPD5",
 581         "HPD6",
 582 };
 583
 584 static void radeon_print_display_setup(struct drm_device *dev)
 585 {
 586         struct drm_connector *connector;
 587         struct radeon_connector *radeon_connector;
 588         struct drm_encoder *encoder;
 589         struct radeon_encoder *radeon_encoder;
 590         uint32_t devices;
 591         int i = 0;
 592
 593         DRM_INFO("Radeon Display Connectors\n");
 594         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 595                 radeon_connector = to_radeon_connector(connector);
 596                 DRM_INFO("Connector %d:\n", i);
 597                 DRM_INFO("  %s\n", drm_get_connector_name(connector));
 598                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 599                         DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
 600                 if (radeon_connector->ddc_bus) {
 601                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 602                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
 603                                  radeon_connector->ddc_bus->rec.mask_data_reg,
 604                                  radeon_connector->ddc_bus->rec.a_clk_reg,
 605                                  radeon_connector->ddc_bus->rec.a_data_reg,
 606                                  radeon_connector->ddc_bus->rec.en_clk_reg,
 607                                  radeon_connector->ddc_bus->rec.en_data_reg,
 608                                  radeon_connector->ddc_bus->rec.y_clk_reg,
 609                                  radeon_connector->ddc_bus->rec.y_data_reg);
 610                         if (radeon_connector->router.ddc_valid)
 611                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 612                                          radeon_connector->router.ddc_mux_control_pin,
 613                                          radeon_connector->router.ddc_mux_state);
 614                         if (radeon_connector->router.cd_valid)
 615                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 616                                          radeon_connector->router.cd_mux_control_pin,
 617                                          radeon_connector->router.cd_mux_state);
 618                 } else {
 619                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 620                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 621                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 622                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 623                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 624                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 625                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 626                 }
 627                 DRM_INFO("  Encoders:\n");
 628                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 629                         radeon_encoder = to_radeon_encoder(encoder);
 630                         devices = radeon_encoder->devices & radeon_connector->devices;
 631                         if (devices) {
 632                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 633                                         DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 634                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 635                                         DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 636                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 637                                         DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 638                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 639                                         DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 640                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 641                                         DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 642                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 643                                         DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
 644                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 645                                         DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
 646                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 647                                         DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
 648                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 649                                         DRM_INFO("    DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
 650                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 651                                         DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 652                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 653                                         DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
 654                         }
 655                 }
 656                 i++;
 657         }
 658 }
 659
 660 static bool radeon_setup_enc_conn(struct drm_device *dev)
 661 {
 662         struct radeon_device *rdev = dev->dev_private;
 663         bool ret = false;
 664
 665         if (rdev->bios) {
 666                 if (rdev->is_atom_bios) {
 667                         ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
 668                         if (ret == false)
 669                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
 670                 } else {
 671                         ret = radeon_get_legacy_connector_info_from_bios(dev);
 672                         if (ret == false)
 673                                 ret = radeon_get_legacy_connector_info_from_table(dev);
 674                 }
 675         } else {
 676                 if (!ASIC_IS_AVIVO(rdev))
 677                         ret = radeon_get_legacy_connector_info_from_table(dev);
 678         }
 679         if (ret) {
 680                 radeon_setup_encoder_clones(dev);
 681                 radeon_print_display_setup(dev);
 682         }
 683
 684         return ret;
 685 }
 686
 687 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
 688 {
 689         struct drm_device *dev = radeon_connector->base.dev;
 690         struct radeon_device *rdev = dev->dev_private;
 691         int ret = 0;
 692
 693         /* on hw with routers, select right port */
 694         if (radeon_connector->router.ddc_valid)
 695                 radeon_router_select_ddc_port(radeon_connector);
 696
 697         if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
 698             ENCODER_OBJECT_ID_NONE) {
 699                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 700
 701                 if (dig->dp_i2c_bus)
 702                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 703                                                               dig->dp_i2c_bus->adapter);
 704         } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 705                    (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
 706                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 707
 708                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 709                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
 710                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 711                                                               dig->dp_i2c_bus->adapter);
 712                 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
 713                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 714                                                               radeon_connector->ddc_bus->adapter);
 715         } else {
 716                 if (radeon_connector->ddc_bus && !radeon_connector->edid)
 717                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 718                                                               radeon_connector->ddc_bus->adapter);
 719         }
 720
 721         if (!radeon_connector->edid) {
 722                 if (rdev->is_atom_bios) {
 723                         /* some laptops provide a hardcoded edid in rom for LCDs */
 724                         if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
 725                              (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
 726                                 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 727                 } else
 728                         /* some servers provide a hardcoded edid in rom for KVMs */
 729                         radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 730         }
 731         if (radeon_connector->edid) {
 732                 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
 733                 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
 734                 return ret;
 735         }
 736         drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
 737         return 0;
 738 }
 739
 740 /* avivo */
 741 static void avivo_get_fb_div(struct radeon_pll *pll,
 742                              u32 target_clock,
 743                              u32 post_div,
 744                              u32 ref_div,
 745                              u32 *fb_div,
 746                              u32 *frac_fb_div)
 747 {
 748         u32 tmp = post_div * ref_div;
 749
 750         tmp *= target_clock;
 751         *fb_div = tmp / pll->reference_freq;
 752         *frac_fb_div = tmp % pll->reference_freq;
 753
 754         if (*fb_div > pll->max_feedback_div)
 755                 *fb_div = pll->max_feedback_div;
 756         else if (*fb_div < pll->min_feedback_div)
 757                 *fb_div = pll->min_feedback_div;
 758 }
 759
 760 static u32 avivo_get_post_div(struct radeon_pll *pll,
 761                               u32 target_clock)
 762 {
 763         u32 vco, post_div, tmp;
 764
 765         if (pll->flags & RADEON_PLL_USE_POST_DIV)
 766                 return pll->post_div;
 767
 768         if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
 769                 if (pll->flags & RADEON_PLL_IS_LCD)
 770                         vco = pll->lcd_pll_out_min;
 771                 else
 772                         vco = pll->pll_out_min;
 773         } else {
 774                 if (pll->flags & RADEON_PLL_IS_LCD)
 775                         vco = pll->lcd_pll_out_max;
 776                 else
 777                         vco = pll->pll_out_max;
 778         }
 779
 780         post_div = vco / target_clock;
 781         tmp = vco % target_clock;
 782
 783         if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
 784                 if (tmp)
 785                         post_div++;
 786         } else {
 787                 if (!tmp)
 788                         post_div--;
 789         }
 790
 791         if (post_div > pll->max_post_div)
 792                 post_div = pll->max_post_div;
 793         else if (post_div < pll->min_post_div)
 794                 post_div = pll->min_post_div;
 795
 796         return post_div;
 797 }
 798
 799 #define MAX_TOLERANCE 10
 800
 801 void radeon_compute_pll_avivo(struct radeon_pll *pll,
 802                               u32 freq,
 803                               u32 *dot_clock_p,
 804                               u32 *fb_div_p,
 805                               u32 *frac_fb_div_p,
 806                               u32 *ref_div_p,
 807                               u32 *post_div_p)
 808 {
 809         u32 target_clock = freq / 10;
 810         u32 post_div = avivo_get_post_div(pll, target_clock);
 811         u32 ref_div = pll->min_ref_div;
 812         u32 fb_div = 0, frac_fb_div = 0, tmp;
 813
 814         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 815                 ref_div = pll->reference_div;
 816
 817         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 818                 avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
 819                 frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
 820                 if (frac_fb_div >= 5) {
 821                         frac_fb_div -= 5;
 822                         frac_fb_div = frac_fb_div / 10;
 823                         frac_fb_div++;
 824                 }
 825                 if (frac_fb_div >= 10) {
 826                         fb_div++;
 827                         frac_fb_div = 0;
 828                 }
 829         } else {
 830                 while (ref_div <= pll->max_ref_div) {
 831                         avivo_get_fb_div(pll, target_clock, post_div, ref_div,
 832                                          &fb_div, &frac_fb_div);
 833                         if (frac_fb_div >= (pll->reference_freq / 2))
 834                                 fb_div++;
 835                         frac_fb_div = 0;
 836                         tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
 837                         tmp = (tmp * 10000) / target_clock;
 838
 839                         if (tmp > (10000 + MAX_TOLERANCE))
 840                                 ref_div++;
 841                         else if (tmp >= (10000 - MAX_TOLERANCE))
 842                                 break;
 843                         else
 844                                 ref_div++;
 845                 }
 846         }
 847
 848         *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
 849                 (ref_div * post_div * 10);
 850         *fb_div_p = fb_div;
 851         *frac_fb_div_p = frac_fb_div;
 852         *ref_div_p = ref_div;
 853         *post_div_p = post_div;
 854         DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
 855                       *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
 856 }
 857
 858 /* pre-avivo */
 859 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
 860 {
 861         uint64_t mod;
 862
 863         n += d / 2;
 864
 865         mod = do_div(n, d);
 866         return n;
 867 }
 868
 869 void radeon_compute_pll_legacy(struct radeon_pll *pll,
 870                                uint64_t freq,
 871                                uint32_t *dot_clock_p,
 872                                uint32_t *fb_div_p,
 873                                uint32_t *frac_fb_div_p,
 874                                uint32_t *ref_div_p,
 875                                uint32_t *post_div_p)
 876 {
 877         uint32_t min_ref_div = pll->min_ref_div;
 878         uint32_t max_ref_div = pll->max_ref_div;
 879         uint32_t min_post_div = pll->min_post_div;
 880         uint32_t max_post_div = pll->max_post_div;
 881         uint32_t min_fractional_feed_div = 0;
 882         uint32_t max_fractional_feed_div = 0;
 883         uint32_t best_vco = pll->best_vco;
 884         uint32_t best_post_div = 1;
 885         uint32_t best_ref_div = 1;
 886         uint32_t best_feedback_div = 1;
 887         uint32_t best_frac_feedback_div = 0;
 888         uint32_t best_freq = -1;
 889         uint32_t best_error = 0xffffffff;
 890         uint32_t best_vco_diff = 1;
 891         uint32_t post_div;
 892         u32 pll_out_min, pll_out_max;
 893
 894         DRM_DEBUG_KMS("PLL freq %ju %u %u\n", (uintmax_t)freq, pll->min_ref_div, pll->max_ref_div);
 895         freq = freq * 1000;
 896
 897         if (pll->flags & RADEON_PLL_IS_LCD) {
 898                 pll_out_min = pll->lcd_pll_out_min;
 899                 pll_out_max = pll->lcd_pll_out_max;
 900         } else {
 901                 pll_out_min = pll->pll_out_min;
 902                 pll_out_max = pll->pll_out_max;
 903         }
 904
 905         if (pll_out_min > 64800)
 906                 pll_out_min = 64800;
 907
 908         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 909                 min_ref_div = max_ref_div = pll->reference_div;
 910         else {
 911                 while (min_ref_div < max_ref_div-1) {
 912                         uint32_t mid = (min_ref_div + max_ref_div) / 2;
 913                         uint32_t pll_in = pll->reference_freq / mid;
 914                         if (pll_in < pll->pll_in_min)
 915                                 max_ref_div = mid;
 916                         else if (pll_in > pll->pll_in_max)
 917                                 min_ref_div = mid;
 918                         else
 919                                 break;
 920                 }
 921         }
 922
 923         if (pll->flags & RADEON_PLL_USE_POST_DIV)
 924                 min_post_div = max_post_div = pll->post_div;
 925
 926         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 927                 min_fractional_feed_div = pll->min_frac_feedback_div;
 928                 max_fractional_feed_div = pll->max_frac_feedback_div;
 929         }
 930
 931         for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
 932                 uint32_t ref_div;
 933
 934                 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
 935                         continue;
 936
 937                 /* legacy radeons only have a few post_divs */
 938                 if (pll->flags & RADEON_PLL_LEGACY) {
 939                         if ((post_div == 5) ||
 940                             (post_div == 7) ||
 941                             (post_div == 9) ||
 942                             (post_div == 10) ||
 943                             (post_div == 11) ||
 944                             (post_div == 13) ||
 945                             (post_div == 14) ||
 946                             (post_div == 15))
 947                                 continue;
 948                 }
 949
 950                 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
 951                         uint32_t feedback_div, current_freq = 0, error, vco_diff;
 952                         uint32_t pll_in = pll->reference_freq / ref_div;
 953                         uint32_t min_feed_div = pll->min_feedback_div;
 954                         uint32_t max_feed_div = pll->max_feedback_div + 1;
 955
 956                         if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
 957                                 continue;
 958
 959                         while (min_feed_div < max_feed_div) {
 960                                 uint32_t vco;
 961                                 uint32_t min_frac_feed_div = min_fractional_feed_div;
 962                                 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
 963                                 uint32_t frac_feedback_div;
 964                                 uint64_t tmp;
 965
 966                                 feedback_div = (min_feed_div + max_feed_div) / 2;
 967
 968                                 tmp = (uint64_t)pll->reference_freq * feedback_div;
 969                                 vco = radeon_div(tmp, ref_div);
 970
 971                                 if (vco < pll_out_min) {
 972                                         min_feed_div = feedback_div + 1;
 973                                         continue;
 974                                 } else if (vco > pll_out_max) {
 975                                         max_feed_div = feedback_div;
 976                                         continue;
 977                                 }
 978
 979                                 while (min_frac_feed_div < max_frac_feed_div) {
 980                                         frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
 981                                         tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
 982                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
 983                                         current_freq = radeon_div(tmp, ref_div * post_div);
 984
 985                                         if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
 986                                                 if (freq < current_freq)
 987                                                         error = 0xffffffff;
 988                                                 else
 989                                                         error = freq - current_freq;
 990                                         } else
 991                                                 error = abs(current_freq - freq);
 992                                         vco_diff = abs(vco - best_vco);
 993
 994                                         if ((best_vco == 0 && error < best_error) ||
 995                                             (best_vco != 0 &&
 996                                              ((best_error > 100 && error < best_error - 100) ||
 997                                               (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
 998                                                 best_post_div = post_div;
 999                                                 best_ref_div = ref_div;
1000                                                 best_feedback_div = feedback_div;
1001                                                 best_frac_feedback_div = frac_feedback_div;
1002                                                 best_freq = current_freq;
1003                                                 best_error = error;
1004                                                 best_vco_diff = vco_diff;
1005                                         } else if (current_freq == freq) {
1006                                                 if (best_freq == -1) {
1007                                                         best_post_div = post_div;
1008                                                         best_ref_div = ref_div;
1009                                                         best_feedback_div = feedback_div;
1010                                                         best_frac_feedback_div = frac_feedback_div;
1011                                                         best_freq = current_freq;
1012                                                         best_error = error;
1013                                                         best_vco_diff = vco_diff;
1014                                                 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1015                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1016                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1017                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1018                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1019                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1020                                                         best_post_div = post_div;
1021                                                         best_ref_div = ref_div;
1022                                                         best_feedback_div = feedback_div;
1023                                                         best_frac_feedback_div = frac_feedback_div;
1024                                                         best_freq = current_freq;
1025                                                         best_error = error;
1026                                                         best_vco_diff = vco_diff;
1027                                                 }
1028                                         }
1029                                         if (current_freq < freq)
1030                                                 min_frac_feed_div = frac_feedback_div + 1;
1031                                         else
1032                                                 max_frac_feed_div = frac_feedback_div;
1033                                 }
1034                                 if (current_freq < freq)
1035                                         min_feed_div = feedback_div + 1;
1036                                 else
1037                                         max_feed_div = feedback_div;
1038                         }
1039                 }
1040         }
1041
1042         *dot_clock_p = best_freq / 10000;
1043         *fb_div_p = best_feedback_div;
1044         *frac_fb_div_p = best_frac_feedback_div;
1045         *ref_div_p = best_ref_div;
1046         *post_div_p = best_post_div;
1047         DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1048                       (long long)freq,
1049                       best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1050                       best_ref_div, best_post_div);
1051
1052 }
1053
1054 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1055 {
1056         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1057
1058         if (radeon_fb->obj) {
1059                 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1060         }
1061         drm_framebuffer_cleanup(fb);
1062         drm_free(radeon_fb, M_DRM);
1063 }
1064
1065 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1066                                                   struct drm_file *file_priv,
1067                                                   unsigned int *handle)
1068 {
1069         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1070
1071         return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1072 }
1073
1074 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1075         .destroy = radeon_user_framebuffer_destroy,
1076         .create_handle = radeon_user_framebuffer_create_handle,
1077 };
1078
1079 int
1080 radeon_framebuffer_init(struct drm_device *dev,
1081                         struct radeon_framebuffer *rfb,
1082                         struct drm_mode_fb_cmd2 *mode_cmd,
1083                         struct drm_gem_object *obj)
1084 {
1085         int ret;
1086         rfb->obj = obj;
1087         drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1088         ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1089         if (ret) {
1090                 rfb->obj = NULL;
1091                 return ret;
1092         }
1093         return 0;
1094 }
1095
1096 static struct drm_framebuffer *
1097 radeon_user_framebuffer_create(struct drm_device *dev,
1098                                struct drm_file *file_priv,
1099                                struct drm_mode_fb_cmd2 *mode_cmd)
1100 {
1101         struct drm_gem_object *obj;
1102         struct radeon_framebuffer *radeon_fb;
1103         int ret;
1104
1105         obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
1106         if (obj ==  NULL) {
1107                 dev_err(dev->dev, "No GEM object associated to handle 0x%08X, "
1108                         "can't create framebuffer\n", mode_cmd->handles[0]);
1109                 return ERR_PTR(-ENOENT);
1110         }
1111
1112         radeon_fb = kmalloc(sizeof(*radeon_fb), M_DRM,
1113                             M_WAITOK | M_ZERO);
1114         if (radeon_fb == NULL) {
1115                 drm_gem_object_unreference_unlocked(obj);
1116                 return ERR_PTR(-ENOMEM);
1117         }
1118
1119         ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1120         if (ret) {
1121                 kfree(radeon_fb);
1122                 drm_gem_object_unreference_unlocked(obj);
1123                 return ERR_PTR(ret);
1124         }
1125
1126         return &radeon_fb->base;
1127 }
1128
1129 static void radeon_output_poll_changed(struct drm_device *dev)
1130 {
1131         struct radeon_device *rdev = dev->dev_private;
1132         radeon_fb_output_poll_changed(rdev);
1133 }
1134
1135 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1136         .fb_create = radeon_user_framebuffer_create,
1137         .output_poll_changed = radeon_output_poll_changed
1138 };
1139
1140 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1141 {       { 0, "driver" },
1142         { 1, "bios" },
1143 };
1144
1145 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1146 {       { TV_STD_NTSC, "ntsc" },
1147         { TV_STD_PAL, "pal" },
1148         { TV_STD_PAL_M, "pal-m" },
1149         { TV_STD_PAL_60, "pal-60" },
1150         { TV_STD_NTSC_J, "ntsc-j" },
1151         { TV_STD_SCART_PAL, "scart-pal" },
1152         { TV_STD_PAL_CN, "pal-cn" },
1153         { TV_STD_SECAM, "secam" },
1154 };
1155
1156 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1157 {       { UNDERSCAN_OFF, "off" },
1158         { UNDERSCAN_ON, "on" },
1159         { UNDERSCAN_AUTO, "auto" },
1160 };
1161
1162 static int radeon_modeset_create_props(struct radeon_device *rdev)
1163 {
1164         int sz;
1165
1166         if (rdev->is_atom_bios) {
1167                 rdev->mode_info.coherent_mode_property =
1168                         drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1169                 if (!rdev->mode_info.coherent_mode_property)
1170                         return -ENOMEM;
1171         }
1172
1173         if (!ASIC_IS_AVIVO(rdev)) {
1174                 sz = DRM_ARRAY_SIZE(radeon_tmds_pll_enum_list);
1175                 rdev->mode_info.tmds_pll_property =
1176                         drm_property_create_enum(rdev->ddev, 0,
1177                                             "tmds_pll",
1178                                             radeon_tmds_pll_enum_list, sz);
1179         }
1180
1181         rdev->mode_info.load_detect_property =
1182                 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1183         if (!rdev->mode_info.load_detect_property)
1184                 return -ENOMEM;
1185
1186         drm_mode_create_scaling_mode_property(rdev->ddev);
1187
1188         sz = DRM_ARRAY_SIZE(radeon_tv_std_enum_list);
1189         rdev->mode_info.tv_std_property =
1190                 drm_property_create_enum(rdev->ddev, 0,
1191                                     "tv standard",
1192                                     radeon_tv_std_enum_list, sz);
1193
1194         sz = DRM_ARRAY_SIZE(radeon_underscan_enum_list);
1195         rdev->mode_info.underscan_property =
1196                 drm_property_create_enum(rdev->ddev, 0,
1197                                     "underscan",
1198                                     radeon_underscan_enum_list, sz);
1199
1200         rdev->mode_info.underscan_hborder_property =
1201                 drm_property_create_range(rdev->ddev, 0,
1202                                         "underscan hborder", 0, 128);
1203         if (!rdev->mode_info.underscan_hborder_property)
1204                 return -ENOMEM;
1205
1206         rdev->mode_info.underscan_vborder_property =
1207                 drm_property_create_range(rdev->ddev, 0,
1208                                         "underscan vborder", 0, 128);
1209         if (!rdev->mode_info.underscan_vborder_property)
1210                 return -ENOMEM;
1211
1212         return 0;
1213 }
1214
1215 void radeon_update_display_priority(struct radeon_device *rdev)
1216 {
1217         /* adjustment options for the display watermarks */
1218         if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1219                 /* set display priority to high for r3xx, rv515 chips
1220                  * this avoids flickering due to underflow to the
1221                  * display controllers during heavy acceleration.
1222                  * Don't force high on rs4xx igp chips as it seems to
1223                  * affect the sound card.  See kernel bug 15982.
1224                  */
1225                 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1226                     !(rdev->flags & RADEON_IS_IGP))
1227                         rdev->disp_priority = 2;
1228                 else
1229                         rdev->disp_priority = 0;
1230         } else
1231                 rdev->disp_priority = radeon_disp_priority;
1232
1233 }
1234
1235 /*
1236  * Allocate hdmi structs and determine register offsets
1237  */
1238 static void radeon_afmt_init(struct radeon_device *rdev)
1239 {
1240         int i;
1241
1242         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1243                 rdev->mode_info.afmt[i] = NULL;
1244
1245         if (ASIC_IS_DCE6(rdev)) {
1246                 /* todo */
1247         } else if (ASIC_IS_DCE4(rdev)) {
1248                 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1249                 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1250                 rdev->mode_info.afmt[0] = kmalloc(sizeof(struct radeon_afmt),
1251                                                   M_DRM,
1252                                                   M_WAITOK | M_ZERO);
1253                 if (rdev->mode_info.afmt[0]) {
1254                         rdev->mode_info.afmt[0]->offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1255                         rdev->mode_info.afmt[0]->id = 0;
1256                 }
1257                 rdev->mode_info.afmt[1] = kmalloc(sizeof(struct radeon_afmt),
1258                                                   M_DRM,
1259                                                   M_WAITOK | M_ZERO);
1260                 if (rdev->mode_info.afmt[1]) {
1261                         rdev->mode_info.afmt[1]->offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1262                         rdev->mode_info.afmt[1]->id = 1;
1263                 }
1264                 if (!ASIC_IS_DCE41(rdev)) {
1265                         rdev->mode_info.afmt[2] = kmalloc(sizeof(struct radeon_afmt),
1266                                                           M_DRM,
1267                                                           M_WAITOK | M_ZERO);
1268                         if (rdev->mode_info.afmt[2]) {
1269                                 rdev->mode_info.afmt[2]->offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1270                                 rdev->mode_info.afmt[2]->id = 2;
1271                         }
1272                         rdev->mode_info.afmt[3] = kmalloc(sizeof(struct radeon_afmt),
1273                                                           M_DRM,
1274                                                           M_WAITOK | M_ZERO);
1275                         if (rdev->mode_info.afmt[3]) {
1276                                 rdev->mode_info.afmt[3]->offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1277                                 rdev->mode_info.afmt[3]->id = 3;
1278                         }
1279                         rdev->mode_info.afmt[4] = kmalloc(sizeof(struct radeon_afmt),
1280                                                           M_DRM,
1281                                                           M_WAITOK | M_ZERO);
1282                         if (rdev->mode_info.afmt[4]) {
1283                                 rdev->mode_info.afmt[4]->offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1284                                 rdev->mode_info.afmt[4]->id = 4;
1285                         }
1286                         rdev->mode_info.afmt[5] = kmalloc(sizeof(struct radeon_afmt),
1287                                                           M_DRM,
1288                                                           M_WAITOK | M_ZERO);
1289                         if (rdev->mode_info.afmt[5]) {
1290                                 rdev->mode_info.afmt[5]->offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1291                                 rdev->mode_info.afmt[5]->id = 5;
1292                         }
1293                 }
1294         } else if (ASIC_IS_DCE3(rdev)) {
1295                 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1296                 rdev->mode_info.afmt[0] = kmalloc(sizeof(struct radeon_afmt),
1297                                                   M_DRM,
1298                                                   M_WAITOK | M_ZERO);
1299                 if (rdev->mode_info.afmt[0]) {
1300                         rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1301                         rdev->mode_info.afmt[0]->id = 0;
1302                 }
1303                 rdev->mode_info.afmt[1] = kmalloc(sizeof(struct radeon_afmt),
1304                                                   M_DRM,
1305                                                   M_WAITOK | M_ZERO);
1306                 if (rdev->mode_info.afmt[1]) {
1307                         rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1308                         rdev->mode_info.afmt[1]->id = 1;
1309                 }
1310         } else if (ASIC_IS_DCE2(rdev)) {
1311                 /* DCE2 has at least 1 routable audio block */
1312                 rdev->mode_info.afmt[0] = kmalloc(sizeof(struct radeon_afmt),
1313                                                   M_DRM,
1314                                                   M_WAITOK | M_ZERO);
1315                 if (rdev->mode_info.afmt[0]) {
1316                         rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1317                         rdev->mode_info.afmt[0]->id = 0;
1318                 }
1319                 /* r6xx has 2 routable audio blocks */
1320                 if (rdev->family >= CHIP_R600) {
1321                         rdev->mode_info.afmt[1] = kmalloc(sizeof(struct radeon_afmt),
1322                                                           M_DRM,
1323                                                           M_WAITOK | M_ZERO);
1324                         if (rdev->mode_info.afmt[1]) {
1325                                 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1326                                 rdev->mode_info.afmt[1]->id = 1;
1327                         }
1328                 }
1329         }
1330 }
1331
1332 static void radeon_afmt_fini(struct radeon_device *rdev)
1333 {
1334         int i;
1335
1336         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1337                 drm_free(rdev->mode_info.afmt[i], M_DRM);
1338                 rdev->mode_info.afmt[i] = NULL;
1339         }
1340 }
1341
1342 int radeon_modeset_init(struct radeon_device *rdev)
1343 {
1344         int i;
1345         int ret;
1346
1347         drm_mode_config_init(rdev->ddev);
1348         rdev->mode_info.mode_config_initialized = true;
1349
1350         rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1351
1352         if (ASIC_IS_DCE5(rdev)) {
1353                 rdev->ddev->mode_config.max_width = 16384;
1354                 rdev->ddev->mode_config.max_height = 16384;
1355         } else if (ASIC_IS_AVIVO(rdev)) {
1356                 rdev->ddev->mode_config.max_width = 8192;
1357                 rdev->ddev->mode_config.max_height = 8192;
1358         } else {
1359                 rdev->ddev->mode_config.max_width = 4096;
1360                 rdev->ddev->mode_config.max_height = 4096;
1361         }
1362
1363         rdev->ddev->mode_config.preferred_depth = 24;
1364         rdev->ddev->mode_config.prefer_shadow = 1;
1365
1366         rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1367
1368         ret = radeon_modeset_create_props(rdev);
1369         if (ret) {
1370                 return ret;
1371         }
1372
1373         /* init i2c buses */
1374         radeon_i2c_init(rdev);
1375
1376         /* check combios for a valid hardcoded EDID - Sun servers */
1377         if (!rdev->is_atom_bios) {
1378                 /* check for hardcoded EDID in BIOS */
1379                 radeon_combios_check_hardcoded_edid(rdev);
1380         }
1381
1382         /* allocate crtcs */
1383         for (i = 0; i < rdev->num_crtc; i++) {
1384                 radeon_crtc_init(rdev->ddev, i);
1385         }
1386
1387         /* okay we should have all the bios connectors */
1388         ret = radeon_setup_enc_conn(rdev->ddev);
1389         if (!ret) {
1390                 return ret;
1391         }
1392
1393         /* init dig PHYs, disp eng pll */
1394         if (rdev->is_atom_bios) {
1395                 radeon_atom_encoder_init(rdev);
1396                 radeon_atom_disp_eng_pll_init(rdev);
1397         }
1398
1399         /* initialize hpd */
1400         radeon_hpd_init(rdev);
1401
1402         /* setup afmt */
1403         radeon_afmt_init(rdev);
1404
1405         /* Initialize power management */
1406         radeon_pm_init(rdev);
1407
1408         radeon_fbdev_init(rdev);
1409         drm_kms_helper_poll_init(rdev->ddev);
1410
1411         return 0;
1412 }
1413
1414 void radeon_modeset_fini(struct radeon_device *rdev)
1415 {
1416         radeon_fbdev_fini(rdev);
1417         drm_free(rdev->mode_info.bios_hardcoded_edid, M_DRM);
1418         radeon_pm_fini(rdev);
1419
1420         if (rdev->mode_info.mode_config_initialized) {
1421                 radeon_afmt_fini(rdev);
1422                 drm_kms_helper_poll_fini(rdev->ddev);
1423                 radeon_hpd_fini(rdev);
1424                 DRM_UNLOCK(rdev->ddev); /* Work around lock recursion. dumbbell@ */
1425                 drm_mode_config_cleanup(rdev->ddev);
1426                 DRM_LOCK(rdev->ddev);
1427                 rdev->mode_info.mode_config_initialized = false;
1428         }
1429         /* free i2c buses */
1430         radeon_i2c_fini(rdev);
1431 }
1432
1433 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1434 {
1435         /* try and guess if this is a tv or a monitor */
1436         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1437             (mode->vdisplay == 576) || /* 576p */
1438             (mode->vdisplay == 720) || /* 720p */
1439             (mode->vdisplay == 1080)) /* 1080p */
1440                 return true;
1441         else
1442                 return false;
1443 }
1444
1445 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1446                                 const struct drm_display_mode *mode,
1447                                 struct drm_display_mode *adjusted_mode)
1448 {
1449         struct drm_device *dev = crtc->dev;
1450         struct radeon_device *rdev = dev->dev_private;
1451         struct drm_encoder *encoder;
1452         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1453         struct radeon_encoder *radeon_encoder;
1454         struct drm_connector *connector;
1455         struct radeon_connector *radeon_connector;
1456         bool first = true;
1457         u32 src_v = 1, dst_v = 1;
1458         u32 src_h = 1, dst_h = 1;
1459
1460         radeon_crtc->h_border = 0;
1461         radeon_crtc->v_border = 0;
1462
1463         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1464                 if (encoder->crtc != crtc)
1465                         continue;
1466                 radeon_encoder = to_radeon_encoder(encoder);
1467                 connector = radeon_get_connector_for_encoder(encoder);
1468                 radeon_connector = to_radeon_connector(connector);
1469
1470                 if (first) {
1471                         /* set scaling */
1472                         if (radeon_encoder->rmx_type == RMX_OFF)
1473                                 radeon_crtc->rmx_type = RMX_OFF;
1474                         else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1475                                  mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1476                                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1477                         else
1478                                 radeon_crtc->rmx_type = RMX_OFF;
1479                         /* copy native mode */
1480                         memcpy(&radeon_crtc->native_mode,
1481                                &radeon_encoder->native_mode,
1482                                 sizeof(struct drm_display_mode));
1483                         src_v = crtc->mode.vdisplay;
1484                         dst_v = radeon_crtc->native_mode.vdisplay;
1485                         src_h = crtc->mode.hdisplay;
1486                         dst_h = radeon_crtc->native_mode.hdisplay;
1487
1488                         /* fix up for overscan on hdmi */
1489                         if (ASIC_IS_AVIVO(rdev) &&
1490                             (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1491                             ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1492                              ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1493                               drm_detect_hdmi_monitor(radeon_connector->edid) &&
1494                               is_hdtv_mode(mode)))) {
1495                                 if (radeon_encoder->underscan_hborder != 0)
1496                                         radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1497                                 else
1498                                         radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1499                                 if (radeon_encoder->underscan_vborder != 0)
1500                                         radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1501                                 else
1502                                         radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1503                                 radeon_crtc->rmx_type = RMX_FULL;
1504                                 src_v = crtc->mode.vdisplay;
1505                                 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1506                                 src_h = crtc->mode.hdisplay;
1507                                 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1508                         }
1509                         first = false;
1510                 } else {
1511                         if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1512                                 /* WARNING: Right now this can't happen but
1513                                  * in the future we need to check that scaling
1514                                  * are consistent across different encoder
1515                                  * (ie all encoder can work with the same
1516                                  *  scaling).
1517                                  */
1518                                 DRM_ERROR("Scaling not consistent across encoder.\n");
1519                                 return false;
1520                         }
1521                 }
1522         }
1523         if (radeon_crtc->rmx_type != RMX_OFF) {
1524                 fixed20_12 a, b;
1525                 a.full = dfixed_const(src_v);
1526                 b.full = dfixed_const(dst_v);
1527                 radeon_crtc->vsc.full = dfixed_div(a, b);
1528                 a.full = dfixed_const(src_h);
1529                 b.full = dfixed_const(dst_h);
1530                 radeon_crtc->hsc.full = dfixed_div(a, b);
1531         } else {
1532                 radeon_crtc->vsc.full = dfixed_const(1);
1533                 radeon_crtc->hsc.full = dfixed_const(1);
1534         }
1535         return true;
1536 }
1537
1538 /*
1539  * Retrieve current video scanout position of crtc on a given gpu.
1540  *
1541  * \param dev Device to query.
1542  * \param crtc Crtc to query.
1543  * \param *vpos Location where vertical scanout position should be stored.
1544  * \param *hpos Location where horizontal scanout position should go.
1545  *
1546  * Returns vpos as a positive number while in active scanout area.
1547  * Returns vpos as a negative number inside vblank, counting the number
1548  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1549  * until start of active scanout / end of vblank."
1550  *
1551  * \return Flags, or'ed together as follows:
1552  *
1553  * DRM_SCANOUTPOS_VALID = Query successful.
1554  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1555  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1556  * this flag means that returned position may be offset by a constant but
1557  * unknown small number of scanlines wrt. real scanout position.
1558  *
1559  */
1560 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos)
1561 {
1562         u32 stat_crtc = 0, vbl = 0, position = 0;
1563         int vbl_start, vbl_end, vtotal, ret = 0;
1564         bool in_vbl = true;
1565
1566         struct radeon_device *rdev = dev->dev_private;
1567
1568         if (ASIC_IS_DCE4(rdev)) {
1569                 if (crtc == 0) {
1570                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1571                                      EVERGREEN_CRTC0_REGISTER_OFFSET);
1572                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1573                                           EVERGREEN_CRTC0_REGISTER_OFFSET);
1574                         ret |= DRM_SCANOUTPOS_VALID;
1575                 }
1576                 if (crtc == 1) {
1577                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1578                                      EVERGREEN_CRTC1_REGISTER_OFFSET);
1579                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1580                                           EVERGREEN_CRTC1_REGISTER_OFFSET);
1581                         ret |= DRM_SCANOUTPOS_VALID;
1582                 }
1583                 if (crtc == 2) {
1584                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1585                                      EVERGREEN_CRTC2_REGISTER_OFFSET);
1586                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1587                                           EVERGREEN_CRTC2_REGISTER_OFFSET);
1588                         ret |= DRM_SCANOUTPOS_VALID;
1589                 }
1590                 if (crtc == 3) {
1591                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1592                                      EVERGREEN_CRTC3_REGISTER_OFFSET);
1593                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1594                                           EVERGREEN_CRTC3_REGISTER_OFFSET);
1595                         ret |= DRM_SCANOUTPOS_VALID;
1596                 }
1597                 if (crtc == 4) {
1598                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1599                                      EVERGREEN_CRTC4_REGISTER_OFFSET);
1600                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1601                                           EVERGREEN_CRTC4_REGISTER_OFFSET);
1602                         ret |= DRM_SCANOUTPOS_VALID;
1603                 }
1604                 if (crtc == 5) {
1605                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1606                                      EVERGREEN_CRTC5_REGISTER_OFFSET);
1607                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1608                                           EVERGREEN_CRTC5_REGISTER_OFFSET);
1609                         ret |= DRM_SCANOUTPOS_VALID;
1610                 }
1611         } else if (ASIC_IS_AVIVO(rdev)) {
1612                 if (crtc == 0) {
1613                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1614                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1615                         ret |= DRM_SCANOUTPOS_VALID;
1616                 }
1617                 if (crtc == 1) {
1618                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1619                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1620                         ret |= DRM_SCANOUTPOS_VALID;
1621                 }
1622         } else {
1623                 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1624                 if (crtc == 0) {
1625                         /* Assume vbl_end == 0, get vbl_start from
1626                          * upper 16 bits.
1627                          */
1628                         vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1629                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1630                         /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1631                         position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1632                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
1633                         if (!(stat_crtc & 1))
1634                                 in_vbl = false;
1635
1636                         ret |= DRM_SCANOUTPOS_VALID;
1637                 }
1638                 if (crtc == 1) {
1639                         vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1640                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1641                         position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1642                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1643                         if (!(stat_crtc & 1))
1644                                 in_vbl = false;
1645
1646                         ret |= DRM_SCANOUTPOS_VALID;
1647                 }
1648         }
1649
1650         /* Decode into vertical and horizontal scanout position. */
1651         *vpos = position & 0x1fff;
1652         *hpos = (position >> 16) & 0x1fff;
1653
1654         /* Valid vblank area boundaries from gpu retrieved? */
1655         if (vbl > 0) {
1656                 /* Yes: Decode. */
1657                 ret |= DRM_SCANOUTPOS_ACCURATE;
1658                 vbl_start = vbl & 0x1fff;
1659                 vbl_end = (vbl >> 16) & 0x1fff;
1660         }
1661         else {
1662                 /* No: Fake something reasonable which gives at least ok results. */
1663                 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1664                 vbl_end = 0;
1665         }
1666
1667         /* Test scanout position against vblank region. */
1668         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1669                 in_vbl = false;
1670
1671         /* Check if inside vblank area and apply corrective offsets:
1672          * vpos will then be >=0 in video scanout area, but negative
1673          * within vblank area, counting down the number of lines until
1674          * start of scanout.
1675          */
1676
1677         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1678         if (in_vbl && (*vpos >= vbl_start)) {
1679                 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1680                 *vpos = *vpos - vtotal;
1681         }
1682
1683         /* Correct for shifted end of vbl at vbl_end. */
1684         *vpos = *vpos - vbl_end;
1685
1686         /* In vblank? */
1687         if (in_vbl)
1688                 ret |= DRM_SCANOUTPOS_INVBL;
1689
1690         return ret;
1691 }