sys/dev/drm/radeon/radeon_legacy_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  *
  26  * $FreeBSD: head/sys/dev/drm2/radeon/radeon_legacy_crtc.c 254885 2013-08-25 19:37:15Z dumbbell $
  27  */
  28
  29 #include <drm/drmP.h>
  30 #include <drm/drm_crtc_helper.h>
  31 #include <uapi_drm/radeon_drm.h>
  32 #include <drm/drm_fixed.h>
  33 #include "radeon.h"
  34 #include "atom.h"
  35
  36 static void radeon_overscan_setup(struct drm_crtc *crtc,
  37                                   struct drm_display_mode *mode)
  38 {
  39         struct drm_device *dev = crtc->dev;
  40         struct radeon_device *rdev = dev->dev_private;
  41         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  42
  43         WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);
  44         WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);
  45         WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);
  46 }
  47
  48 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
  49                                        struct drm_display_mode *mode)
  50 {
  51         struct drm_device *dev = crtc->dev;
  52         struct radeon_device *rdev = dev->dev_private;
  53         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  54         int xres = mode->hdisplay;
  55         int yres = mode->vdisplay;
  56         bool hscale = true, vscale = true;
  57         int hsync_wid;
  58         int vsync_wid;
  59         int hsync_start;
  60         int blank_width;
  61         u32 scale, inc, crtc_more_cntl;
  62         u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
  63         u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
  64         u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
  65         struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
  66
  67         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
  68                 (RADEON_VERT_STRETCH_RESERVED |
  69                  RADEON_VERT_AUTO_RATIO_INC);
  70         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
  71                 (RADEON_HORZ_FP_LOOP_STRETCH |
  72                  RADEON_HORZ_AUTO_RATIO_INC);
  73
  74         crtc_more_cntl = 0;
  75         if ((rdev->family == CHIP_RS100) ||
  76             (rdev->family == CHIP_RS200)) {
  77                 /* This is to workaround the asic bug for RMX, some versions
  78                    of BIOS dosen't have this register initialized correctly. */
  79                 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
  80         }
  81
  82
  83         fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
  84                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
  85
  86         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
  87         if (!hsync_wid)
  88                 hsync_wid = 1;
  89         hsync_start = mode->crtc_hsync_start - 8;
  90
  91         fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
  92                               | ((hsync_wid & 0x3f) << 16)
  93                               | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
  94                                  ? RADEON_CRTC_H_SYNC_POL
  95                                  : 0));
  96
  97         fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
  98                                 | ((mode->crtc_vdisplay - 1) << 16));
  99
 100         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 101         if (!vsync_wid)
 102                 vsync_wid = 1;
 103
 104         fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
 105                               | ((vsync_wid & 0x1f) << 16)
 106                               | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 107                                  ? RADEON_CRTC_V_SYNC_POL
 108                                  : 0));
 109
 110         fp_horz_vert_active = 0;
 111
 112         if (native_mode->hdisplay == 0 ||
 113             native_mode->vdisplay == 0) {
 114                 hscale = false;
 115                 vscale = false;
 116         } else {
 117                 if (xres > native_mode->hdisplay)
 118                         xres = native_mode->hdisplay;
 119                 if (yres > native_mode->vdisplay)
 120                         yres = native_mode->vdisplay;
 121
 122                 if (xres == native_mode->hdisplay)
 123                         hscale = false;
 124                 if (yres == native_mode->vdisplay)
 125                         vscale = false;
 126         }
 127
 128         switch (radeon_crtc->rmx_type) {
 129         case RMX_FULL:
 130         case RMX_ASPECT:
 131                 if (!hscale)
 132                         fp_horz_stretch |= ((xres/8-1) << 16);
 133                 else {
 134                         inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
 135                         scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
 136                                 / native_mode->hdisplay + 1;
 137                         fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
 138                                         RADEON_HORZ_STRETCH_BLEND |
 139                                         RADEON_HORZ_STRETCH_ENABLE |
 140                                         ((native_mode->hdisplay/8-1) << 16));
 141                 }
 142
 143                 if (!vscale)
 144                         fp_vert_stretch |= ((yres-1) << 12);
 145                 else {
 146                         inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
 147                         scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
 148                                 / native_mode->vdisplay + 1;
 149                         fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
 150                                         RADEON_VERT_STRETCH_ENABLE |
 151                                         RADEON_VERT_STRETCH_BLEND |
 152                                         ((native_mode->vdisplay-1) << 12));
 153                 }
 154                 break;
 155         case RMX_CENTER:
 156                 fp_horz_stretch |= ((xres/8-1) << 16);
 157                 fp_vert_stretch |= ((yres-1) << 12);
 158
 159                 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
 160                                 RADEON_CRTC_AUTO_VERT_CENTER_EN);
 161
 162                 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
 163                 if (blank_width > 110)
 164                         blank_width = 110;
 165
 166                 fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
 167                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 168
 169                 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 170                 if (!hsync_wid)
 171                         hsync_wid = 1;
 172
 173                 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
 174                                 | ((hsync_wid & 0x3f) << 16)
 175                                 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 176                                         ? RADEON_CRTC_H_SYNC_POL
 177                                         : 0));
 178
 179                 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
 180                                 | ((mode->crtc_vdisplay - 1) << 16));
 181
 182                 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 183                 if (!vsync_wid)
 184                         vsync_wid = 1;
 185
 186                 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
 187                                         | ((vsync_wid & 0x1f) << 16)
 188                                         | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 189                                                 ? RADEON_CRTC_V_SYNC_POL
 190                                                 : 0)));
 191
 192                 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) |
 193                                 (((native_mode->hdisplay / 8) & 0x1ff) << 16));
 194                 break;
 195         case RMX_OFF:
 196         default:
 197                 fp_horz_stretch |= ((xres/8-1) << 16);
 198                 fp_vert_stretch |= ((yres-1) << 12);
 199                 break;
 200         }
 201
 202         WREG32(RADEON_FP_HORZ_STRETCH,      fp_horz_stretch);
 203         WREG32(RADEON_FP_VERT_STRETCH,      fp_vert_stretch);
 204         WREG32(RADEON_CRTC_MORE_CNTL,       crtc_more_cntl);
 205         WREG32(RADEON_FP_HORZ_VERT_ACTIVE,  fp_horz_vert_active);
 206         WREG32(RADEON_FP_H_SYNC_STRT_WID,   fp_h_sync_strt_wid);
 207         WREG32(RADEON_FP_V_SYNC_STRT_WID,   fp_v_sync_strt_wid);
 208         WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
 209         WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
 210 }
 211
 212 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
 213 {
 214         struct radeon_device *rdev = dev->dev_private;
 215         int i = 0;
 216
 217         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
 218            the cause yet, but this workaround will mask the problem for now.
 219            Other chips usually will pass at the very first test, so the
 220            workaround shouldn't have any effect on them. */
 221         for (i = 0;
 222              (i < 10000 &&
 223               RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
 224              i++);
 225 }
 226
 227 static void radeon_pll_write_update(struct drm_device *dev)
 228 {
 229         struct radeon_device *rdev = dev->dev_private;
 230
 231         while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
 232
 233         WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 234                            RADEON_PPLL_ATOMIC_UPDATE_W,
 235                            ~(RADEON_PPLL_ATOMIC_UPDATE_W));
 236 }
 237
 238 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
 239 {
 240         struct radeon_device *rdev = dev->dev_private;
 241         int i = 0;
 242
 243
 244         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
 245            the cause yet, but this workaround will mask the problem for now.
 246            Other chips usually will pass at the very first test, so the
 247            workaround shouldn't have any effect on them. */
 248         for (i = 0;
 249              (i < 10000 &&
 250               RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
 251              i++);
 252 }
 253
 254 static void radeon_pll2_write_update(struct drm_device *dev)
 255 {
 256         struct radeon_device *rdev = dev->dev_private;
 257
 258         while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
 259
 260         WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
 261                            RADEON_P2PLL_ATOMIC_UPDATE_W,
 262                            ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
 263 }
 264
 265 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
 266                                        uint16_t fb_div)
 267 {
 268         unsigned int vcoFreq;
 269
 270         if (!ref_div)
 271                 return 1;
 272
 273         vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div;
 274
 275         /*
 276          * This is horribly crude: the VCO frequency range is divided into
 277          * 3 parts, each part having a fixed PLL gain value.
 278          */
 279         if (vcoFreq >= 30000)
 280                 /*
 281                  * [300..max] MHz : 7
 282                  */
 283                 return 7;
 284         else if (vcoFreq >= 18000)
 285                 /*
 286                  * [180..300) MHz : 4
 287                  */
 288                 return 4;
 289         else
 290                 /*
 291                  * [0..180) MHz : 1
 292                  */
 293                 return 1;
 294 }
 295
 296 static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
 297 {
 298         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 299         struct drm_device *dev = crtc->dev;
 300         struct radeon_device *rdev = dev->dev_private;
 301         uint32_t crtc_ext_cntl = 0;
 302         uint32_t mask;
 303
 304         if (radeon_crtc->crtc_id)
 305                 mask = (RADEON_CRTC2_DISP_DIS |
 306                         RADEON_CRTC2_VSYNC_DIS |
 307                         RADEON_CRTC2_HSYNC_DIS |
 308                         RADEON_CRTC2_DISP_REQ_EN_B);
 309         else
 310                 mask = (RADEON_CRTC_DISPLAY_DIS |
 311                         RADEON_CRTC_VSYNC_DIS |
 312                         RADEON_CRTC_HSYNC_DIS);
 313
 314         /*
 315          * On all dual CRTC GPUs this bit controls the CRTC of the primary DAC.
 316          * Therefore it is set in the DAC DMPS function.
 317          * This is different for GPU's with a single CRTC but a primary and a
 318          * TV DAC: here it controls the single CRTC no matter where it is
 319          * routed. Therefore we set it here.
 320          */
 321         if (rdev->flags & RADEON_SINGLE_CRTC)
 322                 crtc_ext_cntl = RADEON_CRTC_CRT_ON;
 323
 324         switch (mode) {
 325         case DRM_MODE_DPMS_ON:
 326                 radeon_crtc->enabled = true;
 327                 /* adjust pm to dpms changes BEFORE enabling crtcs */
 328                 radeon_pm_compute_clocks(rdev);
 329                 if (radeon_crtc->crtc_id)
 330                         WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
 331                 else {
 332                         WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
 333                                                                          RADEON_CRTC_DISP_REQ_EN_B));
 334                         WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl));
 335                 }
 336                 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
 337                 radeon_crtc_load_lut(crtc);
 338                 break;
 339         case DRM_MODE_DPMS_STANDBY:
 340         case DRM_MODE_DPMS_SUSPEND:
 341         case DRM_MODE_DPMS_OFF:
 342                 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
 343                 if (radeon_crtc->crtc_id)
 344                         WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
 345                 else {
 346                         WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
 347                                                                                     RADEON_CRTC_DISP_REQ_EN_B));
 348                         WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl));
 349                 }
 350                 radeon_crtc->enabled = false;
 351                 /* adjust pm to dpms changes AFTER disabling crtcs */
 352                 radeon_pm_compute_clocks(rdev);
 353                 break;
 354         }
 355 }
 356
 357 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 358                          struct drm_framebuffer *old_fb)
 359 {
 360         return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
 361 }
 362
 363 int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
 364                                 struct drm_framebuffer *fb,
 365                                 int x, int y, enum mode_set_atomic state)
 366 {
 367         return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
 368 }
 369
 370 int radeon_crtc_do_set_base(struct drm_crtc *crtc,
 371                          struct drm_framebuffer *fb,
 372                          int x, int y, int atomic)
 373 {
 374         struct drm_device *dev = crtc->dev;
 375         struct radeon_device *rdev = dev->dev_private;
 376         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 377         struct radeon_framebuffer *radeon_fb;
 378         struct drm_framebuffer *target_fb;
 379         struct drm_gem_object *obj;
 380         struct radeon_bo *rbo;
 381         uint64_t base;
 382         uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
 383         uint32_t crtc_pitch, pitch_pixels;
 384         uint32_t tiling_flags;
 385         int format;
 386         uint32_t gen_cntl_reg, gen_cntl_val;
 387         int r;
 388
 389         DRM_DEBUG_KMS("\n");
 390         /* no fb bound */
 391         if (!atomic && !crtc->fb) {
 392                 DRM_DEBUG_KMS("No FB bound\n");
 393                 return 0;
 394         }
 395
 396         if (atomic) {
 397                 radeon_fb = to_radeon_framebuffer(fb);
 398                 target_fb = fb;
 399         }
 400         else {
 401                 radeon_fb = to_radeon_framebuffer(crtc->fb);
 402                 target_fb = crtc->fb;
 403         }
 404
 405         switch (target_fb->bits_per_pixel) {
 406         case 8:
 407                 format = 2;
 408                 break;
 409         case 15:      /*  555 */
 410                 format = 3;
 411                 break;
 412         case 16:      /*  565 */
 413                 format = 4;
 414                 break;
 415         case 24:      /*  RGB */
 416                 format = 5;
 417                 break;
 418         case 32:      /* xRGB */
 419                 format = 6;
 420                 break;
 421         default:
 422                 return false;
 423         }
 424
 425         /* Pin framebuffer & get tilling informations */
 426         obj = radeon_fb->obj;
 427         rbo = gem_to_radeon_bo(obj);
 428         r = radeon_bo_reserve(rbo, false);
 429         if (unlikely(r != 0))
 430                 return r;
 431         /* Only 27 bit offset for legacy CRTC */
 432         r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 1 << 27,
 433                                      &base);
 434         if (unlikely(r != 0)) {
 435                 radeon_bo_unreserve(rbo);
 436                 return -EINVAL;
 437         }
 438         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 439         radeon_bo_unreserve(rbo);
 440         if (tiling_flags & RADEON_TILING_MICRO)
 441                 DRM_ERROR("trying to scanout microtiled buffer\n");
 442
 443         /* if scanout was in GTT this really wouldn't work */
 444         /* crtc offset is from display base addr not FB location */
 445         radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start;
 446
 447         base -= radeon_crtc->legacy_display_base_addr;
 448
 449         crtc_offset_cntl = 0;
 450
 451         pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
 452         crtc_pitch  = (((pitch_pixels * target_fb->bits_per_pixel) +
 453                         ((target_fb->bits_per_pixel * 8) - 1)) /
 454                        (target_fb->bits_per_pixel * 8));
 455         crtc_pitch |= crtc_pitch << 16;
 456
 457         crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;
 458         if (tiling_flags & RADEON_TILING_MACRO) {
 459                 if (ASIC_IS_R300(rdev))
 460                         crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
 461                                              R300_CRTC_MICRO_TILE_BUFFER_DIS |
 462                                              R300_CRTC_MACRO_TILE_EN);
 463                 else
 464                         crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
 465         } else {
 466                 if (ASIC_IS_R300(rdev))
 467                         crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
 468                                               R300_CRTC_MICRO_TILE_BUFFER_DIS |
 469                                               R300_CRTC_MACRO_TILE_EN);
 470                 else
 471                         crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
 472         }
 473
 474         if (tiling_flags & RADEON_TILING_MACRO) {
 475                 if (ASIC_IS_R300(rdev)) {
 476                         crtc_tile_x0_y0 = x | (y << 16);
 477                         base &= ~0x7ff;
 478                 } else {
 479                         int byteshift = target_fb->bits_per_pixel >> 4;
 480                         int tile_addr = (((y >> 3) * pitch_pixels +  x) >> (8 - byteshift)) << 11;
 481                         base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
 482                         crtc_offset_cntl |= (y % 16);
 483                 }
 484         } else {
 485                 int offset = y * pitch_pixels + x;
 486                 switch (target_fb->bits_per_pixel) {
 487                 case 8:
 488                         offset *= 1;
 489                         break;
 490                 case 15:
 491                 case 16:
 492                         offset *= 2;
 493                         break;
 494                 case 24:
 495                         offset *= 3;
 496                         break;
 497                 case 32:
 498                         offset *= 4;
 499                         break;
 500                 default:
 501                         return false;
 502                 }
 503                 base += offset;
 504         }
 505
 506         base &= ~7;
 507
 508         if (radeon_crtc->crtc_id == 1)
 509                 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
 510         else
 511                 gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
 512
 513         gen_cntl_val = RREG32(gen_cntl_reg);
 514         gen_cntl_val &= ~(0xf << 8);
 515         gen_cntl_val |= (format << 8);
 516         gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK;
 517         WREG32(gen_cntl_reg, gen_cntl_val);
 518
 519         crtc_offset = (u32)base;
 520
 521         WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
 522
 523         if (ASIC_IS_R300(rdev)) {
 524                 if (radeon_crtc->crtc_id)
 525                         WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
 526                 else
 527                         WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
 528         }
 529         WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
 530         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
 531         WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
 532
 533         if (!atomic && fb && fb != crtc->fb) {
 534                 radeon_fb = to_radeon_framebuffer(fb);
 535                 rbo = gem_to_radeon_bo(radeon_fb->obj);
 536                 r = radeon_bo_reserve(rbo, false);
 537                 if (unlikely(r != 0))
 538                         return r;
 539                 radeon_bo_unpin(rbo);
 540                 radeon_bo_unreserve(rbo);
 541         }
 542
 543         /* Bytes per pixel may have changed */
 544         radeon_bandwidth_update(rdev);
 545
 546         return 0;
 547 }
 548
 549 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
 550 {
 551         struct drm_device *dev = crtc->dev;
 552         struct radeon_device *rdev = dev->dev_private;
 553         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 554         struct drm_encoder *encoder;
 555         int format;
 556         int hsync_start;
 557         int hsync_wid;
 558         int vsync_wid;
 559         uint32_t crtc_h_total_disp;
 560         uint32_t crtc_h_sync_strt_wid;
 561         uint32_t crtc_v_total_disp;
 562         uint32_t crtc_v_sync_strt_wid;
 563         bool is_tv = false;
 564
 565         DRM_DEBUG_KMS("\n");
 566         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 567                 if (encoder->crtc == crtc) {
 568                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 569                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 570                                 is_tv = true;
 571                                 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
 572                                 break;
 573                         }
 574                 }
 575         }
 576
 577         switch (crtc->fb->bits_per_pixel) {
 578         case 8:
 579                 format = 2;
 580                 break;
 581         case 15:      /*  555 */
 582                 format = 3;
 583                 break;
 584         case 16:      /*  565 */
 585                 format = 4;
 586                 break;
 587         case 24:      /*  RGB */
 588                 format = 5;
 589                 break;
 590         case 32:      /* xRGB */
 591                 format = 6;
 592                 break;
 593         default:
 594                 return false;
 595         }
 596
 597         crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
 598                              | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 599
 600         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 601         if (!hsync_wid)
 602                 hsync_wid = 1;
 603         hsync_start = mode->crtc_hsync_start - 8;
 604
 605         crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
 606                                 | ((hsync_wid & 0x3f) << 16)
 607                                 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 608                                    ? RADEON_CRTC_H_SYNC_POL
 609                                    : 0));
 610
 611         /* This works for double scan mode. */
 612         crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
 613                              | ((mode->crtc_vdisplay - 1) << 16));
 614
 615         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 616         if (!vsync_wid)
 617                 vsync_wid = 1;
 618
 619         crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
 620                                 | ((vsync_wid & 0x1f) << 16)
 621                                 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 622                                    ? RADEON_CRTC_V_SYNC_POL
 623                                    : 0));
 624
 625         if (radeon_crtc->crtc_id) {
 626                 uint32_t crtc2_gen_cntl;
 627                 uint32_t disp2_merge_cntl;
 628
 629                 /* if TV DAC is enabled for another crtc and keep it enabled */
 630                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080;
 631                 crtc2_gen_cntl |= ((format << 8)
 632                                    | RADEON_CRTC2_VSYNC_DIS
 633                                    | RADEON_CRTC2_HSYNC_DIS
 634                                    | RADEON_CRTC2_DISP_DIS
 635                                    | RADEON_CRTC2_DISP_REQ_EN_B
 636                                    | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 637                                       ? RADEON_CRTC2_DBL_SCAN_EN
 638                                       : 0)
 639                                    | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 640                                       ? RADEON_CRTC2_CSYNC_EN
 641                                       : 0)
 642                                    | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 643                                       ? RADEON_CRTC2_INTERLACE_EN
 644                                       : 0));
 645
 646                 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
 647                 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
 648                         crtc2_gen_cntl |= RADEON_CRTC2_EN;
 649
 650                 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
 651                 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
 652
 653                 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
 654                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 655
 656                 WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
 657                 WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
 658         } else {
 659                 uint32_t crtc_gen_cntl;
 660                 uint32_t crtc_ext_cntl;
 661                 uint32_t disp_merge_cntl;
 662
 663                 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000;
 664                 crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN
 665                                  | (format << 8)
 666                                  | RADEON_CRTC_DISP_REQ_EN_B
 667                                  | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 668                                     ? RADEON_CRTC_DBL_SCAN_EN
 669                                     : 0)
 670                                  | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 671                                     ? RADEON_CRTC_CSYNC_EN
 672                                     : 0)
 673                                  | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 674                                     ? RADEON_CRTC_INTERLACE_EN
 675                                     : 0));
 676
 677                 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
 678                 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
 679                         crtc_gen_cntl |= RADEON_CRTC_EN;
 680
 681                 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 682                 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
 683                                   RADEON_CRTC_VSYNC_DIS |
 684                                   RADEON_CRTC_HSYNC_DIS |
 685                                   RADEON_CRTC_DISPLAY_DIS);
 686
 687                 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
 688                 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
 689
 690                 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
 691                 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 692                 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 693         }
 694
 695         if (is_tv)
 696                 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
 697                                                  &crtc_h_sync_strt_wid, &crtc_v_total_disp,
 698                                                  &crtc_v_sync_strt_wid);
 699
 700         WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
 701         WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
 702         WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
 703         WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
 704
 705         return true;
 706 }
 707
 708 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 709 {
 710         struct drm_device *dev = crtc->dev;
 711         struct radeon_device *rdev = dev->dev_private;
 712         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 713         struct drm_encoder *encoder;
 714         uint32_t feedback_div = 0;
 715         uint32_t frac_fb_div = 0;
 716         uint32_t reference_div = 0;
 717         uint32_t post_divider = 0;
 718         uint32_t freq = 0;
 719         uint8_t pll_gain;
 720         bool use_bios_divs = false;
 721         /* PLL registers */
 722         uint32_t pll_ref_div = 0;
 723         uint32_t pll_fb_post_div = 0;
 724         uint32_t htotal_cntl = 0;
 725         bool is_tv = false;
 726         struct radeon_pll *pll;
 727
 728         struct {
 729                 int divider;
 730                 int bitvalue;
 731         } *post_div, post_divs[]   = {
 732                 /* From RAGE 128 VR/RAGE 128 GL Register
 733                  * Reference Manual (Technical Reference
 734                  * Manual P/N RRG-G04100-C Rev. 0.04), page
 735                  * 3-17 (PLL_DIV_[3:0]).
 736                  */
 737                 {  1, 0 },              /* VCLK_SRC                 */
 738                 {  2, 1 },              /* VCLK_SRC/2               */
 739                 {  4, 2 },              /* VCLK_SRC/4               */
 740                 {  8, 3 },              /* VCLK_SRC/8               */
 741                 {  3, 4 },              /* VCLK_SRC/3               */
 742                 { 16, 5 },              /* VCLK_SRC/16              */
 743                 {  6, 6 },              /* VCLK_SRC/6               */
 744                 { 12, 7 },              /* VCLK_SRC/12              */
 745                 {  0, 0 }
 746         };
 747
 748         if (radeon_crtc->crtc_id)
 749                 pll = &rdev->clock.p2pll;
 750         else
 751                 pll = &rdev->clock.p1pll;
 752
 753         pll->flags = RADEON_PLL_LEGACY;
 754
 755         if (mode->clock > 200000) /* range limits??? */
 756                 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 757         else
 758                 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 759
 760         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 761                 if (encoder->crtc == crtc) {
 762                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 763
 764                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 765                                 is_tv = true;
 766                                 break;
 767                         }
 768
 769                         if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 770                                 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
 771                         if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
 772                                 if (!rdev->is_atom_bios) {
 773                                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 774                                         struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
 775                                         if (lvds) {
 776                                                 if (lvds->use_bios_dividers) {
 777                                                         pll_ref_div = lvds->panel_ref_divider;
 778                                                         pll_fb_post_div   = (lvds->panel_fb_divider |
 779                                                                              (lvds->panel_post_divider << 16));
 780                                                         htotal_cntl  = 0;
 781                                                         use_bios_divs = true;
 782                                                 }
 783                                         }
 784                                 }
 785                                 pll->flags |= RADEON_PLL_USE_REF_DIV;
 786                         }
 787                 }
 788         }
 789
 790         DRM_DEBUG_KMS("\n");
 791
 792         if (!use_bios_divs) {
 793                 radeon_compute_pll_legacy(pll, mode->clock,
 794                                           &freq, &feedback_div, &frac_fb_div,
 795                                           &reference_div, &post_divider);
 796
 797                 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
 798                         if (post_div->divider == post_divider)
 799                                 break;
 800                 }
 801
 802                 if (!post_div->divider)
 803                         post_div = &post_divs[0];
 804
 805                 DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n",
 806                           (unsigned)freq,
 807                           feedback_div,
 808                           reference_div,
 809                           post_divider);
 810
 811                 pll_ref_div   = reference_div;
 812 #if defined(__powerpc__) && (0) /* TODO */
 813                 /* apparently programming this otherwise causes a hang??? */
 814                 if (info->MacModel == RADEON_MAC_IBOOK)
 815                         pll_fb_post_div = 0x000600ad;
 816                 else
 817 #endif
 818                         pll_fb_post_div     = (feedback_div | (post_div->bitvalue << 16));
 819
 820                 htotal_cntl    = mode->htotal & 0x7;
 821
 822         }
 823
 824         pll_gain = radeon_compute_pll_gain(pll->reference_freq,
 825                                            pll_ref_div & 0x3ff,
 826                                            pll_fb_post_div & 0x7ff);
 827
 828         if (radeon_crtc->crtc_id) {
 829                 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
 830                                           ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
 831                                          RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
 832
 833                 if (is_tv) {
 834                         radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
 835                                                      &pll_ref_div, &pll_fb_post_div,
 836                                                      &pixclks_cntl);
 837                 }
 838
 839                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
 840                              RADEON_PIX2CLK_SRC_SEL_CPUCLK,
 841                              ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 842
 843                 WREG32_PLL_P(RADEON_P2PLL_CNTL,
 844                              RADEON_P2PLL_RESET
 845                              | RADEON_P2PLL_ATOMIC_UPDATE_EN
 846                              | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
 847                              ~(RADEON_P2PLL_RESET
 848                                | RADEON_P2PLL_ATOMIC_UPDATE_EN
 849                                | RADEON_P2PLL_PVG_MASK));
 850
 851                 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
 852                              pll_ref_div,
 853                              ~RADEON_P2PLL_REF_DIV_MASK);
 854
 855                 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
 856                              pll_fb_post_div,
 857                              ~RADEON_P2PLL_FB0_DIV_MASK);
 858
 859                 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
 860                              pll_fb_post_div,
 861                              ~RADEON_P2PLL_POST0_DIV_MASK);
 862
 863                 radeon_pll2_write_update(dev);
 864                 radeon_pll2_wait_for_read_update_complete(dev);
 865
 866                 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
 867
 868                 WREG32_PLL_P(RADEON_P2PLL_CNTL,
 869                              0,
 870                              ~(RADEON_P2PLL_RESET
 871                                | RADEON_P2PLL_SLEEP
 872                                | RADEON_P2PLL_ATOMIC_UPDATE_EN));
 873
 874                 DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
 875                           (unsigned)pll_ref_div,
 876                           (unsigned)pll_fb_post_div,
 877                           (unsigned)htotal_cntl,
 878                           RREG32_PLL(RADEON_P2PLL_CNTL));
 879                 DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n",
 880                           (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
 881                           (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
 882                           (unsigned)((pll_fb_post_div &
 883                                       RADEON_P2PLL_POST0_DIV_MASK) >> 16));
 884
 885                 DRM_MDELAY(50); /* Let the clock to lock */
 886
 887                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
 888                              RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
 889                              ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 890
 891                 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
 892         } else {
 893                 uint32_t pixclks_cntl;
 894
 895
 896                 if (is_tv) {
 897                         pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
 898                         radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
 899                                                      &pll_fb_post_div, &pixclks_cntl);
 900                 }
 901
 902                 if (rdev->flags & RADEON_IS_MOBILITY) {
 903                         /* A temporal workaround for the occasional blanking on certain laptop panels.
 904                            This appears to related to the PLL divider registers (fail to lock?).
 905                            It occurs even when all dividers are the same with their old settings.
 906                            In this case we really don't need to fiddle with PLL registers.
 907                            By doing this we can avoid the blanking problem with some panels.
 908                         */
 909                         if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
 910                             (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
 911                                                  (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
 912                                 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
 913                                          RADEON_PLL_DIV_SEL,
 914                                          ~(RADEON_PLL_DIV_SEL));
 915                                 r100_pll_errata_after_index(rdev);
 916                                 return;
 917                         }
 918                 }
 919
 920                 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
 921                              RADEON_VCLK_SRC_SEL_CPUCLK,
 922                              ~(RADEON_VCLK_SRC_SEL_MASK));
 923                 WREG32_PLL_P(RADEON_PPLL_CNTL,
 924                              RADEON_PPLL_RESET
 925                              | RADEON_PPLL_ATOMIC_UPDATE_EN
 926                              | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 927                              | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
 928                              ~(RADEON_PPLL_RESET
 929                                | RADEON_PPLL_ATOMIC_UPDATE_EN
 930                                | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 931                                | RADEON_PPLL_PVG_MASK));
 932
 933                 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
 934                          RADEON_PLL_DIV_SEL,
 935                          ~(RADEON_PLL_DIV_SEL));
 936                 r100_pll_errata_after_index(rdev);
 937
 938                 if (ASIC_IS_R300(rdev) ||
 939                     (rdev->family == CHIP_RS300) ||
 940                     (rdev->family == CHIP_RS400) ||
 941                     (rdev->family == CHIP_RS480)) {
 942                         if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
 943                                 /* When restoring console mode, use saved PPLL_REF_DIV
 944                                  * setting.
 945                                  */
 946                                 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 947                                              pll_ref_div,
 948                                              0);
 949                         } else {
 950                                 /* R300 uses ref_div_acc field as real ref divider */
 951                                 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 952                                              (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
 953                                              ~R300_PPLL_REF_DIV_ACC_MASK);
 954                         }
 955                 } else
 956                         WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 957                                      pll_ref_div,
 958                                      ~RADEON_PPLL_REF_DIV_MASK);
 959
 960                 WREG32_PLL_P(RADEON_PPLL_DIV_3,
 961                              pll_fb_post_div,
 962                              ~RADEON_PPLL_FB3_DIV_MASK);
 963
 964                 WREG32_PLL_P(RADEON_PPLL_DIV_3,
 965                              pll_fb_post_div,
 966                              ~RADEON_PPLL_POST3_DIV_MASK);
 967
 968                 radeon_pll_write_update(dev);
 969                 radeon_pll_wait_for_read_update_complete(dev);
 970
 971                 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
 972
 973                 WREG32_PLL_P(RADEON_PPLL_CNTL,
 974                              0,
 975                              ~(RADEON_PPLL_RESET
 976                                | RADEON_PPLL_SLEEP
 977                                | RADEON_PPLL_ATOMIC_UPDATE_EN
 978                                | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
 979
 980                 DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
 981                           pll_ref_div,
 982                           pll_fb_post_div,
 983                           (unsigned)htotal_cntl,
 984                           RREG32_PLL(RADEON_PPLL_CNTL));
 985                 DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n",
 986                           pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
 987                           pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
 988                           (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
 989
 990                 DRM_MDELAY(50); /* Let the clock to lock */
 991
 992                 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
 993                              RADEON_VCLK_SRC_SEL_PPLLCLK,
 994                              ~(RADEON_VCLK_SRC_SEL_MASK));
 995
 996                 if (is_tv)
 997                         WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
 998         }
 999 }
1000
1001 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
1002                                    const struct drm_display_mode *mode,
1003                                    struct drm_display_mode *adjusted_mode)
1004 {
1005         if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1006                 return false;
1007         return true;
1008 }
1009
1010 static int radeon_crtc_mode_set(struct drm_crtc *crtc,
1011                                  struct drm_display_mode *mode,
1012                                  struct drm_display_mode *adjusted_mode,
1013                                  int x, int y, struct drm_framebuffer *old_fb)
1014 {
1015         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1016
1017         /* TODO TV */
1018         radeon_crtc_set_base(crtc, x, y, old_fb);
1019         radeon_set_crtc_timing(crtc, adjusted_mode);
1020         radeon_set_pll(crtc, adjusted_mode);
1021         radeon_overscan_setup(crtc, adjusted_mode);
1022         if (radeon_crtc->crtc_id == 0) {
1023                 radeon_legacy_rmx_mode_set(crtc, adjusted_mode);
1024         } else {
1025                 if (radeon_crtc->rmx_type != RMX_OFF) {
1026                         /* FIXME: only first crtc has rmx what should we
1027                          * do ?
1028                          */
1029                         DRM_ERROR("Mode need scaling but only first crtc can do that.\n");
1030                 }
1031         }
1032         return 0;
1033 }
1034
1035 static void radeon_crtc_prepare(struct drm_crtc *crtc)
1036 {
1037         struct drm_device *dev = crtc->dev;
1038         struct drm_crtc *crtci;
1039
1040         /*
1041         * The hardware wedges sometimes if you reconfigure one CRTC
1042         * whilst another is running (see fdo bug #24611).
1043         */
1044         list_for_each_entry(crtci, &dev->mode_config.crtc_list, head)
1045                 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF);
1046 }
1047
1048 static void radeon_crtc_commit(struct drm_crtc *crtc)
1049 {
1050         struct drm_device *dev = crtc->dev;
1051         struct drm_crtc *crtci;
1052
1053         /*
1054         * Reenable the CRTCs that should be running.
1055         */
1056         list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) {
1057                 if (crtci->enabled)
1058                         radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON);
1059         }
1060 }
1061
1062 static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1063         .dpms = radeon_crtc_dpms,
1064         .mode_fixup = radeon_crtc_mode_fixup,
1065         .mode_set = radeon_crtc_mode_set,
1066         .mode_set_base = radeon_crtc_set_base,
1067         .mode_set_base_atomic = radeon_crtc_set_base_atomic,
1068         .prepare = radeon_crtc_prepare,
1069         .commit = radeon_crtc_commit,
1070         .load_lut = radeon_crtc_load_lut,
1071 };
1072
1073
1074 void radeon_legacy_init_crtc(struct drm_device *dev,
1075                                struct radeon_crtc *radeon_crtc)
1076 {
1077         if (radeon_crtc->crtc_id == 1)
1078                 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
1079         drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
1080 }