sys/dev/drm/radeon/radeon_uvd.c

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Christian König <deathsimple@vodafone.de>
  29  */
  30
  31 #include <linux/module.h>
  32 #include <drm/drmP.h>
  33
  34 #include "radeon.h"
  35 #include "r600d.h"
  36
  37 /* 1 second timeout */
  38 #define UVD_IDLE_TIMEOUT_MS     1000
  39
  40 /* Firmware Names */
  41 #define FIRMWARE_RV710          "radeonkmsfw_RV710_uvd"
  42 #define FIRMWARE_CYPRESS        "radeonkmsfw_CYPRESS_uvd"
  43 #define FIRMWARE_SUMO           "radeonkmsfw_SUMO_uvd"
  44 #define FIRMWARE_TAHITI         "radeonkmsfw_TAHITI_uvd"
  45
  46 #if 0
  47 MODULE_FIRMWARE(FIRMWARE_RV710);
  48 MODULE_FIRMWARE(FIRMWARE_CYPRESS);
  49 MODULE_FIRMWARE(FIRMWARE_SUMO);
  50 MODULE_FIRMWARE(FIRMWARE_TAHITI);
  51 #endif
  52
  53 static void radeon_uvd_idle_work_handler(struct work_struct *work);
  54
  55 int radeon_uvd_init(struct radeon_device *rdev)
  56 {
  57         unsigned long bo_size;
  58         const char *fw_name;
  59         int i, r;
  60
  61         INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler);
  62
  63         switch (rdev->family) {
  64         case CHIP_RV710:
  65         case CHIP_RV730:
  66         case CHIP_RV740:
  67                 fw_name = FIRMWARE_RV710;
  68                 break;
  69
  70         case CHIP_CYPRESS:
  71         case CHIP_HEMLOCK:
  72         case CHIP_JUNIPER:
  73         case CHIP_REDWOOD:
  74         case CHIP_CEDAR:
  75                 fw_name = FIRMWARE_CYPRESS;
  76                 break;
  77
  78         case CHIP_SUMO:
  79         case CHIP_SUMO2:
  80         case CHIP_PALM:
  81         case CHIP_CAYMAN:
  82         case CHIP_BARTS:
  83         case CHIP_TURKS:
  84         case CHIP_CAICOS:
  85                 fw_name = FIRMWARE_SUMO;
  86                 break;
  87
  88         case CHIP_TAHITI:
  89         case CHIP_VERDE:
  90         case CHIP_PITCAIRN:
  91         case CHIP_ARUBA:
  92                 fw_name = FIRMWARE_TAHITI;
  93                 break;
  94
  95         default:
  96                 return -EINVAL;
  97         }
  98
  99         rdev->uvd_fw = firmware_get(fw_name);
 100         if (!rdev->uvd_fw) {
 101                 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n",
 102                         fw_name);
 103                 return -EINVAL;
 104         }
 105
 106         bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->datasize + 8) +
 107                   RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE;
 108         r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true,
 109                              RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->uvd.vcpu_bo);
 110         if (r) {
 111                 dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r);
 112                 return r;
 113         }
 114
 115         r = radeon_uvd_resume(rdev);
 116         if (r)
 117                 return r;
 118
 119         memset(rdev->uvd.cpu_addr, 0, bo_size);
 120         memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->datasize);
 121
 122         r = radeon_uvd_suspend(rdev);
 123         if (r)
 124                 return r;
 125
 126         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 127                 atomic_set(&rdev->uvd.handles[i], 0);
 128                 rdev->uvd.filp[i] = NULL;
 129         }
 130
 131         return 0;
 132 }
 133
 134 void radeon_uvd_fini(struct radeon_device *rdev)
 135 {
 136         radeon_uvd_suspend(rdev);
 137         radeon_bo_unref(&rdev->uvd.vcpu_bo);
 138 }
 139
 140 int radeon_uvd_suspend(struct radeon_device *rdev)
 141 {
 142         int r;
 143
 144         if (rdev->uvd.vcpu_bo == NULL)
 145                 return 0;
 146
 147         r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
 148         if (!r) {
 149                 radeon_bo_kunmap(rdev->uvd.vcpu_bo);
 150                 radeon_bo_unpin(rdev->uvd.vcpu_bo);
 151                 rdev->uvd.cpu_addr = NULL;
 152                 if (!radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_CPU, NULL)) {
 153                         radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr);
 154                 }
 155                 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 156
 157                 if (rdev->uvd.cpu_addr) {
 158                         radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX);
 159                 } else {
 160                         rdev->fence_drv[R600_RING_TYPE_UVD_INDEX].cpu_addr = NULL;
 161                 }
 162         }
 163         return r;
 164 }
 165
 166 int radeon_uvd_resume(struct radeon_device *rdev)
 167 {
 168         int r;
 169
 170         if (rdev->uvd.vcpu_bo == NULL)
 171                 return -EINVAL;
 172
 173         r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
 174         if (r) {
 175                 radeon_bo_unref(&rdev->uvd.vcpu_bo);
 176                 dev_err(rdev->dev, "(%d) failed to reserve UVD bo\n", r);
 177                 return r;
 178         }
 179
 180         /* Have been pin in cpu unmap unpin */
 181         radeon_bo_kunmap(rdev->uvd.vcpu_bo);
 182         radeon_bo_unpin(rdev->uvd.vcpu_bo);
 183
 184         r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM,
 185                           &rdev->uvd.gpu_addr);
 186         if (r) {
 187                 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 188                 radeon_bo_unref(&rdev->uvd.vcpu_bo);
 189                 dev_err(rdev->dev, "(%d) UVD bo pin failed\n", r);
 190                 return r;
 191         }
 192
 193         r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr);
 194         if (r) {
 195                 dev_err(rdev->dev, "(%d) UVD map failed\n", r);
 196                 return r;
 197         }
 198
 199         radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 200
 201         return 0;
 202 }
 203
 204 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo)
 205 {
 206         rbo->placement.fpfn = 0 >> PAGE_SHIFT;
 207         rbo->placement.lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
 208 }
 209
 210 void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file *filp)
 211 {
 212         int i, r;
 213         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 214                 if (rdev->uvd.filp[i] == filp) {
 215                         uint32_t handle = atomic_read(&rdev->uvd.handles[i]);
 216                         struct radeon_fence *fence;
 217
 218                         r = radeon_uvd_get_destroy_msg(rdev,
 219                                 R600_RING_TYPE_UVD_INDEX, handle, &fence);
 220                         if (r) {
 221                                 DRM_ERROR("Error destroying UVD (%d)!\n", r);
 222                                 continue;
 223                         }
 224
 225                         radeon_fence_wait(fence, false);
 226                         radeon_fence_unref(&fence);
 227
 228                         rdev->uvd.filp[i] = NULL;
 229                         atomic_set(&rdev->uvd.handles[i], 0);
 230                 }
 231         }
 232 }
 233
 234 static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
 235 {
 236         unsigned stream_type = msg[4];
 237         unsigned width = msg[6];
 238         unsigned height = msg[7];
 239         unsigned dpb_size = msg[9];
 240         unsigned pitch = msg[28];
 241
 242         unsigned width_in_mb = width / 16;
 243         unsigned height_in_mb = ALIGN(height / 16, 2);
 244
 245         unsigned image_size, tmp, min_dpb_size;
 246
 247         image_size = width * height;
 248         image_size += image_size / 2;
 249         image_size = ALIGN(image_size, 1024);
 250
 251         switch (stream_type) {
 252         case 0: /* H264 */
 253
 254                 /* reference picture buffer */
 255                 min_dpb_size = image_size * 17;
 256
 257                 /* macroblock context buffer */
 258                 min_dpb_size += width_in_mb * height_in_mb * 17 * 192;
 259
 260                 /* IT surface buffer */
 261                 min_dpb_size += width_in_mb * height_in_mb * 32;
 262                 break;
 263
 264         case 1: /* VC1 */
 265
 266                 /* reference picture buffer */
 267                 min_dpb_size = image_size * 3;
 268
 269                 /* CONTEXT_BUFFER */
 270                 min_dpb_size += width_in_mb * height_in_mb * 128;
 271
 272                 /* IT surface buffer */
 273                 min_dpb_size += width_in_mb * 64;
 274
 275                 /* DB surface buffer */
 276                 min_dpb_size += width_in_mb * 128;
 277
 278                 /* BP */
 279                 tmp = max(width_in_mb, height_in_mb);
 280                 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
 281                 break;
 282
 283         case 3: /* MPEG2 */
 284
 285                 /* reference picture buffer */
 286                 min_dpb_size = image_size * 3;
 287                 break;
 288
 289         case 4: /* MPEG4 */
 290
 291                 /* reference picture buffer */
 292                 min_dpb_size = image_size * 3;
 293
 294                 /* CM */
 295                 min_dpb_size += width_in_mb * height_in_mb * 64;
 296
 297                 /* IT surface buffer */
 298                 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
 299                 break;
 300
 301         default:
 302                 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
 303                 return -EINVAL;
 304         }
 305
 306         if (width > pitch) {
 307                 DRM_ERROR("Invalid UVD decoding target pitch!\n");
 308                 return -EINVAL;
 309         }
 310
 311         if (dpb_size < min_dpb_size) {
 312                 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
 313                           dpb_size, min_dpb_size);
 314                 return -EINVAL;
 315         }
 316
 317         buf_sizes[0x1] = dpb_size;
 318         buf_sizes[0x2] = image_size;
 319         return 0;
 320 }
 321
 322 static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo,
 323                              unsigned offset, unsigned buf_sizes[])
 324 {
 325         int32_t *msg, msg_type, handle;
 326         void *ptr;
 327
 328         int i, r;
 329
 330         if (offset & 0x3F) {
 331                 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
 332                 return -EINVAL;
 333         }
 334
 335         r = radeon_bo_kmap(bo, &ptr);
 336         if (r)
 337                 return r;
 338
 339         msg = (uint32_t*)((uint8_t*)ptr + offset);
 340
 341         msg_type = msg[1];
 342         handle = msg[2];
 343
 344         if (handle == 0) {
 345                 DRM_ERROR("Invalid UVD handle!\n");
 346                 return -EINVAL;
 347         }
 348
 349         if (msg_type == 1) {
 350                 /* it's a decode msg, calc buffer sizes */
 351                 r = radeon_uvd_cs_msg_decode(msg, buf_sizes);
 352                 radeon_bo_kunmap(bo);
 353                 if (r)
 354                         return r;
 355
 356         } else if (msg_type == 2) {
 357                 /* it's a destroy msg, free the handle */
 358                 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
 359                         atomic_cmpset(&p->rdev->uvd.handles[i], handle, 0);
 360                 radeon_bo_kunmap(bo);
 361                 return 0;
 362         } else {
 363                 /* it's a create msg, no special handling needed */
 364                 radeon_bo_kunmap(bo);
 365         }
 366
 367         /* create or decode, validate the handle */
 368         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 369                 if (atomic_read(&p->rdev->uvd.handles[i]) == handle)
 370                         return 0;
 371         }
 372
 373         /* handle not found try to alloc a new one */
 374         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 375 #if 0
 376                 if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) {
 377 #endif
 378                 if (atomic_cmpset(&p->rdev->uvd.handles[i], 0, handle) == 1) {
 379                         p->rdev->uvd.filp[i] = p->filp;
 380                         return 0;
 381                 }
 382         }
 383
 384         DRM_ERROR("No more free UVD handles!\n");
 385         return -EINVAL;
 386 }
 387
 388 static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
 389                                int data0, int data1,
 390                                unsigned buf_sizes[])
 391 {
 392         struct radeon_cs_chunk *relocs_chunk;
 393         struct radeon_cs_reloc *reloc;
 394         unsigned idx, cmd, offset;
 395         uint64_t start, end;
 396         int r;
 397
 398         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
 399         offset = radeon_get_ib_value(p, data0);
 400         idx = radeon_get_ib_value(p, data1);
 401         if (idx >= relocs_chunk->length_dw) {
 402                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
 403                           idx, relocs_chunk->length_dw);
 404                 return -EINVAL;
 405         }
 406
 407         reloc = p->relocs_ptr[(idx / 4)];
 408         start = reloc->lobj.gpu_offset;
 409         end = start + radeon_bo_size(reloc->robj);
 410         start += offset;
 411
 412         p->ib.ptr[data0] = start & 0xFFFFFFFF;
 413         p->ib.ptr[data1] = start >> 32;
 414
 415         cmd = radeon_get_ib_value(p, p->idx) >> 1;
 416
 417         if (cmd < 0x4) {
 418                 if ((end - start) < buf_sizes[cmd]) {
 419                         DRM_ERROR("buffer to small (%d / %d)!\n",
 420                                   (unsigned)(end - start), buf_sizes[cmd]);
 421                         return -EINVAL;
 422                 }
 423
 424         } else if (cmd != 0x100) {
 425                 DRM_ERROR("invalid UVD command %X!\n", cmd);
 426                 return -EINVAL;
 427         }
 428
 429         if ((start >> 28) != (end >> 28)) {
 430                 DRM_ERROR("reloc %lX-%lX crossing 256MB boundary!\n",
 431                           start, end);
 432                 return -EINVAL;
 433         }
 434
 435         /* TODO: is this still necessary on NI+ ? */
 436         if ((cmd == 0 || cmd == 0x3) &&
 437             (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
 438                 DRM_ERROR("msg/fb buffer %lX-%lX out of 256MB segment!\n",
 439                           start, end);
 440                 return -EINVAL;
 441         }
 442
 443         if (cmd == 0) {
 444                 r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes);
 445                 if (r)
 446                         return r;
 447         }
 448
 449         return 0;
 450 }
 451
 452 static int radeon_uvd_cs_reg(struct radeon_cs_parser *p,
 453                              struct radeon_cs_packet *pkt,
 454                              int *data0, int *data1,
 455                              unsigned buf_sizes[])
 456 {
 457         int i, r;
 458
 459         p->idx++;
 460         for (i = 0; i <= pkt->count; ++i) {
 461                 switch (pkt->reg + i*4) {
 462                 case UVD_GPCOM_VCPU_DATA0:
 463                         *data0 = p->idx;
 464                         break;
 465                 case UVD_GPCOM_VCPU_DATA1:
 466                         *data1 = p->idx;
 467                         break;
 468                 case UVD_GPCOM_VCPU_CMD:
 469                         r = radeon_uvd_cs_reloc(p, *data0, *data1, buf_sizes);
 470                         if (r)
 471                                 return r;
 472                         break;
 473                 case UVD_ENGINE_CNTL:
 474                         break;
 475                 default:
 476                         DRM_ERROR("Invalid reg 0x%X!\n",
 477                                   pkt->reg + i*4);
 478                         return -EINVAL;
 479                 }
 480                 p->idx++;
 481         }
 482         return 0;
 483 }
 484
 485 int radeon_uvd_cs_parse(struct radeon_cs_parser *p)
 486 {
 487         struct radeon_cs_packet pkt;
 488         int r, data0 = 0, data1 = 0;
 489
 490         /* minimum buffer sizes */
 491         unsigned buf_sizes[] = {
 492                 [0x00000000]    =       2048,
 493                 [0x00000001]    =       32 * 1024 * 1024,
 494                 [0x00000002]    =       2048 * 1152 * 3,
 495                 [0x00000003]    =       2048,
 496         };
 497
 498         if (p->chunks[p->chunk_ib_idx].length_dw % 16) {
 499                 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
 500                           p->chunks[p->chunk_ib_idx].length_dw);
 501                 return -EINVAL;
 502         }
 503
 504         if (p->chunk_relocs_idx == -1) {
 505                 DRM_ERROR("No relocation chunk !\n");
 506                 return -EINVAL;
 507         }
 508
 509
 510         do {
 511                 r = radeon_cs_packet_parse(p, &pkt, p->idx);
 512                 if (r)
 513                         return r;
 514                 switch (pkt.type) {
 515                 case RADEON_PACKET_TYPE0:
 516                         r = radeon_uvd_cs_reg(p, &pkt, &data0,
 517                                               &data1, buf_sizes);
 518                         if (r)
 519                                 return r;
 520                         break;
 521                 case RADEON_PACKET_TYPE2:
 522                         p->idx += pkt.count + 2;
 523                         break;
 524                 default:
 525                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
 526                         return -EINVAL;
 527                 }
 528         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
 529         return 0;
 530 }
 531
 532 static int radeon_uvd_send_msg(struct radeon_device *rdev,
 533                                int ring, struct radeon_bo *bo,
 534                                struct radeon_fence **fence)
 535 {
 536         struct ttm_validate_buffer tv;
 537         struct list_head head;
 538         struct radeon_ib ib;
 539         uint64_t addr;
 540         int i, r;
 541
 542         memset(&tv, 0, sizeof(tv));
 543         tv.bo = &bo->tbo;
 544
 545         INIT_LIST_HEAD(&head);
 546         list_add(&tv.head, &head);
 547
 548         r = ttm_eu_reserve_buffers(&head);
 549         if (r)
 550                 return r;
 551
 552         radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_VRAM);
 553         radeon_uvd_force_into_uvd_segment(bo);
 554
 555         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 556         if (r) {
 557                 ttm_eu_backoff_reservation(&head);
 558                 return r;
 559         }
 560
 561         r = radeon_ib_get(rdev, ring, &ib, NULL, 16);
 562         if (r) {
 563                 ttm_eu_backoff_reservation(&head);
 564                 return r;
 565         }
 566
 567         addr = radeon_bo_gpu_offset(bo);
 568         ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0);
 569         ib.ptr[1] = addr;
 570         ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0);
 571         ib.ptr[3] = addr >> 32;
 572         ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0);
 573         ib.ptr[5] = 0;
 574         for (i = 6; i < 16; ++i)
 575                 ib.ptr[i] = PACKET2(0);
 576         ib.length_dw = 16;
 577
 578         r = radeon_ib_schedule(rdev, &ib, NULL);
 579         if (r) {
 580                 ttm_eu_backoff_reservation(&head);
 581                 return r;
 582         }
 583         ttm_eu_fence_buffer_objects(&head, ib.fence);
 584
 585         if (fence)
 586                 *fence = radeon_fence_ref(ib.fence);
 587
 588         radeon_ib_free(rdev, &ib);
 589         radeon_bo_unref(&bo);
 590         return 0;
 591 }
 592
 593 /* multiple fence commands without any stream commands in between can
 594    crash the vcpu so just try to emmit a dummy create/destroy msg to
 595    avoid this */
 596 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
 597                               uint32_t handle, struct radeon_fence **fence)
 598 {
 599         struct radeon_bo *bo;
 600         uint32_t *msg;
 601         int r, i;
 602
 603         r = radeon_bo_create(rdev, 1024, PAGE_SIZE, true,
 604                              RADEON_GEM_DOMAIN_VRAM, NULL, &bo);
 605         if (r)
 606                 return r;
 607
 608         r = radeon_bo_reserve(bo, false);
 609         if (r) {
 610                 radeon_bo_unref(&bo);
 611                 return r;
 612         }
 613
 614         r = radeon_bo_kmap(bo, (void **)&msg);
 615         if (r) {
 616                 radeon_bo_unreserve(bo);
 617                 radeon_bo_unref(&bo);
 618                 return r;
 619         }
 620
 621         /* stitch together an UVD create msg */
 622         msg[0] = cpu_to_le32(0x00000de4);
 623         msg[1] = cpu_to_le32(0x00000000);
 624         msg[2] = cpu_to_le32(handle);
 625         msg[3] = cpu_to_le32(0x00000000);
 626         msg[4] = cpu_to_le32(0x00000000);
 627         msg[5] = cpu_to_le32(0x00000000);
 628         msg[6] = cpu_to_le32(0x00000000);
 629         msg[7] = cpu_to_le32(0x00000780);
 630         msg[8] = cpu_to_le32(0x00000440);
 631         msg[9] = cpu_to_le32(0x00000000);
 632         msg[10] = cpu_to_le32(0x01b37000);
 633         for (i = 11; i < 1024; ++i)
 634                 msg[i] = cpu_to_le32(0x0);
 635
 636         radeon_bo_kunmap(bo);
 637         radeon_bo_unreserve(bo);
 638
 639         return radeon_uvd_send_msg(rdev, ring, bo, fence);
 640 }
 641
 642 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
 643                                uint32_t handle, struct radeon_fence **fence)
 644 {
 645         struct radeon_bo *bo;
 646         uint32_t *msg;
 647         int r, i;
 648
 649         r = radeon_bo_create(rdev, 1024, PAGE_SIZE, true,
 650                              RADEON_GEM_DOMAIN_VRAM, NULL, &bo);
 651         if (r)
 652                 return r;
 653
 654         r = radeon_bo_reserve(bo, false);
 655         if (r) {
 656                 radeon_bo_unref(&bo);
 657                 return r;
 658         }
 659
 660         r = radeon_bo_kmap(bo, (void **)&msg);
 661         if (r) {
 662                 radeon_bo_unreserve(bo);
 663                 radeon_bo_unref(&bo);
 664                 return r;
 665         }
 666
 667         /* stitch together an UVD destroy msg */
 668         msg[0] = cpu_to_le32(0x00000de4);
 669         msg[1] = cpu_to_le32(0x00000002);
 670         msg[2] = cpu_to_le32(handle);
 671         msg[3] = cpu_to_le32(0x00000000);
 672         for (i = 4; i < 1024; ++i)
 673                 msg[i] = cpu_to_le32(0x0);
 674
 675         radeon_bo_kunmap(bo);
 676         radeon_bo_unreserve(bo);
 677
 678         return radeon_uvd_send_msg(rdev, ring, bo, fence);
 679 }
 680
 681 static void radeon_uvd_idle_work_handler(struct work_struct *work)
 682 {
 683         struct radeon_device *rdev =
 684                 container_of(work, struct radeon_device, uvd.idle_work.work);
 685
 686         if (radeon_fence_count_emitted(rdev, R600_RING_TYPE_UVD_INDEX) == 0)
 687                 radeon_set_uvd_clocks(rdev, 0, 0);
 688         else
 689                 schedule_delayed_work(&rdev->uvd.idle_work,
 690                                       msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
 691 }
 692
 693 void radeon_uvd_note_usage(struct radeon_device *rdev)
 694 {
 695         bool set_clocks = !cancel_delayed_work_sync(&rdev->uvd.idle_work);
 696         set_clocks &= schedule_delayed_work(&rdev->uvd.idle_work,
 697                                             msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
 698         if (set_clocks)
 699                 radeon_set_uvd_clocks(rdev, 53300, 40000);
 700 }
 701
 702 static unsigned radeon_uvd_calc_upll_post_div(unsigned vco_freq,
 703                                               unsigned target_freq,
 704                                               unsigned pd_min,
 705                                               unsigned pd_even)
 706 {
 707         unsigned post_div = vco_freq / target_freq;
 708
 709         /* adjust to post divider minimum value */
 710         if (post_div < pd_min)
 711                 post_div = pd_min;
 712
 713         /* we alway need a frequency less than or equal the target */
 714         if ((vco_freq / post_div) > target_freq)
 715                 post_div += 1;
 716
 717         /* post dividers above a certain value must be even */
 718         if (post_div > pd_even && post_div % 2)
 719                 post_div += 1;
 720
 721         return post_div;
 722 }
 723
 724 /**
 725  * radeon_uvd_calc_upll_dividers - calc UPLL clock dividers
 726  *
 727  * @rdev: radeon_device pointer
 728  * @vclk: wanted VCLK
 729  * @dclk: wanted DCLK
 730  * @vco_min: minimum VCO frequency
 731  * @vco_max: maximum VCO frequency
 732  * @fb_factor: factor to multiply vco freq with
 733  * @fb_mask: limit and bitmask for feedback divider
 734  * @pd_min: post divider minimum
 735  * @pd_max: post divider maximum
 736  * @pd_even: post divider must be even above this value
 737  * @optimal_fb_div: resulting feedback divider
 738  * @optimal_vclk_div: resulting vclk post divider
 739  * @optimal_dclk_div: resulting dclk post divider
 740  *
 741  * Calculate dividers for UVDs UPLL (R6xx-SI, except APUs).
 742  * Returns zero on success -EINVAL on error.
 743  */
 744 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
 745                                   unsigned vclk, unsigned dclk,
 746                                   unsigned vco_min, unsigned vco_max,
 747                                   unsigned fb_factor, unsigned fb_mask,
 748                                   unsigned pd_min, unsigned pd_max,
 749                                   unsigned pd_even,
 750                                   unsigned *optimal_fb_div,
 751                                   unsigned *optimal_vclk_div,
 752                                   unsigned *optimal_dclk_div)
 753 {
 754         unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq;
 755
 756         /* start off with something large */
 757         unsigned optimal_score = ~0;
 758
 759         /* loop through vco from low to high */
 760         vco_min = max(max(vco_min, vclk), dclk);
 761         for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) {
 762
 763                 uint64_t fb_div = (uint64_t)vco_freq * fb_factor;
 764                 unsigned vclk_div, dclk_div, score;
 765
 766                 do_div(fb_div, ref_freq);
 767
 768                 /* fb div out of range ? */
 769                 if (fb_div > fb_mask)
 770                         break; /* it can oly get worse */
 771
 772                 fb_div &= fb_mask;
 773
 774                 /* calc vclk divider with current vco freq */
 775                 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk,
 776                                                          pd_min, pd_even);
 777                 if (vclk_div > pd_max)
 778                         break; /* vco is too big, it has to stop */
 779
 780                 /* calc dclk divider with current vco freq */
 781                 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk,
 782                                                          pd_min, pd_even);
 783                 if (vclk_div > pd_max)
 784                         break; /* vco is too big, it has to stop */
 785
 786                 /* calc score with current vco freq */
 787                 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
 788
 789                 /* determine if this vco setting is better than current optimal settings */
 790                 if (score < optimal_score) {
 791                         *optimal_fb_div = fb_div;
 792                         *optimal_vclk_div = vclk_div;
 793                         *optimal_dclk_div = dclk_div;
 794                         optimal_score = score;
 795                         if (optimal_score == 0)
 796                                 break; /* it can't get better than this */
 797                 }
 798         }
 799
 800         /* did we found a valid setup ? */
 801         if (optimal_score == ~0)
 802                 return -EINVAL;
 803
 804         return 0;
 805 }
 806
 807 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
 808                                 unsigned cg_upll_func_cntl)
 809 {
 810         unsigned i;
 811
 812         /* make sure UPLL_CTLREQ is deasserted */
 813         WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
 814
 815         DRM_MDELAY(10);
 816
 817         /* assert UPLL_CTLREQ */
 818         WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
 819
 820         /* wait for CTLACK and CTLACK2 to get asserted */
 821         for (i = 0; i < 100; ++i) {
 822                 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
 823                 if ((RREG32(cg_upll_func_cntl) & mask) == mask)
 824                         break;
 825                 DRM_MDELAY(10);
 826         }
 827
 828         /* deassert UPLL_CTLREQ */
 829         WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
 830
 831         if (i == 100) {
 832                 DRM_ERROR("Timeout setting UVD clocks!\n");
 833                 return -ETIMEDOUT;
 834         }
 835
 836         return 0;
 837 }